2 * Low-Level PCI Access for i386 machines.
4 * (c) 1999 Martin Mares <mj@ucw.cz>
10 #define DBG(x...) printk(x)
15 #define PCI_PROBE_BIOS 0x0001
16 #define PCI_PROBE_CONF1 0x0002
17 #define PCI_PROBE_CONF2 0x0004
18 #define PCI_PROBE_MMCONF 0x0008
19 #define PCI_PROBE_MASK 0x000f
20 #define PCI_PROBE_NOEARLY 0x0010
22 #define PCI_NO_SORT 0x0100
23 #define PCI_BIOS_SORT 0x0200
24 #define PCI_NO_CHECKS 0x0400
25 #define PCI_USE_PIRQ_MASK 0x0800
26 #define PCI_ASSIGN_ROMS 0x1000
27 #define PCI_BIOS_IRQ_SCAN 0x2000
28 #define PCI_ASSIGN_ALL_BUSSES 0x4000
29 #define PCI_CAN_SKIP_ISA_ALIGN 0x8000
31 extern unsigned int pci_probe;
32 extern unsigned long pirq_table_addr;
34 enum pci_bf_sort_state {
43 extern unsigned int pcibios_max_latency;
45 void pcibios_resource_survey(void);
46 int pcibios_enable_resources(struct pci_dev *, int);
50 extern int pcibios_last_bus;
51 extern struct pci_bus *pci_root_bus;
52 extern struct pci_ops pci_root_ops;
57 u8 bus, devfn; /* Bus, device and function */
59 u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
60 u16 bitmap; /* Available IRQs */
61 } __attribute__((packed)) irq[4];
62 u8 slot; /* Slot number, 0=onboard */
64 } __attribute__((packed));
66 struct irq_routing_table {
67 u32 signature; /* PIRQ_SIGNATURE should be here */
68 u16 version; /* PIRQ_VERSION */
69 u16 size; /* Table size in bytes */
70 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
71 u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
72 u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
73 u32 miniport_data; /* Crap */
75 u8 checksum; /* Modulo 256 checksum must give zero */
76 struct irq_info slots[0];
77 } __attribute__((packed));
79 extern unsigned int pcibios_irq_mask;
81 extern int pcibios_scanned;
82 extern spinlock_t pci_config_lock;
84 extern int (*pcibios_enable_irq)(struct pci_dev *dev);
85 extern void (*pcibios_disable_irq)(struct pci_dev *dev);
87 extern int pci_conf1_write(unsigned int seg, unsigned int bus,
88 unsigned int devfn, int reg, int len, u32 value);
89 extern int pci_conf1_read(unsigned int seg, unsigned int bus,
90 unsigned int devfn, int reg, int len, u32 *value);
92 extern int pci_direct_probe(void);
93 extern void pci_direct_init(int type);
94 extern void pci_pcbios_init(void);
95 extern void pci_mmcfg_init(int type);
96 extern void pcibios_sort(void);
100 /* Verify the first 16 busses. We assume that systems with more busses
102 #define PCI_MMCFG_MAX_CHECK_BUS 16
103 extern DECLARE_BITMAP(pci_mmcfg_fallback_slots, 32*PCI_MMCFG_MAX_CHECK_BUS);
105 extern int __init pci_mmcfg_arch_reachable(unsigned int seg, unsigned int bus,
107 extern int __init pci_mmcfg_arch_init(void);
110 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
111 * on their northbrige except through the * %eax register. As such, you MUST
112 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
113 * accessor functions.
114 * In fact just use pci_config_*, nothing else please.
116 static inline unsigned char mmio_config_readb(void __iomem *pos)
119 asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
123 static inline unsigned short mmio_config_readw(void __iomem *pos)
126 asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
130 static inline unsigned int mmio_config_readl(void __iomem *pos)
133 asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
137 static inline void mmio_config_writeb(void __iomem *pos, u8 val)
139 asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
142 static inline void mmio_config_writew(void __iomem *pos, u16 val)
144 asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
147 static inline void mmio_config_writel(void __iomem *pos, u32 val)
149 asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");