Merge commit 'v2.6.34-rc7' into oprofile
[sfrench/cifs-2.6.git] / arch / x86 / oprofile / nmi_int.c
1 /**
2  * @file nmi_int.c
3  *
4  * @remark Copyright 2002-2009 OProfile authors
5  * @remark Read the file COPYING
6  *
7  * @author John Levon <levon@movementarian.org>
8  * @author Robert Richter <robert.richter@amd.com>
9  * @author Barry Kasindorf <barry.kasindorf@amd.com>
10  * @author Jason Yeh <jason.yeh@amd.com>
11  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
12  */
13
14 #include <linux/init.h>
15 #include <linux/notifier.h>
16 #include <linux/smp.h>
17 #include <linux/oprofile.h>
18 #include <linux/sysdev.h>
19 #include <linux/slab.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kdebug.h>
22 #include <linux/cpu.h>
23 #include <asm/nmi.h>
24 #include <asm/msr.h>
25 #include <asm/apic.h>
26
27 #include "op_counter.h"
28 #include "op_x86_model.h"
29
30 static struct op_x86_model_spec *model;
31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
33
34 /* 0 == registered but off, 1 == registered and on */
35 static int nmi_enabled = 0;
36
37 struct op_counter_config counter_config[OP_MAX_COUNTER];
38
39 /* common functions */
40
41 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
42                     struct op_counter_config *counter_config)
43 {
44         u64 val = 0;
45         u16 event = (u16)counter_config->event;
46
47         val |= ARCH_PERFMON_EVENTSEL_INT;
48         val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
49         val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
50         val |= (counter_config->unit_mask & 0xFF) << 8;
51         event &= model->event_mask ? model->event_mask : 0xFF;
52         val |= event & 0xFF;
53         val |= (event & 0x0F00) << 24;
54
55         return val;
56 }
57
58
59 static int profile_exceptions_notify(struct notifier_block *self,
60                                      unsigned long val, void *data)
61 {
62         struct die_args *args = (struct die_args *)data;
63         int ret = NOTIFY_DONE;
64         int cpu = smp_processor_id();
65
66         switch (val) {
67         case DIE_NMI:
68         case DIE_NMI_IPI:
69                 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
70                 ret = NOTIFY_STOP;
71                 break;
72         default:
73                 break;
74         }
75         return ret;
76 }
77
78 static void nmi_cpu_save_registers(struct op_msrs *msrs)
79 {
80         struct op_msr *counters = msrs->counters;
81         struct op_msr *controls = msrs->controls;
82         unsigned int i;
83
84         for (i = 0; i < model->num_counters; ++i) {
85                 if (counters[i].addr)
86                         rdmsrl(counters[i].addr, counters[i].saved);
87         }
88
89         for (i = 0; i < model->num_controls; ++i) {
90                 if (controls[i].addr)
91                         rdmsrl(controls[i].addr, controls[i].saved);
92         }
93 }
94
95 static void nmi_cpu_start(void *dummy)
96 {
97         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
98         model->start(msrs);
99 }
100
101 static int nmi_start(void)
102 {
103         on_each_cpu(nmi_cpu_start, NULL, 1);
104         return 0;
105 }
106
107 static void nmi_cpu_stop(void *dummy)
108 {
109         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
110         model->stop(msrs);
111 }
112
113 static void nmi_stop(void)
114 {
115         on_each_cpu(nmi_cpu_stop, NULL, 1);
116 }
117
118 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
119
120 static DEFINE_PER_CPU(int, switch_index);
121
122 static inline int has_mux(void)
123 {
124         return !!model->switch_ctrl;
125 }
126
127 inline int op_x86_phys_to_virt(int phys)
128 {
129         return __get_cpu_var(switch_index) + phys;
130 }
131
132 inline int op_x86_virt_to_phys(int virt)
133 {
134         return virt % model->num_counters;
135 }
136
137 static void nmi_shutdown_mux(void)
138 {
139         int i;
140
141         if (!has_mux())
142                 return;
143
144         for_each_possible_cpu(i) {
145                 kfree(per_cpu(cpu_msrs, i).multiplex);
146                 per_cpu(cpu_msrs, i).multiplex = NULL;
147                 per_cpu(switch_index, i) = 0;
148         }
149 }
150
151 static int nmi_setup_mux(void)
152 {
153         size_t multiplex_size =
154                 sizeof(struct op_msr) * model->num_virt_counters;
155         int i;
156
157         if (!has_mux())
158                 return 1;
159
160         for_each_possible_cpu(i) {
161                 per_cpu(cpu_msrs, i).multiplex =
162                         kzalloc(multiplex_size, GFP_KERNEL);
163                 if (!per_cpu(cpu_msrs, i).multiplex)
164                         return 0;
165         }
166
167         return 1;
168 }
169
170 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
171 {
172         int i;
173         struct op_msr *multiplex = msrs->multiplex;
174
175         if (!has_mux())
176                 return;
177
178         for (i = 0; i < model->num_virt_counters; ++i) {
179                 if (counter_config[i].enabled) {
180                         multiplex[i].saved = -(u64)counter_config[i].count;
181                 } else {
182                         multiplex[i].saved = 0;
183                 }
184         }
185
186         per_cpu(switch_index, cpu) = 0;
187 }
188
189 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
190 {
191         struct op_msr *counters = msrs->counters;
192         struct op_msr *multiplex = msrs->multiplex;
193         int i;
194
195         for (i = 0; i < model->num_counters; ++i) {
196                 int virt = op_x86_phys_to_virt(i);
197                 if (counters[i].addr)
198                         rdmsrl(counters[i].addr, multiplex[virt].saved);
199         }
200 }
201
202 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
203 {
204         struct op_msr *counters = msrs->counters;
205         struct op_msr *multiplex = msrs->multiplex;
206         int i;
207
208         for (i = 0; i < model->num_counters; ++i) {
209                 int virt = op_x86_phys_to_virt(i);
210                 if (counters[i].addr)
211                         wrmsrl(counters[i].addr, multiplex[virt].saved);
212         }
213 }
214
215 static void nmi_cpu_switch(void *dummy)
216 {
217         int cpu = smp_processor_id();
218         int si = per_cpu(switch_index, cpu);
219         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
220
221         nmi_cpu_stop(NULL);
222         nmi_cpu_save_mpx_registers(msrs);
223
224         /* move to next set */
225         si += model->num_counters;
226         if ((si >= model->num_virt_counters) || (counter_config[si].count == 0))
227                 per_cpu(switch_index, cpu) = 0;
228         else
229                 per_cpu(switch_index, cpu) = si;
230
231         model->switch_ctrl(model, msrs);
232         nmi_cpu_restore_mpx_registers(msrs);
233
234         nmi_cpu_start(NULL);
235 }
236
237
238 /*
239  * Quick check to see if multiplexing is necessary.
240  * The check should be sufficient since counters are used
241  * in ordre.
242  */
243 static int nmi_multiplex_on(void)
244 {
245         return counter_config[model->num_counters].count ? 0 : -EINVAL;
246 }
247
248 static int nmi_switch_event(void)
249 {
250         if (!has_mux())
251                 return -ENOSYS;         /* not implemented */
252         if (nmi_multiplex_on() < 0)
253                 return -EINVAL;         /* not necessary */
254
255         on_each_cpu(nmi_cpu_switch, NULL, 1);
256
257         return 0;
258 }
259
260 static inline void mux_init(struct oprofile_operations *ops)
261 {
262         if (has_mux())
263                 ops->switch_events = nmi_switch_event;
264 }
265
266 static void mux_clone(int cpu)
267 {
268         if (!has_mux())
269                 return;
270
271         memcpy(per_cpu(cpu_msrs, cpu).multiplex,
272                per_cpu(cpu_msrs, 0).multiplex,
273                sizeof(struct op_msr) * model->num_virt_counters);
274 }
275
276 #else
277
278 inline int op_x86_phys_to_virt(int phys) { return phys; }
279 inline int op_x86_virt_to_phys(int virt) { return virt; }
280 static inline void nmi_shutdown_mux(void) { }
281 static inline int nmi_setup_mux(void) { return 1; }
282 static inline void
283 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
284 static inline void mux_init(struct oprofile_operations *ops) { }
285 static void mux_clone(int cpu) { }
286
287 #endif
288
289 static void free_msrs(void)
290 {
291         int i;
292         for_each_possible_cpu(i) {
293                 kfree(per_cpu(cpu_msrs, i).counters);
294                 per_cpu(cpu_msrs, i).counters = NULL;
295                 kfree(per_cpu(cpu_msrs, i).controls);
296                 per_cpu(cpu_msrs, i).controls = NULL;
297         }
298         nmi_shutdown_mux();
299 }
300
301 static int allocate_msrs(void)
302 {
303         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
304         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
305
306         int i;
307         for_each_possible_cpu(i) {
308                 per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
309                                                         GFP_KERNEL);
310                 if (!per_cpu(cpu_msrs, i).counters)
311                         goto fail;
312                 per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
313                                                         GFP_KERNEL);
314                 if (!per_cpu(cpu_msrs, i).controls)
315                         goto fail;
316         }
317
318         if (!nmi_setup_mux())
319                 goto fail;
320
321         return 1;
322
323 fail:
324         free_msrs();
325         return 0;
326 }
327
328 static void nmi_cpu_setup(void *dummy)
329 {
330         int cpu = smp_processor_id();
331         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
332         nmi_cpu_save_registers(msrs);
333         spin_lock(&oprofilefs_lock);
334         model->setup_ctrs(model, msrs);
335         nmi_cpu_setup_mux(cpu, msrs);
336         spin_unlock(&oprofilefs_lock);
337         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
338         apic_write(APIC_LVTPC, APIC_DM_NMI);
339 }
340
341 static struct notifier_block profile_exceptions_nb = {
342         .notifier_call = profile_exceptions_notify,
343         .next = NULL,
344         .priority = 2
345 };
346
347 static int nmi_setup(void)
348 {
349         int err = 0;
350         int cpu;
351
352         if (!allocate_msrs())
353                 return -ENOMEM;
354
355         /* We need to serialize save and setup for HT because the subset
356          * of msrs are distinct for save and setup operations
357          */
358
359         /* Assume saved/restored counters are the same on all CPUs */
360         err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
361         if (err)
362                 goto fail;
363
364         for_each_possible_cpu(cpu) {
365                 if (!cpu)
366                         continue;
367
368                 memcpy(per_cpu(cpu_msrs, cpu).counters,
369                        per_cpu(cpu_msrs, 0).counters,
370                        sizeof(struct op_msr) * model->num_counters);
371
372                 memcpy(per_cpu(cpu_msrs, cpu).controls,
373                        per_cpu(cpu_msrs, 0).controls,
374                        sizeof(struct op_msr) * model->num_controls);
375
376                 mux_clone(cpu);
377         }
378
379         err = register_die_notifier(&profile_exceptions_nb);
380         if (err)
381                 goto fail;
382
383         on_each_cpu(nmi_cpu_setup, NULL, 1);
384         nmi_enabled = 1;
385         return 0;
386 fail:
387         free_msrs();
388         return err;
389 }
390
391 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
392 {
393         struct op_msr *counters = msrs->counters;
394         struct op_msr *controls = msrs->controls;
395         unsigned int i;
396
397         for (i = 0; i < model->num_controls; ++i) {
398                 if (controls[i].addr)
399                         wrmsrl(controls[i].addr, controls[i].saved);
400         }
401
402         for (i = 0; i < model->num_counters; ++i) {
403                 if (counters[i].addr)
404                         wrmsrl(counters[i].addr, counters[i].saved);
405         }
406 }
407
408 static void nmi_cpu_shutdown(void *dummy)
409 {
410         unsigned int v;
411         int cpu = smp_processor_id();
412         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
413
414         /* restoring APIC_LVTPC can trigger an apic error because the delivery
415          * mode and vector nr combination can be illegal. That's by design: on
416          * power on apic lvt contain a zero vector nr which are legal only for
417          * NMI delivery mode. So inhibit apic err before restoring lvtpc
418          */
419         v = apic_read(APIC_LVTERR);
420         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
421         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
422         apic_write(APIC_LVTERR, v);
423         nmi_cpu_restore_registers(msrs);
424 }
425
426 static void nmi_shutdown(void)
427 {
428         struct op_msrs *msrs;
429
430         nmi_enabled = 0;
431         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
432         unregister_die_notifier(&profile_exceptions_nb);
433         msrs = &get_cpu_var(cpu_msrs);
434         model->shutdown(msrs);
435         free_msrs();
436         put_cpu_var(cpu_msrs);
437 }
438
439 static int nmi_create_files(struct super_block *sb, struct dentry *root)
440 {
441         unsigned int i;
442
443         for (i = 0; i < model->num_virt_counters; ++i) {
444                 struct dentry *dir;
445                 char buf[4];
446
447                 /* quick little hack to _not_ expose a counter if it is not
448                  * available for use.  This should protect userspace app.
449                  * NOTE:  assumes 1:1 mapping here (that counters are organized
450                  *        sequentially in their struct assignment).
451                  */
452                 if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i)))
453                         continue;
454
455                 snprintf(buf,  sizeof(buf), "%d", i);
456                 dir = oprofilefs_mkdir(sb, root, buf);
457                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
458                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
459                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
460                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
461                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
462                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
463         }
464
465         return 0;
466 }
467
468 #ifdef CONFIG_SMP
469 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
470                                  void *data)
471 {
472         int cpu = (unsigned long)data;
473         switch (action) {
474         case CPU_DOWN_FAILED:
475         case CPU_ONLINE:
476                 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
477                 break;
478         case CPU_DOWN_PREPARE:
479                 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
480                 break;
481         }
482         return NOTIFY_DONE;
483 }
484
485 static struct notifier_block oprofile_cpu_nb = {
486         .notifier_call = oprofile_cpu_notifier
487 };
488 #endif
489
490 #ifdef CONFIG_PM
491
492 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
493 {
494         /* Only one CPU left, just stop that one */
495         if (nmi_enabled == 1)
496                 nmi_cpu_stop(NULL);
497         return 0;
498 }
499
500 static int nmi_resume(struct sys_device *dev)
501 {
502         if (nmi_enabled == 1)
503                 nmi_cpu_start(NULL);
504         return 0;
505 }
506
507 static struct sysdev_class oprofile_sysclass = {
508         .name           = "oprofile",
509         .resume         = nmi_resume,
510         .suspend        = nmi_suspend,
511 };
512
513 static struct sys_device device_oprofile = {
514         .id     = 0,
515         .cls    = &oprofile_sysclass,
516 };
517
518 static int __init init_sysfs(void)
519 {
520         int error;
521
522         error = sysdev_class_register(&oprofile_sysclass);
523         if (!error)
524                 error = sysdev_register(&device_oprofile);
525         return error;
526 }
527
528 static void exit_sysfs(void)
529 {
530         sysdev_unregister(&device_oprofile);
531         sysdev_class_unregister(&oprofile_sysclass);
532 }
533
534 #else
535 #define init_sysfs() do { } while (0)
536 #define exit_sysfs() do { } while (0)
537 #endif /* CONFIG_PM */
538
539 static int __init p4_init(char **cpu_type)
540 {
541         __u8 cpu_model = boot_cpu_data.x86_model;
542
543         if (cpu_model > 6 || cpu_model == 5)
544                 return 0;
545
546 #ifndef CONFIG_SMP
547         *cpu_type = "i386/p4";
548         model = &op_p4_spec;
549         return 1;
550 #else
551         switch (smp_num_siblings) {
552         case 1:
553                 *cpu_type = "i386/p4";
554                 model = &op_p4_spec;
555                 return 1;
556
557         case 2:
558                 *cpu_type = "i386/p4-ht";
559                 model = &op_p4_ht2_spec;
560                 return 1;
561         }
562 #endif
563
564         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
565         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
566         return 0;
567 }
568
569 static int force_arch_perfmon;
570 static int force_cpu_type(const char *str, struct kernel_param *kp)
571 {
572         if (!strcmp(str, "arch_perfmon")) {
573                 force_arch_perfmon = 1;
574                 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
575         }
576
577         return 0;
578 }
579 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
580
581 static int __init ppro_init(char **cpu_type)
582 {
583         __u8 cpu_model = boot_cpu_data.x86_model;
584         struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
585
586         if (force_arch_perfmon && cpu_has_arch_perfmon)
587                 return 0;
588
589         switch (cpu_model) {
590         case 0 ... 2:
591                 *cpu_type = "i386/ppro";
592                 break;
593         case 3 ... 5:
594                 *cpu_type = "i386/pii";
595                 break;
596         case 6 ... 8:
597         case 10 ... 11:
598                 *cpu_type = "i386/piii";
599                 break;
600         case 9:
601         case 13:
602                 *cpu_type = "i386/p6_mobile";
603                 break;
604         case 14:
605                 *cpu_type = "i386/core";
606                 break;
607         case 15: case 23:
608                 *cpu_type = "i386/core_2";
609                 break;
610         case 0x2e:
611         case 26:
612                 spec = &op_arch_perfmon_spec;
613                 *cpu_type = "i386/core_i7";
614                 break;
615         case 28:
616                 *cpu_type = "i386/atom";
617                 break;
618         default:
619                 /* Unknown */
620                 return 0;
621         }
622
623         model = spec;
624         return 1;
625 }
626
627 /* in order to get sysfs right */
628 static int using_nmi;
629
630 int __init op_nmi_init(struct oprofile_operations *ops)
631 {
632         __u8 vendor = boot_cpu_data.x86_vendor;
633         __u8 family = boot_cpu_data.x86;
634         char *cpu_type = NULL;
635         int ret = 0;
636
637         if (!cpu_has_apic)
638                 return -ENODEV;
639
640         switch (vendor) {
641         case X86_VENDOR_AMD:
642                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
643
644                 switch (family) {
645                 case 6:
646                         cpu_type = "i386/athlon";
647                         break;
648                 case 0xf:
649                         /*
650                          * Actually it could be i386/hammer too, but
651                          * give user space an consistent name.
652                          */
653                         cpu_type = "x86-64/hammer";
654                         break;
655                 case 0x10:
656                         cpu_type = "x86-64/family10";
657                         break;
658                 case 0x11:
659                         cpu_type = "x86-64/family11h";
660                         break;
661                 default:
662                         return -ENODEV;
663                 }
664                 model = &op_amd_spec;
665                 break;
666
667         case X86_VENDOR_INTEL:
668                 switch (family) {
669                         /* Pentium IV */
670                 case 0xf:
671                         p4_init(&cpu_type);
672                         break;
673
674                         /* A P6-class processor */
675                 case 6:
676                         ppro_init(&cpu_type);
677                         break;
678
679                 default:
680                         break;
681                 }
682
683                 if (cpu_type)
684                         break;
685
686                 if (!cpu_has_arch_perfmon)
687                         return -ENODEV;
688
689                 /* use arch perfmon as fallback */
690                 cpu_type = "i386/arch_perfmon";
691                 model = &op_arch_perfmon_spec;
692                 break;
693
694         default:
695                 return -ENODEV;
696         }
697
698 #ifdef CONFIG_SMP
699         register_cpu_notifier(&oprofile_cpu_nb);
700 #endif
701         /* default values, can be overwritten by model */
702         ops->create_files       = nmi_create_files;
703         ops->setup              = nmi_setup;
704         ops->shutdown           = nmi_shutdown;
705         ops->start              = nmi_start;
706         ops->stop               = nmi_stop;
707         ops->cpu_type           = cpu_type;
708
709         if (model->init)
710                 ret = model->init(ops);
711         if (ret)
712                 return ret;
713
714         if (!model->num_virt_counters)
715                 model->num_virt_counters = model->num_counters;
716
717         mux_init(ops);
718
719         init_sysfs();
720         using_nmi = 1;
721         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
722         return 0;
723 }
724
725 void op_nmi_exit(void)
726 {
727         if (using_nmi) {
728                 exit_sysfs();
729 #ifdef CONFIG_SMP
730                 unregister_cpu_notifier(&oprofile_cpu_nb);
731 #endif
732         }
733         if (model->exit)
734                 model->exit();
735 }