Merge tag 'v4.1-rockchip-socfixes2' of git://git.kernel.org/pub/scm/linux/kernel...
[sfrench/cifs-2.6.git] / arch / x86 / kvm / x86.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * derived from drivers/kvm/kvm_main.c
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright (C) 2008 Qumranet, Inc.
8  * Copyright IBM Corporation, 2008
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Amit Shah    <amit.shah@qumranet.com>
15  *   Ben-Ami Yassour <benami@il.ibm.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31
32 #include <linux/clocksource.h>
33 #include <linux/interrupt.h>
34 #include <linux/kvm.h>
35 #include <linux/fs.h>
36 #include <linux/vmalloc.h>
37 #include <linux/module.h>
38 #include <linux/mman.h>
39 #include <linux/highmem.h>
40 #include <linux/iommu.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/cpufreq.h>
43 #include <linux/user-return-notifier.h>
44 #include <linux/srcu.h>
45 #include <linux/slab.h>
46 #include <linux/perf_event.h>
47 #include <linux/uaccess.h>
48 #include <linux/hash.h>
49 #include <linux/pci.h>
50 #include <linux/timekeeper_internal.h>
51 #include <linux/pvclock_gtod.h>
52 #include <trace/events/kvm.h>
53
54 #define CREATE_TRACE_POINTS
55 #include "trace.h"
56
57 #include <asm/debugreg.h>
58 #include <asm/msr.h>
59 #include <asm/desc.h>
60 #include <asm/mtrr.h>
61 #include <asm/mce.h>
62 #include <asm/i387.h>
63 #include <asm/fpu-internal.h> /* Ugh! */
64 #include <asm/xcr.h>
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67
68 #define MAX_IO_MSRS 256
69 #define KVM_MAX_MCE_BANKS 32
70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71
72 #define emul_to_vcpu(ctxt) \
73         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
75 /* EFER defaults:
76  * - enable syscall per default because its emulated by KVM
77  * - enable LME and LMA per default on 64 bit KVM
78  */
79 #ifdef CONFIG_X86_64
80 static
81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 #else
83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
84 #endif
85
86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88
89 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
90 static void process_nmi(struct kvm_vcpu *vcpu);
91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
92
93 struct kvm_x86_ops *kvm_x86_ops;
94 EXPORT_SYMBOL_GPL(kvm_x86_ops);
95
96 static bool ignore_msrs = 0;
97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
99 unsigned int min_timer_period_us = 500;
100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
102 bool kvm_has_tsc_control;
103 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
104 u32  kvm_max_guest_tsc_khz;
105 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106
107 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
108 static u32 tsc_tolerance_ppm = 250;
109 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110
111 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
112 unsigned int lapic_timer_advance_ns = 0;
113 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
114
115 static bool backwards_tsc_observed = false;
116
117 #define KVM_NR_SHARED_MSRS 16
118
119 struct kvm_shared_msrs_global {
120         int nr;
121         u32 msrs[KVM_NR_SHARED_MSRS];
122 };
123
124 struct kvm_shared_msrs {
125         struct user_return_notifier urn;
126         bool registered;
127         struct kvm_shared_msr_values {
128                 u64 host;
129                 u64 curr;
130         } values[KVM_NR_SHARED_MSRS];
131 };
132
133 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
134 static struct kvm_shared_msrs __percpu *shared_msrs;
135
136 struct kvm_stats_debugfs_item debugfs_entries[] = {
137         { "pf_fixed", VCPU_STAT(pf_fixed) },
138         { "pf_guest", VCPU_STAT(pf_guest) },
139         { "tlb_flush", VCPU_STAT(tlb_flush) },
140         { "invlpg", VCPU_STAT(invlpg) },
141         { "exits", VCPU_STAT(exits) },
142         { "io_exits", VCPU_STAT(io_exits) },
143         { "mmio_exits", VCPU_STAT(mmio_exits) },
144         { "signal_exits", VCPU_STAT(signal_exits) },
145         { "irq_window", VCPU_STAT(irq_window_exits) },
146         { "nmi_window", VCPU_STAT(nmi_window_exits) },
147         { "halt_exits", VCPU_STAT(halt_exits) },
148         { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
149         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
150         { "hypercalls", VCPU_STAT(hypercalls) },
151         { "request_irq", VCPU_STAT(request_irq_exits) },
152         { "irq_exits", VCPU_STAT(irq_exits) },
153         { "host_state_reload", VCPU_STAT(host_state_reload) },
154         { "efer_reload", VCPU_STAT(efer_reload) },
155         { "fpu_reload", VCPU_STAT(fpu_reload) },
156         { "insn_emulation", VCPU_STAT(insn_emulation) },
157         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
158         { "irq_injections", VCPU_STAT(irq_injections) },
159         { "nmi_injections", VCPU_STAT(nmi_injections) },
160         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
161         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
162         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
163         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
164         { "mmu_flooded", VM_STAT(mmu_flooded) },
165         { "mmu_recycled", VM_STAT(mmu_recycled) },
166         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
167         { "mmu_unsync", VM_STAT(mmu_unsync) },
168         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
169         { "largepages", VM_STAT(lpages) },
170         { NULL }
171 };
172
173 u64 __read_mostly host_xcr0;
174
175 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
176
177 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
178 {
179         int i;
180         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
181                 vcpu->arch.apf.gfns[i] = ~0;
182 }
183
184 static void kvm_on_user_return(struct user_return_notifier *urn)
185 {
186         unsigned slot;
187         struct kvm_shared_msrs *locals
188                 = container_of(urn, struct kvm_shared_msrs, urn);
189         struct kvm_shared_msr_values *values;
190
191         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
192                 values = &locals->values[slot];
193                 if (values->host != values->curr) {
194                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
195                         values->curr = values->host;
196                 }
197         }
198         locals->registered = false;
199         user_return_notifier_unregister(urn);
200 }
201
202 static void shared_msr_update(unsigned slot, u32 msr)
203 {
204         u64 value;
205         unsigned int cpu = smp_processor_id();
206         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
207
208         /* only read, and nobody should modify it at this time,
209          * so don't need lock */
210         if (slot >= shared_msrs_global.nr) {
211                 printk(KERN_ERR "kvm: invalid MSR slot!");
212                 return;
213         }
214         rdmsrl_safe(msr, &value);
215         smsr->values[slot].host = value;
216         smsr->values[slot].curr = value;
217 }
218
219 void kvm_define_shared_msr(unsigned slot, u32 msr)
220 {
221         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
222         if (slot >= shared_msrs_global.nr)
223                 shared_msrs_global.nr = slot + 1;
224         shared_msrs_global.msrs[slot] = msr;
225         /* we need ensured the shared_msr_global have been updated */
226         smp_wmb();
227 }
228 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
229
230 static void kvm_shared_msr_cpu_online(void)
231 {
232         unsigned i;
233
234         for (i = 0; i < shared_msrs_global.nr; ++i)
235                 shared_msr_update(i, shared_msrs_global.msrs[i]);
236 }
237
238 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
239 {
240         unsigned int cpu = smp_processor_id();
241         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
242         int err;
243
244         if (((value ^ smsr->values[slot].curr) & mask) == 0)
245                 return 0;
246         smsr->values[slot].curr = value;
247         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
248         if (err)
249                 return 1;
250
251         if (!smsr->registered) {
252                 smsr->urn.on_user_return = kvm_on_user_return;
253                 user_return_notifier_register(&smsr->urn);
254                 smsr->registered = true;
255         }
256         return 0;
257 }
258 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
259
260 static void drop_user_return_notifiers(void)
261 {
262         unsigned int cpu = smp_processor_id();
263         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
264
265         if (smsr->registered)
266                 kvm_on_user_return(&smsr->urn);
267 }
268
269 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
270 {
271         return vcpu->arch.apic_base;
272 }
273 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
274
275 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
276 {
277         u64 old_state = vcpu->arch.apic_base &
278                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
279         u64 new_state = msr_info->data &
280                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
282                 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
283
284         if (!msr_info->host_initiated &&
285             ((msr_info->data & reserved_bits) != 0 ||
286              new_state == X2APIC_ENABLE ||
287              (new_state == MSR_IA32_APICBASE_ENABLE &&
288               old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
289              (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
290               old_state == 0)))
291                 return 1;
292
293         kvm_lapic_set_base(vcpu, msr_info->data);
294         return 0;
295 }
296 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
297
298 asmlinkage __visible void kvm_spurious_fault(void)
299 {
300         /* Fault while not rebooting.  We want the trace. */
301         BUG();
302 }
303 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
304
305 #define EXCPT_BENIGN            0
306 #define EXCPT_CONTRIBUTORY      1
307 #define EXCPT_PF                2
308
309 static int exception_class(int vector)
310 {
311         switch (vector) {
312         case PF_VECTOR:
313                 return EXCPT_PF;
314         case DE_VECTOR:
315         case TS_VECTOR:
316         case NP_VECTOR:
317         case SS_VECTOR:
318         case GP_VECTOR:
319                 return EXCPT_CONTRIBUTORY;
320         default:
321                 break;
322         }
323         return EXCPT_BENIGN;
324 }
325
326 #define EXCPT_FAULT             0
327 #define EXCPT_TRAP              1
328 #define EXCPT_ABORT             2
329 #define EXCPT_INTERRUPT         3
330
331 static int exception_type(int vector)
332 {
333         unsigned int mask;
334
335         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
336                 return EXCPT_INTERRUPT;
337
338         mask = 1 << vector;
339
340         /* #DB is trap, as instruction watchpoints are handled elsewhere */
341         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
342                 return EXCPT_TRAP;
343
344         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
345                 return EXCPT_ABORT;
346
347         /* Reserved exceptions will result in fault */
348         return EXCPT_FAULT;
349 }
350
351 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
352                 unsigned nr, bool has_error, u32 error_code,
353                 bool reinject)
354 {
355         u32 prev_nr;
356         int class1, class2;
357
358         kvm_make_request(KVM_REQ_EVENT, vcpu);
359
360         if (!vcpu->arch.exception.pending) {
361         queue:
362                 if (has_error && !is_protmode(vcpu))
363                         has_error = false;
364                 vcpu->arch.exception.pending = true;
365                 vcpu->arch.exception.has_error_code = has_error;
366                 vcpu->arch.exception.nr = nr;
367                 vcpu->arch.exception.error_code = error_code;
368                 vcpu->arch.exception.reinject = reinject;
369                 return;
370         }
371
372         /* to check exception */
373         prev_nr = vcpu->arch.exception.nr;
374         if (prev_nr == DF_VECTOR) {
375                 /* triple fault -> shutdown */
376                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
377                 return;
378         }
379         class1 = exception_class(prev_nr);
380         class2 = exception_class(nr);
381         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
382                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
383                 /* generate double fault per SDM Table 5-5 */
384                 vcpu->arch.exception.pending = true;
385                 vcpu->arch.exception.has_error_code = true;
386                 vcpu->arch.exception.nr = DF_VECTOR;
387                 vcpu->arch.exception.error_code = 0;
388         } else
389                 /* replace previous exception with a new one in a hope
390                    that instruction re-execution will regenerate lost
391                    exception */
392                 goto queue;
393 }
394
395 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
396 {
397         kvm_multiple_exception(vcpu, nr, false, 0, false);
398 }
399 EXPORT_SYMBOL_GPL(kvm_queue_exception);
400
401 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
402 {
403         kvm_multiple_exception(vcpu, nr, false, 0, true);
404 }
405 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
406
407 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
408 {
409         if (err)
410                 kvm_inject_gp(vcpu, 0);
411         else
412                 kvm_x86_ops->skip_emulated_instruction(vcpu);
413 }
414 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
415
416 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
417 {
418         ++vcpu->stat.pf_guest;
419         vcpu->arch.cr2 = fault->address;
420         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
421 }
422 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
423
424 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
425 {
426         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
427                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
428         else
429                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
430
431         return fault->nested_page_fault;
432 }
433
434 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
435 {
436         atomic_inc(&vcpu->arch.nmi_queued);
437         kvm_make_request(KVM_REQ_NMI, vcpu);
438 }
439 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
440
441 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
442 {
443         kvm_multiple_exception(vcpu, nr, true, error_code, false);
444 }
445 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
446
447 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
448 {
449         kvm_multiple_exception(vcpu, nr, true, error_code, true);
450 }
451 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
452
453 /*
454  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
455  * a #GP and return false.
456  */
457 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
458 {
459         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
460                 return true;
461         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
462         return false;
463 }
464 EXPORT_SYMBOL_GPL(kvm_require_cpl);
465
466 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
467 {
468         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
469                 return true;
470
471         kvm_queue_exception(vcpu, UD_VECTOR);
472         return false;
473 }
474 EXPORT_SYMBOL_GPL(kvm_require_dr);
475
476 /*
477  * This function will be used to read from the physical memory of the currently
478  * running guest. The difference to kvm_read_guest_page is that this function
479  * can read from guest physical or from the guest's guest physical memory.
480  */
481 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
482                             gfn_t ngfn, void *data, int offset, int len,
483                             u32 access)
484 {
485         struct x86_exception exception;
486         gfn_t real_gfn;
487         gpa_t ngpa;
488
489         ngpa     = gfn_to_gpa(ngfn);
490         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
491         if (real_gfn == UNMAPPED_GVA)
492                 return -EFAULT;
493
494         real_gfn = gpa_to_gfn(real_gfn);
495
496         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
497 }
498 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
499
500 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
501                                void *data, int offset, int len, u32 access)
502 {
503         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
504                                        data, offset, len, access);
505 }
506
507 /*
508  * Load the pae pdptrs.  Return true is they are all valid.
509  */
510 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
511 {
512         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
513         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
514         int i;
515         int ret;
516         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
517
518         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
519                                       offset * sizeof(u64), sizeof(pdpte),
520                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
521         if (ret < 0) {
522                 ret = 0;
523                 goto out;
524         }
525         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
526                 if (is_present_gpte(pdpte[i]) &&
527                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
528                         ret = 0;
529                         goto out;
530                 }
531         }
532         ret = 1;
533
534         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
535         __set_bit(VCPU_EXREG_PDPTR,
536                   (unsigned long *)&vcpu->arch.regs_avail);
537         __set_bit(VCPU_EXREG_PDPTR,
538                   (unsigned long *)&vcpu->arch.regs_dirty);
539 out:
540
541         return ret;
542 }
543 EXPORT_SYMBOL_GPL(load_pdptrs);
544
545 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
546 {
547         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
548         bool changed = true;
549         int offset;
550         gfn_t gfn;
551         int r;
552
553         if (is_long_mode(vcpu) || !is_pae(vcpu))
554                 return false;
555
556         if (!test_bit(VCPU_EXREG_PDPTR,
557                       (unsigned long *)&vcpu->arch.regs_avail))
558                 return true;
559
560         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
561         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
562         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
563                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
564         if (r < 0)
565                 goto out;
566         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
567 out:
568
569         return changed;
570 }
571
572 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
573 {
574         unsigned long old_cr0 = kvm_read_cr0(vcpu);
575         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
576                                     X86_CR0_CD | X86_CR0_NW;
577
578         cr0 |= X86_CR0_ET;
579
580 #ifdef CONFIG_X86_64
581         if (cr0 & 0xffffffff00000000UL)
582                 return 1;
583 #endif
584
585         cr0 &= ~CR0_RESERVED_BITS;
586
587         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
588                 return 1;
589
590         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
591                 return 1;
592
593         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
594 #ifdef CONFIG_X86_64
595                 if ((vcpu->arch.efer & EFER_LME)) {
596                         int cs_db, cs_l;
597
598                         if (!is_pae(vcpu))
599                                 return 1;
600                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
601                         if (cs_l)
602                                 return 1;
603                 } else
604 #endif
605                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
606                                                  kvm_read_cr3(vcpu)))
607                         return 1;
608         }
609
610         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
611                 return 1;
612
613         kvm_x86_ops->set_cr0(vcpu, cr0);
614
615         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
616                 kvm_clear_async_pf_completion_queue(vcpu);
617                 kvm_async_pf_hash_reset(vcpu);
618         }
619
620         if ((cr0 ^ old_cr0) & update_bits)
621                 kvm_mmu_reset_context(vcpu);
622         return 0;
623 }
624 EXPORT_SYMBOL_GPL(kvm_set_cr0);
625
626 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
627 {
628         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
629 }
630 EXPORT_SYMBOL_GPL(kvm_lmsw);
631
632 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
633 {
634         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
635                         !vcpu->guest_xcr0_loaded) {
636                 /* kvm_set_xcr() also depends on this */
637                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
638                 vcpu->guest_xcr0_loaded = 1;
639         }
640 }
641
642 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
643 {
644         if (vcpu->guest_xcr0_loaded) {
645                 if (vcpu->arch.xcr0 != host_xcr0)
646                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
647                 vcpu->guest_xcr0_loaded = 0;
648         }
649 }
650
651 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
652 {
653         u64 xcr0 = xcr;
654         u64 old_xcr0 = vcpu->arch.xcr0;
655         u64 valid_bits;
656
657         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
658         if (index != XCR_XFEATURE_ENABLED_MASK)
659                 return 1;
660         if (!(xcr0 & XSTATE_FP))
661                 return 1;
662         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
663                 return 1;
664
665         /*
666          * Do not allow the guest to set bits that we do not support
667          * saving.  However, xcr0 bit 0 is always set, even if the
668          * emulated CPU does not support XSAVE (see fx_init).
669          */
670         valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
671         if (xcr0 & ~valid_bits)
672                 return 1;
673
674         if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
675                 return 1;
676
677         if (xcr0 & XSTATE_AVX512) {
678                 if (!(xcr0 & XSTATE_YMM))
679                         return 1;
680                 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
681                         return 1;
682         }
683         kvm_put_guest_xcr0(vcpu);
684         vcpu->arch.xcr0 = xcr0;
685
686         if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
687                 kvm_update_cpuid(vcpu);
688         return 0;
689 }
690
691 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
692 {
693         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
694             __kvm_set_xcr(vcpu, index, xcr)) {
695                 kvm_inject_gp(vcpu, 0);
696                 return 1;
697         }
698         return 0;
699 }
700 EXPORT_SYMBOL_GPL(kvm_set_xcr);
701
702 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
703 {
704         unsigned long old_cr4 = kvm_read_cr4(vcpu);
705         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
706                                    X86_CR4_PAE | X86_CR4_SMEP;
707         if (cr4 & CR4_RESERVED_BITS)
708                 return 1;
709
710         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
711                 return 1;
712
713         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
714                 return 1;
715
716         if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
717                 return 1;
718
719         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
720                 return 1;
721
722         if (is_long_mode(vcpu)) {
723                 if (!(cr4 & X86_CR4_PAE))
724                         return 1;
725         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
726                    && ((cr4 ^ old_cr4) & pdptr_bits)
727                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
728                                    kvm_read_cr3(vcpu)))
729                 return 1;
730
731         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
732                 if (!guest_cpuid_has_pcid(vcpu))
733                         return 1;
734
735                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
736                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
737                         return 1;
738         }
739
740         if (kvm_x86_ops->set_cr4(vcpu, cr4))
741                 return 1;
742
743         if (((cr4 ^ old_cr4) & pdptr_bits) ||
744             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
745                 kvm_mmu_reset_context(vcpu);
746
747         if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
748                 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
749
750         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
751                 kvm_update_cpuid(vcpu);
752
753         return 0;
754 }
755 EXPORT_SYMBOL_GPL(kvm_set_cr4);
756
757 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
758 {
759 #ifdef CONFIG_X86_64
760         cr3 &= ~CR3_PCID_INVD;
761 #endif
762
763         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
764                 kvm_mmu_sync_roots(vcpu);
765                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
766                 return 0;
767         }
768
769         if (is_long_mode(vcpu)) {
770                 if (cr3 & CR3_L_MODE_RESERVED_BITS)
771                         return 1;
772         } else if (is_pae(vcpu) && is_paging(vcpu) &&
773                    !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
774                 return 1;
775
776         vcpu->arch.cr3 = cr3;
777         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
778         kvm_mmu_new_cr3(vcpu);
779         return 0;
780 }
781 EXPORT_SYMBOL_GPL(kvm_set_cr3);
782
783 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
784 {
785         if (cr8 & CR8_RESERVED_BITS)
786                 return 1;
787         if (irqchip_in_kernel(vcpu->kvm))
788                 kvm_lapic_set_tpr(vcpu, cr8);
789         else
790                 vcpu->arch.cr8 = cr8;
791         return 0;
792 }
793 EXPORT_SYMBOL_GPL(kvm_set_cr8);
794
795 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
796 {
797         if (irqchip_in_kernel(vcpu->kvm))
798                 return kvm_lapic_get_cr8(vcpu);
799         else
800                 return vcpu->arch.cr8;
801 }
802 EXPORT_SYMBOL_GPL(kvm_get_cr8);
803
804 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
805 {
806         int i;
807
808         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
809                 for (i = 0; i < KVM_NR_DB_REGS; i++)
810                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
811                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
812         }
813 }
814
815 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
816 {
817         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
818                 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
819 }
820
821 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
822 {
823         unsigned long dr7;
824
825         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
826                 dr7 = vcpu->arch.guest_debug_dr7;
827         else
828                 dr7 = vcpu->arch.dr7;
829         kvm_x86_ops->set_dr7(vcpu, dr7);
830         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
831         if (dr7 & DR7_BP_EN_MASK)
832                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
833 }
834
835 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
836 {
837         u64 fixed = DR6_FIXED_1;
838
839         if (!guest_cpuid_has_rtm(vcpu))
840                 fixed |= DR6_RTM;
841         return fixed;
842 }
843
844 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
845 {
846         switch (dr) {
847         case 0 ... 3:
848                 vcpu->arch.db[dr] = val;
849                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
850                         vcpu->arch.eff_db[dr] = val;
851                 break;
852         case 4:
853                 /* fall through */
854         case 6:
855                 if (val & 0xffffffff00000000ULL)
856                         return -1; /* #GP */
857                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
858                 kvm_update_dr6(vcpu);
859                 break;
860         case 5:
861                 /* fall through */
862         default: /* 7 */
863                 if (val & 0xffffffff00000000ULL)
864                         return -1; /* #GP */
865                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
866                 kvm_update_dr7(vcpu);
867                 break;
868         }
869
870         return 0;
871 }
872
873 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
874 {
875         if (__kvm_set_dr(vcpu, dr, val)) {
876                 kvm_inject_gp(vcpu, 0);
877                 return 1;
878         }
879         return 0;
880 }
881 EXPORT_SYMBOL_GPL(kvm_set_dr);
882
883 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
884 {
885         switch (dr) {
886         case 0 ... 3:
887                 *val = vcpu->arch.db[dr];
888                 break;
889         case 4:
890                 /* fall through */
891         case 6:
892                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
893                         *val = vcpu->arch.dr6;
894                 else
895                         *val = kvm_x86_ops->get_dr6(vcpu);
896                 break;
897         case 5:
898                 /* fall through */
899         default: /* 7 */
900                 *val = vcpu->arch.dr7;
901                 break;
902         }
903         return 0;
904 }
905 EXPORT_SYMBOL_GPL(kvm_get_dr);
906
907 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
908 {
909         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
910         u64 data;
911         int err;
912
913         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
914         if (err)
915                 return err;
916         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
917         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
918         return err;
919 }
920 EXPORT_SYMBOL_GPL(kvm_rdpmc);
921
922 /*
923  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
924  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
925  *
926  * This list is modified at module load time to reflect the
927  * capabilities of the host cpu. This capabilities test skips MSRs that are
928  * kvm-specific. Those are put in the beginning of the list.
929  */
930
931 #define KVM_SAVE_MSRS_BEGIN     12
932 static u32 msrs_to_save[] = {
933         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
934         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
935         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
936         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
937         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
938         MSR_KVM_PV_EOI_EN,
939         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
940         MSR_STAR,
941 #ifdef CONFIG_X86_64
942         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
943 #endif
944         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
945         MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
946 };
947
948 static unsigned num_msrs_to_save;
949
950 static const u32 emulated_msrs[] = {
951         MSR_IA32_TSC_ADJUST,
952         MSR_IA32_TSCDEADLINE,
953         MSR_IA32_MISC_ENABLE,
954         MSR_IA32_MCG_STATUS,
955         MSR_IA32_MCG_CTL,
956 };
957
958 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
959 {
960         if (efer & efer_reserved_bits)
961                 return false;
962
963         if (efer & EFER_FFXSR) {
964                 struct kvm_cpuid_entry2 *feat;
965
966                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
967                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
968                         return false;
969         }
970
971         if (efer & EFER_SVME) {
972                 struct kvm_cpuid_entry2 *feat;
973
974                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
975                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
976                         return false;
977         }
978
979         return true;
980 }
981 EXPORT_SYMBOL_GPL(kvm_valid_efer);
982
983 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
984 {
985         u64 old_efer = vcpu->arch.efer;
986
987         if (!kvm_valid_efer(vcpu, efer))
988                 return 1;
989
990         if (is_paging(vcpu)
991             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
992                 return 1;
993
994         efer &= ~EFER_LMA;
995         efer |= vcpu->arch.efer & EFER_LMA;
996
997         kvm_x86_ops->set_efer(vcpu, efer);
998
999         /* Update reserved bits */
1000         if ((efer ^ old_efer) & EFER_NX)
1001                 kvm_mmu_reset_context(vcpu);
1002
1003         return 0;
1004 }
1005
1006 void kvm_enable_efer_bits(u64 mask)
1007 {
1008        efer_reserved_bits &= ~mask;
1009 }
1010 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1011
1012 /*
1013  * Writes msr value into into the appropriate "register".
1014  * Returns 0 on success, non-0 otherwise.
1015  * Assumes vcpu_load() was already called.
1016  */
1017 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1018 {
1019         switch (msr->index) {
1020         case MSR_FS_BASE:
1021         case MSR_GS_BASE:
1022         case MSR_KERNEL_GS_BASE:
1023         case MSR_CSTAR:
1024         case MSR_LSTAR:
1025                 if (is_noncanonical_address(msr->data))
1026                         return 1;
1027                 break;
1028         case MSR_IA32_SYSENTER_EIP:
1029         case MSR_IA32_SYSENTER_ESP:
1030                 /*
1031                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1032                  * non-canonical address is written on Intel but not on
1033                  * AMD (which ignores the top 32-bits, because it does
1034                  * not implement 64-bit SYSENTER).
1035                  *
1036                  * 64-bit code should hence be able to write a non-canonical
1037                  * value on AMD.  Making the address canonical ensures that
1038                  * vmentry does not fail on Intel after writing a non-canonical
1039                  * value, and that something deterministic happens if the guest
1040                  * invokes 64-bit SYSENTER.
1041                  */
1042                 msr->data = get_canonical(msr->data);
1043         }
1044         return kvm_x86_ops->set_msr(vcpu, msr);
1045 }
1046 EXPORT_SYMBOL_GPL(kvm_set_msr);
1047
1048 /*
1049  * Adapt set_msr() to msr_io()'s calling convention
1050  */
1051 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1052 {
1053         struct msr_data msr;
1054
1055         msr.data = *data;
1056         msr.index = index;
1057         msr.host_initiated = true;
1058         return kvm_set_msr(vcpu, &msr);
1059 }
1060
1061 #ifdef CONFIG_X86_64
1062 struct pvclock_gtod_data {
1063         seqcount_t      seq;
1064
1065         struct { /* extract of a clocksource struct */
1066                 int vclock_mode;
1067                 cycle_t cycle_last;
1068                 cycle_t mask;
1069                 u32     mult;
1070                 u32     shift;
1071         } clock;
1072
1073         u64             boot_ns;
1074         u64             nsec_base;
1075 };
1076
1077 static struct pvclock_gtod_data pvclock_gtod_data;
1078
1079 static void update_pvclock_gtod(struct timekeeper *tk)
1080 {
1081         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1082         u64 boot_ns;
1083
1084         boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1085
1086         write_seqcount_begin(&vdata->seq);
1087
1088         /* copy pvclock gtod data */
1089         vdata->clock.vclock_mode        = tk->tkr_mono.clock->archdata.vclock_mode;
1090         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1091         vdata->clock.mask               = tk->tkr_mono.mask;
1092         vdata->clock.mult               = tk->tkr_mono.mult;
1093         vdata->clock.shift              = tk->tkr_mono.shift;
1094
1095         vdata->boot_ns                  = boot_ns;
1096         vdata->nsec_base                = tk->tkr_mono.xtime_nsec;
1097
1098         write_seqcount_end(&vdata->seq);
1099 }
1100 #endif
1101
1102 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1103 {
1104         /*
1105          * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1106          * vcpu_enter_guest.  This function is only called from
1107          * the physical CPU that is running vcpu.
1108          */
1109         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1110 }
1111
1112 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1113 {
1114         int version;
1115         int r;
1116         struct pvclock_wall_clock wc;
1117         struct timespec boot;
1118
1119         if (!wall_clock)
1120                 return;
1121
1122         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1123         if (r)
1124                 return;
1125
1126         if (version & 1)
1127                 ++version;  /* first time write, random junk */
1128
1129         ++version;
1130
1131         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1132
1133         /*
1134          * The guest calculates current wall clock time by adding
1135          * system time (updated by kvm_guest_time_update below) to the
1136          * wall clock specified here.  guest system time equals host
1137          * system time for us, thus we must fill in host boot time here.
1138          */
1139         getboottime(&boot);
1140
1141         if (kvm->arch.kvmclock_offset) {
1142                 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1143                 boot = timespec_sub(boot, ts);
1144         }
1145         wc.sec = boot.tv_sec;
1146         wc.nsec = boot.tv_nsec;
1147         wc.version = version;
1148
1149         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1150
1151         version++;
1152         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1153 }
1154
1155 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1156 {
1157         uint32_t quotient, remainder;
1158
1159         /* Don't try to replace with do_div(), this one calculates
1160          * "(dividend << 32) / divisor" */
1161         __asm__ ( "divl %4"
1162                   : "=a" (quotient), "=d" (remainder)
1163                   : "0" (0), "1" (dividend), "r" (divisor) );
1164         return quotient;
1165 }
1166
1167 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1168                                s8 *pshift, u32 *pmultiplier)
1169 {
1170         uint64_t scaled64;
1171         int32_t  shift = 0;
1172         uint64_t tps64;
1173         uint32_t tps32;
1174
1175         tps64 = base_khz * 1000LL;
1176         scaled64 = scaled_khz * 1000LL;
1177         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1178                 tps64 >>= 1;
1179                 shift--;
1180         }
1181
1182         tps32 = (uint32_t)tps64;
1183         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1184                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1185                         scaled64 >>= 1;
1186                 else
1187                         tps32 <<= 1;
1188                 shift++;
1189         }
1190
1191         *pshift = shift;
1192         *pmultiplier = div_frac(scaled64, tps32);
1193
1194         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1195                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
1196 }
1197
1198 static inline u64 get_kernel_ns(void)
1199 {
1200         return ktime_get_boot_ns();
1201 }
1202
1203 #ifdef CONFIG_X86_64
1204 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1205 #endif
1206
1207 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1208 static unsigned long max_tsc_khz;
1209
1210 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1211 {
1212         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1213                                    vcpu->arch.virtual_tsc_shift);
1214 }
1215
1216 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1217 {
1218         u64 v = (u64)khz * (1000000 + ppm);
1219         do_div(v, 1000000);
1220         return v;
1221 }
1222
1223 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1224 {
1225         u32 thresh_lo, thresh_hi;
1226         int use_scaling = 0;
1227
1228         /* tsc_khz can be zero if TSC calibration fails */
1229         if (this_tsc_khz == 0)
1230                 return;
1231
1232         /* Compute a scale to convert nanoseconds in TSC cycles */
1233         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1234                            &vcpu->arch.virtual_tsc_shift,
1235                            &vcpu->arch.virtual_tsc_mult);
1236         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1237
1238         /*
1239          * Compute the variation in TSC rate which is acceptable
1240          * within the range of tolerance and decide if the
1241          * rate being applied is within that bounds of the hardware
1242          * rate.  If so, no scaling or compensation need be done.
1243          */
1244         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1245         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1246         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1247                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1248                 use_scaling = 1;
1249         }
1250         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1251 }
1252
1253 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1254 {
1255         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1256                                       vcpu->arch.virtual_tsc_mult,
1257                                       vcpu->arch.virtual_tsc_shift);
1258         tsc += vcpu->arch.this_tsc_write;
1259         return tsc;
1260 }
1261
1262 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1263 {
1264 #ifdef CONFIG_X86_64
1265         bool vcpus_matched;
1266         struct kvm_arch *ka = &vcpu->kvm->arch;
1267         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1268
1269         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1270                          atomic_read(&vcpu->kvm->online_vcpus));
1271
1272         /*
1273          * Once the masterclock is enabled, always perform request in
1274          * order to update it.
1275          *
1276          * In order to enable masterclock, the host clocksource must be TSC
1277          * and the vcpus need to have matched TSCs.  When that happens,
1278          * perform request to enable masterclock.
1279          */
1280         if (ka->use_master_clock ||
1281             (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1282                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1283
1284         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1285                             atomic_read(&vcpu->kvm->online_vcpus),
1286                             ka->use_master_clock, gtod->clock.vclock_mode);
1287 #endif
1288 }
1289
1290 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1291 {
1292         u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1293         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1294 }
1295
1296 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1297 {
1298         struct kvm *kvm = vcpu->kvm;
1299         u64 offset, ns, elapsed;
1300         unsigned long flags;
1301         s64 usdiff;
1302         bool matched;
1303         bool already_matched;
1304         u64 data = msr->data;
1305
1306         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1307         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1308         ns = get_kernel_ns();
1309         elapsed = ns - kvm->arch.last_tsc_nsec;
1310
1311         if (vcpu->arch.virtual_tsc_khz) {
1312                 int faulted = 0;
1313
1314                 /* n.b - signed multiplication and division required */
1315                 usdiff = data - kvm->arch.last_tsc_write;
1316 #ifdef CONFIG_X86_64
1317                 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1318 #else
1319                 /* do_div() only does unsigned */
1320                 asm("1: idivl %[divisor]\n"
1321                     "2: xor %%edx, %%edx\n"
1322                     "   movl $0, %[faulted]\n"
1323                     "3:\n"
1324                     ".section .fixup,\"ax\"\n"
1325                     "4: movl $1, %[faulted]\n"
1326                     "   jmp  3b\n"
1327                     ".previous\n"
1328
1329                 _ASM_EXTABLE(1b, 4b)
1330
1331                 : "=A"(usdiff), [faulted] "=r" (faulted)
1332                 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1333
1334 #endif
1335                 do_div(elapsed, 1000);
1336                 usdiff -= elapsed;
1337                 if (usdiff < 0)
1338                         usdiff = -usdiff;
1339
1340                 /* idivl overflow => difference is larger than USEC_PER_SEC */
1341                 if (faulted)
1342                         usdiff = USEC_PER_SEC;
1343         } else
1344                 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1345
1346         /*
1347          * Special case: TSC write with a small delta (1 second) of virtual
1348          * cycle time against real time is interpreted as an attempt to
1349          * synchronize the CPU.
1350          *
1351          * For a reliable TSC, we can match TSC offsets, and for an unstable
1352          * TSC, we add elapsed time in this computation.  We could let the
1353          * compensation code attempt to catch up if we fall behind, but
1354          * it's better to try to match offsets from the beginning.
1355          */
1356         if (usdiff < USEC_PER_SEC &&
1357             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1358                 if (!check_tsc_unstable()) {
1359                         offset = kvm->arch.cur_tsc_offset;
1360                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1361                 } else {
1362                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1363                         data += delta;
1364                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1365                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1366                 }
1367                 matched = true;
1368                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1369         } else {
1370                 /*
1371                  * We split periods of matched TSC writes into generations.
1372                  * For each generation, we track the original measured
1373                  * nanosecond time, offset, and write, so if TSCs are in
1374                  * sync, we can match exact offset, and if not, we can match
1375                  * exact software computation in compute_guest_tsc()
1376                  *
1377                  * These values are tracked in kvm->arch.cur_xxx variables.
1378                  */
1379                 kvm->arch.cur_tsc_generation++;
1380                 kvm->arch.cur_tsc_nsec = ns;
1381                 kvm->arch.cur_tsc_write = data;
1382                 kvm->arch.cur_tsc_offset = offset;
1383                 matched = false;
1384                 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1385                          kvm->arch.cur_tsc_generation, data);
1386         }
1387
1388         /*
1389          * We also track th most recent recorded KHZ, write and time to
1390          * allow the matching interval to be extended at each write.
1391          */
1392         kvm->arch.last_tsc_nsec = ns;
1393         kvm->arch.last_tsc_write = data;
1394         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1395
1396         vcpu->arch.last_guest_tsc = data;
1397
1398         /* Keep track of which generation this VCPU has synchronized to */
1399         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1400         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1401         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1402
1403         if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1404                 update_ia32_tsc_adjust_msr(vcpu, offset);
1405         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1406         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1407
1408         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1409         if (!matched) {
1410                 kvm->arch.nr_vcpus_matched_tsc = 0;
1411         } else if (!already_matched) {
1412                 kvm->arch.nr_vcpus_matched_tsc++;
1413         }
1414
1415         kvm_track_tsc_matching(vcpu);
1416         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1417 }
1418
1419 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1420
1421 #ifdef CONFIG_X86_64
1422
1423 static cycle_t read_tsc(void)
1424 {
1425         cycle_t ret;
1426         u64 last;
1427
1428         /*
1429          * Empirically, a fence (of type that depends on the CPU)
1430          * before rdtsc is enough to ensure that rdtsc is ordered
1431          * with respect to loads.  The various CPU manuals are unclear
1432          * as to whether rdtsc can be reordered with later loads,
1433          * but no one has ever seen it happen.
1434          */
1435         rdtsc_barrier();
1436         ret = (cycle_t)vget_cycles();
1437
1438         last = pvclock_gtod_data.clock.cycle_last;
1439
1440         if (likely(ret >= last))
1441                 return ret;
1442
1443         /*
1444          * GCC likes to generate cmov here, but this branch is extremely
1445          * predictable (it's just a funciton of time and the likely is
1446          * very likely) and there's a data dependence, so force GCC
1447          * to generate a branch instead.  I don't barrier() because
1448          * we don't actually need a barrier, and if this function
1449          * ever gets inlined it will generate worse code.
1450          */
1451         asm volatile ("");
1452         return last;
1453 }
1454
1455 static inline u64 vgettsc(cycle_t *cycle_now)
1456 {
1457         long v;
1458         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1459
1460         *cycle_now = read_tsc();
1461
1462         v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1463         return v * gtod->clock.mult;
1464 }
1465
1466 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1467 {
1468         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1469         unsigned long seq;
1470         int mode;
1471         u64 ns;
1472
1473         do {
1474                 seq = read_seqcount_begin(&gtod->seq);
1475                 mode = gtod->clock.vclock_mode;
1476                 ns = gtod->nsec_base;
1477                 ns += vgettsc(cycle_now);
1478                 ns >>= gtod->clock.shift;
1479                 ns += gtod->boot_ns;
1480         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1481         *t = ns;
1482
1483         return mode;
1484 }
1485
1486 /* returns true if host is using tsc clocksource */
1487 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1488 {
1489         /* checked again under seqlock below */
1490         if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1491                 return false;
1492
1493         return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1494 }
1495 #endif
1496
1497 /*
1498  *
1499  * Assuming a stable TSC across physical CPUS, and a stable TSC
1500  * across virtual CPUs, the following condition is possible.
1501  * Each numbered line represents an event visible to both
1502  * CPUs at the next numbered event.
1503  *
1504  * "timespecX" represents host monotonic time. "tscX" represents
1505  * RDTSC value.
1506  *
1507  *              VCPU0 on CPU0           |       VCPU1 on CPU1
1508  *
1509  * 1.  read timespec0,tsc0
1510  * 2.                                   | timespec1 = timespec0 + N
1511  *                                      | tsc1 = tsc0 + M
1512  * 3. transition to guest               | transition to guest
1513  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1514  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
1515  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1516  *
1517  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1518  *
1519  *      - ret0 < ret1
1520  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1521  *              ...
1522  *      - 0 < N - M => M < N
1523  *
1524  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1525  * always the case (the difference between two distinct xtime instances
1526  * might be smaller then the difference between corresponding TSC reads,
1527  * when updating guest vcpus pvclock areas).
1528  *
1529  * To avoid that problem, do not allow visibility of distinct
1530  * system_timestamp/tsc_timestamp values simultaneously: use a master
1531  * copy of host monotonic time values. Update that master copy
1532  * in lockstep.
1533  *
1534  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1535  *
1536  */
1537
1538 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1539 {
1540 #ifdef CONFIG_X86_64
1541         struct kvm_arch *ka = &kvm->arch;
1542         int vclock_mode;
1543         bool host_tsc_clocksource, vcpus_matched;
1544
1545         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1546                         atomic_read(&kvm->online_vcpus));
1547
1548         /*
1549          * If the host uses TSC clock, then passthrough TSC as stable
1550          * to the guest.
1551          */
1552         host_tsc_clocksource = kvm_get_time_and_clockread(
1553                                         &ka->master_kernel_ns,
1554                                         &ka->master_cycle_now);
1555
1556         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1557                                 && !backwards_tsc_observed
1558                                 && !ka->boot_vcpu_runs_old_kvmclock;
1559
1560         if (ka->use_master_clock)
1561                 atomic_set(&kvm_guest_has_master_clock, 1);
1562
1563         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1564         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1565                                         vcpus_matched);
1566 #endif
1567 }
1568
1569 static void kvm_gen_update_masterclock(struct kvm *kvm)
1570 {
1571 #ifdef CONFIG_X86_64
1572         int i;
1573         struct kvm_vcpu *vcpu;
1574         struct kvm_arch *ka = &kvm->arch;
1575
1576         spin_lock(&ka->pvclock_gtod_sync_lock);
1577         kvm_make_mclock_inprogress_request(kvm);
1578         /* no guest entries from this point */
1579         pvclock_update_vm_gtod_copy(kvm);
1580
1581         kvm_for_each_vcpu(i, vcpu, kvm)
1582                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1583
1584         /* guest entries allowed */
1585         kvm_for_each_vcpu(i, vcpu, kvm)
1586                 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1587
1588         spin_unlock(&ka->pvclock_gtod_sync_lock);
1589 #endif
1590 }
1591
1592 static int kvm_guest_time_update(struct kvm_vcpu *v)
1593 {
1594         unsigned long flags, this_tsc_khz;
1595         struct kvm_vcpu_arch *vcpu = &v->arch;
1596         struct kvm_arch *ka = &v->kvm->arch;
1597         s64 kernel_ns;
1598         u64 tsc_timestamp, host_tsc;
1599         struct pvclock_vcpu_time_info guest_hv_clock;
1600         u8 pvclock_flags;
1601         bool use_master_clock;
1602
1603         kernel_ns = 0;
1604         host_tsc = 0;
1605
1606         /*
1607          * If the host uses TSC clock, then passthrough TSC as stable
1608          * to the guest.
1609          */
1610         spin_lock(&ka->pvclock_gtod_sync_lock);
1611         use_master_clock = ka->use_master_clock;
1612         if (use_master_clock) {
1613                 host_tsc = ka->master_cycle_now;
1614                 kernel_ns = ka->master_kernel_ns;
1615         }
1616         spin_unlock(&ka->pvclock_gtod_sync_lock);
1617
1618         /* Keep irq disabled to prevent changes to the clock */
1619         local_irq_save(flags);
1620         this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1621         if (unlikely(this_tsc_khz == 0)) {
1622                 local_irq_restore(flags);
1623                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1624                 return 1;
1625         }
1626         if (!use_master_clock) {
1627                 host_tsc = native_read_tsc();
1628                 kernel_ns = get_kernel_ns();
1629         }
1630
1631         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1632
1633         /*
1634          * We may have to catch up the TSC to match elapsed wall clock
1635          * time for two reasons, even if kvmclock is used.
1636          *   1) CPU could have been running below the maximum TSC rate
1637          *   2) Broken TSC compensation resets the base at each VCPU
1638          *      entry to avoid unknown leaps of TSC even when running
1639          *      again on the same CPU.  This may cause apparent elapsed
1640          *      time to disappear, and the guest to stand still or run
1641          *      very slowly.
1642          */
1643         if (vcpu->tsc_catchup) {
1644                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1645                 if (tsc > tsc_timestamp) {
1646                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1647                         tsc_timestamp = tsc;
1648                 }
1649         }
1650
1651         local_irq_restore(flags);
1652
1653         if (!vcpu->pv_time_enabled)
1654                 return 0;
1655
1656         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1657                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1658                                    &vcpu->hv_clock.tsc_shift,
1659                                    &vcpu->hv_clock.tsc_to_system_mul);
1660                 vcpu->hw_tsc_khz = this_tsc_khz;
1661         }
1662
1663         /* With all the info we got, fill in the values */
1664         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1665         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1666         vcpu->last_guest_tsc = tsc_timestamp;
1667
1668         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1669                 &guest_hv_clock, sizeof(guest_hv_clock))))
1670                 return 0;
1671
1672         /* This VCPU is paused, but it's legal for a guest to read another
1673          * VCPU's kvmclock, so we really have to follow the specification where
1674          * it says that version is odd if data is being modified, and even after
1675          * it is consistent.
1676          *
1677          * Version field updates must be kept separate.  This is because
1678          * kvm_write_guest_cached might use a "rep movs" instruction, and
1679          * writes within a string instruction are weakly ordered.  So there
1680          * are three writes overall.
1681          *
1682          * As a small optimization, only write the version field in the first
1683          * and third write.  The vcpu->pv_time cache is still valid, because the
1684          * version field is the first in the struct.
1685          */
1686         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1687
1688         vcpu->hv_clock.version = guest_hv_clock.version + 1;
1689         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1690                                 &vcpu->hv_clock,
1691                                 sizeof(vcpu->hv_clock.version));
1692
1693         smp_wmb();
1694
1695         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1696         pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1697
1698         if (vcpu->pvclock_set_guest_stopped_request) {
1699                 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1700                 vcpu->pvclock_set_guest_stopped_request = false;
1701         }
1702
1703         /* If the host uses TSC clocksource, then it is stable */
1704         if (use_master_clock)
1705                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1706
1707         vcpu->hv_clock.flags = pvclock_flags;
1708
1709         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1710
1711         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1712                                 &vcpu->hv_clock,
1713                                 sizeof(vcpu->hv_clock));
1714
1715         smp_wmb();
1716
1717         vcpu->hv_clock.version++;
1718         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1719                                 &vcpu->hv_clock,
1720                                 sizeof(vcpu->hv_clock.version));
1721         return 0;
1722 }
1723
1724 /*
1725  * kvmclock updates which are isolated to a given vcpu, such as
1726  * vcpu->cpu migration, should not allow system_timestamp from
1727  * the rest of the vcpus to remain static. Otherwise ntp frequency
1728  * correction applies to one vcpu's system_timestamp but not
1729  * the others.
1730  *
1731  * So in those cases, request a kvmclock update for all vcpus.
1732  * We need to rate-limit these requests though, as they can
1733  * considerably slow guests that have a large number of vcpus.
1734  * The time for a remote vcpu to update its kvmclock is bound
1735  * by the delay we use to rate-limit the updates.
1736  */
1737
1738 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1739
1740 static void kvmclock_update_fn(struct work_struct *work)
1741 {
1742         int i;
1743         struct delayed_work *dwork = to_delayed_work(work);
1744         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1745                                            kvmclock_update_work);
1746         struct kvm *kvm = container_of(ka, struct kvm, arch);
1747         struct kvm_vcpu *vcpu;
1748
1749         kvm_for_each_vcpu(i, vcpu, kvm) {
1750                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1751                 kvm_vcpu_kick(vcpu);
1752         }
1753 }
1754
1755 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1756 {
1757         struct kvm *kvm = v->kvm;
1758
1759         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1760         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1761                                         KVMCLOCK_UPDATE_DELAY);
1762 }
1763
1764 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1765
1766 static void kvmclock_sync_fn(struct work_struct *work)
1767 {
1768         struct delayed_work *dwork = to_delayed_work(work);
1769         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1770                                            kvmclock_sync_work);
1771         struct kvm *kvm = container_of(ka, struct kvm, arch);
1772
1773         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1774         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1775                                         KVMCLOCK_SYNC_PERIOD);
1776 }
1777
1778 static bool msr_mtrr_valid(unsigned msr)
1779 {
1780         switch (msr) {
1781         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1782         case MSR_MTRRfix64K_00000:
1783         case MSR_MTRRfix16K_80000:
1784         case MSR_MTRRfix16K_A0000:
1785         case MSR_MTRRfix4K_C0000:
1786         case MSR_MTRRfix4K_C8000:
1787         case MSR_MTRRfix4K_D0000:
1788         case MSR_MTRRfix4K_D8000:
1789         case MSR_MTRRfix4K_E0000:
1790         case MSR_MTRRfix4K_E8000:
1791         case MSR_MTRRfix4K_F0000:
1792         case MSR_MTRRfix4K_F8000:
1793         case MSR_MTRRdefType:
1794         case MSR_IA32_CR_PAT:
1795                 return true;
1796         case 0x2f8:
1797                 return true;
1798         }
1799         return false;
1800 }
1801
1802 static bool valid_pat_type(unsigned t)
1803 {
1804         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1805 }
1806
1807 static bool valid_mtrr_type(unsigned t)
1808 {
1809         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1810 }
1811
1812 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1813 {
1814         int i;
1815         u64 mask;
1816
1817         if (!msr_mtrr_valid(msr))
1818                 return false;
1819
1820         if (msr == MSR_IA32_CR_PAT) {
1821                 for (i = 0; i < 8; i++)
1822                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1823                                 return false;
1824                 return true;
1825         } else if (msr == MSR_MTRRdefType) {
1826                 if (data & ~0xcff)
1827                         return false;
1828                 return valid_mtrr_type(data & 0xff);
1829         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1830                 for (i = 0; i < 8 ; i++)
1831                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1832                                 return false;
1833                 return true;
1834         }
1835
1836         /* variable MTRRs */
1837         WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1838
1839         mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
1840         if ((msr & 1) == 0) {
1841                 /* MTRR base */
1842                 if (!valid_mtrr_type(data & 0xff))
1843                         return false;
1844                 mask |= 0xf00;
1845         } else
1846                 /* MTRR mask */
1847                 mask |= 0x7ff;
1848         if (data & mask) {
1849                 kvm_inject_gp(vcpu, 0);
1850                 return false;
1851         }
1852
1853         return true;
1854 }
1855 EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
1856
1857 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1858 {
1859         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1860
1861         if (!kvm_mtrr_valid(vcpu, msr, data))
1862                 return 1;
1863
1864         if (msr == MSR_MTRRdefType) {
1865                 vcpu->arch.mtrr_state.def_type = data;
1866                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1867         } else if (msr == MSR_MTRRfix64K_00000)
1868                 p[0] = data;
1869         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1870                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1871         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1872                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1873         else if (msr == MSR_IA32_CR_PAT)
1874                 vcpu->arch.pat = data;
1875         else {  /* Variable MTRRs */
1876                 int idx, is_mtrr_mask;
1877                 u64 *pt;
1878
1879                 idx = (msr - 0x200) / 2;
1880                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1881                 if (!is_mtrr_mask)
1882                         pt =
1883                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1884                 else
1885                         pt =
1886                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1887                 *pt = data;
1888         }
1889
1890         kvm_mmu_reset_context(vcpu);
1891         return 0;
1892 }
1893
1894 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1895 {
1896         u64 mcg_cap = vcpu->arch.mcg_cap;
1897         unsigned bank_num = mcg_cap & 0xff;
1898
1899         switch (msr) {
1900         case MSR_IA32_MCG_STATUS:
1901                 vcpu->arch.mcg_status = data;
1902                 break;
1903         case MSR_IA32_MCG_CTL:
1904                 if (!(mcg_cap & MCG_CTL_P))
1905                         return 1;
1906                 if (data != 0 && data != ~(u64)0)
1907                         return -1;
1908                 vcpu->arch.mcg_ctl = data;
1909                 break;
1910         default:
1911                 if (msr >= MSR_IA32_MC0_CTL &&
1912                     msr < MSR_IA32_MCx_CTL(bank_num)) {
1913                         u32 offset = msr - MSR_IA32_MC0_CTL;
1914                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1915                          * some Linux kernels though clear bit 10 in bank 4 to
1916                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1917                          * this to avoid an uncatched #GP in the guest
1918                          */
1919                         if ((offset & 0x3) == 0 &&
1920                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1921                                 return -1;
1922                         vcpu->arch.mce_banks[offset] = data;
1923                         break;
1924                 }
1925                 return 1;
1926         }
1927         return 0;
1928 }
1929
1930 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1931 {
1932         struct kvm *kvm = vcpu->kvm;
1933         int lm = is_long_mode(vcpu);
1934         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1935                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1936         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1937                 : kvm->arch.xen_hvm_config.blob_size_32;
1938         u32 page_num = data & ~PAGE_MASK;
1939         u64 page_addr = data & PAGE_MASK;
1940         u8 *page;
1941         int r;
1942
1943         r = -E2BIG;
1944         if (page_num >= blob_size)
1945                 goto out;
1946         r = -ENOMEM;
1947         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1948         if (IS_ERR(page)) {
1949                 r = PTR_ERR(page);
1950                 goto out;
1951         }
1952         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1953                 goto out_free;
1954         r = 0;
1955 out_free:
1956         kfree(page);
1957 out:
1958         return r;
1959 }
1960
1961 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1962 {
1963         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1964 }
1965
1966 static bool kvm_hv_msr_partition_wide(u32 msr)
1967 {
1968         bool r = false;
1969         switch (msr) {
1970         case HV_X64_MSR_GUEST_OS_ID:
1971         case HV_X64_MSR_HYPERCALL:
1972         case HV_X64_MSR_REFERENCE_TSC:
1973         case HV_X64_MSR_TIME_REF_COUNT:
1974                 r = true;
1975                 break;
1976         }
1977
1978         return r;
1979 }
1980
1981 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1982 {
1983         struct kvm *kvm = vcpu->kvm;
1984
1985         switch (msr) {
1986         case HV_X64_MSR_GUEST_OS_ID:
1987                 kvm->arch.hv_guest_os_id = data;
1988                 /* setting guest os id to zero disables hypercall page */
1989                 if (!kvm->arch.hv_guest_os_id)
1990                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1991                 break;
1992         case HV_X64_MSR_HYPERCALL: {
1993                 u64 gfn;
1994                 unsigned long addr;
1995                 u8 instructions[4];
1996
1997                 /* if guest os id is not set hypercall should remain disabled */
1998                 if (!kvm->arch.hv_guest_os_id)
1999                         break;
2000                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
2001                         kvm->arch.hv_hypercall = data;
2002                         break;
2003                 }
2004                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
2005                 addr = gfn_to_hva(kvm, gfn);
2006                 if (kvm_is_error_hva(addr))
2007                         return 1;
2008                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
2009                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
2010                 if (__copy_to_user((void __user *)addr, instructions, 4))
2011                         return 1;
2012                 kvm->arch.hv_hypercall = data;
2013                 mark_page_dirty(kvm, gfn);
2014                 break;
2015         }
2016         case HV_X64_MSR_REFERENCE_TSC: {
2017                 u64 gfn;
2018                 HV_REFERENCE_TSC_PAGE tsc_ref;
2019                 memset(&tsc_ref, 0, sizeof(tsc_ref));
2020                 kvm->arch.hv_tsc_page = data;
2021                 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
2022                         break;
2023                 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
2024                 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
2025                         &tsc_ref, sizeof(tsc_ref)))
2026                         return 1;
2027                 mark_page_dirty(kvm, gfn);
2028                 break;
2029         }
2030         default:
2031                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2032                             "data 0x%llx\n", msr, data);
2033                 return 1;
2034         }
2035         return 0;
2036 }
2037
2038 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2039 {
2040         switch (msr) {
2041         case HV_X64_MSR_APIC_ASSIST_PAGE: {
2042                 u64 gfn;
2043                 unsigned long addr;
2044
2045                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2046                         vcpu->arch.hv_vapic = data;
2047                         if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2048                                 return 1;
2049                         break;
2050                 }
2051                 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2052                 addr = gfn_to_hva(vcpu->kvm, gfn);
2053                 if (kvm_is_error_hva(addr))
2054                         return 1;
2055                 if (__clear_user((void __user *)addr, PAGE_SIZE))
2056                         return 1;
2057                 vcpu->arch.hv_vapic = data;
2058                 mark_page_dirty(vcpu->kvm, gfn);
2059                 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2060                         return 1;
2061                 break;
2062         }
2063         case HV_X64_MSR_EOI:
2064                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2065         case HV_X64_MSR_ICR:
2066                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2067         case HV_X64_MSR_TPR:
2068                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2069         default:
2070                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2071                             "data 0x%llx\n", msr, data);
2072                 return 1;
2073         }
2074
2075         return 0;
2076 }
2077
2078 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2079 {
2080         gpa_t gpa = data & ~0x3f;
2081
2082         /* Bits 2:5 are reserved, Should be zero */
2083         if (data & 0x3c)
2084                 return 1;
2085
2086         vcpu->arch.apf.msr_val = data;
2087
2088         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2089                 kvm_clear_async_pf_completion_queue(vcpu);
2090                 kvm_async_pf_hash_reset(vcpu);
2091                 return 0;
2092         }
2093
2094         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2095                                         sizeof(u32)))
2096                 return 1;
2097
2098         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2099         kvm_async_pf_wakeup_all(vcpu);
2100         return 0;
2101 }
2102
2103 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2104 {
2105         vcpu->arch.pv_time_enabled = false;
2106 }
2107
2108 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2109 {
2110         u64 delta;
2111
2112         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2113                 return;
2114
2115         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2116         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2117         vcpu->arch.st.accum_steal = delta;
2118 }
2119
2120 static void record_steal_time(struct kvm_vcpu *vcpu)
2121 {
2122         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2123                 return;
2124
2125         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2126                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2127                 return;
2128
2129         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2130         vcpu->arch.st.steal.version += 2;
2131         vcpu->arch.st.accum_steal = 0;
2132
2133         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2134                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2135 }
2136
2137 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2138 {
2139         bool pr = false;
2140         u32 msr = msr_info->index;
2141         u64 data = msr_info->data;
2142
2143         switch (msr) {
2144         case MSR_AMD64_NB_CFG:
2145         case MSR_IA32_UCODE_REV:
2146         case MSR_IA32_UCODE_WRITE:
2147         case MSR_VM_HSAVE_PA:
2148         case MSR_AMD64_PATCH_LOADER:
2149         case MSR_AMD64_BU_CFG2:
2150                 break;
2151
2152         case MSR_EFER:
2153                 return set_efer(vcpu, data);
2154         case MSR_K7_HWCR:
2155                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2156                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2157                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2158                 data &= ~(u64)0x40000;  /* ignore Mc status write enable */
2159                 if (data != 0) {
2160                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2161                                     data);
2162                         return 1;
2163                 }
2164                 break;
2165         case MSR_FAM10H_MMIO_CONF_BASE:
2166                 if (data != 0) {
2167                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2168                                     "0x%llx\n", data);
2169                         return 1;
2170                 }
2171                 break;
2172         case MSR_IA32_DEBUGCTLMSR:
2173                 if (!data) {
2174                         /* We support the non-activated case already */
2175                         break;
2176                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2177                         /* Values other than LBR and BTF are vendor-specific,
2178                            thus reserved and should throw a #GP */
2179                         return 1;
2180                 }
2181                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2182                             __func__, data);
2183                 break;
2184         case 0x200 ... 0x2ff:
2185                 return set_msr_mtrr(vcpu, msr, data);
2186         case MSR_IA32_APICBASE:
2187                 return kvm_set_apic_base(vcpu, msr_info);
2188         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2189                 return kvm_x2apic_msr_write(vcpu, msr, data);
2190         case MSR_IA32_TSCDEADLINE:
2191                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2192                 break;
2193         case MSR_IA32_TSC_ADJUST:
2194                 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2195                         if (!msr_info->host_initiated) {
2196                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2197                                 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2198                         }
2199                         vcpu->arch.ia32_tsc_adjust_msr = data;
2200                 }
2201                 break;
2202         case MSR_IA32_MISC_ENABLE:
2203                 vcpu->arch.ia32_misc_enable_msr = data;
2204                 break;
2205         case MSR_KVM_WALL_CLOCK_NEW:
2206         case MSR_KVM_WALL_CLOCK:
2207                 vcpu->kvm->arch.wall_clock = data;
2208                 kvm_write_wall_clock(vcpu->kvm, data);
2209                 break;
2210         case MSR_KVM_SYSTEM_TIME_NEW:
2211         case MSR_KVM_SYSTEM_TIME: {
2212                 u64 gpa_offset;
2213                 struct kvm_arch *ka = &vcpu->kvm->arch;
2214
2215                 kvmclock_reset(vcpu);
2216
2217                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2218                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2219
2220                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2221                                 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2222                                         &vcpu->requests);
2223
2224                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2225                 }
2226
2227                 vcpu->arch.time = data;
2228                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2229
2230                 /* we verify if the enable bit is set... */
2231                 if (!(data & 1))
2232                         break;
2233
2234                 gpa_offset = data & ~(PAGE_MASK | 1);
2235
2236                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2237                      &vcpu->arch.pv_time, data & ~1ULL,
2238                      sizeof(struct pvclock_vcpu_time_info)))
2239                         vcpu->arch.pv_time_enabled = false;
2240                 else
2241                         vcpu->arch.pv_time_enabled = true;
2242
2243                 break;
2244         }
2245         case MSR_KVM_ASYNC_PF_EN:
2246                 if (kvm_pv_enable_async_pf(vcpu, data))
2247                         return 1;
2248                 break;
2249         case MSR_KVM_STEAL_TIME:
2250
2251                 if (unlikely(!sched_info_on()))
2252                         return 1;
2253
2254                 if (data & KVM_STEAL_RESERVED_MASK)
2255                         return 1;
2256
2257                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2258                                                 data & KVM_STEAL_VALID_BITS,
2259                                                 sizeof(struct kvm_steal_time)))
2260                         return 1;
2261
2262                 vcpu->arch.st.msr_val = data;
2263
2264                 if (!(data & KVM_MSR_ENABLED))
2265                         break;
2266
2267                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2268
2269                 preempt_disable();
2270                 accumulate_steal_time(vcpu);
2271                 preempt_enable();
2272
2273                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2274
2275                 break;
2276         case MSR_KVM_PV_EOI_EN:
2277                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2278                         return 1;
2279                 break;
2280
2281         case MSR_IA32_MCG_CTL:
2282         case MSR_IA32_MCG_STATUS:
2283         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2284                 return set_msr_mce(vcpu, msr, data);
2285
2286         /* Performance counters are not protected by a CPUID bit,
2287          * so we should check all of them in the generic path for the sake of
2288          * cross vendor migration.
2289          * Writing a zero into the event select MSRs disables them,
2290          * which we perfectly emulate ;-). Any other value should be at least
2291          * reported, some guests depend on them.
2292          */
2293         case MSR_K7_EVNTSEL0:
2294         case MSR_K7_EVNTSEL1:
2295         case MSR_K7_EVNTSEL2:
2296         case MSR_K7_EVNTSEL3:
2297                 if (data != 0)
2298                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2299                                     "0x%x data 0x%llx\n", msr, data);
2300                 break;
2301         /* at least RHEL 4 unconditionally writes to the perfctr registers,
2302          * so we ignore writes to make it happy.
2303          */
2304         case MSR_K7_PERFCTR0:
2305         case MSR_K7_PERFCTR1:
2306         case MSR_K7_PERFCTR2:
2307         case MSR_K7_PERFCTR3:
2308                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2309                             "0x%x data 0x%llx\n", msr, data);
2310                 break;
2311         case MSR_P6_PERFCTR0:
2312         case MSR_P6_PERFCTR1:
2313                 pr = true;
2314         case MSR_P6_EVNTSEL0:
2315         case MSR_P6_EVNTSEL1:
2316                 if (kvm_pmu_msr(vcpu, msr))
2317                         return kvm_pmu_set_msr(vcpu, msr_info);
2318
2319                 if (pr || data != 0)
2320                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2321                                     "0x%x data 0x%llx\n", msr, data);
2322                 break;
2323         case MSR_K7_CLK_CTL:
2324                 /*
2325                  * Ignore all writes to this no longer documented MSR.
2326                  * Writes are only relevant for old K7 processors,
2327                  * all pre-dating SVM, but a recommended workaround from
2328                  * AMD for these chips. It is possible to specify the
2329                  * affected processor models on the command line, hence
2330                  * the need to ignore the workaround.
2331                  */
2332                 break;
2333         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2334                 if (kvm_hv_msr_partition_wide(msr)) {
2335                         int r;
2336                         mutex_lock(&vcpu->kvm->lock);
2337                         r = set_msr_hyperv_pw(vcpu, msr, data);
2338                         mutex_unlock(&vcpu->kvm->lock);
2339                         return r;
2340                 } else
2341                         return set_msr_hyperv(vcpu, msr, data);
2342                 break;
2343         case MSR_IA32_BBL_CR_CTL3:
2344                 /* Drop writes to this legacy MSR -- see rdmsr
2345                  * counterpart for further detail.
2346                  */
2347                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2348                 break;
2349         case MSR_AMD64_OSVW_ID_LENGTH:
2350                 if (!guest_cpuid_has_osvw(vcpu))
2351                         return 1;
2352                 vcpu->arch.osvw.length = data;
2353                 break;
2354         case MSR_AMD64_OSVW_STATUS:
2355                 if (!guest_cpuid_has_osvw(vcpu))
2356                         return 1;
2357                 vcpu->arch.osvw.status = data;
2358                 break;
2359         default:
2360                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2361                         return xen_hvm_config(vcpu, data);
2362                 if (kvm_pmu_msr(vcpu, msr))
2363                         return kvm_pmu_set_msr(vcpu, msr_info);
2364                 if (!ignore_msrs) {
2365                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2366                                     msr, data);
2367                         return 1;
2368                 } else {
2369                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2370                                     msr, data);
2371                         break;
2372                 }
2373         }
2374         return 0;
2375 }
2376 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2377
2378
2379 /*
2380  * Reads an msr value (of 'msr_index') into 'pdata'.
2381  * Returns 0 on success, non-0 otherwise.
2382  * Assumes vcpu_load() was already called.
2383  */
2384 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2385 {
2386         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2387 }
2388 EXPORT_SYMBOL_GPL(kvm_get_msr);
2389
2390 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2391 {
2392         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2393
2394         if (!msr_mtrr_valid(msr))
2395                 return 1;
2396
2397         if (msr == MSR_MTRRdefType)
2398                 *pdata = vcpu->arch.mtrr_state.def_type +
2399                          (vcpu->arch.mtrr_state.enabled << 10);
2400         else if (msr == MSR_MTRRfix64K_00000)
2401                 *pdata = p[0];
2402         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2403                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2404         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2405                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2406         else if (msr == MSR_IA32_CR_PAT)
2407                 *pdata = vcpu->arch.pat;
2408         else {  /* Variable MTRRs */
2409                 int idx, is_mtrr_mask;
2410                 u64 *pt;
2411
2412                 idx = (msr - 0x200) / 2;
2413                 is_mtrr_mask = msr - 0x200 - 2 * idx;
2414                 if (!is_mtrr_mask)
2415                         pt =
2416                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2417                 else
2418                         pt =
2419                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2420                 *pdata = *pt;
2421         }
2422
2423         return 0;
2424 }
2425
2426 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2427 {
2428         u64 data;
2429         u64 mcg_cap = vcpu->arch.mcg_cap;
2430         unsigned bank_num = mcg_cap & 0xff;
2431
2432         switch (msr) {
2433         case MSR_IA32_P5_MC_ADDR:
2434         case MSR_IA32_P5_MC_TYPE:
2435                 data = 0;
2436                 break;
2437         case MSR_IA32_MCG_CAP:
2438                 data = vcpu->arch.mcg_cap;
2439                 break;
2440         case MSR_IA32_MCG_CTL:
2441                 if (!(mcg_cap & MCG_CTL_P))
2442                         return 1;
2443                 data = vcpu->arch.mcg_ctl;
2444                 break;
2445         case MSR_IA32_MCG_STATUS:
2446                 data = vcpu->arch.mcg_status;
2447                 break;
2448         default:
2449                 if (msr >= MSR_IA32_MC0_CTL &&
2450                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2451                         u32 offset = msr - MSR_IA32_MC0_CTL;
2452                         data = vcpu->arch.mce_banks[offset];
2453                         break;
2454                 }
2455                 return 1;
2456         }
2457         *pdata = data;
2458         return 0;
2459 }
2460
2461 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2462 {
2463         u64 data = 0;
2464         struct kvm *kvm = vcpu->kvm;
2465
2466         switch (msr) {
2467         case HV_X64_MSR_GUEST_OS_ID:
2468                 data = kvm->arch.hv_guest_os_id;
2469                 break;
2470         case HV_X64_MSR_HYPERCALL:
2471                 data = kvm->arch.hv_hypercall;
2472                 break;
2473         case HV_X64_MSR_TIME_REF_COUNT: {
2474                 data =
2475                      div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2476                 break;
2477         }
2478         case HV_X64_MSR_REFERENCE_TSC:
2479                 data = kvm->arch.hv_tsc_page;
2480                 break;
2481         default:
2482                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2483                 return 1;
2484         }
2485
2486         *pdata = data;
2487         return 0;
2488 }
2489
2490 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2491 {
2492         u64 data = 0;
2493
2494         switch (msr) {
2495         case HV_X64_MSR_VP_INDEX: {
2496                 int r;
2497                 struct kvm_vcpu *v;
2498                 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2499                         if (v == vcpu) {
2500                                 data = r;
2501                                 break;
2502                         }
2503                 }
2504                 break;
2505         }
2506         case HV_X64_MSR_EOI:
2507                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2508         case HV_X64_MSR_ICR:
2509                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2510         case HV_X64_MSR_TPR:
2511                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2512         case HV_X64_MSR_APIC_ASSIST_PAGE:
2513                 data = vcpu->arch.hv_vapic;
2514                 break;
2515         default:
2516                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2517                 return 1;
2518         }
2519         *pdata = data;
2520         return 0;
2521 }
2522
2523 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2524 {
2525         u64 data;
2526
2527         switch (msr) {
2528         case MSR_IA32_PLATFORM_ID:
2529         case MSR_IA32_EBL_CR_POWERON:
2530         case MSR_IA32_DEBUGCTLMSR:
2531         case MSR_IA32_LASTBRANCHFROMIP:
2532         case MSR_IA32_LASTBRANCHTOIP:
2533         case MSR_IA32_LASTINTFROMIP:
2534         case MSR_IA32_LASTINTTOIP:
2535         case MSR_K8_SYSCFG:
2536         case MSR_K7_HWCR:
2537         case MSR_VM_HSAVE_PA:
2538         case MSR_K7_EVNTSEL0:
2539         case MSR_K7_EVNTSEL1:
2540         case MSR_K7_EVNTSEL2:
2541         case MSR_K7_EVNTSEL3:
2542         case MSR_K7_PERFCTR0:
2543         case MSR_K7_PERFCTR1:
2544         case MSR_K7_PERFCTR2:
2545         case MSR_K7_PERFCTR3:
2546         case MSR_K8_INT_PENDING_MSG:
2547         case MSR_AMD64_NB_CFG:
2548         case MSR_FAM10H_MMIO_CONF_BASE:
2549         case MSR_AMD64_BU_CFG2:
2550                 data = 0;
2551                 break;
2552         case MSR_P6_PERFCTR0:
2553         case MSR_P6_PERFCTR1:
2554         case MSR_P6_EVNTSEL0:
2555         case MSR_P6_EVNTSEL1:
2556                 if (kvm_pmu_msr(vcpu, msr))
2557                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2558                 data = 0;
2559                 break;
2560         case MSR_IA32_UCODE_REV:
2561                 data = 0x100000000ULL;
2562                 break;
2563         case MSR_MTRRcap:
2564                 data = 0x500 | KVM_NR_VAR_MTRR;
2565                 break;
2566         case 0x200 ... 0x2ff:
2567                 return get_msr_mtrr(vcpu, msr, pdata);
2568         case 0xcd: /* fsb frequency */
2569                 data = 3;
2570                 break;
2571                 /*
2572                  * MSR_EBC_FREQUENCY_ID
2573                  * Conservative value valid for even the basic CPU models.
2574                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2575                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2576                  * and 266MHz for model 3, or 4. Set Core Clock
2577                  * Frequency to System Bus Frequency Ratio to 1 (bits
2578                  * 31:24) even though these are only valid for CPU
2579                  * models > 2, however guests may end up dividing or
2580                  * multiplying by zero otherwise.
2581                  */
2582         case MSR_EBC_FREQUENCY_ID:
2583                 data = 1 << 24;
2584                 break;
2585         case MSR_IA32_APICBASE:
2586                 data = kvm_get_apic_base(vcpu);
2587                 break;
2588         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2589                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2590                 break;
2591         case MSR_IA32_TSCDEADLINE:
2592                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2593                 break;
2594         case MSR_IA32_TSC_ADJUST:
2595                 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2596                 break;
2597         case MSR_IA32_MISC_ENABLE:
2598                 data = vcpu->arch.ia32_misc_enable_msr;
2599                 break;
2600         case MSR_IA32_PERF_STATUS:
2601                 /* TSC increment by tick */
2602                 data = 1000ULL;
2603                 /* CPU multiplier */
2604                 data |= (((uint64_t)4ULL) << 40);
2605                 break;
2606         case MSR_EFER:
2607                 data = vcpu->arch.efer;
2608                 break;
2609         case MSR_KVM_WALL_CLOCK:
2610         case MSR_KVM_WALL_CLOCK_NEW:
2611                 data = vcpu->kvm->arch.wall_clock;
2612                 break;
2613         case MSR_KVM_SYSTEM_TIME:
2614         case MSR_KVM_SYSTEM_TIME_NEW:
2615                 data = vcpu->arch.time;
2616                 break;
2617         case MSR_KVM_ASYNC_PF_EN:
2618                 data = vcpu->arch.apf.msr_val;
2619                 break;
2620         case MSR_KVM_STEAL_TIME:
2621                 data = vcpu->arch.st.msr_val;
2622                 break;
2623         case MSR_KVM_PV_EOI_EN:
2624                 data = vcpu->arch.pv_eoi.msr_val;
2625                 break;
2626         case MSR_IA32_P5_MC_ADDR:
2627         case MSR_IA32_P5_MC_TYPE:
2628         case MSR_IA32_MCG_CAP:
2629         case MSR_IA32_MCG_CTL:
2630         case MSR_IA32_MCG_STATUS:
2631         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2632                 return get_msr_mce(vcpu, msr, pdata);
2633         case MSR_K7_CLK_CTL:
2634                 /*
2635                  * Provide expected ramp-up count for K7. All other
2636                  * are set to zero, indicating minimum divisors for
2637                  * every field.
2638                  *
2639                  * This prevents guest kernels on AMD host with CPU
2640                  * type 6, model 8 and higher from exploding due to
2641                  * the rdmsr failing.
2642                  */
2643                 data = 0x20000000;
2644                 break;
2645         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2646                 if (kvm_hv_msr_partition_wide(msr)) {
2647                         int r;
2648                         mutex_lock(&vcpu->kvm->lock);
2649                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2650                         mutex_unlock(&vcpu->kvm->lock);
2651                         return r;
2652                 } else
2653                         return get_msr_hyperv(vcpu, msr, pdata);
2654                 break;
2655         case MSR_IA32_BBL_CR_CTL3:
2656                 /* This legacy MSR exists but isn't fully documented in current
2657                  * silicon.  It is however accessed by winxp in very narrow
2658                  * scenarios where it sets bit #19, itself documented as
2659                  * a "reserved" bit.  Best effort attempt to source coherent
2660                  * read data here should the balance of the register be
2661                  * interpreted by the guest:
2662                  *
2663                  * L2 cache control register 3: 64GB range, 256KB size,
2664                  * enabled, latency 0x1, configured
2665                  */
2666                 data = 0xbe702111;
2667                 break;
2668         case MSR_AMD64_OSVW_ID_LENGTH:
2669                 if (!guest_cpuid_has_osvw(vcpu))
2670                         return 1;
2671                 data = vcpu->arch.osvw.length;
2672                 break;
2673         case MSR_AMD64_OSVW_STATUS:
2674                 if (!guest_cpuid_has_osvw(vcpu))
2675                         return 1;
2676                 data = vcpu->arch.osvw.status;
2677                 break;
2678         default:
2679                 if (kvm_pmu_msr(vcpu, msr))
2680                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2681                 if (!ignore_msrs) {
2682                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2683                         return 1;
2684                 } else {
2685                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2686                         data = 0;
2687                 }
2688                 break;
2689         }
2690         *pdata = data;
2691         return 0;
2692 }
2693 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2694
2695 /*
2696  * Read or write a bunch of msrs. All parameters are kernel addresses.
2697  *
2698  * @return number of msrs set successfully.
2699  */
2700 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2701                     struct kvm_msr_entry *entries,
2702                     int (*do_msr)(struct kvm_vcpu *vcpu,
2703                                   unsigned index, u64 *data))
2704 {
2705         int i, idx;
2706
2707         idx = srcu_read_lock(&vcpu->kvm->srcu);
2708         for (i = 0; i < msrs->nmsrs; ++i)
2709                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2710                         break;
2711         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2712
2713         return i;
2714 }
2715
2716 /*
2717  * Read or write a bunch of msrs. Parameters are user addresses.
2718  *
2719  * @return number of msrs set successfully.
2720  */
2721 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2722                   int (*do_msr)(struct kvm_vcpu *vcpu,
2723                                 unsigned index, u64 *data),
2724                   int writeback)
2725 {
2726         struct kvm_msrs msrs;
2727         struct kvm_msr_entry *entries;
2728         int r, n;
2729         unsigned size;
2730
2731         r = -EFAULT;
2732         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2733                 goto out;
2734
2735         r = -E2BIG;
2736         if (msrs.nmsrs >= MAX_IO_MSRS)
2737                 goto out;
2738
2739         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2740         entries = memdup_user(user_msrs->entries, size);
2741         if (IS_ERR(entries)) {
2742                 r = PTR_ERR(entries);
2743                 goto out;
2744         }
2745
2746         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2747         if (r < 0)
2748                 goto out_free;
2749
2750         r = -EFAULT;
2751         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2752                 goto out_free;
2753
2754         r = n;
2755
2756 out_free:
2757         kfree(entries);
2758 out:
2759         return r;
2760 }
2761
2762 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2763 {
2764         int r;
2765
2766         switch (ext) {
2767         case KVM_CAP_IRQCHIP:
2768         case KVM_CAP_HLT:
2769         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2770         case KVM_CAP_SET_TSS_ADDR:
2771         case KVM_CAP_EXT_CPUID:
2772         case KVM_CAP_EXT_EMUL_CPUID:
2773         case KVM_CAP_CLOCKSOURCE:
2774         case KVM_CAP_PIT:
2775         case KVM_CAP_NOP_IO_DELAY:
2776         case KVM_CAP_MP_STATE:
2777         case KVM_CAP_SYNC_MMU:
2778         case KVM_CAP_USER_NMI:
2779         case KVM_CAP_REINJECT_CONTROL:
2780         case KVM_CAP_IRQ_INJECT_STATUS:
2781         case KVM_CAP_IOEVENTFD:
2782         case KVM_CAP_IOEVENTFD_NO_LENGTH:
2783         case KVM_CAP_PIT2:
2784         case KVM_CAP_PIT_STATE2:
2785         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2786         case KVM_CAP_XEN_HVM:
2787         case KVM_CAP_ADJUST_CLOCK:
2788         case KVM_CAP_VCPU_EVENTS:
2789         case KVM_CAP_HYPERV:
2790         case KVM_CAP_HYPERV_VAPIC:
2791         case KVM_CAP_HYPERV_SPIN:
2792         case KVM_CAP_PCI_SEGMENT:
2793         case KVM_CAP_DEBUGREGS:
2794         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2795         case KVM_CAP_XSAVE:
2796         case KVM_CAP_ASYNC_PF:
2797         case KVM_CAP_GET_TSC_KHZ:
2798         case KVM_CAP_KVMCLOCK_CTRL:
2799         case KVM_CAP_READONLY_MEM:
2800         case KVM_CAP_HYPERV_TIME:
2801         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2802         case KVM_CAP_TSC_DEADLINE_TIMER:
2803 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2804         case KVM_CAP_ASSIGN_DEV_IRQ:
2805         case KVM_CAP_PCI_2_3:
2806 #endif
2807                 r = 1;
2808                 break;
2809         case KVM_CAP_COALESCED_MMIO:
2810                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2811                 break;
2812         case KVM_CAP_VAPIC:
2813                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2814                 break;
2815         case KVM_CAP_NR_VCPUS:
2816                 r = KVM_SOFT_MAX_VCPUS;
2817                 break;
2818         case KVM_CAP_MAX_VCPUS:
2819                 r = KVM_MAX_VCPUS;
2820                 break;
2821         case KVM_CAP_NR_MEMSLOTS:
2822                 r = KVM_USER_MEM_SLOTS;
2823                 break;
2824         case KVM_CAP_PV_MMU:    /* obsolete */
2825                 r = 0;
2826                 break;
2827 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2828         case KVM_CAP_IOMMU:
2829                 r = iommu_present(&pci_bus_type);
2830                 break;
2831 #endif
2832         case KVM_CAP_MCE:
2833                 r = KVM_MAX_MCE_BANKS;
2834                 break;
2835         case KVM_CAP_XCRS:
2836                 r = cpu_has_xsave;
2837                 break;
2838         case KVM_CAP_TSC_CONTROL:
2839                 r = kvm_has_tsc_control;
2840                 break;
2841         default:
2842                 r = 0;
2843                 break;
2844         }
2845         return r;
2846
2847 }
2848
2849 long kvm_arch_dev_ioctl(struct file *filp,
2850                         unsigned int ioctl, unsigned long arg)
2851 {
2852         void __user *argp = (void __user *)arg;
2853         long r;
2854
2855         switch (ioctl) {
2856         case KVM_GET_MSR_INDEX_LIST: {
2857                 struct kvm_msr_list __user *user_msr_list = argp;
2858                 struct kvm_msr_list msr_list;
2859                 unsigned n;
2860
2861                 r = -EFAULT;
2862                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2863                         goto out;
2864                 n = msr_list.nmsrs;
2865                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2866                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2867                         goto out;
2868                 r = -E2BIG;
2869                 if (n < msr_list.nmsrs)
2870                         goto out;
2871                 r = -EFAULT;
2872                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2873                                  num_msrs_to_save * sizeof(u32)))
2874                         goto out;
2875                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2876                                  &emulated_msrs,
2877                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2878                         goto out;
2879                 r = 0;
2880                 break;
2881         }
2882         case KVM_GET_SUPPORTED_CPUID:
2883         case KVM_GET_EMULATED_CPUID: {
2884                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2885                 struct kvm_cpuid2 cpuid;
2886
2887                 r = -EFAULT;
2888                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2889                         goto out;
2890
2891                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2892                                             ioctl);
2893                 if (r)
2894                         goto out;
2895
2896                 r = -EFAULT;
2897                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2898                         goto out;
2899                 r = 0;
2900                 break;
2901         }
2902         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2903                 u64 mce_cap;
2904
2905                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2906                 r = -EFAULT;
2907                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2908                         goto out;
2909                 r = 0;
2910                 break;
2911         }
2912         default:
2913                 r = -EINVAL;
2914         }
2915 out:
2916         return r;
2917 }
2918
2919 static void wbinvd_ipi(void *garbage)
2920 {
2921         wbinvd();
2922 }
2923
2924 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2925 {
2926         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2927 }
2928
2929 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2930 {
2931         /* Address WBINVD may be executed by guest */
2932         if (need_emulate_wbinvd(vcpu)) {
2933                 if (kvm_x86_ops->has_wbinvd_exit())
2934                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2935                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2936                         smp_call_function_single(vcpu->cpu,
2937                                         wbinvd_ipi, NULL, 1);
2938         }
2939
2940         kvm_x86_ops->vcpu_load(vcpu, cpu);
2941
2942         /* Apply any externally detected TSC adjustments (due to suspend) */
2943         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2944                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2945                 vcpu->arch.tsc_offset_adjustment = 0;
2946                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2947         }
2948
2949         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2950                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2951                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2952                 if (tsc_delta < 0)
2953                         mark_tsc_unstable("KVM discovered backwards TSC");
2954                 if (check_tsc_unstable()) {
2955                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2956                                                 vcpu->arch.last_guest_tsc);
2957                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2958                         vcpu->arch.tsc_catchup = 1;
2959                 }
2960                 /*
2961                  * On a host with synchronized TSC, there is no need to update
2962                  * kvmclock on vcpu->cpu migration
2963                  */
2964                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2965                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2966                 if (vcpu->cpu != cpu)
2967                         kvm_migrate_timers(vcpu);
2968                 vcpu->cpu = cpu;
2969         }
2970
2971         accumulate_steal_time(vcpu);
2972         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2973 }
2974
2975 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2976 {
2977         kvm_x86_ops->vcpu_put(vcpu);
2978         kvm_put_guest_fpu(vcpu);
2979         vcpu->arch.last_host_tsc = native_read_tsc();
2980 }
2981
2982 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2983                                     struct kvm_lapic_state *s)
2984 {
2985         kvm_x86_ops->sync_pir_to_irr(vcpu);
2986         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2987
2988         return 0;
2989 }
2990
2991 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2992                                     struct kvm_lapic_state *s)
2993 {
2994         kvm_apic_post_state_restore(vcpu, s);
2995         update_cr8_intercept(vcpu);
2996
2997         return 0;
2998 }
2999
3000 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3001                                     struct kvm_interrupt *irq)
3002 {
3003         if (irq->irq >= KVM_NR_INTERRUPTS)
3004                 return -EINVAL;
3005         if (irqchip_in_kernel(vcpu->kvm))
3006                 return -ENXIO;
3007
3008         kvm_queue_interrupt(vcpu, irq->irq, false);
3009         kvm_make_request(KVM_REQ_EVENT, vcpu);
3010
3011         return 0;
3012 }
3013
3014 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3015 {
3016         kvm_inject_nmi(vcpu);
3017
3018         return 0;
3019 }
3020
3021 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3022                                            struct kvm_tpr_access_ctl *tac)
3023 {
3024         if (tac->flags)
3025                 return -EINVAL;
3026         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3027         return 0;
3028 }
3029
3030 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3031                                         u64 mcg_cap)
3032 {
3033         int r;
3034         unsigned bank_num = mcg_cap & 0xff, bank;
3035
3036         r = -EINVAL;
3037         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3038                 goto out;
3039         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3040                 goto out;
3041         r = 0;
3042         vcpu->arch.mcg_cap = mcg_cap;
3043         /* Init IA32_MCG_CTL to all 1s */
3044         if (mcg_cap & MCG_CTL_P)
3045                 vcpu->arch.mcg_ctl = ~(u64)0;
3046         /* Init IA32_MCi_CTL to all 1s */
3047         for (bank = 0; bank < bank_num; bank++)
3048                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3049 out:
3050         return r;
3051 }
3052
3053 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3054                                       struct kvm_x86_mce *mce)
3055 {
3056         u64 mcg_cap = vcpu->arch.mcg_cap;
3057         unsigned bank_num = mcg_cap & 0xff;
3058         u64 *banks = vcpu->arch.mce_banks;
3059
3060         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3061                 return -EINVAL;
3062         /*
3063          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3064          * reporting is disabled
3065          */
3066         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3067             vcpu->arch.mcg_ctl != ~(u64)0)
3068                 return 0;
3069         banks += 4 * mce->bank;
3070         /*
3071          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3072          * reporting is disabled for the bank
3073          */
3074         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3075                 return 0;
3076         if (mce->status & MCI_STATUS_UC) {
3077                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3078                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3079                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3080                         return 0;
3081                 }
3082                 if (banks[1] & MCI_STATUS_VAL)
3083                         mce->status |= MCI_STATUS_OVER;
3084                 banks[2] = mce->addr;
3085                 banks[3] = mce->misc;
3086                 vcpu->arch.mcg_status = mce->mcg_status;
3087                 banks[1] = mce->status;
3088                 kvm_queue_exception(vcpu, MC_VECTOR);
3089         } else if (!(banks[1] & MCI_STATUS_VAL)
3090                    || !(banks[1] & MCI_STATUS_UC)) {
3091                 if (banks[1] & MCI_STATUS_VAL)
3092                         mce->status |= MCI_STATUS_OVER;
3093                 banks[2] = mce->addr;
3094                 banks[3] = mce->misc;
3095                 banks[1] = mce->status;
3096         } else
3097                 banks[1] |= MCI_STATUS_OVER;
3098         return 0;
3099 }
3100
3101 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3102                                                struct kvm_vcpu_events *events)
3103 {
3104         process_nmi(vcpu);
3105         events->exception.injected =
3106                 vcpu->arch.exception.pending &&
3107                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3108         events->exception.nr = vcpu->arch.exception.nr;
3109         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3110         events->exception.pad = 0;
3111         events->exception.error_code = vcpu->arch.exception.error_code;
3112
3113         events->interrupt.injected =
3114                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3115         events->interrupt.nr = vcpu->arch.interrupt.nr;
3116         events->interrupt.soft = 0;
3117         events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3118
3119         events->nmi.injected = vcpu->arch.nmi_injected;
3120         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3121         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3122         events->nmi.pad = 0;
3123
3124         events->sipi_vector = 0; /* never valid when reporting to user space */
3125
3126         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3127                          | KVM_VCPUEVENT_VALID_SHADOW);
3128         memset(&events->reserved, 0, sizeof(events->reserved));
3129 }
3130
3131 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3132                                               struct kvm_vcpu_events *events)
3133 {
3134         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3135                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3136                               | KVM_VCPUEVENT_VALID_SHADOW))
3137                 return -EINVAL;
3138
3139         process_nmi(vcpu);
3140         vcpu->arch.exception.pending = events->exception.injected;
3141         vcpu->arch.exception.nr = events->exception.nr;
3142         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3143         vcpu->arch.exception.error_code = events->exception.error_code;
3144
3145         vcpu->arch.interrupt.pending = events->interrupt.injected;
3146         vcpu->arch.interrupt.nr = events->interrupt.nr;
3147         vcpu->arch.interrupt.soft = events->interrupt.soft;
3148         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3149                 kvm_x86_ops->set_interrupt_shadow(vcpu,
3150                                                   events->interrupt.shadow);
3151
3152         vcpu->arch.nmi_injected = events->nmi.injected;
3153         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3154                 vcpu->arch.nmi_pending = events->nmi.pending;
3155         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3156
3157         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3158             kvm_vcpu_has_lapic(vcpu))
3159                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3160
3161         kvm_make_request(KVM_REQ_EVENT, vcpu);
3162
3163         return 0;
3164 }
3165
3166 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3167                                              struct kvm_debugregs *dbgregs)
3168 {
3169         unsigned long val;
3170
3171         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3172         kvm_get_dr(vcpu, 6, &val);
3173         dbgregs->dr6 = val;
3174         dbgregs->dr7 = vcpu->arch.dr7;
3175         dbgregs->flags = 0;
3176         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3177 }
3178
3179 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3180                                             struct kvm_debugregs *dbgregs)
3181 {
3182         if (dbgregs->flags)
3183                 return -EINVAL;
3184
3185         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3186         kvm_update_dr0123(vcpu);
3187         vcpu->arch.dr6 = dbgregs->dr6;
3188         kvm_update_dr6(vcpu);
3189         vcpu->arch.dr7 = dbgregs->dr7;
3190         kvm_update_dr7(vcpu);
3191
3192         return 0;
3193 }
3194
3195 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3196
3197 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3198 {
3199         struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3200         u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3201         u64 valid;
3202
3203         /*
3204          * Copy legacy XSAVE area, to avoid complications with CPUID
3205          * leaves 0 and 1 in the loop below.
3206          */
3207         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3208
3209         /* Set XSTATE_BV */
3210         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3211
3212         /*
3213          * Copy each region from the possibly compacted offset to the
3214          * non-compacted offset.
3215          */
3216         valid = xstate_bv & ~XSTATE_FPSSE;
3217         while (valid) {
3218                 u64 feature = valid & -valid;
3219                 int index = fls64(feature) - 1;
3220                 void *src = get_xsave_addr(xsave, feature);
3221
3222                 if (src) {
3223                         u32 size, offset, ecx, edx;
3224                         cpuid_count(XSTATE_CPUID, index,
3225                                     &size, &offset, &ecx, &edx);
3226                         memcpy(dest + offset, src, size);
3227                 }
3228
3229                 valid -= feature;
3230         }
3231 }
3232
3233 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3234 {
3235         struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3236         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3237         u64 valid;
3238
3239         /*
3240          * Copy legacy XSAVE area, to avoid complications with CPUID
3241          * leaves 0 and 1 in the loop below.
3242          */
3243         memcpy(xsave, src, XSAVE_HDR_OFFSET);
3244
3245         /* Set XSTATE_BV and possibly XCOMP_BV.  */
3246         xsave->xsave_hdr.xstate_bv = xstate_bv;
3247         if (cpu_has_xsaves)
3248                 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3249
3250         /*
3251          * Copy each region from the non-compacted offset to the
3252          * possibly compacted offset.
3253          */
3254         valid = xstate_bv & ~XSTATE_FPSSE;
3255         while (valid) {
3256                 u64 feature = valid & -valid;
3257                 int index = fls64(feature) - 1;
3258                 void *dest = get_xsave_addr(xsave, feature);
3259
3260                 if (dest) {
3261                         u32 size, offset, ecx, edx;
3262                         cpuid_count(XSTATE_CPUID, index,
3263                                     &size, &offset, &ecx, &edx);
3264                         memcpy(dest, src + offset, size);
3265                 } else
3266                         WARN_ON_ONCE(1);
3267
3268                 valid -= feature;
3269         }
3270 }
3271
3272 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3273                                          struct kvm_xsave *guest_xsave)
3274 {
3275         if (cpu_has_xsave) {
3276                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3277                 fill_xsave((u8 *) guest_xsave->region, vcpu);
3278         } else {
3279                 memcpy(guest_xsave->region,
3280                         &vcpu->arch.guest_fpu.state->fxsave,
3281                         sizeof(struct i387_fxsave_struct));
3282                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3283                         XSTATE_FPSSE;
3284         }
3285 }
3286
3287 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3288                                         struct kvm_xsave *guest_xsave)
3289 {
3290         u64 xstate_bv =
3291                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3292
3293         if (cpu_has_xsave) {
3294                 /*
3295                  * Here we allow setting states that are not present in
3296                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3297                  * with old userspace.
3298                  */
3299                 if (xstate_bv & ~kvm_supported_xcr0())
3300                         return -EINVAL;
3301                 load_xsave(vcpu, (u8 *)guest_xsave->region);
3302         } else {
3303                 if (xstate_bv & ~XSTATE_FPSSE)
3304                         return -EINVAL;
3305                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3306                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
3307         }
3308         return 0;
3309 }
3310
3311 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3312                                         struct kvm_xcrs *guest_xcrs)
3313 {
3314         if (!cpu_has_xsave) {
3315                 guest_xcrs->nr_xcrs = 0;
3316                 return;
3317         }
3318
3319         guest_xcrs->nr_xcrs = 1;
3320         guest_xcrs->flags = 0;
3321         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3322         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3323 }
3324
3325 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3326                                        struct kvm_xcrs *guest_xcrs)
3327 {
3328         int i, r = 0;
3329
3330         if (!cpu_has_xsave)
3331                 return -EINVAL;
3332
3333         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3334                 return -EINVAL;
3335
3336         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3337                 /* Only support XCR0 currently */
3338                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3339                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3340                                 guest_xcrs->xcrs[i].value);
3341                         break;
3342                 }
3343         if (r)
3344                 r = -EINVAL;
3345         return r;
3346 }
3347
3348 /*
3349  * kvm_set_guest_paused() indicates to the guest kernel that it has been
3350  * stopped by the hypervisor.  This function will be called from the host only.
3351  * EINVAL is returned when the host attempts to set the flag for a guest that
3352  * does not support pv clocks.
3353  */
3354 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3355 {
3356         if (!vcpu->arch.pv_time_enabled)
3357                 return -EINVAL;
3358         vcpu->arch.pvclock_set_guest_stopped_request = true;
3359         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3360         return 0;
3361 }
3362
3363 long kvm_arch_vcpu_ioctl(struct file *filp,
3364                          unsigned int ioctl, unsigned long arg)
3365 {
3366         struct kvm_vcpu *vcpu = filp->private_data;
3367         void __user *argp = (void __user *)arg;
3368         int r;
3369         union {
3370                 struct kvm_lapic_state *lapic;
3371                 struct kvm_xsave *xsave;
3372                 struct kvm_xcrs *xcrs;
3373                 void *buffer;
3374         } u;
3375
3376         u.buffer = NULL;
3377         switch (ioctl) {
3378         case KVM_GET_LAPIC: {
3379                 r = -EINVAL;
3380                 if (!vcpu->arch.apic)
3381                         goto out;
3382                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3383
3384                 r = -ENOMEM;
3385                 if (!u.lapic)
3386                         goto out;
3387                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3388                 if (r)
3389                         goto out;
3390                 r = -EFAULT;
3391                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3392                         goto out;
3393                 r = 0;
3394                 break;
3395         }
3396         case KVM_SET_LAPIC: {
3397                 r = -EINVAL;
3398                 if (!vcpu->arch.apic)
3399                         goto out;
3400                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3401                 if (IS_ERR(u.lapic))
3402                         return PTR_ERR(u.lapic);
3403
3404                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3405                 break;
3406         }
3407         case KVM_INTERRUPT: {
3408                 struct kvm_interrupt irq;
3409
3410                 r = -EFAULT;
3411                 if (copy_from_user(&irq, argp, sizeof irq))
3412                         goto out;
3413                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3414                 break;
3415         }
3416         case KVM_NMI: {
3417                 r = kvm_vcpu_ioctl_nmi(vcpu);
3418                 break;
3419         }
3420         case KVM_SET_CPUID: {
3421                 struct kvm_cpuid __user *cpuid_arg = argp;
3422                 struct kvm_cpuid cpuid;
3423
3424                 r = -EFAULT;
3425                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3426                         goto out;
3427                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3428                 break;
3429         }
3430         case KVM_SET_CPUID2: {
3431                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3432                 struct kvm_cpuid2 cpuid;
3433
3434                 r = -EFAULT;
3435                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3436                         goto out;
3437                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3438                                               cpuid_arg->entries);
3439                 break;
3440         }
3441         case KVM_GET_CPUID2: {
3442                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3443                 struct kvm_cpuid2 cpuid;
3444
3445                 r = -EFAULT;
3446                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3447                         goto out;
3448                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3449                                               cpuid_arg->entries);
3450                 if (r)
3451                         goto out;
3452                 r = -EFAULT;
3453                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3454                         goto out;
3455                 r = 0;
3456                 break;
3457         }
3458         case KVM_GET_MSRS:
3459                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3460                 break;
3461         case KVM_SET_MSRS:
3462                 r = msr_io(vcpu, argp, do_set_msr, 0);
3463                 break;
3464         case KVM_TPR_ACCESS_REPORTING: {
3465                 struct kvm_tpr_access_ctl tac;
3466
3467                 r = -EFAULT;
3468                 if (copy_from_user(&tac, argp, sizeof tac))
3469                         goto out;
3470                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3471                 if (r)
3472                         goto out;
3473                 r = -EFAULT;
3474                 if (copy_to_user(argp, &tac, sizeof tac))
3475                         goto out;
3476                 r = 0;
3477                 break;
3478         };
3479         case KVM_SET_VAPIC_ADDR: {
3480                 struct kvm_vapic_addr va;
3481
3482                 r = -EINVAL;
3483                 if (!irqchip_in_kernel(vcpu->kvm))
3484                         goto out;
3485                 r = -EFAULT;
3486                 if (copy_from_user(&va, argp, sizeof va))
3487                         goto out;
3488                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3489                 break;
3490         }
3491         case KVM_X86_SETUP_MCE: {
3492                 u64 mcg_cap;
3493
3494                 r = -EFAULT;
3495                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3496                         goto out;
3497                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3498                 break;
3499         }
3500         case KVM_X86_SET_MCE: {
3501                 struct kvm_x86_mce mce;
3502
3503                 r = -EFAULT;
3504                 if (copy_from_user(&mce, argp, sizeof mce))
3505                         goto out;
3506                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3507                 break;
3508         }
3509         case KVM_GET_VCPU_EVENTS: {
3510                 struct kvm_vcpu_events events;
3511
3512                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3513
3514                 r = -EFAULT;
3515                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3516                         break;
3517                 r = 0;
3518                 break;
3519         }
3520         case KVM_SET_VCPU_EVENTS: {
3521                 struct kvm_vcpu_events events;
3522
3523                 r = -EFAULT;
3524                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3525                         break;
3526
3527                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3528                 break;
3529         }
3530         case KVM_GET_DEBUGREGS: {
3531                 struct kvm_debugregs dbgregs;
3532
3533                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3534
3535                 r = -EFAULT;
3536                 if (copy_to_user(argp, &dbgregs,
3537                                  sizeof(struct kvm_debugregs)))
3538                         break;
3539                 r = 0;
3540                 break;
3541         }
3542         case KVM_SET_DEBUGREGS: {
3543                 struct kvm_debugregs dbgregs;
3544
3545                 r = -EFAULT;
3546                 if (copy_from_user(&dbgregs, argp,
3547                                    sizeof(struct kvm_debugregs)))
3548                         break;
3549
3550                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3551                 break;
3552         }
3553         case KVM_GET_XSAVE: {
3554                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3555                 r = -ENOMEM;
3556                 if (!u.xsave)
3557                         break;
3558
3559                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3560
3561                 r = -EFAULT;
3562                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3563                         break;
3564                 r = 0;
3565                 break;
3566         }
3567         case KVM_SET_XSAVE: {
3568                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3569                 if (IS_ERR(u.xsave))
3570                         return PTR_ERR(u.xsave);
3571
3572                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3573                 break;
3574         }
3575         case KVM_GET_XCRS: {
3576                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3577                 r = -ENOMEM;
3578                 if (!u.xcrs)
3579                         break;
3580
3581                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3582
3583                 r = -EFAULT;
3584                 if (copy_to_user(argp, u.xcrs,
3585                                  sizeof(struct kvm_xcrs)))
3586                         break;
3587                 r = 0;
3588                 break;
3589         }
3590         case KVM_SET_XCRS: {
3591                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3592                 if (IS_ERR(u.xcrs))
3593                         return PTR_ERR(u.xcrs);
3594
3595                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3596                 break;
3597         }
3598         case KVM_SET_TSC_KHZ: {
3599                 u32 user_tsc_khz;
3600
3601                 r = -EINVAL;
3602                 user_tsc_khz = (u32)arg;
3603
3604                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3605                         goto out;
3606
3607                 if (user_tsc_khz == 0)
3608                         user_tsc_khz = tsc_khz;
3609
3610                 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3611
3612                 r = 0;
3613                 goto out;
3614         }
3615         case KVM_GET_TSC_KHZ: {
3616                 r = vcpu->arch.virtual_tsc_khz;
3617                 goto out;
3618         }
3619         case KVM_KVMCLOCK_CTRL: {
3620                 r = kvm_set_guest_paused(vcpu);
3621                 goto out;
3622         }
3623         default:
3624                 r = -EINVAL;
3625         }
3626 out:
3627         kfree(u.buffer);
3628         return r;
3629 }
3630
3631 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3632 {
3633         return VM_FAULT_SIGBUS;
3634 }
3635
3636 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3637 {
3638         int ret;
3639
3640         if (addr > (unsigned int)(-3 * PAGE_SIZE))
3641                 return -EINVAL;
3642         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3643         return ret;
3644 }
3645
3646 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3647                                               u64 ident_addr)
3648 {
3649         kvm->arch.ept_identity_map_addr = ident_addr;
3650         return 0;
3651 }
3652
3653 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3654                                           u32 kvm_nr_mmu_pages)
3655 {
3656         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3657                 return -EINVAL;
3658
3659         mutex_lock(&kvm->slots_lock);
3660
3661         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3662         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3663
3664         mutex_unlock(&kvm->slots_lock);
3665         return 0;
3666 }
3667
3668 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3669 {
3670         return kvm->arch.n_max_mmu_pages;
3671 }
3672
3673 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3674 {
3675         int r;
3676
3677         r = 0;
3678         switch (chip->chip_id) {
3679         case KVM_IRQCHIP_PIC_MASTER:
3680                 memcpy(&chip->chip.pic,
3681                         &pic_irqchip(kvm)->pics[0],
3682                         sizeof(struct kvm_pic_state));
3683                 break;
3684         case KVM_IRQCHIP_PIC_SLAVE:
3685                 memcpy(&chip->chip.pic,
3686                         &pic_irqchip(kvm)->pics[1],
3687                         sizeof(struct kvm_pic_state));
3688                 break;
3689         case KVM_IRQCHIP_IOAPIC:
3690                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3691                 break;
3692         default:
3693                 r = -EINVAL;
3694                 break;
3695         }
3696         return r;
3697 }
3698
3699 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3700 {
3701         int r;
3702
3703         r = 0;
3704         switch (chip->chip_id) {
3705         case KVM_IRQCHIP_PIC_MASTER:
3706                 spin_lock(&pic_irqchip(kvm)->lock);
3707                 memcpy(&pic_irqchip(kvm)->pics[0],
3708                         &chip->chip.pic,
3709                         sizeof(struct kvm_pic_state));
3710                 spin_unlock(&pic_irqchip(kvm)->lock);
3711                 break;
3712         case KVM_IRQCHIP_PIC_SLAVE:
3713                 spin_lock(&pic_irqchip(kvm)->lock);
3714                 memcpy(&pic_irqchip(kvm)->pics[1],
3715                         &chip->chip.pic,
3716                         sizeof(struct kvm_pic_state));
3717                 spin_unlock(&pic_irqchip(kvm)->lock);
3718                 break;
3719         case KVM_IRQCHIP_IOAPIC:
3720                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3721                 break;
3722         default:
3723                 r = -EINVAL;
3724                 break;
3725         }
3726         kvm_pic_update_irq(pic_irqchip(kvm));
3727         return r;
3728 }
3729
3730 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3731 {
3732         int r = 0;
3733
3734         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3735         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3736         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3737         return r;
3738 }
3739
3740 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3741 {
3742         int r = 0;
3743
3744         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3745         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3746         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3747         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3748         return r;
3749 }
3750
3751 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3752 {
3753         int r = 0;
3754
3755         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3756         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3757                 sizeof(ps->channels));
3758         ps->flags = kvm->arch.vpit->pit_state.flags;
3759         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3760         memset(&ps->reserved, 0, sizeof(ps->reserved));
3761         return r;
3762 }
3763
3764 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3765 {
3766         int r = 0, start = 0;
3767         u32 prev_legacy, cur_legacy;
3768         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3769         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3770         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3771         if (!prev_legacy && cur_legacy)
3772                 start = 1;
3773         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3774                sizeof(kvm->arch.vpit->pit_state.channels));
3775         kvm->arch.vpit->pit_state.flags = ps->flags;
3776         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3777         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3778         return r;
3779 }
3780
3781 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3782                                  struct kvm_reinject_control *control)
3783 {
3784         if (!kvm->arch.vpit)
3785                 return -ENXIO;
3786         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3787         kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3788         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3789         return 0;
3790 }
3791
3792 /**
3793  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3794  * @kvm: kvm instance
3795  * @log: slot id and address to which we copy the log
3796  *
3797  * Steps 1-4 below provide general overview of dirty page logging. See
3798  * kvm_get_dirty_log_protect() function description for additional details.
3799  *
3800  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3801  * always flush the TLB (step 4) even if previous step failed  and the dirty
3802  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3803  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3804  * writes will be marked dirty for next log read.
3805  *
3806  *   1. Take a snapshot of the bit and clear it if needed.
3807  *   2. Write protect the corresponding page.
3808  *   3. Copy the snapshot to the userspace.
3809  *   4. Flush TLB's if needed.
3810  */
3811 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3812 {
3813         bool is_dirty = false;
3814         int r;
3815
3816         mutex_lock(&kvm->slots_lock);
3817
3818         /*
3819          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3820          */
3821         if (kvm_x86_ops->flush_log_dirty)
3822                 kvm_x86_ops->flush_log_dirty(kvm);
3823
3824         r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3825
3826         /*
3827          * All the TLBs can be flushed out of mmu lock, see the comments in
3828          * kvm_mmu_slot_remove_write_access().
3829          */
3830         lockdep_assert_held(&kvm->slots_lock);
3831         if (is_dirty)
3832                 kvm_flush_remote_tlbs(kvm);
3833
3834         mutex_unlock(&kvm->slots_lock);