arch/x86/kvm/x86.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * derived from drivers/kvm/kvm_main.c
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright (C) 2008 Qumranet, Inc.
   8  * Copyright IBM Corporation, 2008
   9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  *   Amit Shah    <amit.shah@qumranet.com>
  15  *   Ben-Ami Yassour <benami@il.ibm.com>
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  *
  20  */
  21
  22 #include <linux/kvm_host.h>
  23 #include "irq.h"
  24 #include "mmu.h"
  25 #include "i8254.h"
  26 #include "tss.h"
  27 #include "kvm_cache_regs.h"
  28 #include "x86.h"
  29 #include "cpuid.h"
  30 #include "assigned-dev.h"
  31
  32 #include <linux/clocksource.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/kvm.h>
  35 #include <linux/fs.h>
  36 #include <linux/vmalloc.h>
  37 #include <linux/module.h>
  38 #include <linux/mman.h>
  39 #include <linux/highmem.h>
  40 #include <linux/iommu.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/cpufreq.h>
  43 #include <linux/user-return-notifier.h>
  44 #include <linux/srcu.h>
  45 #include <linux/slab.h>
  46 #include <linux/perf_event.h>
  47 #include <linux/uaccess.h>
  48 #include <linux/hash.h>
  49 #include <linux/pci.h>
  50 #include <linux/timekeeper_internal.h>
  51 #include <linux/pvclock_gtod.h>
  52 #include <trace/events/kvm.h>
  53
  54 #define CREATE_TRACE_POINTS
  55 #include "trace.h"
  56
  57 #include <asm/debugreg.h>
  58 #include <asm/msr.h>
  59 #include <asm/desc.h>
  60 #include <asm/mtrr.h>
  61 #include <asm/mce.h>
  62 #include <asm/i387.h>
  63 #include <asm/fpu-internal.h> /* Ugh! */
  64 #include <asm/xcr.h>
  65 #include <asm/pvclock.h>
  66 #include <asm/div64.h>
  67
  68 #define MAX_IO_MSRS 256
  69 #define KVM_MAX_MCE_BANKS 32
  70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
  71
  72 #define emul_to_vcpu(ctxt) \
  73         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
  74
  75 /* EFER defaults:
  76  * - enable syscall per default because its emulated by KVM
  77  * - enable LME and LMA per default on 64 bit KVM
  78  */
  79 #ifdef CONFIG_X86_64
  80 static
  81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  82 #else
  83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  84 #endif
  85
  86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
  87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
  88
  89 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
  90 static void process_nmi(struct kvm_vcpu *vcpu);
  91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
  92
  93 struct kvm_x86_ops *kvm_x86_ops;
  94 EXPORT_SYMBOL_GPL(kvm_x86_ops);
  95
  96 static bool ignore_msrs = 0;
  97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
  98
  99 unsigned int min_timer_period_us = 500;
 100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 101
 102 bool kvm_has_tsc_control;
 103 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 104 u32  kvm_max_guest_tsc_khz;
 105 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 106
 107 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 108 static u32 tsc_tolerance_ppm = 250;
 109 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 110
 111 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
 112 unsigned int lapic_timer_advance_ns = 0;
 113 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
 114
 115 static bool backwards_tsc_observed = false;
 116
 117 #define KVM_NR_SHARED_MSRS 16
 118
 119 struct kvm_shared_msrs_global {
 120         int nr;
 121         u32 msrs[KVM_NR_SHARED_MSRS];
 122 };
 123
 124 struct kvm_shared_msrs {
 125         struct user_return_notifier urn;
 126         bool registered;
 127         struct kvm_shared_msr_values {
 128                 u64 host;
 129                 u64 curr;
 130         } values[KVM_NR_SHARED_MSRS];
 131 };
 132
 133 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 134 static struct kvm_shared_msrs __percpu *shared_msrs;
 135
 136 struct kvm_stats_debugfs_item debugfs_entries[] = {
 137         { "pf_fixed", VCPU_STAT(pf_fixed) },
 138         { "pf_guest", VCPU_STAT(pf_guest) },
 139         { "tlb_flush", VCPU_STAT(tlb_flush) },
 140         { "invlpg", VCPU_STAT(invlpg) },
 141         { "exits", VCPU_STAT(exits) },
 142         { "io_exits", VCPU_STAT(io_exits) },
 143         { "mmio_exits", VCPU_STAT(mmio_exits) },
 144         { "signal_exits", VCPU_STAT(signal_exits) },
 145         { "irq_window", VCPU_STAT(irq_window_exits) },
 146         { "nmi_window", VCPU_STAT(nmi_window_exits) },
 147         { "halt_exits", VCPU_STAT(halt_exits) },
 148         { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
 149         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
 150         { "hypercalls", VCPU_STAT(hypercalls) },
 151         { "request_irq", VCPU_STAT(request_irq_exits) },
 152         { "irq_exits", VCPU_STAT(irq_exits) },
 153         { "host_state_reload", VCPU_STAT(host_state_reload) },
 154         { "efer_reload", VCPU_STAT(efer_reload) },
 155         { "fpu_reload", VCPU_STAT(fpu_reload) },
 156         { "insn_emulation", VCPU_STAT(insn_emulation) },
 157         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
 158         { "irq_injections", VCPU_STAT(irq_injections) },
 159         { "nmi_injections", VCPU_STAT(nmi_injections) },
 160         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
 161         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
 162         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
 163         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
 164         { "mmu_flooded", VM_STAT(mmu_flooded) },
 165         { "mmu_recycled", VM_STAT(mmu_recycled) },
 166         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
 167         { "mmu_unsync", VM_STAT(mmu_unsync) },
 168         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
 169         { "largepages", VM_STAT(lpages) },
 170         { NULL }
 171 };
 172
 173 u64 __read_mostly host_xcr0;
 174
 175 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 176
 177 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 178 {
 179         int i;
 180         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
 181                 vcpu->arch.apf.gfns[i] = ~0;
 182 }
 183
 184 static void kvm_on_user_return(struct user_return_notifier *urn)
 185 {
 186         unsigned slot;
 187         struct kvm_shared_msrs *locals
 188                 = container_of(urn, struct kvm_shared_msrs, urn);
 189         struct kvm_shared_msr_values *values;
 190
 191         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 192                 values = &locals->values[slot];
 193                 if (values->host != values->curr) {
 194                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 195                         values->curr = values->host;
 196                 }
 197         }
 198         locals->registered = false;
 199         user_return_notifier_unregister(urn);
 200 }
 201
 202 static void shared_msr_update(unsigned slot, u32 msr)
 203 {
 204         u64 value;
 205         unsigned int cpu = smp_processor_id();
 206         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 207
 208         /* only read, and nobody should modify it at this time,
 209          * so don't need lock */
 210         if (slot >= shared_msrs_global.nr) {
 211                 printk(KERN_ERR "kvm: invalid MSR slot!");
 212                 return;
 213         }
 214         rdmsrl_safe(msr, &value);
 215         smsr->values[slot].host = value;
 216         smsr->values[slot].curr = value;
 217 }
 218
 219 void kvm_define_shared_msr(unsigned slot, u32 msr)
 220 {
 221         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
 222         if (slot >= shared_msrs_global.nr)
 223                 shared_msrs_global.nr = slot + 1;
 224         shared_msrs_global.msrs[slot] = msr;
 225         /* we need ensured the shared_msr_global have been updated */
 226         smp_wmb();
 227 }
 228 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 229
 230 static void kvm_shared_msr_cpu_online(void)
 231 {
 232         unsigned i;
 233
 234         for (i = 0; i < shared_msrs_global.nr; ++i)
 235                 shared_msr_update(i, shared_msrs_global.msrs[i]);
 236 }
 237
 238 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 239 {
 240         unsigned int cpu = smp_processor_id();
 241         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 242         int err;
 243
 244         if (((value ^ smsr->values[slot].curr) & mask) == 0)
 245                 return 0;
 246         smsr->values[slot].curr = value;
 247         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
 248         if (err)
 249                 return 1;
 250
 251         if (!smsr->registered) {
 252                 smsr->urn.on_user_return = kvm_on_user_return;
 253                 user_return_notifier_register(&smsr->urn);
 254                 smsr->registered = true;
 255         }
 256         return 0;
 257 }
 258 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 259
 260 static void drop_user_return_notifiers(void)
 261 {
 262         unsigned int cpu = smp_processor_id();
 263         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 264
 265         if (smsr->registered)
 266                 kvm_on_user_return(&smsr->urn);
 267 }
 268
 269 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 270 {
 271         return vcpu->arch.apic_base;
 272 }
 273 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 274
 275 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 276 {
 277         u64 old_state = vcpu->arch.apic_base &
 278                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
 279         u64 new_state = msr_info->data &
 280                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
 281         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
 282                 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
 283
 284         if (!msr_info->host_initiated &&
 285             ((msr_info->data & reserved_bits) != 0 ||
 286              new_state == X2APIC_ENABLE ||
 287              (new_state == MSR_IA32_APICBASE_ENABLE &&
 288               old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
 289              (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
 290               old_state == 0)))
 291                 return 1;
 292
 293         kvm_lapic_set_base(vcpu, msr_info->data);
 294         return 0;
 295 }
 296 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 297
 298 asmlinkage __visible void kvm_spurious_fault(void)
 299 {
 300         /* Fault while not rebooting.  We want the trace. */
 301         BUG();
 302 }
 303 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 304
 305 #define EXCPT_BENIGN            0
 306 #define EXCPT_CONTRIBUTORY      1
 307 #define EXCPT_PF                2
 308
 309 static int exception_class(int vector)
 310 {
 311         switch (vector) {
 312         case PF_VECTOR:
 313                 return EXCPT_PF;
 314         case DE_VECTOR:
 315         case TS_VECTOR:
 316         case NP_VECTOR:
 317         case SS_VECTOR:
 318         case GP_VECTOR:
 319                 return EXCPT_CONTRIBUTORY;
 320         default:
 321                 break;
 322         }
 323         return EXCPT_BENIGN;
 324 }
 325
 326 #define EXCPT_FAULT             0
 327 #define EXCPT_TRAP              1
 328 #define EXCPT_ABORT             2
 329 #define EXCPT_INTERRUPT         3
 330
 331 static int exception_type(int vector)
 332 {
 333         unsigned int mask;
 334
 335         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
 336                 return EXCPT_INTERRUPT;
 337
 338         mask = 1 << vector;
 339
 340         /* #DB is trap, as instruction watchpoints are handled elsewhere */
 341         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
 342                 return EXCPT_TRAP;
 343
 344         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
 345                 return EXCPT_ABORT;
 346
 347         /* Reserved exceptions will result in fault */
 348         return EXCPT_FAULT;
 349 }
 350
 351 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 352                 unsigned nr, bool has_error, u32 error_code,
 353                 bool reinject)
 354 {
 355         u32 prev_nr;
 356         int class1, class2;
 357
 358         kvm_make_request(KVM_REQ_EVENT, vcpu);
 359
 360         if (!vcpu->arch.exception.pending) {
 361         queue:
 362                 if (has_error && !is_protmode(vcpu))
 363                         has_error = false;
 364                 vcpu->arch.exception.pending = true;
 365                 vcpu->arch.exception.has_error_code = has_error;
 366                 vcpu->arch.exception.nr = nr;
 367                 vcpu->arch.exception.error_code = error_code;
 368                 vcpu->arch.exception.reinject = reinject;
 369                 return;
 370         }
 371
 372         /* to check exception */
 373         prev_nr = vcpu->arch.exception.nr;
 374         if (prev_nr == DF_VECTOR) {
 375                 /* triple fault -> shutdown */
 376                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 377                 return;
 378         }
 379         class1 = exception_class(prev_nr);
 380         class2 = exception_class(nr);
 381         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 382                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 383                 /* generate double fault per SDM Table 5-5 */
 384                 vcpu->arch.exception.pending = true;
 385                 vcpu->arch.exception.has_error_code = true;
 386                 vcpu->arch.exception.nr = DF_VECTOR;
 387                 vcpu->arch.exception.error_code = 0;
 388         } else
 389                 /* replace previous exception with a new one in a hope
 390                    that instruction re-execution will regenerate lost
 391                    exception */
 392                 goto queue;
 393 }
 394
 395 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 396 {
 397         kvm_multiple_exception(vcpu, nr, false, 0, false);
 398 }
 399 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 400
 401 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 402 {
 403         kvm_multiple_exception(vcpu, nr, false, 0, true);
 404 }
 405 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 406
 407 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 408 {
 409         if (err)
 410                 kvm_inject_gp(vcpu, 0);
 411         else
 412                 kvm_x86_ops->skip_emulated_instruction(vcpu);
 413 }
 414 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 415
 416 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 417 {
 418         ++vcpu->stat.pf_guest;
 419         vcpu->arch.cr2 = fault->address;
 420         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 421 }
 422 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 423
 424 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 425 {
 426         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
 427                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
 428         else
 429                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
 430
 431         return fault->nested_page_fault;
 432 }
 433
 434 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 435 {
 436         atomic_inc(&vcpu->arch.nmi_queued);
 437         kvm_make_request(KVM_REQ_NMI, vcpu);
 438 }
 439 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 440
 441 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 442 {
 443         kvm_multiple_exception(vcpu, nr, true, error_code, false);
 444 }
 445 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 446
 447 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 448 {
 449         kvm_multiple_exception(vcpu, nr, true, error_code, true);
 450 }
 451 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 452
 453 /*
 454  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 455  * a #GP and return false.
 456  */
 457 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 458 {
 459         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
 460                 return true;
 461         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 462         return false;
 463 }
 464 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 465
 466 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
 467 {
 468         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 469                 return true;
 470
 471         kvm_queue_exception(vcpu, UD_VECTOR);
 472         return false;
 473 }
 474 EXPORT_SYMBOL_GPL(kvm_require_dr);
 475
 476 /*
 477  * This function will be used to read from the physical memory of the currently
 478  * running guest. The difference to kvm_read_guest_page is that this function
 479  * can read from guest physical or from the guest's guest physical memory.
 480  */
 481 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 482                             gfn_t ngfn, void *data, int offset, int len,
 483                             u32 access)
 484 {
 485         struct x86_exception exception;
 486         gfn_t real_gfn;
 487         gpa_t ngpa;
 488
 489         ngpa     = gfn_to_gpa(ngfn);
 490         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
 491         if (real_gfn == UNMAPPED_GVA)
 492                 return -EFAULT;
 493
 494         real_gfn = gpa_to_gfn(real_gfn);
 495
 496         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
 497 }
 498 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 499
 500 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 501                                void *data, int offset, int len, u32 access)
 502 {
 503         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 504                                        data, offset, len, access);
 505 }
 506
 507 /*
 508  * Load the pae pdptrs.  Return true is they are all valid.
 509  */
 510 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 511 {
 512         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 513         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 514         int i;
 515         int ret;
 516         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 517
 518         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 519                                       offset * sizeof(u64), sizeof(pdpte),
 520                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 521         if (ret < 0) {
 522                 ret = 0;
 523                 goto out;
 524         }
 525         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 526                 if (is_present_gpte(pdpte[i]) &&
 527                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
 528                         ret = 0;
 529                         goto out;
 530                 }
 531         }
 532         ret = 1;
 533
 534         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 535         __set_bit(VCPU_EXREG_PDPTR,
 536                   (unsigned long *)&vcpu->arch.regs_avail);
 537         __set_bit(VCPU_EXREG_PDPTR,
 538                   (unsigned long *)&vcpu->arch.regs_dirty);
 539 out:
 540
 541         return ret;
 542 }
 543 EXPORT_SYMBOL_GPL(load_pdptrs);
 544
 545 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
 546 {
 547         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 548         bool changed = true;
 549         int offset;
 550         gfn_t gfn;
 551         int r;
 552
 553         if (is_long_mode(vcpu) || !is_pae(vcpu))
 554                 return false;
 555
 556         if (!test_bit(VCPU_EXREG_PDPTR,
 557                       (unsigned long *)&vcpu->arch.regs_avail))
 558                 return true;
 559
 560         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
 561         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
 562         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 563                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 564         if (r < 0)
 565                 goto out;
 566         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 567 out:
 568
 569         return changed;
 570 }
 571
 572 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 573 {
 574         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 575         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
 576                                     X86_CR0_CD | X86_CR0_NW;
 577
 578         cr0 |= X86_CR0_ET;
 579
 580 #ifdef CONFIG_X86_64
 581         if (cr0 & 0xffffffff00000000UL)
 582                 return 1;
 583 #endif
 584
 585         cr0 &= ~CR0_RESERVED_BITS;
 586
 587         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 588                 return 1;
 589
 590         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 591                 return 1;
 592
 593         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 594 #ifdef CONFIG_X86_64
 595                 if ((vcpu->arch.efer & EFER_LME)) {
 596                         int cs_db, cs_l;
 597
 598                         if (!is_pae(vcpu))
 599                                 return 1;
 600                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 601                         if (cs_l)
 602                                 return 1;
 603                 } else
 604 #endif
 605                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 606                                                  kvm_read_cr3(vcpu)))
 607                         return 1;
 608         }
 609
 610         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 611                 return 1;
 612
 613         kvm_x86_ops->set_cr0(vcpu, cr0);
 614
 615         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 616                 kvm_clear_async_pf_completion_queue(vcpu);
 617                 kvm_async_pf_hash_reset(vcpu);
 618         }
 619
 620         if ((cr0 ^ old_cr0) & update_bits)
 621                 kvm_mmu_reset_context(vcpu);
 622         return 0;
 623 }
 624 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 625
 626 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 627 {
 628         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 629 }
 630 EXPORT_SYMBOL_GPL(kvm_lmsw);
 631
 632 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
 633 {
 634         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
 635                         !vcpu->guest_xcr0_loaded) {
 636                 /* kvm_set_xcr() also depends on this */
 637                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 638                 vcpu->guest_xcr0_loaded = 1;
 639         }
 640 }
 641
 642 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
 643 {
 644         if (vcpu->guest_xcr0_loaded) {
 645                 if (vcpu->arch.xcr0 != host_xcr0)
 646                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 647                 vcpu->guest_xcr0_loaded = 0;
 648         }
 649 }
 650
 651 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 652 {
 653         u64 xcr0 = xcr;
 654         u64 old_xcr0 = vcpu->arch.xcr0;
 655         u64 valid_bits;
 656
 657         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 658         if (index != XCR_XFEATURE_ENABLED_MASK)
 659                 return 1;
 660         if (!(xcr0 & XSTATE_FP))
 661                 return 1;
 662         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
 663                 return 1;
 664
 665         /*
 666          * Do not allow the guest to set bits that we do not support
 667          * saving.  However, xcr0 bit 0 is always set, even if the
 668          * emulated CPU does not support XSAVE (see fx_init).
 669          */
 670         valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
 671         if (xcr0 & ~valid_bits)
 672                 return 1;
 673
 674         if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
 675                 return 1;
 676
 677         if (xcr0 & XSTATE_AVX512) {
 678                 if (!(xcr0 & XSTATE_YMM))
 679                         return 1;
 680                 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
 681                         return 1;
 682         }
 683         kvm_put_guest_xcr0(vcpu);
 684         vcpu->arch.xcr0 = xcr0;
 685
 686         if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
 687                 kvm_update_cpuid(vcpu);
 688         return 0;
 689 }
 690
 691 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 692 {
 693         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
 694             __kvm_set_xcr(vcpu, index, xcr)) {
 695                 kvm_inject_gp(vcpu, 0);
 696                 return 1;
 697         }
 698         return 0;
 699 }
 700 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 701
 702 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 703 {
 704         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 705         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
 706                                    X86_CR4_PAE | X86_CR4_SMEP;
 707         if (cr4 & CR4_RESERVED_BITS)
 708                 return 1;
 709
 710         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
 711                 return 1;
 712
 713         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
 714                 return 1;
 715
 716         if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
 717                 return 1;
 718
 719         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
 720                 return 1;
 721
 722         if (is_long_mode(vcpu)) {
 723                 if (!(cr4 & X86_CR4_PAE))
 724                         return 1;
 725         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 726                    && ((cr4 ^ old_cr4) & pdptr_bits)
 727                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 728                                    kvm_read_cr3(vcpu)))
 729                 return 1;
 730
 731         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
 732                 if (!guest_cpuid_has_pcid(vcpu))
 733                         return 1;
 734
 735                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
 736                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
 737                         return 1;
 738         }
 739
 740         if (kvm_x86_ops->set_cr4(vcpu, cr4))
 741                 return 1;
 742
 743         if (((cr4 ^ old_cr4) & pdptr_bits) ||
 744             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
 745                 kvm_mmu_reset_context(vcpu);
 746
 747         if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
 748                 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
 749
 750         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
 751                 kvm_update_cpuid(vcpu);
 752
 753         return 0;
 754 }
 755 EXPORT_SYMBOL_GPL(kvm_set_cr4);
 756
 757 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 758 {
 759 #ifdef CONFIG_X86_64
 760         cr3 &= ~CR3_PCID_INVD;
 761 #endif
 762
 763         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
 764                 kvm_mmu_sync_roots(vcpu);
 765                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 766                 return 0;
 767         }
 768
 769         if (is_long_mode(vcpu)) {
 770                 if (cr3 & CR3_L_MODE_RESERVED_BITS)
 771                         return 1;
 772         } else if (is_pae(vcpu) && is_paging(vcpu) &&
 773                    !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
 774                 return 1;
 775
 776         vcpu->arch.cr3 = cr3;
 777         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
 778         kvm_mmu_new_cr3(vcpu);
 779         return 0;
 780 }
 781 EXPORT_SYMBOL_GPL(kvm_set_cr3);
 782
 783 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
 784 {
 785         if (cr8 & CR8_RESERVED_BITS)
 786                 return 1;
 787         if (irqchip_in_kernel(vcpu->kvm))
 788                 kvm_lapic_set_tpr(vcpu, cr8);
 789         else
 790                 vcpu->arch.cr8 = cr8;
 791         return 0;
 792 }
 793 EXPORT_SYMBOL_GPL(kvm_set_cr8);
 794
 795 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
 796 {
 797         if (irqchip_in_kernel(vcpu->kvm))
 798                 return kvm_lapic_get_cr8(vcpu);
 799         else
 800                 return vcpu->arch.cr8;
 801 }
 802 EXPORT_SYMBOL_GPL(kvm_get_cr8);
 803
 804 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
 805 {
 806         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
 807                 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
 808 }
 809
 810 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
 811 {
 812         unsigned long dr7;
 813
 814         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 815                 dr7 = vcpu->arch.guest_debug_dr7;
 816         else
 817                 dr7 = vcpu->arch.dr7;
 818         kvm_x86_ops->set_dr7(vcpu, dr7);
 819         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
 820         if (dr7 & DR7_BP_EN_MASK)
 821                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
 822 }
 823
 824 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
 825 {
 826         u64 fixed = DR6_FIXED_1;
 827
 828         if (!guest_cpuid_has_rtm(vcpu))
 829                 fixed |= DR6_RTM;
 830         return fixed;
 831 }
 832
 833 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
 834 {
 835         switch (dr) {
 836         case 0 ... 3:
 837                 vcpu->arch.db[dr] = val;
 838                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
 839                         vcpu->arch.eff_db[dr] = val;
 840                 break;
 841         case 4:
 842                 /* fall through */
 843         case 6:
 844                 if (val & 0xffffffff00000000ULL)
 845                         return -1; /* #GP */
 846                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
 847                 kvm_update_dr6(vcpu);
 848                 break;
 849         case 5:
 850                 /* fall through */
 851         default: /* 7 */
 852                 if (val & 0xffffffff00000000ULL)
 853                         return -1; /* #GP */
 854                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
 855                 kvm_update_dr7(vcpu);
 856                 break;
 857         }
 858
 859         return 0;
 860 }
 861
 862 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
 863 {
 864         if (__kvm_set_dr(vcpu, dr, val)) {
 865                 kvm_inject_gp(vcpu, 0);
 866                 return 1;
 867         }
 868         return 0;
 869 }
 870 EXPORT_SYMBOL_GPL(kvm_set_dr);
 871
 872 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
 873 {
 874         switch (dr) {
 875         case 0 ... 3:
 876                 *val = vcpu->arch.db[dr];
 877                 break;
 878         case 4:
 879                 /* fall through */
 880         case 6:
 881                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 882                         *val = vcpu->arch.dr6;
 883                 else
 884                         *val = kvm_x86_ops->get_dr6(vcpu);
 885                 break;
 886         case 5:
 887                 /* fall through */
 888         default: /* 7 */
 889                 *val = vcpu->arch.dr7;
 890                 break;
 891         }
 892         return 0;
 893 }
 894 EXPORT_SYMBOL_GPL(kvm_get_dr);
 895
 896 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
 897 {
 898         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
 899         u64 data;
 900         int err;
 901
 902         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
 903         if (err)
 904                 return err;
 905         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
 906         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
 907         return err;
 908 }
 909 EXPORT_SYMBOL_GPL(kvm_rdpmc);
 910
 911 /*
 912  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
 913  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
 914  *
 915  * This list is modified at module load time to reflect the
 916  * capabilities of the host cpu. This capabilities test skips MSRs that are
 917  * kvm-specific. Those are put in the beginning of the list.
 918  */
 919
 920 #define KVM_SAVE_MSRS_BEGIN     12
 921 static u32 msrs_to_save[] = {
 922         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
 923         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
 924         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
 925         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
 926         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
 927         MSR_KVM_PV_EOI_EN,
 928         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 929         MSR_STAR,
 930 #ifdef CONFIG_X86_64
 931         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
 932 #endif
 933         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
 934         MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
 935 };
 936
 937 static unsigned num_msrs_to_save;
 938
 939 static const u32 emulated_msrs[] = {
 940         MSR_IA32_TSC_ADJUST,
 941         MSR_IA32_TSCDEADLINE,
 942         MSR_IA32_MISC_ENABLE,
 943         MSR_IA32_MCG_STATUS,
 944         MSR_IA32_MCG_CTL,
 945 };
 946
 947 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
 948 {
 949         if (efer & efer_reserved_bits)
 950                 return false;
 951
 952         if (efer & EFER_FFXSR) {
 953                 struct kvm_cpuid_entry2 *feat;
 954
 955                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
 956                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
 957                         return false;
 958         }
 959
 960         if (efer & EFER_SVME) {
 961                 struct kvm_cpuid_entry2 *feat;
 962
 963                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
 964                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
 965                         return false;
 966         }
 967
 968         return true;
 969 }
 970 EXPORT_SYMBOL_GPL(kvm_valid_efer);
 971
 972 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
 973 {
 974         u64 old_efer = vcpu->arch.efer;
 975
 976         if (!kvm_valid_efer(vcpu, efer))
 977                 return 1;
 978
 979         if (is_paging(vcpu)
 980             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
 981                 return 1;
 982
 983         efer &= ~EFER_LMA;
 984         efer |= vcpu->arch.efer & EFER_LMA;
 985
 986         kvm_x86_ops->set_efer(vcpu, efer);
 987
 988         /* Update reserved bits */
 989         if ((efer ^ old_efer) & EFER_NX)
 990                 kvm_mmu_reset_context(vcpu);
 991
 992         return 0;
 993 }
 994
 995 void kvm_enable_efer_bits(u64 mask)
 996 {
 997        efer_reserved_bits &= ~mask;
 998 }
 999 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1000
1001 /*
1002  * Writes msr value into into the appropriate "register".
1003  * Returns 0 on success, non-0 otherwise.
1004  * Assumes vcpu_load() was already called.
1005  */
1006 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1007 {
1008         switch (msr->index) {
1009         case MSR_FS_BASE:
1010         case MSR_GS_BASE:
1011         case MSR_KERNEL_GS_BASE:
1012         case MSR_CSTAR:
1013         case MSR_LSTAR:
1014                 if (is_noncanonical_address(msr->data))
1015                         return 1;
1016                 break;
1017         case MSR_IA32_SYSENTER_EIP:
1018         case MSR_IA32_SYSENTER_ESP:
1019                 /*
1020                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1021                  * non-canonical address is written on Intel but not on
1022                  * AMD (which ignores the top 32-bits, because it does
1023                  * not implement 64-bit SYSENTER).
1024                  *
1025                  * 64-bit code should hence be able to write a non-canonical
1026                  * value on AMD.  Making the address canonical ensures that
1027                  * vmentry does not fail on Intel after writing a non-canonical
1028                  * value, and that something deterministic happens if the guest
1029                  * invokes 64-bit SYSENTER.
1030                  */
1031                 msr->data = get_canonical(msr->data);
1032         }
1033         return kvm_x86_ops->set_msr(vcpu, msr);
1034 }
1035 EXPORT_SYMBOL_GPL(kvm_set_msr);
1036
1037 /*
1038  * Adapt set_msr() to msr_io()'s calling convention
1039  */
1040 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1041 {
1042         struct msr_data msr;
1043
1044         msr.data = *data;
1045         msr.index = index;
1046         msr.host_initiated = true;
1047         return kvm_set_msr(vcpu, &msr);
1048 }
1049
1050 #ifdef CONFIG_X86_64
1051 struct pvclock_gtod_data {
1052         seqcount_t      seq;
1053
1054         struct { /* extract of a clocksource struct */
1055                 int vclock_mode;
1056                 cycle_t cycle_last;
1057                 cycle_t mask;
1058                 u32     mult;
1059                 u32     shift;
1060         } clock;
1061
1062         u64             boot_ns;
1063         u64             nsec_base;
1064 };
1065
1066 static struct pvclock_gtod_data pvclock_gtod_data;
1067
1068 static void update_pvclock_gtod(struct timekeeper *tk)
1069 {
1070         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1071         u64 boot_ns;
1072
1073         boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
1074
1075         write_seqcount_begin(&vdata->seq);
1076
1077         /* copy pvclock gtod data */
1078         vdata->clock.vclock_mode        = tk->tkr.clock->archdata.vclock_mode;
1079         vdata->clock.cycle_last         = tk->tkr.cycle_last;
1080         vdata->clock.mask               = tk->tkr.mask;
1081         vdata->clock.mult               = tk->tkr.mult;
1082         vdata->clock.shift              = tk->tkr.shift;
1083
1084         vdata->boot_ns                  = boot_ns;
1085         vdata->nsec_base                = tk->tkr.xtime_nsec;
1086
1087         write_seqcount_end(&vdata->seq);
1088 }
1089 #endif
1090
1091 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1092 {
1093         /*
1094          * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1095          * vcpu_enter_guest.  This function is only called from
1096          * the physical CPU that is running vcpu.
1097          */
1098         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1099 }
1100
1101 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1102 {
1103         int version;
1104         int r;
1105         struct pvclock_wall_clock wc;
1106         struct timespec boot;
1107
1108         if (!wall_clock)
1109                 return;
1110
1111         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1112         if (r)
1113                 return;
1114
1115         if (version & 1)
1116                 ++version;  /* first time write, random junk */
1117
1118         ++version;
1119
1120         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1121
1122         /*
1123          * The guest calculates current wall clock time by adding
1124          * system time (updated by kvm_guest_time_update below) to the
1125          * wall clock specified here.  guest system time equals host
1126          * system time for us, thus we must fill in host boot time here.
1127          */
1128         getboottime(&boot);
1129
1130         if (kvm->arch.kvmclock_offset) {
1131                 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1132                 boot = timespec_sub(boot, ts);
1133         }
1134         wc.sec = boot.tv_sec;
1135         wc.nsec = boot.tv_nsec;
1136         wc.version = version;
1137
1138         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1139
1140         version++;
1141         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1142 }
1143
1144 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1145 {
1146         uint32_t quotient, remainder;
1147
1148         /* Don't try to replace with do_div(), this one calculates
1149          * "(dividend << 32) / divisor" */
1150         __asm__ ( "divl %4"
1151                   : "=a" (quotient), "=d" (remainder)
1152                   : "0" (0), "1" (dividend), "r" (divisor) );
1153         return quotient;
1154 }
1155
1156 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1157                                s8 *pshift, u32 *pmultiplier)
1158 {
1159         uint64_t scaled64;
1160         int32_t  shift = 0;
1161         uint64_t tps64;
1162         uint32_t tps32;
1163
1164         tps64 = base_khz * 1000LL;
1165         scaled64 = scaled_khz * 1000LL;
1166         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1167                 tps64 >>= 1;
1168                 shift--;
1169         }
1170
1171         tps32 = (uint32_t)tps64;
1172         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1173                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1174                         scaled64 >>= 1;
1175                 else
1176                         tps32 <<= 1;
1177                 shift++;
1178         }
1179
1180         *pshift = shift;
1181         *pmultiplier = div_frac(scaled64, tps32);
1182
1183         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1184                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
1185 }
1186
1187 static inline u64 get_kernel_ns(void)
1188 {
1189         return ktime_get_boot_ns();
1190 }
1191
1192 #ifdef CONFIG_X86_64
1193 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1194 #endif
1195
1196 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1197 static unsigned long max_tsc_khz;
1198
1199 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1200 {
1201         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1202                                    vcpu->arch.virtual_tsc_shift);
1203 }
1204
1205 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1206 {
1207         u64 v = (u64)khz * (1000000 + ppm);
1208         do_div(v, 1000000);
1209         return v;
1210 }
1211
1212 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1213 {
1214         u32 thresh_lo, thresh_hi;
1215         int use_scaling = 0;
1216
1217         /* tsc_khz can be zero if TSC calibration fails */
1218         if (this_tsc_khz == 0)
1219                 return;
1220
1221         /* Compute a scale to convert nanoseconds in TSC cycles */
1222         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1223                            &vcpu->arch.virtual_tsc_shift,
1224                            &vcpu->arch.virtual_tsc_mult);
1225         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1226
1227         /*
1228          * Compute the variation in TSC rate which is acceptable
1229          * within the range of tolerance and decide if the
1230          * rate being applied is within that bounds of the hardware
1231          * rate.  If so, no scaling or compensation need be done.
1232          */
1233         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1234         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1235         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1236                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1237                 use_scaling = 1;
1238         }
1239         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1240 }
1241
1242 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1243 {
1244         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1245                                       vcpu->arch.virtual_tsc_mult,
1246                                       vcpu->arch.virtual_tsc_shift);
1247         tsc += vcpu->arch.this_tsc_write;
1248         return tsc;
1249 }
1250
1251 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1252 {
1253 #ifdef CONFIG_X86_64
1254         bool vcpus_matched;
1255         struct kvm_arch *ka = &vcpu->kvm->arch;
1256         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1257
1258         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1259                          atomic_read(&vcpu->kvm->online_vcpus));
1260
1261         /*
1262          * Once the masterclock is enabled, always perform request in
1263          * order to update it.
1264          *
1265          * In order to enable masterclock, the host clocksource must be TSC
1266          * and the vcpus need to have matched TSCs.  When that happens,
1267          * perform request to enable masterclock.
1268          */
1269         if (ka->use_master_clock ||
1270             (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1271                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1272
1273         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1274                             atomic_read(&vcpu->kvm->online_vcpus),
1275                             ka->use_master_clock, gtod->clock.vclock_mode);
1276 #endif
1277 }
1278
1279 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1280 {
1281         u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1282         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1283 }
1284
1285 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1286 {
1287         struct kvm *kvm = vcpu->kvm;
1288         u64 offset, ns, elapsed;
1289         unsigned long flags;
1290         s64 usdiff;
1291         bool matched;
1292         bool already_matched;
1293         u64 data = msr->data;
1294
1295         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1296         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1297         ns = get_kernel_ns();
1298         elapsed = ns - kvm->arch.last_tsc_nsec;
1299
1300         if (vcpu->arch.virtual_tsc_khz) {
1301                 int faulted = 0;
1302
1303                 /* n.b - signed multiplication and division required */
1304                 usdiff = data - kvm->arch.last_tsc_write;
1305 #ifdef CONFIG_X86_64
1306                 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1307 #else
1308                 /* do_div() only does unsigned */
1309                 asm("1: idivl %[divisor]\n"
1310                     "2: xor %%edx, %%edx\n"
1311                     "   movl $0, %[faulted]\n"
1312                     "3:\n"
1313                     ".section .fixup,\"ax\"\n"
1314                     "4: movl $1, %[faulted]\n"
1315                     "   jmp  3b\n"
1316                     ".previous\n"
1317
1318                 _ASM_EXTABLE(1b, 4b)
1319
1320                 : "=A"(usdiff), [faulted] "=r" (faulted)
1321                 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1322
1323 #endif
1324                 do_div(elapsed, 1000);
1325                 usdiff -= elapsed;
1326                 if (usdiff < 0)
1327                         usdiff = -usdiff;
1328
1329                 /* idivl overflow => difference is larger than USEC_PER_SEC */
1330                 if (faulted)
1331                         usdiff = USEC_PER_SEC;
1332         } else
1333                 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1334
1335         /*
1336          * Special case: TSC write with a small delta (1 second) of virtual
1337          * cycle time against real time is interpreted as an attempt to
1338          * synchronize the CPU.
1339          *
1340          * For a reliable TSC, we can match TSC offsets, and for an unstable
1341          * TSC, we add elapsed time in this computation.  We could let the
1342          * compensation code attempt to catch up if we fall behind, but
1343          * it's better to try to match offsets from the beginning.
1344          */
1345         if (usdiff < USEC_PER_SEC &&
1346             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1347                 if (!check_tsc_unstable()) {
1348                         offset = kvm->arch.cur_tsc_offset;
1349                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1350                 } else {
1351                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1352                         data += delta;
1353                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1354                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1355                 }
1356                 matched = true;
1357                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1358         } else {
1359                 /*
1360                  * We split periods of matched TSC writes into generations.
1361                  * For each generation, we track the original measured
1362                  * nanosecond time, offset, and write, so if TSCs are in
1363                  * sync, we can match exact offset, and if not, we can match
1364                  * exact software computation in compute_guest_tsc()
1365                  *
1366                  * These values are tracked in kvm->arch.cur_xxx variables.
1367                  */
1368                 kvm->arch.cur_tsc_generation++;
1369                 kvm->arch.cur_tsc_nsec = ns;
1370                 kvm->arch.cur_tsc_write = data;
1371                 kvm->arch.cur_tsc_offset = offset;
1372                 matched = false;
1373                 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1374                          kvm->arch.cur_tsc_generation, data);
1375         }
1376
1377         /*
1378          * We also track th most recent recorded KHZ, write and time to
1379          * allow the matching interval to be extended at each write.
1380          */
1381         kvm->arch.last_tsc_nsec = ns;
1382         kvm->arch.last_tsc_write = data;
1383         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1384
1385         vcpu->arch.last_guest_tsc = data;
1386
1387         /* Keep track of which generation this VCPU has synchronized to */
1388         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1389         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1390         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1391
1392         if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1393                 update_ia32_tsc_adjust_msr(vcpu, offset);
1394         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1395         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1396
1397         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1398         if (!matched) {
1399                 kvm->arch.nr_vcpus_matched_tsc = 0;
1400         } else if (!already_matched) {
1401                 kvm->arch.nr_vcpus_matched_tsc++;
1402         }
1403
1404         kvm_track_tsc_matching(vcpu);
1405         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1406 }
1407
1408 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1409
1410 #ifdef CONFIG_X86_64
1411
1412 static cycle_t read_tsc(void)
1413 {
1414         cycle_t ret;
1415         u64 last;
1416
1417         /*
1418          * Empirically, a fence (of type that depends on the CPU)
1419          * before rdtsc is enough to ensure that rdtsc is ordered
1420          * with respect to loads.  The various CPU manuals are unclear
1421          * as to whether rdtsc can be reordered with later loads,
1422          * but no one has ever seen it happen.
1423          */
1424         rdtsc_barrier();
1425         ret = (cycle_t)vget_cycles();
1426
1427         last = pvclock_gtod_data.clock.cycle_last;
1428
1429         if (likely(ret >= last))
1430                 return ret;
1431
1432         /*
1433          * GCC likes to generate cmov here, but this branch is extremely
1434          * predictable (it's just a funciton of time and the likely is
1435          * very likely) and there's a data dependence, so force GCC
1436          * to generate a branch instead.  I don't barrier() because
1437          * we don't actually need a barrier, and if this function
1438          * ever gets inlined it will generate worse code.
1439          */
1440         asm volatile ("");
1441         return last;
1442 }
1443
1444 static inline u64 vgettsc(cycle_t *cycle_now)
1445 {
1446         long v;
1447         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1448
1449         *cycle_now = read_tsc();
1450
1451         v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1452         return v * gtod->clock.mult;
1453 }
1454
1455 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1456 {
1457         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1458         unsigned long seq;
1459         int mode;
1460         u64 ns;
1461
1462         do {
1463                 seq = read_seqcount_begin(&gtod->seq);
1464                 mode = gtod->clock.vclock_mode;
1465                 ns = gtod->nsec_base;
1466                 ns += vgettsc(cycle_now);
1467                 ns >>= gtod->clock.shift;
1468                 ns += gtod->boot_ns;
1469         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1470         *t = ns;
1471
1472         return mode;
1473 }
1474
1475 /* returns true if host is using tsc clocksource */
1476 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1477 {
1478         /* checked again under seqlock below */
1479         if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1480                 return false;
1481
1482         return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1483 }
1484 #endif
1485
1486 /*
1487  *
1488  * Assuming a stable TSC across physical CPUS, and a stable TSC
1489  * across virtual CPUs, the following condition is possible.
1490  * Each numbered line represents an event visible to both
1491  * CPUs at the next numbered event.
1492  *
1493  * "timespecX" represents host monotonic time. "tscX" represents
1494  * RDTSC value.
1495  *
1496  *              VCPU0 on CPU0           |       VCPU1 on CPU1
1497  *
1498  * 1.  read timespec0,tsc0
1499  * 2.                                   | timespec1 = timespec0 + N
1500  *                                      | tsc1 = tsc0 + M
1501  * 3. transition to guest               | transition to guest
1502  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1503  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
1504  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1505  *
1506  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1507  *
1508  *      - ret0 < ret1
1509  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1510  *              ...
1511  *      - 0 < N - M => M < N
1512  *
1513  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1514  * always the case (the difference between two distinct xtime instances
1515  * might be smaller then the difference between corresponding TSC reads,
1516  * when updating guest vcpus pvclock areas).
1517  *
1518  * To avoid that problem, do not allow visibility of distinct
1519  * system_timestamp/tsc_timestamp values simultaneously: use a master
1520  * copy of host monotonic time values. Update that master copy
1521  * in lockstep.
1522  *
1523  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1524  *
1525  */
1526
1527 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1528 {
1529 #ifdef CONFIG_X86_64
1530         struct kvm_arch *ka = &kvm->arch;
1531         int vclock_mode;
1532         bool host_tsc_clocksource, vcpus_matched;
1533
1534         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1535                         atomic_read(&kvm->online_vcpus));
1536
1537         /*
1538          * If the host uses TSC clock, then passthrough TSC as stable
1539          * to the guest.
1540          */
1541         host_tsc_clocksource = kvm_get_time_and_clockread(
1542                                         &ka->master_kernel_ns,
1543                                         &ka->master_cycle_now);
1544
1545         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1546                                 && !backwards_tsc_observed
1547                                 && !ka->boot_vcpu_runs_old_kvmclock;
1548
1549         if (ka->use_master_clock)
1550                 atomic_set(&kvm_guest_has_master_clock, 1);
1551
1552         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1553         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1554                                         vcpus_matched);
1555 #endif
1556 }
1557
1558 static void kvm_gen_update_masterclock(struct kvm *kvm)
1559 {
1560 #ifdef CONFIG_X86_64
1561         int i;
1562         struct kvm_vcpu *vcpu;
1563         struct kvm_arch *ka = &kvm->arch;
1564
1565         spin_lock(&ka->pvclock_gtod_sync_lock);
1566         kvm_make_mclock_inprogress_request(kvm);
1567         /* no guest entries from this point */
1568         pvclock_update_vm_gtod_copy(kvm);
1569
1570         kvm_for_each_vcpu(i, vcpu, kvm)
1571                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1572
1573         /* guest entries allowed */
1574         kvm_for_each_vcpu(i, vcpu, kvm)
1575                 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1576
1577         spin_unlock(&ka->pvclock_gtod_sync_lock);
1578 #endif
1579 }
1580
1581 static int kvm_guest_time_update(struct kvm_vcpu *v)
1582 {
1583         unsigned long flags, this_tsc_khz;
1584         struct kvm_vcpu_arch *vcpu = &v->arch;
1585         struct kvm_arch *ka = &v->kvm->arch;
1586         s64 kernel_ns;
1587         u64 tsc_timestamp, host_tsc;
1588         struct pvclock_vcpu_time_info guest_hv_clock;
1589         u8 pvclock_flags;
1590         bool use_master_clock;
1591
1592         kernel_ns = 0;
1593         host_tsc = 0;
1594
1595         /*
1596          * If the host uses TSC clock, then passthrough TSC as stable
1597          * to the guest.
1598          */
1599         spin_lock(&ka->pvclock_gtod_sync_lock);
1600         use_master_clock = ka->use_master_clock;
1601         if (use_master_clock) {
1602                 host_tsc = ka->master_cycle_now;
1603                 kernel_ns = ka->master_kernel_ns;
1604         }
1605         spin_unlock(&ka->pvclock_gtod_sync_lock);
1606
1607         /* Keep irq disabled to prevent changes to the clock */
1608         local_irq_save(flags);
1609         this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1610         if (unlikely(this_tsc_khz == 0)) {
1611                 local_irq_restore(flags);
1612                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1613                 return 1;
1614         }
1615         if (!use_master_clock) {
1616                 host_tsc = native_read_tsc();
1617                 kernel_ns = get_kernel_ns();
1618         }
1619
1620         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1621
1622         /*
1623          * We may have to catch up the TSC to match elapsed wall clock
1624          * time for two reasons, even if kvmclock is used.
1625          *   1) CPU could have been running below the maximum TSC rate
1626          *   2) Broken TSC compensation resets the base at each VCPU
1627          *      entry to avoid unknown leaps of TSC even when running
1628          *      again on the same CPU.  This may cause apparent elapsed
1629          *      time to disappear, and the guest to stand still or run
1630          *      very slowly.
1631          */
1632         if (vcpu->tsc_catchup) {
1633                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1634                 if (tsc > tsc_timestamp) {
1635                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1636                         tsc_timestamp = tsc;
1637                 }
1638         }
1639
1640         local_irq_restore(flags);
1641
1642         if (!vcpu->pv_time_enabled)
1643                 return 0;
1644
1645         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1646                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1647                                    &vcpu->hv_clock.tsc_shift,
1648                                    &vcpu->hv_clock.tsc_to_system_mul);
1649                 vcpu->hw_tsc_khz = this_tsc_khz;
1650         }
1651
1652         /* With all the info we got, fill in the values */
1653         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1654         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1655         vcpu->last_guest_tsc = tsc_timestamp;
1656
1657         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1658                 &guest_hv_clock, sizeof(guest_hv_clock))))
1659                 return 0;
1660
1661         /*
1662          * The interface expects us to write an even number signaling that the
1663          * update is finished. Since the guest won't see the intermediate
1664          * state, we just increase by 2 at the end.
1665          */
1666         vcpu->hv_clock.version = guest_hv_clock.version + 2;
1667
1668         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1669         pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1670
1671         if (vcpu->pvclock_set_guest_stopped_request) {
1672                 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1673                 vcpu->pvclock_set_guest_stopped_request = false;
1674         }
1675
1676         /* If the host uses TSC clocksource, then it is stable */
1677         if (use_master_clock)
1678                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1679
1680         vcpu->hv_clock.flags = pvclock_flags;
1681
1682         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1683
1684         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1685                                 &vcpu->hv_clock,
1686                                 sizeof(vcpu->hv_clock));
1687         return 0;
1688 }
1689
1690 /*
1691  * kvmclock updates which are isolated to a given vcpu, such as
1692  * vcpu->cpu migration, should not allow system_timestamp from
1693  * the rest of the vcpus to remain static. Otherwise ntp frequency
1694  * correction applies to one vcpu's system_timestamp but not
1695  * the others.
1696  *
1697  * So in those cases, request a kvmclock update for all vcpus.
1698  * We need to rate-limit these requests though, as they can
1699  * considerably slow guests that have a large number of vcpus.
1700  * The time for a remote vcpu to update its kvmclock is bound
1701  * by the delay we use to rate-limit the updates.
1702  */
1703
1704 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1705
1706 static void kvmclock_update_fn(struct work_struct *work)
1707 {
1708         int i;
1709         struct delayed_work *dwork = to_delayed_work(work);
1710         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1711                                            kvmclock_update_work);
1712         struct kvm *kvm = container_of(ka, struct kvm, arch);
1713         struct kvm_vcpu *vcpu;
1714
1715         kvm_for_each_vcpu(i, vcpu, kvm) {
1716                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1717                 kvm_vcpu_kick(vcpu);
1718         }
1719 }
1720
1721 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1722 {
1723         struct kvm *kvm = v->kvm;
1724
1725         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1726         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1727                                         KVMCLOCK_UPDATE_DELAY);
1728 }
1729
1730 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1731
1732 static void kvmclock_sync_fn(struct work_struct *work)
1733 {
1734         struct delayed_work *dwork = to_delayed_work(work);
1735         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1736                                            kvmclock_sync_work);
1737         struct kvm *kvm = container_of(ka, struct kvm, arch);
1738
1739         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1740         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1741                                         KVMCLOCK_SYNC_PERIOD);
1742 }
1743
1744 static bool msr_mtrr_valid(unsigned msr)
1745 {
1746         switch (msr) {
1747         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1748         case MSR_MTRRfix64K_00000:
1749         case MSR_MTRRfix16K_80000:
1750         case MSR_MTRRfix16K_A0000:
1751         case MSR_MTRRfix4K_C0000:
1752         case MSR_MTRRfix4K_C8000:
1753         case MSR_MTRRfix4K_D0000:
1754         case MSR_MTRRfix4K_D8000:
1755         case MSR_MTRRfix4K_E0000:
1756         case MSR_MTRRfix4K_E8000:
1757         case MSR_MTRRfix4K_F0000:
1758         case MSR_MTRRfix4K_F8000:
1759         case MSR_MTRRdefType:
1760         case MSR_IA32_CR_PAT:
1761                 return true;
1762         case 0x2f8:
1763                 return true;
1764         }
1765         return false;
1766 }
1767
1768 static bool valid_pat_type(unsigned t)
1769 {
1770         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1771 }
1772
1773 static bool valid_mtrr_type(unsigned t)
1774 {
1775         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1776 }
1777
1778 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1779 {
1780         int i;
1781         u64 mask;
1782
1783         if (!msr_mtrr_valid(msr))
1784                 return false;
1785
1786         if (msr == MSR_IA32_CR_PAT) {
1787                 for (i = 0; i < 8; i++)
1788                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1789                                 return false;
1790                 return true;
1791         } else if (msr == MSR_MTRRdefType) {
1792                 if (data & ~0xcff)
1793                         return false;
1794                 return valid_mtrr_type(data & 0xff);
1795         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1796                 for (i = 0; i < 8 ; i++)
1797                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1798                                 return false;
1799                 return true;
1800         }
1801
1802         /* variable MTRRs */
1803         WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1804
1805         mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
1806         if ((msr & 1) == 0) {
1807                 /* MTRR base */
1808                 if (!valid_mtrr_type(data & 0xff))
1809                         return false;
1810                 mask |= 0xf00;
1811         } else
1812                 /* MTRR mask */
1813                 mask |= 0x7ff;
1814         if (data & mask) {
1815                 kvm_inject_gp(vcpu, 0);
1816                 return false;
1817         }
1818
1819         return true;
1820 }
1821 EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
1822
1823 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1824 {
1825         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1826
1827         if (!kvm_mtrr_valid(vcpu, msr, data))
1828                 return 1;
1829
1830         if (msr == MSR_MTRRdefType) {
1831                 vcpu->arch.mtrr_state.def_type = data;
1832                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1833         } else if (msr == MSR_MTRRfix64K_00000)
1834                 p[0] = data;
1835         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1836                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1837         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1838                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1839         else if (msr == MSR_IA32_CR_PAT)
1840                 vcpu->arch.pat = data;
1841         else {  /* Variable MTRRs */
1842                 int idx, is_mtrr_mask;
1843                 u64 *pt;
1844
1845                 idx = (msr - 0x200) / 2;
1846                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1847                 if (!is_mtrr_mask)
1848                         pt =
1849                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1850                 else
1851                         pt =
1852                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1853                 *pt = data;
1854         }
1855
1856         kvm_mmu_reset_context(vcpu);
1857         return 0;
1858 }
1859
1860 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1861 {
1862         u64 mcg_cap = vcpu->arch.mcg_cap;
1863         unsigned bank_num = mcg_cap & 0xff;
1864
1865         switch (msr) {
1866         case MSR_IA32_MCG_STATUS:
1867                 vcpu->arch.mcg_status = data;
1868                 break;
1869         case MSR_IA32_MCG_CTL:
1870                 if (!(mcg_cap & MCG_CTL_P))
1871                         return 1;
1872                 if (data != 0 && data != ~(u64)0)
1873                         return -1;
1874                 vcpu->arch.mcg_ctl = data;
1875                 break;
1876         default:
1877                 if (msr >= MSR_IA32_MC0_CTL &&
1878                     msr < MSR_IA32_MCx_CTL(bank_num)) {
1879                         u32 offset = msr - MSR_IA32_MC0_CTL;
1880                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1881                          * some Linux kernels though clear bit 10 in bank 4 to
1882                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1883                          * this to avoid an uncatched #GP in the guest
1884                          */
1885                         if ((offset & 0x3) == 0 &&
1886                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1887                                 return -1;
1888                         vcpu->arch.mce_banks[offset] = data;
1889                         break;
1890                 }
1891                 return 1;
1892         }
1893         return 0;
1894 }
1895
1896 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1897 {
1898         struct kvm *kvm = vcpu->kvm;
1899         int lm = is_long_mode(vcpu);
1900         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1901                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1902         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1903                 : kvm->arch.xen_hvm_config.blob_size_32;
1904         u32 page_num = data & ~PAGE_MASK;
1905         u64 page_addr = data & PAGE_MASK;
1906         u8 *page;
1907         int r;
1908
1909         r = -E2BIG;
1910         if (page_num >= blob_size)
1911                 goto out;
1912         r = -ENOMEM;
1913         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1914         if (IS_ERR(page)) {
1915                 r = PTR_ERR(page);
1916                 goto out;
1917         }
1918         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1919                 goto out_free;
1920         r = 0;
1921 out_free:
1922         kfree(page);
1923 out:
1924         return r;
1925 }
1926
1927 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1928 {
1929         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1930 }
1931
1932 static bool kvm_hv_msr_partition_wide(u32 msr)
1933 {
1934         bool r = false;
1935         switch (msr) {
1936         case HV_X64_MSR_GUEST_OS_ID:
1937         case HV_X64_MSR_HYPERCALL:
1938         case HV_X64_MSR_REFERENCE_TSC:
1939         case HV_X64_MSR_TIME_REF_COUNT:
1940                 r = true;
1941                 break;
1942         }
1943
1944         return r;
1945 }
1946
1947 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1948 {
1949         struct kvm *kvm = vcpu->kvm;
1950
1951         switch (msr) {
1952         case HV_X64_MSR_GUEST_OS_ID:
1953                 kvm->arch.hv_guest_os_id = data;
1954                 /* setting guest os id to zero disables hypercall page */
1955                 if (!kvm->arch.hv_guest_os_id)
1956                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1957                 break;
1958         case HV_X64_MSR_HYPERCALL: {
1959                 u64 gfn;
1960                 unsigned long addr;
1961                 u8 instructions[4];
1962
1963                 /* if guest os id is not set hypercall should remain disabled */
1964                 if (!kvm->arch.hv_guest_os_id)
1965                         break;
1966                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1967                         kvm->arch.hv_hypercall = data;
1968                         break;
1969                 }
1970                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1971                 addr = gfn_to_hva(kvm, gfn);
1972                 if (kvm_is_error_hva(addr))
1973                         return 1;
1974                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1975                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1976                 if (__copy_to_user((void __user *)addr, instructions, 4))
1977                         return 1;
1978                 kvm->arch.hv_hypercall = data;
1979                 mark_page_dirty(kvm, gfn);
1980                 break;
1981         }
1982         case HV_X64_MSR_REFERENCE_TSC: {
1983                 u64 gfn;
1984                 HV_REFERENCE_TSC_PAGE tsc_ref;
1985                 memset(&tsc_ref, 0, sizeof(tsc_ref));
1986                 kvm->arch.hv_tsc_page = data;
1987                 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1988                         break;
1989                 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1990                 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
1991                         &tsc_ref, sizeof(tsc_ref)))
1992                         return 1;
1993                 mark_page_dirty(kvm, gfn);
1994                 break;
1995         }
1996         default:
1997                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1998                             "data 0x%llx\n", msr, data);
1999                 return 1;
2000         }
2001         return 0;
2002 }
2003
2004 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2005 {
2006         switch (msr) {
2007         case HV_X64_MSR_APIC_ASSIST_PAGE: {
2008                 u64 gfn;
2009                 unsigned long addr;
2010
2011                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2012                         vcpu->arch.hv_vapic = data;
2013                         if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2014                                 return 1;
2015                         break;
2016                 }
2017                 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2018                 addr = gfn_to_hva(vcpu->kvm, gfn);
2019                 if (kvm_is_error_hva(addr))
2020                         return 1;
2021                 if (__clear_user((void __user *)addr, PAGE_SIZE))
2022                         return 1;
2023                 vcpu->arch.hv_vapic = data;
2024                 mark_page_dirty(vcpu->kvm, gfn);
2025                 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2026                         return 1;
2027                 break;
2028         }
2029         case HV_X64_MSR_EOI:
2030                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2031         case HV_X64_MSR_ICR:
2032                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2033         case HV_X64_MSR_TPR:
2034                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2035         default:
2036                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2037                             "data 0x%llx\n", msr, data);
2038                 return 1;
2039         }
2040
2041         return 0;
2042 }
2043
2044 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2045 {
2046         gpa_t gpa = data & ~0x3f;
2047
2048         /* Bits 2:5 are reserved, Should be zero */
2049         if (data & 0x3c)
2050                 return 1;
2051
2052         vcpu->arch.apf.msr_val = data;
2053
2054         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2055                 kvm_clear_async_pf_completion_queue(vcpu);
2056                 kvm_async_pf_hash_reset(vcpu);
2057                 return 0;
2058         }
2059
2060         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2061                                         sizeof(u32)))
2062                 return 1;
2063
2064         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2065         kvm_async_pf_wakeup_all(vcpu);
2066         return 0;
2067 }
2068
2069 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2070 {
2071         vcpu->arch.pv_time_enabled = false;
2072 }
2073
2074 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2075 {
2076         u64 delta;
2077
2078         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2079                 return;
2080
2081         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2082         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2083         vcpu->arch.st.accum_steal = delta;
2084 }
2085
2086 static void record_steal_time(struct kvm_vcpu *vcpu)
2087 {
2088         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2089                 return;
2090
2091         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2092                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2093                 return;
2094
2095         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2096         vcpu->arch.st.steal.version += 2;
2097         vcpu->arch.st.accum_steal = 0;
2098
2099         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2100                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2101 }
2102
2103 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2104 {
2105         bool pr = false;
2106         u32 msr = msr_info->index;
2107         u64 data = msr_info->data;
2108
2109         switch (msr) {
2110         case MSR_AMD64_NB_CFG:
2111         case MSR_IA32_UCODE_REV:
2112         case MSR_IA32_UCODE_WRITE:
2113         case MSR_VM_HSAVE_PA:
2114         case MSR_AMD64_PATCH_LOADER:
2115         case MSR_AMD64_BU_CFG2:
2116                 break;
2117
2118         case MSR_EFER:
2119                 return set_efer(vcpu, data);
2120         case MSR_K7_HWCR:
2121                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2122                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2123                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2124                 data &= ~(u64)0x40000;  /* ignore Mc status write enable */
2125                 if (data != 0) {
2126                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2127                                     data);
2128                         return 1;
2129                 }
2130                 break;
2131         case MSR_FAM10H_MMIO_CONF_BASE:
2132                 if (data != 0) {
2133                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2134                                     "0x%llx\n", data);
2135                         return 1;
2136                 }
2137                 break;
2138         case MSR_IA32_DEBUGCTLMSR:
2139                 if (!data) {
2140                         /* We support the non-activated case already */
2141                         break;
2142                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2143                         /* Values other than LBR and BTF are vendor-specific,
2144                            thus reserved and should throw a #GP */
2145                         return 1;
2146                 }
2147                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2148                             __func__, data);
2149                 break;
2150         case 0x200 ... 0x2ff:
2151                 return set_msr_mtrr(vcpu, msr, data);
2152         case MSR_IA32_APICBASE:
2153                 return kvm_set_apic_base(vcpu, msr_info);
2154         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2155                 return kvm_x2apic_msr_write(vcpu, msr, data);
2156         case MSR_IA32_TSCDEADLINE:
2157                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2158                 break;
2159         case MSR_IA32_TSC_ADJUST:
2160                 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2161                         if (!msr_info->host_initiated) {
2162                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2163                                 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2164                         }
2165                         vcpu->arch.ia32_tsc_adjust_msr = data;
2166                 }
2167                 break;
2168         case MSR_IA32_MISC_ENABLE:
2169                 vcpu->arch.ia32_misc_enable_msr = data;
2170                 break;
2171         case MSR_KVM_WALL_CLOCK_NEW:
2172         case MSR_KVM_WALL_CLOCK:
2173                 vcpu->kvm->arch.wall_clock = data;
2174                 kvm_write_wall_clock(vcpu->kvm, data);
2175                 break;
2176         case MSR_KVM_SYSTEM_TIME_NEW:
2177         case MSR_KVM_SYSTEM_TIME: {
2178                 u64 gpa_offset;
2179                 struct kvm_arch *ka = &vcpu->kvm->arch;
2180
2181                 kvmclock_reset(vcpu);
2182
2183                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2184                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2185
2186                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2187                                 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2188                                         &vcpu->requests);
2189
2190                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2191                 }
2192
2193                 vcpu->arch.time = data;
2194                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2195
2196                 /* we verify if the enable bit is set... */
2197                 if (!(data & 1))
2198                         break;
2199
2200                 gpa_offset = data & ~(PAGE_MASK | 1);
2201
2202                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2203                      &vcpu->arch.pv_time, data & ~1ULL,
2204                      sizeof(struct pvclock_vcpu_time_info)))
2205                         vcpu->arch.pv_time_enabled = false;
2206                 else
2207                         vcpu->arch.pv_time_enabled = true;
2208
2209                 break;
2210         }
2211         case MSR_KVM_ASYNC_PF_EN:
2212                 if (kvm_pv_enable_async_pf(vcpu, data))
2213                         return 1;
2214                 break;
2215         case MSR_KVM_STEAL_TIME:
2216
2217                 if (unlikely(!sched_info_on()))
2218                         return 1;
2219
2220                 if (data & KVM_STEAL_RESERVED_MASK)
2221                         return 1;
2222
2223                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2224                                                 data & KVM_STEAL_VALID_BITS,
2225                                                 sizeof(struct kvm_steal_time)))
2226                         return 1;
2227
2228                 vcpu->arch.st.msr_val = data;
2229
2230                 if (!(data & KVM_MSR_ENABLED))
2231                         break;
2232
2233                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2234
2235                 preempt_disable();
2236                 accumulate_steal_time(vcpu);
2237                 preempt_enable();
2238
2239                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2240
2241                 break;
2242         case MSR_KVM_PV_EOI_EN:
2243                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2244                         return 1;
2245                 break;
2246
2247         case MSR_IA32_MCG_CTL:
2248         case MSR_IA32_MCG_STATUS:
2249         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2250                 return set_msr_mce(vcpu, msr, data);
2251
2252         /* Performance counters are not protected by a CPUID bit,
2253          * so we should check all of them in the generic path for the sake of
2254          * cross vendor migration.
2255          * Writing a zero into the event select MSRs disables them,
2256          * which we perfectly emulate ;-). Any other value should be at least
2257          * reported, some guests depend on them.
2258          */
2259         case MSR_K7_EVNTSEL0:
2260         case MSR_K7_EVNTSEL1:
2261         case MSR_K7_EVNTSEL2:
2262         case MSR_K7_EVNTSEL3:
2263                 if (data != 0)
2264                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2265                                     "0x%x data 0x%llx\n", msr, data);
2266                 break;
2267         /* at least RHEL 4 unconditionally writes to the perfctr registers,
2268          * so we ignore writes to make it happy.
2269          */
2270         case MSR_K7_PERFCTR0:
2271         case MSR_K7_PERFCTR1:
2272         case MSR_K7_PERFCTR2:
2273         case MSR_K7_PERFCTR3:
2274                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2275                             "0x%x data 0x%llx\n", msr, data);
2276                 break;
2277         case MSR_P6_PERFCTR0:
2278         case MSR_P6_PERFCTR1:
2279                 pr = true;
2280         case MSR_P6_EVNTSEL0:
2281         case MSR_P6_EVNTSEL1:
2282                 if (kvm_pmu_msr(vcpu, msr))
2283                         return kvm_pmu_set_msr(vcpu, msr_info);
2284
2285                 if (pr || data != 0)
2286                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2287                                     "0x%x data 0x%llx\n", msr, data);
2288                 break;
2289         case MSR_K7_CLK_CTL:
2290                 /*
2291                  * Ignore all writes to this no longer documented MSR.
2292                  * Writes are only relevant for old K7 processors,
2293                  * all pre-dating SVM, but a recommended workaround from
2294                  * AMD for these chips. It is possible to specify the
2295                  * affected processor models on the command line, hence
2296                  * the need to ignore the workaround.
2297                  */
2298                 break;
2299         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2300                 if (kvm_hv_msr_partition_wide(msr)) {
2301                         int r;
2302                         mutex_lock(&vcpu->kvm->lock);
2303                         r = set_msr_hyperv_pw(vcpu, msr, data);
2304                         mutex_unlock(&vcpu->kvm->lock);
2305                         return r;
2306                 } else
2307                         return set_msr_hyperv(vcpu, msr, data);
2308                 break;
2309         case MSR_IA32_BBL_CR_CTL3:
2310                 /* Drop writes to this legacy MSR -- see rdmsr
2311                  * counterpart for further detail.
2312                  */
2313                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2314                 break;
2315         case MSR_AMD64_OSVW_ID_LENGTH:
2316                 if (!guest_cpuid_has_osvw(vcpu))
2317                         return 1;
2318                 vcpu->arch.osvw.length = data;
2319                 break;
2320         case MSR_AMD64_OSVW_STATUS:
2321                 if (!guest_cpuid_has_osvw(vcpu))
2322                         return 1;
2323                 vcpu->arch.osvw.status = data;
2324                 break;
2325         default:
2326                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2327                         return xen_hvm_config(vcpu, data);
2328                 if (kvm_pmu_msr(vcpu, msr))
2329                         return kvm_pmu_set_msr(vcpu, msr_info);
2330                 if (!ignore_msrs) {
2331                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2332                                     msr, data);
2333                         return 1;
2334                 } else {
2335                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2336                                     msr, data);
2337                         break;
2338                 }
2339         }
2340         return 0;
2341 }
2342 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2343
2344
2345 /*
2346  * Reads an msr value (of 'msr_index') into 'pdata'.
2347  * Returns 0 on success, non-0 otherwise.
2348  * Assumes vcpu_load() was already called.
2349  */
2350 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2351 {
2352         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2353 }
2354 EXPORT_SYMBOL_GPL(kvm_get_msr);
2355
2356 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2357 {
2358         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2359
2360         if (!msr_mtrr_valid(msr))
2361                 return 1;
2362
2363         if (msr == MSR_MTRRdefType)
2364                 *pdata = vcpu->arch.mtrr_state.def_type +
2365                          (vcpu->arch.mtrr_state.enabled << 10);
2366         else if (msr == MSR_MTRRfix64K_00000)
2367                 *pdata = p[0];
2368         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2369                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2370         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2371                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2372         else if (msr == MSR_IA32_CR_PAT)
2373                 *pdata = vcpu->arch.pat;
2374         else {  /* Variable MTRRs */
2375                 int idx, is_mtrr_mask;
2376                 u64 *pt;
2377
2378                 idx = (msr - 0x200) / 2;
2379                 is_mtrr_mask = msr - 0x200 - 2 * idx;
2380                 if (!is_mtrr_mask)
2381                         pt =
2382                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2383                 else
2384                         pt =
2385                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2386                 *pdata = *pt;
2387         }
2388
2389         return 0;
2390 }
2391
2392 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2393 {
2394         u64 data;
2395         u64 mcg_cap = vcpu->arch.mcg_cap;
2396         unsigned bank_num = mcg_cap & 0xff;
2397
2398         switch (msr) {
2399         case MSR_IA32_P5_MC_ADDR:
2400         case MSR_IA32_P5_MC_TYPE:
2401                 data = 0;
2402                 break;
2403         case MSR_IA32_MCG_CAP:
2404                 data = vcpu->arch.mcg_cap;
2405                 break;
2406         case MSR_IA32_MCG_CTL:
2407                 if (!(mcg_cap & MCG_CTL_P))
2408                         return 1;
2409                 data = vcpu->arch.mcg_ctl;
2410                 break;
2411         case MSR_IA32_MCG_STATUS:
2412                 data = vcpu->arch.mcg_status;
2413                 break;
2414         default:
2415                 if (msr >= MSR_IA32_MC0_CTL &&
2416                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2417                         u32 offset = msr - MSR_IA32_MC0_CTL;
2418                         data = vcpu->arch.mce_banks[offset];
2419                         break;
2420                 }
2421                 return 1;
2422         }
2423         *pdata = data;
2424         return 0;
2425 }
2426
2427 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2428 {
2429         u64 data = 0;
2430         struct kvm *kvm = vcpu->kvm;
2431
2432         switch (msr) {
2433         case HV_X64_MSR_GUEST_OS_ID:
2434                 data = kvm->arch.hv_guest_os_id;
2435                 break;
2436         case HV_X64_MSR_HYPERCALL:
2437                 data = kvm->arch.hv_hypercall;
2438                 break;
2439         case HV_X64_MSR_TIME_REF_COUNT: {
2440                 data =
2441                      div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2442                 break;
2443         }
2444         case HV_X64_MSR_REFERENCE_TSC:
2445                 data = kvm->arch.hv_tsc_page;
2446                 break;
2447         default:
2448                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2449                 return 1;
2450         }
2451
2452         *pdata = data;
2453         return 0;
2454 }
2455
2456 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2457 {
2458         u64 data = 0;
2459
2460         switch (msr) {
2461         case HV_X64_MSR_VP_INDEX: {
2462                 int r;
2463                 struct kvm_vcpu *v;
2464                 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2465                         if (v == vcpu) {
2466                                 data = r;
2467                                 break;
2468                         }
2469                 }
2470                 break;
2471         }
2472         case HV_X64_MSR_EOI:
2473                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2474         case HV_X64_MSR_ICR:
2475                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2476         case HV_X64_MSR_TPR:
2477                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2478         case HV_X64_MSR_APIC_ASSIST_PAGE:
2479                 data = vcpu->arch.hv_vapic;
2480                 break;
2481         default:
2482                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2483                 return 1;
2484         }
2485         *pdata = data;
2486         return 0;
2487 }
2488
2489 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2490 {
2491         u64 data;
2492
2493         switch (msr) {
2494         case MSR_IA32_PLATFORM_ID:
2495         case MSR_IA32_EBL_CR_POWERON:
2496         case MSR_IA32_DEBUGCTLMSR:
2497         case MSR_IA32_LASTBRANCHFROMIP:
2498         case MSR_IA32_LASTBRANCHTOIP:
2499         case MSR_IA32_LASTINTFROMIP:
2500         case MSR_IA32_LASTINTTOIP:
2501         case MSR_K8_SYSCFG:
2502         case MSR_K7_HWCR:
2503         case MSR_VM_HSAVE_PA:
2504         case MSR_K7_EVNTSEL0:
2505         case MSR_K7_EVNTSEL1:
2506         case MSR_K7_EVNTSEL2:
2507         case MSR_K7_EVNTSEL3:
2508         case MSR_K7_PERFCTR0:
2509         case MSR_K7_PERFCTR1:
2510         case MSR_K7_PERFCTR2:
2511         case MSR_K7_PERFCTR3:
2512         case MSR_K8_INT_PENDING_MSG:
2513         case MSR_AMD64_NB_CFG:
2514         case MSR_FAM10H_MMIO_CONF_BASE:
2515         case MSR_AMD64_BU_CFG2:
2516                 data = 0;
2517                 break;
2518         case MSR_P6_PERFCTR0:
2519         case MSR_P6_PERFCTR1:
2520         case MSR_P6_EVNTSEL0:
2521         case MSR_P6_EVNTSEL1:
2522                 if (kvm_pmu_msr(vcpu, msr))
2523                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2524                 data = 0;
2525                 break;
2526         case MSR_IA32_UCODE_REV:
2527                 data = 0x100000000ULL;
2528                 break;
2529         case MSR_MTRRcap:
2530                 data = 0x500 | KVM_NR_VAR_MTRR;
2531                 break;
2532         case 0x200 ... 0x2ff:
2533                 return get_msr_mtrr(vcpu, msr, pdata);
2534         case 0xcd: /* fsb frequency */
2535                 data = 3;
2536                 break;
2537                 /*
2538                  * MSR_EBC_FREQUENCY_ID
2539                  * Conservative value valid for even the basic CPU models.
2540                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2541                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2542                  * and 266MHz for model 3, or 4. Set Core Clock
2543                  * Frequency to System Bus Frequency Ratio to 1 (bits
2544                  * 31:24) even though these are only valid for CPU
2545                  * models > 2, however guests may end up dividing or
2546                  * multiplying by zero otherwise.
2547                  */
2548         case MSR_EBC_FREQUENCY_ID:
2549                 data = 1 << 24;
2550                 break;
2551         case MSR_IA32_APICBASE:
2552                 data = kvm_get_apic_base(vcpu);
2553                 break;
2554         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2555                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2556                 break;
2557         case MSR_IA32_TSCDEADLINE:
2558                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2559                 break;
2560         case MSR_IA32_TSC_ADJUST:
2561                 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2562                 break;
2563         case MSR_IA32_MISC_ENABLE:
2564                 data = vcpu->arch.ia32_misc_enable_msr;
2565                 break;
2566         case MSR_IA32_PERF_STATUS:
2567                 /* TSC increment by tick */
2568                 data = 1000ULL;
2569                 /* CPU multiplier */
2570                 data |= (((uint64_t)4ULL) << 40);
2571                 break;
2572         case MSR_EFER:
2573                 data = vcpu->arch.efer;
2574                 break;
2575         case MSR_KVM_WALL_CLOCK:
2576         case MSR_KVM_WALL_CLOCK_NEW:
2577                 data = vcpu->kvm->arch.wall_clock;
2578                 break;
2579         case MSR_KVM_SYSTEM_TIME:
2580         case MSR_KVM_SYSTEM_TIME_NEW:
2581                 data = vcpu->arch.time;
2582                 break;
2583         case MSR_KVM_ASYNC_PF_EN:
2584                 data = vcpu->arch.apf.msr_val;
2585                 break;
2586         case MSR_KVM_STEAL_TIME:
2587                 data = vcpu->arch.st.msr_val;
2588                 break;
2589         case MSR_KVM_PV_EOI_EN:
2590                 data = vcpu->arch.pv_eoi.msr_val;
2591                 break;
2592         case MSR_IA32_P5_MC_ADDR:
2593         case MSR_IA32_P5_MC_TYPE:
2594         case MSR_IA32_MCG_CAP:
2595         case MSR_IA32_MCG_CTL:
2596         case MSR_IA32_MCG_STATUS:
2597         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2598                 return get_msr_mce(vcpu, msr, pdata);
2599         case MSR_K7_CLK_CTL:
2600                 /*
2601                  * Provide expected ramp-up count for K7. All other
2602                  * are set to zero, indicating minimum divisors for
2603                  * every field.
2604                  *
2605                  * This prevents guest kernels on AMD host with CPU
2606                  * type 6, model 8 and higher from exploding due to
2607                  * the rdmsr failing.
2608                  */
2609                 data = 0x20000000;
2610                 break;
2611         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2612                 if (kvm_hv_msr_partition_wide(msr)) {
2613                         int r;
2614                         mutex_lock(&vcpu->kvm->lock);
2615                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2616                         mutex_unlock(&vcpu->kvm->lock);
2617                         return r;
2618                 } else
2619                         return get_msr_hyperv(vcpu, msr, pdata);
2620                 break;
2621         case MSR_IA32_BBL_CR_CTL3:
2622                 /* This legacy MSR exists but isn't fully documented in current
2623                  * silicon.  It is however accessed by winxp in very narrow
2624                  * scenarios where it sets bit #19, itself documented as
2625                  * a "reserved" bit.  Best effort attempt to source coherent
2626                  * read data here should the balance of the register be
2627                  * interpreted by the guest:
2628                  *
2629                  * L2 cache control register 3: 64GB range, 256KB size,
2630                  * enabled, latency 0x1, configured
2631                  */
2632                 data = 0xbe702111;
2633                 break;
2634         case MSR_AMD64_OSVW_ID_LENGTH:
2635                 if (!guest_cpuid_has_osvw(vcpu))
2636                         return 1;
2637                 data = vcpu->arch.osvw.length;
2638                 break;
2639         case MSR_AMD64_OSVW_STATUS:
2640                 if (!guest_cpuid_has_osvw(vcpu))
2641                         return 1;
2642                 data = vcpu->arch.osvw.status;
2643                 break;
2644         default:
2645                 if (kvm_pmu_msr(vcpu, msr))
2646                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2647                 if (!ignore_msrs) {
2648                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2649                         return 1;
2650                 } else {
2651                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2652                         data = 0;
2653                 }
2654                 break;
2655         }
2656         *pdata = data;
2657         return 0;
2658 }
2659 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2660
2661 /*
2662  * Read or write a bunch of msrs. All parameters are kernel addresses.
2663  *
2664  * @return number of msrs set successfully.
2665  */
2666 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2667                     struct kvm_msr_entry *entries,
2668                     int (*do_msr)(struct kvm_vcpu *vcpu,
2669                                   unsigned index, u64 *data))
2670 {
2671         int i, idx;
2672
2673         idx = srcu_read_lock(&vcpu->kvm->srcu);
2674         for (i = 0; i < msrs->nmsrs; ++i)
2675                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2676                         break;
2677         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2678
2679         return i;
2680 }
2681
2682 /*
2683  * Read or write a bunch of msrs. Parameters are user addresses.
2684  *
2685  * @return number of msrs set successfully.
2686  */
2687 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2688                   int (*do_msr)(struct kvm_vcpu *vcpu,
2689                                 unsigned index, u64 *data),
2690                   int writeback)
2691 {
2692         struct kvm_msrs msrs;
2693         struct kvm_msr_entry *entries;
2694         int r, n;
2695         unsigned size;
2696
2697         r = -EFAULT;
2698         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2699                 goto out;
2700
2701         r = -E2BIG;
2702         if (msrs.nmsrs >= MAX_IO_MSRS)
2703                 goto out;
2704
2705         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2706         entries = memdup_user(user_msrs->entries, size);
2707         if (IS_ERR(entries)) {
2708                 r = PTR_ERR(entries);
2709                 goto out;
2710         }
2711
2712         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2713         if (r < 0)
2714                 goto out_free;
2715
2716         r = -EFAULT;
2717         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2718                 goto out_free;
2719
2720         r = n;
2721
2722 out_free:
2723         kfree(entries);
2724 out:
2725         return r;
2726 }
2727
2728 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2729 {
2730         int r;
2731
2732         switch (ext) {
2733         case KVM_CAP_IRQCHIP:
2734         case KVM_CAP_HLT:
2735         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2736         case KVM_CAP_SET_TSS_ADDR:
2737         case KVM_CAP_EXT_CPUID:
2738         case KVM_CAP_EXT_EMUL_CPUID:
2739         case KVM_CAP_CLOCKSOURCE:
2740         case KVM_CAP_PIT:
2741         case KVM_CAP_NOP_IO_DELAY:
2742         case KVM_CAP_MP_STATE:
2743         case KVM_CAP_SYNC_MMU:
2744         case KVM_CAP_USER_NMI:
2745         case KVM_CAP_REINJECT_CONTROL:
2746         case KVM_CAP_IRQ_INJECT_STATUS:
2747         case KVM_CAP_IRQFD:
2748         case KVM_CAP_IOEVENTFD:
2749         case KVM_CAP_IOEVENTFD_NO_LENGTH:
2750         case KVM_CAP_PIT2:
2751         case KVM_CAP_PIT_STATE2:
2752         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2753         case KVM_CAP_XEN_HVM:
2754         case KVM_CAP_ADJUST_CLOCK:
2755         case KVM_CAP_VCPU_EVENTS:
2756         case KVM_CAP_HYPERV:
2757         case KVM_CAP_HYPERV_VAPIC:
2758         case KVM_CAP_HYPERV_SPIN:
2759         case KVM_CAP_PCI_SEGMENT:
2760         case KVM_CAP_DEBUGREGS:
2761         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2762         case KVM_CAP_XSAVE:
2763         case KVM_CAP_ASYNC_PF:
2764         case KVM_CAP_GET_TSC_KHZ:
2765         case KVM_CAP_KVMCLOCK_CTRL:
2766         case KVM_CAP_READONLY_MEM:
2767         case KVM_CAP_HYPERV_TIME:
2768         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2769         case KVM_CAP_TSC_DEADLINE_TIMER:
2770 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2771         case KVM_CAP_ASSIGN_DEV_IRQ:
2772         case KVM_CAP_PCI_2_3:
2773 #endif
2774                 r = 1;
2775                 break;
2776         case KVM_CAP_COALESCED_MMIO:
2777                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2778                 break;
2779         case KVM_CAP_VAPIC:
2780                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2781                 break;
2782         case KVM_CAP_NR_VCPUS:
2783                 r = KVM_SOFT_MAX_VCPUS;
2784                 break;
2785         case KVM_CAP_MAX_VCPUS:
2786                 r = KVM_MAX_VCPUS;
2787                 break;
2788         case KVM_CAP_NR_MEMSLOTS:
2789                 r = KVM_USER_MEM_SLOTS;
2790                 break;
2791         case KVM_CAP_PV_MMU:    /* obsolete */
2792                 r = 0;
2793                 break;
2794 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2795         case KVM_CAP_IOMMU:
2796                 r = iommu_present(&pci_bus_type);
2797                 break;
2798 #endif
2799         case KVM_CAP_MCE:
2800                 r = KVM_MAX_MCE_BANKS;
2801                 break;
2802         case KVM_CAP_XCRS:
2803                 r = cpu_has_xsave;
2804                 break;
2805         case KVM_CAP_TSC_CONTROL:
2806                 r = kvm_has_tsc_control;
2807                 break;
2808         default:
2809                 r = 0;
2810                 break;
2811         }
2812         return r;
2813
2814 }
2815
2816 long kvm_arch_dev_ioctl(struct file *filp,
2817                         unsigned int ioctl, unsigned long arg)
2818 {
2819         void __user *argp = (void __user *)arg;
2820         long r;
2821
2822         switch (ioctl) {
2823         case KVM_GET_MSR_INDEX_LIST: {
2824                 struct kvm_msr_list __user *user_msr_list = argp;
2825                 struct kvm_msr_list msr_list;
2826                 unsigned n;
2827
2828                 r = -EFAULT;
2829                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2830                         goto out;
2831                 n = msr_list.nmsrs;
2832                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2833                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2834                         goto out;
2835                 r = -E2BIG;
2836                 if (n < msr_list.nmsrs)
2837                         goto out;
2838                 r = -EFAULT;
2839                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2840                                  num_msrs_to_save * sizeof(u32)))
2841                         goto out;
2842                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2843                                  &emulated_msrs,
2844                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2845                         goto out;
2846                 r = 0;
2847                 break;
2848         }
2849         case KVM_GET_SUPPORTED_CPUID:
2850         case KVM_GET_EMULATED_CPUID: {
2851                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2852                 struct kvm_cpuid2 cpuid;
2853
2854                 r = -EFAULT;
2855                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2856                         goto out;
2857
2858                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2859                                             ioctl);
2860                 if (r)
2861                         goto out;
2862
2863                 r = -EFAULT;
2864                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2865                         goto out;
2866                 r = 0;
2867                 break;
2868         }
2869         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2870                 u64 mce_cap;
2871
2872                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2873                 r = -EFAULT;
2874                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2875                         goto out;
2876                 r = 0;
2877                 break;
2878         }
2879         default:
2880                 r = -EINVAL;
2881         }
2882 out:
2883         return r;
2884 }
2885
2886 static void wbinvd_ipi(void *garbage)
2887 {
2888         wbinvd();
2889 }
2890
2891 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2892 {
2893         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2894 }
2895
2896 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2897 {
2898         /* Address WBINVD may be executed by guest */
2899         if (need_emulate_wbinvd(vcpu)) {
2900                 if (kvm_x86_ops->has_wbinvd_exit())
2901                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2902                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2903                         smp_call_function_single(vcpu->cpu,
2904                                         wbinvd_ipi, NULL, 1);
2905         }
2906
2907         kvm_x86_ops->vcpu_load(vcpu, cpu);
2908
2909         /* Apply any externally detected TSC adjustments (due to suspend) */
2910         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2911                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2912                 vcpu->arch.tsc_offset_adjustment = 0;
2913                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2914         }
2915
2916         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2917                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2918                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2919                 if (tsc_delta < 0)
2920                         mark_tsc_unstable("KVM discovered backwards TSC");
2921                 if (check_tsc_unstable()) {
2922                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2923                                                 vcpu->arch.last_guest_tsc);
2924                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2925                         vcpu->arch.tsc_catchup = 1;
2926                 }
2927                 /*
2928                  * On a host with synchronized TSC, there is no need to update
2929                  * kvmclock on vcpu->cpu migration
2930                  */
2931                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2932                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2933                 if (vcpu->cpu != cpu)
2934                         kvm_migrate_timers(vcpu);
2935                 vcpu->cpu = cpu;
2936         }
2937
2938         accumulate_steal_time(vcpu);
2939         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2940 }
2941
2942 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2943 {
2944         kvm_x86_ops->vcpu_put(vcpu);
2945         kvm_put_guest_fpu(vcpu);
2946         vcpu->arch.last_host_tsc = native_read_tsc();
2947 }
2948
2949 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2950                                     struct kvm_lapic_state *s)
2951 {
2952         kvm_x86_ops->sync_pir_to_irr(vcpu);
2953         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2954
2955         return 0;
2956 }
2957
2958 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2959                                     struct kvm_lapic_state *s)
2960 {
2961         kvm_apic_post_state_restore(vcpu, s);
2962         update_cr8_intercept(vcpu);
2963
2964         return 0;
2965 }
2966
2967 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2968                                     struct kvm_interrupt *irq)
2969 {
2970         if (irq->irq >= KVM_NR_INTERRUPTS)
2971                 return -EINVAL;
2972         if (irqchip_in_kernel(vcpu->kvm))
2973                 return -ENXIO;
2974
2975         kvm_queue_interrupt(vcpu, irq->irq, false);
2976         kvm_make_request(KVM_REQ_EVENT, vcpu);
2977
2978         return 0;
2979 }
2980
2981 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2982 {
2983         kvm_inject_nmi(vcpu);
2984
2985         return 0;
2986 }
2987
2988 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2989                                            struct kvm_tpr_access_ctl *tac)
2990 {
2991         if (tac->flags)
2992                 return -EINVAL;
2993         vcpu->arch.tpr_access_reporting = !!tac->enabled;
2994         return 0;
2995 }
2996
2997 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2998                                         u64 mcg_cap)
2999 {
3000         int r;
3001         unsigned bank_num = mcg_cap & 0xff, bank;
3002
3003         r = -EINVAL;
3004         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3005                 goto out;
3006         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3007                 goto out;
3008         r = 0;
3009         vcpu->arch.mcg_cap = mcg_cap;
3010         /* Init IA32_MCG_CTL to all 1s */
3011         if (mcg_cap & MCG_CTL_P)
3012                 vcpu->arch.mcg_ctl = ~(u64)0;
3013         /* Init IA32_MCi_CTL to all 1s */
3014         for (bank = 0; bank < bank_num; bank++)
3015                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3016 out:
3017         return r;
3018 }
3019
3020 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3021                                       struct kvm_x86_mce *mce)
3022 {
3023         u64 mcg_cap = vcpu->arch.mcg_cap;
3024         unsigned bank_num = mcg_cap & 0xff;
3025         u64 *banks = vcpu->arch.mce_banks;
3026
3027         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3028                 return -EINVAL;
3029         /*
3030          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3031          * reporting is disabled
3032          */
3033         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3034             vcpu->arch.mcg_ctl != ~(u64)0)
3035                 return 0;
3036         banks += 4 * mce->bank;
3037         /*
3038          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3039          * reporting is disabled for the bank
3040          */
3041         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3042                 return 0;
3043         if (mce->status & MCI_STATUS_UC) {
3044                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3045                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3046                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3047                         return 0;
3048                 }
3049                 if (banks[1] & MCI_STATUS_VAL)
3050                         mce->status |= MCI_STATUS_OVER;
3051                 banks[2] = mce->addr;
3052                 banks[3] = mce->misc;
3053                 vcpu->arch.mcg_status = mce->mcg_status;
3054                 banks[1] = mce->status;
3055                 kvm_queue_exception(vcpu, MC_VECTOR);
3056         } else if (!(banks[1] & MCI_STATUS_VAL)
3057                    || !(banks[1] & MCI_STATUS_UC)) {
3058                 if (banks[1] & MCI_STATUS_VAL)
3059                         mce->status |= MCI_STATUS_OVER;
3060                 banks[2] = mce->addr;
3061                 banks[3] = mce->misc;
3062                 banks[1] = mce->status;
3063         } else
3064                 banks[1] |= MCI_STATUS_OVER;
3065         return 0;
3066 }
3067
3068 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3069                                                struct kvm_vcpu_events *events)
3070 {
3071         process_nmi(vcpu);
3072         events->exception.injected =
3073                 vcpu->arch.exception.pending &&
3074                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3075         events->exception.nr = vcpu->arch.exception.nr;
3076         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3077         events->exception.pad = 0;
3078         events->exception.error_code = vcpu->arch.exception.error_code;
3079
3080         events->interrupt.injected =
3081                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3082         events->interrupt.nr = vcpu->arch.interrupt.nr;
3083         events->interrupt.soft = 0;
3084         events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3085
3086         events->nmi.injected = vcpu->arch.nmi_injected;
3087         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3088         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3089         events->nmi.pad = 0;
3090
3091         events->sipi_vector = 0; /* never valid when reporting to user space */
3092
3093         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3094                          | KVM_VCPUEVENT_VALID_SHADOW);
3095         memset(&events->reserved, 0, sizeof(events->reserved));
3096 }
3097
3098 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3099                                               struct kvm_vcpu_events *events)
3100 {
3101         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3102                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3103                               | KVM_VCPUEVENT_VALID_SHADOW))
3104                 return -EINVAL;
3105
3106         process_nmi(vcpu);
3107         vcpu->arch.exception.pending = events->exception.injected;
3108         vcpu->arch.exception.nr = events->exception.nr;
3109         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3110         vcpu->arch.exception.error_code = events->exception.error_code;
3111
3112         vcpu->arch.interrupt.pending = events->interrupt.injected;
3113         vcpu->arch.interrupt.nr = events->interrupt.nr;
3114         vcpu->arch.interrupt.soft = events->interrupt.soft;
3115         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3116                 kvm_x86_ops->set_interrupt_shadow(vcpu,
3117                                                   events->interrupt.shadow);
3118
3119         vcpu->arch.nmi_injected = events->nmi.injected;
3120         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3121                 vcpu->arch.nmi_pending = events->nmi.pending;
3122         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3123
3124         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3125             kvm_vcpu_has_lapic(vcpu))
3126                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3127
3128         kvm_make_request(KVM_REQ_EVENT, vcpu);
3129
3130         return 0;
3131 }
3132
3133 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3134                                              struct kvm_debugregs *dbgregs)
3135 {
3136         unsigned long val;
3137
3138         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3139         kvm_get_dr(vcpu, 6, &val);
3140         dbgregs->dr6 = val;
3141         dbgregs->dr7 = vcpu->arch.dr7;
3142         dbgregs->flags = 0;
3143         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3144 }
3145
3146 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3147                                             struct kvm_debugregs *dbgregs)
3148 {
3149         if (dbgregs->flags)
3150                 return -EINVAL;
3151
3152         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3153         vcpu->arch.dr6 = dbgregs->dr6;
3154         kvm_update_dr6(vcpu);
3155         vcpu->arch.dr7 = dbgregs->dr7;
3156         kvm_update_dr7(vcpu);
3157
3158         return 0;
3159 }
3160
3161 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3162
3163 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3164 {
3165         struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3166         u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3167         u64 valid;
3168
3169         /*
3170          * Copy legacy XSAVE area, to avoid complications with CPUID
3171          * leaves 0 and 1 in the loop below.
3172          */
3173         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3174
3175         /* Set XSTATE_BV */
3176         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3177
3178         /*
3179          * Copy each region from the possibly compacted offset to the
3180          * non-compacted offset.
3181          */
3182         valid = xstate_bv & ~XSTATE_FPSSE;
3183         while (valid) {
3184                 u64 feature = valid & -valid;
3185                 int index = fls64(feature) - 1;
3186                 void *src = get_xsave_addr(xsave, feature);
3187
3188                 if (src) {
3189                         u32 size, offset, ecx, edx;
3190                         cpuid_count(XSTATE_CPUID, index,
3191                                     &size, &offset, &ecx, &edx);
3192                         memcpy(dest + offset, src, size);
3193                 }
3194
3195                 valid -= feature;
3196         }
3197 }
3198
3199 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3200 {
3201         struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3202         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3203         u64 valid;
3204
3205         /*
3206          * Copy legacy XSAVE area, to avoid complications with CPUID
3207          * leaves 0 and 1 in the loop below.
3208          */
3209         memcpy(xsave, src, XSAVE_HDR_OFFSET);
3210
3211         /* Set XSTATE_BV and possibly XCOMP_BV.  */
3212         xsave->xsave_hdr.xstate_bv = xstate_bv;
3213         if (cpu_has_xsaves)
3214                 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3215
3216         /*
3217          * Copy each region from the non-compacted offset to the
3218          * possibly compacted offset.
3219          */
3220         valid = xstate_bv & ~XSTATE_FPSSE;
3221         while (valid) {
3222                 u64 feature = valid & -valid;
3223                 int index = fls64(feature) - 1;
3224                 void *dest = get_xsave_addr(xsave, feature);
3225
3226                 if (dest) {
3227                         u32 size, offset, ecx, edx;
3228                         cpuid_count(XSTATE_CPUID, index,
3229                                     &size, &offset, &ecx, &edx);
3230                         memcpy(dest, src + offset, size);
3231                 } else
3232                         WARN_ON_ONCE(1);
3233
3234                 valid -= feature;
3235         }
3236 }
3237
3238 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3239                                          struct kvm_xsave *guest_xsave)
3240 {
3241         if (cpu_has_xsave) {
3242                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3243                 fill_xsave((u8 *) guest_xsave->region, vcpu);
3244         } else {
3245                 memcpy(guest_xsave->region,
3246                         &vcpu->arch.guest_fpu.state->fxsave,
3247                         sizeof(struct i387_fxsave_struct));
3248                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3249                         XSTATE_FPSSE;
3250         }
3251 }
3252
3253 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3254                                         struct kvm_xsave *guest_xsave)
3255 {
3256         u64 xstate_bv =
3257                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3258
3259         if (cpu_has_xsave) {
3260                 /*
3261                  * Here we allow setting states that are not present in
3262                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3263                  * with old userspace.
3264                  */
3265                 if (xstate_bv & ~kvm_supported_xcr0())
3266                         return -EINVAL;
3267                 load_xsave(vcpu, (u8 *)guest_xsave->region);
3268         } else {
3269                 if (xstate_bv & ~XSTATE_FPSSE)
3270                         return -EINVAL;
3271                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3272                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
3273         }
3274         return 0;
3275 }
3276
3277 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3278                                         struct kvm_xcrs *guest_xcrs)
3279 {
3280         if (!cpu_has_xsave) {
3281                 guest_xcrs->nr_xcrs = 0;
3282                 return;
3283         }
3284
3285         guest_xcrs->nr_xcrs = 1;
3286         guest_xcrs->flags = 0;
3287         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3288         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3289 }
3290
3291 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3292                                        struct kvm_xcrs *guest_xcrs)
3293 {
3294         int i, r = 0;
3295
3296         if (!cpu_has_xsave)
3297                 return -EINVAL;
3298
3299         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3300                 return -EINVAL;
3301
3302         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3303                 /* Only support XCR0 currently */
3304                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3305                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3306                                 guest_xcrs->xcrs[i].value);
3307                         break;
3308                 }
3309         if (r)
3310                 r = -EINVAL;
3311         return r;
3312 }
3313
3314 /*
3315  * kvm_set_guest_paused() indicates to the guest kernel that it has been
3316  * stopped by the hypervisor.  This function will be called from the host only.
3317  * EINVAL is returned when the host attempts to set the flag for a guest that
3318  * does not support pv clocks.
3319  */
3320 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3321 {
3322         if (!vcpu->arch.pv_time_enabled)
3323                 return -EINVAL;
3324         vcpu->arch.pvclock_set_guest_stopped_request = true;
3325         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3326         return 0;
3327 }
3328
3329 long kvm_arch_vcpu_ioctl(struct file *filp,
3330                          unsigned int ioctl, unsigned long arg)
3331 {
3332         struct kvm_vcpu *vcpu = filp->private_data;
3333         void __user *argp = (void __user *)arg;
3334         int r;
3335         union {
3336                 struct kvm_lapic_state *lapic;
3337                 struct kvm_xsave *xsave;
3338                 struct kvm_xcrs *xcrs;
3339                 void *buffer;
3340         } u;
3341
3342         u.buffer = NULL;
3343         switch (ioctl) {
3344         case KVM_GET_LAPIC: {
3345                 r = -EINVAL;
3346                 if (!vcpu->arch.apic)
3347                         goto out;
3348                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3349
3350                 r = -ENOMEM;
3351                 if (!u.lapic)
3352                         goto out;
3353                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3354                 if (r)
3355                         goto out;
3356                 r = -EFAULT;
3357                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3358                         goto out;
3359                 r = 0;
3360                 break;
3361         }
3362         case KVM_SET_LAPIC: {
3363                 r = -EINVAL;
3364                 if (!vcpu->arch.apic)
3365                         goto out;
3366                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3367                 if (IS_ERR(u.lapic))
3368                         return PTR_ERR(u.lapic);
3369
3370                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3371                 break;
3372         }
3373         case KVM_INTERRUPT: {
3374                 struct kvm_interrupt irq;
3375
3376                 r = -EFAULT;
3377                 if (copy_from_user(&irq, argp, sizeof irq))
3378                         goto out;
3379                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3380                 break;
3381         }
3382         case KVM_NMI: {
3383                 r = kvm_vcpu_ioctl_nmi(vcpu);
3384                 break;
3385         }
3386         case KVM_SET_CPUID: {
3387                 struct kvm_cpuid __user *cpuid_arg = argp;
3388                 struct kvm_cpuid cpuid;
3389
3390                 r = -EFAULT;
3391                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3392                         goto out;
3393                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3394                 break;
3395         }
3396         case KVM_SET_CPUID2: {
3397                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3398                 struct kvm_cpuid2 cpuid;
3399
3400                 r = -EFAULT;
3401                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3402                         goto out;
3403                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3404                                               cpuid_arg->entries);
3405                 break;
3406         }
3407         case KVM_GET_CPUID2: {
3408                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3409                 struct kvm_cpuid2 cpuid;
3410
3411                 r = -EFAULT;
3412                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3413                         goto out;
3414                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3415                                               cpuid_arg->entries);
3416                 if (r)
3417                         goto out;
3418                 r = -EFAULT;
3419                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3420                         goto out;
3421                 r = 0;
3422                 break;
3423         }
3424         case KVM_GET_MSRS:
3425                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3426                 break;
3427         case KVM_SET_MSRS:
3428                 r = msr_io(vcpu, argp, do_set_msr, 0);
3429                 break;
3430         case KVM_TPR_ACCESS_REPORTING: {
3431                 struct kvm_tpr_access_ctl tac;
3432
3433                 r = -EFAULT;
3434                 if (copy_from_user(&tac, argp, sizeof tac))
3435                         goto out;
3436                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3437                 if (r)
3438                         goto out;
3439                 r = -EFAULT;
3440                 if (copy_to_user(argp, &tac, sizeof tac))
3441                         goto out;
3442                 r = 0;
3443                 break;
3444         };
3445         case KVM_SET_VAPIC_ADDR: {
3446                 struct kvm_vapic_addr va;
3447
3448                 r = -EINVAL;
3449                 if (!irqchip_in_kernel(vcpu->kvm))
3450                         goto out;
3451                 r = -EFAULT;
3452                 if (copy_from_user(&va, argp, sizeof va))
3453                         goto out;
3454                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3455                 break;
3456         }
3457         case KVM_X86_SETUP_MCE: {
3458                 u64 mcg_cap;
3459
3460                 r = -EFAULT;
3461                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3462                         goto out;
3463                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3464                 break;
3465         }
3466         case KVM_X86_SET_MCE: {
3467                 struct kvm_x86_mce mce;
3468
3469                 r = -EFAULT;
3470                 if (copy_from_user(&mce, argp, sizeof mce))
3471                         goto out;
3472                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3473                 break;
3474         }
3475         case KVM_GET_VCPU_EVENTS: {
3476                 struct kvm_vcpu_events events;
3477
3478                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3479
3480                 r = -EFAULT;
3481                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3482                         break;
3483                 r = 0;
3484                 break;
3485         }
3486         case KVM_SET_VCPU_EVENTS: {
3487                 struct kvm_vcpu_events events;
3488
3489                 r = -EFAULT;
3490                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3491                         break;
3492
3493                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3494                 break;
3495         }
3496         case KVM_GET_DEBUGREGS: {
3497                 struct kvm_debugregs dbgregs;
3498
3499                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3500
3501                 r = -EFAULT;
3502                 if (copy_to_user(argp, &dbgregs,
3503                                  sizeof(struct kvm_debugregs)))
3504                         break;
3505                 r = 0;
3506                 break;
3507         }
3508         case KVM_SET_DEBUGREGS: {
3509                 struct kvm_debugregs dbgregs;
3510
3511                 r = -EFAULT;
3512                 if (copy_from_user(&dbgregs, argp,
3513                                    sizeof(struct kvm_debugregs)))
3514                         break;
3515
3516                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3517                 break;
3518         }
3519         case KVM_GET_XSAVE: {
3520                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3521                 r = -ENOMEM;
3522                 if (!u.xsave)
3523                         break;
3524
3525                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3526
3527                 r = -EFAULT;
3528                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3529                         break;
3530                 r = 0;
3531                 break;
3532         }
3533         case KVM_SET_XSAVE: {
3534                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3535                 if (IS_ERR(u.xsave))
3536                         return PTR_ERR(u.xsave);
3537
3538                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3539                 break;
3540         }
3541         case KVM_GET_XCRS: {
3542                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3543                 r = -ENOMEM;
3544                 if (!u.xcrs)
3545                         break;
3546
3547                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3548
3549                 r = -EFAULT;
3550                 if (copy_to_user(argp, u.xcrs,
3551                                  sizeof(struct kvm_xcrs)))
3552                         break;
3553                 r = 0;
3554                 break;
3555         }
3556         case KVM_SET_XCRS: {
3557                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3558                 if (IS_ERR(u.xcrs))
3559                         return PTR_ERR(u.xcrs);
3560
3561                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3562                 break;
3563         }
3564         case KVM_SET_TSC_KHZ: {
3565                 u32 user_tsc_khz;
3566
3567                 r = -EINVAL;
3568                 user_tsc_khz = (u32)arg;
3569
3570                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3571                         goto out;
3572
3573                 if (user_tsc_khz == 0)
3574                         user_tsc_khz = tsc_khz;
3575
3576                 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3577
3578                 r = 0;
3579                 goto out;
3580         }
3581         case KVM_GET_TSC_KHZ: {
3582                 r = vcpu->arch.virtual_tsc_khz;
3583                 goto out;
3584         }
3585         case KVM_KVMCLOCK_CTRL: {
3586                 r = kvm_set_guest_paused(vcpu);
3587                 goto out;
3588         }
3589         default:
3590                 r = -EINVAL;
3591         }
3592 out:
3593         kfree(u.buffer);
3594         return r;
3595 }
3596
3597 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3598 {
3599         return VM_FAULT_SIGBUS;
3600 }
3601
3602 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3603 {
3604         int ret;
3605
3606         if (addr > (unsigned int)(-3 * PAGE_SIZE))
3607                 return -EINVAL;
3608         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3609         return ret;
3610 }
3611
3612 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3613                                               u64 ident_addr)
3614 {
3615         kvm->arch.ept_identity_map_addr = ident_addr;
3616         return 0;
3617 }
3618
3619 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3620                                           u32 kvm_nr_mmu_pages)
3621 {
3622         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3623                 return -EINVAL;
3624
3625         mutex_lock(&kvm->slots_lock);
3626
3627         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3628         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3629
3630         mutex_unlock(&kvm->slots_lock);
3631         return 0;
3632 }
3633
3634 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3635 {
3636         return kvm->arch.n_max_mmu_pages;
3637 }
3638
3639 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3640 {
3641         int r;
3642
3643         r = 0;
3644         switch (chip->chip_id) {
3645         case KVM_IRQCHIP_PIC_MASTER:
3646                 memcpy(&chip->chip.pic,
3647                         &pic_irqchip(kvm)->pics[0],
3648                         sizeof(struct kvm_pic_state));
3649                 break;
3650         case KVM_IRQCHIP_PIC_SLAVE:
3651                 memcpy(&chip->chip.pic,
3652                         &pic_irqchip(kvm)->pics[1],
3653                         sizeof(struct kvm_pic_state));
3654                 break;
3655         case KVM_IRQCHIP_IOAPIC:
3656                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3657                 break;
3658         default:
3659                 r = -EINVAL;
3660                 break;
3661         }
3662         return r;
3663 }
3664
3665 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3666 {
3667         int r;
3668
3669         r = 0;
3670         switch (chip->chip_id) {
3671         case KVM_IRQCHIP_PIC_MASTER:
3672                 spin_lock(&pic_irqchip(kvm)->lock);
3673                 memcpy(&pic_irqchip(kvm)->pics[0],
3674                         &chip->chip.pic,
3675                         sizeof(struct kvm_pic_state));
3676                 spin_unlock(&pic_irqchip(kvm)->lock);
3677                 break;
3678         case KVM_IRQCHIP_PIC_SLAVE:
3679                 spin_lock(&pic_irqchip(kvm)->lock);
3680                 memcpy(&pic_irqchip(kvm)->pics[1],
3681                         &chip->chip.pic,
3682                         sizeof(struct kvm_pic_state));
3683                 spin_unlock(&pic_irqchip(kvm)->lock);
3684                 break;
3685         case KVM_IRQCHIP_IOAPIC:
3686                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3687                 break;
3688         default:
3689                 r = -EINVAL;
3690                 break;
3691         }
3692         kvm_pic_update_irq(pic_irqchip(kvm));
3693         return r;
3694 }
3695
3696 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3697 {
3698         int r = 0;
3699
3700         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3701         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3702         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3703         return r;
3704 }
3705
3706 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3707 {
3708         int r = 0;
3709
3710         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3711         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3712         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3713         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3714         return r;
3715 }
3716
3717 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3718 {
3719         int r = 0;
3720
3721         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3722         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3723                 sizeof(ps->channels));
3724         ps->flags = kvm->arch.vpit->pit_state.flags;
3725         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3726         memset(&ps->reserved, 0, sizeof(ps->reserved));
3727         return r;
3728 }
3729
3730 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3731 {
3732         int r = 0, start = 0;
3733         u32 prev_legacy, cur_legacy;
3734         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3735         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3736         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3737         if (!prev_legacy && cur_legacy)
3738                 start = 1;
3739         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3740                sizeof(kvm->arch.vpit->pit_state.channels));
3741         kvm->arch.vpit->pit_state.flags = ps->flags;
3742         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3743         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3744         return r;
3745 }
3746
3747 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3748                                  struct kvm_reinject_control *control)
3749 {
3750         if (!kvm->arch.vpit)
3751                 return -ENXIO;
3752         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3753         kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3754         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3755         return 0;
3756 }
3757
3758 /**
3759  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3760  * @kvm: kvm instance
3761  * @log: slot id and address to which we copy the log
3762  *
3763  * Steps 1-4 below provide general overview of dirty page logging. See
3764  * kvm_get_dirty_log_protect() function description for additional details.
3765  *
3766  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3767  * always flush the TLB (step 4) even if previous step failed  and the dirty
3768  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3769  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3770  * writes will be marked dirty for next log read.
3771  *
3772  *   1. Take a snapshot of the bit and clear it if needed.
3773  *   2. Write protect the corresponding page.
3774  *   3. Copy the snapshot to the userspace.
3775  *   4. Flush TLB's if needed.
3776  */
3777 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3778 {
3779         bool is_dirty = false;
3780         int r;
3781
3782         mutex_lock(&kvm->slots_lock);
3783
3784         /*
3785          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3786          */
3787         if (kvm_x86_ops->flush_log_dirty)
3788                 kvm_x86_ops->flush_log_dirty(kvm);
3789
3790         r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3791
3792         /*
3793          * All the TLBs can be flushed out of mmu lock, see the comments in
3794          * kvm_mmu_slot_remove_write_access().
3795          */
3796         lockdep_assert_held(&kvm->slots_lock);
3797         if (is_dirty)
3798                 kvm_flush_remote_tlbs(kvm);
3799
3800         mutex_unlock(&kvm->slots_lock);
3801         return r;
3802 }
3803
3804 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3805                         bool line_status)
3806 {
3807         if (!irqchip_in_kernel(kvm))
3808                 return -ENXIO;
3809
3810         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3811                                         irq_event->irq, irq_event->level,
3812                                         line_status);
3813         return 0;
3814 }
3815
3816 long kvm_arch_vm_ioctl(struct file *filp,
3817                        unsigned int ioctl, unsigned long arg)
3818 {
3819         struct kvm *kvm = filp->private_data;
3820         void __user *argp = (void __user *)arg;
3821         int r = -ENOTTY;
3822         /*
3823          * This union makes it completely explicit to gcc-3.x
3824          * that these two variables' stack usage should be
3825          * combined, not added together.
3826          */
3827         union {
3828                 struct kvm_pit_state ps;
3829                 struct kvm_pit_state2 ps2;
3830                 struct kvm_pit_config pit_config;
3831         } u;
3832
3833         switch (ioctl) {
3834         case KVM_SET_TSS_ADDR:
3835                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3836                 break;
3837         case KVM_SET_IDENTITY_MAP_ADDR: {
3838                 u64 ident_addr;
3839
3840                 r = -EFAULT;
3841                 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3842                         goto out;
3843                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3844                 break;
3845         }
3846         case KVM_SET_NR_MMU_PAGES:
3847                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3848                 break;
3849         case KVM_GET_NR_MMU_PAGES:
3850                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3851                 break;
3852         case KVM_CREATE_IRQCHIP: {
3853                 struct kvm_pic *vpic;
3854
3855                 mutex_lock(&kvm->lock);
3856                 r = -EEXIST;
3857                 if (kvm->arch.vpic)
3858                         goto create_irqchip_unlock;
3859                 r = -EINVAL;
3860                 if (atomic_read(&kvm->online_vcpus))
3861                         goto create_irqchip_unlock;
3862                 r = -ENOMEM;
3863                 vpic = kvm_create_pic(kvm);
3864                 if (vpic) {
3865                         r = kvm_ioapic_init(kvm);
3866                         if (r) {
3867                                 mutex_lock(&kvm->slots_lock);
3868                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3869                                                           &vpic->dev_master);
3870                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3871                                                           &vpic->dev_slave);
3872                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3873                                                           &vpic->dev_eclr);
3874                                 mutex_unlock(&kvm->slots_lock);
3875                                 kfree(vpic);
3876                                 goto create_irqchip_unlock;
3877                         }
3878                 } else
3879                         goto create_irqchip_unlock;
3880                 smp_wmb();
3881                 kvm->arch.vpic = vpic;
3882                 smp_wmb();
3883                 r = kvm_setup_default_irq_routing(kvm);
3884                 if (r) {
3885                         mutex_lock(&kvm->slots_lock);
3886                         mutex_lock(&kvm->irq_lock);
3887                         kvm_ioapic_destroy(kvm);
3888                         kvm_destroy_pic(kvm);
3889                         mutex_unlock(&kvm->irq_lock);
3890                         mutex_unlock(&kvm->slots_lock);
3891                 }
3892         create_irqchip_unlock:
3893                 mutex_unlock(&kvm->lock);
3894                 break;
3895         }
3896         case KVM_CREATE_PIT:
3897                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3898                 goto create_pit;
3899         case KVM_CREATE_PIT2:
3900                 r = -EFAULT;
3901                 if (copy_from_user(&u.pit_config, argp,
3902                                    sizeof(struct kvm_pit_config)))
3903                         goto out;
3904         create_pit:
3905                 mutex_lock(&kvm->slots_lock);
3906                 r = -EEXIST;
3907                 if (kvm->arch.vpit)
3908                         goto create_pit_unlock;
3909                 r = -ENOMEM;
3910                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3911                 if (kvm->arch.vpit)
3912                         r = 0;
3913         create_pit_unlock:
3914                 mutex_unlock(&kvm->slots_lock);
3915                 break;
3916         case KVM_GET_IRQCHIP: {
3917                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3918                 struct kvm_irqchip *chip;
3919
3920                 chip = memdup_user(argp, sizeof(*chip));
3921                 if (IS_ERR(chip)) {
3922                         r = PTR_ERR(chip);
3923                         goto out;
3924                 }
3925
3926                 r = -ENXIO;
3927                 if (!irqchip_in_kernel(kvm))
3928                         goto get_irqchip_out;
3929                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3930                 if (r)
3931                         goto get_irqchip_out;
3932                 r = -EFAULT;
3933                 if (copy_to_user(argp, chip, sizeof *chip))
3934                         goto get_irqchip_out;
3935                 r = 0;
3936         get_irqchip_out:
3937                 kfree(chip);
3938                 break;
3939         }
3940         case KVM_SET_IRQCHIP: {
3941                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3942                 struct kvm_irqchip *chip;
3943
3944                 chip = memdup_user(argp, sizeof(*chip));
3945                 if (IS_ERR(chip)) {
3946                         r = PTR_ERR(chip);
3947                         goto out;
3948                 }
3949
3950                 r = -ENXIO;
3951                 if (!irqchip_in_kernel(kvm))
3952                         goto set_irqchip_out;
3953                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3954                 if (r)
3955                         goto set_irqchip_out;
3956                 r = 0;
3957         set_irqchip_out:
3958                 kfree(chip);
3959                 break;
3960         }
3961         case KVM_GET_PIT: {
3962                 r = -EFAULT;
3963                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3964                         goto out;
3965                 r = -ENXIO;
3966                 if (!kvm->arch.vpit)
3967                         goto out;
3968                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3969                 if (r)
3970                         goto out;
3971                 r = -EFAULT;
3972                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3973                         goto out;
3974                 r = 0;
3975                 break;
3976         }
3977         case KVM_SET_PIT: {
3978                 r = -EFAULT;
3979                 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3980                         goto out;
3981                 r = -ENXIO;
3982                 if (!kvm->arch.vpit)
3983                         goto out;
3984                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3985                 break;
3986         }
3987         case KVM_GET_PIT2: {
3988                 r = -ENXIO;
3989                 if (!kvm->arch.vpit)
3990                         goto out;
3991                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3992                 if (r)
3993                         goto out;
3994                 r = -EFAULT;
3995                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3996                         goto out;
3997                 r = 0;
3998                 break;
3999         }
4000         case KVM_SET_PIT2: {
4001                 r = -EFAULT;
4002                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4003                         goto out;
4004                 r = -ENXIO;
4005                 if (!kvm->arch.vpit)
4006                         goto out;
4007                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
4008                 break;
4009         }
4010         case KVM_REINJECT_CONTROL: {
4011                 struct kvm_reinject_control control;
4012                 r =  -EFAULT;
4013                 if (copy_from_user(&control, argp, sizeof(control)))
4014                         goto out;
4015                 r = kvm_vm_ioctl_reinject(kvm, &control);
4016                 break;
4017         }
4018         case KVM_XEN_HVM_CONFIG: {
4019                 r = -EFAULT;
4020                 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4021                                    sizeof(struct kvm_xen_hvm_config)))
4022                         goto out;
4023                 r = -EINVAL;
4024                 if (kvm->arch.xen_hvm_config.flags)
4025                         goto out;
4026                 r = 0;
4027                 break;
4028         }
4029         case KVM_SET_CLOCK: {
4030                 struct kvm_clock_data user_ns;
4031                 u64 now_ns;
4032                 s64 delta;
4033
4034                 r = -EFAULT;
4035                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4036                         goto out;
4037
4038                 r = -EINVAL;
4039                 if (user_ns.flags)
4040                         goto out;
4041
4042                 r = 0;
4043                 local_irq_disable();
4044                 now_ns = get_kernel_ns();
4045                 delta = user_ns.clock - now_ns;
4046                 local_irq_enable();
4047                 kvm->arch.kvmclock_offset = delta;
4048                 kvm_gen_update_masterclock(kvm);
4049                 break;
4050         }
4051         case KVM_GET_CLOCK: {
4052                 struct kvm_clock_data user_ns;
4053                 u64 now_ns;
4054
4055                 local_irq_disable();
4056                 now_ns = get_kernel_ns();
4057                 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
4058                 local_irq_enable();
4059                 user_ns.flags = 0;
4060                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
4061
4062                 r = -EFAULT;
4063                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4064                         goto out;
4065                 r = 0;
4066                 break;
4067         }
4068
4069         default:
4070                 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
4071         }
4072 out:
4073         return r;
4074 }
4075
4076 static void kvm_init_msr_list(void)
4077 {
4078         u32 dummy[2];
4079         unsigned i, j;
4080
4081         /* skip the first msrs in the list. KVM-specific */
4082         for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
4083                 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4084                         continue;
4085
4086                 /*
4087                  * Even MSRs that are valid in the host may not be exposed
4088                  * to the guests in some cases.  We could work around this
4089                  * in VMX with the generic MSR save/load machinery, but it
4090                  * is not really worthwhile since it will really only
4091                  * happen with nested virtualization.
4092                  */
4093                 switch (msrs_to_save[i]) {
4094                 case MSR_IA32_BNDCFGS:
4095                         if (!kvm_x86_ops->mpx_supported())
4096                                 continue;
4097                         break;
4098                 default:
4099                         break;
4100                 }
4101
4102                 if (j < i)
4103                         msrs_to_save[j] = msrs_to_save[i];
4104                 j++;
4105         }
4106         num_msrs_to_save = j;
4107 }
4108
4109 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4110                            const void *v)
4111 {
4112         int handled = 0;
4113         int n;
4114
4115         do {
4116                 n = min(len, 8);
4117                 if (!(vcpu->arch.apic &&
4118                       !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4119                     && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4120                         break;
4121                 handled += n;
4122                 addr += n;
4123                 len -= n;
4124                 v += n;
4125         } while (len);
4126
4127         return handled;
4128 }
4129
4130 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
4131 {
4132         int handled = 0;
4133         int n;
4134
4135         do {
4136                 n = min(len, 8);
4137                 if (!(vcpu->arch.apic &&
4138                       !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4139                     && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4140                         break;
4141                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4142                 handled += n;
4143                 addr += n;
4144                 len -= n;
4145                 v += n;
4146         } while (len);
4147
4148         return handled;
4149 }
4150
4151 static void kvm_set_segment(struct kvm_vcpu *vcpu,
4152                         struct kvm_segment *var, int seg)
4153 {
4154         kvm_x86_ops->set_segment(vcpu, var, seg);
4155 }
4156
4157 void kvm_get_segment(struct kvm_vcpu *vcpu,
4158                      struct kvm_segment *var, int seg)
4159 {
4160         kvm_x86_ops->get_segment(vcpu, var, seg);
4161 }
4162
4163 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4164                            struct x86_exception *exception)
4165 {
4166         gpa_t t_gpa;
4167
4168         BUG_ON(!mmu_is_nested(vcpu));
4169
4170         /* NPT walks are always user-walks */
4171         access |= PFERR_USER_MASK;
4172         t_gpa  = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
4173
4174         return t_gpa;
4175 }
4176
4177 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4178                               struct x86_exception *exception)
4179 {
4180         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4181         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4182 }
4183
4184  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4185                                 struct x86_exception *exception)
4186 {
4187         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4188         access |= PFERR_FETCH_MASK;
4189         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4190 }
4191
4192 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4193                                struct x86_exception *exception)
4194 {
4195         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4196         access |= PFERR_WRITE_MASK;
4197         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4198 }
4199
4200 /* uses this to access any guest's mapped memory without checking CPL */
4201 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4202                                 struct x86_exception *exception)
4203 {
4204         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4205 }
4206
4207 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4208                                       struct kvm_vcpu *vcpu, u32 access,
4209                                       struct x86_exception *exception)
4210 {
4211         void *data = val;
4212         int r = X86EMUL_CONTINUE;
4213
4214         while (bytes) {
4215                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4216                                                             exception);
4217                 unsigned offset = addr & (PAGE_SIZE-1);
4218                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4219                 int ret;
4220
4221                 if (gpa == UNMAPPED_GVA)
4222                         return X86EMUL_PROPAGATE_FAULT;
4223                 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4224                                           offset, toread);
4225                 if (ret < 0) {
4226                         r = X86EMUL_IO_NEEDED;
4227                         goto out;
4228                 }
4229
4230                 bytes -= toread;
4231                 data += toread;
4232                 addr += toread;
4233         }
4234 out:
4235         return r;
4236 }
4237
4238 /* used for instruction fetching */
4239 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4240                                 gva_t addr, void *val, unsigned int bytes,
4241                                 struct x86_exception *exception)
4242 {
4243         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4244         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4245         unsigned offset;
4246         int ret;
4247
4248         /* Inline kvm_read_guest_virt_helper for speed.  */
4249         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4250                                                     exception);
4251         if (unlikely(gpa == UNMAPPED_GVA))
4252                 return X86EMUL_PROPAGATE_FAULT;
4253
4254         offset = addr & (PAGE_SIZE-1);
4255         if (WARN_ON(offset + bytes > PAGE_SIZE))
4256                 bytes = (unsigned)PAGE_SIZE - offset;
4257         ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4258                                   offset, bytes);
4259         if (unlikely(ret < 0))
4260                 return X86EMUL_IO_NEEDED;
4261
4262         return X86EMUL_CONTINUE;
4263 }
4264
4265 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4266                                gva_t addr, void *val, unsigned int bytes,
4267                                struct x86_exception *exception)
4268 {
4269         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4270         u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4271
4272         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4273                                           exception);
4274 }
4275 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4276
4277 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4278                                       gva_t addr, void *val, unsigned int bytes,
4279                                       struct x86_exception *exception)
4280 {
4281         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4282         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4283 }
4284
4285 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4286                                        gva_t addr, void *val,
4287                                        unsigned int bytes,
4288                                        struct x86_exception *exception)
4289 {
4290         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4291         void *data = val;
4292         int r = X86EMUL_CONTINUE;
4293
4294         while (bytes) {
4295                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4296                                                              PFERR_WRITE_MASK,
4297                                                              exception);
4298                 unsigned offset = addr & (PAGE_SIZE-1);
4299                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4300                 int ret;
4301
4302                 if (gpa == UNMAPPED_GVA)
4303                         return X86EMUL_PROPAGATE_FAULT;
4304                 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4305                 if (ret < 0) {
4306                         r = X86EMUL_IO_NEEDED;
4307                         goto out;
4308                 }
4309
4310                 bytes -= towrite;
4311                 data += towrite;
4312                 addr += towrite;
4313         }
4314 out:
4315         return r;
4316 }
4317 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4318
4319 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4320                                 gpa_t *gpa, struct x86_exception *exception,
4321                                 bool write)
4322 {
4323         u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4324                 | (write ? PFERR_WRITE_MASK : 0);
4325
4326         if (vcpu_match_mmio_gva(vcpu, gva)
4327             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4328                                  vcpu->arch.access, access)) {
4329                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4330                                         (gva & (PAGE_SIZE - 1));
4331                 trace_vcpu_match_mmio(gva, *gpa, write, false);
4332                 return 1;
4333         }
4334
4335         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4336
4337         if (*gpa == UNMAPPED_GVA)
4338                 return -1;
4339
4340         /* For APIC access vmexit */
4341         if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4342                 return 1;
4343
4344         if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4345                 trace_vcpu_match_mmio(gva, *gpa, write, true);
4346                 return 1;
4347         }
4348
4349         return 0;
4350 }
4351
4352 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4353                         const void *val, int bytes)
4354 {
4355         int ret;
4356
4357         ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4358         if (ret < 0)
4359                 return 0;
4360         kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4361         return 1;
4362 }
4363
4364 struct read_write_emulator_ops {
4365         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4366                                   int bytes);
4367         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4368                                   void *val, int bytes);
4369         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4370                                int bytes, void *val);
4371         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4372                                     void *val, int bytes);
4373         bool write;
4374 };
4375
4376 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4377 {
4378         if (vcpu->mmio_read_completed) {
4379                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4380                                vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4381                 vcpu->mmio_read_completed = 0;
4382                 return 1;
4383         }
4384
4385         return 0;
4386 }
4387
4388 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4389                         void *val, int bytes)
4390 {
4391         return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4392 }
4393
4394 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4395                          void *val, int bytes)
4396 {
4397         return emulator_write_phys(vcpu, gpa, val, bytes);
4398 }
4399
4400 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4401 {
4402         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4403         return vcpu_mmio_write(vcpu, gpa, bytes, val);
4404 }
4405
4406 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4407                           void *val, int bytes)
4408 {
4409         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4410         return X86EMUL_IO_NEEDED;
4411 }
4412
4413 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4414                            void *val, int bytes)
4415 {
4416         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4417
4418         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4419         return X86EMUL_CONTINUE;
4420 }
4421
4422 static const struct read_write_emulator_ops read_emultor = {
4423         .read_write_prepare = read_prepare,
4424         .read_write_emulate = read_emulate,
4425         .read_write_mmio = vcpu_mmio_read,
4426         .read_write_exit_mmio = read_exit_mmio,
4427 };
4428
4429 static const struct read_write_emulator_ops write_emultor = {
4430         .read_write_emulate = write_emulate,
4431         .read_write_mmio = write_mmio,
4432         .read_write_exit_mmio = write_exit_mmio,
4433         .write = true,
4434 };
4435
4436 static int emulator_read_write_onepage(unsigned long addr, void *val,
4437                                        unsigned int bytes,
4438                                        struct x86_exception *exception,
4439                                        struct kvm_vcpu *vcpu,
4440                                        const struct read_write_emulator_ops *ops)
4441 {
4442         gpa_t gpa;
4443         int handled, ret;
4444         bool write = ops->write;
4445         struct kvm_mmio_fragment *frag;
4446
4447         ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4448
4449         if (ret < 0)
4450                 return X86EMUL_PROPAGATE_FAULT;
4451
4452         /* For APIC access vmexit */
4453         if (ret)
4454                 goto mmio;
4455
4456         if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4457                 return X86EMUL_CONTINUE;
4458
4459 mmio:
4460         /*
4461          * Is this MMIO handled locally?
4462          */
4463         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4464         if (handled == bytes)
4465                 return X86EMUL_CONTINUE;
4466
4467         gpa += handled;
4468         bytes -= handled;
4469         val += handled;
4470
4471         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4472         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4473         frag->gpa = gpa;
4474         frag->data = val;
4475         frag->len = bytes;
4476         return X86EMUL_CONTINUE;
4477 }
4478
4479 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4480                         void *val, unsigned int bytes,
4481                         struct x86_exception *exception,
4482                         const struct read_write_emulator_ops *ops)
4483 {
4484         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4485         gpa_t gpa;
4486         int rc;
4487
4488         if (ops->read_write_prepare &&
4489                   ops->read_write_prepare(vcpu, val, bytes))
4490                 return X86EMUL_CONTINUE;
4491
4492         vcpu->mmio_nr_fragments = 0;
4493
4494         /* Crossing a page boundary? */
4495         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4496                 int now;
4497
4498                 now = -addr & ~PAGE_MASK;
4499                 rc = emulator_read_write_onepage(addr, val, now, exception,
4500                                                  vcpu, ops);
4501
4502                 if (rc != X86EMUL_CONTINUE)
4503                         return rc;
4504                 addr += now;
4505                 if (ctxt->mode != X86EMUL_MODE_PROT64)
4506                         addr = (u32)addr;
4507                 val += now;
4508                 bytes -= now;
4509         }
4510
4511         rc = emulator_read_write_onepage(addr, val, bytes, exception,
4512                                          vcpu, ops);
4513         if (rc != X86EMUL_CONTINUE)
4514                 return rc;
4515
4516         if (!vcpu->mmio_nr_fragments)
4517                 return rc;
4518
4519         gpa = vcpu->mmio_fragments[0].gpa;
4520
4521         vcpu->mmio_needed = 1;
4522         vcpu->mmio_cur_fragment = 0;
4523
4524         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4525         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4526         vcpu->run->exit_reason = KVM_EXIT_MMIO;
4527         vcpu->run->mmio.phys_addr = gpa;
4528
4529         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4530 }
4531
4532 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4533                                   unsigned long addr,
4534                                   void *val,
4535                                   unsigned int bytes,
4536                                   struct x86_exception *exception)
4537 {
4538         return emulator_read_write(ctxt, addr, val, bytes,
4539                                    exception, &read_emultor);
4540 }
4541
4542 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4543                             unsigned long addr,
4544                             const void *val,
4545                             unsigned int bytes,
4546                             struct x86_exception *exception)
4547 {
4548         return emulator_read_write(ctxt, addr, (void *)val, bytes,
4549                                    exception, &write_emultor);
4550 }
4551
4552 #define CMPXCHG_TYPE(t, ptr, old, new) \
4553         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4554
4555 #ifdef CONFIG_X86_64
4556 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4557 #else
4558 #  define CMPXCHG64(ptr, old, new) \
4559         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4560 #endif
4561
4562 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4563                                      unsigned long addr,
4564                                      const void *old,
4565                                      const void *new,
4566                                      unsigned int bytes,
4567                                      struct x86_exception *exception)
4568 {
4569         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4570         gpa_t gpa;
4571         struct page *page;
4572         char *kaddr;
4573         bool exchanged;
4574
4575         /* guests cmpxchg8b have to be emulated atomically */
4576         if (bytes > 8 || (bytes & (bytes - 1)))
4577                 goto emul_write;
4578
4579         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4580
4581         if (gpa == UNMAPPED_GVA ||
4582             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4583                 goto emul_write;
4584
4585         if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4586                 goto emul_write;
4587
4588         page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4589         if (is_error_page(page))
4590                 goto emul_write;
4591
4592         kaddr = kmap_atomic(page);
4593         kaddr += offset_in_page(gpa);
4594         switch (bytes) {
4595         case 1:
4596                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4597                 break;
4598         case 2:
4599                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4600                 break;
4601         case 4:
4602                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4603                 break;
4604         case 8:
4605                 exchanged = CMPXCHG64(kaddr, old, new);
4606                 break;
4607         default:
4608                 BUG();
4609         }
4610         kunmap_atomic(kaddr);
4611         kvm_release_page_dirty(page);
4612
4613         if (!exchanged)
4614                 return X86EMUL_CMPXCHG_FAILED;
4615
4616         mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
4617         kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4618
4619         return X86EMUL_CONTINUE;
4620
4621 emul_write:
4622         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4623
4624         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4625 }
4626
4627 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4628 {
4629         /* TODO: String I/O for in kernel device */
4630         int r;
4631
4632         if (vcpu->arch.pio.in)
4633                 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4634                                     vcpu->arch.pio.size, pd);
4635         else
4636                 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4637                                      vcpu->arch.pio.port, vcpu->arch.pio.size,
4638                                      pd);
4639         return r;
4640 }
4641
4642 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4643                                unsigned short port, void *val,
4644                                unsigned int count, bool in)
4645 {
4646         vcpu->arch.pio.port = port;
4647         vcpu->arch.pio.in = in;
4648         vcpu->arch.pio.count  = count;
4649         vcpu->arch.pio.size = size;
4650
4651         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4652                 vcpu->arch.pio.count = 0;
4653                 return 1;
4654         }
4655
4656         vcpu->run->exit_reason = KVM_EXIT_IO;
4657         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4658         vcpu->run->io.size = size;
4659         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4660         vcpu->run->io.count = count;
4661         vcpu->run->io.port = port;
4662
4663         return 0;
4664 }
4665
4666 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4667                                     int size, unsigned short port, void *val,
4668                                     unsigned int count)
4669 {
4670         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4671         int ret;
4672
4673         if (vcpu->arch.pio.count)
4674                 goto data_avail;
4675
4676         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4677         if (ret) {
4678 data_avail:
4679                 memcpy(val, vcpu->arch.pio_data, size * count);
4680                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
4681                 vcpu->arch.pio.count = 0;
4682                 return 1;
4683         }
4684
4685         return 0;
4686 }
4687
4688 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4689                                      int size, unsigned short port,
4690                                      const void *val, unsigned int count)
4691 {
4692         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4693
4694         memcpy(vcpu->arch.pio_data, val, size * count);
4695         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
4696         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4697 }
4698
4699 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4700 {
4701         return kvm_x86_ops->get_segment_base(vcpu, seg);
4702 }
4703
4704 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4705 {
4706         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4707 }
4708
4709 int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
4710 {
4711         if (!need_emulate_wbinvd(vcpu))
4712                 return X86EMUL_CONTINUE;
4713
4714         if (kvm_x86_ops->has_wbinvd_exit()) {
4715                 int cpu = get_cpu();
4716
4717                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4718                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4719                                 wbinvd_ipi, NULL, 1);
4720                 put_cpu();
4721                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4722         } else
4723                 wbinvd();
4724         return X86EMUL_CONTINUE;
4725 }
4726
4727 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4728 {
4729         kvm_x86_ops->skip_emulated_instruction(vcpu);
4730         return kvm_emulate_wbinvd_noskip(vcpu);
4731 }
4732 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4733
4734
4735
4736 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4737 {
4738         kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
4739 }
4740
4741 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4742 {
4743         return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4744 }
4745
4746 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4747 {
4748
4749         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4750 }
4751
4752 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4753 {
4754         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4755 }
4756
4757 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4758 {
4759         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4760         unsigned long value;
4761
4762         switch (cr) {
4763         case 0:
4764                 value = kvm_read_cr0(vcpu);
4765                 break;
4766         case 2:
4767                 value = vcpu->arch.cr2;
4768                 break;
4769         case 3:
4770                 value = kvm_read_cr3(vcpu);
4771                 break;
4772         case 4:
4773                 value = kvm_read_cr4(vcpu);
4774                 break;
4775         case 8:
4776                 value = kvm_get_cr8(vcpu);
4777                 break;
4778         default:
4779                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4780                 return 0;
4781         }
4782
4783         return value;
4784 }
4785
4786 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4787 {
4788         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4789         int res = 0;
4790
4791         switch (cr) {
4792         case 0:
4793                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4794                 break;
4795         case 2:
4796                 vcpu->arch.cr2 = val;
4797                 break;
4798         case 3:
4799                 res = kvm_set_cr3(vcpu, val);
4800                 break;
4801         case 4:
4802                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4803                 break;
4804         case 8:
4805                 res = kvm_set_cr8(vcpu, val);
4806                 break;
4807         default:
4808                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4809                 res = -1;
4810         }
4811
4812         return res;
4813 }
4814
4815 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4816 {
4817         return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4818 }
4819
4820 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4821 {
4822         kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4823 }
4824
4825 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4826 {
4827         kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4828 }
4829
4830 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4831 {
4832         kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4833 }
4834
4835 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4836 {
4837         kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4838 }
4839
4840 static unsigned long emulator_get_cached_segment_base(
4841         struct x86_emulate_ctxt *ctxt, int seg)
4842 {
4843         return get_segment_base(emul_to_vcpu(ctxt), seg);
4844 }
4845
4846 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4847                                  struct desc_struct *desc, u32 *base3,
4848                                  int seg)
4849 {
4850         struct kvm_segment var;
4851
4852         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4853         *selector = var.selector;
4854
4855         if (var.unusable) {
4856                 memset(desc, 0, sizeof(*desc));
4857                 return false;
4858         }
4859
4860         if (var.g)
4861                 var.limit >>= 12;
4862         set_desc_limit(desc, var.limit);
4863         set_desc_base(desc, (unsigned long)var.base);
4864 #ifdef CONFIG_X86_64
4865         if (base3)
4866                 *base3 = var.base >> 32;
4867 #endif
4868         desc->type = var.type;
4869         desc->s = var.s;
4870         desc->dpl = var.dpl;
4871         desc->p = var.present;
4872         desc->avl = var.avl;
4873         desc->l = var.l;
4874         desc->d = var.db;
4875         desc->g = var.g;
4876
4877         return true;
4878 }
4879
4880 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4881                                  struct desc_struct *desc, u32 base3,
4882                                  int seg)
4883 {
4884         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4885         struct kvm_segment var;
4886
4887         var.selector = selector;
4888         var.base = get_desc_base(desc);
4889 #ifdef CONFIG_X86_64
4890         var.base |= ((u64)base3) << 32;
4891 #endif
4892         var.limit = get_desc_limit(desc);
4893         if (desc->g)
4894                 var.limit = (var.limit << 12) | 0xfff;
4895         var.type = desc->type;
4896         var.dpl = desc->dpl;
4897         var.db = desc->d;
4898         var.s = desc->s;
4899         var.l = desc->l;
4900         var.g = desc->g;
4901         var.avl = desc->avl;
4902         var.present = desc->p;
4903         var.unusable = !var.present;
4904         var.padding = 0;
4905
4906         kvm_set_segment(vcpu, &var, seg);
4907         return;
4908 }
4909
4910 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4911                             u32 msr_index, u64 *pdata)
4912 {
4913         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4914 }
4915
4916 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4917                             u32 msr_index, u64 data)
4918 {
4919         struct msr_data msr;
4920
4921         msr.data = data;
4922         msr.index = msr_index;
4923         msr.host_initiated = false;
4924         return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4925 }
4926
4927 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4928                               u32 pmc)
4929 {
4930         return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4931 }
4932
4933 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4934                              u32 pmc, u64 *pdata)
4935 {
4936         return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4937 }
4938
4939 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4940 {
4941         emul_to_vcpu(ctxt)->arch.halt_request = 1;
4942 }
4943
4944 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4945 {
4946         preempt_disable();
4947         kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4948         /*
4949          * CR0.TS may reference the host fpu state, not the guest fpu state,
4950          * so it may be clear at this point.
4951          */
4952         clts();
4953 }
4954
4955 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4956 {
4957         preempt_enable();
4958 }
4959
4960 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4961                               struct x86_instruction_info *info,
4962                               enum x86_intercept_stage stage)
4963 {
4964         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4965 }
4966
4967 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4968                                u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4969 {
4970         kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4971 }
4972
4973 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4974 {
4975         return kvm_register_read(emul_to_vcpu(ctxt), reg);
4976 }
4977
4978 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4979 {
4980         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4981 }
4982
4983 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4984 {
4985         kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4986 }
4987
4988 static const struct x86_emulate_ops emulate_ops = {
4989         .read_gpr            = emulator_read_gpr,
4990         .write_gpr           = emulator_write_gpr,
4991         .read_std            = kvm_read_guest_virt_system,
4992         .write_std           = kvm_write_guest_virt_system,
4993         .fetch               = kvm_fetch_guest_virt,
4994         .read_emulated       = emulator_read_emulated,
4995         .write_emulated      = emulator_write_emulated,
4996         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
4997         .invlpg              = emulator_invlpg,
4998         .pio_in_emulated     = emulator_pio_in_emulated,
4999         .pio_out_emulated    = emulator_pio_out_emulated,
5000         .get_segment         = emulator_get_segment,
5001         .set_segment         = emulator_set_segment,
5002         .get_cached_segment_base = emulator_get_cached_segment_base,
5003         .get_gdt             = emulator_get_gdt,
5004         .get_idt             = emulator_get_idt,
5005         .set_gdt             = emulator_set_gdt,
5006         .set_idt             = emulator_set_idt,
5007         .get_cr              = emulator_get_cr,
5008         .set_cr              = emulator_set_cr,
5009         .cpl                 = emulator_get_cpl,
5010         .get_dr              = emulator_get_dr,
5011         .set_dr              = emulator_set_dr,
5012         .set_msr             = emulator_set_msr,
5013         .get_msr             = emulator_get_msr,
5014         .check_pmc           = emulator_check_pmc,
5015         .read_pmc            = emulator_read_pmc,
5016         .halt                = emulator_halt,
5017         .wbinvd              = emulator_wbinvd,
5018         .fix_hypercall       = emulator_fix_hypercall,
5019         .get_fpu             = emulator_get_fpu,
5020         .put_fpu             = emulator_put_fpu,
5021         .intercept           = emulator_intercept,
5022         .get_cpuid           = emulator_get_cpuid,
5023         .set_nmi_mask        = emulator_set_nmi_mask,
5024 };
5025
5026 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5027 {
5028         u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
5029         /*
5030          * an sti; sti; sequence only disable interrupts for the first
5031          * instruction. So, if the last instruction, be it emulated or
5032          * not, left the system with the INT_STI flag enabled, it
5033          * means that the last instruction is an sti. We should not
5034          * leave the flag on in this case. The same goes for mov ss
5035          */
5036         if (int_shadow & mask)
5037                 mask = 0;
5038         if (unlikely(int_shadow || mask)) {
5039                 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
5040                 if (!mask)
5041                         kvm_make_request(KVM_REQ_EVENT, vcpu);
5042         }
5043 }
5044
5045 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
5046 {
5047         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5048         if (ctxt->exception.vector == PF_VECTOR)
5049                 return kvm_propagate_fault(vcpu, &ctxt->exception);
5050
5051         if (ctxt->exception.error_code_valid)
5052                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5053                                       ctxt->exception.error_code);
5054         else
5055                 kvm_queue_exception(vcpu, ctxt->exception.vector);
5056         return false;
5057 }
5058
5059 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5060 {
5061         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5062         int cs_db, cs_l;
5063
5064         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5065
5066         ctxt->eflags = kvm_get_rflags(vcpu);
5067         ctxt->eip = kvm_rip_read(vcpu);
5068         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
5069                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
5070                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
5071                      cs_db                              ? X86EMUL_MODE_PROT32 :
5072                                                           X86EMUL_MODE_PROT16;
5073         ctxt->guest_mode = is_guest_mode(vcpu);
5074
5075         init_decode_cache(ctxt);
5076         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5077 }
5078
5079 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
5080 {
5081         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5082         int ret;
5083
5084         init_emulate_ctxt(vcpu);
5085
5086         ctxt->op_bytes = 2;
5087         ctxt->ad_bytes = 2;
5088         ctxt->_eip = ctxt->eip + inc_eip;
5089         ret = emulate_int_real(ctxt, irq);
5090
5091         if (ret != X86EMUL_CONTINUE)
5092                 return EMULATE_FAIL;
5093
5094         ctxt->eip = ctxt->_eip;
5095         kvm_rip_write(vcpu, ctxt->eip);
5096         kvm_set_rflags(vcpu, ctxt->eflags);
5097
5098         if (irq == NMI_VECTOR)
5099                 vcpu->arch.nmi_pending = 0;
5100         else
5101                 vcpu->arch.interrupt.pending = false;
5102
5103         return EMULATE_DONE;
5104 }
5105 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5106
5107 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5108 {
5109         int r = EMULATE_DONE;
5110
5111         ++vcpu->stat.insn_emulation_fail;
5112         trace_kvm_emulate_insn_failed(vcpu);
5113         if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
5114                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5115                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5116                 vcpu->run->internal.ndata = 0;
5117                 r = EMULATE_FAIL;
5118         }
5119         kvm_queue_exception(vcpu, UD_VECTOR);
5120
5121         return r;
5122 }
5123
5124 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
5125                                   bool write_fault_to_shadow_pgtable,
5126                                   int emulation_type)
5127 {
5128         gpa_t gpa = cr2;
5129         pfn_t pfn;
5130
5131         if (emulation_type & EMULTYPE_NO_REEXECUTE)
5132                 return false;
5133
5134         if (!vcpu->arch.mmu.direct_map) {
5135                 /*
5136                  * Write permission should be allowed since only
5137                  * write access need to be emulated.
5138                  */
5139                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5140
5141                 /*
5142                  * If the mapping is invalid in guest, let cpu retry
5143                  * it to generate fault.
5144                  */
5145                 if (gpa == UNMAPPED_GVA)
5146                         return true;
5147         }
5148
5149         /*
5150          * Do not retry the unhandleable instruction if it faults on the
5151          * readonly host memory, otherwise it will goto a infinite loop:
5152          * retry instruction -> write #PF -> emulation fail -> retry
5153          * instruction -> ...
5154          */
5155         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
5156
5157         /*
5158          * If the instruction failed on the error pfn, it can not be fixed,
5159          * report the error to userspace.
5160          */
5161         if (is_error_noslot_pfn(pfn))
5162                 return false;
5163
5164         kvm_release_pfn_clean(pfn);
5165
5166         /* The instructions are well-emulated on direct mmu. */
5167         if (vcpu->arch.mmu.direct_map) {
5168                 unsigned int indirect_shadow_pages;
5169
5170                 spin_lock(&vcpu->kvm->mmu_lock);
5171                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5172                 spin_unlock(&vcpu->kvm->mmu_lock);
5173
5174                 if (indirect_shadow_pages)
5175                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5176
5177                 return true;
5178         }
5179
5180         /*
5181          * if emulation was due to access to shadowed page table
5182          * and it failed try to unshadow page and re-enter the
5183          * guest to let CPU execute the instruction.
5184          */
5185         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5186
5187         /*
5188          * If the access faults on its page table, it can not
5189          * be fixed by unprotecting shadow page and it should
5190          * be reported to userspace.
5191          */
5192         return !write_fault_to_shadow_pgtable;
5193 }
5194
5195 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5196                               unsigned long cr2,  int emulation_type)
5197 {
5198         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5199         unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5200
5201         last_retry_eip = vcpu->arch.last_retry_eip;
5202         last_retry_addr = vcpu->arch.last_retry_addr;
5203
5204         /*
5205          * If the emulation is caused by #PF and it is non-page_table
5206          * writing instruction, it means the VM-EXIT is caused by shadow
5207          * page protected, we can zap the shadow page and retry this
5208          * instruction directly.
5209          *
5210          * Note: if the guest uses a non-page-table modifying instruction
5211          * on the PDE that points to the instruction, then we will unmap
5212          * the instruction and go to an infinite loop. So, we cache the
5213          * last retried eip and the last fault address, if we meet the eip
5214          * and the address again, we can break out of the potential infinite
5215          * loop.
5216          */
5217         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5218
5219         if (!(emulation_type & EMULTYPE_RETRY))
5220                 return false;
5221
5222         if (x86_page_table_writing_insn(ctxt))
5223                 return false;
5224
5225         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5226                 return false;
5227
5228         vcpu->arch.last_retry_eip = ctxt->eip;
5229         vcpu->arch.last_retry_addr = cr2;
5230
5231         if (!vcpu->arch.mmu.direct_map)
5232                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5233
5234         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5235
5236         return true;
5237 }
5238
5239 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5240 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5241
5242 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5243                                 unsigned long *db)
5244 {
5245         u32 dr6 = 0;
5246         int i;
5247         u32 enable, rwlen;
5248
5249         enable = dr7;
5250         rwlen = dr7 >> 16;
5251         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5252                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5253                         dr6 |= (1 << i);
5254         return dr6;
5255 }
5256
5257 static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
5258 {
5259         struct kvm_run *kvm_run = vcpu->run;
5260
5261         /*
5262          * rflags is the old, "raw" value of the flags.  The new value has
5263          * not been saved yet.
5264          *
5265          * This is correct even for TF set by the guest, because "the
5266          * processor will not generate this exception after the instruction
5267          * that sets the TF flag".
5268          */
5269         if (unlikely(rflags & X86_EFLAGS_TF)) {
5270                 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5271                         kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5272                                                   DR6_RTM;
5273                         kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5274                         kvm_run->debug.arch.exception = DB_VECTOR;
5275                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
5276                         *r = EMULATE_USER_EXIT;
5277                 } else {
5278                         vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5279                         /*
5280                          * "Certain debug exceptions may clear bit 0-3.  The
5281                          * remaining contents of the DR6 register are never
5282                          * cleared by the processor".
5283                          */
5284                         vcpu->arch.dr6 &= ~15;
5285                         vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5286                         kvm_queue_exception(vcpu, DB_VECTOR);
5287                 }
5288         }
5289 }
5290
5291 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5292 {
5293         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5294             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5295                 struct kvm_run *kvm_run = vcpu->run;
5296                 unsigned long eip = kvm_get_linear_rip(vcpu);
5297                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5298                                            vcpu->arch.guest_debug_dr7,
5299                                            vcpu->arch.eff_db);
5300
5301                 if (dr6 != 0) {
5302                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
5303                         kvm_run->debug.arch.pc = eip;
5304                         kvm_run->debug.arch.exception = DB_VECTOR;
5305                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
5306                         *r = EMULATE_USER_EXIT;
5307                         return true;
5308                 }
5309         }
5310
5311         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5312             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
5313                 unsigned long eip = kvm_get_linear_rip(vcpu);
5314                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5315                                            vcpu->arch.dr7,
5316                                            vcpu->arch.db);
5317
5318                 if (dr6 != 0) {
5319                         vcpu->arch.dr6 &= ~15;
5320                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5321                         kvm_queue_exception(vcpu, DB_VECTOR);
5322                         *r = EMULATE_DONE;
5323                         return true;
5324                 }
5325         }
5326
5327         return false;
5328 }
5329
5330 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5331                             unsigned long cr2,
5332                             int emulation_type,
5333                             void *insn,
5334                             int insn_len)
5335 {
5336         int r;
5337         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5338         bool writeback = true;
5339         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
5340
5341         /*
5342          * Clear write_fault_to_shadow_pgtable here to ensure it is
5343          * never reused.
5344          */
5345         vcpu->arch.write_fault_to_shadow_pgtable = false;
5346         kvm_clear_exception_queue(vcpu);
5347
5348         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
5349                 init_emulate_ctxt(vcpu);
5350
5351                 /*
5352                  * We will reenter on the same instruction since
5353                  * we do not set complete_userspace_io.  This does not
5354                  * handle watchpoints yet, those would be handled in
5355                  * the emulate_ops.
5356                  */
5357                 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5358                         return r;
5359
5360                 ctxt->interruptibility = 0;
5361                 ctxt->have_exception = false;
5362                 ctxt->exception.vector = -1;
5363                 ctxt->perm_ok = false;
5364
5365                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
5366
5367                 r = x86_decode_insn(ctxt, insn, insn_len);
5368
5369                 trace_kvm_emulate_insn_start(vcpu);
5370                 ++vcpu->stat.insn_emulation;
5371                 if (r != EMULATION_OK)  {
5372                         if (emulation_type & EMULTYPE_TRAP_UD)
5373                                 return EMULATE_FAIL;
5374                         if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5375                                                 emulation_type))
5376                                 return EMULATE_DONE;
5377                         if (emulation_type & EMULTYPE_SKIP)
5378                                 return EMULATE_FAIL;
5379                         return handle_emulation_failure(vcpu);
5380                 }
5381         }
5382
5383         if (emulation_type & EMULTYPE_SKIP) {
5384                 kvm_rip_write(vcpu, ctxt->_eip);
5385                 if (ctxt->eflags & X86_EFLAGS_RF)
5386                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
5387                 return EMULATE_DONE;
5388         }
5389
5390         if (retry_instruction(ctxt, cr2, emulation_type))
5391                 return EMULATE_DONE;
5392
5393         /* this is needed for vmware backdoor interface to work since it
5394            changes registers values  during IO operation */
5395         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5396                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5397                 emulator_invalidate_register_cache(ctxt);
5398         }
5399
5400 restart:
5401         r = x86_emulate_insn(ctxt);
5402
5403         if (r == EMULATION_INTERCEPTED)
5404                 return EMULATE_DONE;
5405
5406         if (r == EMULATION_FAILED) {
5407                 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5408                                         emulation_type))
5409                         return EMULATE_DONE;
5410
5411                 return handle_emulation_failure(vcpu);
5412         }
5413
5414         if (ctxt->have_exception) {
5415                 r = EMULATE_DONE;
5416                 if (inject_emulated_exception(vcpu))
5417                         return r;
5418         } else if (vcpu->arch.pio.count) {
5419                 if (!vcpu->arch.pio.in) {
5420                         /* FIXME: return into emulator if single-stepping.  */
5421                         vcpu->arch.pio.count = 0;
5422                 } else {
5423                         writeback = false;
5424                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
5425                 }
5426                 r = EMULATE_USER_EXIT;
5427         } else if (vcpu->mmio_needed) {
5428                 if (!vcpu->mmio_is_write)
5429                         writeback = false;
5430                 r = EMULATE_USER_EXIT;
5431                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5432         } else if (r == EMULATION_RESTART)
5433                 goto restart;
5434         else
5435                 r = EMULATE_DONE;
5436
5437         if (writeback) {
5438                 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5439                 toggle_interruptibility(vcpu, ctxt->interruptibility);
5440                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5441                 kvm_rip_write(vcpu, ctxt->eip);
5442                 if (r == EMULATE_DONE)
5443                         kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5444                 if (!ctxt->have_exception ||
5445                     exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5446                         __kvm_set_rflags(vcpu, ctxt->eflags);
5447
5448                 /*
5449                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5450                  * do nothing, and it will be requested again as soon as
5451                  * the shadow expires.  But we still need to check here,
5452                  * because POPF has no interrupt shadow.
5453                  */
5454                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5455                         kvm_make_request(KVM_REQ_EVENT, vcpu);
5456         } else
5457                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5458
5459         return r;
5460 }
5461 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5462
5463 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5464 {
5465         unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5466         int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5467                                             size, port, &val, 1);
5468         /* do not return to emulator after return from userspace */
5469         vcpu->arch.pio.count = 0;
5470         return ret;
5471 }
5472 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5473
5474 static void tsc_bad(void *info)
5475 {
5476         __this_cpu_write(cpu_tsc_khz, 0);
5477 }
5478
5479 static void tsc_khz_changed(void *data)
5480 {
5481         struct cpufreq_freqs *freq = data;
5482         unsigned long khz = 0;
5483
5484         if (data)
5485                 khz = freq->new;
5486         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5487                 khz = cpufreq_quick_get(raw_smp_processor_id());
5488         if (!khz)
5489                 khz = tsc_khz;
5490         __this_cpu_write(cpu_tsc_khz, khz);
5491 }
5492
5493 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5494                                      void *data)
5495 {
5496         struct cpufreq_freqs *freq = data;
5497         struct kvm *kvm;
5498         struct kvm_vcpu *vcpu;
5499         int i, send_ipi = 0;
5500
5501         /*
5502          * We allow guests to temporarily run on slowing clocks,
5503          * provided we notify them after, or to run on accelerating
5504          * clocks, provided we notify them before.  Thus time never
5505          * goes backwards.
5506          *
5507          * However, we have a problem.  We can't atomically update
5508          * the frequency of a given CPU from this function; it is
5509          * merely a notifier, which can be called from any CPU.
5510          * Changing the TSC frequency at arbitrary points in time
5511          * requires a recomputation of local variables related to
5512          * the TSC for each VCPU.  We must flag these local variables
5513          * to be updated and be sure the update takes place with the
5514          * new frequency before any guests proceed.
5515          *
5516          * Unfortunately, the combination of hotplug CPU and frequency
5517          * change creates an intractable locking scenario; the order
5518          * of when these callouts happen is undefined with respect to
5519          * CPU hotplug, and they can race with each other.  As such,
5520          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5521          * undefined; you can actually have a CPU frequency change take
5522          * place in between the computation of X and the setting of the
5523          * variable.  To protect against this problem, all updates of
5524          * the per_cpu tsc_khz variable are done in an interrupt
5525          * protected IPI, and all callers wishing to update the value
5526          * must wait for a synchronous IPI to complete (which is trivial
5527          * if the caller is on the CPU already).  This establishes the
5528          * necessary total order on variable updates.
5529          *
5530          * Note that because a guest time update may take place
5531          * anytime after the setting of the VCPU's request bit, the
5532          * correct TSC value must be set before the request.  However,
5533          * to ensure the update actually makes it to any guest which
5534          * starts running in hardware virtualization between the set
5535          * and the acquisition of the spinlock, we must also ping the
5536          * CPU after setting the request bit.
5537          *
5538          */
5539
5540         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5541                 return 0;
5542         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5543                 return 0;
5544
5545         smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5546
5547         spin_lock(&kvm_lock);
5548         list_for_each_entry(kvm, &vm_list, vm_list) {
5549                 kvm_for_each_vcpu(i, vcpu, kvm) {
5550                         if (vcpu->cpu != freq->cpu)
5551                                 continue;
5552                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5553                         if (vcpu->cpu != smp_processor_id())
5554                                 send_ipi = 1;
5555                 }
5556         }
5557         spin_unlock(&kvm_lock);
5558
5559         if (freq->old < freq->new && send_ipi) {
5560                 /*
5561                  * We upscale the frequency.  Must make the guest
5562                  * doesn't see old kvmclock values while running with
5563                  * the new frequency, otherwise we risk the guest sees
5564                  * time go backwards.
5565                  *
5566                  * In case we update the frequency for another cpu
5567                  * (which might be in guest context) send an interrupt
5568                  * to kick the cpu out of guest context.  Next time
5569                  * guest context is entered kvmclock will be updated,
5570                  * so the guest will not see stale values.
5571                  */
5572                 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5573         }
5574         return 0;
5575 }
5576
5577 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5578         .notifier_call  = kvmclock_cpufreq_notifier
5579 };
5580
5581 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5582                                         unsigned long action, void *hcpu)
5583 {
5584         unsigned int cpu = (unsigned long)hcpu;
5585
5586         switch (action) {
5587                 case CPU_ONLINE:
5588                 case CPU_DOWN_FAILED:
5589                         smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5590                         break;
5591                 case CPU_DOWN_PREPARE:
5592                         smp_call_function_single(cpu, tsc_bad, NULL, 1);
5593                         break;
5594         }
5595         return NOTIFY_OK;
5596 }
5597
5598 static struct notifier_block kvmclock_cpu_notifier_block = {
5599         .notifier_call  = kvmclock_cpu_notifier,
5600         .priority = -INT_MAX
5601 };
5602
5603 static void kvm_timer_init(void)
5604 {
5605         int cpu;
5606
5607         max_tsc_khz = tsc_khz;
5608
5609         cpu_notifier_register_begin();
5610         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5611 #ifdef CONFIG_CPU_FREQ
5612                 struct cpufreq_policy policy;
5613                 memset(&policy, 0, sizeof(policy));
5614                 cpu = get_cpu();
5615                 cpufreq_get_policy(&policy, cpu);
5616                 if (policy.cpuinfo.max_freq)
5617                         max_tsc_khz = policy.cpuinfo.max_freq;
5618                 put_cpu();
5619 #endif
5620                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5621                                           CPUFREQ_TRANSITION_NOTIFIER);
5622         }
5623         pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5624         for_each_online_cpu(cpu)
5625                 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5626
5627         __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5628         cpu_notifier_register_done();
5629
5630 }
5631
5632 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5633
5634 int kvm_is_in_guest(void)
5635 {
5636         return __this_cpu_read(current_vcpu) != NULL;
5637 }
5638
5639 static int kvm_is_user_mode(void)
5640 {
5641         int user_mode = 3;
5642
5643         if (__this_cpu_read(current_vcpu))
5644                 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5645
5646         return user_mode != 0;
5647 }
5648
5649 static unsigned long kvm_get_guest_ip(void)
5650 {
5651         unsigned long ip = 0;
5652
5653         if (__this_cpu_read(current_vcpu))
5654                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5655
5656         return ip;
5657 }
5658
5659 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5660         .is_in_guest            = kvm_is_in_guest,
5661         .is_user_mode           = kvm_is_user_mode,
5662         .get_guest_ip           = kvm_get_guest_ip,
5663 };
5664
5665 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5666 {
5667         __this_cpu_write(current_vcpu, vcpu);
5668 }
5669 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5670
5671 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5672 {
5673         __this_cpu_write(current_vcpu, NULL);
5674 }
5675 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5676
5677 static void kvm_set_mmio_spte_mask(void)
5678 {
5679         u64 mask;
5680         int maxphyaddr = boot_cpu_data.x86_phys_bits;
5681
5682         /*
5683          * Set the reserved bits and the present bit of an paging-structure
5684          * entry to generate page fault with PFER.RSV = 1.
5685          */
5686          /* Mask the reserved physical address bits. */
5687         mask = rsvd_bits(maxphyaddr, 51);
5688
5689         /* Bit 62 is always reserved for 32bit host. */
5690         mask |= 0x3ull << 62;
5691
5692         /* Set the present bit. */
5693         mask |= 1ull;
5694
5695 #ifdef CONFIG_X86_64
5696         /*
5697          * If reserved bit is not supported, clear the present bit to disable
5698          * mmio page fault.
5699          */
5700         if (maxphyaddr == 52)
5701                 mask &= ~1ull;
5702 #endif
5703
5704         kvm_mmu_set_mmio_spte_mask(mask);
5705 }
5706
5707 #ifdef CONFIG_X86_64
5708 static void pvclock_gtod_update_fn(struct work_struct *work)
5709 {
5710         struct kvm *kvm;
5711
5712         struct kvm_vcpu *vcpu;
5713         int i;
5714
5715         spin_lock(&kvm_lock);
5716         list_for_each_entry(kvm, &vm_list, vm_list)
5717                 kvm_for_each_vcpu(i, vcpu, kvm)
5718                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
5719         atomic_set(&kvm_guest_has_master_clock, 0);
5720         spin_unlock(&kvm_lock);
5721 }
5722
5723 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5724
5725 /*
5726  * Notification about pvclock gtod data update.
5727  */
5728 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5729                                void *priv)
5730 {
5731         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5732         struct timekeeper *tk = priv;
5733
5734         update_pvclock_gtod(tk);
5735
5736         /* disable master clock if host does not trust, or does not
5737          * use, TSC clocksource
5738          */
5739         if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5740             atomic_read(&kvm_guest_has_master_clock) != 0)
5741                 queue_work(system_long_wq, &pvclock_gtod_work);
5742
5743         return 0;
5744 }
5745
5746 static struct notifier_block pvclock_gtod_notifier = {
5747         .notifier_call = pvclock_gtod_notify,
5748 };
5749 #endif
5750
5751 int kvm_arch_init(void *opaque)
5752 {
5753         int r;
5754         struct kvm_x86_ops *ops = opaque;
5755
5756         if (kvm_x86_ops) {
5757                 printk(KERN_ERR "kvm: already loaded the other module\n");
5758                 r = -EEXIST;
5759                 goto out;
5760         }
5761
5762         if (!ops->cpu_has_kvm_support()) {
5763                 printk(KERN_ERR "kvm: no hardware support\n");
5764                 r = -EOPNOTSUPP;
5765                 goto out;
5766         }
5767         if (ops->disabled_by_bios()) {
5768                 printk(KERN_ERR "kvm: disabled by bios\n");
5769                 r = -EOPNOTSUPP;
5770                 goto out;
5771         }
5772
5773         r = -ENOMEM;
5774         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5775         if (!shared_msrs) {
5776                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5777                 goto out;
5778         }
5779
5780         r = kvm_mmu_module_init();
5781         if (r)
5782                 goto out_free_percpu;
5783
5784         kvm_set_mmio_spte_mask();
5785
5786         kvm_x86_ops = ops;
5787         kvm_init_msr_list();
5788
5789         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5790                         PT_DIRTY_MASK, PT64_NX_MASK, 0);
5791
5792         kvm_timer_init();
5793
5794         perf_register_guest_info_callbacks(&kvm_guest_cbs);
5795
5796         if (cpu_has_xsave)
5797                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5798
5799         kvm_lapic_init();
5800 #ifdef CONFIG_X86_64
5801         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5802 #endif
5803
5804         return 0;
5805
5806 out_free_percpu:
5807         free_percpu(shared_msrs);
5808 out:
5809         return r;
5810 }
5811
5812 void kvm_arch_exit(void)
5813 {
5814         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5815
5816         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5817                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5818                                             CPUFREQ_TRANSITION_NOTIFIER);
5819         unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5820 #ifdef CONFIG_X86_64
5821         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5822 #endif
5823         kvm_x86_ops = NULL;
5824         kvm_mmu_module_exit();
5825         free_percpu(shared_msrs);
5826 }
5827
5828 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
5829 {
5830         ++vcpu->stat.halt_exits;
5831         if (irqchip_in_kernel(vcpu->kvm)) {
5832                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5833                 return 1;
5834         } else {
5835                 vcpu->run->exit_reason = KVM_EXIT_HLT;
5836                 return 0;
5837         }
5838 }
5839 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5840
5841 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5842 {
5843         kvm_x86_ops->skip_emulated_instruction(vcpu);
5844         return kvm_vcpu_halt(vcpu);
5845 }
5846 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5847
5848 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5849 {
5850         u64 param, ingpa, outgpa, ret;
5851         uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5852         bool fast, longmode;
5853
5854         /*
5855          * hypercall generates UD from non zero cpl and real mode
5856          * per HYPER-V spec
5857          */
5858         if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5859                 kvm_queue_exception(vcpu, UD_VECTOR);
5860                 return 0;
5861         }
5862
5863         longmode = is_64_bit_mode(vcpu);
5864
5865         if (!longmode) {
5866                 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5867                         (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5868                 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5869                         (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5870                 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5871                         (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5872         }
5873 #ifdef CONFIG_X86_64
5874         else {
5875                 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5876                 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5877                 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5878         }
5879 #endif
5880
5881         code = param & 0xffff;
5882         fast = (param >> 16) & 0x1;
5883         rep_cnt = (param >> 32) & 0xfff;
5884         rep_idx = (param >> 48) & 0xfff;
5885
5886         trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5887
5888         switch (code) {
5889         case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5890                 kvm_vcpu_on_spin(vcpu);
5891                 break;
5892         default:
5893                 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5894                 break;
5895         }
5896
5897         ret = res | (((u64)rep_done & 0xfff) << 32);
5898         if (longmode) {
5899                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5900         } else {
5901                 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5902                 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5903         }
5904
5905         return 1;
5906 }
5907
5908 /*
5909  * kvm_pv_kick_cpu_op:  Kick a vcpu.
5910  *
5911  * @apicid - apicid of vcpu to be kicked.
5912  */
5913 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5914 {
5915         struct kvm_lapic_irq lapic_irq;
5916
5917         lapic_irq.shorthand = 0;
5918         lapic_irq.dest_mode = 0;
5919         lapic_irq.dest_id = apicid;
5920
5921         lapic_irq.delivery_mode = APIC_DM_REMRD;
5922         kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
5923 }
5924
5925 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5926 {
5927         unsigned long nr, a0, a1, a2, a3, ret;
5928         int op_64_bit, r = 1;
5929
5930         kvm_x86_ops->skip_emulated_instruction(vcpu);
5931
5932         if (kvm_hv_hypercall_enabled(vcpu->kvm))
5933                 return kvm_hv_hypercall(vcpu);
5934
5935         nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5936         a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5937         a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5938         a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5939         a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5940
5941         trace_kvm_hypercall(nr, a0, a1, a2, a3);
5942
5943         op_64_bit = is_64_bit_mode(vcpu);
5944         if (!op_64_bit) {
5945                 nr &= 0xFFFFFFFF;
5946                 a0 &= 0xFFFFFFFF;
5947                 a1 &= 0xFFFFFFFF;
5948                 a2 &= 0xFFFFFFFF;
5949                 a3 &= 0xFFFFFFFF;
5950         }
5951
5952         if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5953                 ret = -KVM_EPERM;
5954                 goto out;
5955         }
5956
5957         switch (nr) {
5958         case KVM_HC_VAPIC_POLL_IRQ:
5959                 ret = 0;
5960                 break;
5961         case KVM_HC_KICK_CPU:
5962                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5963                 ret = 0;
5964                 break;
5965         default:
5966                 ret = -KVM_ENOSYS;
5967                 break;
5968         }
5969 out:
5970         if (!op_64_bit)
5971                 ret = (u32)ret;
5972         kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5973         ++vcpu->stat.hypercalls;
5974         return r;
5975 }
5976 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5977
5978 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5979 {
5980         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5981         char instruction[3];
5982         unsigned long rip = kvm_rip_read(vcpu);
5983
5984         kvm_x86_ops->patch_hypercall(vcpu, instruction);
5985
5986         return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5987 }
5988
5989 /*
5990  * Check if userspace requested an interrupt window, and that the
5991  * interrupt window is open.
5992  *
5993  * No need to exit to userspace if we already have an interrupt queued.
5994  */
5995 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5996 {
5997         return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5998                 vcpu->run->request_interrupt_window &&
5999                 kvm_arch_interrupt_allowed(vcpu));
6000 }
6001
6002 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
6003 {
6004         struct kvm_run *kvm_run = vcpu->run;
6005
6006         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
6007         kvm_run->cr8 = kvm_get_cr8(vcpu);
6008         kvm_run->apic_base = kvm_get_apic_base(vcpu);
6009         if (irqchip_in_kernel(vcpu->kvm))
6010                 kvm_run->ready_for_interrupt_injection = 1;
6011         else
6012                 kvm_run->ready_for_interrupt_injection =
6013                         kvm_arch_interrupt_allowed(vcpu) &&
6014                         !kvm_cpu_has_interrupt(vcpu) &&
6015                         !kvm_event_needs_reinjection(vcpu);
6016 }
6017
6018 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6019 {
6020         int max_irr, tpr;
6021
6022         if (!kvm_x86_ops->update_cr8_intercept)
6023                 return;
6024
6025         if (!vcpu->arch.apic)
6026                 return;
6027
6028         if (!vcpu->arch.apic->vapic_addr)
6029                 max_irr = kvm_lapic_find_highest_irr(vcpu);
6030         else
6031                 max_irr = -1;
6032
6033         if (max_irr != -1)
6034                 max_irr >>= 4;
6035
6036         tpr = kvm_lapic_get_cr8(vcpu);
6037
6038         kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6039 }
6040
6041 static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
6042 {
6043         int r;
6044
6045         /* try to reinject previous events if any */
6046         if (vcpu->arch.exception.pending) {
6047                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6048                                         vcpu->arch.exception.has_error_code,
6049                                         vcpu->arch.exception.error_code);
6050
6051                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6052                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6053                                              X86_EFLAGS_RF);
6054
6055                 if (vcpu->arch.exception.nr == DB_VECTOR &&
6056                     (vcpu->arch.dr7 & DR7_GD)) {
6057                         vcpu->arch.dr7 &= ~DR7_GD;
6058                         kvm_update_dr7(vcpu);
6059                 }
6060
6061                 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6062                                           vcpu->arch.exception.has_error_code,
6063                                           vcpu->arch.exception.error_code,
6064                                           vcpu->arch.exception.reinject);
6065                 return 0;
6066         }
6067
6068         if (vcpu->arch.nmi_injected) {
6069                 kvm_x86_ops->set_nmi(vcpu);
6070                 return 0;
6071         }
6072
6073         if (vcpu->arch.interrupt.pending) {
6074                 kvm_x86_ops->set_irq(vcpu);
6075                 return 0;
6076         }
6077
6078         if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6079                 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6080                 if (r != 0)
6081                         return r;
6082         }
6083
6084         /* try to inject new event if pending */
6085         if (vcpu->arch.nmi_pending) {
6086                 if (kvm_x86_ops->nmi_allowed(vcpu)) {
6087                         --vcpu->arch.nmi_pending;
6088                         vcpu->arch.nmi_injected = true;
6089                         kvm_x86_ops->set_nmi(vcpu);
6090                 }
6091         } else if (kvm_cpu_has_injectable_intr(vcpu)) {
6092                 /*
6093                  * Because interrupts can be injected asynchronously, we are
6094                  * calling check_nested_events again here to avoid a race condition.
6095                  * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6096                  * proposal and current concerns.  Perhaps we should be setting
6097                  * KVM_REQ_EVENT only on certain events and not unconditionally?
6098                  */
6099                 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6100                         r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6101                         if (r != 0)
6102                                 return r;
6103                 }
6104                 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
6105                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6106                                             false);
6107                         kvm_x86_ops->set_irq(vcpu);
6108                 }
6109         }
6110         return 0;
6111 }
6112
6113 static void process_nmi(struct kvm_vcpu *vcpu)
6114 {
6115         unsigned limit = 2;
6116
6117         /*
6118          * x86 is limited to one NMI running, and one NMI pending after it.
6119          * If an NMI is already in progress, limit further NMIs to just one.
6120          * Otherwise, allow two (and we'll inject the first one immediately).
6121          */
6122         if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6123                 limit = 1;
6124
6125         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6126         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6127         kvm_make_request(KVM_REQ_EVENT, vcpu);
6128 }
6129
6130 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
6131 {
6132         u64 eoi_exit_bitmap[4];
6133         u32 tmr[8];
6134
6135         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6136                 return;
6137
6138         memset(eoi_exit_bitmap, 0, 32);
6139         memset(tmr, 0, 32);
6140
6141         kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
6142         kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
6143         kvm_apic_update_tmr(vcpu, tmr);
6144 }
6145
6146 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6147 {
6148         ++vcpu->stat.tlb_flush;
6149         kvm_x86_ops->tlb_flush(vcpu);
6150 }
6151
6152 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6153 {
6154         struct page *page = NULL;
6155
6156         if (!irqchip_in_kernel(vcpu->kvm))
6157                 return;
6158
6159         if (!kvm_x86_ops->set_apic_access_page_addr)
6160                 return;
6161
6162         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6163         kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6164
6165         /*
6166          * Do not pin apic access page in memory, the MMU notifier
6167          * will call us again if it is migrated or swapped out.
6168          */
6169         put_page(page);
6170 }
6171 EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6172
6173 void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6174                                            unsigned long address)
6175 {
6176         /*
6177          * The physical address of apic access page is stored in the VMCS.
6178          * Update it when it becomes invalid.
6179          */
6180         if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6181                 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6182 }
6183
6184 /*
6185  * Returns 1 to let __vcpu_run() continue the guest execution loop without
6186  * exiting to the userspace.  Otherwise, the value will be returned to the
6187  * userspace.
6188  */
6189 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
6190 {
6191         int r;
6192         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
6193                 vcpu->run->request_interrupt_window;
6194         bool req_immediate_exit = false;
6195
6196         if (vcpu->requests) {
6197                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
6198                         kvm_mmu_unload(vcpu);
6199                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
6200                         __kvm_migrate_timers(vcpu);
6201                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6202                         kvm_gen_update_masterclock(vcpu->kvm);
6203                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6204                         kvm_gen_kvmclock_update(vcpu);
6205                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6206                         r = kvm_guest_time_update(vcpu);
6207                         if (unlikely(r))
6208                                 goto out;
6209                 }
6210                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
6211                         kvm_mmu_sync_roots(vcpu);
6212                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
6213                         kvm_vcpu_flush_tlb(vcpu);
6214                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
6215                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
6216                         r = 0;
6217                         goto out;
6218                 }
6219                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
6220                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
6221                         r = 0;
6222                         goto out;
6223                 }
6224                 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
6225                         vcpu->fpu_active = 0;
6226                         kvm_x86_ops->fpu_deactivate(vcpu);
6227                 }
6228                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6229                         /* Page is swapped out. Do synthetic halt */
6230                         vcpu->arch.apf.halted = true;
6231                         r = 1;
6232                         goto out;
6233                 }
6234                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6235                         record_steal_time(vcpu);
6236                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6237                         process_nmi(vcpu);
6238                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6239                         kvm_handle_pmu_event(vcpu);
6240                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6241                         kvm_deliver_pmi(vcpu);
6242                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6243                         vcpu_scan_ioapic(vcpu);
6244                 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6245                         kvm_vcpu_reload_apic_access_page(vcpu);
6246         }
6247
6248         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
6249                 kvm_apic_accept_events(vcpu);
6250                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6251                         r = 1;
6252                         goto out;
6253                 }
6254
6255                 if (inject_pending_event(vcpu, req_int_win) != 0)
6256                         req_immediate_exit = true;
6257                 /* enable NMI/IRQ window open exits if needed */
6258                 else if (vcpu->arch.nmi_pending)
6259                         kvm_x86_ops->enable_nmi_window(vcpu);
6260                 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6261                         kvm_x86_ops->enable_irq_window(vcpu);
6262
6263                 if (kvm_lapic_enabled(vcpu)) {
6264                         /*
6265                          * Update architecture specific hints for APIC
6266                          * virtual interrupt delivery.
6267                          */
6268                         if (kvm_x86_ops->hwapic_irr_update)
6269                                 kvm_x86_ops->hwapic_irr_update(vcpu,
6270                                         kvm_lapic_find_highest_irr(vcpu));
6271                         update_cr8_intercept(vcpu);
6272                         kvm_lapic_sync_to_vapic(vcpu);
6273                 }
6274         }
6275
6276         r = kvm_mmu_reload(vcpu);
6277         if (unlikely(r)) {
6278                 goto cancel_injection;
6279         }
6280
6281         preempt_disable();
6282
6283         kvm_x86_ops->prepare_guest_switch(vcpu);
6284         if (vcpu->fpu_active)
6285                 kvm_load_guest_fpu(vcpu);
6286         kvm_load_guest_xcr0(vcpu);
6287
6288         vcpu->mode = IN_GUEST_MODE;
6289
6290         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6291
6292         /* We should set ->mode before check ->requests,
6293          * see the comment in make_all_cpus_request.
6294          */
6295         smp_mb__after_srcu_read_unlock();
6296
6297         local_irq_disable();
6298
6299         if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
6300             || need_resched() || signal_pending(current)) {
6301                 vcpu->mode = OUTSIDE_GUEST_MODE;
6302                 smp_wmb();
6303                 local_irq_enable();
6304                 preempt_enable();
6305                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6306                 r = 1;
6307                 goto cancel_injection;
6308         }
6309
6310         if (req_immediate_exit)
6311                 smp_send_reschedule(vcpu->cpu);
6312
6313         kvm_guest_enter();
6314
6315         if (unlikely(vcpu->arch.switch_db_regs)) {
6316                 set_debugreg(0, 7);
6317                 set_debugreg(vcpu->arch.eff_db[0], 0);
6318                 set_debugreg(vcpu->arch.eff_db[1], 1);
6319                 set_debugreg(vcpu->arch.eff_db[2], 2);
6320                 set_debugreg(vcpu->arch.eff_db[3], 3);
6321                 set_debugreg(vcpu->arch.dr6, 6);
6322         }
6323
6324         trace_kvm_entry(vcpu->vcpu_id);
6325         wait_lapic_expire(vcpu);
6326         kvm_x86_ops->run(vcpu);
6327
6328         /*
6329          * Do this here before restoring debug registers on the host.  And
6330          * since we do this before handling the vmexit, a DR access vmexit
6331          * can (a) read the correct value of the debug registers, (b) set
6332          * KVM_DEBUGREG_WONT_EXIT again.
6333          */
6334         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6335                 int i;
6336
6337                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6338                 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6339                 for (i = 0; i < KVM_NR_DB_REGS; i++)
6340                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6341         }
6342
6343         /*
6344          * If the guest has used debug registers, at least dr7
6345          * will be disabled while returning to the host.
6346          * If we don't have active breakpoints in the host, we don't
6347          * care about the messed up debug address registers. But if
6348          * we have some of them active, restore the old state.
6349          */
6350         if (hw_breakpoint_active())
6351                 hw_breakpoint_restore();
6352
6353         vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6354                                                            native_read_tsc());
6355
6356         vcpu->mode = OUTSIDE_GUEST_MODE;
6357         smp_wmb();
6358
6359         /* Interrupt is enabled by handle_external_intr() */
6360         kvm_x86_ops->handle_external_intr(vcpu);
6361
6362         ++vcpu->stat.exits;
6363
6364         /*
6365          * We must have an instruction between local_irq_enable() and
6366          * kvm_guest_exit(), so the timer interrupt isn't delayed by
6367          * the interrupt shadow.  The stat.exits increment will do nicely.
6368          * But we need to prevent reordering, hence this barrier():
6369          */
6370         barrier();
6371
6372         kvm_guest_exit();
6373
6374         preempt_enable();
6375
6376         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6377
6378         /*
6379          * Profile KVM exit RIPs:
6380          */
6381         if (unlikely(prof_on == KVM_PROFILING)) {
6382                 unsigned long rip = kvm_rip_read(vcpu);
6383                 profile_hit(KVM_PROFILING, (void *)rip);
6384         }
6385
6386         if (unlikely(vcpu->arch.tsc_always_catchup))
6387                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6388
6389         if (vcpu->arch.apic_attention)
6390                 kvm_lapic_sync_from_vapic(vcpu);
6391
6392         r = kvm_x86_ops->handle_exit(vcpu);
6393         return r;
6394
6395 cancel_injection:
6396         kvm_x86_ops->cancel_injection(vcpu);
6397         if (unlikely(vcpu->arch.apic_attention))
6398                 kvm_lapic_sync_from_vapic(vcpu);
6399 out:
6400         return r;
6401 }
6402
6403
6404 static int __vcpu_run(struct kvm_vcpu *vcpu)
6405 {
6406         int r;
6407         struct kvm *kvm = vcpu->kvm;
6408
6409         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6410
6411         r = 1;
6412         while (r > 0) {
6413                 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6414                     !vcpu->arch.apf.halted)
6415                         r = vcpu_enter_guest(vcpu);
6416                 else {
6417                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6418                         kvm_vcpu_block(vcpu);
6419                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6420                         if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6421                                 kvm_apic_accept_events(vcpu);
6422                                 switch(vcpu->arch.mp_state) {
6423                                 case KVM_MP_STATE_HALTED:
6424                                         vcpu->arch.pv.pv_unhalted = false;
6425                                         vcpu->arch.mp_state =
6426                                                 KVM_MP_STATE_RUNNABLE;
6427                                 case KVM_MP_STATE_RUNNABLE:
6428                                         vcpu->arch.apf.halted = false;
6429                                         break;
6430                                 case KVM_MP_STATE_INIT_RECEIVED:
6431                                         break;
6432                                 default:
6433                                         r = -EINTR;
6434                                         break;
6435                                 }
6436                         }
6437                 }
6438
6439                 if (r <= 0)
6440                         break;
6441
6442                 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6443                 if (kvm_cpu_has_pending_timer(vcpu))
6444                         kvm_inject_pending_timer_irqs(vcpu);
6445
6446                 if (dm_request_for_irq_injection(vcpu)) {
6447                         r = -EINTR;
6448                         vcpu->run->exit_reason = KVM_EXIT_INTR;
6449                         ++vcpu->stat.request_irq_exits;
6450                 }
6451
6452                 kvm_check_async_pf_completion(vcpu);
6453
6454                 if (signal_pending(current)) {
6455                         r = -EINTR;
6456                         vcpu->run->exit_reason = KVM_EXIT_INTR;
6457                         ++vcpu->stat.signal_exits;
6458                 }
6459                 if (need_resched()) {
6460                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6461                         cond_resched();
6462                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6463                 }
6464         }
6465
6466         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6467
6468         return r;
6469 }
6470
6471 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6472 {
6473         int r;
6474         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6475         r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6476         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6477         if (r != EMULATE_DONE)
6478                 return 0;
6479         return 1;
6480 }
6481
6482 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6483 {
6484         BUG_ON(!vcpu->arch.pio.count);
6485
6486         return complete_emulated_io(vcpu);
6487 }
6488
6489 /*
6490  * Implements the following, as a state machine:
6491  *
6492  * read:
6493  *   for each fragment
6494  *     for each mmio piece in the fragment
6495  *       write gpa, len
6496  *       exit
6497  *       copy data
6498  *   execute insn
6499  *
6500  * write:
6501  *   for each fragment
6502  *     for each mmio piece in the fragment
6503  *       write gpa, len
6504  *       copy data
6505  *       exit
6506  */
6507 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6508 {
6509         struct kvm_run *run = vcpu->run;
6510         struct kvm_mmio_fragment *frag;
6511         unsigned len;
6512
6513         BUG_ON(!vcpu->mmio_needed);
6514
6515         /* Complete previous fragment */
6516         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6517         len = min(8u, frag->len);
6518         if (!vcpu->mmio_is_write)
6519                 memcpy(frag->data, run->mmio.data, len);
6520
6521         if (frag->len <= 8) {
6522                 /* Switch to the next fragment. */
6523                 frag++;
6524                 vcpu->mmio_cur_fragment++;
6525         } else {
6526                 /* Go forward to the next mmio piece. */
6527                 frag->data += len;
6528                 frag->gpa += len;
6529                 frag->len -= len;
6530         }
6531
6532         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6533                 vcpu->mmio_needed = 0;
6534
6535                 /* FIXME: return into emulator if single-stepping.  */
6536                 if (vcpu->mmio_is_write)
6537                         return 1;
6538                 vcpu->mmio_read_completed = 1;
6539                 return complete_emulated_io(vcpu);
6540         }
6541
6542         run->exit_reason = KVM_EXIT_MMIO;
6543         run->mmio.phys_addr = frag->gpa;
6544         if (vcpu->mmio_is_write)
6545                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6546         run->mmio.len = min(8u, frag->len);
6547         run->mmio.is_write = vcpu->mmio_is_write;
6548         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6549         return 0;
6550 }
6551
6552
6553 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6554 {
6555         int r;
6556         sigset_t sigsaved;
6557
6558         if (!tsk_used_math(current) && init_fpu(current))
6559                 return -ENOMEM;
6560
6561         if (vcpu->sigset_active)
6562                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6563
6564         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6565                 kvm_vcpu_block(vcpu);
6566                 kvm_apic_accept_events(vcpu);
6567                 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6568                 r = -EAGAIN;
6569                 goto out;
6570         }
6571
6572         /* re-sync apic's tpr */
6573         if (!irqchip_in_kernel(vcpu->kvm)) {
6574                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6575                         r = -EINVAL;
6576                         goto out;
6577                 }
6578         }
6579
6580         if (unlikely(vcpu->arch.complete_userspace_io)) {
6581                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6582                 vcpu->arch.complete_userspace_io = NULL;
6583                 r = cui(vcpu);
6584                 if (r <= 0)
6585                         goto out;
6586         } else
6587                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6588
6589         r = __vcpu_run(vcpu);
6590
6591 out:
6592         post_kvm_run_save(vcpu);
6593         if (vcpu->sigset_active)
6594                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6595
6596         return r;
6597 }
6598
6599 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6600 {
6601         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6602                 /*
6603                  * We are here if userspace calls get_regs() in the middle of
6604                  * instruction emulation. Registers state needs to be copied
6605                  * back from emulation context to vcpu. Userspace shouldn't do
6606                  * that usually, but some bad designed PV devices (vmware
6607                  * backdoor interface) need this to work
6608                  */
6609                 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6610                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6611         }
6612         regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6613         regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6614         regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6615         regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6616         regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6617         regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6618         regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6619         regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6620 #ifdef CONFIG_X86_64
6621         regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6622         regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6623         regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6624         regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6625         regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6626         regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6627         regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6628         regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6629 #endif
6630
6631         regs->rip = kvm_rip_read(vcpu);
6632         regs->rflags = kvm_get_rflags(vcpu);
6633
6634         return 0;
6635 }
6636
6637 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6638 {
6639         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6640         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6641
6642         kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6643         kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6644         kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6645         kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6646         kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6647         kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6648         kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6649         kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6650 #ifdef CONFIG_X86_64
6651         kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6652         kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6653         kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6654         kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6655         kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6656         kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6657         kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6658         kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6659 #endif
6660
6661         kvm_rip_write(vcpu, regs->rip);
6662         kvm_set_rflags(vcpu, regs->rflags);
6663
6664         vcpu->arch.exception.pending = false;
6665
6666         kvm_make_request(KVM_REQ_EVENT, vcpu);
6667
6668         return 0;
6669 }
6670
6671 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6672 {
6673         struct kvm_segment cs;
6674
6675         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6676         *db = cs.db;
6677         *l = cs.l;
6678 }
6679 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6680
6681 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6682                                   struct kvm_sregs *sregs)
6683 {
6684         struct desc_ptr dt;
6685
6686         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6687         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6688         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6689         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6690         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6691         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6692
6693         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6694         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6695
6696         kvm_x86_ops->get_idt(vcpu, &dt);
6697         sregs->idt.limit = dt.size;
6698         sregs->idt.base = dt.address;
6699         kvm_x86_ops->get_gdt(vcpu, &dt);
6700         sregs->gdt.limit = dt.size;
6701         sregs->gdt.base = dt.address;
6702
6703         sregs->cr0 = kvm_read_cr0(vcpu);
6704         sregs->cr2 = vcpu->arch.cr2;
6705         sregs->cr3 = kvm_read_cr3(vcpu);
6706         sregs->cr4 = kvm_read_cr4(vcpu);
6707         sregs->cr8 = kvm_get_cr8(vcpu);
6708         sregs->efer = vcpu->arch.efer;
6709         sregs->apic_base = kvm_get_apic_base(vcpu);
6710
6711         memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6712
6713         if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6714                 set_bit(vcpu->arch.interrupt.nr,
6715                         (unsigned long *)sregs->interrupt_bitmap);
6716
6717         return 0;
6718 }
6719
6720 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6721                                     struct kvm_mp_state *mp_state)
6722 {
6723         kvm_apic_accept_events(vcpu);
6724         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6725                                         vcpu->arch.pv.pv_unhalted)
6726                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6727         else
6728                 mp_state->mp_state = vcpu->arch.mp_state;
6729
6730         return 0;
6731 }
6732
6733 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6734                                     struct kvm_mp_state *mp_state)
6735 {
6736         if (!kvm_vcpu_has_lapic(vcpu) &&
6737             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6738                 return -EINVAL;
6739
6740         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6741                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6742                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6743         } else
6744                 vcpu->arch.mp_state = mp_state->mp_state;
6745         kvm_make_request(KVM_REQ_EVENT, vcpu);
6746         return 0;
6747 }
6748
6749 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6750                     int reason, bool has_error_code, u32 error_code)
6751 {
6752         struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6753         int ret;
6754
6755         init_emulate_ctxt(vcpu);
6756
6757         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6758                                    has_error_code, error_code);
6759
6760         if (ret)
6761                 return EMULATE_FAIL;
6762
6763         kvm_rip_write(vcpu, ctxt->eip);
6764         kvm_set_rflags(vcpu, ctxt->eflags);
6765         kvm_make_request(KVM_REQ_EVENT, vcpu);
6766         return EMULATE_DONE;
6767 }
6768 EXPORT_SYMBOL_GPL(kvm_task_switch);
6769
6770 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6771                                   struct kvm_sregs *sregs)
6772 {
6773         struct msr_data apic_base_msr;
6774         int mmu_reset_needed = 0;
6775         int pending_vec, max_bits, idx;
6776         struct desc_ptr dt;
6777
6778         if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6779                 return -EINVAL;
6780
6781         dt.size = sregs->idt.limit;
6782         dt.address = sregs->idt.base;
6783         kvm_x86_ops->set_idt(vcpu, &dt);
6784         dt.size = sregs->gdt.limit;
6785         dt.address = sregs->gdt.base;
6786         kvm_x86_ops->set_gdt(vcpu, &dt);
6787
6788         vcpu->arch.cr2 = sregs->cr2;
6789         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6790         vcpu->arch.cr3 = sregs->cr3;
6791         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6792
6793         kvm_set_cr8(vcpu, sregs->cr8);
6794
6795         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6796         kvm_x86_ops->set_efer(vcpu, sregs->efer);
6797         apic_base_msr.data = sregs->apic_base;
6798         apic_base_msr.host_initiated = true;
6799         kvm_set_apic_base(vcpu, &apic_base_msr);
6800
6801         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6802         kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6803         vcpu->arch.cr0 = sregs->cr0;
6804
6805         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6806         kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6807         if (sregs->cr4 & X86_CR4_OSXSAVE)
6808                 kvm_update_cpuid(vcpu);
6809
6810         idx = srcu_read_lock(&vcpu->kvm->srcu);
6811         if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6812                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6813                 mmu_reset_needed = 1;
6814         }
6815         srcu_read_unlock(&vcpu->kvm->srcu, idx);
6816
6817         if (mmu_reset_needed)
6818                 kvm_mmu_reset_context(vcpu);
6819
6820         max_bits = KVM_NR_INTERRUPTS;
6821         pending_vec = find_first_bit(
6822                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6823         if (pending_vec < max_bits) {
6824                 kvm_queue_interrupt(vcpu, pending_vec, false);
6825                 pr_debug("Set back pending irq %d\n", pending_vec);
6826         }
6827
6828         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6829         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6830         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6831         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6832         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6833         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6834
6835         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6836         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6837
6838         update_cr8_intercept(vcpu);
6839
6840         /* Older userspace won't unhalt the vcpu on reset. */
6841         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6842             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6843             !is_protmode(vcpu))
6844                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6845
6846         kvm_make_request(KVM_REQ_EVENT, vcpu);
6847
6848         return 0;
6849 }
6850
6851 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6852                                         struct kvm_guest_debug *dbg)
6853 {
6854         unsigned long rflags;
6855         int i, r;
6856
6857         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6858                 r = -EBUSY;
6859                 if (vcpu->arch.exception.pending)
6860                         goto out;
6861                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6862                         kvm_queue_exception(vcpu, DB_VECTOR);
6863                 else
6864                         kvm_queue_exception(vcpu, BP_VECTOR);
6865         }
6866
6867         /*
6868          * Read rflags as long as potentially injected trace flags are still
6869          * filtered out.
6870          */
6871         rflags = kvm_get_rflags(vcpu);
6872
6873         vcpu->guest_debug = dbg->control;
6874         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6875                 vcpu->guest_debug = 0;
6876
6877         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6878                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6879                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6880                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6881         } else {
6882                 for (i = 0; i < KVM_NR_DB_REGS; i++)
6883                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6884         }
6885         kvm_update_dr7(vcpu);
6886
6887         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6888                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6889                         get_segment_base(vcpu, VCPU_SREG_CS);
6890
6891         /*
6892          * Trigger an rflags update that will inject or remove the trace
6893          * flags.
6894          */
6895         kvm_set_rflags(vcpu, rflags);
6896
6897         kvm_x86_ops->update_db_bp_intercept(vcpu);
6898
6899         r = 0;
6900
6901 out:
6902
6903         return r;
6904 }
6905
6906 /*
6907  * Translate a guest virtual address to a guest physical address.
6908  */
6909 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6910                                     struct kvm_translation *tr)
6911 {
6912         unsigned long vaddr = tr->linear_address;
6913         gpa_t gpa;
6914         int idx;
6915
6916         idx = srcu_read_lock(&vcpu->kvm->srcu);
6917         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6918         srcu_read_unlock(&vcpu->kvm->srcu, idx);
6919         tr->physical_address = gpa;
6920         tr->valid = gpa != UNMAPPED_GVA;
6921         tr->writeable = 1;
6922         tr->usermode = 0;
6923
6924         return 0;
6925 }
6926
6927 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6928 {
6929         struct i387_fxsave_struct *fxsave =
6930                         &vcpu->arch.guest_fpu.state->fxsave;
6931
6932         memcpy(fpu->fpr, fxsave->st_space, 128);
6933         fpu->fcw = fxsave->cwd;
6934         fpu->fsw = fxsave->swd;
6935         fpu->ftwx = fxsave->twd;
6936         fpu->last_opcode = fxsave->fop;
6937         fpu->last_ip = fxsave->rip;
6938         fpu->last_dp = fxsave->rdp;
6939         memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6940
6941         return 0;
6942 }
6943
6944 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6945 {
6946         struct i387_fxsave_struct *fxsave =
6947                         &vcpu->arch.guest_fpu.state->fxsave;
6948
6949         memcpy(fxsave->st_space, fpu->fpr, 128);
6950         fxsave->cwd = fpu->fcw;
6951         fxsave->swd = fpu->fsw;
6952         fxsave->twd = fpu->ftwx;
6953         fxsave->fop = fpu->last_opcode;
6954         fxsave->rip = fpu->last_ip;
6955         fxsave->rdp = fpu->last_dp;
6956         memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6957
6958         return 0;
6959 }
6960
6961 int fx_init(struct kvm_vcpu *vcpu)
6962 {
6963         int err;
6964
6965         err = fpu_alloc(&vcpu->arch.guest_fpu);
6966         if (err)
6967                 return err;
6968
6969         fpu_finit(&vcpu->arch.guest_fpu);
6970         if (cpu_has_xsaves)
6971                 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
6972                         host_xcr0 | XSTATE_COMPACTION_ENABLED;
6973
6974         /*
6975          * Ensure guest xcr0 is valid for loading
6976          */
6977         vcpu->arch.xcr0 = XSTATE_FP;
6978
6979         vcpu->arch.cr0 |= X86_CR0_ET;
6980
6981         return 0;
6982 }
6983 EXPORT_SYMBOL_GPL(fx_init);
6984
6985 static void fx_free(struct kvm_vcpu *vcpu)
6986 {
6987         fpu_free(&vcpu->arch.guest_fpu);
6988 }
6989
6990 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6991 {
6992         if (vcpu->guest_fpu_loaded)
6993                 return;
6994
6995         /*
6996          * Restore all possible states in the guest,
6997          * and assume host would use all available bits.
6998          * Guest xcr0 would be loaded later.
6999          */
7000         kvm_put_guest_xcr0(vcpu);
7001         vcpu->guest_fpu_loaded = 1;
7002         __kernel_fpu_begin();
7003         fpu_restore_checking(&vcpu->arch.guest_fpu);
7004         trace_kvm_fpu(1);
7005 }
7006
7007 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7008 {
7009         kvm_put_guest_xcr0(vcpu);
7010
7011         if (!vcpu->guest_fpu_loaded)
7012                 return;
7013
7014         vcpu->guest_fpu_loaded = 0;
7015         fpu_save_init(&vcpu->arch.guest_fpu);
7016         __kernel_fpu_end();
7017         ++vcpu->stat.fpu_reload;
7018         kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7019         trace_kvm_fpu(0);
7020 }
7021
7022 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7023 {
7024         kvmclock_reset(vcpu);
7025
7026         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7027         fx_free(vcpu);
7028         kvm_x86_ops->vcpu_free(vcpu);
7029 }
7030
7031 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7032                                                 unsigned int id)
7033 {
7034         if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7035                 printk_once(KERN_WARNING
7036                 "kvm: SMP vm created on host with unstable TSC; "
7037                 "guest TSC will not be reliable\n");
7038         return kvm_x86_ops->vcpu_create(kvm, id);
7039 }
7040
7041 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7042 {
7043         int r;
7044
7045         vcpu->arch.mtrr_state.have_fixed = 1;
7046         r = vcpu_load(vcpu);
7047         if (r)
7048                 return r;
7049         kvm_vcpu_reset(vcpu);
7050         kvm_mmu_setup(vcpu);
7051         vcpu_put(vcpu);
7052
7053         return r;
7054 }
7055
7056 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
7057 {
7058         struct msr_data msr;
7059         struct kvm *kvm = vcpu->kvm;
7060
7061         if (vcpu_load(vcpu))
7062                 return;
7063         msr.data = 0x0;
7064         msr.index = MSR_IA32_TSC;
7065         msr.host_initiated = true;
7066         kvm_write_tsc(vcpu, &msr);
7067         vcpu_put(vcpu);
7068
7069         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7070                                         KVMCLOCK_SYNC_PERIOD);
7071 }
7072
7073 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
7074 {
7075         int r;
7076         vcpu->arch.apf.msr_val = 0;
7077
7078         r = vcpu_load(vcpu);
7079         BUG_ON(r);
7080         kvm_mmu_unload(vcpu);
7081         vcpu_put(vcpu);
7082
7083         fx_free(vcpu);
7084         kvm_x86_ops->vcpu_free(vcpu);
7085 }
7086
7087 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
7088 {
7089         atomic_set(&vcpu->arch.nmi_queued, 0);
7090         vcpu->arch.nmi_pending = 0;
7091         vcpu->arch.nmi_injected = false;
7092         kvm_clear_interrupt_queue(vcpu);
7093         kvm_clear_exception_queue(vcpu);
7094
7095         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
7096         vcpu->arch.dr6 = DR6_INIT;
7097         kvm_update_dr6(vcpu);
7098         vcpu->arch.dr7 = DR7_FIXED_1;
7099         kvm_update_dr7(vcpu);
7100
7101         kvm_make_request(KVM_REQ_EVENT, vcpu);
7102         vcpu->arch.apf.msr_val = 0;
7103         vcpu->arch.st.msr_val = 0;
7104
7105         kvmclock_reset(vcpu);
7106
7107         kvm_clear_async_pf_completion_queue(vcpu);
7108         kvm_async_pf_hash_reset(vcpu);
7109         vcpu->arch.apf.halted = false;
7110
7111         kvm_pmu_reset(vcpu);
7112
7113         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7114         vcpu->arch.regs_avail = ~0;
7115         vcpu->arch.regs_dirty = ~0;
7116
7117         kvm_x86_ops->vcpu_reset(vcpu);
7118 }
7119
7120 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
7121 {
7122         struct kvm_segment cs;
7123
7124         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7125         cs.selector = vector << 8;
7126         cs.base = vector << 12;
7127         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7128         kvm_rip_write(vcpu, 0);
7129 }
7130
7131 int kvm_arch_hardware_enable(void)
7132 {
7133         struct kvm *kvm;
7134         struct kvm_vcpu *vcpu;
7135         int i;
7136         int ret;
7137         u64 local_tsc;
7138         u64 max_tsc = 0;
7139         bool stable, backwards_tsc = false;
7140
7141         kvm_shared_msr_cpu_online();
7142         ret = kvm_x86_ops->hardware_enable();
7143         if (ret != 0)
7144                 return ret;
7145
7146         local_tsc = native_read_tsc();
7147         stable = !check_tsc_unstable();
7148         list_for_each_entry(kvm, &vm_list, vm_list) {
7149                 kvm_for_each_vcpu(i, vcpu, kvm) {
7150                         if (!stable && vcpu->cpu == smp_processor_id())
7151                                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7152                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7153                                 backwards_tsc = true;
7154                                 if (vcpu->arch.last_host_tsc > max_tsc)
7155                                         max_tsc = vcpu->arch.last_host_tsc;
7156                         }
7157                 }
7158         }
7159
7160         /*
7161          * Sometimes, even reliable TSCs go backwards.  This happens on
7162          * platforms that reset TSC during suspend or hibernate actions, but
7163          * maintain synchronization.  We must compensate.  Fortunately, we can
7164          * detect that condition here, which happens early in CPU bringup,
7165          * before any KVM threads can be running.  Unfortunately, we can't
7166          * bring the TSCs fully up to date with real time, as we aren't yet far
7167          * enough into CPU bringup that we know how much real time has actually
7168          * elapsed; our helper function, get_kernel_ns() will be using boot
7169          * variables that haven't been updated yet.
7170          *
7171          * So we simply find the maximum observed TSC above, then record the
7172          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
7173          * the adjustment will be applied.  Note that we accumulate
7174          * adjustments, in case multiple suspend cycles happen before some VCPU
7175          * gets a chance to run again.  In the event that no KVM threads get a
7176          * chance to run, we will miss the entire elapsed period, as we'll have
7177          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7178          * loose cycle time.  This isn't too big a deal, since the loss will be
7179          * uniform across all VCPUs (not to mention the scenario is extremely
7180          * unlikely). It is possible that a second hibernate recovery happens
7181          * much faster than a first, causing the observed TSC here to be
7182          * smaller; this would require additional padding adjustment, which is
7183          * why we set last_host_tsc to the local tsc observed here.
7184          *
7185          * N.B. - this code below runs only on platforms with reliable TSC,
7186          * as that is the only way backwards_tsc is set above.  Also note
7187          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7188          * have the same delta_cyc adjustment applied if backwards_tsc
7189          * is detected.  Note further, this adjustment is only done once,
7190          * as we reset last_host_tsc on all VCPUs to stop this from being
7191          * called multiple times (one for each physical CPU bringup).
7192          *
7193          * Platforms with unreliable TSCs don't have to deal with this, they
7194          * will be compensated by the logic in vcpu_load, which sets the TSC to
7195          * catchup mode.  This will catchup all VCPUs to real time, but cannot
7196          * guarantee that they stay in perfect synchronization.
7197          */
7198         if (backwards_tsc) {
7199                 u64 delta_cyc = max_tsc - local_tsc;
7200                 backwards_tsc_observed = true;
7201                 list_for_each_entry(kvm, &vm_list, vm_list) {
7202                         kvm_for_each_vcpu(i, vcpu, kvm) {
7203                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7204                                 vcpu->arch.last_host_tsc = local_tsc;
7205                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7206                         }
7207
7208                         /*
7209                          * We have to disable TSC offset matching.. if you were
7210                          * booting a VM while issuing an S4 host suspend....
7211                          * you may have some problem.  Solving this issue is
7212                          * left as an exercise to the reader.
7213                          */
7214                         kvm->arch.last_tsc_nsec = 0;
7215                         kvm->arch.last_tsc_write = 0;
7216                 }
7217
7218         }
7219         return 0;
7220 }
7221
7222 void kvm_arch_hardware_disable(void)
7223 {
7224         kvm_x86_ops->hardware_disable();
7225         drop_user_return_notifiers();
7226 }
7227
7228 int kvm_arch_hardware_setup(void)
7229 {
7230         return kvm_x86_ops->hardware_setup();
7231 }
7232
7233 void kvm_arch_hardware_unsetup(void)
7234 {
7235         kvm_x86_ops->hardware_unsetup();
7236 }
7237
7238 void kvm_arch_check_processor_compat(void *rtn)
7239 {
7240         kvm_x86_ops->check_processor_compatibility(rtn);
7241 }
7242
7243 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7244 {
7245         return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7246 }
7247
7248 struct static_key kvm_no_apic_vcpu __read_mostly;
7249
7250 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7251 {
7252         struct page *page;
7253         struct kvm *kvm;
7254         int r;
7255
7256         BUG_ON(vcpu->kvm == NULL);
7257         kvm = vcpu->kvm;
7258
7259         vcpu->arch.pv.pv_unhalted = false;
7260         vcpu->arch.emulate_ctxt.ops = &emulate_ops;
7261         if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
7262                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7263         else
7264                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
7265
7266         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7267         if (!page) {
7268                 r = -ENOMEM;
7269                 goto fail;
7270         }
7271         vcpu->arch.pio_data = page_address(page);
7272
7273         kvm_set_tsc_khz(vcpu, max_tsc_khz);
7274
7275         r = kvm_mmu_create(vcpu);
7276         if (r < 0)
7277                 goto fail_free_pio_data;
7278
7279         if (irqchip_in_kernel(kvm)) {
7280                 r = kvm_create_lapic(vcpu);
7281                 if (r < 0)
7282                         goto fail_mmu_destroy;
7283         } else
7284                 static_key_slow_inc(&kvm_no_apic_vcpu);
7285
7286         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7287                                        GFP_KERNEL);
7288         if (!vcpu->arch.mce_banks) {
7289                 r = -ENOMEM;
7290                 goto fail_free_lapic;
7291         }
7292         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7293
7294         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7295                 r = -ENOMEM;
7296                 goto fail_free_mce_banks;
7297         }
7298
7299         r = fx_init(vcpu);
7300         if (r)
7301                 goto fail_free_wbinvd_dirty_mask;
7302
7303         vcpu->arch.ia32_tsc_adjust_msr = 0x0;
7304         vcpu->arch.pv_time_enabled = false;
7305
7306         vcpu->arch.guest_supported_xcr0 = 0;
7307         vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
7308
7309         kvm_async_pf_hash_reset(vcpu);
7310         kvm_pmu_init(vcpu);
7311
7312         return 0;
7313 fail_free_wbinvd_dirty_mask:
7314         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
7315 fail_free_mce_banks:
7316         kfree(vcpu->arch.mce_banks);
7317 fail_free_lapic:
7318         kvm_free_lapic(vcpu);
7319 fail_mmu_destroy:
7320         kvm_mmu_destroy(vcpu);
7321 fail_free_pio_data:
7322         free_page((unsigned long)vcpu->arch.pio_data);
7323 fail:
7324         return r;
7325 }
7326
7327 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7328 {
7329         int idx;
7330
7331         kvm_pmu_destroy(vcpu);
7332         kfree(vcpu->arch.mce_banks);
7333         kvm_free_lapic(vcpu);
7334         idx = srcu_read_lock(&vcpu->kvm->srcu);
7335         kvm_mmu_destroy(vcpu);
7336         srcu_read_unlock(&vcpu->kvm->srcu, idx);
7337         free_page((unsigned long)vcpu->arch.pio_data);
7338         if (!irqchip_in_kernel(vcpu->kvm))
7339                 static_key_slow_dec(&kvm_no_apic_vcpu);
7340 }
7341
7342 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7343 {
7344         kvm_x86_ops->sched_in(vcpu, cpu);
7345 }
7346
7347 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
7348 {
7349         if (type)
7350                 return -EINVAL;
7351
7352         INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
7353         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
7354         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
7355         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
7356         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
7357
7358         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7359         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7360         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7361         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7362                 &kvm->arch.irq_sources_bitmap);
7363
7364         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
7365         mutex_init(&kvm->arch.apic_map_lock);
7366         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7367
7368         pvclock_update_vm_gtod_copy(kvm);
7369
7370         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
7371         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7372
7373         return 0;
7374 }
7375
7376 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7377 {
7378         int r;
7379         r = vcpu_load(vcpu);
7380         BUG_ON(r);
7381         kvm_mmu_unload(vcpu);
7382         vcpu_put(vcpu);
7383 }
7384
7385 static void kvm_free_vcpus(struct kvm *kvm)
7386 {
7387         unsigned int i;
7388         struct kvm_vcpu *vcpu;
7389
7390         /*
7391          * Unpin any mmu pages first.
7392          */
7393         kvm_for_each_vcpu(i, vcpu, kvm) {
7394                 kvm_clear_async_pf_completion_queue(vcpu);
7395                 kvm_unload_vcpu_mmu(vcpu);
7396         }
7397         kvm_for_each_vcpu(i, vcpu, kvm)
7398                 kvm_arch_vcpu_free(vcpu);
7399
7400         mutex_lock(&kvm->lock);
7401         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7402                 kvm->vcpus[i] = NULL;
7403
7404         atomic_set(&kvm->online_vcpus, 0);
7405         mutex_unlock(&kvm->lock);
7406 }
7407
7408 void kvm_arch_sync_events(struct kvm *kvm)
7409 {
7410         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7411         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
7412         kvm_free_all_assigned_devices(kvm);
7413         kvm_free_pit(kvm);
7414 }
7415
7416 void kvm_arch_destroy_vm(struct kvm *kvm)
7417 {
7418         if (current->mm == kvm->mm) {
7419                 /*
7420                  * Free memory regions allocated on behalf of userspace,
7421                  * unless the the memory map has changed due to process exit
7422                  * or fd copying.
7423                  */
7424                 struct kvm_userspace_memory_region mem;
7425                 memset(&mem, 0, sizeof(mem));
7426                 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7427                 kvm_set_memory_region(kvm, &mem);
7428
7429                 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7430                 kvm_set_memory_region(kvm, &mem);
7431
7432                 mem.slot = TSS_PRIVATE_MEMSLOT;
7433                 kvm_set_memory_region(kvm, &mem);
7434         }
7435         kvm_iommu_unmap_guest(kvm);
7436         kfree(kvm->arch.vpic);
7437         kfree(kvm->arch.vioapic);
7438         kvm_free_vcpus(kvm);
7439         kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
7440 }
7441
7442 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
7443                            struct kvm_memory_slot *dont)
7444 {
7445         int i;
7446
7447         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7448                 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7449                         kvfree(free->arch.rmap[i]);
7450                         free->arch.rmap[i] = NULL;
7451                 }
7452                 if (i == 0)
7453                         continue;
7454
7455                 if (!dont || free->arch.lpage_info[i - 1] !=
7456                              dont->arch.lpage_info[i - 1]) {
7457                         kvfree(free->arch.lpage_info[i - 1]);
7458                         free->arch.lpage_info[i - 1] = NULL;
7459                 }
7460         }
7461 }
7462
7463 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7464                             unsigned long npages)
7465 {
7466         int i;
7467
7468         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7469                 unsigned long ugfn;
7470                 int lpages;
7471                 int level = i + 1;
7472
7473                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7474                                       slot->base_gfn, level) + 1;
7475
7476                 slot->arch.rmap[i] =
7477                         kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7478                 if (!slot->arch.rmap[i])
7479                         goto out_free;
7480                 if (i == 0)
7481                         continue;
7482
7483                 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7484                                         sizeof(*slot->arch.lpage_info[i - 1]));
7485                 if (!slot->arch.lpage_info[i - 1])
7486                         goto out_free;
7487
7488                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
7489                         slot->arch.lpage_info[i - 1][0].write_count = 1;
7490                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
7491                         slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
7492                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7493                 /*
7494                  * If the gfn and userspace address are not aligned wrt each
7495                  * other, or if explicitly asked to, disable large page
7496                  * support for this slot
7497                  */
7498                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7499                     !kvm_largepages_enabled()) {
7500                         unsigned long j;
7501
7502                         for (j = 0; j < lpages; ++j)
7503                                 slot->arch.lpage_info[i - 1][j].write_count = 1;
7504                 }
7505         }
7506
7507         return 0;
7508
7509 out_free:
7510         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7511                 kvfree(slot->arch.rmap[i]);
7512                 slot->arch.rmap[i] = NULL;
7513                 if (i == 0)
7514                         continue;
7515
7516                 kvfree(slot->arch.lpage_info[i - 1]);
7517                 slot->arch.lpage_info[i - 1] = NULL;
7518         }
7519         return -ENOMEM;
7520 }
7521
7522 void kvm_arch_memslots_updated(struct kvm *kvm)
7523 {
7524         /*
7525          * memslots->generation has been incremented.
7526          * mmio generation may have reached its maximum value.
7527          */
7528         kvm_mmu_invalidate_mmio_sptes(kvm);
7529 }
7530
7531 int kvm_arch_prepare_memory_region(struct kvm *kvm,
7532                                 struct kvm_memory_slot *memslot,
7533                                 struct kvm_userspace_memory_region *mem,
7534                                 enum kvm_mr_change change)
7535 {
7536         /*
7537          * Only private memory slots need to be mapped here since
7538          * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7539          */
7540         if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7541                 unsigned long userspace_addr;
7542
7543                 /*
7544                  * MAP_SHARED to prevent internal slot pages from being moved
7545                  * by fork()/COW.
7546                  */
7547                 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7548                                          PROT_READ | PROT_WRITE,
7549                                          MAP_SHARED | MAP_ANONYMOUS, 0);
7550
7551                 if (IS_ERR((void *)userspace_addr))
7552                         return PTR_ERR((void *)userspace_addr);
7553
7554                 memslot->userspace_addr = userspace_addr;
7555         }
7556
7557         return 0;
7558 }
7559
7560 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7561                                      struct kvm_memory_slot *new)
7562 {
7563         /* Still write protect RO slot */
7564         if (new->flags & KVM_MEM_READONLY) {
7565                 kvm_mmu_slot_remove_write_access(kvm, new);
7566                 return;
7567         }
7568
7569         /*
7570          * Call kvm_x86_ops dirty logging hooks when they are valid.
7571          *
7572          * kvm_x86_ops->slot_disable_log_dirty is called when:
7573          *
7574          *  - KVM_MR_CREATE with dirty logging is disabled
7575          *  - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7576          *
7577          * The reason is, in case of PML, we need to set D-bit for any slots
7578          * with dirty logging disabled in order to eliminate unnecessary GPA
7579          * logging in PML buffer (and potential PML buffer full VMEXT). This
7580          * guarantees leaving PML enabled during guest's lifetime won't have
7581          * any additonal overhead from PML when guest is running with dirty
7582          * logging disabled for memory slots.
7583          *
7584          * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7585          * to dirty logging mode.
7586          *
7587          * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7588          *
7589          * In case of write protect:
7590          *
7591          * Write protect all pages for dirty logging.
7592          *
7593          * All the sptes including the large sptes which point to this
7594          * slot are set to readonly. We can not create any new large
7595          * spte on this slot until the end of the logging.
7596          *
7597          * See the comments in fast_page_fault().
7598          */
7599         if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7600                 if (kvm_x86_ops->slot_enable_log_dirty)
7601                         kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7602                 else
7603                         kvm_mmu_slot_remove_write_access(kvm, new);
7604         } else {
7605                 if (kvm_x86_ops->slot_disable_log_dirty)
7606                         kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7607         }
7608 }
7609
7610 void kvm_arch_commit_memory_region(struct kvm *kvm,
7611                                 struct kvm_userspace_memory_region *mem,
7612                                 const struct kvm_memory_slot *old,
7613                                 enum kvm_mr_change change)
7614 {
7615         struct kvm_memory_slot *new;
7616         int nr_mmu_pages = 0;
7617
7618         if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7619                 int ret;
7620
7621                 ret = vm_munmap(old->userspace_addr,
7622                                 old->npages * PAGE_SIZE);
7623                 if (ret < 0)
7624                         printk(KERN_WARNING
7625                                "kvm_vm_ioctl_set_memory_region: "
7626                                "failed to munmap memory\n");
7627         }
7628
7629         if (!kvm->arch.n_requested_mmu_pages)
7630                 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7631
7632         if (nr_mmu_pages)
7633                 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7634
7635         /* It's OK to get 'new' slot here as it has already been installed */
7636         new = id_to_memslot(kvm->memslots, mem->slot);
7637
7638         /*
7639          * Set up write protection and/or dirty logging for the new slot.
7640          *
7641          * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7642          * been zapped so no dirty logging staff is needed for old slot. For
7643          * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7644          * new and it's also covered when dealing with the new slot.
7645          */
7646         if (change != KVM_MR_DELETE)
7647                 kvm_mmu_slot_apply_flags(kvm, new);
7648 }
7649
7650 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7651 {
7652         kvm_mmu_invalidate_zap_all_pages(kvm);
7653 }
7654
7655 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7656                                    struct kvm_memory_slot *slot)
7657 {
7658         kvm_mmu_invalidate_zap_all_pages(kvm);
7659 }
7660
7661 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7662 {
7663         if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7664                 kvm_x86_ops->check_nested_events(vcpu, false);
7665
7666         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7667                 !vcpu->arch.apf.halted)
7668                 || !list_empty_careful(&vcpu->async_pf.done)
7669                 || kvm_apic_has_events(vcpu)
7670                 || vcpu->arch.pv.pv_unhalted
7671                 || atomic_read(&vcpu->arch.nmi_queued) ||
7672                 (kvm_arch_interrupt_allowed(vcpu) &&
7673                  kvm_cpu_has_interrupt(vcpu));
7674 }
7675
7676 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7677 {
7678         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7679 }
7680
7681 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7682 {
7683         return kvm_x86_ops->interrupt_allowed(vcpu);
7684 }
7685
7686 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
7687 {
7688         if (is_64_bit_mode(vcpu))
7689                 return kvm_rip_read(vcpu);
7690         return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7691                      kvm_rip_read(vcpu));
7692 }
7693 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
7694
7695 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7696 {
7697         return kvm_get_linear_rip(vcpu) == linear_rip;
7698 }
7699 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7700
7701 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7702 {
7703         unsigned long rflags;
7704
7705         rflags = kvm_x86_ops->get_rflags(vcpu);
7706         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7707                 rflags &= ~X86_EFLAGS_TF;
7708         return rflags;
7709 }
7710 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7711
7712 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7713 {
7714         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7715             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7716                 rflags |= X86_EFLAGS_TF;
7717         kvm_x86_ops->set_rflags(vcpu, rflags);
7718 }
7719
7720 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7721 {
7722         __kvm_set_rflags(vcpu, rflags);
7723         kvm_make_request(KVM_REQ_EVENT, vcpu);
7724 }
7725 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7726
7727 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7728 {
7729         int r;
7730
7731         if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7732               work->wakeup_all)
7733                 return;
7734
7735         r = kvm_mmu_reload(vcpu);
7736         if (unlikely(r))
7737                 return;
7738
7739         if (!vcpu->arch.mmu.direct_map &&
7740               work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7741                 return;
7742
7743         vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7744 }
7745
7746 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7747 {
7748         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7749 }
7750
7751 static inline u32 kvm_async_pf_next_probe(u32 key)
7752 {
7753         return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7754 }
7755
7756 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7757 {
7758         u32 key = kvm_async_pf_hash_fn(gfn);
7759
7760         while (vcpu->arch.apf.gfns[key] != ~0)
7761                 key = kvm_async_pf_next_probe(key);
7762
7763         vcpu->arch.apf.gfns[key] = gfn;
7764 }
7765
7766 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7767 {
7768         int i;
7769         u32 key = kvm_async_pf_hash_fn(gfn);
7770
7771         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7772                      (vcpu->arch.apf.gfns[key] != gfn &&
7773                       vcpu->arch.apf.gfns[key] != ~0); i++)
7774                 key = kvm_async_pf_next_probe(key);
7775
7776         return key;
7777 }
7778
7779 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7780 {
7781         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7782 }
7783
7784 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7785 {
7786         u32 i, j, k;
7787
7788         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7789         while (true) {
7790                 vcpu->arch.apf.gfns[i] = ~0;
7791                 do {
7792                         j = kvm_async_pf_next_probe(j);
7793                         if (vcpu->arch.apf.gfns[j] == ~0)
7794                                 return;
7795                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7796                         /*
7797                          * k lies cyclically in ]i,j]
7798                          * |    i.k.j |
7799                          * |....j i.k.| or  |.k..j i...|
7800                          */
7801                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7802                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7803                 i = j;
7804         }
7805 }
7806
7807 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7808 {
7809
7810         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7811                                       sizeof(val));
7812 }
7813
7814 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7815                                      struct kvm_async_pf *work)
7816 {
7817         struct x86_exception fault;
7818
7819         trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7820         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7821
7822         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7823             (vcpu->arch.apf.send_user_only &&
7824              kvm_x86_ops->get_cpl(vcpu) == 0))
7825                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7826         else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7827                 fault.vector = PF_VECTOR;
7828                 fault.error_code_valid = true;
7829                 fault.error_code = 0;
7830                 fault.nested_page_fault = false;
7831                 fault.address = work->arch.token;
7832                 kvm_inject_page_fault(vcpu, &fault);
7833         }
7834 }
7835
7836 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7837                                  struct kvm_async_pf *work)
7838 {
7839         struct x86_exception fault;
7840
7841         trace_kvm_async_pf_ready(work->arch.token, work->gva);
7842         if (work->wakeup_all)
7843                 work->arch.token = ~0; /* broadcast wakeup */
7844         else
7845                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7846
7847         if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7848             !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7849                 fault.vector = PF_VECTOR;
7850                 fault.error_code_valid = true;
7851                 fault.error_code = 0;
7852                 fault.nested_page_fault = false;
7853                 fault.address = work->arch.token;
7854                 kvm_inject_page_fault(vcpu, &fault);
7855         }
7856         vcpu->arch.apf.halted = false;
7857         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7858 }
7859
7860 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7861 {
7862         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7863                 return true;
7864         else
7865                 return !kvm_event_needs_reinjection(vcpu) &&
7866                         kvm_x86_ops->interrupt_allowed(vcpu);
7867 }
7868
7869 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7870 {
7871         atomic_inc(&kvm->arch.noncoherent_dma_count);
7872 }
7873 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7874
7875 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7876 {
7877         atomic_dec(&kvm->arch.noncoherent_dma_count);
7878 }
7879 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7880
7881 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7882 {
7883         return atomic_read(&kvm->arch.noncoherent_dma_count);
7884 }
7885 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7886
7887 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7888 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7889 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7890 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7891 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7892 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7893 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7894 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7895 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7896 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7897 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7898 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
7899 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7900 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
7901 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);