Merge tag 'iwlwifi-for-kalle-2015-05-28' of https://git.kernel.org/pub/scm/linux...
[sfrench/cifs-2.6.git] / arch / x86 / kvm / x86.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * derived from drivers/kvm/kvm_main.c
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright (C) 2008 Qumranet, Inc.
8  * Copyright IBM Corporation, 2008
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Amit Shah    <amit.shah@qumranet.com>
15  *   Ben-Ami Yassour <benami@il.ibm.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31
32 #include <linux/clocksource.h>
33 #include <linux/interrupt.h>
34 #include <linux/kvm.h>
35 #include <linux/fs.h>
36 #include <linux/vmalloc.h>
37 #include <linux/module.h>
38 #include <linux/mman.h>
39 #include <linux/highmem.h>
40 #include <linux/iommu.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/cpufreq.h>
43 #include <linux/user-return-notifier.h>
44 #include <linux/srcu.h>
45 #include <linux/slab.h>
46 #include <linux/perf_event.h>
47 #include <linux/uaccess.h>
48 #include <linux/hash.h>
49 #include <linux/pci.h>
50 #include <linux/timekeeper_internal.h>
51 #include <linux/pvclock_gtod.h>
52 #include <trace/events/kvm.h>
53
54 #define CREATE_TRACE_POINTS
55 #include "trace.h"
56
57 #include <asm/debugreg.h>
58 #include <asm/msr.h>
59 #include <asm/desc.h>
60 #include <asm/mtrr.h>
61 #include <asm/mce.h>
62 #include <asm/i387.h>
63 #include <asm/fpu-internal.h> /* Ugh! */
64 #include <asm/xcr.h>
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67
68 #define MAX_IO_MSRS 256
69 #define KVM_MAX_MCE_BANKS 32
70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71
72 #define emul_to_vcpu(ctxt) \
73         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
75 /* EFER defaults:
76  * - enable syscall per default because its emulated by KVM
77  * - enable LME and LMA per default on 64 bit KVM
78  */
79 #ifdef CONFIG_X86_64
80 static
81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 #else
83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
84 #endif
85
86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88
89 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
90 static void process_nmi(struct kvm_vcpu *vcpu);
91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
92
93 struct kvm_x86_ops *kvm_x86_ops;
94 EXPORT_SYMBOL_GPL(kvm_x86_ops);
95
96 static bool ignore_msrs = 0;
97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
99 unsigned int min_timer_period_us = 500;
100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
102 bool kvm_has_tsc_control;
103 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
104 u32  kvm_max_guest_tsc_khz;
105 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106
107 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
108 static u32 tsc_tolerance_ppm = 250;
109 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110
111 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
112 unsigned int lapic_timer_advance_ns = 0;
113 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
114
115 static bool backwards_tsc_observed = false;
116
117 #define KVM_NR_SHARED_MSRS 16
118
119 struct kvm_shared_msrs_global {
120         int nr;
121         u32 msrs[KVM_NR_SHARED_MSRS];
122 };
123
124 struct kvm_shared_msrs {
125         struct user_return_notifier urn;
126         bool registered;
127         struct kvm_shared_msr_values {
128                 u64 host;
129                 u64 curr;
130         } values[KVM_NR_SHARED_MSRS];
131 };
132
133 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
134 static struct kvm_shared_msrs __percpu *shared_msrs;
135
136 struct kvm_stats_debugfs_item debugfs_entries[] = {
137         { "pf_fixed", VCPU_STAT(pf_fixed) },
138         { "pf_guest", VCPU_STAT(pf_guest) },
139         { "tlb_flush", VCPU_STAT(tlb_flush) },
140         { "invlpg", VCPU_STAT(invlpg) },
141         { "exits", VCPU_STAT(exits) },
142         { "io_exits", VCPU_STAT(io_exits) },
143         { "mmio_exits", VCPU_STAT(mmio_exits) },
144         { "signal_exits", VCPU_STAT(signal_exits) },
145         { "irq_window", VCPU_STAT(irq_window_exits) },
146         { "nmi_window", VCPU_STAT(nmi_window_exits) },
147         { "halt_exits", VCPU_STAT(halt_exits) },
148         { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
149         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
150         { "hypercalls", VCPU_STAT(hypercalls) },
151         { "request_irq", VCPU_STAT(request_irq_exits) },
152         { "irq_exits", VCPU_STAT(irq_exits) },
153         { "host_state_reload", VCPU_STAT(host_state_reload) },
154         { "efer_reload", VCPU_STAT(efer_reload) },
155         { "fpu_reload", VCPU_STAT(fpu_reload) },
156         { "insn_emulation", VCPU_STAT(insn_emulation) },
157         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
158         { "irq_injections", VCPU_STAT(irq_injections) },
159         { "nmi_injections", VCPU_STAT(nmi_injections) },
160         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
161         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
162         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
163         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
164         { "mmu_flooded", VM_STAT(mmu_flooded) },
165         { "mmu_recycled", VM_STAT(mmu_recycled) },
166         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
167         { "mmu_unsync", VM_STAT(mmu_unsync) },
168         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
169         { "largepages", VM_STAT(lpages) },
170         { NULL }
171 };
172
173 u64 __read_mostly host_xcr0;
174
175 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
176
177 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
178 {
179         int i;
180         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
181                 vcpu->arch.apf.gfns[i] = ~0;
182 }
183
184 static void kvm_on_user_return(struct user_return_notifier *urn)
185 {
186         unsigned slot;
187         struct kvm_shared_msrs *locals
188                 = container_of(urn, struct kvm_shared_msrs, urn);
189         struct kvm_shared_msr_values *values;
190
191         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
192                 values = &locals->values[slot];
193                 if (values->host != values->curr) {
194                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
195                         values->curr = values->host;
196                 }
197         }
198         locals->registered = false;
199         user_return_notifier_unregister(urn);
200 }
201
202 static void shared_msr_update(unsigned slot, u32 msr)
203 {
204         u64 value;
205         unsigned int cpu = smp_processor_id();
206         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
207
208         /* only read, and nobody should modify it at this time,
209          * so don't need lock */
210         if (slot >= shared_msrs_global.nr) {
211                 printk(KERN_ERR "kvm: invalid MSR slot!");
212                 return;
213         }
214         rdmsrl_safe(msr, &value);
215         smsr->values[slot].host = value;
216         smsr->values[slot].curr = value;
217 }
218
219 void kvm_define_shared_msr(unsigned slot, u32 msr)
220 {
221         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
222         if (slot >= shared_msrs_global.nr)
223                 shared_msrs_global.nr = slot + 1;
224         shared_msrs_global.msrs[slot] = msr;
225         /* we need ensured the shared_msr_global have been updated */
226         smp_wmb();
227 }
228 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
229
230 static void kvm_shared_msr_cpu_online(void)
231 {
232         unsigned i;
233
234         for (i = 0; i < shared_msrs_global.nr; ++i)
235                 shared_msr_update(i, shared_msrs_global.msrs[i]);
236 }
237
238 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
239 {
240         unsigned int cpu = smp_processor_id();
241         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
242         int err;
243
244         if (((value ^ smsr->values[slot].curr) & mask) == 0)
245                 return 0;
246         smsr->values[slot].curr = value;
247         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
248         if (err)
249                 return 1;
250
251         if (!smsr->registered) {
252                 smsr->urn.on_user_return = kvm_on_user_return;
253                 user_return_notifier_register(&smsr->urn);
254                 smsr->registered = true;
255         }
256         return 0;
257 }
258 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
259
260 static void drop_user_return_notifiers(void)
261 {
262         unsigned int cpu = smp_processor_id();
263         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
264
265         if (smsr->registered)
266                 kvm_on_user_return(&smsr->urn);
267 }
268
269 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
270 {
271         return vcpu->arch.apic_base;
272 }
273 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
274
275 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
276 {
277         u64 old_state = vcpu->arch.apic_base &
278                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
279         u64 new_state = msr_info->data &
280                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
282                 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
283
284         if (!msr_info->host_initiated &&
285             ((msr_info->data & reserved_bits) != 0 ||
286              new_state == X2APIC_ENABLE ||
287              (new_state == MSR_IA32_APICBASE_ENABLE &&
288               old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
289              (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
290               old_state == 0)))
291                 return 1;
292
293         kvm_lapic_set_base(vcpu, msr_info->data);
294         return 0;
295 }
296 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
297
298 asmlinkage __visible void kvm_spurious_fault(void)
299 {
300         /* Fault while not rebooting.  We want the trace. */
301         BUG();
302 }
303 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
304
305 #define EXCPT_BENIGN            0
306 #define EXCPT_CONTRIBUTORY      1
307 #define EXCPT_PF                2
308
309 static int exception_class(int vector)
310 {
311         switch (vector) {
312         case PF_VECTOR:
313                 return EXCPT_PF;
314         case DE_VECTOR:
315         case TS_VECTOR:
316         case NP_VECTOR:
317         case SS_VECTOR:
318         case GP_VECTOR:
319                 return EXCPT_CONTRIBUTORY;
320         default:
321                 break;
322         }
323         return EXCPT_BENIGN;
324 }
325
326 #define EXCPT_FAULT             0
327 #define EXCPT_TRAP              1
328 #define EXCPT_ABORT             2
329 #define EXCPT_INTERRUPT         3
330
331 static int exception_type(int vector)
332 {
333         unsigned int mask;
334
335         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
336                 return EXCPT_INTERRUPT;
337
338         mask = 1 << vector;
339
340         /* #DB is trap, as instruction watchpoints are handled elsewhere */
341         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
342                 return EXCPT_TRAP;
343
344         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
345                 return EXCPT_ABORT;
346
347         /* Reserved exceptions will result in fault */
348         return EXCPT_FAULT;
349 }
350
351 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
352                 unsigned nr, bool has_error, u32 error_code,
353                 bool reinject)
354 {
355         u32 prev_nr;
356         int class1, class2;
357
358         kvm_make_request(KVM_REQ_EVENT, vcpu);
359
360         if (!vcpu->arch.exception.pending) {
361         queue:
362                 if (has_error && !is_protmode(vcpu))
363                         has_error = false;
364                 vcpu->arch.exception.pending = true;
365                 vcpu->arch.exception.has_error_code = has_error;
366                 vcpu->arch.exception.nr = nr;
367                 vcpu->arch.exception.error_code = error_code;
368                 vcpu->arch.exception.reinject = reinject;
369                 return;
370         }
371
372         /* to check exception */
373         prev_nr = vcpu->arch.exception.nr;
374         if (prev_nr == DF_VECTOR) {
375                 /* triple fault -> shutdown */
376                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
377                 return;
378         }
379         class1 = exception_class(prev_nr);
380         class2 = exception_class(nr);
381         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
382                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
383                 /* generate double fault per SDM Table 5-5 */
384                 vcpu->arch.exception.pending = true;
385                 vcpu->arch.exception.has_error_code = true;
386                 vcpu->arch.exception.nr = DF_VECTOR;
387                 vcpu->arch.exception.error_code = 0;
388         } else
389                 /* replace previous exception with a new one in a hope
390                    that instruction re-execution will regenerate lost
391                    exception */
392                 goto queue;
393 }
394
395 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
396 {
397         kvm_multiple_exception(vcpu, nr, false, 0, false);
398 }
399 EXPORT_SYMBOL_GPL(kvm_queue_exception);
400
401 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
402 {
403         kvm_multiple_exception(vcpu, nr, false, 0, true);
404 }
405 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
406
407 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
408 {
409         if (err)
410                 kvm_inject_gp(vcpu, 0);
411         else
412                 kvm_x86_ops->skip_emulated_instruction(vcpu);
413 }
414 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
415
416 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
417 {
418         ++vcpu->stat.pf_guest;
419         vcpu->arch.cr2 = fault->address;
420         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
421 }
422 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
423
424 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
425 {
426         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
427                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
428         else
429                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
430
431         return fault->nested_page_fault;
432 }
433
434 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
435 {
436         atomic_inc(&vcpu->arch.nmi_queued);
437         kvm_make_request(KVM_REQ_NMI, vcpu);
438 }
439 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
440
441 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
442 {
443         kvm_multiple_exception(vcpu, nr, true, error_code, false);
444 }
445 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
446
447 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
448 {
449         kvm_multiple_exception(vcpu, nr, true, error_code, true);
450 }
451 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
452
453 /*
454  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
455  * a #GP and return false.
456  */
457 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
458 {
459         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
460                 return true;
461         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
462         return false;
463 }
464 EXPORT_SYMBOL_GPL(kvm_require_cpl);
465
466 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
467 {
468         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
469                 return true;
470
471         kvm_queue_exception(vcpu, UD_VECTOR);
472         return false;
473 }
474 EXPORT_SYMBOL_GPL(kvm_require_dr);
475
476 /*
477  * This function will be used to read from the physical memory of the currently
478  * running guest. The difference to kvm_read_guest_page is that this function
479  * can read from guest physical or from the guest's guest physical memory.
480  */
481 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
482                             gfn_t ngfn, void *data, int offset, int len,
483                             u32 access)
484 {
485         struct x86_exception exception;
486         gfn_t real_gfn;
487         gpa_t ngpa;
488
489         ngpa     = gfn_to_gpa(ngfn);
490         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
491         if (real_gfn == UNMAPPED_GVA)
492                 return -EFAULT;
493
494         real_gfn = gpa_to_gfn(real_gfn);
495
496         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
497 }
498 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
499
500 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
501                                void *data, int offset, int len, u32 access)
502 {
503         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
504                                        data, offset, len, access);
505 }
506
507 /*
508  * Load the pae pdptrs.  Return true is they are all valid.
509  */
510 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
511 {
512         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
513         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
514         int i;
515         int ret;
516         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
517
518         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
519                                       offset * sizeof(u64), sizeof(pdpte),
520                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
521         if (ret < 0) {
522                 ret = 0;
523                 goto out;
524         }
525         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
526                 if (is_present_gpte(pdpte[i]) &&
527                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
528                         ret = 0;
529                         goto out;
530                 }
531         }
532         ret = 1;
533
534         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
535         __set_bit(VCPU_EXREG_PDPTR,
536                   (unsigned long *)&vcpu->arch.regs_avail);
537         __set_bit(VCPU_EXREG_PDPTR,
538                   (unsigned long *)&vcpu->arch.regs_dirty);
539 out:
540
541         return ret;
542 }
543 EXPORT_SYMBOL_GPL(load_pdptrs);
544
545 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
546 {
547         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
548         bool changed = true;
549         int offset;
550         gfn_t gfn;
551         int r;
552
553         if (is_long_mode(vcpu) || !is_pae(vcpu))
554                 return false;
555
556         if (!test_bit(VCPU_EXREG_PDPTR,
557                       (unsigned long *)&vcpu->arch.regs_avail))
558                 return true;
559
560         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
561         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
562         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
563                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
564         if (r < 0)
565                 goto out;
566         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
567 out:
568
569         return changed;
570 }
571
572 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
573 {
574         unsigned long old_cr0 = kvm_read_cr0(vcpu);
575         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
576                                     X86_CR0_CD | X86_CR0_NW;
577
578         cr0 |= X86_CR0_ET;
579
580 #ifdef CONFIG_X86_64
581         if (cr0 & 0xffffffff00000000UL)
582                 return 1;
583 #endif
584
585         cr0 &= ~CR0_RESERVED_BITS;
586
587         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
588                 return 1;
589
590         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
591                 return 1;
592
593         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
594 #ifdef CONFIG_X86_64
595                 if ((vcpu->arch.efer & EFER_LME)) {
596                         int cs_db, cs_l;
597
598                         if (!is_pae(vcpu))
599                                 return 1;
600                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
601                         if (cs_l)
602                                 return 1;
603                 } else
604 #endif
605                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
606                                                  kvm_read_cr3(vcpu)))
607                         return 1;
608         }
609
610         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
611                 return 1;
612
613         kvm_x86_ops->set_cr0(vcpu, cr0);
614
615         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
616                 kvm_clear_async_pf_completion_queue(vcpu);
617                 kvm_async_pf_hash_reset(vcpu);
618         }
619
620         if ((cr0 ^ old_cr0) & update_bits)
621                 kvm_mmu_reset_context(vcpu);
622         return 0;
623 }
624 EXPORT_SYMBOL_GPL(kvm_set_cr0);
625
626 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
627 {
628         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
629 }
630 EXPORT_SYMBOL_GPL(kvm_lmsw);
631
632 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
633 {
634         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
635                         !vcpu->guest_xcr0_loaded) {
636                 /* kvm_set_xcr() also depends on this */
637                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
638                 vcpu->guest_xcr0_loaded = 1;
639         }
640 }
641
642 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
643 {
644         if (vcpu->guest_xcr0_loaded) {
645                 if (vcpu->arch.xcr0 != host_xcr0)
646                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
647                 vcpu->guest_xcr0_loaded = 0;
648         }
649 }
650
651 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
652 {
653         u64 xcr0 = xcr;
654         u64 old_xcr0 = vcpu->arch.xcr0;
655         u64 valid_bits;
656
657         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
658         if (index != XCR_XFEATURE_ENABLED_MASK)
659                 return 1;
660         if (!(xcr0 & XSTATE_FP))
661                 return 1;
662         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
663                 return 1;
664
665         /*
666          * Do not allow the guest to set bits that we do not support
667          * saving.  However, xcr0 bit 0 is always set, even if the
668          * emulated CPU does not support XSAVE (see fx_init).
669          */
670         valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
671         if (xcr0 & ~valid_bits)
672                 return 1;
673
674         if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
675                 return 1;
676
677         if (xcr0 & XSTATE_AVX512) {
678                 if (!(xcr0 & XSTATE_YMM))
679                         return 1;
680                 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
681                         return 1;
682         }
683         kvm_put_guest_xcr0(vcpu);
684         vcpu->arch.xcr0 = xcr0;
685
686         if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
687                 kvm_update_cpuid(vcpu);
688         return 0;
689 }
690
691 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
692 {
693         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
694             __kvm_set_xcr(vcpu, index, xcr)) {
695                 kvm_inject_gp(vcpu, 0);
696                 return 1;
697         }
698         return 0;
699 }
700 EXPORT_SYMBOL_GPL(kvm_set_xcr);
701
702 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
703 {
704         unsigned long old_cr4 = kvm_read_cr4(vcpu);
705         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
706                                    X86_CR4_PAE | X86_CR4_SMEP;
707         if (cr4 & CR4_RESERVED_BITS)
708                 return 1;
709
710         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
711                 return 1;
712
713         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
714                 return 1;
715
716         if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
717                 return 1;
718
719         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
720                 return 1;
721
722         if (is_long_mode(vcpu)) {
723                 if (!(cr4 & X86_CR4_PAE))
724                         return 1;
725         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
726                    && ((cr4 ^ old_cr4) & pdptr_bits)
727                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
728                                    kvm_read_cr3(vcpu)))
729                 return 1;
730
731         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
732                 if (!guest_cpuid_has_pcid(vcpu))
733                         return 1;
734
735                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
736                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
737                         return 1;
738         }
739
740         if (kvm_x86_ops->set_cr4(vcpu, cr4))
741                 return 1;
742
743         if (((cr4 ^ old_cr4) & pdptr_bits) ||
744             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
745                 kvm_mmu_reset_context(vcpu);
746
747         if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
748                 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
749
750         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
751                 kvm_update_cpuid(vcpu);
752
753         return 0;
754 }
755 EXPORT_SYMBOL_GPL(kvm_set_cr4);
756
757 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
758 {
759 #ifdef CONFIG_X86_64
760         cr3 &= ~CR3_PCID_INVD;
761 #endif
762
763         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
764                 kvm_mmu_sync_roots(vcpu);
765                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
766                 return 0;
767         }
768
769         if (is_long_mode(vcpu)) {
770                 if (cr3 & CR3_L_MODE_RESERVED_BITS)
771                         return 1;
772         } else if (is_pae(vcpu) && is_paging(vcpu) &&
773                    !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
774                 return 1;
775
776         vcpu->arch.cr3 = cr3;
777         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
778         kvm_mmu_new_cr3(vcpu);
779         return 0;
780 }
781 EXPORT_SYMBOL_GPL(kvm_set_cr3);
782
783 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
784 {
785         if (cr8 & CR8_RESERVED_BITS)
786                 return 1;
787         if (irqchip_in_kernel(vcpu->kvm))
788                 kvm_lapic_set_tpr(vcpu, cr8);
789         else
790                 vcpu->arch.cr8 = cr8;
791         return 0;
792 }
793 EXPORT_SYMBOL_GPL(kvm_set_cr8);
794
795 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
796 {
797         if (irqchip_in_kernel(vcpu->kvm))
798                 return kvm_lapic_get_cr8(vcpu);
799         else
800                 return vcpu->arch.cr8;
801 }
802 EXPORT_SYMBOL_GPL(kvm_get_cr8);
803
804 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
805 {
806         int i;
807
808         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
809                 for (i = 0; i < KVM_NR_DB_REGS; i++)
810                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
811                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
812         }
813 }
814
815 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
816 {
817         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
818                 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
819 }
820
821 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
822 {
823         unsigned long dr7;
824
825         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
826                 dr7 = vcpu->arch.guest_debug_dr7;
827         else
828                 dr7 = vcpu->arch.dr7;
829         kvm_x86_ops->set_dr7(vcpu, dr7);
830         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
831         if (dr7 & DR7_BP_EN_MASK)
832                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
833 }
834
835 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
836 {
837         u64 fixed = DR6_FIXED_1;
838
839         if (!guest_cpuid_has_rtm(vcpu))
840                 fixed |= DR6_RTM;
841         return fixed;
842 }
843
844 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
845 {
846         switch (dr) {
847         case 0 ... 3:
848                 vcpu->arch.db[dr] = val;
849                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
850                         vcpu->arch.eff_db[dr] = val;
851                 break;
852         case 4:
853                 /* fall through */
854         case 6:
855                 if (val & 0xffffffff00000000ULL)
856                         return -1; /* #GP */
857                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
858                 kvm_update_dr6(vcpu);
859                 break;
860         case 5:
861                 /* fall through */
862         default: /* 7 */
863                 if (val & 0xffffffff00000000ULL)
864                         return -1; /* #GP */
865                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
866                 kvm_update_dr7(vcpu);
867                 break;
868         }
869
870         return 0;
871 }
872
873 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
874 {
875         if (__kvm_set_dr(vcpu, dr, val)) {
876                 kvm_inject_gp(vcpu, 0);
877                 return 1;
878         }
879         return 0;
880 }
881 EXPORT_SYMBOL_GPL(kvm_set_dr);
882
883 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
884 {
885         switch (dr) {
886         case 0 ... 3:
887                 *val = vcpu->arch.db[dr];
888                 break;
889         case 4:
890                 /* fall through */
891         case 6:
892                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
893                         *val = vcpu->arch.dr6;
894                 else
895                         *val = kvm_x86_ops->get_dr6(vcpu);
896                 break;
897         case 5:
898                 /* fall through */
899         default: /* 7 */
900                 *val = vcpu->arch.dr7;
901                 break;
902         }
903         return 0;
904 }
905 EXPORT_SYMBOL_GPL(kvm_get_dr);
906
907 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
908 {
909         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
910         u64 data;
911         int err;
912
913         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
914         if (err)
915                 return err;
916         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
917         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
918         return err;
919 }
920 EXPORT_SYMBOL_GPL(kvm_rdpmc);
921
922 /*
923  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
924  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
925  *
926  * This list is modified at module load time to reflect the
927  * capabilities of the host cpu. This capabilities test skips MSRs that are
928  * kvm-specific. Those are put in the beginning of the list.
929  */
930
931 #define KVM_SAVE_MSRS_BEGIN     12
932 static u32 msrs_to_save[] = {
933         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
934         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
935         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
936         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
937         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
938         MSR_KVM_PV_EOI_EN,
939         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
940         MSR_STAR,
941 #ifdef CONFIG_X86_64
942         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
943 #endif
944         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
945         MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
946 };
947
948 static unsigned num_msrs_to_save;
949
950 static const u32 emulated_msrs[] = {
951         MSR_IA32_TSC_ADJUST,
952         MSR_IA32_TSCDEADLINE,
953         MSR_IA32_MISC_ENABLE,
954         MSR_IA32_MCG_STATUS,
955         MSR_IA32_MCG_CTL,
956 };
957
958 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
959 {
960         if (efer & efer_reserved_bits)
961                 return false;
962
963         if (efer & EFER_FFXSR) {
964                 struct kvm_cpuid_entry2 *feat;
965
966                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
967                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
968                         return false;
969         }
970
971         if (efer & EFER_SVME) {
972                 struct kvm_cpuid_entry2 *feat;
973
974                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
975                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
976                         return false;
977         }
978
979         return true;
980 }
981 EXPORT_SYMBOL_GPL(kvm_valid_efer);
982
983 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
984 {
985         u64 old_efer = vcpu->arch.efer;
986
987         if (!kvm_valid_efer(vcpu, efer))
988                 return 1;
989
990         if (is_paging(vcpu)
991             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
992                 return 1;
993
994         efer &= ~EFER_LMA;
995         efer |= vcpu->arch.efer & EFER_LMA;
996
997         kvm_x86_ops->set_efer(vcpu, efer);
998
999         /* Update reserved bits */
1000         if ((efer ^ old_efer) & EFER_NX)
1001                 kvm_mmu_reset_context(vcpu);
1002
1003         return 0;
1004 }
1005
1006 void kvm_enable_efer_bits(u64 mask)
1007 {
1008        efer_reserved_bits &= ~mask;
1009 }
1010 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1011
1012 /*
1013  * Writes msr value into into the appropriate "register".
1014  * Returns 0 on success, non-0 otherwise.
1015  * Assumes vcpu_load() was already called.
1016  */
1017 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1018 {
1019         switch (msr->index) {
1020         case MSR_FS_BASE:
1021         case MSR_GS_BASE:
1022         case MSR_KERNEL_GS_BASE:
1023         case MSR_CSTAR:
1024         case MSR_LSTAR:
1025                 if (is_noncanonical_address(msr->data))
1026                         return 1;
1027                 break;
1028         case MSR_IA32_SYSENTER_EIP:
1029         case MSR_IA32_SYSENTER_ESP:
1030                 /*
1031                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1032                  * non-canonical address is written on Intel but not on
1033                  * AMD (which ignores the top 32-bits, because it does
1034                  * not implement 64-bit SYSENTER).
1035                  *
1036                  * 64-bit code should hence be able to write a non-canonical
1037                  * value on AMD.  Making the address canonical ensures that
1038                  * vmentry does not fail on Intel after writing a non-canonical
1039                  * value, and that something deterministic happens if the guest
1040                  * invokes 64-bit SYSENTER.
1041                  */
1042                 msr->data = get_canonical(msr->data);
1043         }
1044         return kvm_x86_ops->set_msr(vcpu, msr);
1045 }
1046 EXPORT_SYMBOL_GPL(kvm_set_msr);
1047
1048 /*
1049  * Adapt set_msr() to msr_io()'s calling convention
1050  */
1051 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1052 {
1053         struct msr_data msr;
1054
1055         msr.data = *data;
1056         msr.index = index;
1057         msr.host_initiated = true;
1058         return kvm_set_msr(vcpu, &msr);
1059 }
1060
1061 #ifdef CONFIG_X86_64
1062 struct pvclock_gtod_data {
1063         seqcount_t      seq;
1064
1065         struct { /* extract of a clocksource struct */
1066                 int vclock_mode;
1067                 cycle_t cycle_last;
1068                 cycle_t mask;
1069                 u32     mult;
1070                 u32     shift;
1071         } clock;
1072
1073         u64             boot_ns;
1074         u64             nsec_base;
1075 };
1076
1077 static struct pvclock_gtod_data pvclock_gtod_data;
1078
1079 static void update_pvclock_gtod(struct timekeeper *tk)
1080 {
1081         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1082         u64 boot_ns;
1083
1084         boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1085
1086         write_seqcount_begin(&vdata->seq);
1087
1088         /* copy pvclock gtod data */
1089         vdata->clock.vclock_mode        = tk->tkr_mono.clock->archdata.vclock_mode;
1090         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1091         vdata->clock.mask               = tk->tkr_mono.mask;
1092         vdata->clock.mult               = tk->tkr_mono.mult;
1093         vdata->clock.shift              = tk->tkr_mono.shift;
1094
1095         vdata->boot_ns                  = boot_ns;
1096         vdata->nsec_base                = tk->tkr_mono.xtime_nsec;
1097
1098         write_seqcount_end(&vdata->seq);
1099 }
1100 #endif
1101
1102 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1103 {
1104         /*
1105          * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1106          * vcpu_enter_guest.  This function is only called from
1107          * the physical CPU that is running vcpu.
1108          */
1109         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1110 }
1111
1112 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1113 {
1114         int version;
1115         int r;
1116         struct pvclock_wall_clock wc;
1117         struct timespec boot;
1118
1119         if (!wall_clock)
1120                 return;
1121
1122         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1123         if (r)
1124                 return;
1125
1126         if (version & 1)
1127                 ++version;  /* first time write, random junk */
1128
1129         ++version;
1130
1131         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1132
1133         /*
1134          * The guest calculates current wall clock time by adding
1135          * system time (updated by kvm_guest_time_update below) to the
1136          * wall clock specified here.  guest system time equals host
1137          * system time for us, thus we must fill in host boot time here.
1138          */
1139         getboottime(&boot);
1140
1141         if (kvm->arch.kvmclock_offset) {
1142                 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1143                 boot = timespec_sub(boot, ts);
1144         }
1145         wc.sec = boot.tv_sec;
1146         wc.nsec = boot.tv_nsec;
1147         wc.version = version;
1148
1149         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1150
1151         version++;
1152         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1153 }
1154
1155 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1156 {
1157         uint32_t quotient, remainder;
1158
1159         /* Don't try to replace with do_div(), this one calculates
1160          * "(dividend << 32) / divisor" */
1161         __asm__ ( "divl %4"
1162                   : "=a" (quotient), "=d" (remainder)
1163                   : "0" (0), "1" (dividend), "r" (divisor) );
1164         return quotient;
1165 }
1166
1167 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1168                                s8 *pshift, u32 *pmultiplier)
1169 {
1170         uint64_t scaled64;
1171         int32_t  shift = 0;
1172         uint64_t tps64;
1173         uint32_t tps32;
1174
1175         tps64 = base_khz * 1000LL;
1176         scaled64 = scaled_khz * 1000LL;
1177         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1178                 tps64 >>= 1;
1179                 shift--;
1180         }
1181
1182         tps32 = (uint32_t)tps64;
1183         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1184                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1185                         scaled64 >>= 1;
1186                 else
1187                         tps32 <<= 1;
1188                 shift++;
1189         }
1190
1191         *pshift = shift;
1192         *pmultiplier = div_frac(scaled64, tps32);
1193
1194         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1195                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
1196 }
1197
1198 static inline u64 get_kernel_ns(void)
1199 {
1200         return ktime_get_boot_ns();
1201 }
1202
1203 #ifdef CONFIG_X86_64
1204 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1205 #endif
1206
1207 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1208 static unsigned long max_tsc_khz;
1209
1210 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1211 {
1212         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1213                                    vcpu->arch.virtual_tsc_shift);
1214 }
1215
1216 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1217 {
1218         u64 v = (u64)khz * (1000000 + ppm);
1219         do_div(v, 1000000);
1220         return v;
1221 }
1222
1223 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1224 {
1225         u32 thresh_lo, thresh_hi;
1226         int use_scaling = 0;
1227
1228         /* tsc_khz can be zero if TSC calibration fails */
1229         if (this_tsc_khz == 0)
1230                 return;
1231
1232         /* Compute a scale to convert nanoseconds in TSC cycles */
1233         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1234                            &vcpu->arch.virtual_tsc_shift,
1235                            &vcpu->arch.virtual_tsc_mult);
1236         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1237
1238         /*
1239          * Compute the variation in TSC rate which is acceptable
1240          * within the range of tolerance and decide if the
1241          * rate being applied is within that bounds of the hardware
1242          * rate.  If so, no scaling or compensation need be done.
1243          */
1244         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1245         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1246         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1247                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1248                 use_scaling = 1;
1249         }
1250         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1251 }
1252
1253 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1254 {
1255         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1256                                       vcpu->arch.virtual_tsc_mult,
1257                                       vcpu->arch.virtual_tsc_shift);
1258         tsc += vcpu->arch.this_tsc_write;
1259         return tsc;
1260 }
1261
1262 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1263 {
1264 #ifdef CONFIG_X86_64
1265         bool vcpus_matched;
1266         struct kvm_arch *ka = &vcpu->kvm->arch;
1267         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1268
1269         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1270                          atomic_read(&vcpu->kvm->online_vcpus));
1271
1272         /*
1273          * Once the masterclock is enabled, always perform request in
1274          * order to update it.
1275          *
1276          * In order to enable masterclock, the host clocksource must be TSC
1277          * and the vcpus need to have matched TSCs.  When that happens,
1278          * perform request to enable masterclock.
1279          */
1280         if (ka->use_master_clock ||
1281             (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1282                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1283
1284         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1285                             atomic_read(&vcpu->kvm->online_vcpus),
1286                             ka->use_master_clock, gtod->clock.vclock_mode);
1287 #endif
1288 }
1289
1290 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1291 {
1292         u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1293         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1294 }
1295
1296 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1297 {
1298         struct kvm *kvm = vcpu->kvm;
1299         u64 offset, ns, elapsed;
1300         unsigned long flags;
1301         s64 usdiff;
1302         bool matched;
1303         bool already_matched;
1304         u64 data = msr->data;
1305
1306         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1307         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1308         ns = get_kernel_ns();
1309         elapsed = ns - kvm->arch.last_tsc_nsec;
1310
1311         if (vcpu->arch.virtual_tsc_khz) {
1312                 int faulted = 0;
1313
1314                 /* n.b - signed multiplication and division required */
1315                 usdiff = data - kvm->arch.last_tsc_write;
1316 #ifdef CONFIG_X86_64
1317                 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1318 #else
1319                 /* do_div() only does unsigned */
1320                 asm("1: idivl %[divisor]\n"
1321                     "2: xor %%edx, %%edx\n"
1322                     "   movl $0, %[faulted]\n"
1323                     "3:\n"
1324                     ".section .fixup,\"ax\"\n"
1325                     "4: movl $1, %[faulted]\n"
1326                     "   jmp  3b\n"
1327                     ".previous\n"
1328
1329                 _ASM_EXTABLE(1b, 4b)
1330
1331                 : "=A"(usdiff), [faulted] "=r" (faulted)
1332                 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1333
1334 #endif
1335                 do_div(elapsed, 1000);
1336                 usdiff -= elapsed;
1337                 if (usdiff < 0)
1338                         usdiff = -usdiff;
1339
1340                 /* idivl overflow => difference is larger than USEC_PER_SEC */
1341                 if (faulted)
1342                         usdiff = USEC_PER_SEC;
1343         } else
1344                 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1345
1346         /*
1347          * Special case: TSC write with a small delta (1 second) of virtual
1348          * cycle time against real time is interpreted as an attempt to
1349          * synchronize the CPU.
1350          *
1351          * For a reliable TSC, we can match TSC offsets, and for an unstable
1352          * TSC, we add elapsed time in this computation.  We could let the
1353          * compensation code attempt to catch up if we fall behind, but
1354          * it's better to try to match offsets from the beginning.
1355          */
1356         if (usdiff < USEC_PER_SEC &&
1357             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1358                 if (!check_tsc_unstable()) {
1359                         offset = kvm->arch.cur_tsc_offset;
1360                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1361                 } else {
1362                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1363                         data += delta;
1364                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1365                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1366                 }
1367                 matched = true;
1368                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1369         } else {
1370                 /*
1371                  * We split periods of matched TSC writes into generations.
1372                  * For each generation, we track the original measured
1373                  * nanosecond time, offset, and write, so if TSCs are in
1374                  * sync, we can match exact offset, and if not, we can match
1375                  * exact software computation in compute_guest_tsc()
1376                  *
1377                  * These values are tracked in kvm->arch.cur_xxx variables.
1378                  */
1379                 kvm->arch.cur_tsc_generation++;
1380                 kvm->arch.cur_tsc_nsec = ns;
1381                 kvm->arch.cur_tsc_write = data;
1382                 kvm->arch.cur_tsc_offset = offset;
1383                 matched = false;
1384                 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1385                          kvm->arch.cur_tsc_generation, data);
1386         }
1387
1388         /*
1389          * We also track th most recent recorded KHZ, write and time to
1390          * allow the matching interval to be extended at each write.
1391          */
1392         kvm->arch.last_tsc_nsec = ns;
1393         kvm->arch.last_tsc_write = data;
1394         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1395
1396         vcpu->arch.last_guest_tsc = data;
1397
1398         /* Keep track of which generation this VCPU has synchronized to */
1399         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1400         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1401         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1402
1403         if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1404                 update_ia32_tsc_adjust_msr(vcpu, offset);
1405         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1406         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1407
1408         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1409         if (!matched) {
1410                 kvm->arch.nr_vcpus_matched_tsc = 0;
1411         } else if (!already_matched) {
1412                 kvm->arch.nr_vcpus_matched_tsc++;
1413         }
1414
1415         kvm_track_tsc_matching(vcpu);
1416         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1417 }
1418
1419 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1420
1421 #ifdef CONFIG_X86_64
1422
1423 static cycle_t read_tsc(void)
1424 {
1425         cycle_t ret;
1426         u64 last;
1427
1428         /*
1429          * Empirically, a fence (of type that depends on the CPU)
1430          * before rdtsc is enough to ensure that rdtsc is ordered
1431          * with respect to loads.  The various CPU manuals are unclear
1432          * as to whether rdtsc can be reordered with later loads,
1433          * but no one has ever seen it happen.
1434          */
1435         rdtsc_barrier();
1436         ret = (cycle_t)vget_cycles();
1437
1438         last = pvclock_gtod_data.clock.cycle_last;
1439
1440         if (likely(ret >= last))
1441                 return ret;
1442
1443         /*
1444          * GCC likes to generate cmov here, but this branch is extremely
1445          * predictable (it's just a funciton of time and the likely is
1446          * very likely) and there's a data dependence, so force GCC
1447          * to generate a branch instead.  I don't barrier() because
1448          * we don't actually need a barrier, and if this function
1449          * ever gets inlined it will generate worse code.
1450          */
1451         asm volatile ("");
1452         return last;
1453 }
1454
1455 static inline u64 vgettsc(cycle_t *cycle_now)
1456 {
1457         long v;
1458         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1459
1460         *cycle_now = read_tsc();
1461
1462         v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1463         return v * gtod->clock.mult;
1464 }
1465
1466 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1467 {
1468         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1469         unsigned long seq;
1470         int mode;
1471         u64 ns;
1472
1473         do {
1474                 seq = read_seqcount_begin(&gtod->seq);
1475                 mode = gtod->clock.vclock_mode;
1476                 ns = gtod->nsec_base;
1477                 ns += vgettsc(cycle_now);
1478                 ns >>= gtod->clock.shift;
1479                 ns += gtod->boot_ns;
1480         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1481         *t = ns;
1482
1483         return mode;
1484 }
1485
1486 /* returns true if host is using tsc clocksource */
1487 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1488 {
1489         /* checked again under seqlock below */
1490         if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1491                 return false;
1492
1493         return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1494 }
1495 #endif
1496
1497 /*
1498  *
1499  * Assuming a stable TSC across physical CPUS, and a stable TSC
1500  * across virtual CPUs, the following condition is possible.
1501  * Each numbered line represents an event visible to both
1502  * CPUs at the next numbered event.
1503  *
1504  * "timespecX" represents host monotonic time. "tscX" represents
1505  * RDTSC value.
1506  *
1507  *              VCPU0 on CPU0           |       VCPU1 on CPU1
1508  *
1509  * 1.  read timespec0,tsc0
1510  * 2.                                   | timespec1 = timespec0 + N
1511  *                                      | tsc1 = tsc0 + M
1512  * 3. transition to guest               | transition to guest
1513  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1514  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
1515  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1516  *
1517  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1518  *
1519  *      - ret0 < ret1
1520  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1521  *              ...
1522  *      - 0 < N - M => M < N
1523  *
1524  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1525  * always the case (the difference between two distinct xtime instances
1526  * might be smaller then the difference between corresponding TSC reads,
1527  * when updating guest vcpus pvclock areas).
1528  *
1529  * To avoid that problem, do not allow visibility of distinct
1530  * system_timestamp/tsc_timestamp values simultaneously: use a master
1531  * copy of host monotonic time values. Update that master copy
1532  * in lockstep.
1533  *
1534  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1535  *
1536  */
1537
1538 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1539 {
1540 #ifdef CONFIG_X86_64
1541         struct kvm_arch *ka = &kvm->arch;
1542         int vclock_mode;
1543         bool host_tsc_clocksource, vcpus_matched;
1544
1545         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1546                         atomic_read(&kvm->online_vcpus));
1547
1548         /*
1549          * If the host uses TSC clock, then passthrough TSC as stable
1550          * to the guest.
1551          */
1552         host_tsc_clocksource = kvm_get_time_and_clockread(
1553                                         &ka->master_kernel_ns,
1554                                         &ka->master_cycle_now);
1555
1556         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1557                                 && !backwards_tsc_observed
1558                                 && !ka->boot_vcpu_runs_old_kvmclock;
1559
1560         if (ka->use_master_clock)
1561                 atomic_set(&kvm_guest_has_master_clock, 1);
1562
1563         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1564         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1565                                         vcpus_matched);
1566 #endif
1567 }
1568
1569 static void kvm_gen_update_masterclock(struct kvm *kvm)
1570 {
1571 #ifdef CONFIG_X86_64
1572         int i;
1573         struct kvm_vcpu *vcpu;
1574         struct kvm_arch *ka = &kvm->arch;
1575
1576         spin_lock(&ka->pvclock_gtod_sync_lock);
1577         kvm_make_mclock_inprogress_request(kvm);
1578         /* no guest entries from this point */
1579         pvclock_update_vm_gtod_copy(kvm);
1580
1581         kvm_for_each_vcpu(i, vcpu, kvm)
1582                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1583
1584         /* guest entries allowed */
1585         kvm_for_each_vcpu(i, vcpu, kvm)
1586                 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1587
1588         spin_unlock(&ka->pvclock_gtod_sync_lock);
1589 #endif
1590 }
1591
1592 static int kvm_guest_time_update(struct kvm_vcpu *v)
1593 {
1594         unsigned long flags, this_tsc_khz;
1595         struct kvm_vcpu_arch *vcpu = &v->arch;
1596         struct kvm_arch *ka = &v->kvm->arch;
1597         s64 kernel_ns;
1598         u64 tsc_timestamp, host_tsc;
1599         struct pvclock_vcpu_time_info guest_hv_clock;
1600         u8 pvclock_flags;
1601         bool use_master_clock;
1602
1603         kernel_ns = 0;
1604         host_tsc = 0;
1605
1606         /*
1607          * If the host uses TSC clock, then passthrough TSC as stable
1608          * to the guest.
1609          */
1610         spin_lock(&ka->pvclock_gtod_sync_lock);
1611         use_master_clock = ka->use_master_clock;
1612         if (use_master_clock) {
1613                 host_tsc = ka->master_cycle_now;
1614                 kernel_ns = ka->master_kernel_ns;
1615         }
1616         spin_unlock(&ka->pvclock_gtod_sync_lock);
1617
1618         /* Keep irq disabled to prevent changes to the clock */
1619         local_irq_save(flags);
1620         this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1621         if (unlikely(this_tsc_khz == 0)) {
1622                 local_irq_restore(flags);
1623                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1624                 return 1;
1625         }
1626         if (!use_master_clock) {
1627                 host_tsc = native_read_tsc();
1628                 kernel_ns = get_kernel_ns();
1629         }
1630
1631         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1632
1633         /*
1634          * We may have to catch up the TSC to match elapsed wall clock
1635          * time for two reasons, even if kvmclock is used.
1636          *   1) CPU could have been running below the maximum TSC rate
1637          *   2) Broken TSC compensation resets the base at each VCPU
1638          *      entry to avoid unknown leaps of TSC even when running
1639          *      again on the same CPU.  This may cause apparent elapsed
1640          *      time to disappear, and the guest to stand still or run
1641          *      very slowly.
1642          */
1643         if (vcpu->tsc_catchup) {
1644                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1645                 if (tsc > tsc_timestamp) {
1646                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1647                         tsc_timestamp = tsc;
1648                 }
1649         }
1650
1651         local_irq_restore(flags);
1652
1653         if (!vcpu->pv_time_enabled)
1654                 return 0;
1655
1656         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1657                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1658                                    &vcpu->hv_clock.tsc_shift,
1659                                    &vcpu->hv_clock.tsc_to_system_mul);
1660                 vcpu->hw_tsc_khz = this_tsc_khz;
1661         }
1662
1663         /* With all the info we got, fill in the values */
1664         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1665         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1666         vcpu->last_guest_tsc = tsc_timestamp;
1667
1668         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1669                 &guest_hv_clock, sizeof(guest_hv_clock))))
1670                 return 0;
1671
1672         /*
1673          * The interface expects us to write an even number signaling that the
1674          * update is finished. Since the guest won't see the intermediate
1675          * state, we just increase by 2 at the end.
1676          */
1677         vcpu->hv_clock.version = guest_hv_clock.version + 2;
1678
1679         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1680         pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1681
1682         if (vcpu->pvclock_set_guest_stopped_request) {
1683                 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1684                 vcpu->pvclock_set_guest_stopped_request = false;
1685         }
1686
1687         /* If the host uses TSC clocksource, then it is stable */
1688         if (use_master_clock)
1689                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1690
1691         vcpu->hv_clock.flags = pvclock_flags;
1692
1693         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1694
1695         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1696                                 &vcpu->hv_clock,
1697                                 sizeof(vcpu->hv_clock));
1698         return 0;
1699 }
1700
1701 /*
1702  * kvmclock updates which are isolated to a given vcpu, such as
1703  * vcpu->cpu migration, should not allow system_timestamp from
1704  * the rest of the vcpus to remain static. Otherwise ntp frequency
1705  * correction applies to one vcpu's system_timestamp but not
1706  * the others.
1707  *
1708  * So in those cases, request a kvmclock update for all vcpus.
1709  * We need to rate-limit these requests though, as they can
1710  * considerably slow guests that have a large number of vcpus.
1711  * The time for a remote vcpu to update its kvmclock is bound
1712  * by the delay we use to rate-limit the updates.
1713  */
1714
1715 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1716
1717 static void kvmclock_update_fn(struct work_struct *work)
1718 {
1719         int i;
1720         struct delayed_work *dwork = to_delayed_work(work);
1721         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1722                                            kvmclock_update_work);
1723         struct kvm *kvm = container_of(ka, struct kvm, arch);
1724         struct kvm_vcpu *vcpu;
1725
1726         kvm_for_each_vcpu(i, vcpu, kvm) {
1727                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1728                 kvm_vcpu_kick(vcpu);
1729         }
1730 }
1731
1732 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1733 {
1734         struct kvm *kvm = v->kvm;
1735
1736         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1737         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1738                                         KVMCLOCK_UPDATE_DELAY);
1739 }
1740
1741 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1742
1743 static void kvmclock_sync_fn(struct work_struct *work)
1744 {
1745         struct delayed_work *dwork = to_delayed_work(work);
1746         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1747                                            kvmclock_sync_work);
1748         struct kvm *kvm = container_of(ka, struct kvm, arch);
1749
1750         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1751         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1752                                         KVMCLOCK_SYNC_PERIOD);
1753 }
1754
1755 static bool msr_mtrr_valid(unsigned msr)
1756 {
1757         switch (msr) {
1758         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1759         case MSR_MTRRfix64K_00000:
1760         case MSR_MTRRfix16K_80000:
1761         case MSR_MTRRfix16K_A0000:
1762         case MSR_MTRRfix4K_C0000:
1763         case MSR_MTRRfix4K_C8000:
1764         case MSR_MTRRfix4K_D0000:
1765         case MSR_MTRRfix4K_D8000:
1766         case MSR_MTRRfix4K_E0000:
1767         case MSR_MTRRfix4K_E8000:
1768         case MSR_MTRRfix4K_F0000:
1769         case MSR_MTRRfix4K_F8000:
1770         case MSR_MTRRdefType:
1771         case MSR_IA32_CR_PAT:
1772                 return true;
1773         case 0x2f8:
1774                 return true;
1775         }
1776         return false;
1777 }
1778
1779 static bool valid_pat_type(unsigned t)
1780 {
1781         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1782 }
1783
1784 static bool valid_mtrr_type(unsigned t)
1785 {
1786         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1787 }
1788
1789 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1790 {
1791         int i;
1792         u64 mask;
1793
1794         if (!msr_mtrr_valid(msr))
1795                 return false;
1796
1797         if (msr == MSR_IA32_CR_PAT) {
1798                 for (i = 0; i < 8; i++)
1799                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1800                                 return false;
1801                 return true;
1802         } else if (msr == MSR_MTRRdefType) {
1803                 if (data & ~0xcff)
1804                         return false;
1805                 return valid_mtrr_type(data & 0xff);
1806         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1807                 for (i = 0; i < 8 ; i++)
1808                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1809                                 return false;
1810                 return true;
1811         }
1812
1813         /* variable MTRRs */
1814         WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1815
1816         mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
1817         if ((msr & 1) == 0) {
1818                 /* MTRR base */
1819                 if (!valid_mtrr_type(data & 0xff))
1820                         return false;
1821                 mask |= 0xf00;
1822         } else
1823                 /* MTRR mask */
1824                 mask |= 0x7ff;
1825         if (data & mask) {
1826                 kvm_inject_gp(vcpu, 0);
1827                 return false;
1828         }
1829
1830         return true;
1831 }
1832 EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
1833
1834 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1835 {
1836         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1837
1838         if (!kvm_mtrr_valid(vcpu, msr, data))
1839                 return 1;
1840
1841         if (msr == MSR_MTRRdefType) {
1842                 vcpu->arch.mtrr_state.def_type = data;
1843                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1844         } else if (msr == MSR_MTRRfix64K_00000)
1845                 p[0] = data;
1846         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1847                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1848         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1849                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1850         else if (msr == MSR_IA32_CR_PAT)
1851                 vcpu->arch.pat = data;
1852         else {  /* Variable MTRRs */
1853                 int idx, is_mtrr_mask;
1854                 u64 *pt;
1855
1856                 idx = (msr - 0x200) / 2;
1857                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1858                 if (!is_mtrr_mask)
1859                         pt =
1860                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1861                 else
1862                         pt =
1863                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1864                 *pt = data;
1865         }
1866
1867         kvm_mmu_reset_context(vcpu);
1868         return 0;
1869 }
1870
1871 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1872 {
1873         u64 mcg_cap = vcpu->arch.mcg_cap;
1874         unsigned bank_num = mcg_cap & 0xff;
1875
1876         switch (msr) {
1877         case MSR_IA32_MCG_STATUS:
1878                 vcpu->arch.mcg_status = data;
1879                 break;
1880         case MSR_IA32_MCG_CTL:
1881                 if (!(mcg_cap & MCG_CTL_P))
1882                         return 1;
1883                 if (data != 0 && data != ~(u64)0)
1884                         return -1;
1885                 vcpu->arch.mcg_ctl = data;
1886                 break;
1887         default:
1888                 if (msr >= MSR_IA32_MC0_CTL &&
1889                     msr < MSR_IA32_MCx_CTL(bank_num)) {
1890                         u32 offset = msr - MSR_IA32_MC0_CTL;
1891                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1892                          * some Linux kernels though clear bit 10 in bank 4 to
1893                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1894                          * this to avoid an uncatched #GP in the guest
1895                          */
1896                         if ((offset & 0x3) == 0 &&
1897                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1898                                 return -1;
1899                         vcpu->arch.mce_banks[offset] = data;
1900                         break;
1901                 }
1902                 return 1;
1903         }
1904         return 0;
1905 }
1906
1907 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1908 {
1909         struct kvm *kvm = vcpu->kvm;
1910         int lm = is_long_mode(vcpu);
1911         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1912                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1913         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1914                 : kvm->arch.xen_hvm_config.blob_size_32;
1915         u32 page_num = data & ~PAGE_MASK;
1916         u64 page_addr = data & PAGE_MASK;
1917         u8 *page;
1918         int r;
1919
1920         r = -E2BIG;
1921         if (page_num >= blob_size)
1922                 goto out;
1923         r = -ENOMEM;
1924         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1925         if (IS_ERR(page)) {
1926                 r = PTR_ERR(page);
1927                 goto out;
1928         }
1929         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1930                 goto out_free;
1931         r = 0;
1932 out_free:
1933         kfree(page);
1934 out:
1935         return r;
1936 }
1937
1938 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1939 {
1940         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1941 }
1942
1943 static bool kvm_hv_msr_partition_wide(u32 msr)
1944 {
1945         bool r = false;
1946         switch (msr) {
1947         case HV_X64_MSR_GUEST_OS_ID:
1948         case HV_X64_MSR_HYPERCALL:
1949         case HV_X64_MSR_REFERENCE_TSC:
1950         case HV_X64_MSR_TIME_REF_COUNT:
1951                 r = true;
1952                 break;
1953         }
1954
1955         return r;
1956 }
1957
1958 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1959 {
1960         struct kvm *kvm = vcpu->kvm;
1961
1962         switch (msr) {
1963         case HV_X64_MSR_GUEST_OS_ID:
1964                 kvm->arch.hv_guest_os_id = data;
1965                 /* setting guest os id to zero disables hypercall page */
1966                 if (!kvm->arch.hv_guest_os_id)
1967                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1968                 break;
1969         case HV_X64_MSR_HYPERCALL: {
1970                 u64 gfn;
1971                 unsigned long addr;
1972                 u8 instructions[4];
1973
1974                 /* if guest os id is not set hypercall should remain disabled */
1975                 if (!kvm->arch.hv_guest_os_id)
1976                         break;
1977                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1978                         kvm->arch.hv_hypercall = data;
1979                         break;
1980                 }
1981                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1982                 addr = gfn_to_hva(kvm, gfn);
1983                 if (kvm_is_error_hva(addr))
1984                         return 1;
1985                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1986                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1987                 if (__copy_to_user((void __user *)addr, instructions, 4))
1988                         return 1;
1989                 kvm->arch.hv_hypercall = data;
1990                 mark_page_dirty(kvm, gfn);
1991                 break;
1992         }
1993         case HV_X64_MSR_REFERENCE_TSC: {
1994                 u64 gfn;
1995                 HV_REFERENCE_TSC_PAGE tsc_ref;
1996                 memset(&tsc_ref, 0, sizeof(tsc_ref));
1997                 kvm->arch.hv_tsc_page = data;
1998                 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1999                         break;
2000                 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
2001                 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
2002                         &tsc_ref, sizeof(tsc_ref)))
2003                         return 1;
2004                 mark_page_dirty(kvm, gfn);
2005                 break;
2006         }
2007         default:
2008                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2009                             "data 0x%llx\n", msr, data);
2010                 return 1;
2011         }
2012         return 0;
2013 }
2014
2015 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2016 {
2017         switch (msr) {
2018         case HV_X64_MSR_APIC_ASSIST_PAGE: {
2019                 u64 gfn;
2020                 unsigned long addr;
2021
2022                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2023                         vcpu->arch.hv_vapic = data;
2024                         if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2025                                 return 1;
2026                         break;
2027                 }
2028                 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2029                 addr = gfn_to_hva(vcpu->kvm, gfn);
2030                 if (kvm_is_error_hva(addr))
2031                         return 1;
2032                 if (__clear_user((void __user *)addr, PAGE_SIZE))
2033                         return 1;
2034                 vcpu->arch.hv_vapic = data;
2035                 mark_page_dirty(vcpu->kvm, gfn);
2036                 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2037                         return 1;
2038                 break;
2039         }
2040         case HV_X64_MSR_EOI:
2041                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2042         case HV_X64_MSR_ICR:
2043                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2044         case HV_X64_MSR_TPR:
2045                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2046         default:
2047                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2048                             "data 0x%llx\n", msr, data);
2049                 return 1;
2050         }
2051
2052         return 0;
2053 }
2054
2055 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2056 {
2057         gpa_t gpa = data & ~0x3f;
2058
2059         /* Bits 2:5 are reserved, Should be zero */
2060         if (data & 0x3c)
2061                 return 1;
2062
2063         vcpu->arch.apf.msr_val = data;
2064
2065         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2066                 kvm_clear_async_pf_completion_queue(vcpu);
2067                 kvm_async_pf_hash_reset(vcpu);
2068                 return 0;
2069         }
2070
2071         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2072                                         sizeof(u32)))
2073                 return 1;
2074
2075         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2076         kvm_async_pf_wakeup_all(vcpu);
2077         return 0;
2078 }
2079
2080 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2081 {
2082         vcpu->arch.pv_time_enabled = false;
2083 }
2084
2085 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2086 {
2087         u64 delta;
2088
2089         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2090                 return;
2091
2092         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2093         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2094         vcpu->arch.st.accum_steal = delta;
2095 }
2096
2097 static void record_steal_time(struct kvm_vcpu *vcpu)
2098 {
2099         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2100                 return;
2101
2102         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2103                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2104                 return;
2105
2106         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2107         vcpu->arch.st.steal.version += 2;
2108         vcpu->arch.st.accum_steal = 0;
2109
2110         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2111                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2112 }
2113
2114 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2115 {
2116         bool pr = false;
2117         u32 msr = msr_info->index;
2118         u64 data = msr_info->data;
2119
2120         switch (msr) {
2121         case MSR_AMD64_NB_CFG:
2122         case MSR_IA32_UCODE_REV:
2123         case MSR_IA32_UCODE_WRITE:
2124         case MSR_VM_HSAVE_PA:
2125         case MSR_AMD64_PATCH_LOADER:
2126         case MSR_AMD64_BU_CFG2:
2127                 break;
2128
2129         case MSR_EFER:
2130                 return set_efer(vcpu, data);
2131         case MSR_K7_HWCR:
2132                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2133                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2134                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2135                 data &= ~(u64)0x40000;  /* ignore Mc status write enable */
2136                 if (data != 0) {
2137                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2138                                     data);
2139                         return 1;
2140                 }
2141                 break;
2142         case MSR_FAM10H_MMIO_CONF_BASE:
2143                 if (data != 0) {
2144                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2145                                     "0x%llx\n", data);
2146                         return 1;
2147                 }
2148                 break;
2149         case MSR_IA32_DEBUGCTLMSR:
2150                 if (!data) {
2151                         /* We support the non-activated case already */
2152                         break;
2153                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2154                         /* Values other than LBR and BTF are vendor-specific,
2155                            thus reserved and should throw a #GP */
2156                         return 1;
2157                 }
2158                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2159                             __func__, data);
2160                 break;
2161         case 0x200 ... 0x2ff:
2162                 return set_msr_mtrr(vcpu, msr, data);
2163         case MSR_IA32_APICBASE:
2164                 return kvm_set_apic_base(vcpu, msr_info);
2165         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2166                 return kvm_x2apic_msr_write(vcpu, msr, data);
2167         case MSR_IA32_TSCDEADLINE:
2168                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2169                 break;
2170         case MSR_IA32_TSC_ADJUST:
2171                 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2172                         if (!msr_info->host_initiated) {
2173                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2174                                 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2175                         }
2176                         vcpu->arch.ia32_tsc_adjust_msr = data;
2177                 }
2178                 break;
2179         case MSR_IA32_MISC_ENABLE:
2180                 vcpu->arch.ia32_misc_enable_msr = data;
2181                 break;
2182         case MSR_KVM_WALL_CLOCK_NEW:
2183         case MSR_KVM_WALL_CLOCK:
2184                 vcpu->kvm->arch.wall_clock = data;
2185                 kvm_write_wall_clock(vcpu->kvm, data);
2186                 break;
2187         case MSR_KVM_SYSTEM_TIME_NEW:
2188         case MSR_KVM_SYSTEM_TIME: {
2189                 u64 gpa_offset;
2190                 struct kvm_arch *ka = &vcpu->kvm->arch;
2191
2192                 kvmclock_reset(vcpu);
2193
2194                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2195                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2196
2197                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2198                                 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2199                                         &vcpu->requests);
2200
2201                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2202                 }
2203
2204                 vcpu->arch.time = data;
2205                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2206
2207                 /* we verify if the enable bit is set... */
2208                 if (!(data & 1))
2209                         break;
2210
2211                 gpa_offset = data & ~(PAGE_MASK | 1);
2212
2213                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2214                      &vcpu->arch.pv_time, data & ~1ULL,
2215                      sizeof(struct pvclock_vcpu_time_info)))
2216                         vcpu->arch.pv_time_enabled = false;
2217                 else
2218                         vcpu->arch.pv_time_enabled = true;
2219
2220                 break;
2221         }
2222         case MSR_KVM_ASYNC_PF_EN:
2223                 if (kvm_pv_enable_async_pf(vcpu, data))
2224                         return 1;
2225                 break;
2226         case MSR_KVM_STEAL_TIME:
2227
2228                 if (unlikely(!sched_info_on()))
2229                         return 1;
2230
2231                 if (data & KVM_STEAL_RESERVED_MASK)
2232                         return 1;
2233
2234                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2235                                                 data & KVM_STEAL_VALID_BITS,
2236                                                 sizeof(struct kvm_steal_time)))
2237                         return 1;
2238
2239                 vcpu->arch.st.msr_val = data;
2240
2241                 if (!(data & KVM_MSR_ENABLED))
2242                         break;
2243
2244                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2245
2246                 preempt_disable();
2247                 accumulate_steal_time(vcpu);
2248                 preempt_enable();
2249
2250                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2251
2252                 break;
2253         case MSR_KVM_PV_EOI_EN:
2254                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2255                         return 1;
2256                 break;
2257
2258         case MSR_IA32_MCG_CTL:
2259         case MSR_IA32_MCG_STATUS:
2260         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2261                 return set_msr_mce(vcpu, msr, data);
2262
2263         /* Performance counters are not protected by a CPUID bit,
2264          * so we should check all of them in the generic path for the sake of
2265          * cross vendor migration.
2266          * Writing a zero into the event select MSRs disables them,
2267          * which we perfectly emulate ;-). Any other value should be at least
2268          * reported, some guests depend on them.
2269          */
2270         case MSR_K7_EVNTSEL0:
2271         case MSR_K7_EVNTSEL1:
2272         case MSR_K7_EVNTSEL2:
2273         case MSR_K7_EVNTSEL3:
2274                 if (data != 0)
2275                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2276                                     "0x%x data 0x%llx\n", msr, data);
2277                 break;
2278         /* at least RHEL 4 unconditionally writes to the perfctr registers,
2279          * so we ignore writes to make it happy.
2280          */
2281         case MSR_K7_PERFCTR0:
2282         case MSR_K7_PERFCTR1:
2283         case MSR_K7_PERFCTR2:
2284         case MSR_K7_PERFCTR3:
2285                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2286                             "0x%x data 0x%llx\n", msr, data);
2287                 break;
2288         case MSR_P6_PERFCTR0:
2289         case MSR_P6_PERFCTR1:
2290                 pr = true;
2291         case MSR_P6_EVNTSEL0:
2292         case MSR_P6_EVNTSEL1:
2293                 if (kvm_pmu_msr(vcpu, msr))
2294                         return kvm_pmu_set_msr(vcpu, msr_info);
2295
2296                 if (pr || data != 0)
2297                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2298                                     "0x%x data 0x%llx\n", msr, data);
2299                 break;
2300         case MSR_K7_CLK_CTL:
2301                 /*
2302                  * Ignore all writes to this no longer documented MSR.
2303                  * Writes are only relevant for old K7 processors,
2304                  * all pre-dating SVM, but a recommended workaround from
2305                  * AMD for these chips. It is possible to specify the
2306                  * affected processor models on the command line, hence
2307                  * the need to ignore the workaround.
2308                  */
2309                 break;
2310         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2311                 if (kvm_hv_msr_partition_wide(msr)) {
2312                         int r;
2313                         mutex_lock(&vcpu->kvm->lock);
2314                         r = set_msr_hyperv_pw(vcpu, msr, data);
2315                         mutex_unlock(&vcpu->kvm->lock);
2316                         return r;
2317                 } else
2318                         return set_msr_hyperv(vcpu, msr, data);
2319                 break;
2320         case MSR_IA32_BBL_CR_CTL3:
2321                 /* Drop writes to this legacy MSR -- see rdmsr
2322                  * counterpart for further detail.
2323                  */
2324                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2325                 break;
2326         case MSR_AMD64_OSVW_ID_LENGTH:
2327                 if (!guest_cpuid_has_osvw(vcpu))
2328                         return 1;
2329                 vcpu->arch.osvw.length = data;
2330                 break;
2331         case MSR_AMD64_OSVW_STATUS:
2332                 if (!guest_cpuid_has_osvw(vcpu))
2333                         return 1;
2334                 vcpu->arch.osvw.status = data;
2335                 break;
2336         default:
2337                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2338                         return xen_hvm_config(vcpu, data);
2339                 if (kvm_pmu_msr(vcpu, msr))
2340                         return kvm_pmu_set_msr(vcpu, msr_info);
2341                 if (!ignore_msrs) {
2342                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2343                                     msr, data);
2344                         return 1;
2345                 } else {
2346                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2347                                     msr, data);
2348                         break;
2349                 }
2350         }
2351         return 0;
2352 }
2353 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2354
2355
2356 /*
2357  * Reads an msr value (of 'msr_index') into 'pdata'.
2358  * Returns 0 on success, non-0 otherwise.
2359  * Assumes vcpu_load() was already called.
2360  */
2361 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2362 {
2363         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2364 }
2365 EXPORT_SYMBOL_GPL(kvm_get_msr);
2366
2367 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2368 {
2369         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2370
2371         if (!msr_mtrr_valid(msr))
2372                 return 1;
2373
2374         if (msr == MSR_MTRRdefType)
2375                 *pdata = vcpu->arch.mtrr_state.def_type +
2376                          (vcpu->arch.mtrr_state.enabled << 10);
2377         else if (msr == MSR_MTRRfix64K_00000)
2378                 *pdata = p[0];
2379         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2380                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2381         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2382                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2383         else if (msr == MSR_IA32_CR_PAT)
2384                 *pdata = vcpu->arch.pat;
2385         else {  /* Variable MTRRs */
2386                 int idx, is_mtrr_mask;
2387                 u64 *pt;
2388
2389                 idx = (msr - 0x200) / 2;
2390                 is_mtrr_mask = msr - 0x200 - 2 * idx;
2391                 if (!is_mtrr_mask)
2392                         pt =
2393                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2394                 else
2395                         pt =
2396                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2397                 *pdata = *pt;
2398         }
2399
2400         return 0;
2401 }
2402
2403 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2404 {
2405         u64 data;
2406         u64 mcg_cap = vcpu->arch.mcg_cap;
2407         unsigned bank_num = mcg_cap & 0xff;
2408
2409         switch (msr) {
2410         case MSR_IA32_P5_MC_ADDR:
2411         case MSR_IA32_P5_MC_TYPE:
2412                 data = 0;
2413                 break;
2414         case MSR_IA32_MCG_CAP:
2415                 data = vcpu->arch.mcg_cap;
2416                 break;
2417         case MSR_IA32_MCG_CTL:
2418                 if (!(mcg_cap & MCG_CTL_P))
2419                         return 1;
2420                 data = vcpu->arch.mcg_ctl;
2421                 break;
2422         case MSR_IA32_MCG_STATUS:
2423                 data = vcpu->arch.mcg_status;
2424                 break;
2425         default:
2426                 if (msr >= MSR_IA32_MC0_CTL &&
2427                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2428                         u32 offset = msr - MSR_IA32_MC0_CTL;
2429                         data = vcpu->arch.mce_banks[offset];
2430                         break;
2431                 }
2432                 return 1;
2433         }
2434         *pdata = data;
2435         return 0;
2436 }
2437
2438 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2439 {
2440         u64 data = 0;
2441         struct kvm *kvm = vcpu->kvm;
2442
2443         switch (msr) {
2444         case HV_X64_MSR_GUEST_OS_ID:
2445                 data = kvm->arch.hv_guest_os_id;
2446                 break;
2447         case HV_X64_MSR_HYPERCALL:
2448                 data = kvm->arch.hv_hypercall;
2449                 break;
2450         case HV_X64_MSR_TIME_REF_COUNT: {
2451                 data =
2452                      div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2453                 break;
2454         }
2455         case HV_X64_MSR_REFERENCE_TSC:
2456                 data = kvm->arch.hv_tsc_page;
2457                 break;
2458         default:
2459                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2460                 return 1;
2461         }
2462
2463         *pdata = data;
2464         return 0;
2465 }
2466
2467 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2468 {
2469         u64 data = 0;
2470
2471         switch (msr) {
2472         case HV_X64_MSR_VP_INDEX: {
2473                 int r;
2474                 struct kvm_vcpu *v;
2475                 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2476                         if (v == vcpu) {
2477                                 data = r;
2478                                 break;
2479                         }
2480                 }
2481                 break;
2482         }
2483         case HV_X64_MSR_EOI:
2484                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2485         case HV_X64_MSR_ICR:
2486                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2487         case HV_X64_MSR_TPR:
2488                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2489         case HV_X64_MSR_APIC_ASSIST_PAGE:
2490                 data = vcpu->arch.hv_vapic;
2491                 break;
2492         default:
2493                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2494                 return 1;
2495         }
2496         *pdata = data;
2497         return 0;
2498 }
2499
2500 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2501 {
2502         u64 data;
2503
2504         switch (msr) {
2505         case MSR_IA32_PLATFORM_ID:
2506         case MSR_IA32_EBL_CR_POWERON:
2507         case MSR_IA32_DEBUGCTLMSR:
2508         case MSR_IA32_LASTBRANCHFROMIP:
2509         case MSR_IA32_LASTBRANCHTOIP:
2510         case MSR_IA32_LASTINTFROMIP:
2511         case MSR_IA32_LASTINTTOIP:
2512         case MSR_K8_SYSCFG:
2513         case MSR_K7_HWCR:
2514         case MSR_VM_HSAVE_PA:
2515         case MSR_K7_EVNTSEL0:
2516         case MSR_K7_EVNTSEL1:
2517         case MSR_K7_EVNTSEL2:
2518         case MSR_K7_EVNTSEL3:
2519         case MSR_K7_PERFCTR0:
2520         case MSR_K7_PERFCTR1:
2521         case MSR_K7_PERFCTR2:
2522         case MSR_K7_PERFCTR3:
2523         case MSR_K8_INT_PENDING_MSG:
2524         case MSR_AMD64_NB_CFG:
2525         case MSR_FAM10H_MMIO_CONF_BASE:
2526         case MSR_AMD64_BU_CFG2:
2527                 data = 0;
2528                 break;
2529         case MSR_P6_PERFCTR0:
2530         case MSR_P6_PERFCTR1:
2531         case MSR_P6_EVNTSEL0:
2532         case MSR_P6_EVNTSEL1:
2533                 if (kvm_pmu_msr(vcpu, msr))
2534                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2535                 data = 0;
2536                 break;
2537         case MSR_IA32_UCODE_REV:
2538                 data = 0x100000000ULL;
2539                 break;
2540         case MSR_MTRRcap:
2541                 data = 0x500 | KVM_NR_VAR_MTRR;
2542                 break;
2543         case 0x200 ... 0x2ff:
2544                 return get_msr_mtrr(vcpu, msr, pdata);
2545         case 0xcd: /* fsb frequency */
2546                 data = 3;
2547                 break;
2548                 /*
2549                  * MSR_EBC_FREQUENCY_ID
2550                  * Conservative value valid for even the basic CPU models.
2551                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2552                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2553                  * and 266MHz for model 3, or 4. Set Core Clock
2554                  * Frequency to System Bus Frequency Ratio to 1 (bits
2555                  * 31:24) even though these are only valid for CPU
2556                  * models > 2, however guests may end up dividing or
2557                  * multiplying by zero otherwise.
2558                  */
2559         case MSR_EBC_FREQUENCY_ID:
2560                 data = 1 << 24;
2561                 break;
2562         case MSR_IA32_APICBASE:
2563                 data = kvm_get_apic_base(vcpu);
2564                 break;
2565         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2566                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2567                 break;
2568         case MSR_IA32_TSCDEADLINE:
2569                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2570                 break;
2571         case MSR_IA32_TSC_ADJUST:
2572                 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2573                 break;
2574         case MSR_IA32_MISC_ENABLE:
2575                 data = vcpu->arch.ia32_misc_enable_msr;
2576                 break;
2577         case MSR_IA32_PERF_STATUS:
2578                 /* TSC increment by tick */
2579                 data = 1000ULL;
2580                 /* CPU multiplier */
2581                 data |= (((uint64_t)4ULL) << 40);
2582                 break;
2583         case MSR_EFER:
2584                 data = vcpu->arch.efer;
2585                 break;
2586         case MSR_KVM_WALL_CLOCK:
2587         case MSR_KVM_WALL_CLOCK_NEW:
2588                 data = vcpu->kvm->arch.wall_clock;
2589                 break;
2590         case MSR_KVM_SYSTEM_TIME:
2591         case MSR_KVM_SYSTEM_TIME_NEW:
2592                 data = vcpu->arch.time;
2593                 break;
2594         case MSR_KVM_ASYNC_PF_EN:
2595                 data = vcpu->arch.apf.msr_val;
2596                 break;
2597         case MSR_KVM_STEAL_TIME:
2598                 data = vcpu->arch.st.msr_val;
2599                 break;
2600         case MSR_KVM_PV_EOI_EN:
2601                 data = vcpu->arch.pv_eoi.msr_val;
2602                 break;
2603         case MSR_IA32_P5_MC_ADDR:
2604         case MSR_IA32_P5_MC_TYPE:
2605         case MSR_IA32_MCG_CAP:
2606         case MSR_IA32_MCG_CTL:
2607         case MSR_IA32_MCG_STATUS:
2608         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2609                 return get_msr_mce(vcpu, msr, pdata);
2610         case MSR_K7_CLK_CTL:
2611                 /*
2612                  * Provide expected ramp-up count for K7. All other
2613                  * are set to zero, indicating minimum divisors for
2614                  * every field.
2615                  *
2616                  * This prevents guest kernels on AMD host with CPU
2617                  * type 6, model 8 and higher from exploding due to
2618                  * the rdmsr failing.
2619                  */
2620                 data = 0x20000000;
2621                 break;
2622         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2623                 if (kvm_hv_msr_partition_wide(msr)) {
2624                         int r;
2625                         mutex_lock(&vcpu->kvm->lock);
2626                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2627                         mutex_unlock(&vcpu->kvm->lock);
2628                         return r;
2629                 } else
2630                         return get_msr_hyperv(vcpu, msr, pdata);
2631                 break;
2632         case MSR_IA32_BBL_CR_CTL3:
2633                 /* This legacy MSR exists but isn't fully documented in current
2634                  * silicon.  It is however accessed by winxp in very narrow
2635                  * scenarios where it sets bit #19, itself documented as
2636                  * a "reserved" bit.  Best effort attempt to source coherent
2637                  * read data here should the balance of the register be
2638                  * interpreted by the guest:
2639                  *
2640                  * L2 cache control register 3: 64GB range, 256KB size,
2641                  * enabled, latency 0x1, configured
2642                  */
2643                 data = 0xbe702111;
2644                 break;
2645         case MSR_AMD64_OSVW_ID_LENGTH:
2646                 if (!guest_cpuid_has_osvw(vcpu))
2647                         return 1;
2648                 data = vcpu->arch.osvw.length;
2649                 break;
2650         case MSR_AMD64_OSVW_STATUS:
2651                 if (!guest_cpuid_has_osvw(vcpu))
2652                         return 1;
2653                 data = vcpu->arch.osvw.status;
2654                 break;
2655         default:
2656                 if (kvm_pmu_msr(vcpu, msr))
2657                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2658                 if (!ignore_msrs) {
2659                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2660                         return 1;
2661                 } else {
2662                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2663                         data = 0;
2664                 }
2665                 break;
2666         }
2667         *pdata = data;
2668         return 0;
2669 }
2670 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2671
2672 /*
2673  * Read or write a bunch of msrs. All parameters are kernel addresses.
2674  *
2675  * @return number of msrs set successfully.
2676  */
2677 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2678                     struct kvm_msr_entry *entries,
2679                     int (*do_msr)(struct kvm_vcpu *vcpu,
2680                                   unsigned index, u64 *data))
2681 {
2682         int i, idx;
2683
2684         idx = srcu_read_lock(&vcpu->kvm->srcu);
2685         for (i = 0; i < msrs->nmsrs; ++i)
2686                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2687                         break;
2688         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2689
2690         return i;
2691 }
2692
2693 /*
2694  * Read or write a bunch of msrs. Parameters are user addresses.
2695  *
2696  * @return number of msrs set successfully.
2697  */
2698 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2699                   int (*do_msr)(struct kvm_vcpu *vcpu,
2700                                 unsigned index, u64 *data),
2701                   int writeback)
2702 {
2703         struct kvm_msrs msrs;
2704         struct kvm_msr_entry *entries;
2705         int r, n;
2706         unsigned size;
2707
2708         r = -EFAULT;
2709         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2710                 goto out;
2711
2712         r = -E2BIG;
2713         if (msrs.nmsrs >= MAX_IO_MSRS)
2714                 goto out;
2715
2716         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2717         entries = memdup_user(user_msrs->entries, size);
2718         if (IS_ERR(entries)) {
2719                 r = PTR_ERR(entries);
2720                 goto out;
2721         }
2722
2723         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2724         if (r < 0)
2725                 goto out_free;
2726
2727         r = -EFAULT;
2728         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2729                 goto out_free;
2730
2731         r = n;
2732
2733 out_free:
2734         kfree(entries);
2735 out:
2736         return r;
2737 }
2738
2739 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2740 {
2741         int r;
2742
2743         switch (ext) {
2744         case KVM_CAP_IRQCHIP:
2745         case KVM_CAP_HLT:
2746         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2747         case KVM_CAP_SET_TSS_ADDR:
2748         case KVM_CAP_EXT_CPUID:
2749         case KVM_CAP_EXT_EMUL_CPUID:
2750         case KVM_CAP_CLOCKSOURCE:
2751         case KVM_CAP_PIT:
2752         case KVM_CAP_NOP_IO_DELAY:
2753         case KVM_CAP_MP_STATE:
2754         case KVM_CAP_SYNC_MMU:
2755         case KVM_CAP_USER_NMI:
2756         case KVM_CAP_REINJECT_CONTROL:
2757         case KVM_CAP_IRQ_INJECT_STATUS:
2758         case KVM_CAP_IOEVENTFD:
2759         case KVM_CAP_IOEVENTFD_NO_LENGTH:
2760         case KVM_CAP_PIT2:
2761         case KVM_CAP_PIT_STATE2:
2762         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2763         case KVM_CAP_XEN_HVM:
2764         case KVM_CAP_ADJUST_CLOCK:
2765         case KVM_CAP_VCPU_EVENTS:
2766         case KVM_CAP_HYPERV:
2767         case KVM_CAP_HYPERV_VAPIC:
2768         case KVM_CAP_HYPERV_SPIN:
2769         case KVM_CAP_PCI_SEGMENT:
2770         case KVM_CAP_DEBUGREGS:
2771         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2772         case KVM_CAP_XSAVE:
2773         case KVM_CAP_ASYNC_PF:
2774         case KVM_CAP_GET_TSC_KHZ:
2775         case KVM_CAP_KVMCLOCK_CTRL:
2776         case KVM_CAP_READONLY_MEM:
2777         case KVM_CAP_HYPERV_TIME:
2778         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2779         case KVM_CAP_TSC_DEADLINE_TIMER:
2780 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2781         case KVM_CAP_ASSIGN_DEV_IRQ:
2782         case KVM_CAP_PCI_2_3:
2783 #endif
2784                 r = 1;
2785                 break;
2786         case KVM_CAP_COALESCED_MMIO:
2787                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2788                 break;
2789         case KVM_CAP_VAPIC:
2790                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2791                 break;
2792         case KVM_CAP_NR_VCPUS:
2793                 r = KVM_SOFT_MAX_VCPUS;
2794                 break;
2795         case KVM_CAP_MAX_VCPUS:
2796                 r = KVM_MAX_VCPUS;
2797                 break;
2798         case KVM_CAP_NR_MEMSLOTS:
2799                 r = KVM_USER_MEM_SLOTS;
2800                 break;
2801         case KVM_CAP_PV_MMU:    /* obsolete */
2802                 r = 0;
2803                 break;
2804 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2805         case KVM_CAP_IOMMU:
2806                 r = iommu_present(&pci_bus_type);
2807                 break;
2808 #endif
2809         case KVM_CAP_MCE:
2810                 r = KVM_MAX_MCE_BANKS;
2811                 break;
2812         case KVM_CAP_XCRS:
2813                 r = cpu_has_xsave;
2814                 break;
2815         case KVM_CAP_TSC_CONTROL:
2816                 r = kvm_has_tsc_control;
2817                 break;
2818         default:
2819                 r = 0;
2820                 break;
2821         }
2822         return r;
2823
2824 }
2825
2826 long kvm_arch_dev_ioctl(struct file *filp,
2827                         unsigned int ioctl, unsigned long arg)
2828 {
2829         void __user *argp = (void __user *)arg;
2830         long r;
2831
2832         switch (ioctl) {
2833         case KVM_GET_MSR_INDEX_LIST: {
2834                 struct kvm_msr_list __user *user_msr_list = argp;
2835                 struct kvm_msr_list msr_list;
2836                 unsigned n;
2837
2838                 r = -EFAULT;
2839                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2840                         goto out;
2841                 n = msr_list.nmsrs;
2842                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2843                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2844                         goto out;
2845                 r = -E2BIG;
2846                 if (n < msr_list.nmsrs)
2847                         goto out;
2848                 r = -EFAULT;
2849                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2850                                  num_msrs_to_save * sizeof(u32)))
2851                         goto out;
2852                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2853                                  &emulated_msrs,
2854                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2855                         goto out;
2856                 r = 0;
2857                 break;
2858         }
2859         case KVM_GET_SUPPORTED_CPUID:
2860         case KVM_GET_EMULATED_CPUID: {
2861                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2862                 struct kvm_cpuid2 cpuid;
2863
2864                 r = -EFAULT;
2865                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2866                         goto out;
2867
2868                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2869                                             ioctl);
2870                 if (r)
2871                         goto out;
2872
2873                 r = -EFAULT;
2874                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2875                         goto out;
2876                 r = 0;
2877                 break;
2878         }
2879         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2880                 u64 mce_cap;
2881
2882                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2883                 r = -EFAULT;
2884                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2885                         goto out;
2886                 r = 0;
2887                 break;
2888         }
2889         default:
2890                 r = -EINVAL;
2891         }
2892 out:
2893         return r;
2894 }
2895
2896 static void wbinvd_ipi(void *garbage)
2897 {
2898         wbinvd();
2899 }
2900
2901 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2902 {
2903         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2904 }
2905
2906 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2907 {
2908         /* Address WBINVD may be executed by guest */
2909         if (need_emulate_wbinvd(vcpu)) {
2910                 if (kvm_x86_ops->has_wbinvd_exit())
2911                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2912                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2913                         smp_call_function_single(vcpu->cpu,
2914                                         wbinvd_ipi, NULL, 1);
2915         }
2916
2917         kvm_x86_ops->vcpu_load(vcpu, cpu);
2918
2919         /* Apply any externally detected TSC adjustments (due to suspend) */
2920         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2921                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2922                 vcpu->arch.tsc_offset_adjustment = 0;
2923                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2924         }
2925
2926         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2927                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2928                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2929                 if (tsc_delta < 0)
2930                         mark_tsc_unstable("KVM discovered backwards TSC");
2931                 if (check_tsc_unstable()) {
2932                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2933                                                 vcpu->arch.last_guest_tsc);
2934                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2935                         vcpu->arch.tsc_catchup = 1;
2936                 }
2937                 /*
2938                  * On a host with synchronized TSC, there is no need to update
2939                  * kvmclock on vcpu->cpu migration
2940                  */
2941                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2942                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2943                 if (vcpu->cpu != cpu)
2944                         kvm_migrate_timers(vcpu);
2945                 vcpu->cpu = cpu;
2946         }
2947
2948         accumulate_steal_time(vcpu);
2949         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2950 }
2951
2952 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2953 {
2954         kvm_x86_ops->vcpu_put(vcpu);
2955         kvm_put_guest_fpu(vcpu);
2956         vcpu->arch.last_host_tsc = native_read_tsc();
2957 }
2958
2959 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2960                                     struct kvm_lapic_state *s)
2961 {
2962         kvm_x86_ops->sync_pir_to_irr(vcpu);
2963         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2964
2965         return 0;
2966 }
2967
2968 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2969                                     struct kvm_lapic_state *s)
2970 {
2971         kvm_apic_post_state_restore(vcpu, s);
2972         update_cr8_intercept(vcpu);
2973
2974         return 0;
2975 }
2976
2977 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2978                                     struct kvm_interrupt *irq)
2979 {
2980         if (irq->irq >= KVM_NR_INTERRUPTS)
2981                 return -EINVAL;
2982         if (irqchip_in_kernel(vcpu->kvm))
2983                 return -ENXIO;
2984
2985         kvm_queue_interrupt(vcpu, irq->irq, false);
2986         kvm_make_request(KVM_REQ_EVENT, vcpu);
2987
2988         return 0;
2989 }
2990
2991 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2992 {
2993         kvm_inject_nmi(vcpu);
2994
2995         return 0;
2996 }
2997
2998 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2999                                            struct kvm_tpr_access_ctl *tac)
3000 {
3001         if (tac->flags)
3002                 return -EINVAL;
3003         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3004         return 0;
3005 }
3006
3007 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3008                                         u64 mcg_cap)
3009 {
3010         int r;
3011         unsigned bank_num = mcg_cap & 0xff, bank;
3012
3013         r = -EINVAL;
3014         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3015                 goto out;
3016         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3017                 goto out;
3018         r = 0;
3019         vcpu->arch.mcg_cap = mcg_cap;
3020         /* Init IA32_MCG_CTL to all 1s */
3021         if (mcg_cap & MCG_CTL_P)
3022                 vcpu->arch.mcg_ctl = ~(u64)0;
3023         /* Init IA32_MCi_CTL to all 1s */
3024         for (bank = 0; bank < bank_num; bank++)
3025                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3026 out:
3027         return r;
3028 }
3029
3030 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3031                                       struct kvm_x86_mce *mce)
3032 {
3033         u64 mcg_cap = vcpu->arch.mcg_cap;
3034         unsigned bank_num = mcg_cap & 0xff;
3035         u64 *banks = vcpu->arch.mce_banks;
3036
3037         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3038                 return -EINVAL;
3039         /*
3040          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3041          * reporting is disabled
3042          */
3043         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3044             vcpu->arch.mcg_ctl != ~(u64)0)
3045                 return 0;
3046         banks += 4 * mce->bank;
3047         /*
3048          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3049          * reporting is disabled for the bank
3050          */
3051         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3052                 return 0;
3053         if (mce->status & MCI_STATUS_UC) {
3054                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3055                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3056                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3057                         return 0;
3058                 }
3059                 if (banks[1] & MCI_STATUS_VAL)
3060                         mce->status |= MCI_STATUS_OVER;
3061                 banks[2] = mce->addr;
3062                 banks[3] = mce->misc;
3063                 vcpu->arch.mcg_status = mce->mcg_status;
3064                 banks[1] = mce->status;
3065                 kvm_queue_exception(vcpu, MC_VECTOR);
3066         } else if (!(banks[1] & MCI_STATUS_VAL)
3067                    || !(banks[1] & MCI_STATUS_UC)) {
3068                 if (banks[1] & MCI_STATUS_VAL)
3069                         mce->status |= MCI_STATUS_OVER;
3070                 banks[2] = mce->addr;
3071                 banks[3] = mce->misc;
3072                 banks[1] = mce->status;
3073         } else
3074                 banks[1] |= MCI_STATUS_OVER;
3075         return 0;
3076 }
3077
3078 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3079                                                struct kvm_vcpu_events *events)
3080 {
3081         process_nmi(vcpu);
3082         events->exception.injected =
3083                 vcpu->arch.exception.pending &&
3084                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3085         events->exception.nr = vcpu->arch.exception.nr;
3086         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3087         events->exception.pad = 0;
3088         events->exception.error_code = vcpu->arch.exception.error_code;
3089
3090         events->interrupt.injected =
3091                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3092         events->interrupt.nr = vcpu->arch.interrupt.nr;
3093         events->interrupt.soft = 0;
3094         events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3095
3096         events->nmi.injected = vcpu->arch.nmi_injected;
3097         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3098         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3099         events->nmi.pad = 0;
3100
3101         events->sipi_vector = 0; /* never valid when reporting to user space */
3102
3103         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3104                          | KVM_VCPUEVENT_VALID_SHADOW);
3105         memset(&events->reserved, 0, sizeof(events->reserved));
3106 }
3107
3108 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3109                                               struct kvm_vcpu_events *events)
3110 {
3111         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3112                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3113                               | KVM_VCPUEVENT_VALID_SHADOW))
3114                 return -EINVAL;
3115
3116         process_nmi(vcpu);
3117         vcpu->arch.exception.pending = events->exception.injected;
3118         vcpu->arch.exception.nr = events->exception.nr;
3119         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3120         vcpu->arch.exception.error_code = events->exception.error_code;
3121
3122         vcpu->arch.interrupt.pending = events->interrupt.injected;
3123         vcpu->arch.interrupt.nr = events->interrupt.nr;
3124         vcpu->arch.interrupt.soft = events->interrupt.soft;
3125         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3126                 kvm_x86_ops->set_interrupt_shadow(vcpu,
3127                                                   events->interrupt.shadow);
3128
3129         vcpu->arch.nmi_injected = events->nmi.injected;
3130         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3131                 vcpu->arch.nmi_pending = events->nmi.pending;
3132         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3133
3134         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3135             kvm_vcpu_has_lapic(vcpu))
3136                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3137
3138         kvm_make_request(KVM_REQ_EVENT, vcpu);
3139
3140         return 0;
3141 }
3142
3143 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3144                                              struct kvm_debugregs *dbgregs)
3145 {
3146         unsigned long val;
3147
3148         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3149         kvm_get_dr(vcpu, 6, &val);
3150         dbgregs->dr6 = val;
3151         dbgregs->dr7 = vcpu->arch.dr7;
3152         dbgregs->flags = 0;
3153         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3154 }
3155
3156 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3157                                             struct kvm_debugregs *dbgregs)
3158 {
3159         if (dbgregs->flags)
3160                 return -EINVAL;
3161
3162         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3163         kvm_update_dr0123(vcpu);
3164         vcpu->arch.dr6 = dbgregs->dr6;
3165         kvm_update_dr6(vcpu);
3166         vcpu->arch.dr7 = dbgregs->dr7;
3167         kvm_update_dr7(vcpu);
3168
3169         return 0;
3170 }
3171
3172 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3173
3174 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3175 {
3176         struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3177         u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3178         u64 valid;
3179
3180         /*
3181          * Copy legacy XSAVE area, to avoid complications with CPUID
3182          * leaves 0 and 1 in the loop below.
3183          */
3184         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3185
3186         /* Set XSTATE_BV */
3187         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3188
3189         /*
3190          * Copy each region from the possibly compacted offset to the
3191          * non-compacted offset.
3192          */
3193         valid = xstate_bv & ~XSTATE_FPSSE;
3194         while (valid) {
3195                 u64 feature = valid & -valid;
3196                 int index = fls64(feature) - 1;
3197                 void *src = get_xsave_addr(xsave, feature);
3198
3199                 if (src) {
3200                         u32 size, offset, ecx, edx;
3201                         cpuid_count(XSTATE_CPUID, index,
3202                                     &size, &offset, &ecx, &edx);
3203                         memcpy(dest + offset, src, size);
3204                 }
3205
3206                 valid -= feature;
3207         }
3208 }
3209
3210 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3211 {
3212         struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3213         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3214         u64 valid;
3215
3216         /*
3217          * Copy legacy XSAVE area, to avoid complications with CPUID
3218          * leaves 0 and 1 in the loop below.
3219          */
3220         memcpy(xsave, src, XSAVE_HDR_OFFSET);
3221
3222         /* Set XSTATE_BV and possibly XCOMP_BV.  */
3223         xsave->xsave_hdr.xstate_bv = xstate_bv;
3224         if (cpu_has_xsaves)
3225                 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3226
3227         /*
3228          * Copy each region from the non-compacted offset to the
3229          * possibly compacted offset.
3230          */
3231         valid = xstate_bv & ~XSTATE_FPSSE;
3232         while (valid) {
3233                 u64 feature = valid & -valid;
3234                 int index = fls64(feature) - 1;
3235                 void *dest = get_xsave_addr(xsave, feature);
3236
3237                 if (dest) {
3238                         u32 size, offset, ecx, edx;
3239                         cpuid_count(XSTATE_CPUID, index,
3240                                     &size, &offset, &ecx, &edx);
3241                         memcpy(dest, src + offset, size);
3242                 } else
3243                         WARN_ON_ONCE(1);
3244
3245                 valid -= feature;
3246         }
3247 }
3248
3249 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3250                                          struct kvm_xsave *guest_xsave)
3251 {
3252         if (cpu_has_xsave) {
3253                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3254                 fill_xsave((u8 *) guest_xsave->region, vcpu);
3255         } else {
3256                 memcpy(guest_xsave->region,
3257                         &vcpu->arch.guest_fpu.state->fxsave,
3258                         sizeof(struct i387_fxsave_struct));
3259                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3260                         XSTATE_FPSSE;
3261         }
3262 }
3263
3264 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3265                                         struct kvm_xsave *guest_xsave)
3266 {
3267         u64 xstate_bv =
3268                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3269
3270         if (cpu_has_xsave) {
3271                 /*
3272                  * Here we allow setting states that are not present in
3273                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3274                  * with old userspace.
3275                  */
3276                 if (xstate_bv & ~kvm_supported_xcr0())
3277                         return -EINVAL;
3278                 load_xsave(vcpu, (u8 *)guest_xsave->region);
3279         } else {
3280                 if (xstate_bv & ~XSTATE_FPSSE)
3281                         return -EINVAL;
3282                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3283                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
3284         }
3285         return 0;
3286 }
3287
3288 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3289                                         struct kvm_xcrs *guest_xcrs)
3290 {
3291         if (!cpu_has_xsave) {
3292                 guest_xcrs->nr_xcrs = 0;
3293                 return;
3294         }
3295
3296         guest_xcrs->nr_xcrs = 1;
3297         guest_xcrs->flags = 0;
3298         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3299         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3300 }
3301
3302 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3303                                        struct kvm_xcrs *guest_xcrs)
3304 {
3305         int i, r = 0;
3306
3307         if (!cpu_has_xsave)
3308                 return -EINVAL;
3309
3310         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3311                 return -EINVAL;
3312
3313         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3314                 /* Only support XCR0 currently */
3315                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3316                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3317                                 guest_xcrs->xcrs[i].value);
3318                         break;
3319                 }
3320         if (r)
3321                 r = -EINVAL;
3322         return r;
3323 }
3324
3325 /*
3326  * kvm_set_guest_paused() indicates to the guest kernel that it has been
3327  * stopped by the hypervisor.  This function will be called from the host only.
3328  * EINVAL is returned when the host attempts to set the flag for a guest that
3329  * does not support pv clocks.
3330  */
3331 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3332 {
3333         if (!vcpu->arch.pv_time_enabled)
3334                 return -EINVAL;
3335         vcpu->arch.pvclock_set_guest_stopped_request = true;
3336         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3337         return 0;
3338 }
3339
3340 long kvm_arch_vcpu_ioctl(struct file *filp,
3341                          unsigned int ioctl, unsigned long arg)
3342 {
3343         struct kvm_vcpu *vcpu = filp->private_data;
3344         void __user *argp = (void __user *)arg;
3345         int r;
3346         union {
3347                 struct kvm_lapic_state *lapic;
3348                 struct kvm_xsave *xsave;
3349                 struct kvm_xcrs *xcrs;
3350                 void *buffer;
3351         } u;
3352
3353         u.buffer = NULL;
3354         switch (ioctl) {
3355         case KVM_GET_LAPIC: {
3356                 r = -EINVAL;
3357                 if (!vcpu->arch.apic)
3358                         goto out;
3359                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3360
3361                 r = -ENOMEM;
3362                 if (!u.lapic)
3363                         goto out;
3364                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3365                 if (r)
3366                         goto out;
3367                 r = -EFAULT;
3368                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3369                         goto out;
3370                 r = 0;
3371                 break;
3372         }
3373         case KVM_SET_LAPIC: {
3374                 r = -EINVAL;
3375                 if (!vcpu->arch.apic)
3376                         goto out;
3377                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3378                 if (IS_ERR(u.lapic))
3379                         return PTR_ERR(u.lapic);
3380
3381                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3382                 break;
3383         }
3384         case KVM_INTERRUPT: {
3385                 struct kvm_interrupt irq;
3386
3387                 r = -EFAULT;
3388                 if (copy_from_user(&irq, argp, sizeof irq))
3389                         goto out;
3390                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3391                 break;
3392         }
3393         case KVM_NMI: {
3394                 r = kvm_vcpu_ioctl_nmi(vcpu);
3395                 break;
3396         }
3397         case KVM_SET_CPUID: {
3398                 struct kvm_cpuid __user *cpuid_arg = argp;
3399                 struct kvm_cpuid cpuid;
3400
3401                 r = -EFAULT;
3402                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3403                         goto out;
3404                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3405                 break;
3406         }
3407         case KVM_SET_CPUID2: {
3408                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3409                 struct kvm_cpuid2 cpuid;
3410
3411                 r = -EFAULT;
3412                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3413                         goto out;
3414                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3415                                               cpuid_arg->entries);
3416                 break;
3417         }
3418         case KVM_GET_CPUID2: {
3419                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3420                 struct kvm_cpuid2 cpuid;
3421
3422                 r = -EFAULT;
3423                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3424                         goto out;
3425                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3426                                               cpuid_arg->entries);
3427                 if (r)
3428                         goto out;
3429                 r = -EFAULT;
3430                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3431                         goto out;
3432                 r = 0;
3433                 break;
3434         }
3435         case KVM_GET_MSRS:
3436                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3437                 break;
3438         case KVM_SET_MSRS:
3439                 r = msr_io(vcpu, argp, do_set_msr, 0);
3440                 break;
3441         case KVM_TPR_ACCESS_REPORTING: {
3442                 struct kvm_tpr_access_ctl tac;
3443
3444                 r = -EFAULT;
3445                 if (copy_from_user(&tac, argp, sizeof tac))
3446                         goto out;
3447                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3448                 if (r)
3449                         goto out;
3450                 r = -EFAULT;
3451                 if (copy_to_user(argp, &tac, sizeof tac))
3452                         goto out;
3453                 r = 0;
3454                 break;
3455         };
3456         case KVM_SET_VAPIC_ADDR: {
3457                 struct kvm_vapic_addr va;
3458
3459                 r = -EINVAL;
3460                 if (!irqchip_in_kernel(vcpu->kvm))
3461                         goto out;
3462                 r = -EFAULT;
3463                 if (copy_from_user(&va, argp, sizeof va))
3464                         goto out;
3465                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3466                 break;
3467         }
3468         case KVM_X86_SETUP_MCE: {
3469                 u64 mcg_cap;
3470
3471                 r = -EFAULT;
3472                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3473                         goto out;
3474                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3475                 break;
3476         }
3477         case KVM_X86_SET_MCE: {
3478                 struct kvm_x86_mce mce;
3479
3480                 r = -EFAULT;
3481                 if (copy_from_user(&mce, argp, sizeof mce))
3482                         goto out;
3483                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3484                 break;
3485         }
3486         case KVM_GET_VCPU_EVENTS: {
3487                 struct kvm_vcpu_events events;
3488
3489                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3490
3491                 r = -EFAULT;
3492                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3493                         break;
3494                 r = 0;
3495                 break;
3496         }
3497         case KVM_SET_VCPU_EVENTS: {
3498                 struct kvm_vcpu_events events;
3499
3500                 r = -EFAULT;
3501                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3502                         break;
3503
3504                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3505                 break;
3506         }
3507         case KVM_GET_DEBUGREGS: {
3508                 struct kvm_debugregs dbgregs;
3509
3510                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3511
3512                 r = -EFAULT;
3513                 if (copy_to_user(argp, &dbgregs,
3514                                  sizeof(struct kvm_debugregs)))
3515                         break;
3516                 r = 0;
3517                 break;
3518         }
3519         case KVM_SET_DEBUGREGS: {
3520                 struct kvm_debugregs dbgregs;
3521
3522                 r = -EFAULT;
3523                 if (copy_from_user(&dbgregs, argp,
3524                                    sizeof(struct kvm_debugregs)))
3525                         break;
3526
3527                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3528                 break;
3529         }
3530         case KVM_GET_XSAVE: {
3531                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3532                 r = -ENOMEM;
3533                 if (!u.xsave)
3534                         break;
3535
3536                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3537
3538                 r = -EFAULT;
3539                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3540                         break;
3541                 r = 0;
3542                 break;
3543         }
3544         case KVM_SET_XSAVE: {
3545                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3546                 if (IS_ERR(u.xsave))
3547                         return PTR_ERR(u.xsave);
3548
3549                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3550                 break;
3551         }
3552         case KVM_GET_XCRS: {
3553                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3554                 r = -ENOMEM;
3555                 if (!u.xcrs)
3556                         break;
3557
3558                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3559
3560                 r = -EFAULT;
3561                 if (copy_to_user(argp, u.xcrs,
3562                                  sizeof(struct kvm_xcrs)))
3563                         break;
3564                 r = 0;
3565                 break;
3566         }
3567         case KVM_SET_XCRS: {
3568                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3569                 if (IS_ERR(u.xcrs))
3570                         return PTR_ERR(u.xcrs);
3571
3572                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3573                 break;
3574         }
3575         case KVM_SET_TSC_KHZ: {
3576                 u32 user_tsc_khz;
3577
3578                 r = -EINVAL;
3579                 user_tsc_khz = (u32)arg;
3580
3581                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3582                         goto out;
3583
3584                 if (user_tsc_khz == 0)
3585                         user_tsc_khz = tsc_khz;
3586
3587                 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3588
3589                 r = 0;
3590                 goto out;
3591         }
3592         case KVM_GET_TSC_KHZ: {
3593                 r = vcpu->arch.virtual_tsc_khz;
3594                 goto out;
3595         }
3596         case KVM_KVMCLOCK_CTRL: {
3597                 r = kvm_set_guest_paused(vcpu);
3598                 goto out;
3599         }
3600         default:
3601                 r = -EINVAL;
3602         }
3603 out:
3604         kfree(u.buffer);
3605         return r;
3606 }
3607
3608 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3609 {
3610         return VM_FAULT_SIGBUS;
3611 }
3612
3613 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3614 {
3615         int ret;
3616
3617         if (addr > (unsigned int)(-3 * PAGE_SIZE))
3618                 return -EINVAL;
3619         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3620         return ret;
3621 }
3622
3623 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3624                                               u64 ident_addr)
3625 {
3626         kvm->arch.ept_identity_map_addr = ident_addr;
3627         return 0;
3628 }
3629
3630 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3631                                           u32 kvm_nr_mmu_pages)
3632 {
3633         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3634                 return -EINVAL;
3635
3636         mutex_lock(&kvm->slots_lock);
3637
3638         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3639         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3640
3641         mutex_unlock(&kvm->slots_lock);
3642         return 0;
3643 }
3644
3645 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3646 {
3647         return kvm->arch.n_max_mmu_pages;
3648 }
3649
3650 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3651 {
3652         int r;
3653
3654         r = 0;
3655         switch (chip->chip_id) {
3656         case KVM_IRQCHIP_PIC_MASTER:
3657                 memcpy(&chip->chip.pic,
3658                         &pic_irqchip(kvm)->pics[0],
3659                         sizeof(struct kvm_pic_state));
3660                 break;
3661         case KVM_IRQCHIP_PIC_SLAVE:
3662                 memcpy(&chip->chip.pic,
3663                         &pic_irqchip(kvm)->pics[1],
3664                         sizeof(struct kvm_pic_state));
3665                 break;
3666         case KVM_IRQCHIP_IOAPIC:
3667                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3668                 break;
3669         default:
3670                 r = -EINVAL;
3671                 break;
3672         }
3673         return r;
3674 }
3675
3676 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3677 {
3678         int r;
3679
3680         r = 0;
3681         switch (chip->chip_id) {
3682         case KVM_IRQCHIP_PIC_MASTER:
3683                 spin_lock(&pic_irqchip(kvm)->lock);
3684                 memcpy(&pic_irqchip(kvm)->pics[0],
3685                         &chip->chip.pic,
3686                         sizeof(struct kvm_pic_state));
3687                 spin_unlock(&pic_irqchip(kvm)->lock);
3688                 break;
3689         case KVM_IRQCHIP_PIC_SLAVE:
3690                 spin_lock(&pic_irqchip(kvm)->lock);
3691                 memcpy(&pic_irqchip(kvm)->pics[1],
3692                         &chip->chip.pic,
3693                         sizeof(struct kvm_pic_state));
3694                 spin_unlock(&pic_irqchip(kvm)->lock);
3695                 break;
3696         case KVM_IRQCHIP_IOAPIC:
3697                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3698                 break;
3699         default:
3700                 r = -EINVAL;
3701                 break;
3702         }
3703         kvm_pic_update_irq(pic_irqchip(kvm));
3704         return r;
3705 }
3706
3707 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3708 {
3709         int r = 0;
3710
3711         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3712         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3713         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3714         return r;
3715 }
3716
3717 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3718 {
3719         int r = 0;
3720
3721         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3722         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3723         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3724         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3725         return r;
3726 }
3727
3728 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3729 {
3730         int r = 0;
3731
3732         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3733         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3734                 sizeof(ps->channels));
3735         ps->flags = kvm->arch.vpit->pit_state.flags;
3736         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3737         memset(&ps->reserved, 0, sizeof(ps->reserved));
3738         return r;
3739 }
3740
3741 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3742 {
3743         int r = 0, start = 0;
3744         u32 prev_legacy, cur_legacy;
3745         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3746         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3747         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3748         if (!prev_legacy && cur_legacy)
3749                 start = 1;
3750         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3751                sizeof(kvm->arch.vpit->pit_state.channels));
3752         kvm->arch.vpit->pit_state.flags = ps->flags;
3753         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3754         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3755         return r;
3756 }
3757
3758 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3759                                  struct kvm_reinject_control *control)
3760 {
3761         if (!kvm->arch.vpit)
3762                 return -ENXIO;
3763         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3764         kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3765         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3766         return 0;
3767 }
3768
3769 /**
3770  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3771  * @kvm: kvm instance
3772  * @log: slot id and address to which we copy the log
3773  *
3774  * Steps 1-4 below provide general overview of dirty page logging. See
3775  * kvm_get_dirty_log_protect() function description for additional details.
3776  *
3777  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3778  * always flush the TLB (step 4) even if previous step failed  and the dirty
3779  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3780  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3781  * writes will be marked dirty for next log read.
3782  *
3783  *   1. Take a snapshot of the bit and clear it if needed.
3784  *   2. Write protect the corresponding page.
3785  *   3. Copy the snapshot to the userspace.
3786  *   4. Flush TLB's if needed.
3787  */
3788 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3789 {
3790         bool is_dirty = false;
3791         int r;
3792
3793         mutex_lock(&kvm->slots_lock);
3794
3795         /*
3796          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3797          */
3798         if (kvm_x86_ops->flush_log_dirty)
3799                 kvm_x86_ops->flush_log_dirty(kvm);
3800
3801         r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
3802
3803         /*
3804          * All the TLBs can be flushed out of mmu lock, see the comments in
3805          * kvm_mmu_slot_remove_write_access().
3806          */
3807         lockdep_assert_held(&kvm->slots_lock);
3808         if (is_dirty)
3809                 kvm_flush_remote_tlbs(kvm);
3810
3811         mutex_unlock(&kvm->slots_lock);
3812         return r;
3813 }
3814
3815 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3816                         bool line_status)
3817 {
3818         if (!irqchip_in_kernel(kvm))
3819                 return -ENXIO;
3820
3821         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3822                                         irq_event->irq, irq_event->level,
3823                                         line_status);
3824         return 0;
3825 }
3826
3827 long kvm_arch_vm_ioctl(struct file *filp,
3828                        unsigned int ioctl, unsigned long arg)
3829 {
3830         struct kvm *kvm = filp->private_data;
3831         void __user *argp = (void __user *)arg;
3832         int r = -ENOTTY;
3833         /*
3834          * This union makes it completely explicit to gcc-3.x
3835          * that these two variables' stack usage should be
3836          * combined, not added together.