arch/x86/kvm/x86.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * derived from drivers/kvm/kvm_main.c
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright (C) 2008 Qumranet, Inc.
   9  * Copyright IBM Corporation, 2008
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *   Yaniv Kamay  <yaniv@qumranet.com>
  15  *   Amit Shah    <amit.shah@qumranet.com>
  16  *   Ben-Ami Yassour <benami@il.ibm.com>
  17  */
  18
  19 #include <linux/kvm_host.h>
  20 #include "irq.h"
  21 #include "mmu.h"
  22 #include "i8254.h"
  23 #include "tss.h"
  24 #include "kvm_cache_regs.h"
  25 #include "kvm_emulate.h"
  26 #include "x86.h"
  27 #include "cpuid.h"
  28 #include "pmu.h"
  29 #include "hyperv.h"
  30 #include "lapic.h"
  31
  32 #include <linux/clocksource.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/kvm.h>
  35 #include <linux/fs.h>
  36 #include <linux/vmalloc.h>
  37 #include <linux/export.h>
  38 #include <linux/moduleparam.h>
  39 #include <linux/mman.h>
  40 #include <linux/highmem.h>
  41 #include <linux/iommu.h>
  42 #include <linux/intel-iommu.h>
  43 #include <linux/cpufreq.h>
  44 #include <linux/user-return-notifier.h>
  45 #include <linux/srcu.h>
  46 #include <linux/slab.h>
  47 #include <linux/perf_event.h>
  48 #include <linux/uaccess.h>
  49 #include <linux/hash.h>
  50 #include <linux/pci.h>
  51 #include <linux/timekeeper_internal.h>
  52 #include <linux/pvclock_gtod.h>
  53 #include <linux/kvm_irqfd.h>
  54 #include <linux/irqbypass.h>
  55 #include <linux/sched/stat.h>
  56 #include <linux/sched/isolation.h>
  57 #include <linux/mem_encrypt.h>
  58
  59 #include <trace/events/kvm.h>
  60
  61 #include <asm/debugreg.h>
  62 #include <asm/msr.h>
  63 #include <asm/desc.h>
  64 #include <asm/mce.h>
  65 #include <linux/kernel_stat.h>
  66 #include <asm/fpu/internal.h> /* Ugh! */
  67 #include <asm/pvclock.h>
  68 #include <asm/div64.h>
  69 #include <asm/irq_remapping.h>
  70 #include <asm/mshyperv.h>
  71 #include <asm/hypervisor.h>
  72 #include <asm/intel_pt.h>
  73 #include <asm/emulate_prefix.h>
  74 #include <clocksource/hyperv_timer.h>
  75
  76 #define CREATE_TRACE_POINTS
  77 #include "trace.h"
  78
  79 #define MAX_IO_MSRS 256
  80 #define KVM_MAX_MCE_BANKS 32
  81 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
  82 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
  83
  84 #define emul_to_vcpu(ctxt) \
  85         ((struct kvm_vcpu *)(ctxt)->vcpu)
  86
  87 /* EFER defaults:
  88  * - enable syscall per default because its emulated by KVM
  89  * - enable LME and LMA per default on 64 bit KVM
  90  */
  91 #ifdef CONFIG_X86_64
  92 static
  93 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  94 #else
  95 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  96 #endif
  97
  98 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
  99
 100 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
 101 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
 102
 103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
 104                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
 105
 106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
 107 static void process_nmi(struct kvm_vcpu *vcpu);
 108 static void enter_smm(struct kvm_vcpu *vcpu);
 109 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 110 static void store_regs(struct kvm_vcpu *vcpu);
 111 static int sync_regs(struct kvm_vcpu *vcpu);
 112
 113 struct kvm_x86_ops kvm_x86_ops __read_mostly;
 114 EXPORT_SYMBOL_GPL(kvm_x86_ops);
 115
 116 static bool __read_mostly ignore_msrs = 0;
 117 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
 118
 119 static bool __read_mostly report_ignored_msrs = true;
 120 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
 121
 122 unsigned int min_timer_period_us = 200;
 123 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 124
 125 static bool __read_mostly kvmclock_periodic_sync = true;
 126 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
 127
 128 bool __read_mostly kvm_has_tsc_control;
 129 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 130 u32  __read_mostly kvm_max_guest_tsc_khz;
 131 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 132 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
 133 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
 134 u64  __read_mostly kvm_max_tsc_scaling_ratio;
 135 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
 136 u64 __read_mostly kvm_default_tsc_scaling_ratio;
 137 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
 138
 139 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 140 static u32 __read_mostly tsc_tolerance_ppm = 250;
 141 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 142
 143 /*
 144  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
 145  * adaptive tuning starting from default advancment of 1000ns.  '0' disables
 146  * advancement entirely.  Any other value is used as-is and disables adaptive
 147  * tuning, i.e. allows priveleged userspace to set an exact advancement time.
 148  */
 149 static int __read_mostly lapic_timer_advance_ns = -1;
 150 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
 151
 152 static bool __read_mostly vector_hashing = true;
 153 module_param(vector_hashing, bool, S_IRUGO);
 154
 155 bool __read_mostly enable_vmware_backdoor = false;
 156 module_param(enable_vmware_backdoor, bool, S_IRUGO);
 157 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
 158
 159 static bool __read_mostly force_emulation_prefix = false;
 160 module_param(force_emulation_prefix, bool, S_IRUGO);
 161
 162 int __read_mostly pi_inject_timer = -1;
 163 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
 164
 165 #define KVM_NR_SHARED_MSRS 16
 166
 167 struct kvm_shared_msrs_global {
 168         int nr;
 169         u32 msrs[KVM_NR_SHARED_MSRS];
 170 };
 171
 172 struct kvm_shared_msrs {
 173         struct user_return_notifier urn;
 174         bool registered;
 175         struct kvm_shared_msr_values {
 176                 u64 host;
 177                 u64 curr;
 178         } values[KVM_NR_SHARED_MSRS];
 179 };
 180
 181 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 182 static struct kvm_shared_msrs __percpu *shared_msrs;
 183
 184 #define KVM_SUPPORTED_XCR0     (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
 185                                 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
 186                                 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
 187                                 | XFEATURE_MASK_PKRU)
 188
 189 u64 __read_mostly host_efer;
 190 EXPORT_SYMBOL_GPL(host_efer);
 191
 192 static u64 __read_mostly host_xss;
 193 u64 __read_mostly supported_xss;
 194 EXPORT_SYMBOL_GPL(supported_xss);
 195
 196 struct kvm_stats_debugfs_item debugfs_entries[] = {
 197         { "pf_fixed", VCPU_STAT(pf_fixed) },
 198         { "pf_guest", VCPU_STAT(pf_guest) },
 199         { "tlb_flush", VCPU_STAT(tlb_flush) },
 200         { "invlpg", VCPU_STAT(invlpg) },
 201         { "exits", VCPU_STAT(exits) },
 202         { "io_exits", VCPU_STAT(io_exits) },
 203         { "mmio_exits", VCPU_STAT(mmio_exits) },
 204         { "signal_exits", VCPU_STAT(signal_exits) },
 205         { "irq_window", VCPU_STAT(irq_window_exits) },
 206         { "nmi_window", VCPU_STAT(nmi_window_exits) },
 207         { "halt_exits", VCPU_STAT(halt_exits) },
 208         { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
 209         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
 210         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
 211         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
 212         { "hypercalls", VCPU_STAT(hypercalls) },
 213         { "request_irq", VCPU_STAT(request_irq_exits) },
 214         { "irq_exits", VCPU_STAT(irq_exits) },
 215         { "host_state_reload", VCPU_STAT(host_state_reload) },
 216         { "fpu_reload", VCPU_STAT(fpu_reload) },
 217         { "insn_emulation", VCPU_STAT(insn_emulation) },
 218         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
 219         { "irq_injections", VCPU_STAT(irq_injections) },
 220         { "nmi_injections", VCPU_STAT(nmi_injections) },
 221         { "req_event", VCPU_STAT(req_event) },
 222         { "l1d_flush", VCPU_STAT(l1d_flush) },
 223         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
 224         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
 225         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
 226         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
 227         { "mmu_flooded", VM_STAT(mmu_flooded) },
 228         { "mmu_recycled", VM_STAT(mmu_recycled) },
 229         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
 230         { "mmu_unsync", VM_STAT(mmu_unsync) },
 231         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
 232         { "largepages", VM_STAT(lpages, .mode = 0444) },
 233         { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) },
 234         { "max_mmu_page_hash_collisions",
 235                 VM_STAT(max_mmu_page_hash_collisions) },
 236         { NULL }
 237 };
 238
 239 u64 __read_mostly host_xcr0;
 240 u64 __read_mostly supported_xcr0;
 241 EXPORT_SYMBOL_GPL(supported_xcr0);
 242
 243 struct kmem_cache *x86_fpu_cache;
 244 EXPORT_SYMBOL_GPL(x86_fpu_cache);
 245
 246 static struct kmem_cache *x86_emulator_cache;
 247
 248 static struct kmem_cache *kvm_alloc_emulator_cache(void)
 249 {
 250         unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
 251         unsigned int size = sizeof(struct x86_emulate_ctxt);
 252
 253         return kmem_cache_create_usercopy("x86_emulator", size,
 254                                           __alignof__(struct x86_emulate_ctxt),
 255                                           SLAB_ACCOUNT, useroffset,
 256                                           size - useroffset, NULL);
 257 }
 258
 259 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 260
 261 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 262 {
 263         int i;
 264         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
 265                 vcpu->arch.apf.gfns[i] = ~0;
 266 }
 267
 268 static void kvm_on_user_return(struct user_return_notifier *urn)
 269 {
 270         unsigned slot;
 271         struct kvm_shared_msrs *locals
 272                 = container_of(urn, struct kvm_shared_msrs, urn);
 273         struct kvm_shared_msr_values *values;
 274         unsigned long flags;
 275
 276         /*
 277          * Disabling irqs at this point since the following code could be
 278          * interrupted and executed through kvm_arch_hardware_disable()
 279          */
 280         local_irq_save(flags);
 281         if (locals->registered) {
 282                 locals->registered = false;
 283                 user_return_notifier_unregister(urn);
 284         }
 285         local_irq_restore(flags);
 286         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 287                 values = &locals->values[slot];
 288                 if (values->host != values->curr) {
 289                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 290                         values->curr = values->host;
 291                 }
 292         }
 293 }
 294
 295 void kvm_define_shared_msr(unsigned slot, u32 msr)
 296 {
 297         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
 298         shared_msrs_global.msrs[slot] = msr;
 299         if (slot >= shared_msrs_global.nr)
 300                 shared_msrs_global.nr = slot + 1;
 301 }
 302 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 303
 304 static void kvm_shared_msr_cpu_online(void)
 305 {
 306         unsigned int cpu = smp_processor_id();
 307         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 308         u64 value;
 309         int i;
 310
 311         for (i = 0; i < shared_msrs_global.nr; ++i) {
 312                 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
 313                 smsr->values[i].host = value;
 314                 smsr->values[i].curr = value;
 315         }
 316 }
 317
 318 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 319 {
 320         unsigned int cpu = smp_processor_id();
 321         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 322         int err;
 323
 324         value = (value & mask) | (smsr->values[slot].host & ~mask);
 325         if (value == smsr->values[slot].curr)
 326                 return 0;
 327         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
 328         if (err)
 329                 return 1;
 330
 331         smsr->values[slot].curr = value;
 332         if (!smsr->registered) {
 333                 smsr->urn.on_user_return = kvm_on_user_return;
 334                 user_return_notifier_register(&smsr->urn);
 335                 smsr->registered = true;
 336         }
 337         return 0;
 338 }
 339 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 340
 341 static void drop_user_return_notifiers(void)
 342 {
 343         unsigned int cpu = smp_processor_id();
 344         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 345
 346         if (smsr->registered)
 347                 kvm_on_user_return(&smsr->urn);
 348 }
 349
 350 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 351 {
 352         return vcpu->arch.apic_base;
 353 }
 354 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 355
 356 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
 357 {
 358         return kvm_apic_mode(kvm_get_apic_base(vcpu));
 359 }
 360 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
 361
 362 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 363 {
 364         enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
 365         enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
 366         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
 367                 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
 368
 369         if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
 370                 return 1;
 371         if (!msr_info->host_initiated) {
 372                 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
 373                         return 1;
 374                 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
 375                         return 1;
 376         }
 377
 378         kvm_lapic_set_base(vcpu, msr_info->data);
 379         kvm_recalculate_apic_map(vcpu->kvm);
 380         return 0;
 381 }
 382 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 383
 384 asmlinkage __visible void kvm_spurious_fault(void)
 385 {
 386         /* Fault while not rebooting.  We want the trace. */
 387         BUG_ON(!kvm_rebooting);
 388 }
 389 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 390
 391 #define EXCPT_BENIGN            0
 392 #define EXCPT_CONTRIBUTORY      1
 393 #define EXCPT_PF                2
 394
 395 static int exception_class(int vector)
 396 {
 397         switch (vector) {
 398         case PF_VECTOR:
 399                 return EXCPT_PF;
 400         case DE_VECTOR:
 401         case TS_VECTOR:
 402         case NP_VECTOR:
 403         case SS_VECTOR:
 404         case GP_VECTOR:
 405                 return EXCPT_CONTRIBUTORY;
 406         default:
 407                 break;
 408         }
 409         return EXCPT_BENIGN;
 410 }
 411
 412 #define EXCPT_FAULT             0
 413 #define EXCPT_TRAP              1
 414 #define EXCPT_ABORT             2
 415 #define EXCPT_INTERRUPT         3
 416
 417 static int exception_type(int vector)
 418 {
 419         unsigned int mask;
 420
 421         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
 422                 return EXCPT_INTERRUPT;
 423
 424         mask = 1 << vector;
 425
 426         /* #DB is trap, as instruction watchpoints are handled elsewhere */
 427         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
 428                 return EXCPT_TRAP;
 429
 430         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
 431                 return EXCPT_ABORT;
 432
 433         /* Reserved exceptions will result in fault */
 434         return EXCPT_FAULT;
 435 }
 436
 437 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
 438 {
 439         unsigned nr = vcpu->arch.exception.nr;
 440         bool has_payload = vcpu->arch.exception.has_payload;
 441         unsigned long payload = vcpu->arch.exception.payload;
 442
 443         if (!has_payload)
 444                 return;
 445
 446         switch (nr) {
 447         case DB_VECTOR:
 448                 /*
 449                  * "Certain debug exceptions may clear bit 0-3.  The
 450                  * remaining contents of the DR6 register are never
 451                  * cleared by the processor".
 452                  */
 453                 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
 454                 /*
 455                  * DR6.RTM is set by all #DB exceptions that don't clear it.
 456                  */
 457                 vcpu->arch.dr6 |= DR6_RTM;
 458                 vcpu->arch.dr6 |= payload;
 459                 /*
 460                  * Bit 16 should be set in the payload whenever the #DB
 461                  * exception should clear DR6.RTM. This makes the payload
 462                  * compatible with the pending debug exceptions under VMX.
 463                  * Though not currently documented in the SDM, this also
 464                  * makes the payload compatible with the exit qualification
 465                  * for #DB exceptions under VMX.
 466                  */
 467                 vcpu->arch.dr6 ^= payload & DR6_RTM;
 468
 469                 /*
 470                  * The #DB payload is defined as compatible with the 'pending
 471                  * debug exceptions' field under VMX, not DR6. While bit 12 is
 472                  * defined in the 'pending debug exceptions' field (enabled
 473                  * breakpoint), it is reserved and must be zero in DR6.
 474                  */
 475                 vcpu->arch.dr6 &= ~BIT(12);
 476                 break;
 477         case PF_VECTOR:
 478                 vcpu->arch.cr2 = payload;
 479                 break;
 480         }
 481
 482         vcpu->arch.exception.has_payload = false;
 483         vcpu->arch.exception.payload = 0;
 484 }
 485 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
 486
 487 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 488                 unsigned nr, bool has_error, u32 error_code,
 489                 bool has_payload, unsigned long payload, bool reinject)
 490 {
 491         u32 prev_nr;
 492         int class1, class2;
 493
 494         kvm_make_request(KVM_REQ_EVENT, vcpu);
 495
 496         if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
 497         queue:
 498                 if (has_error && !is_protmode(vcpu))
 499                         has_error = false;
 500                 if (reinject) {
 501                         /*
 502                          * On vmentry, vcpu->arch.exception.pending is only
 503                          * true if an event injection was blocked by
 504                          * nested_run_pending.  In that case, however,
 505                          * vcpu_enter_guest requests an immediate exit,
 506                          * and the guest shouldn't proceed far enough to
 507                          * need reinjection.
 508                          */
 509                         WARN_ON_ONCE(vcpu->arch.exception.pending);
 510                         vcpu->arch.exception.injected = true;
 511                         if (WARN_ON_ONCE(has_payload)) {
 512                                 /*
 513                                  * A reinjected event has already
 514                                  * delivered its payload.
 515                                  */
 516                                 has_payload = false;
 517                                 payload = 0;
 518                         }
 519                 } else {
 520                         vcpu->arch.exception.pending = true;
 521                         vcpu->arch.exception.injected = false;
 522                 }
 523                 vcpu->arch.exception.has_error_code = has_error;
 524                 vcpu->arch.exception.nr = nr;
 525                 vcpu->arch.exception.error_code = error_code;
 526                 vcpu->arch.exception.has_payload = has_payload;
 527                 vcpu->arch.exception.payload = payload;
 528                 if (!is_guest_mode(vcpu))
 529                         kvm_deliver_exception_payload(vcpu);
 530                 return;
 531         }
 532
 533         /* to check exception */
 534         prev_nr = vcpu->arch.exception.nr;
 535         if (prev_nr == DF_VECTOR) {
 536                 /* triple fault -> shutdown */
 537                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 538                 return;
 539         }
 540         class1 = exception_class(prev_nr);
 541         class2 = exception_class(nr);
 542         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 543                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 544                 /*
 545                  * Generate double fault per SDM Table 5-5.  Set
 546                  * exception.pending = true so that the double fault
 547                  * can trigger a nested vmexit.
 548                  */
 549                 vcpu->arch.exception.pending = true;
 550                 vcpu->arch.exception.injected = false;
 551                 vcpu->arch.exception.has_error_code = true;
 552                 vcpu->arch.exception.nr = DF_VECTOR;
 553                 vcpu->arch.exception.error_code = 0;
 554                 vcpu->arch.exception.has_payload = false;
 555                 vcpu->arch.exception.payload = 0;
 556         } else
 557                 /* replace previous exception with a new one in a hope
 558                    that instruction re-execution will regenerate lost
 559                    exception */
 560                 goto queue;
 561 }
 562
 563 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 564 {
 565         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
 566 }
 567 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 568
 569 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 570 {
 571         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
 572 }
 573 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 574
 575 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
 576                            unsigned long payload)
 577 {
 578         kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
 579 }
 580 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
 581
 582 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
 583                                     u32 error_code, unsigned long payload)
 584 {
 585         kvm_multiple_exception(vcpu, nr, true, error_code,
 586                                true, payload, false);
 587 }
 588
 589 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 590 {
 591         if (err)
 592                 kvm_inject_gp(vcpu, 0);
 593         else
 594                 return kvm_skip_emulated_instruction(vcpu);
 595
 596         return 1;
 597 }
 598 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 599
 600 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 601 {
 602         ++vcpu->stat.pf_guest;
 603         vcpu->arch.exception.nested_apf =
 604                 is_guest_mode(vcpu) && fault->async_page_fault;
 605         if (vcpu->arch.exception.nested_apf) {
 606                 vcpu->arch.apf.nested_apf_token = fault->address;
 607                 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 608         } else {
 609                 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
 610                                         fault->address);
 611         }
 612 }
 613 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 614
 615 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 616 {
 617         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
 618                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
 619         else
 620                 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
 621
 622         return fault->nested_page_fault;
 623 }
 624
 625 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 626 {
 627         atomic_inc(&vcpu->arch.nmi_queued);
 628         kvm_make_request(KVM_REQ_NMI, vcpu);
 629 }
 630 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 631
 632 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 633 {
 634         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
 635 }
 636 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 637
 638 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 639 {
 640         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
 641 }
 642 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 643
 644 /*
 645  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 646  * a #GP and return false.
 647  */
 648 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 649 {
 650         if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
 651                 return true;
 652         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 653         return false;
 654 }
 655 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 656
 657 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
 658 {
 659         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 660                 return true;
 661
 662         kvm_queue_exception(vcpu, UD_VECTOR);
 663         return false;
 664 }
 665 EXPORT_SYMBOL_GPL(kvm_require_dr);
 666
 667 /*
 668  * This function will be used to read from the physical memory of the currently
 669  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
 670  * can read from guest physical or from the guest's guest physical memory.
 671  */
 672 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 673                             gfn_t ngfn, void *data, int offset, int len,
 674                             u32 access)
 675 {
 676         struct x86_exception exception;
 677         gfn_t real_gfn;
 678         gpa_t ngpa;
 679
 680         ngpa     = gfn_to_gpa(ngfn);
 681         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
 682         if (real_gfn == UNMAPPED_GVA)
 683                 return -EFAULT;
 684
 685         real_gfn = gpa_to_gfn(real_gfn);
 686
 687         return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
 688 }
 689 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 690
 691 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 692                                void *data, int offset, int len, u32 access)
 693 {
 694         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 695                                        data, offset, len, access);
 696 }
 697
 698 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
 699 {
 700         return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
 701                rsvd_bits(1, 2);
 702 }
 703
 704 /*
 705  * Load the pae pdptrs.  Return 1 if they are all valid, 0 otherwise.
 706  */
 707 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 708 {
 709         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 710         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 711         int i;
 712         int ret;
 713         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 714
 715         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 716                                       offset * sizeof(u64), sizeof(pdpte),
 717                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 718         if (ret < 0) {
 719                 ret = 0;
 720                 goto out;
 721         }
 722         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 723                 if ((pdpte[i] & PT_PRESENT_MASK) &&
 724                     (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
 725                         ret = 0;
 726                         goto out;
 727                 }
 728         }
 729         ret = 1;
 730
 731         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 732         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
 733
 734 out:
 735
 736         return ret;
 737 }
 738 EXPORT_SYMBOL_GPL(load_pdptrs);
 739
 740 bool pdptrs_changed(struct kvm_vcpu *vcpu)
 741 {
 742         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 743         int offset;
 744         gfn_t gfn;
 745         int r;
 746
 747         if (!is_pae_paging(vcpu))
 748                 return false;
 749
 750         if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
 751                 return true;
 752
 753         gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
 754         offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
 755         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 756                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 757         if (r < 0)
 758                 return true;
 759
 760         return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 761 }
 762 EXPORT_SYMBOL_GPL(pdptrs_changed);
 763
 764 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 765 {
 766         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 767         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
 768
 769         cr0 |= X86_CR0_ET;
 770
 771 #ifdef CONFIG_X86_64
 772         if (cr0 & 0xffffffff00000000UL)
 773                 return 1;
 774 #endif
 775
 776         cr0 &= ~CR0_RESERVED_BITS;
 777
 778         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 779                 return 1;
 780
 781         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 782                 return 1;
 783
 784         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 785 #ifdef CONFIG_X86_64
 786                 if ((vcpu->arch.efer & EFER_LME)) {
 787                         int cs_db, cs_l;
 788
 789                         if (!is_pae(vcpu))
 790                                 return 1;
 791                         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 792                         if (cs_l)
 793                                 return 1;
 794                 } else
 795 #endif
 796                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 797                                                  kvm_read_cr3(vcpu)))
 798                         return 1;
 799         }
 800
 801         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 802                 return 1;
 803
 804         kvm_x86_ops.set_cr0(vcpu, cr0);
 805
 806         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 807                 kvm_clear_async_pf_completion_queue(vcpu);
 808                 kvm_async_pf_hash_reset(vcpu);
 809         }
 810
 811         if ((cr0 ^ old_cr0) & update_bits)
 812                 kvm_mmu_reset_context(vcpu);
 813
 814         if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
 815             kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
 816             !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
 817                 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
 818
 819         return 0;
 820 }
 821 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 822
 823 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 824 {
 825         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 826 }
 827 EXPORT_SYMBOL_GPL(kvm_lmsw);
 828
 829 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
 830 {
 831         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 832
 833                 if (vcpu->arch.xcr0 != host_xcr0)
 834                         xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 835
 836                 if (vcpu->arch.xsaves_enabled &&
 837                     vcpu->arch.ia32_xss != host_xss)
 838                         wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
 839         }
 840 }
 841 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
 842
 843 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
 844 {
 845         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 846
 847                 if (vcpu->arch.xcr0 != host_xcr0)
 848                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 849
 850                 if (vcpu->arch.xsaves_enabled &&
 851                     vcpu->arch.ia32_xss != host_xss)
 852                         wrmsrl(MSR_IA32_XSS, host_xss);
 853         }
 854
 855 }
 856 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
 857
 858 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 859 {
 860         u64 xcr0 = xcr;
 861         u64 old_xcr0 = vcpu->arch.xcr0;
 862         u64 valid_bits;
 863
 864         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 865         if (index != XCR_XFEATURE_ENABLED_MASK)
 866                 return 1;
 867         if (!(xcr0 & XFEATURE_MASK_FP))
 868                 return 1;
 869         if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
 870                 return 1;
 871
 872         /*
 873          * Do not allow the guest to set bits that we do not support
 874          * saving.  However, xcr0 bit 0 is always set, even if the
 875          * emulated CPU does not support XSAVE (see fx_init).
 876          */
 877         valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
 878         if (xcr0 & ~valid_bits)
 879                 return 1;
 880
 881         if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
 882             (!(xcr0 & XFEATURE_MASK_BNDCSR)))
 883                 return 1;
 884
 885         if (xcr0 & XFEATURE_MASK_AVX512) {
 886                 if (!(xcr0 & XFEATURE_MASK_YMM))
 887                         return 1;
 888                 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
 889                         return 1;
 890         }
 891         vcpu->arch.xcr0 = xcr0;
 892
 893         if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
 894                 kvm_update_cpuid(vcpu);
 895         return 0;
 896 }
 897
 898 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 899 {
 900         if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
 901             __kvm_set_xcr(vcpu, index, xcr)) {
 902                 kvm_inject_gp(vcpu, 0);
 903                 return 1;
 904         }
 905         return 0;
 906 }
 907 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 908
 909 #define __cr4_reserved_bits(__cpu_has, __c)             \
 910 ({                                                      \
 911         u64 __reserved_bits = CR4_RESERVED_BITS;        \
 912                                                         \
 913         if (!__cpu_has(__c, X86_FEATURE_XSAVE))         \
 914                 __reserved_bits |= X86_CR4_OSXSAVE;     \
 915         if (!__cpu_has(__c, X86_FEATURE_SMEP))          \
 916                 __reserved_bits |= X86_CR4_SMEP;        \
 917         if (!__cpu_has(__c, X86_FEATURE_SMAP))          \
 918                 __reserved_bits |= X86_CR4_SMAP;        \
 919         if (!__cpu_has(__c, X86_FEATURE_FSGSBASE))      \
 920                 __reserved_bits |= X86_CR4_FSGSBASE;    \
 921         if (!__cpu_has(__c, X86_FEATURE_PKU))           \
 922                 __reserved_bits |= X86_CR4_PKE;         \
 923         if (!__cpu_has(__c, X86_FEATURE_LA57))          \
 924                 __reserved_bits |= X86_CR4_LA57;        \
 925         if (!__cpu_has(__c, X86_FEATURE_UMIP))          \
 926                 __reserved_bits |= X86_CR4_UMIP;        \
 927         __reserved_bits;                                \
 928 })
 929
 930 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 931 {
 932         if (cr4 & cr4_reserved_bits)
 933                 return -EINVAL;
 934
 935         if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
 936                 return -EINVAL;
 937
 938         return 0;
 939 }
 940
 941 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 942 {
 943         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 944         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
 945                                    X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
 946
 947         if (kvm_valid_cr4(vcpu, cr4))
 948                 return 1;
 949
 950         if (is_long_mode(vcpu)) {
 951                 if (!(cr4 & X86_CR4_PAE))
 952                         return 1;
 953         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 954                    && ((cr4 ^ old_cr4) & pdptr_bits)
 955                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 956                                    kvm_read_cr3(vcpu)))
 957                 return 1;
 958
 959         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
 960                 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
 961                         return 1;
 962
 963                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
 964                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
 965                         return 1;
 966         }
 967
 968         if (kvm_x86_ops.set_cr4(vcpu, cr4))
 969                 return 1;
 970
 971         if (((cr4 ^ old_cr4) & pdptr_bits) ||
 972             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
 973                 kvm_mmu_reset_context(vcpu);
 974
 975         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
 976                 kvm_update_cpuid(vcpu);
 977
 978         return 0;
 979 }
 980 EXPORT_SYMBOL_GPL(kvm_set_cr4);
 981
 982 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 983 {
 984         bool skip_tlb_flush = false;
 985 #ifdef CONFIG_X86_64
 986         bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
 987
 988         if (pcid_enabled) {
 989                 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
 990                 cr3 &= ~X86_CR3_PCID_NOFLUSH;
 991         }
 992 #endif
 993
 994         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
 995                 if (!skip_tlb_flush) {
 996                         kvm_mmu_sync_roots(vcpu);
 997                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 998                 }
 999                 return 0;
1000         }
1001
1002         if (is_long_mode(vcpu) &&
1003             (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
1004                 return 1;
1005         else if (is_pae_paging(vcpu) &&
1006                  !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1007                 return 1;
1008
1009         kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
1010         vcpu->arch.cr3 = cr3;
1011         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1012
1013         return 0;
1014 }
1015 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1016
1017 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1018 {
1019         if (cr8 & CR8_RESERVED_BITS)
1020                 return 1;
1021         if (lapic_in_kernel(vcpu))
1022                 kvm_lapic_set_tpr(vcpu, cr8);
1023         else
1024                 vcpu->arch.cr8 = cr8;
1025         return 0;
1026 }
1027 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1028
1029 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1030 {
1031         if (lapic_in_kernel(vcpu))
1032                 return kvm_lapic_get_cr8(vcpu);
1033         else
1034                 return vcpu->arch.cr8;
1035 }
1036 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1037
1038 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1039 {
1040         int i;
1041
1042         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1043                 for (i = 0; i < KVM_NR_DB_REGS; i++)
1044                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1045                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1046         }
1047 }
1048
1049 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1050 {
1051         unsigned long dr7;
1052
1053         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1054                 dr7 = vcpu->arch.guest_debug_dr7;
1055         else
1056                 dr7 = vcpu->arch.dr7;
1057         kvm_x86_ops.set_dr7(vcpu, dr7);
1058         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1059         if (dr7 & DR7_BP_EN_MASK)
1060                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1061 }
1062
1063 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1064 {
1065         u64 fixed = DR6_FIXED_1;
1066
1067         if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1068                 fixed |= DR6_RTM;
1069         return fixed;
1070 }
1071
1072 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1073 {
1074         size_t size = ARRAY_SIZE(vcpu->arch.db);
1075
1076         switch (dr) {
1077         case 0 ... 3:
1078                 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1079                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1080                         vcpu->arch.eff_db[dr] = val;
1081                 break;
1082         case 4:
1083                 /* fall through */
1084         case 6:
1085                 if (val & 0xffffffff00000000ULL)
1086                         return -1; /* #GP */
1087                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1088                 break;
1089         case 5:
1090                 /* fall through */
1091         default: /* 7 */
1092                 if (!kvm_dr7_valid(val))
1093                         return -1; /* #GP */
1094                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1095                 kvm_update_dr7(vcpu);
1096                 break;
1097         }
1098
1099         return 0;
1100 }
1101
1102 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1103 {
1104         if (__kvm_set_dr(vcpu, dr, val)) {
1105                 kvm_inject_gp(vcpu, 0);
1106                 return 1;
1107         }
1108         return 0;
1109 }
1110 EXPORT_SYMBOL_GPL(kvm_set_dr);
1111
1112 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1113 {
1114         size_t size = ARRAY_SIZE(vcpu->arch.db);
1115
1116         switch (dr) {
1117         case 0 ... 3:
1118                 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1119                 break;
1120         case 4:
1121                 /* fall through */
1122         case 6:
1123                 *val = vcpu->arch.dr6;
1124                 break;
1125         case 5:
1126                 /* fall through */
1127         default: /* 7 */
1128                 *val = vcpu->arch.dr7;
1129                 break;
1130         }
1131         return 0;
1132 }
1133 EXPORT_SYMBOL_GPL(kvm_get_dr);
1134
1135 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1136 {
1137         u32 ecx = kvm_rcx_read(vcpu);
1138         u64 data;
1139         int err;
1140
1141         err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1142         if (err)
1143                 return err;
1144         kvm_rax_write(vcpu, (u32)data);
1145         kvm_rdx_write(vcpu, data >> 32);
1146         return err;
1147 }
1148 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1149
1150 /*
1151  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1152  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1153  *
1154  * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1155  * extract the supported MSRs from the related const lists.
1156  * msrs_to_save is selected from the msrs_to_save_all to reflect the
1157  * capabilities of the host cpu. This capabilities test skips MSRs that are
1158  * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1159  * may depend on host virtualization features rather than host cpu features.
1160  */
1161
1162 static const u32 msrs_to_save_all[] = {
1163         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1164         MSR_STAR,
1165 #ifdef CONFIG_X86_64
1166         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1167 #endif
1168         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1169         MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1170         MSR_IA32_SPEC_CTRL,
1171         MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1172         MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1173         MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1174         MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1175         MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1176         MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1177         MSR_IA32_UMWAIT_CONTROL,
1178
1179         MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1180         MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1181         MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1182         MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1183         MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1184         MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1185         MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1186         MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1187         MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1188         MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1189         MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1190         MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1191         MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1192         MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1193         MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1194         MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1195         MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1196         MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1197         MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1198         MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1199         MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1200         MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1201 };
1202
1203 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1204 static unsigned num_msrs_to_save;
1205
1206 static const u32 emulated_msrs_all[] = {
1207         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1208         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1209         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1210         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1211         HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1212         HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1213         HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1214         HV_X64_MSR_RESET,
1215         HV_X64_MSR_VP_INDEX,
1216         HV_X64_MSR_VP_RUNTIME,
1217         HV_X64_MSR_SCONTROL,
1218         HV_X64_MSR_STIMER0_CONFIG,
1219         HV_X64_MSR_VP_ASSIST_PAGE,
1220         HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1221         HV_X64_MSR_TSC_EMULATION_STATUS,
1222
1223         MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1224         MSR_KVM_PV_EOI_EN,
1225
1226         MSR_IA32_TSC_ADJUST,
1227         MSR_IA32_TSCDEADLINE,
1228         MSR_IA32_ARCH_CAPABILITIES,
1229         MSR_IA32_MISC_ENABLE,
1230         MSR_IA32_MCG_STATUS,
1231         MSR_IA32_MCG_CTL,
1232         MSR_IA32_MCG_EXT_CTL,
1233         MSR_IA32_SMBASE,
1234         MSR_SMI_COUNT,
1235         MSR_PLATFORM_INFO,
1236         MSR_MISC_FEATURES_ENABLES,
1237         MSR_AMD64_VIRT_SPEC_CTRL,
1238         MSR_IA32_POWER_CTL,
1239         MSR_IA32_UCODE_REV,
1240
1241         /*
1242          * The following list leaves out MSRs whose values are determined
1243          * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1244          * We always support the "true" VMX control MSRs, even if the host
1245          * processor does not, so I am putting these registers here rather
1246          * than in msrs_to_save_all.
1247          */
1248         MSR_IA32_VMX_BASIC,
1249         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1250         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1251         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1252         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1253         MSR_IA32_VMX_MISC,
1254         MSR_IA32_VMX_CR0_FIXED0,
1255         MSR_IA32_VMX_CR4_FIXED0,
1256         MSR_IA32_VMX_VMCS_ENUM,
1257         MSR_IA32_VMX_PROCBASED_CTLS2,
1258         MSR_IA32_VMX_EPT_VPID_CAP,
1259         MSR_IA32_VMX_VMFUNC,
1260
1261         MSR_K7_HWCR,
1262         MSR_KVM_POLL_CONTROL,
1263 };
1264
1265 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1266 static unsigned num_emulated_msrs;
1267
1268 /*
1269  * List of msr numbers which are used to expose MSR-based features that
1270  * can be used by a hypervisor to validate requested CPU features.
1271  */
1272 static const u32 msr_based_features_all[] = {
1273         MSR_IA32_VMX_BASIC,
1274         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1275         MSR_IA32_VMX_PINBASED_CTLS,
1276         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1277         MSR_IA32_VMX_PROCBASED_CTLS,
1278         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1279         MSR_IA32_VMX_EXIT_CTLS,
1280         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1281         MSR_IA32_VMX_ENTRY_CTLS,
1282         MSR_IA32_VMX_MISC,
1283         MSR_IA32_VMX_CR0_FIXED0,
1284         MSR_IA32_VMX_CR0_FIXED1,
1285         MSR_IA32_VMX_CR4_FIXED0,
1286         MSR_IA32_VMX_CR4_FIXED1,
1287         MSR_IA32_VMX_VMCS_ENUM,
1288         MSR_IA32_VMX_PROCBASED_CTLS2,
1289         MSR_IA32_VMX_EPT_VPID_CAP,
1290         MSR_IA32_VMX_VMFUNC,
1291
1292         MSR_F10H_DECFG,
1293         MSR_IA32_UCODE_REV,
1294         MSR_IA32_ARCH_CAPABILITIES,
1295 };
1296
1297 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1298 static unsigned int num_msr_based_features;
1299
1300 static u64 kvm_get_arch_capabilities(void)
1301 {
1302         u64 data = 0;
1303
1304         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1305                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1306
1307         /*
1308          * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1309          * the nested hypervisor runs with NX huge pages.  If it is not,
1310          * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1311          * L1 guests, so it need not worry about its own (L2) guests.
1312          */
1313         data |= ARCH_CAP_PSCHANGE_MC_NO;
1314
1315         /*
1316          * If we're doing cache flushes (either "always" or "cond")
1317          * we will do one whenever the guest does a vmlaunch/vmresume.
1318          * If an outer hypervisor is doing the cache flush for us
1319          * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1320          * capability to the guest too, and if EPT is disabled we're not
1321          * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1322          * require a nested hypervisor to do a flush of its own.
1323          */
1324         if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1325                 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1326
1327         if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1328                 data |= ARCH_CAP_RDCL_NO;
1329         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1330                 data |= ARCH_CAP_SSB_NO;
1331         if (!boot_cpu_has_bug(X86_BUG_MDS))
1332                 data |= ARCH_CAP_MDS_NO;
1333
1334         /*
1335          * On TAA affected systems:
1336          *      - nothing to do if TSX is disabled on the host.
1337          *      - we emulate TSX_CTRL if present on the host.
1338          *        This lets the guest use VERW to clear CPU buffers.
1339          */
1340         if (!boot_cpu_has(X86_FEATURE_RTM))
1341                 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1342         else if (!boot_cpu_has_bug(X86_BUG_TAA))
1343                 data |= ARCH_CAP_TAA_NO;
1344
1345         return data;
1346 }
1347
1348 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1349 {
1350         switch (msr->index) {
1351         case MSR_IA32_ARCH_CAPABILITIES:
1352                 msr->data = kvm_get_arch_capabilities();
1353                 break;
1354         case MSR_IA32_UCODE_REV:
1355                 rdmsrl_safe(msr->index, &msr->data);
1356                 break;
1357         default:
1358                 if (kvm_x86_ops.get_msr_feature(msr))
1359                         return 1;
1360         }
1361         return 0;
1362 }
1363
1364 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1365 {
1366         struct kvm_msr_entry msr;
1367         int r;
1368
1369         msr.index = index;
1370         r = kvm_get_msr_feature(&msr);
1371         if (r)
1372                 return r;
1373
1374         *data = msr.data;
1375
1376         return 0;
1377 }
1378
1379 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1380 {
1381         if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1382                 return false;
1383
1384         if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1385                 return false;
1386
1387         if (efer & (EFER_LME | EFER_LMA) &&
1388             !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1389                 return false;
1390
1391         if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1392                 return false;
1393
1394         return true;
1395
1396 }
1397 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1398 {
1399         if (efer & efer_reserved_bits)
1400                 return false;
1401
1402         return __kvm_valid_efer(vcpu, efer);
1403 }
1404 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1405
1406 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1407 {
1408         u64 old_efer = vcpu->arch.efer;
1409         u64 efer = msr_info->data;
1410
1411         if (efer & efer_reserved_bits)
1412                 return 1;
1413
1414         if (!msr_info->host_initiated) {
1415                 if (!__kvm_valid_efer(vcpu, efer))
1416                         return 1;
1417
1418                 if (is_paging(vcpu) &&
1419                     (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1420                         return 1;
1421         }
1422
1423         efer &= ~EFER_LMA;
1424         efer |= vcpu->arch.efer & EFER_LMA;
1425
1426         kvm_x86_ops.set_efer(vcpu, efer);
1427
1428         /* Update reserved bits */
1429         if ((efer ^ old_efer) & EFER_NX)
1430                 kvm_mmu_reset_context(vcpu);
1431
1432         return 0;
1433 }
1434
1435 void kvm_enable_efer_bits(u64 mask)
1436 {
1437        efer_reserved_bits &= ~mask;
1438 }
1439 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1440
1441 /*
1442  * Write @data into the MSR specified by @index.  Select MSR specific fault
1443  * checks are bypassed if @host_initiated is %true.
1444  * Returns 0 on success, non-0 otherwise.
1445  * Assumes vcpu_load() was already called.
1446  */
1447 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1448                          bool host_initiated)
1449 {
1450         struct msr_data msr;
1451
1452         switch (index) {
1453         case MSR_FS_BASE:
1454         case MSR_GS_BASE:
1455         case MSR_KERNEL_GS_BASE:
1456         case MSR_CSTAR:
1457         case MSR_LSTAR:
1458                 if (is_noncanonical_address(data, vcpu))
1459                         return 1;
1460                 break;
1461         case MSR_IA32_SYSENTER_EIP:
1462         case MSR_IA32_SYSENTER_ESP:
1463                 /*
1464                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1465                  * non-canonical address is written on Intel but not on
1466                  * AMD (which ignores the top 32-bits, because it does
1467                  * not implement 64-bit SYSENTER).
1468                  *
1469                  * 64-bit code should hence be able to write a non-canonical
1470                  * value on AMD.  Making the address canonical ensures that
1471                  * vmentry does not fail on Intel after writing a non-canonical
1472                  * value, and that something deterministic happens if the guest
1473                  * invokes 64-bit SYSENTER.
1474                  */
1475                 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1476         }
1477
1478         msr.data = data;
1479         msr.index = index;
1480         msr.host_initiated = host_initiated;
1481
1482         return kvm_x86_ops.set_msr(vcpu, &msr);
1483 }
1484
1485 /*
1486  * Read the MSR specified by @index into @data.  Select MSR specific fault
1487  * checks are bypassed if @host_initiated is %true.
1488  * Returns 0 on success, non-0 otherwise.
1489  * Assumes vcpu_load() was already called.
1490  */
1491 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1492                   bool host_initiated)
1493 {
1494         struct msr_data msr;
1495         int ret;
1496
1497         msr.index = index;
1498         msr.host_initiated = host_initiated;
1499
1500         ret = kvm_x86_ops.get_msr(vcpu, &msr);
1501         if (!ret)
1502                 *data = msr.data;
1503         return ret;
1504 }
1505
1506 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1507 {
1508         return __kvm_get_msr(vcpu, index, data, false);
1509 }
1510 EXPORT_SYMBOL_GPL(kvm_get_msr);
1511
1512 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1513 {
1514         return __kvm_set_msr(vcpu, index, data, false);
1515 }
1516 EXPORT_SYMBOL_GPL(kvm_set_msr);
1517
1518 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1519 {
1520         u32 ecx = kvm_rcx_read(vcpu);
1521         u64 data;
1522
1523         if (kvm_get_msr(vcpu, ecx, &data)) {
1524                 trace_kvm_msr_read_ex(ecx);
1525                 kvm_inject_gp(vcpu, 0);
1526                 return 1;
1527         }
1528
1529         trace_kvm_msr_read(ecx, data);
1530
1531         kvm_rax_write(vcpu, data & -1u);
1532         kvm_rdx_write(vcpu, (data >> 32) & -1u);
1533         return kvm_skip_emulated_instruction(vcpu);
1534 }
1535 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1536
1537 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1538 {
1539         u32 ecx = kvm_rcx_read(vcpu);
1540         u64 data = kvm_read_edx_eax(vcpu);
1541
1542         if (kvm_set_msr(vcpu, ecx, data)) {
1543                 trace_kvm_msr_write_ex(ecx, data);
1544                 kvm_inject_gp(vcpu, 0);
1545                 return 1;
1546         }
1547
1548         trace_kvm_msr_write(ecx, data);
1549         return kvm_skip_emulated_instruction(vcpu);
1550 }
1551 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1552
1553 /*
1554  * The fast path for frequent and performance sensitive wrmsr emulation,
1555  * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1556  * the latency of virtual IPI by avoiding the expensive bits of transitioning
1557  * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1558  * other cases which must be called after interrupts are enabled on the host.
1559  */
1560 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1561 {
1562         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1563                 return 1;
1564
1565         if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1566                 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1567                 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1568                 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1569
1570                 data &= ~(1 << 12);
1571                 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1572                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1573                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1574                 trace_kvm_apic_write(APIC_ICR, (u32)data);
1575                 return 0;
1576         }
1577
1578         return 1;
1579 }
1580
1581 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1582 {
1583         u32 msr = kvm_rcx_read(vcpu);
1584         u64 data;
1585         int ret = 0;
1586
1587         switch (msr) {
1588         case APIC_BASE_MSR + (APIC_ICR >> 4):
1589                 data = kvm_read_edx_eax(vcpu);
1590                 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data);
1591                 break;
1592         default:
1593                 return EXIT_FASTPATH_NONE;
1594         }
1595
1596         if (!ret) {
1597                 trace_kvm_msr_write(msr, data);
1598                 return EXIT_FASTPATH_SKIP_EMUL_INS;
1599         }
1600
1601         return EXIT_FASTPATH_NONE;
1602 }
1603 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1604
1605 /*
1606  * Adapt set_msr() to msr_io()'s calling convention
1607  */
1608 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1609 {
1610         return __kvm_get_msr(vcpu, index, data, true);
1611 }
1612
1613 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1614 {
1615         return __kvm_set_msr(vcpu, index, *data, true);
1616 }
1617
1618 #ifdef CONFIG_X86_64
1619 struct pvclock_clock {
1620         int vclock_mode;
1621         u64 cycle_last;
1622         u64 mask;
1623         u32 mult;
1624         u32 shift;
1625         u64 base_cycles;
1626         u64 offset;
1627 };
1628
1629 struct pvclock_gtod_data {
1630         seqcount_t      seq;
1631
1632         struct pvclock_clock clock; /* extract of a clocksource struct */
1633         struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1634
1635         ktime_t         offs_boot;
1636         u64             wall_time_sec;
1637 };
1638
1639 static struct pvclock_gtod_data pvclock_gtod_data;
1640
1641 static void update_pvclock_gtod(struct timekeeper *tk)
1642 {
1643         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1644
1645         write_seqcount_begin(&vdata->seq);
1646
1647         /* copy pvclock gtod data */
1648         vdata->clock.vclock_mode        = tk->tkr_mono.clock->vdso_clock_mode;
1649         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1650         vdata->clock.mask               = tk->tkr_mono.mask;
1651         vdata->clock.mult               = tk->tkr_mono.mult;
1652         vdata->clock.shift              = tk->tkr_mono.shift;
1653         vdata->clock.base_cycles        = tk->tkr_mono.xtime_nsec;
1654         vdata->clock.offset             = tk->tkr_mono.base;
1655
1656         vdata->raw_clock.vclock_mode    = tk->tkr_raw.clock->vdso_clock_mode;
1657         vdata->raw_clock.cycle_last     = tk->tkr_raw.cycle_last;
1658         vdata->raw_clock.mask           = tk->tkr_raw.mask;
1659         vdata->raw_clock.mult           = tk->tkr_raw.mult;
1660         vdata->raw_clock.shift          = tk->tkr_raw.shift;
1661         vdata->raw_clock.base_cycles    = tk->tkr_raw.xtime_nsec;
1662         vdata->raw_clock.offset         = tk->tkr_raw.base;
1663
1664         vdata->wall_time_sec            = tk->xtime_sec;
1665
1666         vdata->offs_boot                = tk->offs_boot;
1667
1668         write_seqcount_end(&vdata->seq);
1669 }
1670
1671 static s64 get_kvmclock_base_ns(void)
1672 {
1673         /* Count up from boot time, but with the frequency of the raw clock.  */
1674         return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1675 }
1676 #else
1677 static s64 get_kvmclock_base_ns(void)
1678 {
1679         /* Master clock not used, so we can just use CLOCK_BOOTTIME.  */
1680         return ktime_get_boottime_ns();
1681 }
1682 #endif
1683
1684 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1685 {
1686         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1687         kvm_vcpu_kick(vcpu);
1688 }
1689
1690 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1691 {
1692         int version;
1693         int r;
1694         struct pvclock_wall_clock wc;
1695         u64 wall_nsec;
1696
1697         if (!wall_clock)
1698                 return;
1699
1700         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1701         if (r)
1702                 return;
1703
1704         if (version & 1)
1705                 ++version;  /* first time write, random junk */
1706
1707         ++version;
1708
1709         if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1710                 return;
1711
1712         /*
1713          * The guest calculates current wall clock time by adding
1714          * system time (updated by kvm_guest_time_update below) to the
1715          * wall clock specified here.  We do the reverse here.
1716          */
1717         wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1718
1719         wc.nsec = do_div(wall_nsec, 1000000000);
1720         wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1721         wc.version = version;
1722
1723         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1724
1725         version++;
1726         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1727 }
1728
1729 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1730 {
1731         do_shl32_div32(dividend, divisor);
1732         return dividend;
1733 }
1734
1735 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1736                                s8 *pshift, u32 *pmultiplier)
1737 {
1738         uint64_t scaled64;
1739         int32_t  shift = 0;
1740         uint64_t tps64;
1741         uint32_t tps32;
1742
1743         tps64 = base_hz;
1744         scaled64 = scaled_hz;
1745         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1746                 tps64 >>= 1;
1747                 shift--;
1748         }
1749
1750         tps32 = (uint32_t)tps64;
1751         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1752                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1753                         scaled64 >>= 1;
1754                 else
1755                         tps32 <<= 1;
1756                 shift++;
1757         }
1758
1759         *pshift = shift;
1760         *pmultiplier = div_frac(scaled64, tps32);
1761 }
1762
1763 #ifdef CONFIG_X86_64
1764 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1765 #endif
1766
1767 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1768 static unsigned long max_tsc_khz;
1769
1770 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1771 {
1772         u64 v = (u64)khz * (1000000 + ppm);
1773         do_div(v, 1000000);
1774         return v;
1775 }
1776
1777 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1778 {
1779         u64 ratio;
1780
1781         /* Guest TSC same frequency as host TSC? */
1782         if (!scale) {
1783                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1784                 return 0;
1785         }
1786
1787         /* TSC scaling supported? */
1788         if (!kvm_has_tsc_control) {
1789                 if (user_tsc_khz > tsc_khz) {
1790                         vcpu->arch.tsc_catchup = 1;
1791                         vcpu->arch.tsc_always_catchup = 1;
1792                         return 0;
1793                 } else {
1794                         pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1795                         return -1;
1796                 }
1797         }
1798
1799         /* TSC scaling required  - calculate ratio */
1800         ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1801                                 user_tsc_khz, tsc_khz);
1802
1803         if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1804                 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1805                                     user_tsc_khz);
1806                 return -1;
1807         }
1808
1809         vcpu->arch.tsc_scaling_ratio = ratio;
1810         return 0;
1811 }
1812
1813 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1814 {
1815         u32 thresh_lo, thresh_hi;
1816         int use_scaling = 0;
1817
1818         /* tsc_khz can be zero if TSC calibration fails */
1819         if (user_tsc_khz == 0) {
1820                 /* set tsc_scaling_ratio to a safe value */
1821                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1822                 return -1;
1823         }
1824
1825         /* Compute a scale to convert nanoseconds in TSC cycles */
1826         kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1827                            &vcpu->arch.virtual_tsc_shift,
1828                            &vcpu->arch.virtual_tsc_mult);
1829         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1830
1831         /*
1832          * Compute the variation in TSC rate which is acceptable
1833          * within the range of tolerance and decide if the
1834          * rate being applied is within that bounds of the hardware
1835          * rate.  If so, no scaling or compensation need be done.
1836          */
1837         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1838         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1839         if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1840                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1841                 use_scaling = 1;
1842         }
1843         return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1844 }
1845
1846 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1847 {
1848         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1849                                       vcpu->arch.virtual_tsc_mult,
1850                                       vcpu->arch.virtual_tsc_shift);
1851         tsc += vcpu->arch.this_tsc_write;
1852         return tsc;
1853 }
1854
1855 static inline int gtod_is_based_on_tsc(int mode)
1856 {
1857         return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
1858 }
1859
1860 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1861 {
1862 #ifdef CONFIG_X86_64
1863         bool vcpus_matched;
1864         struct kvm_arch *ka = &vcpu->kvm->arch;
1865         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1866
1867         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1868                          atomic_read(&vcpu->kvm->online_vcpus));
1869
1870         /*
1871          * Once the masterclock is enabled, always perform request in
1872          * order to update it.
1873          *
1874          * In order to enable masterclock, the host clocksource must be TSC
1875          * and the vcpus need to have matched TSCs.  When that happens,
1876          * perform request to enable masterclock.
1877          */
1878         if (ka->use_master_clock ||
1879             (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1880                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1881
1882         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1883                             atomic_read(&vcpu->kvm->online_vcpus),
1884                             ka->use_master_clock, gtod->clock.vclock_mode);
1885 #endif
1886 }
1887
1888 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1889 {
1890         u64 curr_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu);
1891         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1892 }
1893
1894 /*
1895  * Multiply tsc by a fixed point number represented by ratio.
1896  *
1897  * The most significant 64-N bits (mult) of ratio represent the
1898  * integral part of the fixed point number; the remaining N bits
1899  * (frac) represent the fractional part, ie. ratio represents a fixed
1900  * point number (mult + frac * 2^(-N)).
1901  *
1902  * N equals to kvm_tsc_scaling_ratio_frac_bits.
1903  */
1904 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1905 {
1906         return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1907 }
1908
1909 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1910 {
1911         u64 _tsc = tsc;
1912         u64 ratio = vcpu->arch.tsc_scaling_ratio;
1913
1914         if (ratio != kvm_default_tsc_scaling_ratio)
1915                 _tsc = __scale_tsc(ratio, tsc);
1916
1917         return _tsc;
1918 }
1919 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1920
1921 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1922 {
1923         u64 tsc;
1924
1925         tsc = kvm_scale_tsc(vcpu, rdtsc());
1926
1927         return target_tsc - tsc;
1928 }
1929
1930 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1931 {
1932         u64 tsc_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu);
1933
1934         return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1935 }
1936 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1937
1938 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1939 {
1940         vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
1941 }
1942
1943 static inline bool kvm_check_tsc_unstable(void)
1944 {
1945 #ifdef CONFIG_X86_64
1946         /*
1947          * TSC is marked unstable when we're running on Hyper-V,
1948          * 'TSC page' clocksource is good.
1949          */
1950         if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
1951                 return false;
1952 #endif
1953         return check_tsc_unstable();
1954 }
1955
1956 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1957 {
1958         struct kvm *kvm = vcpu->kvm;
1959         u64 offset, ns, elapsed;
1960         unsigned long flags;
1961         bool matched;
1962         bool already_matched;
1963         u64 data = msr->data;
1964         bool synchronizing = false;
1965
1966         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1967         offset = kvm_compute_tsc_offset(vcpu, data);
1968         ns = get_kvmclock_base_ns();
1969         elapsed = ns - kvm->arch.last_tsc_nsec;
1970
1971         if (vcpu->arch.virtual_tsc_khz) {
1972                 if (data == 0 && msr->host_initiated) {
1973                         /*
1974                          * detection of vcpu initialization -- need to sync
1975                          * with other vCPUs. This particularly helps to keep
1976                          * kvm_clock stable after CPU hotplug
1977                          */
1978                         synchronizing = true;
1979                 } else {
1980                         u64 tsc_exp = kvm->arch.last_tsc_write +
1981                                                 nsec_to_cycles(vcpu, elapsed);
1982                         u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1983                         /*
1984                          * Special case: TSC write with a small delta (1 second)
1985                          * of virtual cycle time against real time is
1986                          * interpreted as an attempt to synchronize the CPU.
1987                          */
1988                         synchronizing = data < tsc_exp + tsc_hz &&
1989                                         data + tsc_hz > tsc_exp;
1990                 }
1991         }
1992
1993         /*
1994          * For a reliable TSC, we can match TSC offsets, and for an unstable
1995          * TSC, we add elapsed time in this computation.  We could let the
1996          * compensation code attempt to catch up if we fall behind, but
1997          * it's better to try to match offsets from the beginning.
1998          */
1999         if (synchronizing &&
2000             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2001                 if (!kvm_check_tsc_unstable()) {
2002                         offset = kvm->arch.cur_tsc_offset;
2003                 } else {
2004                         u64 delta = nsec_to_cycles(vcpu, elapsed);
2005                         data += delta;
2006                         offset = kvm_compute_tsc_offset(vcpu, data);
2007                 }
2008                 matched = true;
2009                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2010         } else {
2011                 /*
2012                  * We split periods of matched TSC writes into generations.
2013                  * For each generation, we track the original measured
2014                  * nanosecond time, offset, and write, so if TSCs are in
2015                  * sync, we can match exact offset, and if not, we can match
2016                  * exact software computation in compute_guest_tsc()
2017                  *
2018                  * These values are tracked in kvm->arch.cur_xxx variables.
2019                  */
2020                 kvm->arch.cur_tsc_generation++;
2021                 kvm->arch.cur_tsc_nsec = ns;
2022                 kvm->arch.cur_tsc_write = data;
2023                 kvm->arch.cur_tsc_offset = offset;
2024                 matched = false;
2025         }
2026
2027         /*
2028          * We also track th most recent recorded KHZ, write and time to
2029          * allow the matching interval to be extended at each write.
2030          */
2031         kvm->arch.last_tsc_nsec = ns;
2032         kvm->arch.last_tsc_write = data;
2033         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2034
2035         vcpu->arch.last_guest_tsc = data;
2036
2037         /* Keep track of which generation this VCPU has synchronized to */
2038         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2039         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2040         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2041
2042         if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2043                 update_ia32_tsc_adjust_msr(vcpu, offset);
2044
2045         kvm_vcpu_write_tsc_offset(vcpu, offset);
2046         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2047
2048         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2049         if (!matched) {
2050                 kvm->arch.nr_vcpus_matched_tsc = 0;
2051         } else if (!already_matched) {
2052                 kvm->arch.nr_vcpus_matched_tsc++;
2053         }
2054
2055         kvm_track_tsc_matching(vcpu);
2056         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2057 }
2058
2059 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2060
2061 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2062                                            s64 adjustment)
2063 {
2064         u64 tsc_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu);
2065         kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2066 }
2067
2068 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2069 {
2070         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2071                 WARN_ON(adjustment < 0);
2072         adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2073         adjust_tsc_offset_guest(vcpu, adjustment);
2074 }
2075
2076 #ifdef CONFIG_X86_64
2077
2078 static u64 read_tsc(void)
2079 {
2080         u64 ret = (u64)rdtsc_ordered();
2081         u64 last = pvclock_gtod_data.clock.cycle_last;
2082
2083         if (likely(ret >= last))
2084                 return ret;
2085
2086         /*
2087          * GCC likes to generate cmov here, but this branch is extremely
2088          * predictable (it's just a function of time and the likely is
2089          * very likely) and there's a data dependence, so force GCC
2090          * to generate a branch instead.  I don't barrier() because
2091          * we don't actually need a barrier, and if this function
2092          * ever gets inlined it will generate worse code.
2093          */
2094         asm volatile ("");
2095         return last;
2096 }
2097
2098 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2099                           int *mode)
2100 {
2101         long v;
2102         u64 tsc_pg_val;
2103
2104         switch (clock->vclock_mode) {
2105         case VDSO_CLOCKMODE_HVCLOCK:
2106                 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2107                                                   tsc_timestamp);
2108                 if (tsc_pg_val != U64_MAX) {
2109                         /* TSC page valid */
2110                         *mode = VDSO_CLOCKMODE_HVCLOCK;
2111                         v = (tsc_pg_val - clock->cycle_last) &
2112                                 clock->mask;
2113                 } else {
2114                         /* TSC page invalid */
2115                         *mode = VDSO_CLOCKMODE_NONE;
2116                 }
2117                 break;
2118         case VDSO_CLOCKMODE_TSC:
2119                 *mode = VDSO_CLOCKMODE_TSC;
2120                 *tsc_timestamp = read_tsc();
2121                 v = (*tsc_timestamp - clock->cycle_last) &
2122                         clock->mask;
2123                 break;
2124         default:
2125                 *mode = VDSO_CLOCKMODE_NONE;
2126         }
2127
2128         if (*mode == VDSO_CLOCKMODE_NONE)
2129                 *tsc_timestamp = v = 0;
2130
2131         return v * clock->mult;
2132 }
2133
2134 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2135 {
2136         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2137         unsigned long seq;
2138         int mode;
2139         u64 ns;
2140
2141         do {
2142                 seq = read_seqcount_begin(&gtod->seq);
2143                 ns = gtod->raw_clock.base_cycles;
2144                 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2145                 ns >>= gtod->raw_clock.shift;
2146                 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2147         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2148         *t = ns;
2149
2150         return mode;
2151 }
2152
2153 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2154 {
2155         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2156         unsigned long seq;
2157         int mode;
2158         u64 ns;
2159
2160         do {
2161                 seq = read_seqcount_begin(&gtod->seq);
2162                 ts->tv_sec = gtod->wall_time_sec;
2163                 ns = gtod->clock.base_cycles;
2164                 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2165                 ns >>= gtod->clock.shift;
2166         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2167
2168         ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2169         ts->tv_nsec = ns;
2170
2171         return mode;
2172 }
2173
2174 /* returns true if host is using TSC based clocksource */
2175 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2176 {
2177         /* checked again under seqlock below */
2178         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2179                 return false;
2180
2181         return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2182                                                       tsc_timestamp));
2183 }
2184
2185 /* returns true if host is using TSC based clocksource */
2186 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2187                                            u64 *tsc_timestamp)
2188 {
2189         /* checked again under seqlock below */
2190         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2191                 return false;
2192
2193         return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2194 }
2195 #endif
2196
2197 /*
2198  *
2199  * Assuming a stable TSC across physical CPUS, and a stable TSC
2200  * across virtual CPUs, the following condition is possible.
2201  * Each numbered line represents an event visible to both
2202  * CPUs at the next numbered event.
2203  *
2204  * "timespecX" represents host monotonic time. "tscX" represents
2205  * RDTSC value.
2206  *
2207  *              VCPU0 on CPU0           |       VCPU1 on CPU1
2208  *
2209  * 1.  read timespec0,tsc0
2210  * 2.                                   | timespec1 = timespec0 + N
2211  *                                      | tsc1 = tsc0 + M
2212  * 3. transition to guest               | transition to guest
2213  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2214  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
2215  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2216  *
2217  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2218  *
2219  *      - ret0 < ret1
2220  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2221  *              ...
2222  *      - 0 < N - M => M < N
2223  *
2224  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2225  * always the case (the difference between two distinct xtime instances
2226  * might be smaller then the difference between corresponding TSC reads,
2227  * when updating guest vcpus pvclock areas).
2228  *
2229  * To avoid that problem, do not allow visibility of distinct
2230  * system_timestamp/tsc_timestamp values simultaneously: use a master
2231  * copy of host monotonic time values. Update that master copy
2232  * in lockstep.
2233  *
2234  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2235  *
2236  */
2237
2238 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2239 {
2240 #ifdef CONFIG_X86_64
2241         struct kvm_arch *ka = &kvm->arch;
2242         int vclock_mode;
2243         bool host_tsc_clocksource, vcpus_matched;
2244
2245         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2246                         atomic_read(&kvm->online_vcpus));
2247
2248         /*
2249          * If the host uses TSC clock, then passthrough TSC as stable
2250          * to the guest.
2251          */
2252         host_tsc_clocksource = kvm_get_time_and_clockread(
2253                                         &ka->master_kernel_ns,
2254                                         &ka->master_cycle_now);
2255
2256         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2257                                 && !ka->backwards_tsc_observed
2258                                 && !ka->boot_vcpu_runs_old_kvmclock;
2259
2260         if (ka->use_master_clock)
2261                 atomic_set(&kvm_guest_has_master_clock, 1);
2262
2263         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2264         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2265                                         vcpus_matched);
2266 #endif
2267 }
2268
2269 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2270 {
2271         kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2272 }
2273
2274 static void kvm_gen_update_masterclock(struct kvm *kvm)
2275 {
2276 #ifdef CONFIG_X86_64
2277         int i;
2278         struct kvm_vcpu *vcpu;
2279         struct kvm_arch *ka = &kvm->arch;
2280
2281         spin_lock(&ka->pvclock_gtod_sync_lock);
2282         kvm_make_mclock_inprogress_request(kvm);
2283         /* no guest entries from this point */
2284         pvclock_update_vm_gtod_copy(kvm);
2285
2286         kvm_for_each_vcpu(i, vcpu, kvm)
2287                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2288
2289         /* guest entries allowed */
2290         kvm_for_each_vcpu(i, vcpu, kvm)
2291                 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2292
2293         spin_unlock(&ka->pvclock_gtod_sync_lock);
2294 #endif
2295 }
2296
2297 u64 get_kvmclock_ns(struct kvm *kvm)
2298 {
2299         struct kvm_arch *ka = &kvm->arch;
2300         struct pvclock_vcpu_time_info hv_clock;
2301         u64 ret;
2302
2303         spin_lock(&ka->pvclock_gtod_sync_lock);
2304         if (!ka->use_master_clock) {
2305                 spin_unlock(&ka->pvclock_gtod_sync_lock);
2306                 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2307         }
2308
2309         hv_clock.tsc_timestamp = ka->master_cycle_now;
2310         hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2311         spin_unlock(&ka->pvclock_gtod_sync_lock);
2312
2313         /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2314         get_cpu();
2315
2316         if (__this_cpu_read(cpu_tsc_khz)) {
2317                 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2318                                    &hv_clock.tsc_shift,
2319                                    &hv_clock.tsc_to_system_mul);
2320                 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2321         } else
2322                 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2323
2324         put_cpu();
2325
2326         return ret;
2327 }
2328
2329 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2330 {
2331         struct kvm_vcpu_arch *vcpu = &v->arch;
2332         struct pvclock_vcpu_time_info guest_hv_clock;
2333
2334         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2335                 &guest_hv_clock, sizeof(guest_hv_clock))))
2336                 return;
2337
2338         /* This VCPU is paused, but it's legal for a guest to read another
2339          * VCPU's kvmclock, so we really have to follow the specification where
2340          * it says that version is odd if data is being modified, and even after
2341          * it is consistent.
2342          *
2343          * Version field updates must be kept separate.  This is because
2344          * kvm_write_guest_cached might use a "rep movs" instruction, and
2345          * writes within a string instruction are weakly ordered.  So there
2346          * are three writes overall.
2347          *
2348          * As a small optimization, only write the version field in the first
2349          * and third write.  The vcpu->pv_time cache is still valid, because the
2350          * version field is the first in the struct.
2351          */
2352         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2353
2354         if (guest_hv_clock.version & 1)
2355                 ++guest_hv_clock.version;  /* first time write, random junk */
2356
2357         vcpu->hv_clock.version = guest_hv_clock.version + 1;
2358         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2359                                 &vcpu->hv_clock,
2360                                 sizeof(vcpu->hv_clock.version));
2361
2362         smp_wmb();
2363
2364         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2365         vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2366
2367         if (vcpu->pvclock_set_guest_stopped_request) {
2368                 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2369                 vcpu->pvclock_set_guest_stopped_request = false;
2370         }
2371
2372         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2373
2374         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2375                                 &vcpu->hv_clock,
2376                                 sizeof(vcpu->hv_clock));
2377
2378         smp_wmb();
2379
2380         vcpu->hv_clock.version++;
2381         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2382                                 &vcpu->hv_clock,
2383                                 sizeof(vcpu->hv_clock.version));
2384 }
2385
2386 static int kvm_guest_time_update(struct kvm_vcpu *v)
2387 {
2388         unsigned long flags, tgt_tsc_khz;
2389         struct kvm_vcpu_arch *vcpu = &v->arch;
2390         struct kvm_arch *ka = &v->kvm->arch;
2391         s64 kernel_ns;
2392         u64 tsc_timestamp, host_tsc;
2393         u8 pvclock_flags;
2394         bool use_master_clock;
2395
2396         kernel_ns = 0;
2397         host_tsc = 0;
2398
2399         /*
2400          * If the host uses TSC clock, then passthrough TSC as stable
2401          * to the guest.
2402          */
2403         spin_lock(&ka->pvclock_gtod_sync_lock);
2404         use_master_clock = ka->use_master_clock;
2405         if (use_master_clock) {
2406                 host_tsc = ka->master_cycle_now;
2407                 kernel_ns = ka->master_kernel_ns;
2408         }
2409         spin_unlock(&ka->pvclock_gtod_sync_lock);
2410
2411         /* Keep irq disabled to prevent changes to the clock */
2412         local_irq_save(flags);
2413         tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2414         if (unlikely(tgt_tsc_khz == 0)) {
2415                 local_irq_restore(flags);
2416                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2417                 return 1;
2418         }
2419         if (!use_master_clock) {
2420                 host_tsc = rdtsc();
2421                 kernel_ns = get_kvmclock_base_ns();
2422         }
2423
2424         tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2425
2426         /*
2427          * We may have to catch up the TSC to match elapsed wall clock
2428          * time for two reasons, even if kvmclock is used.
2429          *   1) CPU could have been running below the maximum TSC rate
2430          *   2) Broken TSC compensation resets the base at each VCPU
2431          *      entry to avoid unknown leaps of TSC even when running
2432          *      again on the same CPU.  This may cause apparent elapsed
2433          *      time to disappear, and the guest to stand still or run
2434          *      very slowly.
2435          */
2436         if (vcpu->tsc_catchup) {
2437                 u64 tsc = compute_guest_tsc(v, kernel_ns);
2438                 if (tsc > tsc_timestamp) {
2439                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2440                         tsc_timestamp = tsc;
2441                 }
2442         }
2443
2444         local_irq_restore(flags);
2445
2446         /* With all the info we got, fill in the values */
2447
2448         if (kvm_has_tsc_control)
2449                 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2450
2451         if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2452                 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2453                                    &vcpu->hv_clock.tsc_shift,
2454                                    &vcpu->hv_clock.tsc_to_system_mul);
2455                 vcpu->hw_tsc_khz = tgt_tsc_khz;
2456         }
2457
2458         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2459         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2460         vcpu->last_guest_tsc = tsc_timestamp;
2461
2462         /* If the host uses TSC clocksource, then it is stable */
2463         pvclock_flags = 0;
2464         if (use_master_clock)
2465                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2466
2467         vcpu->hv_clock.flags = pvclock_flags;
2468
2469         if (vcpu->pv_time_enabled)
2470                 kvm_setup_pvclock_page(v);
2471         if (v == kvm_get_vcpu(v->kvm, 0))
2472                 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2473         return 0;
2474 }
2475
2476 /*
2477  * kvmclock updates which are isolated to a given vcpu, such as
2478  * vcpu->cpu migration, should not allow system_timestamp from
2479  * the rest of the vcpus to remain static. Otherwise ntp frequency
2480  * correction applies to one vcpu's system_timestamp but not
2481  * the others.
2482  *
2483  * So in those cases, request a kvmclock update for all vcpus.
2484  * We need to rate-limit these requests though, as they can
2485  * considerably slow guests that have a large number of vcpus.
2486  * The time for a remote vcpu to update its kvmclock is bound
2487  * by the delay we use to rate-limit the updates.
2488  */
2489
2490 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2491
2492 static void kvmclock_update_fn(struct work_struct *work)
2493 {
2494         int i;
2495         struct delayed_work *dwork = to_delayed_work(work);
2496         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2497                                            kvmclock_update_work);
2498         struct kvm *kvm = container_of(ka, struct kvm, arch);
2499         struct kvm_vcpu *vcpu;
2500
2501         kvm_for_each_vcpu(i, vcpu, kvm) {
2502                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2503                 kvm_vcpu_kick(vcpu);
2504         }
2505 }
2506
2507 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2508 {
2509         struct kvm *kvm = v->kvm;
2510
2511         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2512         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2513                                         KVMCLOCK_UPDATE_DELAY);
2514 }
2515
2516 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2517
2518 static void kvmclock_sync_fn(struct work_struct *work)
2519 {
2520         struct delayed_work *dwork = to_delayed_work(work);
2521         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2522                                            kvmclock_sync_work);
2523         struct kvm *kvm = container_of(ka, struct kvm, arch);
2524
2525         if (!kvmclock_periodic_sync)
2526                 return;
2527
2528         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2529         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2530                                         KVMCLOCK_SYNC_PERIOD);
2531 }
2532
2533 /*
2534  * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2535  */
2536 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2537 {
2538         /* McStatusWrEn enabled? */
2539         if (guest_cpuid_is_amd_or_hygon(vcpu))
2540                 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2541
2542         return false;
2543 }
2544
2545 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2546 {
2547         u64 mcg_cap = vcpu->arch.mcg_cap;
2548         unsigned bank_num = mcg_cap & 0xff;
2549         u32 msr = msr_info->index;
2550         u64 data = msr_info->data;
2551
2552         switch (msr) {
2553         case MSR_IA32_MCG_STATUS:
2554                 vcpu->arch.mcg_status = data;
2555                 break;
2556         case MSR_IA32_MCG_CTL:
2557                 if (!(mcg_cap & MCG_CTL_P) &&
2558                     (data || !msr_info->host_initiated))
2559                         return 1;
2560                 if (data != 0 && data != ~(u64)0)
2561                         return 1;
2562                 vcpu->arch.mcg_ctl = data;
2563                 break;
2564         default:
2565                 if (msr >= MSR_IA32_MC0_CTL &&
2566                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2567                         u32 offset = array_index_nospec(
2568                                 msr - MSR_IA32_MC0_CTL,
2569                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2570
2571                         /* only 0 or all 1s can be written to IA32_MCi_CTL
2572                          * some Linux kernels though clear bit 10 in bank 4 to
2573                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2574                          * this to avoid an uncatched #GP in the guest
2575                          */
2576                         if ((offset & 0x3) == 0 &&
2577                             data != 0 && (data | (1 << 10)) != ~(u64)0)
2578                                 return -1;
2579
2580                         /* MCi_STATUS */
2581                         if (!msr_info->host_initiated &&
2582                             (offset & 0x3) == 1 && data != 0) {
2583                                 if (!can_set_mci_status(vcpu))
2584                                         return -1;
2585                         }
2586
2587                         vcpu->arch.mce_banks[offset] = data;
2588                         break;
2589                 }
2590                 return 1;
2591         }
2592         return 0;
2593 }
2594
2595 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2596 {
2597         struct kvm *kvm = vcpu->kvm;
2598         int lm = is_long_mode(vcpu);
2599         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2600                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2601         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2602                 : kvm->arch.xen_hvm_config.blob_size_32;
2603         u32 page_num = data & ~PAGE_MASK;
2604         u64 page_addr = data & PAGE_MASK;
2605         u8 *page;
2606         int r;
2607
2608         r = -E2BIG;
2609         if (page_num >= blob_size)
2610                 goto out;
2611         r = -ENOMEM;
2612         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2613         if (IS_ERR(page)) {
2614                 r = PTR_ERR(page);
2615                 goto out;
2616         }
2617         if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2618                 goto out_free;
2619         r = 0;
2620 out_free:
2621         kfree(page);
2622 out:
2623         return r;
2624 }
2625
2626 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2627 {
2628         gpa_t gpa = data & ~0x3f;
2629
2630         /* Bits 3:5 are reserved, Should be zero */
2631         if (data & 0x38)
2632                 return 1;
2633
2634         vcpu->arch.apf.msr_val = data;
2635
2636         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2637                 kvm_clear_async_pf_completion_queue(vcpu);
2638                 kvm_async_pf_hash_reset(vcpu);
2639                 return 0;
2640         }
2641
2642         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2643                                         sizeof(u32)))
2644                 return 1;
2645
2646         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2647         vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2648         kvm_async_pf_wakeup_all(vcpu);
2649         return 0;
2650 }
2651
2652 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2653 {
2654         vcpu->arch.pv_time_enabled = false;
2655         vcpu->arch.time = 0;
2656 }
2657
2658 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2659 {
2660         ++vcpu->stat.tlb_flush;
2661         kvm_x86_ops.tlb_flush(vcpu, invalidate_gpa);
2662 }
2663
2664 static void record_steal_time(struct kvm_vcpu *vcpu)
2665 {
2666         struct kvm_host_map map;
2667         struct kvm_steal_time *st;
2668
2669         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2670                 return;
2671
2672         /* -EAGAIN is returned in atomic context so we can just return. */
2673         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2674                         &map, &vcpu->arch.st.cache, false))
2675                 return;
2676
2677         st = map.hva +
2678                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2679
2680         /*
2681          * Doing a TLB flush here, on the guest's behalf, can avoid
2682          * expensive IPIs.
2683          */
2684         trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2685                 st->preempted & KVM_VCPU_FLUSH_TLB);
2686         if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2687                 kvm_vcpu_flush_tlb(vcpu, false);
2688
2689         vcpu->arch.st.preempted = 0;
2690
2691         if (st->version & 1)
2692                 st->version += 1;  /* first time write, random junk */
2693
2694         st->version += 1;
2695
2696         smp_wmb();
2697
2698         st->steal += current->sched_info.run_delay -
2699                 vcpu->arch.st.last_steal;
2700         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2701
2702         smp_wmb();
2703
2704         st->version += 1;
2705
2706         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2707 }
2708
2709 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2710 {
2711         bool pr = false;
2712         u32 msr = msr_info->index;
2713         u64 data = msr_info->data;
2714
2715         switch (msr) {
2716         case MSR_AMD64_NB_CFG:
2717         case MSR_IA32_UCODE_WRITE:
2718         case MSR_VM_HSAVE_PA:
2719         case MSR_AMD64_PATCH_LOADER:
2720         case MSR_AMD64_BU_CFG2:
2721         case MSR_AMD64_DC_CFG:
2722         case MSR_F15H_EX_CFG:
2723                 break;
2724
2725         case MSR_IA32_UCODE_REV:
2726                 if (msr_info->host_initiated)
2727                         vcpu->arch.microcode_version = data;
2728                 break;
2729         case MSR_IA32_ARCH_CAPABILITIES:
2730                 if (!msr_info->host_initiated)
2731                         return 1;
2732                 vcpu->arch.arch_capabilities = data;
2733                 break;
2734         case MSR_EFER:
2735                 return set_efer(vcpu, msr_info);
2736         case MSR_K7_HWCR:
2737                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2738                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2739                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2740
2741                 /* Handle McStatusWrEn */
2742                 if (data == BIT_ULL(18)) {
2743                         vcpu->arch.msr_hwcr = data;
2744                 } else if (data != 0) {
2745                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2746                                     data);
2747                         return 1;
2748                 }
2749                 break;
2750         case MSR_FAM10H_MMIO_CONF_BASE:
2751                 if (data != 0) {
2752                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2753                                     "0x%llx\n", data);
2754                         return 1;
2755                 }
2756                 break;
2757         case MSR_IA32_DEBUGCTLMSR:
2758                 if (!data) {
2759                         /* We support the non-activated case already */
2760                         break;
2761                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2762                         /* Values other than LBR and BTF are vendor-specific,
2763                            thus reserved and should throw a #GP */
2764                         return 1;
2765                 }
2766                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2767                             __func__, data);
2768                 break;
2769         case 0x200 ... 0x2ff:
2770                 return kvm_mtrr_set_msr(vcpu, msr, data);
2771         case MSR_IA32_APICBASE:
2772                 return kvm_set_apic_base(vcpu, msr_info);
2773         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2774                 return kvm_x2apic_msr_write(vcpu, msr, data);
2775         case MSR_IA32_TSCDEADLINE:
2776                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2777                 break;
2778         case MSR_IA32_TSC_ADJUST:
2779                 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2780                         if (!msr_info->host_initiated) {
2781                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2782                                 adjust_tsc_offset_guest(vcpu, adj);
2783                         }
2784                         vcpu->arch.ia32_tsc_adjust_msr = data;
2785                 }
2786                 break;
2787         case MSR_IA32_MISC_ENABLE:
2788                 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2789                     ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2790                         if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2791                                 return 1;
2792                         vcpu->arch.ia32_misc_enable_msr = data;
2793                         kvm_update_cpuid(vcpu);
2794                 } else {
2795                         vcpu->arch.ia32_misc_enable_msr = data;
2796                 }
2797                 break;
2798         case MSR_IA32_SMBASE:
2799                 if (!msr_info->host_initiated)
2800                         return 1;
2801                 vcpu->arch.smbase = data;
2802                 break;
2803         case MSR_IA32_POWER_CTL:
2804                 vcpu->arch.msr_ia32_power_ctl = data;
2805                 break;
2806         case MSR_IA32_TSC:
2807                 kvm_write_tsc(vcpu, msr_info);
2808                 break;
2809         case MSR_IA32_XSS:
2810                 if (!msr_info->host_initiated &&
2811                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2812                         return 1;
2813                 /*
2814                  * KVM supports exposing PT to the guest, but does not support
2815                  * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
2816                  * XSAVES/XRSTORS to save/restore PT MSRs.
2817                  */
2818                 if (data & ~supported_xss)
2819                         return 1;
2820                 vcpu->arch.ia32_xss = data;
2821                 break;
2822         case MSR_SMI_COUNT:
2823                 if (!msr_info->host_initiated)
2824                         return 1;
2825                 vcpu->arch.smi_count = data;
2826                 break;
2827         case MSR_KVM_WALL_CLOCK_NEW:
2828         case MSR_KVM_WALL_CLOCK:
2829                 vcpu->kvm->arch.wall_clock = data;
2830                 kvm_write_wall_clock(vcpu->kvm, data);
2831                 break;
2832         case MSR_KVM_SYSTEM_TIME_NEW:
2833         case MSR_KVM_SYSTEM_TIME: {
2834                 struct kvm_arch *ka = &vcpu->kvm->arch;
2835
2836                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2837                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2838
2839                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2840                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2841
2842                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2843                 }
2844
2845                 vcpu->arch.time = data;
2846                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2847
2848                 /* we verify if the enable bit is set... */
2849                 vcpu->arch.pv_time_enabled = false;
2850                 if (!(data & 1))
2851                         break;
2852
2853                 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2854                      &vcpu->arch.pv_time, data & ~1ULL,
2855                      sizeof(struct pvclock_vcpu_time_info)))
2856                         vcpu->arch.pv_time_enabled = true;
2857
2858                 break;
2859         }
2860         case MSR_KVM_ASYNC_PF_EN:
2861                 if (kvm_pv_enable_async_pf(vcpu, data))
2862                         return 1;
2863                 break;
2864         case MSR_KVM_STEAL_TIME:
2865
2866                 if (unlikely(!sched_info_on()))
2867                         return 1;
2868
2869                 if (data & KVM_STEAL_RESERVED_MASK)
2870                         return 1;
2871
2872                 vcpu->arch.st.msr_val = data;
2873
2874                 if (!(data & KVM_MSR_ENABLED))
2875                         break;
2876
2877                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2878
2879                 break;
2880         case MSR_KVM_PV_EOI_EN:
2881                 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2882                         return 1;
2883                 break;
2884
2885         case MSR_KVM_POLL_CONTROL:
2886                 /* only enable bit supported */
2887                 if (data & (-1ULL << 1))
2888                         return 1;
2889
2890                 vcpu->arch.msr_kvm_poll_control = data;
2891                 break;
2892
2893         case MSR_IA32_MCG_CTL:
2894         case MSR_IA32_MCG_STATUS:
2895         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2896                 return set_msr_mce(vcpu, msr_info);
2897
2898         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2899         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2900                 pr = true; /* fall through */
2901         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2902         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2903                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2904                         return kvm_pmu_set_msr(vcpu, msr_info);
2905
2906                 if (pr || data != 0)
2907                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2908                                     "0x%x data 0x%llx\n", msr, data);
2909                 break;
2910         case MSR_K7_CLK_CTL:
2911                 /*
2912                  * Ignore all writes to this no longer documented MSR.
2913                  * Writes are only relevant for old K7 processors,
2914                  * all pre-dating SVM, but a recommended workaround from
2915                  * AMD for these chips. It is possible to specify the
2916                  * affected processor models on the command line, hence
2917                  * the need to ignore the workaround.
2918                  */
2919                 break;
2920         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2921         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2922         case HV_X64_MSR_CRASH_CTL:
2923         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2924         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2925         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2926         case HV_X64_MSR_TSC_EMULATION_STATUS:
2927                 return kvm_hv_set_msr_common(vcpu, msr, data,
2928                                              msr_info->host_initiated);
2929         case MSR_IA32_BBL_CR_CTL3:
2930                 /* Drop writes to this legacy MSR -- see rdmsr
2931                  * counterpart for further detail.
2932                  */
2933                 if (report_ignored_msrs)
2934                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2935                                 msr, data);
2936                 break;
2937         case MSR_AMD64_OSVW_ID_LENGTH:
2938                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2939                         return 1;
2940                 vcpu->arch.osvw.length = data;
2941                 break;
2942         case MSR_AMD64_OSVW_STATUS:
2943                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2944                         return 1;
2945                 vcpu->arch.osvw.status = data;
2946                 break;
2947         case MSR_PLATFORM_INFO:
2948                 if (!msr_info->host_initiated ||
2949                     (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2950                      cpuid_fault_enabled(vcpu)))
2951                         return 1;
2952                 vcpu->arch.msr_platform_info = data;
2953                 break;
2954         case MSR_MISC_FEATURES_ENABLES:
2955                 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2956                     (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2957                      !supports_cpuid_fault(vcpu)))
2958                         return 1;
2959                 vcpu->arch.msr_misc_features_enables = data;
2960                 break;
2961         default:
2962                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2963                         return xen_hvm_config(vcpu, data);
2964                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2965                         return kvm_pmu_set_msr(vcpu, msr_info);
2966                 if (!ignore_msrs) {
2967                         vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2968                                     msr, data);
2969                         return 1;
2970                 } else {
2971                         if (report_ignored_msrs)
2972                                 vcpu_unimpl(vcpu,
2973                                         "ignored wrmsr: 0x%x data 0x%llx\n",
2974                                         msr, data);
2975                         break;
2976                 }
2977         }
2978         return 0;
2979 }
2980 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2981
2982 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
2983 {
2984         u64 data;
2985         u64 mcg_cap = vcpu->arch.mcg_cap;
2986         unsigned bank_num = mcg_cap & 0xff;
2987
2988         switch (msr) {
2989         case MSR_IA32_P5_MC_ADDR:
2990         case MSR_IA32_P5_MC_TYPE:
2991                 data = 0;
2992                 break;
2993         case MSR_IA32_MCG_CAP:
2994                 data = vcpu->arch.mcg_cap;
2995                 break;
2996         case MSR_IA32_MCG_CTL:
2997                 if (!(mcg_cap & MCG_CTL_P) && !host)
2998                         return 1;
2999                 data = vcpu->arch.mcg_ctl;
3000                 break;
3001         case MSR_IA32_MCG_STATUS:
3002                 data = vcpu->arch.mcg_status;
3003                 break;
3004         default:
3005                 if (msr >= MSR_IA32_MC0_CTL &&
3006                     msr < MSR_IA32_MCx_CTL(bank_num)) {
3007                         u32 offset = array_index_nospec(
3008                                 msr - MSR_IA32_MC0_CTL,
3009                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3010
3011                         data = vcpu->arch.mce_banks[offset];
3012                         break;
3013                 }
3014                 return 1;
3015         }
3016         *pdata = data;
3017         return 0;
3018 }
3019
3020 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3021 {
3022         switch (msr_info->index) {
3023         case MSR_IA32_PLATFORM_ID:
3024         case MSR_IA32_EBL_CR_POWERON:
3025         case MSR_IA32_DEBUGCTLMSR:
3026         case MSR_IA32_LASTBRANCHFROMIP:
3027         case MSR_IA32_LASTBRANCHTOIP:
3028         case MSR_IA32_LASTINTFROMIP:
3029         case MSR_IA32_LASTINTTOIP:
3030         case MSR_K8_SYSCFG:
3031         case MSR_K8_TSEG_ADDR:
3032         case MSR_K8_TSEG_MASK:
3033         case MSR_VM_HSAVE_PA:
3034         case MSR_K8_INT_PENDING_MSG:
3035         case MSR_AMD64_NB_CFG:
3036         case MSR_FAM10H_MMIO_CONF_BASE:
3037         case MSR_AMD64_BU_CFG2:
3038         case MSR_IA32_PERF_CTL:
3039         case MSR_AMD64_DC_CFG:
3040         case MSR_F15H_EX_CFG:
3041         /*
3042          * Intel Sandy Bridge CPUs must support the RAPL (running average power
3043          * limit) MSRs. Just return 0, as we do not want to expose the host
3044          * data here. Do not conditionalize this on CPUID, as KVM does not do
3045          * so for existing CPU-specific MSRs.
3046          */
3047         case MSR_RAPL_POWER_UNIT:
3048         case MSR_PP0_ENERGY_STATUS:     /* Power plane 0 (core) */
3049         case MSR_PP1_ENERGY_STATUS:     /* Power plane 1 (graphics uncore) */
3050         case MSR_PKG_ENERGY_STATUS:     /* Total package */
3051         case MSR_DRAM_ENERGY_STATUS:    /* DRAM controller */
3052                 msr_info->data = 0;
3053                 break;
3054         case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3055         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3056         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3057         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3058         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3059                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3060                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3061                 msr_info->data = 0;
3062                 break;
3063         case MSR_IA32_UCODE_REV:
3064                 msr_info->data = vcpu->arch.microcode_version;
3065                 break;
3066         case MSR_IA32_ARCH_CAPABILITIES:
3067                 if (!msr_info->host_initiated &&
3068                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3069                         return 1;
3070                 msr_info->data = vcpu->arch.arch_capabilities;
3071                 break;
3072         case MSR_IA32_POWER_CTL:
3073                 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3074                 break;
3075         case MSR_IA32_TSC:
3076                 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3077                 break;
3078         case MSR_MTRRcap:
3079         case 0x200 ... 0x2ff:
3080                 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3081         case 0xcd: /* fsb frequency */
3082                 msr_info->data = 3;
3083                 break;
3084                 /*
3085                  * MSR_EBC_FREQUENCY_ID
3086                  * Conservative value valid for even the basic CPU models.
3087                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3088                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3089                  * and 266MHz for model 3, or 4. Set Core Clock
3090                  * Frequency to System Bus Frequency Ratio to 1 (bits
3091                  * 31:24) even though these are only valid for CPU
3092                  * models > 2, however guests may end up dividing or
3093                  * multiplying by zero otherwise.
3094                  */
3095         case MSR_EBC_FREQUENCY_ID:
3096                 msr_info->data = 1 << 24;
3097                 break;
3098         case MSR_IA32_APICBASE:
3099                 msr_info->data = kvm_get_apic_base(vcpu);
3100                 break;
3101         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
3102                 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3103         case MSR_IA32_TSCDEADLINE:
3104                 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3105                 break;
3106         case MSR_IA32_TSC_ADJUST:
3107                 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3108                 break;
3109         case MSR_IA32_MISC_ENABLE:
3110                 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3111                 break;
3112         case MSR_IA32_SMBASE:
3113                 if (!msr_info->host_initiated)
3114                         return 1;
3115                 msr_info->data = vcpu->arch.smbase;
3116                 break;
3117         case MSR_SMI_COUNT:
3118                 msr_info->data = vcpu->arch.smi_count;
3119                 break;
3120         case MSR_IA32_PERF_STATUS:
3121                 /* TSC increment by tick */
3122                 msr_info->data = 1000ULL;
3123                 /* CPU multiplier */
3124                 msr_info->data |= (((uint64_t)4ULL) << 40);
3125                 break;
3126         case MSR_EFER:
3127                 msr_info->data = vcpu->arch.efer;
3128                 break;
3129         case MSR_KVM_WALL_CLOCK:
3130         case MSR_KVM_WALL_CLOCK_NEW:
3131                 msr_info->data = vcpu->kvm->arch.wall_clock;
3132                 break;
3133         case MSR_KVM_SYSTEM_TIME:
3134         case MSR_KVM_SYSTEM_TIME_NEW:
3135                 msr_info->data = vcpu->arch.time;
3136                 break;
3137         case MSR_KVM_ASYNC_PF_EN:
3138                 msr_info->data = vcpu->arch.apf.msr_val;
3139                 break;
3140         case MSR_KVM_STEAL_TIME:
3141                 msr_info->data = vcpu->arch.st.msr_val;
3142                 break;
3143         case MSR_KVM_PV_EOI_EN:
3144                 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3145                 break;
3146         case MSR_KVM_POLL_CONTROL:
3147                 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3148                 break;
3149         case MSR_IA32_P5_MC_ADDR:
3150         case MSR_IA32_P5_MC_TYPE:
3151         case MSR_IA32_MCG_CAP:
3152         case MSR_IA32_MCG_CTL:
3153         case MSR_IA32_MCG_STATUS:
3154         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3155                 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3156                                    msr_info->host_initiated);
3157         case MSR_IA32_XSS:
3158                 if (!msr_info->host_initiated &&
3159                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3160                         return 1;
3161                 msr_info->data = vcpu->arch.ia32_xss;
3162                 break;
3163         case MSR_K7_CLK_CTL:
3164                 /*
3165                  * Provide expected ramp-up count for K7. All other
3166                  * are set to zero, indicating minimum divisors for
3167                  * every field.
3168                  *
3169                  * This prevents guest kernels on AMD host with CPU
3170                  * type 6, model 8 and higher from exploding due to
3171                  * the rdmsr failing.
3172                  */
3173                 msr_info->data = 0x20000000;
3174                 break;
3175         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3176         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3177         case HV_X64_MSR_CRASH_CTL:
3178         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3179         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3180         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3181         case HV_X64_MSR_TSC_EMULATION_STATUS:
3182                 return kvm_hv_get_msr_common(vcpu,
3183                                              msr_info->index, &msr_info->data,
3184                                              msr_info->host_initiated);
3185         case MSR_IA32_BBL_CR_CTL3:
3186                 /* This legacy MSR exists but isn't fully documented in current
3187                  * silicon.  It is however accessed by winxp in very narrow
3188                  * scenarios where it sets bit #19, itself documented as
3189                  * a "reserved" bit.  Best effort attempt to source coherent
3190                  * read data here should the balance of the register be
3191                  * interpreted by the guest:
3192                  *
3193                  * L2 cache control register 3: 64GB range, 256KB size,
3194                  * enabled, latency 0x1, configured
3195                  */
3196                 msr_info->data = 0xbe702111;
3197                 break;
3198         case MSR_AMD64_OSVW_ID_LENGTH:
3199                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3200                         return 1;
3201                 msr_info->data = vcpu->arch.osvw.length;
3202                 break;
3203         case MSR_AMD64_OSVW_STATUS:
3204                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3205                         return 1;
3206                 msr_info->data = vcpu->arch.osvw.status;
3207                 break;
3208         case MSR_PLATFORM_INFO:
3209                 if (!msr_info->host_initiated &&
3210                     !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3211                         return 1;
3212                 msr_info->data = vcpu->arch.msr_platform_info;
3213                 break;
3214         case MSR_MISC_FEATURES_ENABLES:
3215                 msr_info->data = vcpu->arch.msr_misc_features_enables;
3216                 break;
3217         case MSR_K7_HWCR:
3218                 msr_info->data = vcpu->arch.msr_hwcr;
3219                 break;
3220         default:
3221                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3222                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3223                 if (!ignore_msrs) {
3224                         vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3225                                                msr_info->index);
3226                         return 1;
3227                 } else {
3228                         if (report_ignored_msrs)
3229                                 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3230                                         msr_info->index);
3231                         msr_info->data = 0;
3232                 }
3233                 break;
3234         }
3235         return 0;
3236 }
3237 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3238
3239 /*
3240  * Read or write a bunch of msrs. All parameters are kernel addresses.
3241  *
3242  * @return number of msrs set successfully.
3243  */
3244 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3245                     struct kvm_msr_entry *entries,
3246                     int (*do_msr)(struct kvm_vcpu *vcpu,
3247                                   unsigned index, u64 *data))
3248 {
3249         int i;
3250
3251         for (i = 0; i < msrs->nmsrs; ++i)
3252                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3253                         break;
3254
3255         return i;
3256 }
3257
3258 /*
3259  * Read or write a bunch of msrs. Parameters are user addresses.
3260  *
3261  * @return number of msrs set successfully.
3262  */
3263 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3264                   int (*do_msr)(struct kvm_vcpu *vcpu,
3265                                 unsigned index, u64 *data),
3266                   int writeback)
3267 {
3268         struct kvm_msrs msrs;
3269         struct kvm_msr_entry *entries;
3270         int r, n;
3271         unsigned size;
3272
3273         r = -EFAULT;
3274         if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3275                 goto out;
3276
3277         r = -E2BIG;
3278         if (msrs.nmsrs >= MAX_IO_MSRS)
3279                 goto out;
3280
3281         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3282         entries = memdup_user(user_msrs->entries, size);
3283         if (IS_ERR(entries)) {
3284                 r = PTR_ERR(entries);
3285                 goto out;
3286         }
3287
3288         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3289         if (r < 0)
3290                 goto out_free;
3291
3292         r = -EFAULT;
3293         if (writeback && copy_to_user(user_msrs->entries, entries, size))
3294                 goto out_free;
3295
3296         r = n;
3297
3298 out_free:
3299         kfree(entries);
3300 out:
3301         return r;
3302 }
3303
3304 static inline bool kvm_can_mwait_in_guest(void)
3305 {
3306         return boot_cpu_has(X86_FEATURE_MWAIT) &&
3307                 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3308                 boot_cpu_has(X86_FEATURE_ARAT);
3309 }
3310
3311 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3312 {
3313         int r = 0;
3314
3315         switch (ext) {
3316         case KVM_CAP_IRQCHIP:
3317         case KVM_CAP_HLT:
3318         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3319         case KVM_CAP_SET_TSS_ADDR:
3320         case KVM_CAP_EXT_CPUID:
3321         case KVM_CAP_EXT_EMUL_CPUID:
3322         case KVM_CAP_CLOCKSOURCE:
3323         case KVM_CAP_PIT:
3324         case KVM_CAP_NOP_IO_DELAY:
3325         case KVM_CAP_MP_STATE:
3326         case KVM_CAP_SYNC_MMU:
3327         case KVM_CAP_USER_NMI:
3328         case KVM_CAP_REINJECT_CONTROL:
3329         case KVM_CAP_IRQ_INJECT_STATUS:
3330         case KVM_CAP_IOEVENTFD:
3331         case KVM_CAP_IOEVENTFD_NO_LENGTH:
3332         case KVM_CAP_PIT2:
3333         case KVM_CAP_PIT_STATE2:
3334         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3335         case KVM_CAP_XEN_HVM:
3336         case KVM_CAP_VCPU_EVENTS:
3337         case KVM_CAP_HYPERV:
3338         case KVM_CAP_HYPERV_VAPIC:
3339         case KVM_CAP_HYPERV_SPIN:
3340         case KVM_CAP_HYPERV_SYNIC:
3341         case KVM_CAP_HYPERV_SYNIC2:
3342         case KVM_CAP_HYPERV_VP_INDEX:
3343         case KVM_CAP_HYPERV_EVENTFD:
3344         case KVM_CAP_HYPERV_TLBFLUSH:
3345         case KVM_CAP_HYPERV_SEND_IPI:
3346         case KVM_CAP_HYPERV_CPUID:
3347         case KVM_CAP_PCI_SEGMENT:
3348         case KVM_CAP_DEBUGREGS:
3349         case KVM_CAP_X86_ROBUST_SINGLESTEP:
3350         case KVM_CAP_XSAVE:
3351         case KVM_CAP_ASYNC_PF:
3352         case KVM_CAP_GET_TSC_KHZ:
3353         case KVM_CAP_KVMCLOCK_CTRL:
3354         case KVM_CAP_READONLY_MEM:
3355         case KVM_CAP_HYPERV_TIME:
3356         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3357         case KVM_CAP_TSC_DEADLINE_TIMER:
3358         case KVM_CAP_DISABLE_QUIRKS:
3359         case KVM_CAP_SET_BOOT_CPU_ID:
3360         case KVM_CAP_SPLIT_IRQCHIP:
3361         case KVM_CAP_IMMEDIATE_EXIT:
3362         case KVM_CAP_PMU_EVENT_FILTER:
3363         case KVM_CAP_GET_MSR_FEATURES:
3364         case KVM_CAP_MSR_PLATFORM_INFO:
3365         case KVM_CAP_EXCEPTION_PAYLOAD:
3366         case KVM_CAP_SET_GUEST_DEBUG:
3367                 r = 1;
3368                 break;
3369         case KVM_CAP_SYNC_REGS:
3370                 r = KVM_SYNC_X86_VALID_FIELDS;
3371                 break;
3372         case KVM_CAP_ADJUST_CLOCK:
3373                 r = KVM_CLOCK_TSC_STABLE;
3374                 break;
3375         case KVM_CAP_X86_DISABLE_EXITS:
3376                 r |=  KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3377                       KVM_X86_DISABLE_EXITS_CSTATE;
3378                 if(kvm_can_mwait_in_guest())
3379                         r |= KVM_X86_DISABLE_EXITS_MWAIT;
3380                 break;
3381         case KVM_CAP_X86_SMM:
3382                 /* SMBASE is usually relocated above 1M on modern chipsets,
3383                  * and SMM handlers might indeed rely on 4G segment limits,
3384                  * so do not report SMM to be available if real mode is
3385                  * emulated via vm86 mode.  Still, do not go to great lengths
3386                  * to avoid userspace's usage of the feature, because it is a
3387                  * fringe case that is not enabled except via specific settings
3388                  * of the module parameters.
3389                  */
3390                 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3391                 break;
3392         case KVM_CAP_VAPIC:
3393                 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3394                 break;
3395         case KVM_CAP_NR_VCPUS:
3396                 r = KVM_SOFT_MAX_VCPUS;
3397                 break;
3398         case KVM_CAP_MAX_VCPUS:
3399                 r = KVM_MAX_VCPUS;
3400                 break;
3401         case KVM_CAP_MAX_VCPU_ID:
3402                 r = KVM_MAX_VCPU_ID;
3403                 break;
3404         case KVM_CAP_PV_MMU:    /* obsolete */
3405                 r = 0;
3406                 break;
3407         case KVM_CAP_MCE:
3408                 r = KVM_MAX_MCE_BANKS;
3409                 break;
3410         case KVM_CAP_XCRS:
3411                 r = boot_cpu_has(X86_FEATURE_XSAVE);
3412                 break;
3413         case KVM_CAP_TSC_CONTROL:
3414                 r = kvm_has_tsc_control;
3415                 break;
3416         case KVM_CAP_X2APIC_API:
3417                 r = KVM_X2APIC_API_VALID_FLAGS;
3418                 break;
3419         case KVM_CAP_NESTED_STATE:
3420                 r = kvm_x86_ops.get_nested_state ?
3421                         kvm_x86_ops.get_nested_state(NULL, NULL, 0) : 0;
3422                 break;
3423         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3424                 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3425                 break;
3426         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3427                 r = kvm_x86_ops.nested_enable_evmcs != NULL;
3428                 break;
3429         default:
3430                 break;
3431         }
3432         return r;
3433
3434 }
3435
3436 long kvm_arch_dev_ioctl(struct file *filp,
3437                         unsigned int ioctl, unsigned long arg)
3438 {
3439         void __user *argp = (void __user *)arg;
3440         long r;
3441
3442         switch (ioctl) {
3443         case KVM_GET_MSR_INDEX_LIST: {
3444                 struct kvm_msr_list __user *user_msr_list = argp;
3445                 struct kvm_msr_list msr_list;
3446                 unsigned n;
3447
3448                 r = -EFAULT;
3449                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3450                         goto out;
3451                 n = msr_list.nmsrs;
3452                 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3453                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3454                         goto out;
3455                 r = -E2BIG;
3456                 if (n < msr_list.nmsrs)
3457                         goto out;
3458                 r = -EFAULT;
3459                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3460                                  num_msrs_to_save * sizeof(u32)))
3461                         goto out;
3462                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3463                                  &emulated_msrs,
3464                                  num_emulated_msrs * sizeof(u32)))
3465                         goto out;
3466                 r = 0;
3467                 break;
3468         }
3469         case KVM_GET_SUPPORTED_CPUID:
3470         case KVM_GET_EMULATED_CPUID: {
3471                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3472                 struct kvm_cpuid2 cpuid;
3473
3474                 r = -EFAULT;
3475                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3476                         goto out;
3477
3478                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3479                                             ioctl);
3480                 if (r)
3481                         goto out;
3482
3483                 r = -EFAULT;
3484                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3485                         goto out;
3486                 r = 0;
3487                 break;
3488         }
3489         case KVM_X86_GET_MCE_CAP_SUPPORTED:
3490                 r = -EFAULT;
3491                 if (copy_to_user(argp, &kvm_mce_cap_supported,
3492                                  sizeof(kvm_mce_cap_supported)))
3493                         goto out;
3494                 r = 0;
3495                 break;
3496         case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3497                 struct kvm_msr_list __user *user_msr_list = argp;
3498                 struct kvm_msr_list msr_list;
3499                 unsigned int n;
3500
3501                 r = -EFAULT;
3502                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3503                         goto out;
3504                 n = msr_list.nmsrs;
3505                 msr_list.nmsrs = num_msr_based_features;
3506                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3507                         goto out;
3508                 r = -E2BIG;
3509                 if (n < msr_list.nmsrs)
3510                         goto out;
3511                 r = -EFAULT;
3512                 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3513                                  num_msr_based_features * sizeof(u32)))
3514                         goto out;
3515                 r = 0;
3516                 break;
3517         }
3518         case KVM_GET_MSRS:
3519                 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3520                 break;
3521         default:
3522                 r = -EINVAL;
3523                 break;
3524         }
3525 out:
3526         return r;
3527 }
3528
3529 static void wbinvd_ipi(void *garbage)
3530 {
3531         wbinvd();
3532 }
3533
3534 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3535 {
3536         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3537 }
3538
3539 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3540 {
3541         /* Address WBINVD may be executed by guest */
3542         if (need_emulate_wbinvd(vcpu)) {
3543                 if (kvm_x86_ops.has_wbinvd_exit())
3544                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3545                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3546                         smp_call_function_single(vcpu->cpu,
3547                                         wbinvd_ipi, NULL, 1);
3548         }
3549
3550         kvm_x86_ops.vcpu_load(vcpu, cpu);
3551
3552         /* Apply any externally detected TSC adjustments (due to suspend) */
3553         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3554                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3555                 vcpu->arch.tsc_offset_adjustment = 0;
3556                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3557         }
3558
3559         if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3560                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3561                                 rdtsc() - vcpu->arch.last_host_tsc;
3562                 if (tsc_delta < 0)
3563                         mark_tsc_unstable("KVM discovered backwards TSC");
3564
3565                 if (kvm_check_tsc_unstable()) {
3566                         u64 offset = kvm_compute_tsc_offset(vcpu,
3567                                                 vcpu->arch.last_guest_tsc);
3568                         kvm_vcpu_write_tsc_offset(vcpu, offset);
3569                         vcpu->arch.tsc_catchup = 1;
3570                 }
3571
3572                 if (kvm_lapic_hv_timer_in_use(vcpu))
3573                         kvm_lapic_restart_hv_timer(vcpu);
3574
3575                 /*
3576                  * On a host with synchronized TSC, there is no need to update
3577                  * kvmclock on vcpu->cpu migration
3578                  */
3579                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3580                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3581                 if (vcpu->cpu != cpu)
3582                         kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3583                 vcpu->cpu = cpu;
3584         }
3585
3586         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3587 }
3588
3589 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3590 {
3591         struct kvm_host_map map;
3592         struct kvm_steal_time *st;
3593
3594         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3595                 return;
3596
3597         if (vcpu->arch.st.preempted)
3598                 return;
3599
3600         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3601                         &vcpu->arch.st.cache, true))
3602                 return;
3603
3604         st = map.hva +
3605                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3606
3607         st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3608
3609         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3610 }
3611
3612 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3613 {
3614         int idx;
3615
3616         if (vcpu->preempted)
3617                 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
3618
3619         /*
3620          * Disable page faults because we're in atomic context here.
3621          * kvm_write_guest_offset_cached() would call might_fault()
3622          * that relies on pagefault_disable() to tell if there's a
3623          * bug. NOTE: the write to guest memory may not go through if
3624          * during postcopy live migration or if there's heavy guest
3625          * paging.
3626          */
3627         pagefault_disable();
3628         /*
3629          * kvm_memslots() will be called by
3630          * kvm_write_guest_offset_cached() so take the srcu lock.
3631          */
3632         idx = srcu_read_lock(&vcpu->kvm->srcu);
3633         kvm_steal_time_set_preempted(vcpu);
3634         srcu_read_unlock(&vcpu->kvm->srcu, idx);
3635         pagefault_enable();
3636         kvm_x86_ops.vcpu_put(vcpu);
3637         vcpu->arch.last_host_tsc = rdtsc();
3638         /*
3639          * If userspace has set any breakpoints or watchpoints, dr6 is restored
3640          * on every vmexit, but if not, we might have a stale dr6 from the
3641          * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3642          */
3643         set_debugreg(0, 6);
3644 }
3645
3646 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3647                                     struct kvm_lapic_state *s)
3648 {
3649         if (vcpu->arch.apicv_active)
3650                 kvm_x86_ops.sync_pir_to_irr(vcpu);
3651
3652         return kvm_apic_get_state(vcpu, s);
3653 }
3654
3655 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3656                                     struct kvm_lapic_state *s)
3657 {
3658         int r;
3659
3660         r = kvm_apic_set_state(vcpu, s);
3661         if (r)
3662                 return r;
3663         update_cr8_intercept(vcpu);
3664
3665         return 0;
3666 }
3667
3668 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3669 {
3670         return (!lapic_in_kernel(vcpu) ||
3671                 kvm_apic_accept_pic_intr(vcpu));
3672 }
3673
3674 /*
3675  * if userspace requested an interrupt window, check that the
3676  * interrupt window is open.
3677  *
3678  * No need to exit to userspace if we already have an interrupt queued.
3679  */
3680 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3681 {
3682         return kvm_arch_interrupt_allowed(vcpu) &&
3683                 !kvm_cpu_has_interrupt(vcpu) &&
3684                 !kvm_event_needs_reinjection(vcpu) &&
3685                 kvm_cpu_accept_dm_intr(vcpu);
3686 }
3687
3688 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3689                                     struct kvm_interrupt *irq)
3690 {
3691         if (irq->irq >= KVM_NR_INTERRUPTS)
3692                 return -EINVAL;
3693
3694         if (!irqchip_in_kernel(vcpu->kvm)) {
3695                 kvm_queue_interrupt(vcpu, irq->irq, false);
3696                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3697                 return 0;
3698         }
3699
3700         /*
3701          * With in-kernel LAPIC, we only use this to inject EXTINT, so
3702          * fail for in-kernel 8259.
3703          */
3704         if (pic_in_kernel(vcpu->kvm))
3705                 return -ENXIO;
3706
3707         if (vcpu->arch.pending_external_vector != -1)
3708                 return -EEXIST;
3709
3710         vcpu->arch.pending_external_vector = irq->irq;
3711         kvm_make_request(KVM_REQ_EVENT, vcpu);
3712         return 0;
3713 }
3714
3715 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3716 {
3717         kvm_inject_nmi(vcpu);
3718
3719         return 0;
3720 }
3721
3722 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3723 {
3724         kvm_make_request(KVM_REQ_SMI, vcpu);
3725
3726         return 0;
3727 }
3728
3729 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3730                                            struct kvm_tpr_access_ctl *tac)
3731 {
3732         if (tac->flags)
3733                 return -EINVAL;
3734         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3735         return 0;
3736 }
3737
3738 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3739                                         u64 mcg_cap)
3740 {
3741         int r;
3742         unsigned bank_num = mcg_cap & 0xff, bank;
3743
3744         r = -EINVAL;
3745         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3746                 goto out;
3747         if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3748                 goto out;
3749         r = 0;
3750         vcpu->arch.mcg_cap = mcg_cap;
3751         /* Init IA32_MCG_CTL to all 1s */
3752         if (mcg_cap & MCG_CTL_P)
3753                 vcpu->arch.mcg_ctl = ~(u64)0;
3754         /* Init IA32_MCi_CTL to all 1s */
3755         for (bank = 0; bank < bank_num; bank++)
3756                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3757
3758         kvm_x86_ops.setup_mce(vcpu);
3759 out:
3760         return r;
3761 }
3762
3763 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3764                                       struct kvm_x86_mce *mce)
3765 {
3766         u64 mcg_cap = vcpu->arch.mcg_cap;
3767         unsigned bank_num = mcg_cap & 0xff;
3768         u64 *banks = vcpu->arch.mce_banks;
3769
3770         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3771                 return -EINVAL;
3772         /*
3773          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3774          * reporting is disabled
3775          */
3776         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3777             vcpu->arch.mcg_ctl != ~(u64)0)
3778                 return 0;
3779         banks += 4 * mce->bank;
3780         /*
3781          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3782          * reporting is disabled for the bank
3783          */
3784         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3785                 return 0;
3786         if (mce->status & MCI_STATUS_UC) {
3787                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3788                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3789                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3790                         return 0;
3791                 }
3792                 if (banks[1] & MCI_STATUS_VAL)
3793                         mce->status |= MCI_STATUS_OVER;
3794                 banks[2] = mce->addr;
3795                 banks[3] = mce->misc;
3796                 vcpu->arch.mcg_status = mce->mcg_status;
3797                 banks[1] = mce->status;
3798                 kvm_queue_exception(vcpu, MC_VECTOR);
3799         } else if (!(banks[1] & MCI_STATUS_VAL)
3800                    || !(banks[1] & MCI_STATUS_UC)) {
3801                 if (banks[1] & MCI_STATUS_VAL)
3802                         mce->status |= MCI_STATUS_OVER;
3803                 banks[2] = mce->addr;
3804                 banks[3] = mce->misc;
3805                 banks[1] = mce->status;
3806         } else
3807                 banks[1] |= MCI_STATUS_OVER;
3808         return 0;
3809 }
3810
3811 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3812                                                struct kvm_vcpu_events *events)
3813 {
3814         process_nmi(vcpu);
3815
3816         /*
3817          * In guest mode, payload delivery should be deferred,
3818          * so that the L1 hypervisor can intercept #PF before
3819          * CR2 is modified (or intercept #DB before DR6 is
3820          * modified under nVMX). Unless the per-VM capability,
3821          * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3822          * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3823          * opportunistically defer the exception payload, deliver it if the
3824          * capability hasn't been requested before processing a
3825          * KVM_GET_VCPU_EVENTS.
3826          */
3827         if (!vcpu->kvm->arch.exception_payload_enabled &&
3828             vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3829                 kvm_deliver_exception_payload(vcpu);
3830
3831         /*
3832          * The API doesn't provide the instruction length for software
3833          * exceptions, so don't report them. As long as the guest RIP
3834          * isn't advanced, we should expect to encounter the exception
3835          * again.
3836          */
3837         if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3838                 events->exception.injected = 0;
3839                 events->exception.pending = 0;
3840         } else {
3841                 events->exception.injected = vcpu->arch.exception.injected;
3842                 events->exception.pending = vcpu->arch.exception.pending;
3843                 /*
3844                  * For ABI compatibility, deliberately conflate
3845                  * pending and injected exceptions when
3846                  * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3847                  */
3848                 if (!vcpu->kvm->arch.exception_payload_enabled)
3849                         events->exception.injected |=
3850                                 vcpu->arch.exception.pending;
3851         }
3852         events->exception.nr = vcpu->arch.exception.nr;
3853         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3854         events->exception.error_code = vcpu->arch.exception.error_code;
3855         events->exception_has_payload = vcpu->arch.exception.has_payload;
3856         events->exception_payload = vcpu->arch.exception.payload;
3857
3858         events->interrupt.injected =
3859                 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3860         events->interrupt.nr = vcpu->arch.interrupt.nr;
3861         events->interrupt.soft = 0;
3862         events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
3863
3864         events->nmi.injected = vcpu->arch.nmi_injected;
3865         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3866         events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
3867         events->nmi.pad = 0;
3868
3869         events->sipi_vector = 0; /* never valid when reporting to user space */
3870
3871         events->smi.smm = is_smm(vcpu);
3872         events->smi.pending = vcpu->arch.smi_pending;
3873         events->smi.smm_inside_nmi =
3874                 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3875         events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3876
3877         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3878                          | KVM_VCPUEVENT_VALID_SHADOW
3879                          | KVM_VCPUEVENT_VALID_SMM);
3880         if (vcpu->kvm->arch.exception_payload_enabled)
3881                 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3882
3883         memset(&events->reserved, 0, sizeof(events->reserved));
3884 }
3885
3886 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3887
3888 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3889                                               struct kvm_vcpu_events *events)
3890 {
3891         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3892                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3893                               | KVM_VCPUEVENT_VALID_SHADOW
3894                               | KVM_VCPUEVENT_VALID_SMM
3895                               | KVM_VCPUEVENT_VALID_PAYLOAD))
3896                 return -EINVAL;
3897
3898         if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3899                 if (!vcpu->kvm->arch.exception_payload_enabled)
3900                         return -EINVAL;
3901                 if (events->exception.pending)
3902                         events->exception.injected = 0;
3903                 else
3904                         events->exception_has_payload = 0;
3905         } else {
3906                 events->exception.pending = 0;
3907                 events->exception_has_payload = 0;
3908         }
3909
3910         if ((events->exception.injected || events->exception.pending) &&
3911             (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3912                 return -EINVAL;
3913
3914         /* INITs are latched while in SMM */
3915         if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3916             (events->smi.smm || events->smi.pending) &&
3917             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3918                 return -EINVAL;
3919
3920         process_nmi(vcpu);
3921         vcpu->arch.exception.injected = events->exception.injected;
3922         vcpu->arch.exception.pending = events->exception.pending;
3923         vcpu->arch.exception.nr = events->exception.nr;
3924         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3925         vcpu->arch.exception.error_code = events->exception.error_code;
3926         vcpu->arch.exception.has_payload = events->exception_has_payload;
3927         vcpu->arch.exception.payload = events->exception_payload;
3928
3929         vcpu->arch.interrupt.injected = events->interrupt.injected;
3930         vcpu->arch.interrupt.nr = events->interrupt.nr;
3931         vcpu->arch.interrupt.soft = events->interrupt.soft;
3932         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3933                 kvm_x86_ops.set_interrupt_shadow(vcpu,
3934                                                   events->interrupt.shadow);
3935
3936         vcpu->arch.nmi_injected = events->nmi.injected;
3937         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3938                 vcpu->arch.nmi_pending = events->nmi.pending;
3939         kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
3940
3941         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3942             lapic_in_kernel(vcpu))
3943                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3944
3945         if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3946                 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3947                         if (events->smi.smm)
3948                                 vcpu->arch.hflags |= HF_SMM_MASK;
3949                         else
3950                                 vcpu->arch.hflags &= ~HF_SMM_MASK;
3951                         kvm_smm_changed(vcpu);
3952                 }
3953
3954                 vcpu->arch.smi_pending = events->smi.pending;
3955
3956                 if (events->smi.smm) {
3957                         if (events->smi.smm_inside_nmi)
3958                                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3959                         else
3960                                 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3961                 }
3962
3963                 if (lapic_in_kernel(vcpu)) {
3964                         if (events->smi.latched_init)
3965                                 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3966                         else
3967                                 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3968                 }
3969         }
3970
3971         kvm_make_request(KVM_REQ_EVENT, vcpu);
3972
3973         return 0;
3974 }
3975
3976 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3977                                              struct kvm_debugregs *dbgregs)
3978 {
3979         unsigned long val;
3980
3981         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3982         kvm_get_dr(vcpu, 6, &val);
3983         dbgregs->dr6 = val;
3984         dbgregs->dr7 = vcpu->arch.dr7;
3985         dbgregs->flags = 0;
3986         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3987 }
3988
3989 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3990                                             struct kvm_debugregs *dbgregs)
3991 {
3992         if (dbgregs->flags)
3993                 return -EINVAL;
3994
3995         if (dbgregs->dr6 & ~0xffffffffull)
3996                 return -EINVAL;
3997         if (dbgregs->dr7 & ~0xffffffffull)
3998                 return -EINVAL;
3999
4000         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4001         kvm_update_dr0123(vcpu);
4002         vcpu->arch.dr6 = dbgregs->dr6;
4003         vcpu->arch.dr7 = dbgregs->dr7;
4004         kvm_update_dr7(vcpu);
4005
4006         return 0;
4007 }
4008
4009 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4010
4011 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4012 {
4013         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4014         u64 xstate_bv = xsave->header.xfeatures;
4015         u64 valid;
4016
4017         /*
4018          * Copy legacy XSAVE area, to avoid complications with CPUID
4019          * leaves 0 and 1 in the loop below.
4020          */
4021         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4022
4023         /* Set XSTATE_BV */
4024         xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4025         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4026
4027         /*
4028          * Copy each region from the possibly compacted offset to the
4029          * non-compacted offset.
4030          */
4031         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4032         while (valid) {
4033                 u64 xfeature_mask = valid & -valid;
4034                 int xfeature_nr = fls64(xfeature_mask) - 1;
4035                 void *src = get_xsave_addr(xsave, xfeature_nr);
4036
4037                 if (src) {
4038                         u32 size, offset, ecx, edx;
4039                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4040                                     &size, &offset, &ecx, &edx);
4041                         if (xfeature_nr == XFEATURE_PKRU)
4042                                 memcpy(dest + offset, &vcpu->arch.pkru,
4043                                        sizeof(vcpu->arch.pkru));
4044                         else
4045                                 memcpy(dest + offset, src, size);
4046
4047                 }
4048
4049                 valid -= xfeature_mask;
4050         }
4051 }
4052
4053 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4054 {
4055         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4056         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4057         u64 valid;
4058
4059         /*
4060          * Copy legacy XSAVE area, to avoid complications with CPUID
4061          * leaves 0 and 1 in the loop below.
4062          */
4063         memcpy(xsave, src, XSAVE_HDR_OFFSET);
4064
4065         /* Set XSTATE_BV and possibly XCOMP_BV.  */
4066         xsave->header.xfeatures = xstate_bv;
4067         if (boot_cpu_has(X86_FEATURE_XSAVES))
4068                 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4069
4070         /*
4071          * Copy each region from the non-compacted offset to the
4072          * possibly compacted offset.
4073          */
4074         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4075         while (valid) {
4076                 u64 xfeature_mask = valid & -valid;
4077                 int xfeature_nr = fls64(xfeature_mask) - 1;
4078                 void *dest = get_xsave_addr(xsave, xfeature_nr);
4079
4080                 if (dest) {
4081                         u32 size, offset, ecx, edx;
4082                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4083                                     &size, &offset, &ecx, &edx);
4084                         if (xfeature_nr == XFEATURE_PKRU)
4085                                 memcpy(&vcpu->arch.pkru, src + offset,
4086                                        sizeof(vcpu->arch.pkru));
4087                         else
4088                                 memcpy(dest, src + offset, size);
4089                 }
4090
4091                 valid -= xfeature_mask;
4092         }
4093 }
4094
4095 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4096                                          struct kvm_xsave *guest_xsave)
4097 {
4098         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4099                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4100                 fill_xsave((u8 *) guest_xsave->region, vcpu);
4101         } else {
4102                 memcpy(guest_xsave->region,
4103                         &vcpu->arch.guest_fpu->state.fxsave,
4104                         sizeof(struct fxregs_state));
4105                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4106                         XFEATURE_MASK_FPSSE;
4107         }
4108 }
4109
4110 #define XSAVE_MXCSR_OFFSET 24
4111
4112 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4113                                         struct kvm_xsave *guest_xsave)
4114 {
4115         u64 xstate_bv =
4116                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4117         u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4118
4119         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4120                 /*
4121                  * Here we allow setting states that are not present in
4122                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
4123                  * with old userspace.
4124                  */
4125                 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4126                         return -EINVAL;
4127                 load_xsave(vcpu, (u8 *)guest_xsave->region);
4128         } else {
4129                 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4130                         mxcsr & ~mxcsr_feature_mask)
4131                         return -EINVAL;
4132                 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4133                         guest_xsave->region, sizeof(struct fxregs_state));
4134         }
4135         return 0;
4136 }
4137
4138 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4139                                         struct kvm_xcrs *guest_xcrs)
4140 {
4141         if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4142                 guest_xcrs->nr_xcrs = 0;
4143                 return;
4144         }
4145
4146         guest_xcrs->nr_xcrs = 1;
4147         guest_xcrs->flags = 0;
4148         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4149         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4150 }
4151
4152 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4153                                        struct kvm_xcrs *guest_xcrs)
4154 {
4155         int i, r = 0;
4156
4157         if (!boot_cpu_has(X86_FEATURE_XSAVE))
4158                 return -EINVAL;
4159
4160         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4161                 return -EINVAL;
4162
4163         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4164                 /* Only support XCR0 currently */
4165                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4166                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4167                                 guest_xcrs->xcrs[i].value);
4168                         break;
4169                 }
4170         if (r)
4171                 r = -EINVAL;
4172         return r;
4173 }
4174
4175 /*
4176  * kvm_set_guest_paused() indicates to the guest kernel that it has been
4177  * stopped by the hypervisor.  This function will be called from the host only.
4178  * EINVAL is returned when the host attempts to set the flag for a guest that
4179  * does not support pv clocks.
4180  */
4181 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4182 {
4183         if (!vcpu->arch.pv_time_enabled)
4184                 return -EINVAL;
4185         vcpu->arch.pvclock_set_guest_stopped_request = true;
4186         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4187         return 0;
4188 }
4189
4190 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4191                                      struct kvm_enable_cap *cap)
4192 {
4193         int r;
4194         uint16_t vmcs_version;
4195         void __user *user_ptr;
4196
4197         if (cap->flags)
4198                 return -EINVAL;
4199
4200         switch (cap->cap) {
4201         case KVM_CAP_HYPERV_SYNIC2:
4202                 if (cap->args[0])
4203                         return -EINVAL;
4204                 /* fall through */
4205
4206         case KVM_CAP_HYPERV_SYNIC:
4207                 if (!irqchip_in_kernel(vcpu->kvm))
4208                         return -EINVAL;
4209                 return kvm_hv_activate_synic(vcpu, cap->cap ==
4210                                              KVM_CAP_HYPERV_SYNIC2);
4211         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4212                 if (!kvm_x86_ops.nested_enable_evmcs)
4213                         return -ENOTTY;
4214                 r = kvm_x86_ops.nested_enable_evmcs(vcpu, &vmcs_version);
4215                 if (!r) {
4216                         user_ptr = (void __user *)(uintptr_t)cap->args[0];
4217                         if (copy_to_user(user_ptr, &vmcs_version,
4218                                          sizeof(vmcs_version)))
4219                                 r = -EFAULT;
4220                 }
4221                 return r;
4222         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4223                 if (!kvm_x86_ops.enable_direct_tlbflush)
4224                         return -ENOTTY;
4225
4226                 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4227
4228         default:
4229                 return -EINVAL;
4230         }
4231 }
4232
4233 long kvm_arch_vcpu_ioctl(struct file *filp,
4234                          unsigned int ioctl, unsigned long arg)
4235 {
4236         struct kvm_vcpu *vcpu = filp->private_data;
4237         void __user *argp = (void __user *)arg;
4238         int r;
4239         union {
4240                 struct kvm_lapic_state *lapic;
4241                 struct kvm_xsave *xsave;
4242                 struct kvm_xcrs *xcrs;
4243                 void *buffer;
4244         } u;
4245
4246         vcpu_load(vcpu);
4247
4248         u.buffer = NULL;
4249         switch (ioctl) {
4250         case KVM_GET_LAPIC: {
4251                 r = -EINVAL;
4252                 if (!lapic_in_kernel(vcpu))
4253                         goto out;
4254                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4255                                 GFP_KERNEL_ACCOUNT);
4256
4257                 r = -ENOMEM;
4258                 if (!u.lapic)
4259                         goto out;
4260                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4261                 if (r)
4262                         goto out;
4263                 r = -EFAULT;
4264                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4265                         goto out;
4266                 r = 0;
4267                 break;
4268         }
4269         case KVM_SET_LAPIC: {
4270                 r = -EINVAL;
4271                 if (!lapic_in_kernel(vcpu))
4272                         goto out;
4273                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4274                 if (IS_ERR(u.lapic)) {
4275                         r = PTR_ERR(u.lapic);
4276                         goto out_nofree;
4277                 }
4278
4279                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4280                 break;
4281         }
4282         case KVM_INTERRUPT: {
4283                 struct kvm_interrupt irq;
4284
4285                 r = -EFAULT;
4286                 if (copy_from_user(&irq, argp, sizeof(irq)))
4287                         goto out;
4288                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4289                 break;
4290         }
4291         case KVM_NMI: {
4292                 r = kvm_vcpu_ioctl_nmi(vcpu);
4293                 break;
4294         }
4295         case KVM_SMI: {
4296                 r = kvm_vcpu_ioctl_smi(vcpu);
4297                 break;
4298         }
4299         case KVM_SET_CPUID: {
4300                 struct kvm_cpuid __user *cpuid_arg = argp;
4301                 struct kvm_cpuid cpuid;
4302
4303                 r = -EFAULT;
4304                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4305                         goto out;
4306                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4307                 break;
4308         }
4309         case KVM_SET_CPUID2: {
4310                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4311                 struct kvm_cpuid2 cpuid;
4312
4313                 r = -EFAULT;
4314                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4315                         goto out;
4316                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4317                                               cpuid_arg->entries);
4318                 break;
4319         }
4320         case KVM_GET_CPUID2: {
4321                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4322                 struct kvm_cpuid2 cpuid;
4323
4324                 r = -EFAULT;
4325                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4326                         goto out;
4327                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4328                                               cpuid_arg->entries);
4329                 if (r)
4330                         goto out;
4331                 r = -EFAULT;
4332                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4333                         goto out;
4334                 r = 0;
4335                 break;
4336         }
4337         case KVM_GET_MSRS: {
4338                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4339                 r = msr_io(vcpu, argp, do_get_msr, 1);
4340                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4341                 break;
4342         }
4343         case KVM_SET_MSRS: {
4344                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4345                 r = msr_io(vcpu, argp, do_set_msr, 0);
4346                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4347                 break;
4348         }
4349         case KVM_TPR_ACCESS_REPORTING: {
4350                 struct kvm_tpr_access_ctl tac;
4351
4352                 r = -EFAULT;
4353                 if (copy_from_user(&tac, argp, sizeof(tac)))
4354                         goto out;
4355                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4356                 if (r)
4357                         goto out;
4358                 r = -EFAULT;
4359                 if (copy_to_user(argp, &tac, sizeof(tac)))
4360                         goto out;
4361                 r = 0;
4362                 break;
4363         };
4364         case KVM_SET_VAPIC_ADDR: {
4365                 struct kvm_vapic_addr va;
4366                 int idx;
4367
4368                 r = -EINVAL;
4369                 if (!lapic_in_kernel(vcpu))
4370                         goto out;
4371                 r = -EFAULT;
4372                 if (copy_from_user(&va, argp, sizeof(va)))
4373                         goto out;
4374                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4375                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4376                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4377                 break;
4378         }
4379         case KVM_X86_SETUP_MCE: {
4380                 u64 mcg_cap;
4381
4382                 r = -EFAULT;
4383                 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4384                         goto out;
4385                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4386                 break;
4387         }
4388         case KVM_X86_SET_MCE: {
4389                 struct kvm_x86_mce mce;
4390
4391                 r = -EFAULT;
4392                 if (copy_from_user(&mce, argp, sizeof(mce)))
4393                         goto out;
4394                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4395                 break;
4396         }
4397         case KVM_GET_VCPU_EVENTS: {
4398                 struct kvm_vcpu_events events;
4399
4400                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4401
4402                 r = -EFAULT;
4403                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4404                         break;
4405                 r = 0;
4406                 break;
4407         }
4408         case KVM_SET_VCPU_EVENTS: {
4409                 struct kvm_vcpu_events events;
4410
4411                 r = -EFAULT;
4412                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4413                         break;
4414
4415                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4416                 break;
4417         }
4418         case KVM_GET_DEBUGREGS: {
4419                 struct kvm_debugregs dbgregs;
4420
4421                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4422
4423                 r = -EFAULT;
4424                 if (copy_to_user(argp, &dbgregs,
4425                                  sizeof(struct kvm_debugregs)))
4426                         break;
4427                 r = 0;
4428                 break;
4429         }
4430         case KVM_SET_DEBUGREGS: {
4431                 struct kvm_debugregs dbgregs;
4432
4433                 r = -EFAULT;
4434                 if (copy_from_user(&dbgregs, argp,
4435                                    sizeof(struct kvm_debugregs)))
4436                         break;
4437
4438                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4439                 break;
4440         }
4441         case KVM_GET_XSAVE: {
4442                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4443                 r = -ENOMEM;
4444                 if (!u.xsave)
4445                         break;
4446
4447                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4448
4449                 r = -EFAULT;
4450                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4451                         break;
4452                 r = 0;
4453                 break;
4454         }
4455         case KVM_SET_XSAVE: {
4456                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4457                 if (IS_ERR(u.xsave)) {
4458                         r = PTR_ERR(u.xsave);
4459                         goto out_nofree;
4460                 }
4461
4462                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4463                 break;
4464         }
4465         case KVM_GET_XCRS: {
4466                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4467                 r = -ENOMEM;
4468                 if (!u.xcrs)
4469                         break;
4470
4471                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4472
4473                 r = -EFAULT;
4474                 if (copy_to_user(argp, u.xcrs,
4475                                  sizeof(struct kvm_xcrs)))
4476                         break;
4477                 r = 0;
4478                 break;
4479         }
4480         case KVM_SET_XCRS: {
4481                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4482                 if (IS_ERR(u.xcrs)) {
4483                         r = PTR_ERR(u.xcrs);
4484                         goto out_nofree;
4485                 }
4486
4487                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4488                 break;
4489         }
4490         case KVM_SET_TSC_KHZ: {
4491                 u32 user_tsc_khz;
4492
4493                 r = -EINVAL;
4494                 user_tsc_khz = (u32)arg;
4495
4496                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4497                         goto out;
4498
4499                 if (user_tsc_khz == 0)
4500                         user_tsc_khz = tsc_khz;
4501
4502                 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4503                         r = 0;
4504
4505                 goto out;
4506         }
4507         case KVM_GET_TSC_KHZ: {
4508                 r = vcpu->arch.virtual_tsc_khz;
4509                 goto out;
4510         }
4511         case KVM_KVMCLOCK_CTRL: {
4512                 r = kvm_set_guest_paused(vcpu);
4513                 goto out;
4514         }
4515         case KVM_ENABLE_CAP: {
4516                 struct kvm_enable_cap cap;
4517
4518                 r = -EFAULT;
4519                 if (copy_from_user(&cap, argp, sizeof(cap)))
4520                         goto out;
4521                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4522                 break;
4523         }
4524         case KVM_GET_NESTED_STATE: {
4525                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4526                 u32 user_data_size;
4527
4528                 r = -EINVAL;
4529                 if (!kvm_x86_ops.get_nested_state)
4530                         break;
4531
4532                 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4533                 r = -EFAULT;
4534                 if (get_user(user_data_size, &user_kvm_nested_state->size))
4535                         break;
4536
4537                 r = kvm_x86_ops.get_nested_state(vcpu, user_kvm_nested_state,
4538                                                   user_data_size);
4539                 if (r < 0)
4540                         break;
4541
4542                 if (r > user_data_size) {
4543                         if (put_user(r, &user_kvm_nested_state->size))
4544                                 r = -EFAULT;
4545                         else
4546                                 r = -E2BIG;
4547                         break;
4548                 }
4549
4550                 r = 0;
4551                 break;
4552         }
4553         case KVM_SET_NESTED_STATE: {
4554                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4555                 struct kvm_nested_state kvm_state;
4556                 int idx;
4557
4558                 r = -EINVAL;
4559                 if (!kvm_x86_ops.set_nested_state)
4560                         break;
4561
4562                 r = -EFAULT;
4563                 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4564                         break;
4565
4566                 r = -EINVAL;
4567                 if (kvm_state.size < sizeof(kvm_state))
4568                         break;
4569
4570                 if (kvm_state.flags &
4571                     ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4572                       | KVM_STATE_NESTED_EVMCS))
4573                         break;
4574
4575                 /* nested_run_pending implies guest_mode.  */
4576                 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4577                     && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4578                         break;
4579
4580                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4581                 r = kvm_x86_ops.set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4582                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4583                 break;
4584         }
4585         case KVM_GET_SUPPORTED_HV_CPUID: {
4586                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4587                 struct kvm_cpuid2 cpuid;
4588
4589                 r = -EFAULT;
4590                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4591                         goto out;
4592
4593                 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4594                                                 cpuid_arg->entries);
4595                 if (r)
4596                         goto out;
4597
4598                 r = -EFAULT;
4599                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4600                         goto out;
4601                 r = 0;
4602                 break;
4603         }
4604         default:
4605                 r = -EINVAL;
4606         }
4607 out:
4608         kfree(u.buffer);
4609 out_nofree:
4610         vcpu_put(vcpu);
4611         return r;
4612 }
4613
4614 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4615 {
4616         return VM_FAULT_SIGBUS;
4617 }
4618
4619 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4620 {
4621         int ret;
4622
4623         if (addr > (unsigned int)(-3 * PAGE_SIZE))
4624                 return -EINVAL;
4625         ret = kvm_x86_ops.set_tss_addr(kvm, addr);
4626         return ret;
4627 }
4628
4629 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4630                                               u64 ident_addr)
4631 {
4632         return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
4633 }
4634
4635 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4636                                          unsigned long kvm_nr_mmu_pages)
4637 {
4638         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4639                 return -EINVAL;
4640
4641         mutex_lock(&kvm->slots_lock);
4642
4643         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4644         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4645
4646         mutex_unlock(&kvm->slots_lock);
4647         return 0;
4648 }
4649
4650 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4651 {
4652         return kvm->arch.n_max_mmu_pages;
4653 }
4654
4655 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4656 {
4657         struct kvm_pic *pic = kvm->arch.vpic;
4658         int r;
4659
4660         r = 0;
4661         switch (chip->chip_id) {
4662         case KVM_IRQCHIP_PIC_MASTER:
4663                 memcpy(&chip->chip.pic, &pic->pics[0],
4664                         sizeof(struct kvm_pic_state));
4665                 break;
4666         case KVM_IRQCHIP_PIC_SLAVE:
4667                 memcpy(&chip->chip.pic, &pic->pics[1],
4668                         sizeof(struct kvm_pic_state));
4669                 break;
4670         case KVM_IRQCHIP_IOAPIC:
4671                 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4672                 break;
4673         default:
4674                 r = -EINVAL;
4675                 break;
4676         }
4677         return r;
4678 }
4679
4680 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4681 {
4682         struct kvm_pic *pic = kvm->arch.vpic;
4683         int r;
4684
4685         r = 0;
4686         switch (chip->chip_id) {
4687         case KVM_IRQCHIP_PIC_MASTER:
4688                 spin_lock(&pic->lock);
4689                 memcpy(&pic->pics[0], &chip->chip.pic,
4690                         sizeof(struct kvm_pic_state));
4691                 spin_unlock(&pic->lock);
4692                 break;
4693         case KVM_IRQCHIP_PIC_SLAVE:
4694                 spin_lock(&pic->lock);
4695                 memcpy(&pic->pics[1], &chip->chip.pic,
4696                         sizeof(struct kvm_pic_state));
4697                 spin_unlock(&pic->lock);
4698                 break;
4699         case KVM_IRQCHIP_IOAPIC:
4700                 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4701                 break;
4702         default:
4703                 r = -EINVAL;
4704                 break;
4705         }
4706         kvm_pic_update_irq(pic);
4707         return r;
4708 }
4709
4710 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4711 {
4712         struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4713
4714         BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4715
4716         mutex_lock(&kps->lock);
4717         memcpy(ps, &kps->channels, sizeof(*ps));
4718         mutex_unlock(&kps->lock);
4719         return 0;
4720 }
4721
4722 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4723 {
4724         int i;
4725         struct kvm_pit *pit = kvm->arch.vpit;
4726
4727         mutex_lock(&pit->pit_state.lock);
4728         memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4729         for (i = 0; i < 3; i++)
4730                 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4731         mutex_unlock(&pit->pit_state.lock);
4732         return 0;
4733 }
4734
4735 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4736 {
4737         mutex_lock(&kvm->arch.vpit->pit_state.lock);
4738         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4739                 sizeof(ps->channels));
4740         ps->flags = kvm->arch.vpit->pit_state.flags;
4741         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4742         memset(&ps->reserved, 0, sizeof(ps->reserved));
4743         return 0;
4744 }
4745
4746 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4747 {
4748         int start = 0;
4749         int i;
4750         u32 prev_legacy, cur_legacy;
4751         struct kvm_pit *pit = kvm->arch.vpit;
4752
4753         mutex_lock(&pit->pit_state.lock);
4754         prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4755         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4756         if (!prev_legacy && cur_legacy)
4757                 start = 1;
4758         memcpy(&pit->pit_state.channels, &ps->channels,
4759                sizeof(pit->pit_state.channels));
4760         pit->pit_state.flags = ps->flags;
4761         for (i = 0; i < 3; i++)
4762                 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4763                                    start && i == 0);
4764         mutex_unlock(&pit->pit_state.lock);
4765         return 0;
4766 }
4767
4768 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4769                                  struct kvm_reinject_control *control)
4770 {
4771         struct kvm_pit *pit = kvm->arch.vpit;
4772
4773         /* pit->pit_state.lock was overloaded to prevent userspace from getting
4774          * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4775          * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
4776          */
4777         mutex_lock(&pit->pit_state.lock);
4778         kvm_pit_set_reinject(pit, control->pit_reinject);
4779         mutex_unlock(&pit->pit_state.lock);
4780
4781         return 0;
4782 }
4783
4784 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
4785 {
4786         /*
4787          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4788          */
4789         if (kvm_x86_ops.flush_log_dirty)
4790                 kvm_x86_ops.flush_log_dirty(kvm);
4791 }
4792
4793 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4794                         bool line_status)
4795 {
4796         if (!irqchip_in_kernel(kvm))
4797                 return -ENXIO;
4798
4799         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4800                                         irq_event->irq, irq_event->level,
4801                                         line_status);
4802         return 0;
4803 }
4804
4805 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4806                             struct kvm_enable_cap *cap)
4807 {
4808         int r;
4809
4810         if (cap->flags)
4811                 return -EINVAL;
4812
4813         switch (cap->cap) {
4814         case KVM_CAP_DISABLE_QUIRKS:
4815                 kvm->arch.disabled_quirks = cap->args[0];
4816                 r = 0;
4817                 break;
4818         case KVM_CAP_SPLIT_IRQCHIP: {
4819                 mutex_lock(&kvm->lock);
4820                 r = -EINVAL;
4821                 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4822                         goto split_irqchip_unlock;
4823                 r = -EEXIST;
4824                 if (irqchip_in_kernel(kvm))
4825                         goto split_irqchip_unlock;
4826                 if (kvm->created_vcpus)
4827                         goto split_irqchip_unlock;
4828                 r = kvm_setup_empty_irq_routing(kvm);
4829                 if (r)
4830                         goto split_irqchip_unlock;
4831                 /* Pairs with irqchip_in_kernel. */
4832                 smp_wmb();
4833                 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4834                 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4835                 r = 0;
4836 split_irqchip_unlock:
4837                 mutex_unlock(&kvm->lock);
4838                 break;
4839         }
4840         case KVM_CAP_X2APIC_API:
4841                 r = -EINVAL;
4842                 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4843                         break;
4844
4845                 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4846                         kvm->arch.x2apic_format = true;
4847                 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4848                         kvm->arch.x2apic_broadcast_quirk_disabled = true;
4849
4850                 r = 0;
4851                 break;
4852         case KVM_CAP_X86_DISABLE_EXITS:
4853                 r = -EINVAL;
4854                 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4855                         break;
4856
4857                 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4858                         kvm_can_mwait_in_guest())
4859                         kvm->arch.mwait_in_guest = true;
4860                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4861                         kvm->arch.hlt_in_guest = true;
4862                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4863                         kvm->arch.pause_in_guest = true;
4864                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4865                         kvm->arch.cstate_in_guest = true;
4866                 r = 0;
4867                 break;
4868         case KVM_CAP_MSR_PLATFORM_INFO:
4869                 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4870                 r = 0;
4871                 break;
4872         case KVM_CAP_EXCEPTION_PAYLOAD:
4873                 kvm->arch.exception_payload_enabled = cap->args[0];
4874                 r = 0;
4875                 break;
4876         default:
4877                 r = -EINVAL;
4878                 break;
4879         }
4880         return r;
4881 }
4882
4883 long kvm_arch_vm_ioctl(struct file *filp,
4884                        unsigned int ioctl, unsigned long arg)
4885 {
4886         struct kvm *kvm = filp->private_data;
4887         void __user *argp = (void __user *)arg;
4888         int r = -ENOTTY;
4889         /*
4890          * This union makes it completely explicit to gcc-3.x
4891          * that these two variables' stack usage should be
4892          * combined, not added together.
4893          */
4894         union {
4895                 struct kvm_pit_state ps;
4896                 struct kvm_pit_state2 ps2;
4897                 struct kvm_pit_config pit_config;
4898         } u;
4899
4900         switch (ioctl) {
4901         case KVM_SET_TSS_ADDR:
4902                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4903                 break;
4904         case KVM_SET_IDENTITY_MAP_ADDR: {
4905                 u64 ident_addr;
4906
4907                 mutex_lock(&kvm->lock);
4908                 r = -EINVAL;
4909                 if (kvm->created_vcpus)
4910                         goto set_identity_unlock;
4911                 r = -EFAULT;
4912                 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4913                         goto set_identity_unlock;
4914                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4915 set_identity_unlock:
4916                 mutex_unlock(&kvm->lock);
4917                 break;
4918         }
4919         case KVM_SET_NR_MMU_PAGES:
4920                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4921                 break;
4922         case KVM_GET_NR_MMU_PAGES:
4923                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4924                 break;
4925         case KVM_CREATE_IRQCHIP: {
4926                 mutex_lock(&kvm->lock);
4927
4928                 r = -EEXIST;
4929                 if (irqchip_in_kernel(kvm))
4930                         goto create_irqchip_unlock;
4931
4932                 r = -EINVAL;
4933                 if (kvm->created_vcpus)
4934                         goto create_irqchip_unlock;
4935
4936                 r = kvm_pic_init(kvm);
4937                 if (r)
4938                         goto create_irqchip_unlock;
4939
4940                 r = kvm_ioapic_init(kvm);
4941                 if (r) {
4942                         kvm_pic_destroy(kvm);
4943                         goto create_irqchip_unlock;
4944                 }
4945
4946                 r = kvm_setup_default_irq_routing(kvm);
4947                 if (r) {
4948                         kvm_ioapic_destroy(kvm);
4949                         kvm_pic_destroy(kvm);
4950                         goto create_irqchip_unlock;
4951                 }
4952                 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4953                 smp_wmb();
4954                 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4955         create_irqchip_unlock:
4956                 mutex_unlock(&kvm->lock);
4957                 break;
4958         }
4959         case KVM_CREATE_PIT:
4960                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4961                 goto create_pit;
4962         case KVM_CREATE_PIT2:
4963                 r = -EFAULT;
4964                 if (copy_from_user(&u.pit_config, argp,
4965                                    sizeof(struct kvm_pit_config)))
4966                         goto out;
4967         create_pit:
4968                 mutex_lock(&kvm->lock);
4969                 r = -EEXIST;
4970                 if (kvm->arch.vpit)
4971                         goto create_pit_unlock;
4972                 r = -ENOMEM;
4973                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4974                 if (kvm->arch.vpit)
4975                         r = 0;
4976         create_pit_unlock:
4977                 mutex_unlock(&kvm->lock);
4978                 break;
4979         case KVM_GET_IRQCHIP: {
4980                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
4981                 struct kvm_irqchip *chip;
4982
4983                 chip = memdup_user(argp, sizeof(*chip));
4984                 if (IS_ERR(chip)) {
4985                         r = PTR_ERR(chip);
4986                         goto out;
4987                 }
4988
4989                 r = -ENXIO;
4990                 if (!irqchip_kernel(kvm))
4991                         goto get_irqchip_out;
4992                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
4993                 if (r)
4994                         goto get_irqchip_out;
4995                 r = -EFAULT;
4996                 if (copy_to_user(argp, chip, sizeof(*chip)))
4997                         goto get_irqchip_out;
4998                 r = 0;
4999         get_irqchip_out:
5000                 kfree(chip);
5001                 break;
5002         }
5003         case KVM_SET_IRQCHIP: {
5004                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5005                 struct kvm_irqchip *chip;
5006
5007                 chip = memdup_user(argp, sizeof(*chip));
5008                 if (IS_ERR(chip)) {
5009                         r = PTR_ERR(chip);
5010                         goto out;
5011                 }
5012
5013                 r = -ENXIO;
5014                 if (!irqchip_kernel(kvm))
5015                         goto set_irqchip_out;
5016                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5017         set_irqchip_out:
5018                 kfree(chip);
5019                 break;
5020         }
5021         case KVM_GET_PIT: {
5022                 r = -EFAULT;
5023                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5024                         goto out;
5025                 r = -ENXIO;
5026                 if (!kvm->arch.vpit)
5027                         goto out;
5028                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5029                 if (r)
5030                         goto out;
5031                 r = -EFAULT;
5032                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5033                         goto out;
5034                 r = 0;
5035                 break;
5036         }
5037         case KVM_SET_PIT: {
5038                 r = -EFAULT;
5039                 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5040                         goto out;
5041                 mutex_lock(&kvm->lock);
5042                 r = -ENXIO;
5043                 if (!kvm->arch.vpit)
5044                         goto set_pit_out;
5045                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5046 set_pit_out:
5047                 mutex_unlock(&kvm->lock);
5048                 break;
5049         }
5050         case KVM_GET_PIT2: {
5051                 r = -ENXIO;
5052                 if (!kvm->arch.vpit)
5053                         goto out;
5054                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5055                 if (r)
5056                         goto out;
5057                 r = -EFAULT;
5058                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5059                         goto out;
5060                 r = 0;
5061                 break;
5062         }
5063         case KVM_SET_PIT2: {
5064                 r = -EFAULT;
5065                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5066                         goto out;
5067                 mutex_lock(&kvm->lock);
5068                 r = -ENXIO;
5069                 if (!kvm->arch.vpit)
5070                         goto set_pit2_out;
5071                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5072 set_pit2_out:
5073                 mutex_unlock(&kvm->lock);
5074                 break;
5075         }
5076         case KVM_REINJECT_CONTROL: {
5077                 struct kvm_reinject_control control;
5078                 r =  -EFAULT;
5079                 if (copy_from_user(&control, argp, sizeof(control)))
5080                         goto out;
5081                 r = -ENXIO;
5082                 if (!kvm->arch.vpit)
5083                         goto out;
5084                 r = kvm_vm_ioctl_reinject(kvm, &control);
5085                 break;
5086         }
5087         case KVM_SET_BOOT_CPU_ID:
5088                 r = 0;
5089                 mutex_lock(&kvm->lock);
5090                 if (kvm->created_vcpus)
5091                         r = -EBUSY;
5092                 else
5093                         kvm->arch.bsp_vcpu_id = arg;
5094                 mutex_unlock(&kvm->lock);
5095                 break;
5096         case KVM_XEN_HVM_CONFIG: {
5097                 struct kvm_xen_hvm_config xhc;
5098                 r = -EFAULT;
5099                 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5100                         goto out;
5101                 r = -EINVAL;
5102                 if (xhc.flags)
5103                         goto out;
5104                 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5105                 r = 0;
5106                 break;
5107         }
5108         case KVM_SET_CLOCK: {
5109                 struct kvm_clock_data user_ns;
5110                 u64 now_ns;
5111
5112                 r = -EFAULT;
5113                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5114                         goto out;
5115
5116                 r = -EINVAL;
5117                 if (user_ns.flags)
5118                         goto out;
5119
5120                 r = 0;
5121                 /*
5122                  * TODO: userspace has to take care of races with VCPU_RUN, so
5123                  * kvm_gen_update_masterclock() can be cut down to locked
5124                  * pvclock_update_vm_gtod_copy().
5125                  */
5126                 kvm_gen_update_masterclock(kvm);
5127                 now_ns = get_kvmclock_ns(kvm);
5128                 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5129                 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5130                 break;
5131         }
5132         case KVM_GET_CLOCK: {
5133                 struct kvm_clock_data user_ns;
5134                 u64 now_ns;
5135
5136                 now_ns = get_kvmclock_ns(kvm);
5137                 user_ns.clock = now_ns;
5138                 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5139                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5140
5141                 r = -EFAULT;
5142                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5143                         goto out;
5144                 r = 0;
5145                 break;
5146         }
5147         case KVM_MEMORY_ENCRYPT_OP: {
5148                 r = -ENOTTY;
5149                 if (kvm_x86_ops.mem_enc_op)
5150                         r = kvm_x86_ops.mem_enc_op(kvm, argp);
5151                 break;
5152         }
5153         case KVM_MEMORY_ENCRYPT_REG_REGION: {
5154                 struct kvm_enc_region region;
5155
5156                 r = -EFAULT;
5157                 if (copy_from_user(&region, argp, sizeof(region)))
5158                         goto out;
5159
5160                 r = -ENOTTY;
5161                 if (kvm_x86_ops.mem_enc_reg_region)
5162                         r = kvm_x86_ops.mem_enc_reg_region(kvm, &region);
5163                 break;
5164         }
5165         case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5166                 struct kvm_enc_region region;
5167
5168                 r = -EFAULT;
5169                 if (copy_from_user(&region, argp, sizeof(region)))
5170                         goto out;
5171
5172                 r = -ENOTTY;
5173                 if (kvm_x86_ops.mem_enc_unreg_region)
5174                         r = kvm_x86_ops.mem_enc_unreg_region(kvm, &region);
5175                 break;
5176         }
5177         case KVM_HYPERV_EVENTFD: {
5178                 struct kvm_hyperv_eventfd hvevfd;
5179
5180                 r = -EFAULT;
5181                 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5182                         goto out;
5183                 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5184                 break;
5185         }
5186         case KVM_SET_PMU_EVENT_FILTER:
5187                 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5188                 break;
5189         default:
5190                 r = -ENOTTY;
5191         }
5192 out:
5193         return r;
5194 }
5195
5196 static void kvm_init_msr_list(void)
5197 {
5198         struct x86_pmu_capability x86_pmu;
5199         u32 dummy[2];
5200         unsigned i;
5201
5202         BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5203                          "Please update the fixed PMCs in msrs_to_saved_all[]");
5204
5205         perf_get_x86_pmu_capability(&x86_pmu);
5206
5207         num_msrs_to_save = 0;
5208         num_emulated_msrs = 0;
5209         num_msr_based_features = 0;
5210
5211         for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5212                 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5213                         continue;
5214
5215                 /*
5216                  * Even MSRs that are valid in the host may not be exposed
5217                  * to the guests in some cases.
5218                  */
5219                 switch (msrs_to_save_all[i]) {
5220                 case MSR_IA32_BNDCFGS:
5221                         if (!kvm_mpx_supported())
5222                                 continue;
5223                         break;
5224                 case MSR_TSC_AUX:
5225                         if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5226                                 continue;
5227                         break;
5228                 case MSR_IA32_RTIT_CTL:
5229                 case MSR_IA32_RTIT_STATUS:
5230                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5231                                 continue;
5232                         break;
5233                 case MSR_IA32_RTIT_CR3_MATCH:
5234                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5235                             !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5236                                 continue;
5237                         break;
5238                 case MSR_IA32_RTIT_OUTPUT_BASE:
5239                 case MSR_IA32_RTIT_OUTPUT_MASK:
5240                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5241                                 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5242                                  !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5243                                 continue;
5244                         break;
5245                 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5246                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5247                                 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5248                                 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5249                                 continue;
5250                         break;
5251                 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5252                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5253                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5254                                 continue;
5255                         break;
5256                 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5257                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5258                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5259                                 continue;
5260                 }
5261                 default:
5262                         break;
5263                 }
5264
5265                 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5266         }
5267
5268         for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5269                 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5270                         continue;
5271
5272                 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5273         }
5274
5275         for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5276                 struct kvm_msr_entry msr;
5277
5278                 msr.index = msr_based_features_all[i];
5279                 if (kvm_get_msr_feature(&msr))
5280                         continue;
5281
5282                 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5283         }
5284 }
5285
5286 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5287                            const void *v)
5288 {
5289         int handled = 0;
5290         int n;
5291
5292         do {
5293                 n = min(len, 8);
5294                 if (!(lapic_in_kernel(vcpu) &&
5295                       !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5296                     && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5297                         break;
5298                 handled += n;
5299                 addr += n;
5300                 len -= n;
5301                 v += n;
5302         } while (len);
5303
5304         return handled;
5305 }
5306
5307 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5308 {
5309         int handled = 0;
5310         int n;
5311
5312         do {
5313                 n = min(len, 8);
5314                 if (!(lapic_in_kernel(vcpu) &&
5315                       !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5316                                          addr, n, v))
5317                     && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5318                         break;
5319                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5320                 handled += n;
5321                 addr += n;
5322                 len -= n;
5323                 v += n;
5324         } while (len);
5325
5326         return handled;
5327 }
5328
5329 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5330                         struct kvm_segment *var, int seg)
5331 {
5332         kvm_x86_ops.set_segment(vcpu, var, seg);
5333 }
5334
5335 void kvm_get_segment(struct kvm_vcpu *vcpu,
5336                      struct kvm_segment *var, int seg)
5337 {
5338         kvm_x86_ops.get_segment(vcpu, var, seg);
5339 }
5340
5341 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5342                            struct x86_exception *exception)
5343 {
5344         gpa_t t_gpa;
5345
5346         BUG_ON(!mmu_is_nested(vcpu));
5347
5348         /* NPT walks are always user-walks */
5349         access |= PFERR_USER_MASK;
5350         t_gpa  = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5351
5352         return t_gpa;
5353 }
5354
5355 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5356                               struct x86_exception *exception)
5357 {
5358         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5359         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5360 }
5361
5362  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5363                                 struct x86_exception *exception)
5364 {
5365         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5366         access |= PFERR_FETCH_MASK;
5367         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5368 }
5369
5370 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5371                                struct x86_exception *exception)
5372 {
5373         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5374         access |= PFERR_WRITE_MASK;
5375         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5376 }
5377
5378 /* uses this to access any guest's mapped memory without checking CPL */
5379 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5380                                 struct x86_exception *exception)
5381 {
5382         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5383 }
5384
5385 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5386                                       struct kvm_vcpu *vcpu, u32 access,
5387                                       struct x86_exception *exception)
5388 {
5389         void *data = val;
5390         int r = X86EMUL_CONTINUE;
5391
5392         while (bytes) {
5393                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5394                                                             exception);
5395                 unsigned offset = addr & (PAGE_SIZE-1);
5396                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5397                 int ret;
5398
5399                 if (gpa == UNMAPPED_GVA)
5400                         return X86EMUL_PROPAGATE_FAULT;
5401                 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5402                                                offset, toread);
5403                 if (ret < 0) {
5404                         r = X86EMUL_IO_NEEDED;
5405                         goto out;
5406                 }
5407
5408                 bytes -= toread;
5409                 data += toread;
5410                 addr += toread;
5411         }
5412 out:
5413         return r;
5414 }
5415
5416 /* used for instruction fetching */
5417 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5418                                 gva_t addr, void *val, unsigned int bytes,
5419                                 struct x86_exception *exception)
5420 {
5421         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5422         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5423         unsigned offset;
5424         int ret;
5425
5426         /* Inline kvm_read_guest_virt_helper for speed.  */
5427         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5428                                                     exception);
5429         if (unlikely(gpa == UNMAPPED_GVA))
5430                 return X86EMUL_PROPAGATE_FAULT;
5431
5432         offset = addr & (PAGE_SIZE-1);
5433         if (WARN_ON(offset + bytes > PAGE_SIZE))
5434                 bytes = (unsigned)PAGE_SIZE - offset;
5435         ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5436                                        offset, bytes);
5437         if (unlikely(ret < 0))
5438                 return X86EMUL_IO_NEEDED;
5439
5440         return X86EMUL_CONTINUE;
5441 }
5442
5443 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5444                                gva_t addr, void *val, unsigned int bytes,
5445                                struct x86_exception *exception)
5446 {
5447         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5448
5449         /*
5450          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5451          * is returned, but our callers are not ready for that and they blindly
5452          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5453          * uninitialized kernel stack memory into cr2 and error code.
5454          */
5455         memset(exception, 0, sizeof(*exception));
5456         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5457                                           exception);
5458 }
5459 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5460
5461 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5462                              gva_t addr, void *val, unsigned int bytes,
5463                              struct x86_exception *exception, bool system)
5464 {
5465         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5466         u32 access = 0;
5467
5468         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5469                 access |= PFERR_USER_MASK;
5470
5471         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5472 }
5473
5474 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5475                 unsigned long addr, void *val, unsigned int bytes)
5476 {
5477         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5478         int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5479
5480         return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5481 }
5482
5483 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5484                                       struct kvm_vcpu *vcpu, u32 access,
5485                                       struct x86_exception *exception)
5486 {
5487         void *data = val;
5488         int r = X86EMUL_CONTINUE;
5489
5490         while (bytes) {
5491                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5492                                                              access,
5493                                                              exception);
5494                 unsigned offset = addr & (PAGE_SIZE-1);
5495                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5496                 int ret;
5497
5498                 if (gpa == UNMAPPED_GVA)
5499                         return X86EMUL_PROPAGATE_FAULT;
5500                 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5501                 if (ret < 0) {
5502                         r = X86EMUL_IO_NEEDED;
5503                         goto out;
5504                 }
5505
5506                 bytes -= towrite;
5507                 data += towrite;
5508                 addr += towrite;
5509         }
5510 out:
5511         return r;
5512 }
5513
5514 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5515                               unsigned int bytes, struct x86_exception *exception,
5516                               bool system)
5517 {
5518         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5519         u32 access = PFERR_WRITE_MASK;
5520
5521         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5522                 access |= PFERR_USER_MASK;
5523
5524         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5525                                            access, exception);
5526 }
5527
5528 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5529                                 unsigned int bytes, struct x86_exception *exception)
5530 {
5531         /* kvm_write_guest_virt_system can pull in tons of pages. */
5532         vcpu->arch.l1tf_flush_l1d = true;
5533
5534         /*
5535          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5536          * is returned, but our callers are not ready for that and they blindly
5537          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5538          * uninitialized kernel stack memory into cr2 and error code.
5539          */
5540         memset(exception, 0, sizeof(*exception));
5541         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5542                                            PFERR_WRITE_MASK, exception);
5543 }
5544 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5545
5546 int handle_ud(struct kvm_vcpu *vcpu)
5547 {
5548         static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5549         int emul_type = EMULTYPE_TRAP_UD;
5550         char sig[5]; /* ud2; .ascii "kvm" */
5551         struct x86_exception e;
5552
5553         if (force_emulation_prefix &&
5554             kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5555                                 sig, sizeof(sig), &e) == 0 &&
5556             memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5557                 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5558                 emul_type = EMULTYPE_TRAP_UD_FORCED;
5559         }
5560
5561         return kvm_emulate_instruction(vcpu, emul_type);
5562 }
5563 EXPORT_SYMBOL_GPL(handle_ud);
5564
5565 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5566                             gpa_t gpa, bool write)
5567 {
5568         /* For APIC access vmexit */
5569         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5570                 return 1;
5571
5572         if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5573                 trace_vcpu_match_mmio(gva, gpa, write, true);
5574                 return 1;
5575         }
5576
5577         return 0;
5578 }
5579
5580 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5581                                 gpa_t *gpa, struct x86_exception *exception,
5582                                 bool write)
5583 {
5584         u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5585                 | (write ? PFERR_WRITE_MASK : 0);
5586
5587         /*
5588          * currently PKRU is only applied to ept enabled guest so
5589          * there is no pkey in EPT page table for L1 guest or EPT
5590          * shadow page table for L2 guest.
5591          */
5592         if (vcpu_match_mmio_gva(vcpu, gva)
5593             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5594                                  vcpu->arch.mmio_access, 0, access)) {
5595                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5596                                         (gva & (PAGE_SIZE - 1));
5597                 trace_vcpu_match_mmio(gva, *gpa, write, false);
5598                 return 1;
5599         }
5600
5601         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5602
5603         if (*gpa == UNMAPPED_GVA)
5604                 return -1;
5605
5606         return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5607 }
5608
5609 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5610                         const void *val, int bytes)
5611 {
5612         int ret;
5613
5614         ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5615         if (ret < 0)
5616                 return 0;
5617         kvm_page_track_write(vcpu, gpa, val, bytes);
5618         return 1;
5619 }
5620
5621 struct read_write_emulator_ops {
5622         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5623                                   int bytes);
5624         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5625                                   void *val, int bytes);
5626         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5627                                int bytes, void *val);
5628         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5629                                     void *val, int bytes);
5630         bool write;
5631 };
5632
5633 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5634 {
5635         if (vcpu->mmio_read_completed) {
5636                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5637                                vcpu->mmio_fragments[0].gpa, val);
5638                 vcpu->mmio_read_completed = 0;
5639                 return 1;
5640         }
5641
5642         return 0;
5643 }
5644
5645 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5646                         void *val, int bytes)
5647 {
5648         return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5649 }
5650
5651 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5652                          void *val, int bytes)
5653 {
5654         return emulator_write_phys(vcpu, gpa, val, bytes);
5655 }
5656
5657 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5658 {
5659         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5660         return vcpu_mmio_write(vcpu, gpa, bytes, val);
5661 }
5662
5663 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5664                           void *val, int bytes)
5665 {
5666         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5667         return X86EMUL_IO_NEEDED;
5668 }
5669
5670 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5671                            void *val, int bytes)
5672 {
5673         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5674
5675         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5676         return X86EMUL_CONTINUE;
5677 }
5678
5679 static const struct read_write_emulator_ops read_emultor = {
5680         .read_write_prepare = read_prepare,
5681         .read_write_emulate = read_emulate,
5682         .read_write_mmio = vcpu_mmio_read,
5683         .read_write_exit_mmio = read_exit_mmio,
5684 };
5685
5686 static const struct read_write_emulator_ops write_emultor = {
5687         .read_write_emulate = write_emulate,
5688         .read_write_mmio = write_mmio,
5689         .read_write_exit_mmio = write_exit_mmio,
5690         .write = true,
5691 };
5692
5693 static int emulator_read_write_onepage(unsigned long addr, void *val,
5694                                        unsigned int bytes,
5695                                        struct x86_exception *exception,
5696                                        struct kvm_vcpu *vcpu,
5697                                        const struct read_write_emulator_ops *ops)
5698 {
5699         gpa_t gpa;
5700         int handled, ret;
5701         bool write = ops->write;
5702         struct kvm_mmio_fragment *frag;
5703         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
5704
5705         /*
5706          * If the exit was due to a NPF we may already have a GPA.
5707          * If the GPA is present, use it to avoid the GVA to GPA table walk.
5708          * Note, this cannot be used on string operations since string
5709          * operation using rep will only have the initial GPA from the NPF
5710          * occurred.
5711          */
5712         if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
5713             (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
5714                 gpa = ctxt->gpa_val;
5715                 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5716         } else {
5717                 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5718                 if (ret < 0)
5719                         return X86EMUL_PROPAGATE_FAULT;
5720         }
5721
5722         if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5723                 return X86EMUL_CONTINUE;
5724
5725         /*
5726          * Is this MMIO handled locally?
5727          */
5728         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5729         if (handled == bytes)
5730                 return X86EMUL_CONTINUE;
5731
5732         gpa += handled;
5733         bytes -= handled;
5734         val += handled;
5735
5736         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5737         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5738         frag->gpa = gpa;
5739         frag->data = val;
5740         frag->len = bytes;
5741         return X86EMUL_CONTINUE;
5742 }
5743
5744 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5745                         unsigned long addr,
5746                         void *val, unsigned int bytes,
5747                         struct x86_exception *exception,
5748                         const struct read_write_emulator_ops *ops)
5749 {
5750         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5751         gpa_t gpa;
5752         int rc;
5753
5754         if (ops->read_write_prepare &&
5755                   ops->read_write_prepare(vcpu, val, bytes))
5756                 return X86EMUL_CONTINUE;
5757
5758         vcpu->mmio_nr_fragments = 0;
5759
5760         /* Crossing a page boundary? */
5761         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5762                 int now;
5763
5764                 now = -addr & ~PAGE_MASK;
5765                 rc = emulator_read_write_onepage(addr, val, now, exception,
5766                                                  vcpu, ops);
5767
5768                 if (rc != X86EMUL_CONTINUE)
5769                         return rc;
5770                 addr += now;
5771                 if (ctxt->mode != X86EMUL_MODE_PROT64)
5772                         addr = (u32)addr;
5773                 val += now;
5774                 bytes -= now;
5775         }
5776
5777         rc = emulator_read_write_onepage(addr, val, bytes, exception,
5778                                          vcpu, ops);
5779         if (rc != X86EMUL_CONTINUE)
5780                 return rc;
5781
5782         if (!vcpu->mmio_nr_fragments)
5783                 return rc;
5784
5785         gpa = vcpu->mmio_fragments[0].gpa;
5786
5787         vcpu->mmio_needed = 1;
5788         vcpu->mmio_cur_fragment = 0;
5789
5790         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5791         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5792         vcpu->run->exit_reason = KVM_EXIT_MMIO;
5793         vcpu->run->mmio.phys_addr = gpa;
5794
5795         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5796 }
5797
5798 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5799                                   unsigned long addr,
5800                                   void *val,
5801                                   unsigned int bytes,
5802                                   struct x86_exception *exception)
5803 {
5804         return emulator_read_write(ctxt, addr, val, bytes,
5805                                    exception, &read_emultor);
5806 }
5807
5808 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5809                             unsigned long addr,
5810                             const void *val,
5811                             unsigned int bytes,
5812                             struct x86_exception *exception)
5813 {
5814         return emulator_read_write(ctxt, addr, (void *)val, bytes,
5815                                    exception, &write_emultor);
5816 }
5817
5818 #define CMPXCHG_TYPE(t, ptr, old, new) \
5819         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5820
5821 #ifdef CONFIG_X86_64
5822 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5823 #else
5824 #  define CMPXCHG64(ptr, old, new) \
5825         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5826 #endif
5827
5828 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5829                                      unsigned long addr,
5830                                      const void *old,
5831                                      const void *new,
5832                                      unsigned int bytes,
5833                                      struct x86_exception *exception)
5834 {
5835         struct kvm_host_map map;
5836         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5837         u64 page_line_mask;
5838         gpa_t gpa;
5839         char *kaddr;
5840         bool exchanged;
5841
5842         /* guests cmpxchg8b have to be emulated atomically */
5843         if (bytes > 8 || (bytes & (bytes - 1)))
5844                 goto emul_write;
5845
5846         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5847
5848         if (gpa == UNMAPPED_GVA ||
5849             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5850                 goto emul_write;
5851
5852         /*
5853          * Emulate the atomic as a straight write to avoid #AC if SLD is
5854          * enabled in the host and the access splits a cache line.
5855          */
5856         if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
5857                 page_line_mask = ~(cache_line_size() - 1);
5858         else
5859                 page_line_mask = PAGE_MASK;
5860
5861         if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
5862                 goto emul_write;
5863
5864         if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5865                 goto emul_write;
5866
5867         kaddr = map.hva + offset_in_page(gpa);
5868
5869         switch (bytes) {
5870         case 1:
5871                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5872                 break;
5873         case 2:
5874                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5875                 break;
5876         case 4:
5877                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5878                 break;
5879         case 8:
5880                 exchanged = CMPXCHG64(kaddr, old, new);
5881                 break;
5882         default:
5883                 BUG();
5884         }
5885
5886         kvm_vcpu_unmap(vcpu, &map, true);
5887
5888         if (!exchanged)
5889                 return X86EMUL_CMPXCHG_FAILED;
5890
5891         kvm_page_track_write(vcpu, gpa, new, bytes);
5892
5893         return X86EMUL_CONTINUE;
5894
5895 emul_write:
5896         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5897
5898         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5899 }
5900
5901 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5902 {
5903         int r = 0, i;
5904
5905         for (i = 0; i < vcpu->arch.pio.count; i++) {
5906                 if (vcpu->arch.pio.in)
5907                         r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5908                                             vcpu->arch.pio.size, pd);
5909                 else
5910                         r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5911                                              vcpu->arch.pio.port, vcpu->arch.pio.size,
5912                                              pd);
5913                 if (r)
5914                         break;
5915                 pd += vcpu->arch.pio.size;
5916         }
5917         return r;
5918 }
5919
5920 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5921                                unsigned short port, void *val,
5922                                unsigned int count, bool in)
5923 {
5924         vcpu->arch.pio.port = port;
5925         vcpu->arch.pio.in = in;
5926         vcpu->arch.pio.count  = count;
5927         vcpu->arch.pio.size = size;
5928
5929         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5930                 vcpu->arch.pio.count = 0;
5931                 return 1;
5932         }
5933
5934         vcpu->run->exit_reason = KVM_EXIT_IO;
5935         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5936         vcpu->run->io.size = size;
5937         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5938         vcpu->run->io.count = count;
5939         vcpu->run->io.port = port;
5940
5941         return 0;
5942 }
5943
5944 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
5945                            unsigned short port, void *val, unsigned int count)
5946 {
5947         int ret;
5948
5949         if (vcpu->arch.pio.count)
5950                 goto data_avail;
5951
5952         memset(vcpu->arch.pio_data, 0, size * count);
5953
5954         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5955         if (ret) {
5956 data_avail:
5957                 memcpy(val, vcpu->arch.pio_data, size * count);
5958                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5959                 vcpu->arch.pio.count = 0;
5960                 return 1;
5961         }
5962
5963         return 0;
5964 }
5965
5966 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5967                                     int size, unsigned short port, void *val,
5968                                     unsigned int count)
5969 {
5970         return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
5971
5972 }
5973
5974 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
5975                             unsigned short port, const void *val,
5976                             unsigned int count)
5977 {
5978         memcpy(vcpu->arch.pio_data, val, size * count);
5979         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
5980         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5981 }
5982
5983 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5984                                      int size, unsigned short port,
5985                                      const void *val, unsigned int count)
5986 {
5987         return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
5988 }
5989
5990 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5991 {
5992         return kvm_x86_ops.get_segment_base(vcpu, seg);
5993 }
5994
5995 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
5996 {
5997         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
5998 }
5999
6000 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6001 {
6002         if (!need_emulate_wbinvd(vcpu))
6003                 return X86EMUL_CONTINUE;
6004
6005         if (kvm_x86_ops.has_wbinvd_exit()) {
6006                 int cpu = get_cpu();
6007
6008                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6009                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6010                                 wbinvd_ipi, NULL, 1);
6011                 put_cpu();
6012                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6013         } else
6014                 wbinvd();
6015         return X86EMUL_CONTINUE;
6016 }
6017
6018 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6019 {
6020         kvm_emulate_wbinvd_noskip(vcpu);
6021         return kvm_skip_emulated_instruction(vcpu);
6022 }
6023 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6024
6025
6026
6027 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6028 {
6029         kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6030 }
6031
6032 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6033                            unsigned long *dest)
6034 {
6035         return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6036 }
6037
6038 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6039                            unsigned long value)
6040 {
6041
6042         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6043 }
6044
6045 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6046 {
6047         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6048 }
6049
6050 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6051 {
6052         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6053         unsigned long value;
6054
6055         switch (cr) {
6056         case 0:
6057                 value = kvm_read_cr0(vcpu);
6058                 break;
6059         case 2:
6060                 value = vcpu->arch.cr2;
6061                 break;
6062         case 3:
6063                 value = kvm_read_cr3(vcpu);
6064                 break;
6065         case 4:
6066                 value = kvm_read_cr4(vcpu);
6067                 break;
6068         case 8:
6069                 value = kvm_get_cr8(vcpu);
6070                 break;
6071         default:
6072                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6073                 return 0;
6074         }
6075
6076         return value;
6077 }
6078
6079 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6080 {
6081         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6082         int res = 0;
6083
6084         switch (cr) {
6085         case 0:
6086                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6087                 break;
6088         case 2:
6089                 vcpu->arch.cr2 = val;
6090                 break;
6091         case 3:
6092                 res = kvm_set_cr3(vcpu, val);
6093                 break;
6094         case 4:
6095                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6096                 break;
6097         case 8:
6098                 res = kvm_set_cr8(vcpu, val);
6099                 break;
6100         default:
6101                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6102                 res = -1;
6103         }
6104
6105         return res;
6106 }
6107
6108 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6109 {
6110         return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6111 }
6112
6113 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6114 {
6115         kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6116 }
6117
6118 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6119 {
6120         kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6121 }
6122
6123 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6124 {
6125         kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6126 }
6127
6128 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6129 {
6130         kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6131 }
6132
6133 static unsigned long emulator_get_cached_segment_base(
6134         struct x86_emulate_ctxt *ctxt, int seg)
6135 {
6136         return get_segment_base(emul_to_vcpu(ctxt), seg);
6137 }
6138
6139 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6140                                  struct desc_struct *desc, u32 *base3,
6141                                  int seg)
6142 {
6143         struct kvm_segment var;
6144
6145         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6146         *selector = var.selector;
6147
6148         if (var.unusable) {
6149                 memset(desc, 0, sizeof(*desc));
6150                 if (base3)
6151                         *base3 = 0;
6152                 return false;
6153         }
6154
6155         if (var.g)
6156                 var.limit >>= 12;
6157         set_desc_limit(desc, var.limit);
6158         set_desc_base(desc, (unsigned long)var.base);
6159 #ifdef CONFIG_X86_64
6160         if (base3)
6161                 *base3 = var.base >> 32;
6162 #endif
6163         desc->type = var.type;
6164         desc->s = var.s;
6165         desc->dpl = var.dpl;
6166         desc->p = var.present;
6167         desc->avl = var.avl;
6168         desc->l = var.l;
6169         desc->d = var.db;
6170         desc->g = var.g;
6171
6172         return true;
6173 }
6174
6175 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6176                                  struct desc_struct *desc, u32 base3,
6177                                  int seg)
6178 {
6179         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6180         struct kvm_segment var;
6181
6182         var.selector = selector;
6183         var.base = get_desc_base(desc);
6184 #ifdef CONFIG_X86_64
6185         var.base |= ((u64)base3) << 32;
6186 #endif
6187         var.limit = get_desc_limit(desc);
6188         if (desc->g)
6189                 var.limit = (var.limit << 12) | 0xfff;
6190         var.type = desc->type;
6191         var.dpl = desc->dpl;
6192         var.db = desc->d;
6193         var.s = desc->s;
6194         var.l = desc->l;
6195         var.g = desc->g;
6196         var.avl = desc->avl;
6197         var.present = desc->p;
6198         var.unusable = !var.present;
6199         var.padding = 0;
6200
6201         kvm_set_segment(vcpu, &var, seg);
6202         return;
6203 }
6204
6205 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6206                             u32 msr_index, u64 *pdata)
6207 {
6208         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6209 }
6210
6211 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6212                             u32 msr_index, u64 data)
6213 {
6214         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6215 }
6216
6217 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6218 {
6219         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6220
6221         return vcpu->arch.smbase;
6222 }
6223
6224 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6225 {
6226         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6227
6228         vcpu->arch.smbase = smbase;
6229 }
6230
6231 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6232                               u32 pmc)
6233 {
6234         return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6235 }
6236
6237 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6238                              u32 pmc, u64 *pdata)
6239 {
6240         return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6241 }
6242
6243 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6244 {
6245         emul_to_vcpu(ctxt)->arch.halt_request = 1;
6246 }
6247
6248 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6249                               struct x86_instruction_info *info,
6250                               enum x86_intercept_stage stage)
6251 {
6252         return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6253                                             &ctxt->exception);
6254 }
6255
6256 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6257                               u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6258                               bool exact_only)
6259 {
6260         return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6261 }
6262
6263 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6264 {
6265         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6266 }
6267
6268 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6269 {
6270         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6271 }
6272
6273 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6274 {
6275         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6276 }
6277
6278 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6279 {
6280         return kvm_register_read(emul_to_vcpu(ctxt), reg);
6281 }
6282
6283 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6284 {
6285         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6286 }
6287
6288 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6289 {
6290         kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6291 }
6292
6293 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6294 {
6295         return emul_to_vcpu(ctxt)->arch.hflags;
6296 }
6297
6298 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6299 {
6300         emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6301 }
6302
6303 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6304                                   const char *smstate)
6305 {
6306         return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6307 }
6308
6309 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6310 {
6311         kvm_smm_changed(emul_to_vcpu(ctxt));
6312 }
6313
6314 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6315 {
6316         return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6317 }
6318
6319 static const struct x86_emulate_ops emulate_ops = {
6320         .read_gpr            = emulator_read_gpr,
6321         .write_gpr           = emulator_write_gpr,
6322         .read_std            = emulator_read_std,
6323         .write_std           = emulator_write_std,
6324         .read_phys           = kvm_read_guest_phys_system,
6325         .fetch               = kvm_fetch_guest_virt,
6326         .read_emulated       = emulator_read_emulated,
6327         .write_emulated      = emulator_write_emulated,
6328         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
6329         .invlpg              = emulator_invlpg,
6330         .pio_in_emulated     = emulator_pio_in_emulated,
6331         .pio_out_emulated    = emulator_pio_out_emulated,
6332         .get_segment         = emulator_get_segment,
6333         .set_segment         = emulator_set_segment,
6334         .get_cached_segment_base = emulator_get_cached_segment_base,
6335         .get_gdt             = emulator_get_gdt,
6336         .get_idt             = emulator_get_idt,
6337         .set_gdt             = emulator_set_gdt,
6338         .set_idt             = emulator_set_idt,
6339         .get_cr              = emulator_get_cr,
6340         .set_cr              = emulator_set_cr,
6341         .cpl                 = emulator_get_cpl,
6342         .get_dr              = emulator_get_dr,
6343         .set_dr              = emulator_set_dr,
6344         .get_smbase          = emulator_get_smbase,
6345         .set_smbase          = emulator_set_smbase,
6346         .set_msr             = emulator_set_msr,
6347         .get_msr             = emulator_get_msr,
6348         .check_pmc           = emulator_check_pmc,
6349         .read_pmc            = emulator_read_pmc,
6350         .halt                = emulator_halt,
6351         .wbinvd              = emulator_wbinvd,
6352         .fix_hypercall       = emulator_fix_hypercall,
6353         .intercept           = emulator_intercept,
6354         .get_cpuid           = emulator_get_cpuid,
6355         .guest_has_long_mode = emulator_guest_has_long_mode,
6356         .guest_has_movbe     = emulator_guest_has_movbe,
6357         .guest_has_fxsr      = emulator_guest_has_fxsr,
6358         .set_nmi_mask        = emulator_set_nmi_mask,
6359         .get_hflags          = emulator_get_hflags,
6360         .set_hflags          = emulator_set_hflags,
6361         .pre_leave_smm       = emulator_pre_leave_smm,
6362         .post_leave_smm      = emulator_post_leave_smm,
6363         .set_xcr             = emulator_set_xcr,
6364 };
6365
6366 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6367 {
6368         u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6369         /*
6370          * an sti; sti; sequence only disable interrupts for the first
6371          * instruction. So, if the last instruction, be it emulated or
6372          * not, left the system with the INT_STI flag enabled, it
6373          * means that the last instruction is an sti. We should not
6374          * leave the flag on in this case. The same goes for mov ss
6375          */
6376         if (int_shadow & mask)
6377                 mask = 0;
6378         if (unlikely(int_shadow || mask)) {
6379                 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6380                 if (!mask)
6381                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6382         }
6383 }
6384
6385 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6386 {
6387         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6388         if (ctxt->exception.vector == PF_VECTOR)
6389                 return kvm_propagate_fault(vcpu, &ctxt->exception);
6390
6391         if (ctxt->exception.error_code_valid)
6392                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6393                                       ctxt->exception.error_code);
6394         else
6395                 kvm_queue_exception(vcpu, ctxt->exception.vector);
6396         return false;
6397 }
6398
6399 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6400 {
6401         struct x86_emulate_ctxt *ctxt;
6402
6403         ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6404         if (!ctxt) {
6405                 pr_err("kvm: failed to allocate vcpu's emulator\n");
6406                 return NULL;
6407         }
6408
6409         ctxt->vcpu = vcpu;
6410         ctxt->ops = &emulate_ops;
6411         vcpu->arch.emulate_ctxt = ctxt;
6412
6413         return ctxt;
6414 }
6415
6416 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6417 {
6418         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6419         int cs_db, cs_l;
6420
6421         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6422
6423         ctxt->gpa_available = false;
6424         ctxt->eflags = kvm_get_rflags(vcpu);
6425         ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6426
6427         ctxt->eip = kvm_rip_read(vcpu);
6428         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
6429                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
6430                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
6431                      cs_db                              ? X86EMUL_MODE_PROT32 :
6432                                                           X86EMUL_MODE_PROT16;
6433         BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6434         BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6435         BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6436
6437         init_decode_cache(ctxt);
6438         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6439 }
6440
6441 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6442 {
6443         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6444         int ret;
6445
6446         init_emulate_ctxt(vcpu);
6447
6448         ctxt->op_bytes = 2;
6449         ctxt->ad_bytes = 2;
6450         ctxt->_eip = ctxt->eip + inc_eip;
6451         ret = emulate_int_real(ctxt, irq);
6452
6453         if (ret != X86EMUL_CONTINUE) {
6454                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6455         } else {
6456                 ctxt->eip = ctxt->_eip;
6457                 kvm_rip_write(vcpu, ctxt->eip);
6458                 kvm_set_rflags(vcpu, ctxt->eflags);
6459         }
6460 }
6461 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6462
6463 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6464 {
6465         ++vcpu->stat.insn_emulation_fail;
6466         trace_kvm_emulate_insn_failed(vcpu);
6467
6468         if (emulation_type & EMULTYPE_VMWARE_GP) {
6469                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6470                 return 1;
6471         }
6472
6473         if (emulation_type & EMULTYPE_SKIP) {
6474                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6475                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6476                 vcpu->run->internal.ndata = 0;
6477                 return 0;
6478         }
6479
6480         kvm_queue_exception(vcpu, UD_VECTOR);
6481
6482         if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
6483                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6484                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6485                 vcpu->run->internal.ndata = 0;
6486                 return 0;
6487         }
6488
6489         return 1;
6490 }
6491
6492 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6493                                   bool write_fault_to_shadow_pgtable,
6494                                   int emulation_type)
6495 {
6496         gpa_t gpa = cr2_or_gpa;
6497         kvm_pfn_t pfn;
6498
6499         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6500                 return false;
6501
6502         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6503             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6504                 return false;
6505
6506         if (!vcpu->arch.mmu->direct_map) {
6507                 /*
6508                  * Write permission should be allowed since only
6509                  * write access need to be emulated.
6510                  */
6511                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6512
6513                 /*
6514                  * If the mapping is invalid in guest, let cpu retry
6515                  * it to generate fault.
6516                  */
6517                 if (gpa == UNMAPPED_GVA)
6518                         return true;
6519         }
6520
6521         /*
6522          * Do not retry the unhandleable instruction if it faults on the
6523          * readonly host memory, otherwise it will goto a infinite loop:
6524          * retry instruction -> write #PF -> emulation fail -> retry
6525          * instruction -> ...
6526          */
6527         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6528
6529         /*
6530          * If the instruction failed on the error pfn, it can not be fixed,
6531          * report the error to userspace.
6532          */
6533         if (is_error_noslot_pfn(pfn))
6534                 return false;
6535
6536         kvm_release_pfn_clean(pfn);
6537
6538         /* The instructions are well-emulated on direct mmu. */
6539         if (vcpu->arch.mmu->direct_map) {
6540                 unsigned int indirect_shadow_pages;
6541
6542                 spin_lock(&vcpu->kvm->mmu_lock);
6543                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6544                 spin_unlock(&vcpu->kvm->mmu_lock);
6545
6546                 if (indirect_shadow_pages)
6547                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6548
6549                 return true;
6550         }
6551
6552         /*
6553          * if emulation was due to access to shadowed page table
6554          * and it failed try to unshadow page and re-enter the
6555          * guest to let CPU execute the instruction.
6556          */
6557         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6558
6559         /*
6560          * If the access faults on its page table, it can not
6561          * be fixed by unprotecting shadow page and it should
6562          * be reported to userspace.
6563          */
6564         return !write_fault_to_shadow_pgtable;
6565 }
6566
6567 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6568                               gpa_t cr2_or_gpa,  int emulation_type)
6569 {
6570         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6571         unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6572
6573         last_retry_eip = vcpu->arch.last_retry_eip;
6574         last_retry_addr = vcpu->arch.last_retry_addr;
6575
6576         /*
6577          * If the emulation is caused by #PF and it is non-page_table
6578          * writing instruction, it means the VM-EXIT is caused by shadow
6579          * page protected, we can zap the shadow page and retry this
6580          * instruction directly.
6581          *
6582          * Note: if the guest uses a non-page-table modifying instruction
6583          * on the PDE that points to the instruction, then we will unmap
6584          * the instruction and go to an infinite loop. So, we cache the
6585          * last retried eip and the last fault address, if we meet the eip
6586          * and the address again, we can break out of the potential infinite
6587          * loop.
6588          */
6589         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6590
6591         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6592                 return false;
6593
6594         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6595             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6596                 return false;
6597
6598         if (x86_page_table_writing_insn(ctxt))
6599                 return false;
6600
6601         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6602                 return false;
6603
6604         vcpu->arch.last_retry_eip = ctxt->eip;
6605         vcpu->arch.last_retry_addr = cr2_or_gpa;
6606
6607         if (!vcpu->arch.mmu->direct_map)
6608                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6609
6610         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6611
6612         return true;
6613 }
6614
6615 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6616 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6617
6618 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6619 {
6620         if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6621                 /* This is a good place to trace that we are exiting SMM.  */
6622                 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6623
6624                 /* Process a latched INIT or SMI, if any.  */
6625                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6626         }
6627
6628         kvm_mmu_reset_context(vcpu);
6629 }
6630
6631 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6632                                 unsigned long *db)
6633 {
6634         u32 dr6 = 0;
6635         int i;
6636         u32 enable, rwlen;
6637
6638         enable = dr7;
6639         rwlen = dr7 >> 16;
6640         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6641                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6642                         dr6 |= (1 << i);
6643         return dr6;
6644 }
6645
6646 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6647 {
6648         struct kvm_run *kvm_run = vcpu->run;
6649
6650         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6651                 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6652                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6653                 kvm_run->debug.arch.exception = DB_VECTOR;
6654                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6655                 return 0;
6656         }
6657         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6658         return 1;
6659 }
6660
6661 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6662 {
6663         unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6664         int r;
6665
6666         r = kvm_x86_ops.skip_emulated_instruction(vcpu);
6667         if (unlikely(!r))
6668                 return 0;
6669
6670         /*
6671          * rflags is the old, "raw" value of the flags.  The new value has
6672          * not been saved yet.
6673          *
6674          * This is correct even for TF set by the guest, because "the
6675          * processor will not generate this exception after the instruction
6676          * that sets the TF flag".
6677          */
6678         if (unlikely(rflags & X86_EFLAGS_TF))
6679                 r = kvm_vcpu_do_singlestep(vcpu);
6680         return r;
6681 }
6682 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6683
6684 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6685 {
6686         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6687             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6688                 struct kvm_run *kvm_run = vcpu->run;
6689                 unsigned long eip = kvm_get_linear_rip(vcpu);
6690                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6691                                            vcpu->arch.guest_debug_dr7,
6692                                            vcpu->arch.eff_db);
6693
6694                 if (dr6 != 0) {
6695                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6696                         kvm_run->debug.arch.pc = eip;
6697                         kvm_run->debug.arch.exception = DB_VECTOR;
6698                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
6699                         *r = 0;
6700                         return true;
6701                 }
6702         }
6703
6704         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6705             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6706                 unsigned long eip = kvm_get_linear_rip(vcpu);
6707                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6708                                            vcpu->arch.dr7,
6709                                            vcpu->arch.db);
6710
6711                 if (dr6 != 0) {
6712                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
6713                         *r = 1;
6714                         return true;
6715                 }
6716         }
6717
6718         return false;
6719 }
6720
6721 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6722 {
6723         switch (ctxt->opcode_len) {
6724         case 1:
6725                 switch (ctxt->b) {
6726                 case 0xe4:      /* IN */
6727                 case 0xe5:
6728                 case 0xec:
6729                 case 0xed:
6730                 case 0xe6:      /* OUT */
6731                 case 0xe7:
6732                 case 0xee:
6733                 case 0xef:
6734                 case 0x6c:      /* INS */
6735                 case 0x6d:
6736                 case 0x6e:      /* OUTS */
6737                 case 0x6f:
6738                         return true;
6739                 }
6740                 break;
6741         case 2:
6742                 switch (ctxt->b) {
6743                 case 0x33:      /* RDPMC */
6744                         return true;
6745                 }
6746                 break;
6747         }
6748
6749         return false;
6750 }
6751
6752 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6753                             int emulation_type, void *insn, int insn_len)
6754 {
6755         int r;
6756         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6757         bool writeback = true;
6758         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6759
6760         vcpu->arch.l1tf_flush_l1d = true;
6761
6762         /*
6763          * Clear write_fault_to_shadow_pgtable here to ensure it is
6764          * never reused.
6765          */
6766         vcpu->arch.write_fault_to_shadow_pgtable = false;
6767         kvm_clear_exception_queue(vcpu);
6768
6769         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6770                 init_emulate_ctxt(vcpu);
6771
6772                 /*
6773                  * We will reenter on the same instruction since
6774                  * we do not set complete_userspace_io.  This does not
6775                  * handle watchpoints yet, those would be handled in
6776                  * the emulate_ops.
6777                  */
6778                 if (!(emulation_type & EMULTYPE_SKIP) &&
6779                     kvm_vcpu_check_breakpoint(vcpu, &r))
6780                         return r;
6781
6782                 ctxt->interruptibility = 0;
6783                 ctxt->have_exception = false;
6784                 ctxt->exception.vector = -1;
6785                 ctxt->perm_ok = false;
6786
6787                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6788
6789                 r = x86_decode_insn(ctxt, insn, insn_len);
6790
6791                 trace_kvm_emulate_insn_start(vcpu);
6792                 ++vcpu->stat.insn_emulation;
6793                 if (r != EMULATION_OK)  {
6794                         if ((emulation_type & EMULTYPE_TRAP_UD) ||
6795                             (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6796                                 kvm_queue_exception(vcpu, UD_VECTOR);
6797                                 return 1;
6798                         }
6799                         if (reexecute_instruction(vcpu, cr2_or_gpa,
6800                                                   write_fault_to_spt,
6801                                                   emulation_type))
6802                                 return 1;
6803                         if (ctxt->have_exception) {
6804                                 /*
6805                                  * #UD should result in just EMULATION_FAILED, and trap-like
6806                                  * exception should not be encountered during decode.
6807                                  */
6808                                 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6809                                              exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6810                                 inject_emulated_exception(vcpu);
6811                                 return 1;
6812                         }
6813                         return handle_emulation_failure(vcpu, emulation_type);
6814                 }
6815         }
6816
6817         if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6818             !is_vmware_backdoor_opcode(ctxt)) {
6819                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6820                 return 1;
6821         }
6822
6823         /*
6824          * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6825          * for kvm_skip_emulated_instruction().  The caller is responsible for
6826          * updating interruptibility state and injecting single-step #DBs.
6827          */
6828         if (emulation_type & EMULTYPE_SKIP) {
6829                 kvm_rip_write(vcpu, ctxt->_eip);
6830                 if (ctxt->eflags & X86_EFLAGS_RF)
6831                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6832                 return 1;
6833         }
6834
6835         if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6836                 return 1;
6837
6838         /* this is needed for vmware backdoor interface to work since it
6839            changes registers values  during IO operation */
6840         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6841                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6842                 emulator_invalidate_register_cache(ctxt);
6843         }
6844
6845 restart:
6846         if (emulation_type & EMULTYPE_PF) {
6847                 /* Save the faulting GPA (cr2) in the address field */
6848                 ctxt->exception.address = cr2_or_gpa;
6849
6850                 /* With shadow page tables, cr2 contains a GVA or nGPA. */
6851                 if (vcpu->arch.mmu->direct_map) {
6852                         ctxt->gpa_available = true;
6853                         ctxt->gpa_val = cr2_or_gpa;
6854                 }
6855         } else {
6856                 /* Sanitize the address out of an abundance of paranoia. */
6857                 ctxt->exception.address = 0;
6858         }
6859
6860         r = x86_emulate_insn(ctxt);
6861
6862         if (r == EMULATION_INTERCEPTED)
6863                 return 1;
6864
6865         if (r == EMULATION_FAILED) {
6866                 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
6867                                         emulation_type))
6868                         return 1;
6869
6870                 return handle_emulation_failure(vcpu, emulation_type);
6871         }
6872
6873         if (ctxt->have_exception) {
6874                 r = 1;
6875                 if (inject_emulated_exception(vcpu))
6876                         return r;
6877         } else if (vcpu->arch.pio.count) {
6878                 if (!vcpu->arch.pio.in) {
6879                         /* FIXME: return into emulator if single-stepping.  */
6880                         vcpu->arch.pio.count = 0;
6881                 } else {
6882                         writeback = false;
6883                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
6884                 }
6885                 r = 0;
6886         } else if (vcpu->mmio_needed) {
6887                 ++vcpu->stat.mmio_exits;
6888
6889                 if (!vcpu->mmio_is_write)
6890                         writeback = false;
6891                 r = 0;
6892                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6893         } else if (r == EMULATION_RESTART)
6894                 goto restart;
6895         else
6896                 r = 1;
6897
6898         if (writeback) {
6899                 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6900                 toggle_interruptibility(vcpu, ctxt->interruptibility);
6901                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6902                 if (!ctxt->have_exception ||
6903                     exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6904                         kvm_rip_write(vcpu, ctxt->eip);
6905                         if (r && ctxt->tf)
6906                                 r = kvm_vcpu_do_singlestep(vcpu);
6907                         if (kvm_x86_ops.update_emulated_instruction)
6908                                 kvm_x86_ops.update_emulated_instruction(vcpu);
6909                         __kvm_set_rflags(vcpu, ctxt->eflags);
6910                 }
6911
6912                 /*
6913                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6914                  * do nothing, and it will be requested again as soon as
6915                  * the shadow expires.  But we still need to check here,
6916                  * because POPF has no interrupt shadow.
6917                  */
6918                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6919                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6920         } else
6921                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6922
6923         return r;
6924 }
6925
6926 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6927 {
6928         return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6929 }
6930 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6931
6932 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6933                                         void *insn, int insn_len)
6934 {
6935         return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6936 }
6937 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6938
6939 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6940 {
6941         vcpu->arch.pio.count = 0;
6942         return 1;
6943 }
6944
6945 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6946 {
6947         vcpu->arch.pio.count = 0;
6948
6949         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6950                 return 1;
6951
6952         return kvm_skip_emulated_instruction(vcpu);
6953 }
6954
6955 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6956                             unsigned short port)
6957 {
6958         unsigned long val = kvm_rax_read(vcpu);
6959         int ret = emulator_pio_out(vcpu, size, port, &val, 1);
6960
6961         if (ret)
6962                 return ret;
6963
6964         /*
6965          * Workaround userspace that relies on old KVM behavior of %rip being
6966          * incremented prior to exiting to userspace to handle "OUT 0x7e".
6967          */
6968         if (port == 0x7e &&
6969             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6970                 vcpu->arch.complete_userspace_io =
6971                         complete_fast_pio_out_port_0x7e;
6972                 kvm_skip_emulated_instruction(vcpu);
6973         } else {
6974                 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6975                 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6976         }
6977         return 0;
6978 }
6979
6980 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6981 {
6982         unsigned long val;
6983
6984         /* We should only ever be called with arch.pio.count equal to 1 */
6985         BUG_ON(vcpu->arch.pio.count != 1);
6986
6987         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6988                 vcpu->arch.pio.count = 0;
6989                 return 1;
6990         }
6991
6992         /* For size less than 4 we merge, else we zero extend */
6993         val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
6994
6995         /*
6996          * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
6997          * the copy and tracing
6998          */
6999         emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7000         kvm_rax_write(vcpu, val);
7001
7002         return kvm_skip_emulated_instruction(vcpu);
7003 }
7004
7005 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7006                            unsigned short port)
7007 {
7008         unsigned long val;
7009         int ret;
7010
7011         /* For size less than 4 we merge, else we zero extend */
7012         val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7013
7014         ret = emulator_pio_in(vcpu, size, port, &val, 1);
7015         if (ret) {
7016                 kvm_rax_write(vcpu, val);
7017                 return ret;
7018         }
7019
7020         vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7021         vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7022
7023         return 0;
7024 }
7025
7026 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7027 {
7028         int ret;
7029
7030         if (in)
7031                 ret = kvm_fast_pio_in(vcpu, size, port);
7032         else
7033                 ret = kvm_fast_pio_out(vcpu, size, port);
7034         return ret && kvm_skip_emulated_instruction(vcpu);
7035 }
7036 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7037
7038 static int kvmclock_cpu_down_prep(unsigned int cpu)
7039 {
7040         __this_cpu_write(cpu_tsc_khz, 0);
7041         return 0;
7042 }
7043
7044 static void tsc_khz_changed(void *data)
7045 {
7046         struct cpufreq_freqs *freq = data;
7047         unsigned long khz = 0;
7048
7049         if (data)
7050                 khz = freq->new;
7051         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7052                 khz = cpufreq_quick_get(raw_smp_processor_id());
7053         if (!khz)
7054                 khz = tsc_khz;
7055         __this_cpu_write(cpu_tsc_khz, khz);
7056 }
7057
7058 #ifdef CONFIG_X86_64
7059 static void kvm_hyperv_tsc_notifier(void)
7060 {
7061         struct kvm *kvm;
7062         struct kvm_vcpu *vcpu;
7063         int cpu;
7064
7065         mutex_lock(&kvm_lock);
7066         list_for_each_entry(kvm, &vm_list, vm_list)
7067                 kvm_make_mclock_inprogress_request(kvm);
7068
7069         hyperv_stop_tsc_emulation();
7070
7071         /* TSC frequency always matches when on Hyper-V */
7072         for_each_present_cpu(cpu)
7073                 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7074         kvm_max_guest_tsc_khz = tsc_khz;
7075
7076         list_for_each_entry(kvm, &vm_list, vm_list) {
7077                 struct kvm_arch *ka = &kvm->arch;
7078
7079                 spin_lock(&ka->pvclock_gtod_sync_lock);
7080
7081                 pvclock_update_vm_gtod_copy(kvm);
7082
7083                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7084                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7085
7086                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7087                         kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7088
7089                 spin_unlock(&ka->pvclock_gtod_sync_lock);
7090         }
7091         mutex_unlock(&kvm_lock);
7092 }
7093 #endif
7094
7095 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7096 {
7097         struct kvm *kvm;
7098         struct kvm_vcpu *vcpu;
7099         int i, send_ipi = 0;
7100
7101         /*
7102          * We allow guests to temporarily run on slowing clocks,
7103          * provided we notify them after, or to run on accelerating
7104          * clocks, provided we notify them before.  Thus time never
7105          * goes backwards.
7106          *
7107          * However, we have a problem.  We can't atomically update
7108          * the frequency of a given CPU from this function; it is
7109          * merely a notifier, which can be called from any CPU.
7110          * Changing the TSC frequency at arbitrary points in time
7111          * requires a recomputation of local variables related to
7112          * the TSC for each VCPU.  We must flag these local variables
7113          * to be updated and be sure the update takes place with the
7114          * new frequency before any guests proceed.
7115          *
7116          * Unfortunately, the combination of hotplug CPU and frequency
7117          * change creates an intractable locking scenario; the order
7118          * of when these callouts happen is undefined with respect to
7119          * CPU hotplug, and they can race with each other.  As such,
7120          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7121          * undefined; you can actually have a CPU frequency change take
7122          * place in between the computation of X and the setting of the
7123          * variable.  To protect against this problem, all updates of
7124          * the per_cpu tsc_khz variable are done in an interrupt
7125          * protected IPI, and all callers wishing to update the value
7126          * must wait for a synchronous IPI to complete (which is trivial
7127          * if the caller is on the CPU already).  This establishes the
7128          * necessary total order on variable updates.
7129          *
7130          * Note that because a guest time update may take place
7131          * anytime after the setting of the VCPU's request bit, the
7132          * correct TSC value must be set before the request.  However,
7133          * to ensure the update actually makes it to any guest which
7134          * starts running in hardware virtualization between the set
7135          * and the acquisition of the spinlock, we must also ping the
7136          * CPU after setting the request bit.
7137          *
7138          */
7139
7140         smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7141
7142         mutex_lock(&kvm_lock);
7143         list_for_each_entry(kvm, &vm_list, vm_list) {
7144                 kvm_for_each_vcpu(i, vcpu, kvm) {
7145                         if (vcpu->cpu != cpu)
7146                                 continue;
7147                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7148                         if (vcpu->cpu != raw_smp_processor_id())
7149                                 send_ipi = 1;
7150                 }
7151         }
7152         mutex_unlock(&kvm_lock);
7153
7154         if (freq->old < freq->new && send_ipi) {
7155                 /*
7156                  * We upscale the frequency.  Must make the guest
7157                  * doesn't see old kvmclock values while running with
7158                  * the new frequency, otherwise we risk the guest sees
7159                  * time go backwards.
7160                  *
7161                  * In case we update the frequency for another cpu
7162                  * (which might be in guest context) send an interrupt
7163                  * to kick the cpu out of guest context.  Next time
7164                  * guest context is entered kvmclock will be updated,
7165                  * so the guest will not see stale values.
7166                  */
7167                 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7168         }
7169 }
7170
7171 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7172                                      void *data)
7173 {
7174         struct cpufreq_freqs *freq = data;
7175         int cpu;
7176
7177         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7178                 return 0;
7179         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7180                 return 0;
7181
7182         for_each_cpu(cpu, freq->policy->cpus)
7183                 __kvmclock_cpufreq_notifier(freq, cpu);
7184
7185         return 0;
7186 }
7187
7188 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7189         .notifier_call  = kvmclock_cpufreq_notifier
7190 };
7191
7192 static int kvmclock_cpu_online(unsigned int cpu)
7193 {
7194         tsc_khz_changed(NULL);
7195         return 0;
7196 }
7197
7198 static void kvm_timer_init(void)
7199 {
7200         max_tsc_khz = tsc_khz;
7201
7202         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7203 #ifdef CONFIG_CPU_FREQ
7204                 struct cpufreq_policy *policy;
7205                 int cpu;
7206
7207                 cpu = get_cpu();
7208                 policy = cpufreq_cpu_get(cpu);
7209                 if (policy) {
7210                         if (policy->cpuinfo.max_freq)
7211                                 max_tsc_khz = policy->cpuinfo.max_freq;
7212                         cpufreq_cpu_put(policy);
7213                 }
7214                 put_cpu();
7215 #endif
7216                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7217                                           CPUFREQ_TRANSITION_NOTIFIER);
7218         }
7219
7220         cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7221                           kvmclock_cpu_online, kvmclock_cpu_down_prep);
7222 }
7223
7224 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7225 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7226
7227 int kvm_is_in_guest(void)
7228 {
7229         return __this_cpu_read(current_vcpu) != NULL;
7230 }
7231
7232 static int kvm_is_user_mode(void)
7233 {
7234         int user_mode = 3;
7235
7236         if (__this_cpu_read(current_vcpu))
7237                 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7238
7239         return user_mode != 0;
7240 }
7241
7242 static unsigned long kvm_get_guest_ip(void)
7243 {
7244         unsigned long ip = 0;
7245
7246         if (__this_cpu_read(current_vcpu))
7247                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7248
7249         return ip;
7250 }
7251
7252 static void kvm_handle_intel_pt_intr(void)
7253 {
7254         struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7255
7256         kvm_make_request(KVM_REQ_PMI, vcpu);
7257         __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7258                         (unsigned long *)&vcpu->arch.pmu.global_status);
7259 }
7260
7261 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7262         .is_in_guest            = kvm_is_in_guest,
7263         .is_user_mode           = kvm_is_user_mode,
7264         .get_guest_ip           = kvm_get_guest_ip,
7265         .handle_intel_pt_intr   = kvm_handle_intel_pt_intr,
7266 };
7267
7268 #ifdef CONFIG_X86_64
7269 static void pvclock_gtod_update_fn(struct work_struct *work)
7270 {
7271         struct kvm *kvm;
7272
7273         struct kvm_vcpu *vcpu;
7274         int i;
7275
7276         mutex_lock(&kvm_lock);
7277         list_for_each_entry(kvm, &vm_list, vm_list)
7278                 kvm_for_each_vcpu(i, vcpu, kvm)
7279                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7280         atomic_set(&kvm_guest_has_master_clock, 0);
7281         mutex_unlock(&kvm_lock);
7282 }
7283
7284 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7285
7286 /*
7287  * Notification about pvclock gtod data update.
7288  */
7289 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7290                                void *priv)
7291 {
7292         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7293         struct timekeeper *tk = priv;
7294
7295         update_pvclock_gtod(tk);
7296
7297         /* disable master clock if host does not trust, or does not
7298          * use, TSC based clocksource.
7299          */
7300         if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7301             atomic_read(&kvm_guest_has_master_clock) != 0)
7302                 queue_work(system_long_wq, &pvclock_gtod_work);
7303
7304         return 0;
7305 }
7306
7307 static struct notifier_block pvclock_gtod_notifier = {
7308         .notifier_call = pvclock_gtod_notify,
7309 };
7310 #endif
7311
7312 int kvm_arch_init(void *opaque)
7313 {
7314         struct kvm_x86_init_ops *ops = opaque;
7315         int r;
7316
7317         if (kvm_x86_ops.hardware_enable) {
7318                 printk(KERN_ERR "kvm: already loaded the other module\n");
7319                 r = -EEXIST;
7320                 goto out;
7321         }
7322
7323         if (!ops->cpu_has_kvm_support()) {
7324                 pr_err_ratelimited("kvm: no hardware support\n");
7325                 r = -EOPNOTSUPP;
7326                 goto out;
7327         }
7328         if (ops->disabled_by_bios()) {
7329                 pr_err_ratelimited("kvm: disabled by bios\n");
7330                 r = -EOPNOTSUPP;
7331                 goto out;
7332         }
7333
7334         /*
7335          * KVM explicitly assumes that the guest has an FPU and
7336          * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7337          * vCPU's FPU state as a fxregs_state struct.
7338          */
7339         if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7340                 printk(KERN_ERR "kvm: inadequate fpu\n");
7341                 r = -EOPNOTSUPP;
7342                 goto out;
7343         }
7344
7345         r = -ENOMEM;
7346         x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7347                                           __alignof__(struct fpu), SLAB_ACCOUNT,
7348                                           NULL);
7349         if (!x86_fpu_cache) {
7350                 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7351                 goto out;
7352         }
7353
7354         x86_emulator_cache = kvm_alloc_emulator_cache();
7355         if (!x86_emulator_cache) {
7356                 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7357                 goto out_free_x86_fpu_cache;
7358         }
7359
7360         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7361         if (!shared_msrs) {
7362                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7363                 goto out_free_x86_emulator_cache;
7364         }
7365
7366         r = kvm_mmu_module_init();
7367         if (r)
7368                 goto out_free_percpu;
7369
7370         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7371                         PT_DIRTY_MASK, PT64_NX_MASK, 0,
7372                         PT_PRESENT_MASK, 0, sme_me_mask);
7373         kvm_timer_init();
7374
7375         perf_register_guest_info_callbacks(&kvm_guest_cbs);
7376
7377         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7378                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7379                 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7380         }
7381
7382         kvm_lapic_init();
7383         if (pi_inject_timer == -1)
7384                 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7385 #ifdef CONFIG_X86_64
7386         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7387
7388         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7389                 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7390 #endif
7391
7392         return 0;
7393
7394 out_free_percpu:
7395         free_percpu(shared_msrs);
7396 out_free_x86_emulator_cache:
7397         kmem_cache_destroy(x86_emulator_cache);
7398 out_free_x86_fpu_cache:
7399         kmem_cache_destroy(x86_fpu_cache);
7400 out:
7401         return r;
7402 }
7403
7404 void kvm_arch_exit(void)
7405 {
7406 #ifdef CONFIG_X86_64
7407         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7408                 clear_hv_tscchange_cb();
7409 #endif
7410         kvm_lapic_exit();
7411         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7412
7413         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7414                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7415                                             CPUFREQ_TRANSITION_NOTIFIER);
7416         cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7417 #ifdef CONFIG_X86_64
7418         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7419 #endif
7420         kvm_x86_ops.hardware_enable = NULL;
7421         kvm_mmu_module_exit();
7422         free_percpu(shared_msrs);
7423         kmem_cache_destroy(x86_fpu_cache);
7424 }
7425
7426 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7427 {
7428         ++vcpu->stat.halt_exits;
7429         if (lapic_in_kernel(vcpu)) {
7430                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7431                 return 1;
7432         } else {
7433                 vcpu->run->exit_reason = KVM_EXIT_HLT;
7434                 return 0;
7435         }
7436 }
7437 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7438
7439 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7440 {
7441         int ret = kvm_skip_emulated_instruction(vcpu);
7442         /*
7443          * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7444          * KVM_EXIT_DEBUG here.
7445          */
7446         return kvm_vcpu_halt(vcpu) && ret;
7447 }
7448 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7449
7450 #ifdef CONFIG_X86_64
7451 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7452                                 unsigned long clock_type)
7453 {
7454         struct kvm_clock_pairing clock_pairing;
7455         struct timespec64 ts;
7456         u64 cycle;
7457         int ret;
7458
7459         if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7460                 return -KVM_EOPNOTSUPP;
7461
7462         if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7463                 return -KVM_EOPNOTSUPP;
7464
7465         clock_pairing.sec = ts.tv_sec;
7466         clock_pairing.nsec = ts.tv_nsec;
7467         clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7468         clock_pairing.flags = 0;
7469         memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7470
7471         ret = 0;
7472         if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7473                             sizeof(struct kvm_clock_pairing)))
7474                 ret = -KVM_EFAULT;
7475
7476         return ret;
7477 }
7478 #endif
7479
7480 /*
7481  * kvm_pv_kick_cpu_op:  Kick a vcpu.
7482  *
7483  * @apicid - apicid of vcpu to be kicked.
7484  */
7485 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7486 {
7487         struct kvm_lapic_irq lapic_irq;
7488
7489         lapic_irq.shorthand = APIC_DEST_NOSHORT;
7490         lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7491         lapic_irq.level = 0;
7492         lapic_irq.dest_id = apicid;
7493         lapic_irq.msi_redir_hint = false;
7494
7495         lapic_irq.delivery_mode = APIC_DM_REMRD;
7496         kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7497 }
7498
7499 bool kvm_apicv_activated(struct kvm *kvm)
7500 {
7501         return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7502 }
7503 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7504
7505 void kvm_apicv_init(struct kvm *kvm, bool enable)
7506 {
7507         if (enable)
7508                 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7509                           &kvm->arch.apicv_inhibit_reasons);
7510         else
7511                 set_bit(APICV_INHIBIT_REASON_DISABLE,
7512                         &kvm->arch.apicv_inhibit_reasons);
7513 }
7514 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7515
7516 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7517 {
7518         struct kvm_vcpu *target = NULL;
7519         struct kvm_apic_map *map;
7520
7521         rcu_read_lock();
7522         map = rcu_dereference(kvm->arch.apic_map);
7523
7524         if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7525                 target = map->phys_map[dest_id]->vcpu;
7526
7527         rcu_read_unlock();
7528
7529         if (target && READ_ONCE(target->ready))
7530                 kvm_vcpu_yield_to(target);
7531 }
7532
7533 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7534 {
7535         unsigned long nr, a0, a1, a2, a3, ret;
7536         int op_64_bit;
7537
7538         if (kvm_hv_hypercall_enabled(vcpu->kvm))
7539                 return kvm_hv_hypercall(vcpu);
7540
7541         nr = kvm_rax_read(vcpu);
7542         a0 = kvm_rbx_read(vcpu);
7543         a1 = kvm_rcx_read(vcpu);
7544         a2 = kvm_rdx_read(vcpu);
7545         a3 = kvm_rsi_read(vcpu);
7546
7547         trace_kvm_hypercall(nr, a0, a1, a2, a3);
7548
7549         op_64_bit = is_64_bit_mode(vcpu);
7550         if (!op_64_bit) {
7551                 nr &= 0xFFFFFFFF;
7552                 a0 &= 0xFFFFFFFF;
7553                 a1 &= 0xFFFFFFFF;
7554                 a2 &= 0xFFFFFFFF;
7555                 a3 &= 0xFFFFFFFF;
7556         }
7557
7558         if (kvm_x86_ops.get_cpl(vcpu) != 0) {
7559                 ret = -KVM_EPERM;
7560                 goto out;
7561         }
7562
7563         switch (nr) {
7564         case KVM_HC_VAPIC_POLL_IRQ:
7565                 ret = 0;
7566                 break;
7567         case KVM_HC_KICK_CPU:
7568                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7569                 kvm_sched_yield(vcpu->kvm, a1);
7570                 ret = 0;
7571                 break;
7572 #ifdef CONFIG_X86_64
7573         case KVM_HC_CLOCK_PAIRING:
7574                 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7575                 break;
7576 #endif
7577         case KVM_HC_SEND_IPI:
7578                 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7579                 break;
7580         case KVM_HC_SCHED_YIELD:
7581                 kvm_sched_yield(vcpu->kvm, a0);
7582                 ret = 0;
7583                 break;
7584         default:
7585                 ret = -KVM_ENOSYS;
7586                 break;
7587         }
7588 out:
7589         if (!op_64_bit)
7590                 ret = (u32)ret;
7591         kvm_rax_write(vcpu, ret);
7592
7593         ++vcpu->stat.hypercalls;
7594         return kvm_skip_emulated_instruction(vcpu);
7595 }
7596 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7597
7598 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7599 {
7600         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7601         char instruction[3];
7602         unsigned long rip = kvm_rip_read(vcpu);
7603
7604         kvm_x86_ops.patch_hypercall(vcpu, instruction);
7605
7606         return emulator_write_emulated(ctxt, rip, instruction, 3,
7607                 &ctxt->exception);
7608 }
7609
7610 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7611 {
7612         return vcpu->run->request_interrupt_window &&
7613                 likely(!pic_in_kernel(vcpu->kvm));
7614 }
7615
7616 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7617 {
7618         struct kvm_run *kvm_run = vcpu->run;
7619
7620         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7621         kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7622         kvm_run->cr8 = kvm_get_cr8(vcpu);
7623         kvm_run->apic_base = kvm_get_apic_base(vcpu);
7624         kvm_run->ready_for_interrupt_injection =
7625                 pic_in_kernel(vcpu->kvm) ||
7626                 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7627 }
7628
7629 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7630 {
7631         int max_irr, tpr;
7632
7633         if (!kvm_x86_ops.update_cr8_intercept)
7634                 return;
7635
7636         if (!lapic_in_kernel(vcpu))
7637                 return;
7638
7639         if (vcpu->arch.apicv_active)
7640                 return;
7641
7642         if (!vcpu->arch.apic->vapic_addr)
7643                 max_irr = kvm_lapic_find_highest_irr(vcpu);
7644         else
7645                 max_irr = -1;
7646
7647         if (max_irr != -1)
7648                 max_irr >>= 4;
7649
7650         tpr = kvm_lapic_get_cr8(vcpu);
7651
7652         kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
7653 }
7654
7655 static int inject_pending_event(struct kvm_vcpu *vcpu)
7656 {
7657         int r;
7658
7659         /* try to reinject previous events if any */
7660
7661         if (vcpu->arch.exception.injected)
7662                 kvm_x86_ops.queue_exception(vcpu);
7663         /*
7664          * Do not inject an NMI or interrupt if there is a pending
7665          * exception.  Exceptions and interrupts are recognized at
7666          * instruction boundaries, i.e. the start of an instruction.
7667          * Trap-like exceptions, e.g. #DB, have higher priority than
7668          * NMIs and interrupts, i.e. traps are recognized before an
7669          * NMI/interrupt that's pending on the same instruction.
7670          * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7671          * priority, but are only generated (pended) during instruction
7672          * execution, i.e. a pending fault-like exception means the
7673          * fault occurred on the *previous* instruction and must be
7674          * serviced prior to recognizing any new events in order to
7675          * fully complete the previous instruction.
7676          */
7677         else if (!vcpu->arch.exception.pending) {
7678                 if (vcpu->arch.nmi_injected)
7679                         kvm_x86_ops.set_nmi(vcpu);
7680                 else if (vcpu->arch.interrupt.injected)
7681                         kvm_x86_ops.set_irq(vcpu);
7682         }
7683
7684         /*
7685          * Call check_nested_events() even if we reinjected a previous event
7686          * in order for caller to determine if it should require immediate-exit
7687          * from L2 to L1 due to pending L1 events which require exit
7688          * from L2 to L1.
7689          */
7690         if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) {
7691                 r = kvm_x86_ops.check_nested_events(vcpu);
7692                 if (r != 0)
7693                         return r;
7694         }
7695
7696         /* try to inject new event if pending */
7697         if (vcpu->arch.exception.pending) {
7698                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7699                                         vcpu->arch.exception.has_error_code,
7700                                         vcpu->arch.exception.error_code);
7701
7702                 WARN_ON_ONCE(vcpu->arch.exception.injected);
7703                 vcpu->arch.exception.pending = false;
7704                 vcpu->arch.exception.injected = true;
7705
7706                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7707                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7708                                              X86_EFLAGS_RF);
7709
7710                 if (vcpu->arch.exception.nr == DB_VECTOR) {
7711                         /*
7712                          * This code assumes that nSVM doesn't use
7713                          * check_nested_events(). If it does, the
7714                          * DR6/DR7 changes should happen before L1
7715                          * gets a #VMEXIT for an intercepted #DB in
7716                          * L2.  (Under VMX, on the other hand, the
7717                          * DR6/DR7 changes should not happen in the
7718                          * event of a VM-exit to L1 for an intercepted
7719                          * #DB in L2.)
7720                          */
7721                         kvm_deliver_exception_payload(vcpu);
7722                         if (vcpu->arch.dr7 & DR7_GD) {
7723                                 vcpu->arch.dr7 &= ~DR7_GD;
7724                                 kvm_update_dr7(vcpu);
7725                         }
7726                 }
7727
7728                 kvm_x86_ops.queue_exception(vcpu);
7729         }
7730
7731         /* Don't consider new event if we re-injected an event */
7732         if (kvm_event_needs_reinjection(vcpu))
7733                 return 0;
7734
7735         if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7736             kvm_x86_ops.smi_allowed(vcpu)) {
7737                 vcpu->arch.smi_pending = false;
7738                 ++vcpu->arch.smi_count;
7739                 enter_smm(vcpu);
7740         } else if (vcpu->arch.nmi_pending && kvm_x86_ops.nmi_allowed(vcpu)) {
7741                 --vcpu->arch.nmi_pending;
7742                 vcpu->arch.nmi_injected = true;
7743                 kvm_x86_ops.set_nmi(vcpu);
7744         } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7745                 /*
7746                  * Because interrupts can be injected asynchronously, we are
7747                  * calling check_nested_events again here to avoid a race condition.
7748                  * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7749                  * proposal and current concerns.  Perhaps we should be setting
7750                  * KVM_REQ_EVENT only on certain events and not unconditionally?
7751                  */
7752                 if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) {
7753                         r = kvm_x86_ops.check_nested_events(vcpu);
7754                         if (r != 0)
7755                                 return r;
7756                 }
7757                 if (kvm_x86_ops.interrupt_allowed(vcpu)) {
7758                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7759                                             false);
7760                         kvm_x86_ops.set_irq(vcpu);
7761                 }
7762         }
7763
7764         return 0;
7765 }
7766
7767 static void process_nmi(struct kvm_vcpu *vcpu)
7768 {
7769         unsigned limit = 2;
7770
7771         /*
7772          * x86 is limited to one NMI running, and one NMI pending after it.
7773          * If an NMI is already in progress, limit further NMIs to just one.
7774          * Otherwise, allow two (and we'll inject the first one immediately).
7775          */
7776         if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7777                 limit = 1;
7778
7779         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7780         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7781         kvm_make_request(KVM_REQ_EVENT, vcpu);
7782 }
7783
7784 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7785 {
7786         u32 flags = 0;
7787         flags |= seg->g       << 23;
7788         flags |= seg->db      << 22;
7789         flags |= seg->l       << 21;
7790         flags |= seg->avl     << 20;
7791         flags |= seg->present << 15;
7792         flags |= seg->dpl     << 13;
7793         flags |= seg->s       << 12;
7794         flags |= seg->type    << 8;
7795         return flags;
7796 }
7797
7798 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7799 {
7800         struct kvm_segment seg;
7801         int offset;
7802
7803         kvm_get_segment(vcpu, &seg, n);
7804         put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7805
7806         if (n < 3)
7807                 offset = 0x7f84 + n * 12;
7808         else
7809                 offset = 0x7f2c + (n - 3) * 12;
7810
7811         put_smstate(u32, buf, offset + 8, seg.base);
7812         put_smstate(u32, buf, offset + 4, seg.limit);
7813         put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7814 }
7815
7816 #ifdef CONFIG_X86_64
7817 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7818 {
7819         struct kvm_segment seg;
7820         int offset;
7821         u16 flags;
7822
7823         kvm_get_segment(vcpu, &seg, n);
7824         offset = 0x7e00 + n * 16;
7825
7826         flags = enter_smm_get_segment_flags(&seg) >> 8;
7827         put_smstate(u16, buf, offset, seg.selector);
7828         put_smstate(u16, buf, offset + 2, flags);
7829         put_smstate(u32, buf, offset + 4, seg.limit);
7830         put_smstate(u64, buf, offset + 8, seg.base);
7831 }
7832 #endif
7833
7834 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7835 {
7836         struct desc_ptr dt;
7837         struct kvm_segment seg;
7838         unsigned long val;
7839         int i;
7840
7841         put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7842         put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7843         put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7844         put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7845
7846         for (i = 0; i < 8; i++)
7847                 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7848
7849         kvm_get_dr(vcpu, 6, &val);
7850         put_smstate(u32, buf, 0x7fcc, (u32)val);
7851         kvm_get_dr(vcpu, 7, &val);
7852         put_smstate(u32, buf, 0x7fc8, (u32)val);
7853
7854         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7855         put_smstate(u32, buf, 0x7fc4, seg.selector);
7856         put_smstate(u32, buf, 0x7f64, seg.base);
7857         put_smstate(u32, buf, 0x7f60, seg.limit);
7858         put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7859
7860         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7861         put_smstate(u32, buf, 0x7fc0, seg.selector);
7862         put_smstate(u32, buf, 0x7f80, seg.base);
7863         put_smstate(u32, buf, 0x7f7c, seg.limit);
7864         put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7865
7866         kvm_x86_ops.get_gdt(vcpu, &dt);
7867         put_smstate(u32, buf, 0x7f74, dt.address);
7868         put_smstate(u32, buf, 0x7f70, dt.size);
7869
7870         kvm_x86_ops.get_idt(vcpu, &dt);
7871         put_smstate(u32, buf, 0x7f58, dt.address);
7872         put_smstate(u32, buf, 0x7f54, dt.size);
7873
7874         for (i = 0; i < 6; i++)
7875                 enter_smm_save_seg_32(vcpu, buf, i);
7876
7877         put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7878
7879         /* revision id */
7880         put_smstate(u32, buf, 0x7efc, 0x00020000);
7881         put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7882 }
7883
7884 #ifdef CONFIG_X86_64
7885 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7886 {
7887         struct desc_ptr dt;
7888         struct kvm_segment seg;
7889         unsigned long val;
7890         int i;
7891
7892         for (i = 0; i < 16; i++)
7893                 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7894
7895         put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7896         put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7897
7898         kvm_get_dr(vcpu, 6, &val);
7899         put_smstate(u64, buf, 0x7f68, val);
7900         kvm_get_dr(vcpu, 7, &val);
7901         put_smstate(u64, buf, 0x7f60, val);
7902
7903         put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7904         put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7905         put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7906
7907         put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7908
7909         /* revision id */
7910         put_smstate(u32, buf, 0x7efc, 0x00020064);
7911
7912         put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7913
7914         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7915         put_smstate(u16, buf, 0x7e90, seg.selector);
7916         put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7917         put_smstate(u32, buf, 0x7e94, seg.limit);
7918         put_smstate(u64, buf, 0x7e98, seg.base);
7919
7920         kvm_x86_ops.get_idt(vcpu, &dt);
7921         put_smstate(u32, buf, 0x7e84, dt.size);
7922         put_smstate(u64, buf, 0x7e88, dt.address);
7923
7924         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7925         put_smstate(u16, buf, 0x7e70, seg.selector);
7926         put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7927         put_smstate(u32, buf, 0x7e74, seg.limit);
7928         put_smstate(u64, buf, 0x7e78, seg.base);
7929
7930         kvm_x86_ops.get_gdt(vcpu, &dt);
7931         put_smstate(u32, buf, 0x7e64, dt.size);
7932         put_smstate(u64, buf, 0x7e68, dt.address);
7933
7934         for (i = 0; i < 6; i++)
7935                 enter_smm_save_seg_64(vcpu, buf, i);
7936 }
7937 #endif
7938
7939 static void enter_smm(struct kvm_vcpu *vcpu)
7940 {
7941         struct kvm_segment cs, ds;
7942         struct desc_ptr dt;
7943         char buf[512];
7944         u32 cr0;
7945
7946         trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7947         memset(buf, 0, 512);
7948 #ifdef CONFIG_X86_64
7949         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7950                 enter_smm_save_state_64(vcpu, buf);
7951         else
7952 #endif
7953                 enter_smm_save_state_32(vcpu, buf);
7954
7955         /*
7956          * Give pre_enter_smm() a chance to make ISA-specific changes to the
7957          * vCPU state (e.g. leave guest mode) after we've saved the state into
7958          * the SMM state-save area.
7959          */
7960         kvm_x86_ops.pre_enter_smm(vcpu, buf);
7961
7962         vcpu->arch.hflags |= HF_SMM_MASK;
7963         kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7964
7965         if (kvm_x86_ops.get_nmi_mask(vcpu))
7966                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7967         else
7968                 kvm_x86_ops.set_nmi_mask(vcpu, true);
7969
7970         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7971         kvm_rip_write(vcpu, 0x8000);
7972
7973         cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7974         kvm_x86_ops.set_cr0(vcpu, cr0);
7975         vcpu->arch.cr0 = cr0;
7976
7977         kvm_x86_ops.set_cr4(vcpu, 0);
7978
7979         /* Undocumented: IDT limit is set to zero on entry to SMM.  */
7980         dt.address = dt.size = 0;
7981         kvm_x86_ops.set_idt(vcpu, &dt);
7982
7983         __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7984
7985         cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7986         cs.base = vcpu->arch.smbase;
7987
7988         ds.selector = 0;
7989         ds.base = 0;
7990
7991         cs.limit    = ds.limit = 0xffffffff;
7992         cs.type     = ds.type = 0x3;
7993         cs.dpl      = ds.dpl = 0;
7994         cs.db       = ds.db = 0;
7995         cs.s        = ds.s = 1;
7996         cs.l        = ds.l = 0;
7997         cs.g        = ds.g = 1;
7998         cs.avl      = ds.avl = 0;
7999         cs.present  = ds.present = 1;
8000         cs.unusable = ds.unusable = 0;
8001         cs.padding  = ds.padding = 0;
8002
8003         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8004         kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8005         kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8006         kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8007         kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8008         kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8009
8010 #ifdef CONFIG_X86_64
8011         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8012                 kvm_x86_ops.set_efer(vcpu, 0);
8013 #endif
8014
8015         kvm_update_cpuid(vcpu);
8016         kvm_mmu_reset_context(vcpu);
8017 }
8018
8019 static void process_smi(struct kvm_vcpu *vcpu)
8020 {
8021         vcpu->arch.smi_pending = true;
8022         kvm_make_request(KVM_REQ_EVENT, vcpu);
8023 }
8024
8025 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8026                                        unsigned long *vcpu_bitmap)
8027 {
8028         cpumask_var_t cpus;
8029
8030         zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8031
8032         kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8033                                     vcpu_bitmap, cpus);
8034
8035         free_cpumask_var(cpus);
8036 }
8037
8038 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8039 {
8040         kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8041 }
8042
8043 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8044 {
8045         if (!lapic_in_kernel(vcpu))
8046                 return;
8047
8048         vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8049         kvm_apic_update_apicv(vcpu);
8050         kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8051 }
8052 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8053
8054 /*
8055  * NOTE: Do not hold any lock prior to calling this.
8056  *
8057  * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8058  * locked, because it calls __x86_set_memory_region() which does
8059  * synchronize_srcu(&kvm->srcu).
8060  */
8061 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8062 {
8063         unsigned long old, new, expected;
8064
8065         if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8066             !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8067                 return;
8068
8069         old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8070         do {
8071                 expected = new = old;
8072                 if (activate)
8073                         __clear_bit(bit, &new);
8074                 else
8075                         __set_bit(bit, &new);
8076                 if (new == old)
8077                         break;
8078                 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8079         } while (old != expected);
8080
8081         if (!!old == !!new)
8082                 return;
8083
8084         trace_kvm_apicv_update_request(activate, bit);
8085         if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8086                 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8087         kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
8088 }
8089 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8090
8091 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8092 {
8093         if (!kvm_apic_present(vcpu))
8094                 return;
8095
8096         bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8097
8098         if (irqchip_split(vcpu->kvm))
8099                 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8100         else {
8101                 if (vcpu->arch.apicv_active)
8102                         kvm_x86_ops.sync_pir_to_irr(vcpu);
8103                 if (ioapic_in_kernel(vcpu->kvm))
8104                         kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8105         }
8106
8107         if (is_guest_mode(vcpu))
8108                 vcpu->arch.load_eoi_exitmap_pending = true;
8109         else
8110                 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8111 }
8112
8113 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8114 {
8115         u64 eoi_exit_bitmap[4];
8116
8117         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8118                 return;
8119
8120         bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8121                   vcpu_to_synic(vcpu)->vec_bitmap, 256);
8122         kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8123 }
8124
8125 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8126                 unsigned long start, unsigned long end,
8127                 bool blockable)
8128 {
8129         unsigned long apic_address;
8130
8131         /*
8132          * The physical address of apic access page is stored in the VMCS.
8133          * Update it when it becomes invalid.
8134          */
8135         apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8136         if (start <= apic_address && apic_address < end)
8137                 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8138
8139         return 0;
8140 }
8141
8142 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8143 {
8144         struct page *page = NULL;
8145
8146         if (!lapic_in_kernel(vcpu))
8147                 return;
8148
8149         if (!kvm_x86_ops.set_apic_access_page_addr)
8150                 return;
8151
8152         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8153         if (is_error_page(page))
8154                 return;
8155         kvm_x86_ops.set_apic_access_page_addr(vcpu, page_to_phys(page));
8156
8157         /*
8158          * Do not pin apic access page in memory, the MMU notifier
8159          * will call us again if it is migrated or swapped out.
8160          */
8161         put_page(page);
8162 }
8163
8164 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8165 {
8166         smp_send_reschedule(vcpu->cpu);
8167 }
8168 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8169
8170 /*
8171  * Returns 1 to let vcpu_run() continue the guest execution loop without
8172  * exiting to the userspace.  Otherwise, the value will be returned to the
8173  * userspace.
8174  */
8175 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8176 {
8177         int r;
8178         bool req_int_win =
8179                 dm_request_for_irq_injection(vcpu) &&
8180                 kvm_cpu_accept_dm_intr(vcpu);
8181         enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE;
8182
8183         bool req_immediate_exit = false;
8184
8185         if (kvm_request_pending(vcpu)) {
8186                 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8187                         if (unlikely(!kvm_x86_ops.get_vmcs12_pages(vcpu))) {
8188                                 r = 0;
8189                                 goto out;
8190                         }
8191                 }
8192                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8193                         kvm_mmu_unload(vcpu);
8194                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8195                         __kvm_migrate_timers(vcpu);
8196                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8197                         kvm_gen_update_masterclock(vcpu->kvm);
8198                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8199                         kvm_gen_kvmclock_update(vcpu);
8200                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8201                         r = kvm_guest_time_update(vcpu);
8202                         if (unlikely(r))
8203                                 goto out;
8204                 }
8205                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8206                         kvm_mmu_sync_roots(vcpu);
8207                 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8208                         kvm_mmu_load_pgd(vcpu);
8209                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
8210                         kvm_vcpu_flush_tlb(vcpu, true);
8211                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8212                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8213                         r = 0;
8214                         goto out;
8215                 }
8216                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8217                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8218                         vcpu->mmio_needed = 0;
8219                         r = 0;
8220                         goto out;
8221                 }
8222                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8223                         /* Page is swapped out. Do synthetic halt */
8224                         vcpu->arch.apf.halted = true;
8225                         r = 1;
8226                         goto out;
8227                 }
8228                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8229                         record_steal_time(vcpu);
8230                 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8231                         process_smi(vcpu);
8232                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8233                         process_nmi(vcpu);
8234                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8235                         kvm_pmu_handle_event(vcpu);
8236                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8237                         kvm_pmu_deliver_pmi(vcpu);
8238                 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8239                         BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8240                         if (test_bit(vcpu->arch.pending_ioapic_eoi,
8241                                      vcpu->arch.ioapic_handled_vectors)) {
8242                                 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8243                                 vcpu->run->eoi.vector =
8244                                                 vcpu->arch.pending_ioapic_eoi;
8245                                 r = 0;
8246                                 goto out;
8247                         }
8248                 }
8249                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8250                         vcpu_scan_ioapic(vcpu);
8251                 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8252                         vcpu_load_eoi_exitmap(vcpu);
8253                 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8254                         kvm_vcpu_reload_apic_access_page(vcpu);
8255                 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8256                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8257                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8258                         r = 0;
8259                         goto out;
8260                 }
8261                 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8262                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8263                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8264                         r = 0;
8265                         goto out;
8266                 }
8267                 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8268                         vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8269                         vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8270                         r = 0;
8271                         goto out;
8272                 }
8273
8274                 /*
8275                  * KVM_REQ_HV_STIMER has to be processed after
8276                  * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8277                  * depend on the guest clock being up-to-date
8278                  */
8279                 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8280                         kvm_hv_process_stimers(vcpu);
8281                 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8282                         kvm_vcpu_update_apicv(vcpu);
8283         }
8284
8285         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8286                 ++vcpu->stat.req_event;
8287                 kvm_apic_accept_events(vcpu);
8288                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8289                         r = 1;
8290                         goto out;
8291                 }
8292
8293                 if (inject_pending_event(vcpu) != 0)
8294                         req_immediate_exit = true;
8295                 else {
8296                         /* Enable SMI/NMI/IRQ window open exits if needed.
8297                          *
8298                          * SMIs have three cases:
8299                          * 1) They can be nested, and then there is nothing to
8300                          *    do here because RSM will cause a vmexit anyway.
8301                          * 2) There is an ISA-specific reason why SMI cannot be
8302                          *    injected, and the moment when this changes can be
8303                          *    intercepted.
8304                          * 3) Or the SMI can be pending because
8305                          *    inject_pending_event has completed the injection
8306                          *    of an IRQ or NMI from the previous vmexit, and
8307                          *    then we request an immediate exit to inject the
8308                          *    SMI.
8309                          */
8310                         if (vcpu->arch.smi_pending && !is_smm(vcpu))
8311                                 if (!kvm_x86_ops.enable_smi_window(vcpu))
8312                                         req_immediate_exit = true;
8313                         if (vcpu->arch.nmi_pending)
8314                                 kvm_x86_ops.enable_nmi_window(vcpu);
8315                         if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8316                                 kvm_x86_ops.enable_irq_window(vcpu);
8317                         WARN_ON(vcpu->arch.exception.pending);
8318                 }
8319
8320                 if (kvm_lapic_enabled(vcpu)) {
8321                         update_cr8_intercept(vcpu);
8322                         kvm_lapic_sync_to_vapic(vcpu);
8323                 }
8324         }
8325
8326         r = kvm_mmu_reload(vcpu);
8327         if (unlikely(r)) {
8328                 goto cancel_injection;
8329         }
8330
8331         preempt_disable();
8332
8333         kvm_x86_ops.prepare_guest_switch(vcpu);
8334
8335         /*
8336          * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
8337          * IPI are then delayed after guest entry, which ensures that they
8338          * result in virtual interrupt delivery.
8339          */
8340         local_irq_disable();
8341         vcpu->mode = IN_GUEST_MODE;
8342
8343         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8344
8345         /*
8346          * 1) We should set ->mode before checking ->requests.  Please see
8347          * the comment in kvm_vcpu_exiting_guest_mode().
8348          *
8349          * 2) For APICv, we should set ->mode before checking PID.ON. This
8350          * pairs with the memory barrier implicit in pi_test_and_set_on
8351          * (see vmx_deliver_posted_interrupt).
8352          *
8353          * 3) This also orders the write to mode from any reads to the page
8354          * tables done while the VCPU is running.  Please see the comment
8355          * in kvm_flush_remote_tlbs.
8356          */
8357         smp_mb__after_srcu_read_unlock();
8358
8359         /*
8360          * This handles the case where a posted interrupt was
8361          * notified with kvm_vcpu_kick.
8362          */
8363         if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8364                 kvm_x86_ops.sync_pir_to_irr(vcpu);
8365
8366         if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8367             || need_resched() || signal_pending(current)) {
8368                 vcpu->mode = OUTSIDE_GUEST_MODE;
8369                 smp_wmb();
8370                 local_irq_enable();
8371                 preempt_enable();
8372                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8373                 r = 1;
8374                 goto cancel_injection;
8375         }
8376
8377         if (req_immediate_exit) {
8378                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8379                 kvm_x86_ops.request_immediate_exit(vcpu);
8380         }
8381
8382         trace_kvm_entry(vcpu->vcpu_id);
8383         guest_enter_irqoff();
8384
8385         fpregs_assert_state_consistent();
8386         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8387                 switch_fpu_return();
8388
8389         if (unlikely(vcpu->arch.switch_db_regs)) {
8390                 set_debugreg(0, 7);
8391                 set_debugreg(vcpu->arch.eff_db[0], 0);
8392                 set_debugreg(vcpu->arch.eff_db[1], 1);
8393                 set_debugreg(vcpu->arch.eff_db[2], 2);
8394                 set_debugreg(vcpu->arch.eff_db[3], 3);
8395                 set_debugreg(vcpu->arch.dr6, 6);
8396                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8397         }
8398
8399         kvm_x86_ops.run(vcpu);
8400
8401         /*
8402          * Do this here before restoring debug registers on the host.  And
8403          * since we do this before handling the vmexit, a DR access vmexit
8404          * can (a) read the correct value of the debug registers, (b) set
8405          * KVM_DEBUGREG_WONT_EXIT again.
8406          */
8407         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8408                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8409                 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8410                 kvm_update_dr0123(vcpu);
8411                 kvm_update_dr7(vcpu);
8412                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8413         }
8414
8415         /*
8416          * If the guest has used debug registers, at least dr7
8417          * will be disabled while returning to the host.
8418          * If we don't have active breakpoints in the host, we don't
8419          * care about the messed up debug address registers. But if
8420          * we have some of them active, restore the old state.
8421          */
8422         if (hw_breakpoint_active())
8423                 hw_breakpoint_restore();
8424
8425         vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8426
8427         vcpu->mode = OUTSIDE_GUEST_MODE;
8428         smp_wmb();
8429
8430         kvm_x86_ops.handle_exit_irqoff(vcpu, &exit_fastpath);
8431
8432         /*
8433          * Consume any pending interrupts, including the possible source of
8434          * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8435          * An instruction is required after local_irq_enable() to fully unblock
8436          * interrupts on processors that implement an interrupt shadow, the
8437          * stat.exits increment will do nicely.
8438          */
8439         kvm_before_interrupt(vcpu);
8440         local_irq_enable();
8441         ++vcpu->stat.exits;
8442         local_irq_disable();
8443         kvm_after_interrupt(vcpu);
8444
8445         guest_exit_irqoff();
8446         if (lapic_in_kernel(vcpu)) {
8447                 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8448                 if (delta != S64_MIN) {
8449                         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8450                         vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8451                 }
8452         }
8453
8454         local_irq_enable();
8455         preempt_enable();
8456
8457         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8458
8459         /*
8460          * Profile KVM exit RIPs:
8461          */
8462         if (unlikely(prof_on == KVM_PROFILING)) {
8463                 unsigned long rip = kvm_rip_read(vcpu);
8464                 profile_hit(KVM_PROFILING, (void *)rip);
8465         }
8466
8467         if (unlikely(vcpu->arch.tsc_always_catchup))
8468                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8469
8470         if (vcpu->arch.apic_attention)
8471                 kvm_lapic_sync_from_vapic(vcpu);
8472
8473         r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
8474         return r;
8475
8476 cancel_injection:
8477         kvm_x86_ops.cancel_injection(vcpu);
8478         if (unlikely(vcpu->arch.apic_attention))
8479                 kvm_lapic_sync_from_vapic(vcpu);
8480 out:
8481         return r;
8482 }
8483
8484 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8485 {
8486         if (!kvm_arch_vcpu_runnable(vcpu) &&
8487             (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
8488                 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8489                 kvm_vcpu_block(vcpu);
8490                 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8491
8492                 if (kvm_x86_ops.post_block)
8493                         kvm_x86_ops.post_block(vcpu);
8494
8495                 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8496                         return 1;
8497         }
8498
8499         kvm_apic_accept_events(vcpu);
8500         switch(vcpu->arch.mp_state) {
8501         case KVM_MP_STATE_HALTED:
8502                 vcpu->arch.pv.pv_unhalted = false;
8503                 vcpu->arch.mp_state =
8504                         KVM_MP_STATE_RUNNABLE;
8505                 /* fall through */
8506         case KVM_MP_STATE_RUNNABLE:
8507                 vcpu->arch.apf.halted = false;
8508                 break;
8509         case KVM_MP_STATE_INIT_RECEIVED:
8510                 break;
8511         default:
8512                 return -EINTR;
8513         }
8514         return 1;
8515 }
8516
8517 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8518 {
8519         if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events)
8520                 kvm_x86_ops.check_nested_events(vcpu);
8521
8522         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8523                 !vcpu->arch.apf.halted);
8524 }
8525
8526 static int vcpu_run(struct kvm_vcpu *vcpu)
8527 {
8528         int r;
8529         struct kvm *kvm = vcpu->kvm;
8530
8531         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8532         vcpu->arch.l1tf_flush_l1d = true;
8533
8534         for (;;) {
8535                 if (kvm_vcpu_running(vcpu)) {
8536                         r = vcpu_enter_guest(vcpu);
8537                 } else {
8538                         r = vcpu_block(kvm, vcpu);
8539                 }
8540
8541                 if (r <= 0)
8542                         break;
8543
8544                 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8545                 if (kvm_cpu_has_pending_timer(vcpu))
8546                         kvm_inject_pending_timer_irqs(vcpu);
8547
8548                 if (dm_request_for_irq_injection(vcpu) &&
8549                         kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8550                         r = 0;
8551                         vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8552                         ++vcpu->stat.request_irq_exits;
8553                         break;
8554                 }
8555
8556                 kvm_check_async_pf_completion(vcpu);
8557
8558                 if (signal_pending(current)) {
8559                         r = -EINTR;
8560                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8561                         ++vcpu->stat.signal_exits;
8562                         break;
8563                 }
8564                 if (need_resched()) {
8565                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8566                         cond_resched();
8567                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8568                 }
8569         }
8570
8571         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8572
8573         return r;
8574 }
8575
8576 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8577 {
8578         int r;
8579
8580         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8581         r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8582         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8583         return r;
8584 }
8585
8586 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8587 {
8588         BUG_ON(!vcpu->arch.pio.count);
8589
8590         return complete_emulated_io(vcpu);
8591 }
8592
8593 /*
8594  * Implements the following, as a state machine:
8595  *
8596  * read:
8597  *   for each fragment
8598  *     for each mmio piece in the fragment
8599  *       write gpa, len
8600  *       exit
8601  *       copy data
8602  *   execute insn
8603  *
8604  * write:
8605  *   for each fragment
8606  *     for each mmio piece in the fragment
8607  *       write gpa, len
8608  *       copy data
8609  *       exit
8610  */
8611 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8612 {
8613         struct kvm_run *run = vcpu->run;
8614         struct kvm_mmio_fragment *frag;
8615         unsigned len;
8616
8617         BUG_ON(!vcpu->mmio_needed);
8618
8619         /* Complete previous fragment */
8620         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8621         len = min(8u, frag->len);
8622         if (!vcpu->mmio_is_write)
8623                 memcpy(frag->data, run->mmio.data, len);
8624
8625         if (frag->len <= 8) {
8626                 /* Switch to the next fragment. */
8627                 frag++;
8628                 vcpu->mmio_cur_fragment++;
8629         } else {
8630                 /* Go forward to the next mmio piece. */
8631                 frag->data += len;
8632                 frag->gpa += len;
8633                 frag->len -= len;
8634         }
8635
8636         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8637                 vcpu->mmio_needed = 0;
8638
8639                 /* FIXME: return into emulator if single-stepping.  */
8640                 if (vcpu->mmio_is_write)
8641                         return 1;
8642                 vcpu->mmio_read_completed = 1;
8643                 return complete_emulated_io(vcpu);
8644         }
8645
8646         run->exit_reason = KVM_EXIT_MMIO;
8647         run->mmio.phys_addr = frag->gpa;
8648         if (vcpu->mmio_is_write)
8649                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8650         run->mmio.len = min(8u, frag->len);
8651         run->mmio.is_write = vcpu->mmio_is_write;
8652         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8653         return 0;
8654 }
8655
8656 static void kvm_save_current_fpu(struct fpu *fpu)
8657 {
8658         /*
8659          * If the target FPU state is not resident in the CPU registers, just
8660          * memcpy() from current, else save CPU state directly to the target.
8661          */
8662         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8663                 memcpy(&fpu->state, &current->thread.fpu.state,
8664                        fpu_kernel_xstate_size);
8665         else
8666                 copy_fpregs_to_fpstate(fpu);
8667 }
8668
8669 /* Swap (qemu) user FPU context for the guest FPU context. */
8670 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8671 {
8672         fpregs_lock();
8673
8674         kvm_save_current_fpu(vcpu->arch.user_fpu);
8675
8676         /* PKRU is separately restored in kvm_x86_ops.run.  */
8677         __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8678                                 ~XFEATURE_MASK_PKRU);
8679
8680         fpregs_mark_activate();
8681         fpregs_unlock();
8682
8683         trace_kvm_fpu(1);
8684 }
8685
8686 /* When vcpu_run ends, restore user space FPU context. */
8687 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8688 {
8689         fpregs_lock();
8690
8691         kvm_save_current_fpu(vcpu->arch.guest_fpu);
8692
8693         copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8694
8695         fpregs_mark_activate();
8696         fpregs_unlock();
8697
8698         ++vcpu->stat.fpu_reload;
8699         trace_kvm_fpu(0);
8700 }
8701
8702 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8703 {
8704         int r;
8705
8706         vcpu_load(vcpu);
8707         kvm_sigset_activate(vcpu);
8708         kvm_load_guest_fpu(vcpu);
8709
8710         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8711                 if (kvm_run->immediate_exit) {
8712                         r = -EINTR;
8713                         goto out;
8714                 }
8715                 kvm_vcpu_block(vcpu);
8716                 kvm_apic_accept_events(vcpu);
8717                 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8718                 r = -EAGAIN;
8719                 if (signal_pending(current)) {
8720                         r = -EINTR;
8721                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8722                         ++vcpu->stat.signal_exits;
8723                 }
8724                 goto out;
8725         }
8726
8727         if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8728                 r = -EINVAL;
8729                 goto out;
8730         }
8731
8732         if (vcpu->run->kvm_dirty_regs) {
8733                 r = sync_regs(vcpu);
8734                 if (r != 0)
8735                         goto out;
8736         }
8737
8738         /* re-sync apic's tpr */
8739         if (!lapic_in_kernel(vcpu)) {
8740                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8741                         r = -EINVAL;
8742                         goto out;
8743                 }
8744         }
8745
8746         if (unlikely(vcpu->arch.complete_userspace_io)) {
8747                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8748                 vcpu->arch.complete_userspace_io = NULL;
8749                 r = cui(vcpu);
8750                 if (r <= 0)
8751                         goto out;
8752         } else
8753                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8754
8755         if (kvm_run->immediate_exit)
8756                 r = -EINTR;
8757         else
8758                 r = vcpu_run(vcpu);
8759
8760 out:
8761         kvm_put_guest_fpu(vcpu);
8762         if (vcpu->run->kvm_valid_regs)
8763                 store_regs(vcpu);
8764         post_kvm_run_save(vcpu);
8765         kvm_sigset_deactivate(vcpu);
8766
8767         vcpu_put(vcpu);
8768         return r;
8769 }
8770
8771 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8772 {
8773         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8774                 /*
8775                  * We are here if userspace calls get_regs() in the middle of
8776                  * instruction emulation. Registers state needs to be copied
8777                  * back from emulation context to vcpu. Userspace shouldn't do
8778                  * that usually, but some bad designed PV devices (vmware
8779                  * backdoor interface) need this to work
8780                  */
8781                 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
8782                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8783         }
8784         regs->rax = kvm_rax_read(vcpu);
8785         regs->rbx = kvm_rbx_read(vcpu);
8786         regs->rcx = kvm_rcx_read(vcpu);
8787         regs->rdx = kvm_rdx_read(vcpu);
8788         regs->rsi = kvm_rsi_read(vcpu);
8789         regs->rdi = kvm_rdi_read(vcpu);
8790         regs->rsp = kvm_rsp_read(vcpu);
8791         regs->rbp = kvm_rbp_read(vcpu);
8792 #ifdef CONFIG_X86_64
8793         regs->r8 = kvm_r8_read(vcpu);
8794         regs->r9 = kvm_r9_read(vcpu);
8795         regs->r10 = kvm_r10_read(vcpu);
8796         regs->r11 = kvm_r11_read(vcpu);
8797         regs->r12 = kvm_r12_read(vcpu);
8798         regs->r13 = kvm_r13_read(vcpu);
8799         regs->r14 = kvm_r14_read(vcpu);
8800         regs->r15 = kvm_r15_read(vcpu);
8801 #endif
8802
8803         regs->rip = kvm_rip_read(vcpu);
8804         regs->rflags = kvm_get_rflags(vcpu);
8805 }
8806
8807 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8808 {
8809         vcpu_load(vcpu);
8810         __get_regs(vcpu, regs);
8811         vcpu_put(vcpu);
8812         return 0;
8813 }
8814
8815 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8816 {
8817         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8818         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8819
8820         kvm_rax_write(vcpu, regs->rax);
8821         kvm_rbx_write(vcpu, regs->rbx);
8822         kvm_rcx_write(vcpu, regs->rcx);
8823         kvm_rdx_write(vcpu, regs->rdx);
8824         kvm_rsi_write(vcpu, regs->rsi);
8825         kvm_rdi_write(vcpu, regs->rdi);
8826         kvm_rsp_write(vcpu, regs->rsp);
8827         kvm_rbp_write(vcpu, regs->rbp);
8828 #ifdef CONFIG_X86_64
8829         kvm_r8_write(vcpu, regs->r8);
8830         kvm_r9_write(vcpu, regs->r9);
8831         kvm_r10_write(vcpu, regs->r10);
8832         kvm_r11_write(vcpu, regs->r11);
8833         kvm_r12_write(vcpu, regs->r12);
8834         kvm_r13_write(vcpu, regs->r13);
8835         kvm_r14_write(vcpu, regs->r14);
8836         kvm_r15_write(vcpu, regs->r15);
8837 #endif
8838
8839         kvm_rip_write(vcpu, regs->rip);
8840         kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8841
8842         vcpu->arch.exception.pending = false;
8843
8844         kvm_make_request(KVM_REQ_EVENT, vcpu);
8845 }
8846
8847 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8848 {
8849         vcpu_load(vcpu);
8850         __set_regs(vcpu, regs);
8851         vcpu_put(vcpu);
8852         return 0;
8853 }
8854
8855 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8856 {
8857         struct kvm_segment cs;
8858
8859         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8860         *db = cs.db;
8861         *l = cs.l;
8862 }
8863 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8864
8865 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8866 {
8867         struct desc_ptr dt;
8868
8869         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8870         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8871         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8872         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8873         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8874         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8875
8876         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8877         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8878
8879         kvm_x86_ops.get_idt(vcpu, &dt);
8880         sregs->idt.limit = dt.size;
8881         sregs->idt.base = dt.address;
8882         kvm_x86_ops.get_gdt(vcpu, &dt);
8883         sregs->gdt.limit = dt.size;
8884         sregs->gdt.base = dt.address;
8885
8886         sregs->cr0 = kvm_read_cr0(vcpu);
8887         sregs->cr2 = vcpu->arch.cr2;
8888         sregs->cr3 = kvm_read_cr3(vcpu);
8889         sregs->cr4 = kvm_read_cr4(vcpu);
8890         sregs->cr8 = kvm_get_cr8(vcpu);
8891         sregs->efer = vcpu->arch.efer;
8892         sregs->apic_base = kvm_get_apic_base(vcpu);
8893
8894         memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8895
8896         if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8897                 set_bit(vcpu->arch.interrupt.nr,
8898                         (unsigned long *)sregs->interrupt_bitmap);
8899 }
8900
8901 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8902                                   struct kvm_sregs *sregs)
8903 {
8904         vcpu_load(vcpu);
8905         __get_sregs(vcpu, sregs);
8906         vcpu_put(vcpu);
8907         return 0;
8908 }
8909
8910 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8911                                     struct kvm_mp_state *mp_state)
8912 {
8913         vcpu_load(vcpu);
8914         if (kvm_mpx_supported())
8915                 kvm_load_guest_fpu(vcpu);
8916
8917         kvm_apic_accept_events(vcpu);
8918         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8919                                         vcpu->arch.pv.pv_unhalted)
8920                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8921         else
8922                 mp_state->mp_state = vcpu->arch.mp_state;
8923
8924         if (kvm_mpx_supported())
8925                 kvm_put_guest_fpu(vcpu);
8926         vcpu_put(vcpu);
8927         return 0;
8928 }
8929
8930 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8931                                     struct kvm_mp_state *mp_state)
8932 {
8933         int ret = -EINVAL;
8934
8935         vcpu_load(vcpu);
8936
8937         if (!lapic_in_kernel(vcpu) &&
8938             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8939                 goto out;
8940
8941         /*
8942          * KVM_MP_STATE_INIT_RECEIVED means the processor is in
8943          * INIT state; latched init should be reported using
8944          * KVM_SET_VCPU_EVENTS, so reject it here.
8945          */
8946         if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
8947             (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8948              mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8949                 goto out;
8950
8951         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8952                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8953                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8954         } else
8955                 vcpu->arch.mp_state = mp_state->mp_state;
8956         kvm_make_request(KVM_REQ_EVENT, vcpu);
8957
8958         ret = 0;
8959 out:
8960         vcpu_put(vcpu);
8961         return ret;
8962 }
8963
8964 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8965                     int reason, bool has_error_code, u32 error_code)
8966 {
8967         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8968         int ret;
8969
8970         init_emulate_ctxt(vcpu);
8971
8972         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8973                                    has_error_code, error_code);
8974         if (ret) {
8975                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8976                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8977                 vcpu->run->internal.ndata = 0;
8978                 return 0;
8979         }
8980
8981         kvm_rip_write(vcpu, ctxt->eip);
8982         kvm_set_rflags(vcpu, ctxt->eflags);
8983         return 1;
8984 }
8985 EXPORT_SYMBOL_GPL(kvm_task_switch);
8986
8987 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8988 {
8989         if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
8990                 /*
8991                  * When EFER.LME and CR0.PG are set, the processor is in
8992                  * 64-bit mode (though maybe in a 32-bit code segment).
8993                  * CR4.PAE and EFER.LMA must be set.
8994                  */
8995                 if (!(sregs->cr4 & X86_CR4_PAE)
8996                     || !(sregs->efer & EFER_LMA))
8997                         return -EINVAL;
8998         } else {
8999                 /*
9000                  * Not in 64-bit mode: EFER.LMA is clear and the code
9001                  * segment cannot be 64-bit.
9002                  */
9003                 if (sregs->efer & EFER_LMA || sregs->cs.l)
9004                         return -EINVAL;
9005         }
9006
9007         return kvm_valid_cr4(vcpu, sregs->cr4);
9008 }
9009
9010 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9011 {
9012         struct msr_data apic_base_msr;
9013         int mmu_reset_needed = 0;
9014         int cpuid_update_needed = 0;
9015         int pending_vec, max_bits, idx;
9016         struct desc_ptr dt;
9017         int ret = -EINVAL;
9018
9019         if (kvm_valid_sregs(vcpu, sregs))
9020                 goto out;
9021
9022         apic_base_msr.data = sregs->apic_base;
9023         apic_base_msr.host_initiated = true;
9024         if (kvm_set_apic_base(vcpu, &apic_base_msr))
9025                 goto out;
9026
9027         dt.size = sregs->idt.limit;
9028         dt.address = sregs->idt.base;
9029         kvm_x86_ops.set_idt(vcpu, &dt);
9030         dt.size = sregs->gdt.limit;
9031         dt.address = sregs->gdt.base;
9032         kvm_x86_ops.set_gdt(vcpu, &dt);
9033
9034         vcpu->arch.cr2 = sregs->cr2;
9035         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9036         vcpu->arch.cr3 = sregs->cr3;
9037         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9038
9039         kvm_set_cr8(vcpu, sregs->cr8);
9040
9041         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9042         kvm_x86_ops.set_efer(vcpu, sregs->efer);
9043
9044         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9045         kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9046         vcpu->arch.cr0 = sregs->cr0;
9047
9048         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9049         cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9050                                 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9051         kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9052         if (cpuid_update_needed)
9053                 kvm_update_cpuid(vcpu);
9054
9055         idx = srcu_read_lock(&vcpu->kvm->srcu);
9056         if (is_pae_paging(vcpu)) {
9057                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9058                 mmu_reset_needed = 1;
9059         }
9060         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9061
9062         if (mmu_reset_needed)
9063                 kvm_mmu_reset_context(vcpu);
9064
9065         max_bits = KVM_NR_INTERRUPTS;
9066         pending_vec = find_first_bit(
9067                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9068         if (pending_vec < max_bits) {
9069                 kvm_queue_interrupt(vcpu, pending_vec, false);
9070                 pr_debug("Set back pending irq %d\n", pending_vec);
9071         }
9072
9073         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9074         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9075         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9076         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9077         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9078         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9079
9080         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9081         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9082
9083         update_cr8_intercept(vcpu);
9084
9085         /* Older userspace won't unhalt the vcpu on reset. */
9086         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9087             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9088             !is_protmode(vcpu))
9089                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9090
9091         kvm_make_request(KVM_REQ_EVENT, vcpu);
9092
9093         ret = 0;
9094 out:
9095         return ret;
9096 }
9097
9098 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9099                                   struct kvm_sregs *sregs)
9100 {
9101         int ret;
9102
9103         vcpu_load(vcpu);
9104         ret = __set_sregs(vcpu, sregs);
9105         vcpu_put(vcpu);
9106         return ret;
9107 }
9108
9109 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9110                                         struct kvm_guest_debug *dbg)
9111 {
9112         unsigned long rflags;
9113         int i, r;
9114
9115         vcpu_load(vcpu);
9116
9117         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9118                 r = -EBUSY;
9119                 if (vcpu->arch.exception.pending)
9120                         goto out;
9121                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9122                         kvm_queue_exception(vcpu, DB_VECTOR);
9123                 else
9124                         kvm_queue_exception(vcpu, BP_VECTOR);
9125         }
9126
9127         /*
9128          * Read rflags as long as potentially injected trace flags are still
9129          * filtered out.
9130          */
9131         rflags = kvm_get_rflags(vcpu);
9132
9133         vcpu->guest_debug = dbg->control;
9134         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9135                 vcpu->guest_debug = 0;
9136
9137         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9138                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9139                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9140                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9141         } else {
9142                 for (i = 0; i < KVM_NR_DB_REGS; i++)
9143                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9144         }
9145         kvm_update_dr7(vcpu);
9146
9147         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9148                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9149                         get_segment_base(vcpu, VCPU_SREG_CS);
9150
9151         /*
9152          * Trigger an rflags update that will inject or remove the trace
9153          * flags.
9154          */
9155         kvm_set_rflags(vcpu, rflags);
9156
9157         kvm_x86_ops.update_bp_intercept(vcpu);
9158
9159         r = 0;
9160
9161 out:
9162         vcpu_put(vcpu);
9163         return r;
9164 }
9165
9166 /*
9167  * Translate a guest virtual address to a guest physical address.
9168  */
9169 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9170                                     struct kvm_translation *tr)
9171 {
9172         unsigned long vaddr = tr->linear_address;
9173         gpa_t gpa;
9174         int idx;
9175
9176         vcpu_load(vcpu);
9177
9178         idx = srcu_read_lock(&vcpu->kvm->srcu);
9179         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9180         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9181         tr->physical_address = gpa;
9182         tr->valid = gpa != UNMAPPED_GVA;
9183         tr->writeable = 1;
9184         tr->usermode = 0;
9185
9186         vcpu_put(vcpu);
9187         return 0;
9188 }
9189
9190 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9191 {
9192         struct fxregs_state *fxsave;
9193
9194         vcpu_load(vcpu);
9195
9196         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9197         memcpy(fpu->fpr, fxsave->st_space, 128);
9198         fpu->fcw = fxsave->cwd;
9199         fpu->fsw = fxsave->swd;
9200         fpu->ftwx = fxsave->twd;
9201         fpu->last_opcode = fxsave->fop;
9202         fpu->last_ip = fxsave->rip;
9203         fpu->last_dp = fxsave->rdp;
9204         memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9205
9206         vcpu_put(vcpu);
9207         return 0;
9208 }
9209
9210 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9211 {
9212         struct fxregs_state *fxsave;
9213
9214         vcpu_load(vcpu);
9215
9216         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9217
9218         memcpy(fxsave->st_space, fpu->fpr, 128);
9219         fxsave->cwd = fpu->fcw;
9220         fxsave->swd = fpu->fsw;
9221         fxsave->twd = fpu->ftwx;
9222         fxsave->fop = fpu->last_opcode;
9223         fxsave->rip = fpu->last_ip;
9224         fxsave->rdp = fpu->last_dp;
9225         memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9226
9227         vcpu_put(vcpu);
9228         return 0;
9229 }
9230
9231 static void store_regs(struct kvm_vcpu *vcpu)
9232 {
9233         BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9234
9235         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9236                 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9237
9238         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9239                 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9240
9241         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9242                 kvm_vcpu_ioctl_x86_get_vcpu_events(
9243                                 vcpu, &vcpu->run->s.regs.events);
9244 }
9245
9246 static int sync_regs(struct kvm_vcpu *vcpu)
9247 {
9248         if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9249                 return -EINVAL;
9250
9251         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9252                 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9253                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9254         }
9255         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9256                 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9257                         return -EINVAL;
9258                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9259         }
9260         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9261                 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9262                                 vcpu, &vcpu->run->s.regs.events))
9263                         return -EINVAL;
9264                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9265         }
9266
9267         return 0;
9268 }
9269
9270 static void fx_init(struct kvm_vcpu *vcpu)
9271 {
9272         fpstate_init(&vcpu->arch.guest_fpu->state);
9273         if (boot_cpu_has(X86_FEATURE_XSAVES))
9274                 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9275                         host_xcr0 | XSTATE_COMPACTION_ENABLED;
9276
9277         /*
9278          * Ensure guest xcr0 is valid for loading
9279          */
9280         vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9281
9282         vcpu->arch.cr0 |= X86_CR0_ET;
9283 }
9284
9285 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9286 {
9287         if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9288                 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9289                              "guest TSC will not be reliable\n");
9290
9291         return 0;
9292 }
9293
9294 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9295 {
9296         struct page *page;
9297         int r;
9298
9299         if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9300                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9301         else
9302                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9303
9304         kvm_set_tsc_khz(vcpu, max_tsc_khz);
9305
9306         r = kvm_mmu_create(vcpu);
9307         if (r < 0)
9308                 return r;
9309
9310         if (irqchip_in_kernel(vcpu->kvm)) {
9311                 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9312                 if (r < 0)
9313                         goto fail_mmu_destroy;
9314                 if (kvm_apicv_activated(vcpu->kvm))
9315                         vcpu->arch.apicv_active = true;
9316         } else
9317                 static_key_slow_inc(&kvm_no_apic_vcpu);
9318
9319         r = -ENOMEM;
9320
9321         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9322         if (!page)
9323                 goto fail_free_lapic;
9324         vcpu->arch.pio_data = page_address(page);
9325
9326         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9327                                        GFP_KERNEL_ACCOUNT);
9328         if (!vcpu->arch.mce_banks)
9329                 goto fail_free_pio_data;
9330         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9331
9332         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9333                                 GFP_KERNEL_ACCOUNT))
9334                 goto fail_free_mce_banks;
9335
9336         if (!alloc_emulate_ctxt(vcpu))
9337                 goto free_wbinvd_dirty_mask;
9338
9339         vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9340                                                 GFP_KERNEL_ACCOUNT);
9341         if (!vcpu->arch.user_fpu) {
9342                 pr_err("kvm: failed to allocate userspace's fpu\n");
9343                 goto free_emulate_ctxt;
9344         }
9345
9346         vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9347                                                  GFP_KERNEL_ACCOUNT);
9348         if (!vcpu->arch.guest_fpu) {
9349                 pr_err("kvm: failed to allocate vcpu's fpu\n");
9350                 goto free_user_fpu;
9351         }
9352         fx_init(vcpu);
9353
9354         vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9355
9356         vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9357
9358         vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9359
9360         kvm_async_pf_hash_reset(vcpu);
9361         kvm_pmu_init(vcpu);
9362
9363         vcpu->arch.pending_external_vector = -1;
9364         vcpu->arch.preempted_in_kernel = false;
9365
9366         kvm_hv_vcpu_init(vcpu);
9367
9368         r = kvm_x86_ops.vcpu_create(vcpu);
9369         if (r)
9370                 goto free_guest_fpu;
9371
9372         vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9373         vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9374         kvm_vcpu_mtrr_init(vcpu);
9375         vcpu_load(vcpu);
9376         kvm_vcpu_reset(vcpu, false);
9377         kvm_init_mmu(vcpu, false);
9378         vcpu_put(vcpu);
9379         return 0;
9380
9381 free_guest_fpu:
9382         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9383 free_user_fpu:
9384         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9385 free_emulate_ctxt:
9386         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9387 free_wbinvd_dirty_mask:
9388         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9389 fail_free_mce_banks:
9390         kfree(vcpu->arch.mce_banks);
9391 fail_free_pio_data:
9392         free_page((unsigned long)vcpu->arch.pio_data);
9393 fail_free_lapic:
9394         kvm_free_lapic(vcpu);
9395 fail_mmu_destroy:
9396         kvm_mmu_destroy(vcpu);
9397         return r;
9398 }
9399
9400 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9401 {
9402         struct msr_data msr;
9403         struct kvm *kvm = vcpu->kvm;
9404
9405         kvm_hv_vcpu_postcreate(vcpu);
9406
9407         if (mutex_lock_killable(&vcpu->mutex))
9408                 return;
9409         vcpu_load(vcpu);
9410         msr.data = 0x0;
9411         msr.index = MSR_IA32_TSC;
9412         msr.host_initiated = true;
9413         kvm_write_tsc(vcpu, &msr);
9414         vcpu_put(vcpu);
9415
9416         /* poll control enabled by default */
9417         vcpu->arch.msr_kvm_poll_control = 1;
9418
9419         mutex_unlock(&vcpu->mutex);
9420
9421         if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9422                 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9423                                                 KVMCLOCK_SYNC_PERIOD);
9424 }
9425
9426 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9427 {
9428         struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9429         int idx;
9430
9431         kvm_release_pfn(cache->pfn, cache->dirty, cache);
9432
9433         kvmclock_reset(vcpu);
9434
9435         kvm_x86_ops.vcpu_free(vcpu);
9436
9437         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9438         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9439         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9440         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9441
9442         kvm_hv_vcpu_uninit(vcpu);
9443         kvm_pmu_destroy(vcpu);
9444         kfree(vcpu->arch.mce_banks);
9445         kvm_free_lapic(vcpu);
9446         idx = srcu_read_lock(&vcpu->kvm->srcu);
9447         kvm_mmu_destroy(vcpu);
9448         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9449         free_page((unsigned long)vcpu->arch.pio_data);
9450         if (!lapic_in_kernel(vcpu))
9451                 static_key_slow_dec(&kvm_no_apic_vcpu);
9452 }
9453
9454 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9455 {
9456         kvm_lapic_reset(vcpu, init_event);
9457
9458         vcpu->arch.hflags = 0;
9459
9460         vcpu->arch.smi_pending = 0;
9461         vcpu->arch.smi_count = 0;
9462         atomic_set(&vcpu->arch.nmi_queued, 0);
9463         vcpu->arch.nmi_pending = 0;
9464         vcpu->arch.nmi_injected = false;
9465         kvm_clear_interrupt_queue(vcpu);
9466         kvm_clear_exception_queue(vcpu);
9467
9468         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9469         kvm_update_dr0123(vcpu);
9470         vcpu->arch.dr6 = DR6_INIT;
9471         vcpu->arch.dr7 = DR7_FIXED_1;
9472         kvm_update_dr7(vcpu);
9473
9474         vcpu->arch.cr2 = 0;
9475
9476         kvm_make_request(KVM_REQ_EVENT, vcpu);
9477         vcpu->arch.apf.msr_val = 0;
9478         vcpu->arch.st.msr_val = 0;
9479
9480         kvmclock_reset(vcpu);
9481
9482         kvm_clear_async_pf_completion_queue(vcpu);
9483         kvm_async_pf_hash_reset(vcpu);
9484         vcpu->arch.apf.halted = false;
9485
9486         if (kvm_mpx_supported()) {
9487                 void *mpx_state_buffer;
9488
9489                 /*
9490                  * To avoid have the INIT path from kvm_apic_has_events() that be
9491                  * called with loaded FPU and does not let userspace fix the state.
9492                  */
9493                 if (init_event)
9494                         kvm_put_guest_fpu(vcpu);
9495                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9496                                         XFEATURE_BNDREGS);
9497                 if (mpx_state_buffer)
9498                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9499                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9500                                         XFEATURE_BNDCSR);
9501                 if (mpx_state_buffer)
9502                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9503                 if (init_event)
9504                         kvm_load_guest_fpu(vcpu);
9505         }
9506
9507         if (!init_event) {
9508                 kvm_pmu_reset(vcpu);
9509                 vcpu->arch.smbase = 0x30000;
9510
9511                 vcpu->arch.msr_misc_features_enables = 0;
9512
9513                 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9514         }
9515
9516         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9517         vcpu->arch.regs_avail = ~0;
9518         vcpu->arch.regs_dirty = ~0;
9519
9520         vcpu->arch.ia32_xss = 0;
9521
9522         kvm_x86_ops.vcpu_reset(vcpu, init_event);
9523 }
9524
9525 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9526 {
9527         struct kvm_segment cs;
9528
9529         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9530         cs.selector = vector << 8;
9531         cs.base = vector << 12;
9532         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9533         kvm_rip_write(vcpu, 0);
9534 }
9535
9536 int kvm_arch_hardware_enable(void)
9537 {
9538         struct kvm *kvm;
9539         struct kvm_vcpu *vcpu;
9540         int i;
9541         int ret;
9542         u64 local_tsc;
9543         u64 max_tsc = 0;
9544         bool stable, backwards_tsc = false;
9545
9546         kvm_shared_msr_cpu_online();
9547         ret = kvm_x86_ops.hardware_enable();
9548         if (ret != 0)
9549                 return ret;
9550
9551         local_tsc = rdtsc();
9552         stable = !kvm_check_tsc_unstable();
9553         list_for_each_entry(kvm, &vm_list, vm_list) {
9554                 kvm_for_each_vcpu(i, vcpu, kvm) {
9555                         if (!stable && vcpu->cpu == smp_processor_id())
9556                                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9557                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9558                                 backwards_tsc = true;
9559                                 if (vcpu->arch.last_host_tsc > max_tsc)
9560                                         max_tsc = vcpu->arch.last_host_tsc;
9561                         }
9562                 }
9563         }
9564
9565         /*
9566          * Sometimes, even reliable TSCs go backwards.  This happens on
9567          * platforms that reset TSC during suspend or hibernate actions, but
9568          * maintain synchronization.  We must compensate.  Fortunately, we can
9569          * detect that condition here, which happens early in CPU bringup,
9570          * before any KVM threads can be running.  Unfortunately, we can't
9571          * bring the TSCs fully up to date with real time, as we aren't yet far
9572          * enough into CPU bringup that we know how much real time has actually
9573          * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9574          * variables that haven't been updated yet.
9575          *
9576          * So we simply find the maximum observed TSC above, then record the
9577          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
9578          * the adjustment will be applied.  Note that we accumulate
9579          * adjustments, in case multiple suspend cycles happen before some VCPU
9580          * gets a chance to run again.  In the event that no KVM threads get a
9581          * chance to run, we will miss the entire elapsed period, as we'll have
9582          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9583          * loose cycle time.  This isn't too big a deal, since the loss will be
9584          * uniform across all VCPUs (not to mention the scenario is extremely
9585          * unlikely). It is possible that a second hibernate recovery happens
9586          * much faster than a first, causing the observed TSC here to be
9587          * smaller; this would require additional padding adjustment, which is
9588          * why we set last_host_tsc to the local tsc observed here.
9589          *
9590          * N.B. - this code below runs only on platforms with reliable TSC,
9591          * as that is the only way backwards_tsc is set above.  Also note
9592          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9593          * have the same delta_cyc adjustment applied if backwards_tsc
9594          * is detected.  Note further, this adjustment is only done once,
9595          * as we reset last_host_tsc on all VCPUs to stop this from being
9596          * called multiple times (one for each physical CPU bringup).
9597          *
9598          * Platforms with unreliable TSCs don't have to deal with this, they
9599          * will be compensated by the logic in vcpu_load, which sets the TSC to
9600          * catchup mode.  This will catchup all VCPUs to real time, but cannot
9601          * guarantee that they stay in perfect synchronization.
9602          */
9603         if (backwards_tsc) {
9604                 u64 delta_cyc = max_tsc - local_tsc;
9605                 list_for_each_entry(kvm, &vm_list, vm_list) {
9606                         kvm->arch.backwards_tsc_observed = true;
9607                         kvm_for_each_vcpu(i, vcpu, kvm) {
9608                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9609                                 vcpu->arch.last_host_tsc = local_tsc;
9610                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9611                         }
9612
9613                         /*
9614                          * We have to disable TSC offset matching.. if you were
9615                          * booting a VM while issuing an S4 host suspend....
9616                          * you may have some problem.  Solving this issue is
9617                          * left as an exercise to the reader.
9618                          */
9619                         kvm->arch.last_tsc_nsec = 0;
9620                         kvm->arch.last_tsc_write = 0;
9621                 }
9622
9623         }
9624         return 0;
9625 }
9626
9627 void kvm_arch_hardware_disable(void)
9628 {
9629         kvm_x86_ops.hardware_disable();
9630         drop_user_return_notifiers();
9631 }
9632
9633 int kvm_arch_hardware_setup(void *opaque)
9634 {
9635         struct kvm_x86_init_ops *ops = opaque;
9636         int r;
9637
9638         rdmsrl_safe(MSR_EFER, &host_efer);
9639
9640         if (boot_cpu_has(X86_FEATURE_XSAVES))
9641                 rdmsrl(MSR_IA32_XSS, host_xss);
9642
9643         r = ops->hardware_setup();
9644         if (r != 0)
9645                 return r;
9646
9647         memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9648
9649         if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9650                 supported_xss = 0;
9651
9652 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9653         cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9654 #undef __kvm_cpu_cap_has
9655
9656         if (kvm_has_tsc_control) {
9657                 /*
9658                  * Make sure the user can only configure tsc_khz values that
9659                  * fit into a signed integer.
9660                  * A min value is not calculated because it will always
9661                  * be 1 on all machines.
9662                  */
9663                 u64 max = min(0x7fffffffULL,
9664                               __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9665                 kvm_max_guest_tsc_khz = max;
9666
9667                 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9668         }
9669
9670         kvm_init_msr_list();
9671         return 0;
9672 }
9673
9674 void kvm_arch_hardware_unsetup(void)
9675 {
9676         kvm_x86_ops.hardware_unsetup();
9677 }
9678
9679 int kvm_arch_check_processor_compat(void *opaque)
9680 {
9681         struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9682         struct kvm_x86_init_ops *ops = opaque;
9683
9684         WARN_ON(!irqs_disabled());
9685
9686         if (__cr4_reserved_bits(cpu_has, c) !=
9687             __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9688                 return -EIO;
9689
9690         return ops->check_processor_compatibility();
9691 }
9692
9693 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9694 {
9695         return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9696 }
9697 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9698
9699 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9700 {
9701         return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9702 }
9703
9704 struct static_key kvm_no_apic_vcpu __read_mostly;
9705 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9706
9707 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9708 {
9709         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9710
9711         vcpu->arch.l1tf_flush_l1d = true;
9712         if (pmu->version && unlikely(pmu->event_count)) {
9713                 pmu->need_cleanup = true;
9714                 kvm_make_request(KVM_REQ_PMU, vcpu);
9715         }
9716         kvm_x86_ops.sched_in(vcpu, cpu);
9717 }
9718
9719 void kvm_arch_free_vm(struct kvm *kvm)
9720 {
9721         kfree(kvm->arch.hyperv.hv_pa_pg);
9722         vfree(kvm);
9723 }
9724
9725
9726 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9727 {
9728         if (type)
9729                 return -EINVAL;
9730
9731         INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9732         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9733         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9734         INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9735         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9736         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9737
9738         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9739         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9740         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9741         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9742                 &kvm->arch.irq_sources_bitmap);
9743
9744         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9745         mutex_init(&kvm->arch.apic_map_lock);
9746         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9747
9748         kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9749         pvclock_update_vm_gtod_copy(kvm);
9750
9751         kvm->arch.guest_can_read_msr_platform_info = true;
9752
9753         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9754         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9755
9756         kvm_hv_init_vm(kvm);
9757         kvm_page_track_init(kvm);
9758         kvm_mmu_init_vm(kvm);
9759
9760         return kvm_x86_ops.vm_init(kvm);
9761 }
9762
9763 int kvm_arch_post_init_vm(struct kvm *kvm)
9764 {
9765         return kvm_mmu_post_init_vm(kvm);
9766 }
9767
9768 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9769 {
9770         vcpu_load(vcpu);
9771         kvm_mmu_unload(vcpu);
9772         vcpu_put(vcpu);
9773 }
9774
9775 static void kvm_free_vcpus(struct kvm *kvm)
9776 {
9777         unsigned int i;
9778         struct kvm_vcpu *vcpu;
9779
9780         /*
9781          * Unpin any mmu pages first.
9782          */
9783         kvm_for_each_vcpu(i, vcpu, kvm) {
9784                 kvm_clear_async_pf_completion_queue(vcpu);
9785                 kvm_unload_vcpu_mmu(vcpu);
9786         }
9787         kvm_for_each_vcpu(i, vcpu, kvm)
9788                 kvm_vcpu_destroy(vcpu);
9789
9790         mutex_lock(&kvm->lock);
9791         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9792                 kvm->vcpus[i] = NULL;
9793
9794         atomic_set(&kvm->online_vcpus, 0);
9795         mutex_unlock(&kvm->lock);
9796 }
9797
9798 void kvm_arch_sync_events(struct kvm *kvm)
9799 {
9800         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9801         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9802         kvm_free_pit(kvm);
9803 }
9804
9805 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9806 {
9807         int i, r;
9808         unsigned long hva, uninitialized_var(old_npages);
9809         struct kvm_memslots *slots = kvm_memslots(kvm);
9810         struct kvm_memory_slot *slot;
9811
9812         /* Called with kvm->slots_lock held.  */
9813         if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9814                 return -EINVAL;
9815
9816         slot = id_to_memslot(slots, id);
9817         if (size) {
9818                 if (slot && slot->npages)
9819                         return -EEXIST;
9820
9821                 /*
9822                  * MAP_SHARED to prevent internal slot pages from being moved
9823                  * by fork()/COW.
9824                  */
9825                 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9826                               MAP_SHARED | MAP_ANONYMOUS, 0);
9827                 if (IS_ERR((void *)hva))
9828                         return PTR_ERR((void *)hva);
9829         } else {
9830                 if (!slot || !slot->npages)
9831                         return 0;
9832
9833                 /*
9834                  * Stuff a non-canonical value to catch use-after-delete.  This
9835                  * ends up being 0 on 32-bit KVM, but there's no better
9836                  * alternative.
9837                  */
9838                 hva = (unsigned long)(0xdeadull << 48);
9839                 old_npages = slot->npages;
9840         }
9841
9842         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9843                 struct kvm_userspace_memory_region m;
9844
9845                 m.slot = id | (i << 16);
9846                 m.flags = 0;
9847                 m.guest_phys_addr = gpa;
9848                 m.userspace_addr = hva;
9849                 m.memory_size = size;
9850                 r = __kvm_set_memory_region(kvm, &m);
9851                 if (r < 0)
9852                         return r;
9853         }
9854
9855         if (!size)
9856                 vm_munmap(hva, old_npages * PAGE_SIZE);
9857
9858         return 0;
9859 }
9860 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9861
9862 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9863 {
9864         kvm_mmu_pre_destroy_vm(kvm);
9865 }
9866
9867 void kvm_arch_destroy_vm(struct kvm *kvm)
9868 {
9869         if (current->mm == kvm->mm) {
9870                 /*
9871                  * Free memory regions allocated on behalf of userspace,
9872                  * unless the the memory map has changed due to process exit
9873                  * or fd copying.
9874                  */
9875                 mutex_lock(&kvm->slots_lock);
9876                 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
9877                                         0, 0);
9878                 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
9879                                         0, 0);
9880                 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9881                 mutex_unlock(&kvm->slots_lock);
9882         }
9883         if (kvm_x86_ops.vm_destroy)
9884                 kvm_x86_ops.vm_destroy(kvm);
9885         kvm_pic_destroy(kvm);
9886         kvm_ioapic_destroy(kvm);
9887         kvm_free_vcpus(kvm);
9888         kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9889         kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9890         kvm_mmu_uninit_vm(kvm);
9891         kvm_page_track_cleanup(kvm);
9892         kvm_hv_destroy_vm(kvm);
9893 }
9894
9895 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
9896 {
9897         int i;
9898
9899         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9900                 kvfree(slot->arch.rmap[i]);
9901                 slot->arch.rmap[i] = NULL;
9902
9903                 if (i == 0)
9904                         continue;
9905
9906                 kvfree(slot->arch.lpage_info[i - 1]);
9907                 slot->arch.lpage_info[i - 1] = NULL;
9908         }
9909
9910         kvm_page_track_free_memslot(slot);
9911 }
9912
9913 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
9914                                       unsigned long npages)
9915 {
9916         int i;
9917
9918         /*
9919          * Clear out the previous array pointers for the KVM_MR_MOVE case.  The
9920          * old arrays will be freed by __kvm_set_memory_region() if installing
9921          * the new memslot is successful.
9922          */
9923         memset(&slot->arch, 0, sizeof(slot->arch));
9924
9925         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9926                 struct kvm_lpage_info *linfo;
9927                 unsigned long ugfn;
9928                 int lpages;
9929                 int level = i + 1;
9930
9931                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9932                                       slot->base_gfn, level) + 1;
9933
9934                 slot->arch.rmap[i] =
9935                         kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9936                                  GFP_KERNEL_ACCOUNT);
9937                 if (!slot->arch.rmap[i])
9938                         goto out_free;
9939                 if (i == 0)
9940                         continue;
9941
9942                 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9943                 if (!linfo)
9944                         goto out_free;
9945
9946                 slot->arch.lpage_info[i - 1] = linfo;
9947
9948                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9949                         linfo[0].disallow_lpage = 1;
9950                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9951                         linfo[lpages - 1].disallow_lpage = 1;
9952                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9953                 /*
9954                  * If the gfn and userspace address are not aligned wrt each
9955                  * other, disable large page support for this slot.
9956                  */
9957                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
9958                         unsigned long j;
9959
9960                         for (j = 0; j < lpages; ++j)
9961                                 linfo[j].disallow_lpage = 1;
9962                 }
9963         }
9964
9965         if (kvm_page_track_create_memslot(slot, npages))
9966                 goto out_free;
9967
9968         return 0;
9969
9970 out_free:
9971         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9972                 kvfree(slot->arch.rmap[i]);
9973                 slot->arch.rmap[i] = NULL;
9974                 if (i == 0)
9975                         continue;
9976
9977                 kvfree(slot->arch.lpage_info[i - 1]);
9978                 slot->arch.lpage_info[i - 1] = NULL;
9979         }
9980         return -ENOMEM;
9981 }
9982
9983 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
9984 {
9985         struct kvm_vcpu *vcpu;
9986         int i;
9987
9988         /*
9989          * memslots->generation has been incremented.
9990          * mmio generation may have reached its maximum value.
9991          */
9992         kvm_mmu_invalidate_mmio_sptes(kvm, gen);
9993
9994         /* Force re-initialization of steal_time cache */
9995         kvm_for_each_vcpu(i, vcpu, kvm)
9996                 kvm_vcpu_kick(vcpu);
9997 }
9998
9999 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10000                                 struct kvm_memory_slot *memslot,
10001                                 const struct kvm_userspace_memory_region *mem,
10002                                 enum kvm_mr_change change)
10003 {
10004         if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10005                 return kvm_alloc_memslot_metadata(memslot,
10006                                                   mem->memory_size >> PAGE_SHIFT);
10007         return 0;
10008 }
10009
10010 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10011                                      struct kvm_memory_slot *new)
10012 {
10013         /* Still write protect RO slot */
10014         if (new->flags & KVM_MEM_READONLY) {
10015                 kvm_mmu_slot_remove_write_access(kvm, new, PT_PAGE_TABLE_LEVEL);
10016                 return;
10017         }
10018
10019         /*
10020          * Call kvm_x86_ops dirty logging hooks when they are valid.
10021          *
10022          * kvm_x86_ops.slot_disable_log_dirty is called when:
10023          *
10024          *  - KVM_MR_CREATE with dirty logging is disabled
10025          *  - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
10026          *
10027          * The reason is, in case of PML, we need to set D-bit for any slots
10028          * with dirty logging disabled in order to eliminate unnecessary GPA
10029          * logging in PML buffer (and potential PML buffer full VMEXIT). This
10030          * guarantees leaving PML enabled during guest's lifetime won't have
10031          * any additional overhead from PML when guest is running with dirty
10032          * logging disabled for memory slots.
10033          *
10034          * kvm_x86_ops.slot_enable_log_dirty is called when switching new slot
10035          * to dirty logging mode.
10036          *
10037          * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
10038          *
10039          * In case of write protect:
10040          *
10041          * Write protect all pages for dirty logging.
10042          *
10043          * All the sptes including the large sptes which point to this
10044          * slot are set to readonly. We can not create any new large
10045          * spte on this slot until the end of the logging.
10046          *
10047          * See the comments in fast_page_fault().
10048          */
10049         if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10050                 if (kvm_x86_ops.slot_enable_log_dirty) {
10051                         kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10052                 } else {
10053                         int level =
10054                                 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10055                                 PT_DIRECTORY_LEVEL : PT_PAGE_TABLE_LEVEL;
10056
10057                         /*
10058                          * If we're with initial-all-set, we don't need
10059                          * to write protect any small page because
10060                          * they're reported as dirty already.  However
10061                          * we still need to write-protect huge pages
10062                          * so that the page split can happen lazily on
10063                          * the first write to the huge page.
10064                          */
10065                         kvm_mmu_slot_remove_write_access(kvm, new, level);
10066                 }
10067         } else {
10068                 if (kvm_x86_ops.slot_disable_log_dirty)
10069                         kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10070         }
10071 }
10072
10073 void kvm_arch_commit_memory_region(struct kvm *kvm,
10074                                 const struct kvm_userspace_memory_region *mem,
10075                                 struct kvm_memory_slot *old,
10076                                 const struct kvm_memory_slot *new,
10077                                 enum kvm_mr_change change)
10078 {
10079         if (!kvm->arch.n_requested_mmu_pages)
10080                 kvm_mmu_change_mmu_pages(kvm,
10081                                 kvm_mmu_calculate_default_mmu_pages(kvm));
10082
10083         /*
10084          * Dirty logging tracks sptes in 4k granularity, meaning that large
10085          * sptes have to be split.  If live migration is successful, the guest
10086          * in the source machine will be destroyed and large sptes will be
10087          * created in the destination. However, if the guest continues to run
10088          * in the source machine (for example if live migration fails), small
10089          * sptes will remain around and cause bad performance.
10090          *
10091          * Scan sptes if dirty logging has been stopped, dropping those
10092          * which can be collapsed into a single large-page spte.  Later
10093          * page faults will create the large-page sptes.
10094          *
10095          * There is no need to do this in any of the following cases:
10096          * CREATE:      No dirty mappings will already exist.
10097          * MOVE/DELETE: The old mappings will already have been cleaned up by
10098          *              kvm_arch_flush_shadow_memslot()
10099          */
10100         if (change == KVM_MR_FLAGS_ONLY &&
10101                 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10102                 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10103                 kvm_mmu_zap_collapsible_sptes(kvm, new);
10104
10105         /*
10106          * Set up write protection and/or dirty logging for the new slot.
10107          *
10108          * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
10109          * been zapped so no dirty logging staff is needed for old slot. For
10110          * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
10111          * new and it's also covered when dealing with the new slot.
10112          *
10113          * FIXME: const-ify all uses of struct kvm_memory_slot.
10114          */
10115         if (change != KVM_MR_DELETE)
10116                 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
10117
10118         /* Free the arrays associated with the old memslot. */
10119         if (change == KVM_MR_MOVE)
10120                 kvm_arch_free_memslot(kvm, old);
10121 }
10122
10123 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10124 {
10125         kvm_mmu_zap_all(kvm);
10126 }
10127
10128 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10129                                    struct kvm_memory_slot *slot)
10130 {
10131         kvm_page_track_flush_slot(kvm, slot);
10132 }
10133
10134 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10135 {
10136         return (is_guest_mode(vcpu) &&
10137                         kvm_x86_ops.guest_apic_has_interrupt &&
10138                         kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10139 }
10140
10141 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10142 {
10143         if (!list_empty_careful(&vcpu->async_pf.done))
10144                 return true;
10145
10146         if (kvm_apic_has_events(vcpu))
10147                 return true;
10148
10149         if (vcpu->arch.pv.pv_unhalted)
10150                 return true;
10151
10152         if (vcpu->arch.exception.pending)
10153                 return true;
10154
10155         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10156             (vcpu->arch.nmi_pending &&
10157              kvm_x86_ops.nmi_allowed(vcpu)))
10158                 return true;
10159
10160         if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10161             (vcpu->arch.smi_pending && !is_smm(vcpu)))
10162                 return true;
10163
10164         if (kvm_arch_interrupt_allowed(vcpu) &&
10165             (kvm_cpu_has_interrupt(vcpu) ||
10166             kvm_guest_apic_has_interrupt(vcpu)))
10167                 return true;
10168
10169         if (kvm_hv_has_stimer_pending(vcpu))
10170                 return true;
10171
10172         return false;
10173 }
10174
10175 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10176 {
10177         return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10178 }
10179
10180 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10181 {
10182         if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10183                 return true;
10184
10185         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10186                 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10187                  kvm_test_request(KVM_REQ_EVENT, vcpu))
10188                 return true;
10189
10190         if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10191                 return true;
10192
10193         return false;
10194 }
10195
10196 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10197 {
10198         return vcpu->arch.preempted_in_kernel;
10199 }
10200
10201 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10202 {
10203         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10204 }
10205
10206 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10207 {
10208         return kvm_x86_ops.interrupt_allowed(vcpu);
10209 }
10210
10211 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10212 {
10213         if (is_64_bit_mode(vcpu))
10214                 return kvm_rip_read(vcpu);
10215         return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10216                      kvm_rip_read(vcpu));
10217 }
10218 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10219
10220 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10221 {
10222         return kvm_get_linear_rip(vcpu) == linear_rip;
10223 }
10224 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10225
10226 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10227 {
10228         unsigned long rflags;
10229
10230         rflags = kvm_x86_ops.get_rflags(vcpu);
10231         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10232                 rflags &= ~X86_EFLAGS_TF;
10233         return rflags;
10234 }
10235 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10236
10237 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10238 {
10239         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10240             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10241                 rflags |= X86_EFLAGS_TF;
10242         kvm_x86_ops.set_rflags(vcpu, rflags);
10243 }
10244
10245 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10246 {
10247         __kvm_set_rflags(vcpu, rflags);
10248         kvm_make_request(KVM_REQ_EVENT, vcpu);
10249 }
10250 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10251
10252 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10253 {
10254         int r;
10255
10256         if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10257               work->wakeup_all)
10258                 return;
10259
10260         r = kvm_mmu_reload(vcpu);
10261         if (unlikely(r))
10262                 return;
10263
10264         if (!vcpu->arch.mmu->direct_map &&
10265               work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10266                 return;
10267
10268         kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10269 }
10270
10271 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10272 {
10273         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10274 }
10275
10276 static inline u32 kvm_async_pf_next_probe(u32 key)
10277 {
10278         return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
10279 }
10280
10281 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10282 {
10283         u32 key = kvm_async_pf_hash_fn(gfn);
10284
10285         while (vcpu->arch.apf.gfns[key] != ~0)
10286                 key = kvm_async_pf_next_probe(key);
10287
10288         vcpu->arch.apf.gfns[key] = gfn;
10289 }
10290
10291 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10292 {
10293         int i;
10294         u32 key = kvm_async_pf_hash_fn(gfn);
10295
10296         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
10297                      (vcpu->arch.apf.gfns[key] != gfn &&
10298                       vcpu->arch.apf.gfns[key] != ~0); i++)
10299                 key = kvm_async_pf_next_probe(key);
10300
10301         return key;
10302 }
10303
10304 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10305 {
10306         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10307 }
10308
10309 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10310 {
10311         u32 i, j, k;
10312
10313         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10314         while (true) {
10315                 vcpu->arch.apf.gfns[i] = ~0;
10316                 do {
10317                         j = kvm_async_pf_next_probe(j);
10318                         if (vcpu->arch.apf.gfns[j] == ~0)
10319                                 return;
10320                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10321                         /*
10322                          * k lies cyclically in ]i,j]
10323                          * |    i.k.j |
10324                          * |....j i.k.| or  |.k..j i...|
10325                          */
10326                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10327                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10328                 i = j;
10329         }
10330 }
10331
10332 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10333 {
10334
10335         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10336                                       sizeof(val));
10337 }
10338
10339 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10340 {
10341
10342         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10343                                       sizeof(u32));
10344 }
10345
10346 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10347 {
10348         if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10349                 return false;
10350
10351         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10352             (vcpu->arch.apf.send_user_only &&
10353              kvm_x86_ops.get_cpl(vcpu) == 0))
10354                 return false;
10355
10356         return true;
10357 }
10358
10359 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10360 {
10361         if (unlikely(!lapic_in_kernel(vcpu) ||
10362                      kvm_event_needs_reinjection(vcpu) ||
10363                      vcpu->arch.exception.pending))
10364                 return false;
10365
10366         if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10367                 return false;
10368
10369         /*
10370          * If interrupts are off we cannot even use an artificial
10371          * halt state.
10372          */
10373         return kvm_x86_ops.interrupt_allowed(vcpu);
10374 }
10375
10376 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10377                                      struct kvm_async_pf *work)
10378 {
10379         struct x86_exception fault;
10380
10381         trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10382         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10383
10384         if (kvm_can_deliver_async_pf(vcpu) &&
10385             !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10386                 fault.vector = PF_VECTOR;
10387                 fault.error_code_valid = true;
10388                 fault.error_code = 0;
10389                 fault.nested_page_fault = false;
10390                 fault.address = work->arch.token;
10391                 fault.async_page_fault = true;
10392                 kvm_inject_page_fault(vcpu, &fault);
10393         } else {
10394                 /*
10395                  * It is not possible to deliver a paravirtualized asynchronous
10396                  * page fault, but putting the guest in an artificial halt state
10397                  * can be beneficial nevertheless: if an interrupt arrives, we
10398                  * can deliver it timely and perhaps the guest will schedule
10399                  * another process.  When the instruction that triggered a page
10400                  * fault is retried, hopefully the page will be ready in the host.
10401                  */
10402                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10403         }
10404 }
10405
10406 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10407                                  struct kvm_async_pf *work)
10408 {
10409         struct x86_exception fault;
10410         u32 val;
10411
10412         if (work->wakeup_all)
10413                 work->arch.token = ~0; /* broadcast wakeup */
10414         else
10415                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10416         trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10417
10418         if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10419             !apf_get_user(vcpu, &val)) {
10420                 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10421                     vcpu->arch.exception.pending &&
10422                     vcpu->arch.exception.nr == PF_VECTOR &&
10423                     !apf_put_user(vcpu, 0)) {
10424                         vcpu->arch.exception.injected = false;
10425                         vcpu->arch.exception.pending = false;
10426                         vcpu->arch.exception.nr = 0;
10427                         vcpu->arch.exception.has_error_code = false;
10428                         vcpu->arch.exception.error_code = 0;
10429                         vcpu->arch.exception.has_payload = false;
10430                         vcpu->arch.exception.payload = 0;
10431                 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10432                         fault.vector = PF_VECTOR;
10433                         fault.error_code_valid = true;
10434                         fault.error_code = 0;
10435                         fault.nested_page_fault = false;
10436                         fault.address = work->arch.token;
10437                         fault.async_page_fault = true;
10438                         kvm_inject_page_fault(vcpu, &fault);
10439                 }
10440         }
10441         vcpu->arch.apf.halted = false;
10442         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10443 }
10444
10445 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10446 {
10447         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10448                 return true;
10449         else
10450                 return kvm_can_do_async_pf(vcpu);
10451 }
10452
10453 void kvm_arch_start_assignment(struct kvm *kvm)
10454 {
10455         atomic_inc(&kvm->arch.assigned_device_count);
10456 }
10457 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10458
10459 void kvm_arch_end_assignment(struct kvm *kvm)
10460 {
10461         atomic_dec(&kvm->arch.assigned_device_count);
10462 }
10463 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10464
10465 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10466 {
10467         return atomic_read(&kvm->arch.assigned_device_count);
10468 }
10469 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10470
10471 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10472 {
10473         atomic_inc(&kvm->arch.noncoherent_dma_count);
10474 }
10475 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10476
10477 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10478 {
10479         atomic_dec(&kvm->arch.noncoherent_dma_count);
10480 }
10481 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10482
10483 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10484 {
10485         return atomic_read(&kvm->arch.noncoherent_dma_count);
10486 }
10487 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10488
10489 bool kvm_arch_has_irq_bypass(void)
10490 {
10491         return true;
10492 }
10493
10494 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10495                                       struct irq_bypass_producer *prod)
10496 {
10497         struct kvm_kernel_irqfd *irqfd =
10498                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10499
10500         irqfd->producer = prod;
10501
10502         return kvm_x86_ops.update_pi_irte(irqfd->kvm,
10503                                            prod->irq, irqfd->gsi, 1);
10504 }
10505
10506 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10507                                       struct irq_bypass_producer *prod)
10508 {
10509         int ret;
10510         struct kvm_kernel_irqfd *irqfd =
10511                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10512
10513         WARN_ON(irqfd->producer != prod);
10514         irqfd->producer = NULL;
10515
10516         /*
10517          * When producer of consumer is unregistered, we change back to
10518          * remapped mode, so we can re-use the current implementation
10519          * when the irq is masked/disabled or the consumer side (KVM
10520          * int this case doesn't want to receive the interrupts.
10521         */
10522         ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10523         if (ret)
10524                 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10525                        " fails: %d\n", irqfd->consumer.token, ret);
10526 }
10527
10528 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10529                                    uint32_t guest_irq, bool set)
10530 {
10531         return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
10532 }
10533
10534 bool kvm_vector_hashing_enabled(void)
10535 {
10536         return vector_hashing;
10537 }
10538
10539 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10540 {
10541         return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10542 }
10543 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10544
10545 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10546 {
10547         uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10548
10549         /* The STIBP bit doesn't fault even if it's not advertised */
10550         if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10551             !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10552                 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10553         if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10554             !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10555                 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10556
10557         if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10558             !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10559                 bits &= ~SPEC_CTRL_SSBD;
10560         if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10561             !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10562                 bits &= ~SPEC_CTRL_SSBD;
10563
10564         return bits;
10565 }
10566 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
10567
10568 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10569 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10570 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10571 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10576 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10577 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10578 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10579 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10580 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10581 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10582 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10583 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10584 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10585 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10586 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10587 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10588 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
10589 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);