Merge branches 'arm/rockchip', 'arm/exynos', 'arm/smmu', 'x86/vt-d', 'x86/amd', ...
[sfrench/cifs-2.6.git] / arch / x86 / kvm / x86.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * derived from drivers/kvm/kvm_main.c
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright (C) 2008 Qumranet, Inc.
8  * Copyright IBM Corporation, 2008
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Amit Shah    <amit.shah@qumranet.com>
15  *   Ben-Ami Yassour <benami@il.ibm.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "assigned-dev.h"
31
32 #include <linux/clocksource.h>
33 #include <linux/interrupt.h>
34 #include <linux/kvm.h>
35 #include <linux/fs.h>
36 #include <linux/vmalloc.h>
37 #include <linux/module.h>
38 #include <linux/mman.h>
39 #include <linux/highmem.h>
40 #include <linux/iommu.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/cpufreq.h>
43 #include <linux/user-return-notifier.h>
44 #include <linux/srcu.h>
45 #include <linux/slab.h>
46 #include <linux/perf_event.h>
47 #include <linux/uaccess.h>
48 #include <linux/hash.h>
49 #include <linux/pci.h>
50 #include <linux/timekeeper_internal.h>
51 #include <linux/pvclock_gtod.h>
52 #include <trace/events/kvm.h>
53
54 #define CREATE_TRACE_POINTS
55 #include "trace.h"
56
57 #include <asm/debugreg.h>
58 #include <asm/msr.h>
59 #include <asm/desc.h>
60 #include <asm/mtrr.h>
61 #include <asm/mce.h>
62 #include <asm/i387.h>
63 #include <asm/fpu-internal.h> /* Ugh! */
64 #include <asm/xcr.h>
65 #include <asm/pvclock.h>
66 #include <asm/div64.h>
67
68 #define MAX_IO_MSRS 256
69 #define KVM_MAX_MCE_BANKS 32
70 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
71
72 #define emul_to_vcpu(ctxt) \
73         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
75 /* EFER defaults:
76  * - enable syscall per default because its emulated by KVM
77  * - enable LME and LMA per default on 64 bit KVM
78  */
79 #ifdef CONFIG_X86_64
80 static
81 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
82 #else
83 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
84 #endif
85
86 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
88
89 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
90 static void process_nmi(struct kvm_vcpu *vcpu);
91 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
92
93 struct kvm_x86_ops *kvm_x86_ops;
94 EXPORT_SYMBOL_GPL(kvm_x86_ops);
95
96 static bool ignore_msrs = 0;
97 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
98
99 unsigned int min_timer_period_us = 500;
100 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
102 bool kvm_has_tsc_control;
103 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
104 u32  kvm_max_guest_tsc_khz;
105 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106
107 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
108 static u32 tsc_tolerance_ppm = 250;
109 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110
111 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
112 unsigned int lapic_timer_advance_ns = 0;
113 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
114
115 static bool backwards_tsc_observed = false;
116
117 #define KVM_NR_SHARED_MSRS 16
118
119 struct kvm_shared_msrs_global {
120         int nr;
121         u32 msrs[KVM_NR_SHARED_MSRS];
122 };
123
124 struct kvm_shared_msrs {
125         struct user_return_notifier urn;
126         bool registered;
127         struct kvm_shared_msr_values {
128                 u64 host;
129                 u64 curr;
130         } values[KVM_NR_SHARED_MSRS];
131 };
132
133 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
134 static struct kvm_shared_msrs __percpu *shared_msrs;
135
136 struct kvm_stats_debugfs_item debugfs_entries[] = {
137         { "pf_fixed", VCPU_STAT(pf_fixed) },
138         { "pf_guest", VCPU_STAT(pf_guest) },
139         { "tlb_flush", VCPU_STAT(tlb_flush) },
140         { "invlpg", VCPU_STAT(invlpg) },
141         { "exits", VCPU_STAT(exits) },
142         { "io_exits", VCPU_STAT(io_exits) },
143         { "mmio_exits", VCPU_STAT(mmio_exits) },
144         { "signal_exits", VCPU_STAT(signal_exits) },
145         { "irq_window", VCPU_STAT(irq_window_exits) },
146         { "nmi_window", VCPU_STAT(nmi_window_exits) },
147         { "halt_exits", VCPU_STAT(halt_exits) },
148         { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
149         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
150         { "hypercalls", VCPU_STAT(hypercalls) },
151         { "request_irq", VCPU_STAT(request_irq_exits) },
152         { "irq_exits", VCPU_STAT(irq_exits) },
153         { "host_state_reload", VCPU_STAT(host_state_reload) },
154         { "efer_reload", VCPU_STAT(efer_reload) },
155         { "fpu_reload", VCPU_STAT(fpu_reload) },
156         { "insn_emulation", VCPU_STAT(insn_emulation) },
157         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
158         { "irq_injections", VCPU_STAT(irq_injections) },
159         { "nmi_injections", VCPU_STAT(nmi_injections) },
160         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
161         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
162         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
163         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
164         { "mmu_flooded", VM_STAT(mmu_flooded) },
165         { "mmu_recycled", VM_STAT(mmu_recycled) },
166         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
167         { "mmu_unsync", VM_STAT(mmu_unsync) },
168         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
169         { "largepages", VM_STAT(lpages) },
170         { NULL }
171 };
172
173 u64 __read_mostly host_xcr0;
174
175 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
176
177 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
178 {
179         int i;
180         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
181                 vcpu->arch.apf.gfns[i] = ~0;
182 }
183
184 static void kvm_on_user_return(struct user_return_notifier *urn)
185 {
186         unsigned slot;
187         struct kvm_shared_msrs *locals
188                 = container_of(urn, struct kvm_shared_msrs, urn);
189         struct kvm_shared_msr_values *values;
190
191         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
192                 values = &locals->values[slot];
193                 if (values->host != values->curr) {
194                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
195                         values->curr = values->host;
196                 }
197         }
198         locals->registered = false;
199         user_return_notifier_unregister(urn);
200 }
201
202 static void shared_msr_update(unsigned slot, u32 msr)
203 {
204         u64 value;
205         unsigned int cpu = smp_processor_id();
206         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
207
208         /* only read, and nobody should modify it at this time,
209          * so don't need lock */
210         if (slot >= shared_msrs_global.nr) {
211                 printk(KERN_ERR "kvm: invalid MSR slot!");
212                 return;
213         }
214         rdmsrl_safe(msr, &value);
215         smsr->values[slot].host = value;
216         smsr->values[slot].curr = value;
217 }
218
219 void kvm_define_shared_msr(unsigned slot, u32 msr)
220 {
221         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
222         if (slot >= shared_msrs_global.nr)
223                 shared_msrs_global.nr = slot + 1;
224         shared_msrs_global.msrs[slot] = msr;
225         /* we need ensured the shared_msr_global have been updated */
226         smp_wmb();
227 }
228 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
229
230 static void kvm_shared_msr_cpu_online(void)
231 {
232         unsigned i;
233
234         for (i = 0; i < shared_msrs_global.nr; ++i)
235                 shared_msr_update(i, shared_msrs_global.msrs[i]);
236 }
237
238 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
239 {
240         unsigned int cpu = smp_processor_id();
241         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
242         int err;
243
244         if (((value ^ smsr->values[slot].curr) & mask) == 0)
245                 return 0;
246         smsr->values[slot].curr = value;
247         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
248         if (err)
249                 return 1;
250
251         if (!smsr->registered) {
252                 smsr->urn.on_user_return = kvm_on_user_return;
253                 user_return_notifier_register(&smsr->urn);
254                 smsr->registered = true;
255         }
256         return 0;
257 }
258 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
259
260 static void drop_user_return_notifiers(void)
261 {
262         unsigned int cpu = smp_processor_id();
263         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
264
265         if (smsr->registered)
266                 kvm_on_user_return(&smsr->urn);
267 }
268
269 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
270 {
271         return vcpu->arch.apic_base;
272 }
273 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
274
275 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
276 {
277         u64 old_state = vcpu->arch.apic_base &
278                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
279         u64 new_state = msr_info->data &
280                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
282                 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
283
284         if (!msr_info->host_initiated &&
285             ((msr_info->data & reserved_bits) != 0 ||
286              new_state == X2APIC_ENABLE ||
287              (new_state == MSR_IA32_APICBASE_ENABLE &&
288               old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
289              (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
290               old_state == 0)))
291                 return 1;
292
293         kvm_lapic_set_base(vcpu, msr_info->data);
294         return 0;
295 }
296 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
297
298 asmlinkage __visible void kvm_spurious_fault(void)
299 {
300         /* Fault while not rebooting.  We want the trace. */
301         BUG();
302 }
303 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
304
305 #define EXCPT_BENIGN            0
306 #define EXCPT_CONTRIBUTORY      1
307 #define EXCPT_PF                2
308
309 static int exception_class(int vector)
310 {
311         switch (vector) {
312         case PF_VECTOR:
313                 return EXCPT_PF;
314         case DE_VECTOR:
315         case TS_VECTOR:
316         case NP_VECTOR:
317         case SS_VECTOR:
318         case GP_VECTOR:
319                 return EXCPT_CONTRIBUTORY;
320         default:
321                 break;
322         }
323         return EXCPT_BENIGN;
324 }
325
326 #define EXCPT_FAULT             0
327 #define EXCPT_TRAP              1
328 #define EXCPT_ABORT             2
329 #define EXCPT_INTERRUPT         3
330
331 static int exception_type(int vector)
332 {
333         unsigned int mask;
334
335         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
336                 return EXCPT_INTERRUPT;
337
338         mask = 1 << vector;
339
340         /* #DB is trap, as instruction watchpoints are handled elsewhere */
341         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
342                 return EXCPT_TRAP;
343
344         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
345                 return EXCPT_ABORT;
346
347         /* Reserved exceptions will result in fault */
348         return EXCPT_FAULT;
349 }
350
351 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
352                 unsigned nr, bool has_error, u32 error_code,
353                 bool reinject)
354 {
355         u32 prev_nr;
356         int class1, class2;
357
358         kvm_make_request(KVM_REQ_EVENT, vcpu);
359
360         if (!vcpu->arch.exception.pending) {
361         queue:
362                 if (has_error && !is_protmode(vcpu))
363                         has_error = false;
364                 vcpu->arch.exception.pending = true;
365                 vcpu->arch.exception.has_error_code = has_error;
366                 vcpu->arch.exception.nr = nr;
367                 vcpu->arch.exception.error_code = error_code;
368                 vcpu->arch.exception.reinject = reinject;
369                 return;
370         }
371
372         /* to check exception */
373         prev_nr = vcpu->arch.exception.nr;
374         if (prev_nr == DF_VECTOR) {
375                 /* triple fault -> shutdown */
376                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
377                 return;
378         }
379         class1 = exception_class(prev_nr);
380         class2 = exception_class(nr);
381         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
382                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
383                 /* generate double fault per SDM Table 5-5 */
384                 vcpu->arch.exception.pending = true;
385                 vcpu->arch.exception.has_error_code = true;
386                 vcpu->arch.exception.nr = DF_VECTOR;
387                 vcpu->arch.exception.error_code = 0;
388         } else
389                 /* replace previous exception with a new one in a hope
390                    that instruction re-execution will regenerate lost
391                    exception */
392                 goto queue;
393 }
394
395 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
396 {
397         kvm_multiple_exception(vcpu, nr, false, 0, false);
398 }
399 EXPORT_SYMBOL_GPL(kvm_queue_exception);
400
401 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
402 {
403         kvm_multiple_exception(vcpu, nr, false, 0, true);
404 }
405 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
406
407 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
408 {
409         if (err)
410                 kvm_inject_gp(vcpu, 0);
411         else
412                 kvm_x86_ops->skip_emulated_instruction(vcpu);
413 }
414 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
415
416 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
417 {
418         ++vcpu->stat.pf_guest;
419         vcpu->arch.cr2 = fault->address;
420         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
421 }
422 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
423
424 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
425 {
426         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
427                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
428         else
429                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
430
431         return fault->nested_page_fault;
432 }
433
434 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
435 {
436         atomic_inc(&vcpu->arch.nmi_queued);
437         kvm_make_request(KVM_REQ_NMI, vcpu);
438 }
439 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
440
441 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
442 {
443         kvm_multiple_exception(vcpu, nr, true, error_code, false);
444 }
445 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
446
447 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
448 {
449         kvm_multiple_exception(vcpu, nr, true, error_code, true);
450 }
451 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
452
453 /*
454  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
455  * a #GP and return false.
456  */
457 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
458 {
459         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
460                 return true;
461         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
462         return false;
463 }
464 EXPORT_SYMBOL_GPL(kvm_require_cpl);
465
466 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
467 {
468         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
469                 return true;
470
471         kvm_queue_exception(vcpu, UD_VECTOR);
472         return false;
473 }
474 EXPORT_SYMBOL_GPL(kvm_require_dr);
475
476 /*
477  * This function will be used to read from the physical memory of the currently
478  * running guest. The difference to kvm_read_guest_page is that this function
479  * can read from guest physical or from the guest's guest physical memory.
480  */
481 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
482                             gfn_t ngfn, void *data, int offset, int len,
483                             u32 access)
484 {
485         struct x86_exception exception;
486         gfn_t real_gfn;
487         gpa_t ngpa;
488
489         ngpa     = gfn_to_gpa(ngfn);
490         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
491         if (real_gfn == UNMAPPED_GVA)
492                 return -EFAULT;
493
494         real_gfn = gpa_to_gfn(real_gfn);
495
496         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
497 }
498 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
499
500 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
501                                void *data, int offset, int len, u32 access)
502 {
503         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
504                                        data, offset, len, access);
505 }
506
507 /*
508  * Load the pae pdptrs.  Return true is they are all valid.
509  */
510 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
511 {
512         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
513         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
514         int i;
515         int ret;
516         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
517
518         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
519                                       offset * sizeof(u64), sizeof(pdpte),
520                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
521         if (ret < 0) {
522                 ret = 0;
523                 goto out;
524         }
525         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
526                 if (is_present_gpte(pdpte[i]) &&
527                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
528                         ret = 0;
529                         goto out;
530                 }
531         }
532         ret = 1;
533
534         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
535         __set_bit(VCPU_EXREG_PDPTR,
536                   (unsigned long *)&vcpu->arch.regs_avail);
537         __set_bit(VCPU_EXREG_PDPTR,
538                   (unsigned long *)&vcpu->arch.regs_dirty);
539 out:
540
541         return ret;
542 }
543 EXPORT_SYMBOL_GPL(load_pdptrs);
544
545 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
546 {
547         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
548         bool changed = true;
549         int offset;
550         gfn_t gfn;
551         int r;
552
553         if (is_long_mode(vcpu) || !is_pae(vcpu))
554                 return false;
555
556         if (!test_bit(VCPU_EXREG_PDPTR,
557                       (unsigned long *)&vcpu->arch.regs_avail))
558                 return true;
559
560         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
561         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
562         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
563                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
564         if (r < 0)
565                 goto out;
566         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
567 out:
568
569         return changed;
570 }
571
572 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
573 {
574         unsigned long old_cr0 = kvm_read_cr0(vcpu);
575         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
576                                     X86_CR0_CD | X86_CR0_NW;
577
578         cr0 |= X86_CR0_ET;
579
580 #ifdef CONFIG_X86_64
581         if (cr0 & 0xffffffff00000000UL)
582                 return 1;
583 #endif
584
585         cr0 &= ~CR0_RESERVED_BITS;
586
587         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
588                 return 1;
589
590         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
591                 return 1;
592
593         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
594 #ifdef CONFIG_X86_64
595                 if ((vcpu->arch.efer & EFER_LME)) {
596                         int cs_db, cs_l;
597
598                         if (!is_pae(vcpu))
599                                 return 1;
600                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
601                         if (cs_l)
602                                 return 1;
603                 } else
604 #endif
605                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
606                                                  kvm_read_cr3(vcpu)))
607                         return 1;
608         }
609
610         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
611                 return 1;
612
613         kvm_x86_ops->set_cr0(vcpu, cr0);
614
615         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
616                 kvm_clear_async_pf_completion_queue(vcpu);
617                 kvm_async_pf_hash_reset(vcpu);
618         }
619
620         if ((cr0 ^ old_cr0) & update_bits)
621                 kvm_mmu_reset_context(vcpu);
622         return 0;
623 }
624 EXPORT_SYMBOL_GPL(kvm_set_cr0);
625
626 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
627 {
628         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
629 }
630 EXPORT_SYMBOL_GPL(kvm_lmsw);
631
632 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
633 {
634         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
635                         !vcpu->guest_xcr0_loaded) {
636                 /* kvm_set_xcr() also depends on this */
637                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
638                 vcpu->guest_xcr0_loaded = 1;
639         }
640 }
641
642 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
643 {
644         if (vcpu->guest_xcr0_loaded) {
645                 if (vcpu->arch.xcr0 != host_xcr0)
646                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
647                 vcpu->guest_xcr0_loaded = 0;
648         }
649 }
650
651 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
652 {
653         u64 xcr0 = xcr;
654         u64 old_xcr0 = vcpu->arch.xcr0;
655         u64 valid_bits;
656
657         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
658         if (index != XCR_XFEATURE_ENABLED_MASK)
659                 return 1;
660         if (!(xcr0 & XSTATE_FP))
661                 return 1;
662         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
663                 return 1;
664
665         /*
666          * Do not allow the guest to set bits that we do not support
667          * saving.  However, xcr0 bit 0 is always set, even if the
668          * emulated CPU does not support XSAVE (see fx_init).
669          */
670         valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
671         if (xcr0 & ~valid_bits)
672                 return 1;
673
674         if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
675                 return 1;
676
677         if (xcr0 & XSTATE_AVX512) {
678                 if (!(xcr0 & XSTATE_YMM))
679                         return 1;
680                 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
681                         return 1;
682         }
683         kvm_put_guest_xcr0(vcpu);
684         vcpu->arch.xcr0 = xcr0;
685
686         if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
687                 kvm_update_cpuid(vcpu);
688         return 0;
689 }
690
691 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
692 {
693         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
694             __kvm_set_xcr(vcpu, index, xcr)) {
695                 kvm_inject_gp(vcpu, 0);
696                 return 1;
697         }
698         return 0;
699 }
700 EXPORT_SYMBOL_GPL(kvm_set_xcr);
701
702 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
703 {
704         unsigned long old_cr4 = kvm_read_cr4(vcpu);
705         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
706                                    X86_CR4_SMEP | X86_CR4_SMAP;
707
708         if (cr4 & CR4_RESERVED_BITS)
709                 return 1;
710
711         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
712                 return 1;
713
714         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
715                 return 1;
716
717         if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
718                 return 1;
719
720         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
721                 return 1;
722
723         if (is_long_mode(vcpu)) {
724                 if (!(cr4 & X86_CR4_PAE))
725                         return 1;
726         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
727                    && ((cr4 ^ old_cr4) & pdptr_bits)
728                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
729                                    kvm_read_cr3(vcpu)))
730                 return 1;
731
732         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
733                 if (!guest_cpuid_has_pcid(vcpu))
734                         return 1;
735
736                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
737                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
738                         return 1;
739         }
740
741         if (kvm_x86_ops->set_cr4(vcpu, cr4))
742                 return 1;
743
744         if (((cr4 ^ old_cr4) & pdptr_bits) ||
745             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
746                 kvm_mmu_reset_context(vcpu);
747
748         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
749                 kvm_update_cpuid(vcpu);
750
751         return 0;
752 }
753 EXPORT_SYMBOL_GPL(kvm_set_cr4);
754
755 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
756 {
757 #ifdef CONFIG_X86_64
758         cr3 &= ~CR3_PCID_INVD;
759 #endif
760
761         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
762                 kvm_mmu_sync_roots(vcpu);
763                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
764                 return 0;
765         }
766
767         if (is_long_mode(vcpu)) {
768                 if (cr3 & CR3_L_MODE_RESERVED_BITS)
769                         return 1;
770         } else if (is_pae(vcpu) && is_paging(vcpu) &&
771                    !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
772                 return 1;
773
774         vcpu->arch.cr3 = cr3;
775         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
776         kvm_mmu_new_cr3(vcpu);
777         return 0;
778 }
779 EXPORT_SYMBOL_GPL(kvm_set_cr3);
780
781 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
782 {
783         if (cr8 & CR8_RESERVED_BITS)
784                 return 1;
785         if (irqchip_in_kernel(vcpu->kvm))
786                 kvm_lapic_set_tpr(vcpu, cr8);
787         else
788                 vcpu->arch.cr8 = cr8;
789         return 0;
790 }
791 EXPORT_SYMBOL_GPL(kvm_set_cr8);
792
793 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
794 {
795         if (irqchip_in_kernel(vcpu->kvm))
796                 return kvm_lapic_get_cr8(vcpu);
797         else
798                 return vcpu->arch.cr8;
799 }
800 EXPORT_SYMBOL_GPL(kvm_get_cr8);
801
802 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
803 {
804         int i;
805
806         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
807                 for (i = 0; i < KVM_NR_DB_REGS; i++)
808                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
809                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
810         }
811 }
812
813 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
814 {
815         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
816                 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
817 }
818
819 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
820 {
821         unsigned long dr7;
822
823         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
824                 dr7 = vcpu->arch.guest_debug_dr7;
825         else
826                 dr7 = vcpu->arch.dr7;
827         kvm_x86_ops->set_dr7(vcpu, dr7);
828         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
829         if (dr7 & DR7_BP_EN_MASK)
830                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
831 }
832
833 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
834 {
835         u64 fixed = DR6_FIXED_1;
836
837         if (!guest_cpuid_has_rtm(vcpu))
838                 fixed |= DR6_RTM;
839         return fixed;
840 }
841
842 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
843 {
844         switch (dr) {
845         case 0 ... 3:
846                 vcpu->arch.db[dr] = val;
847                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
848                         vcpu->arch.eff_db[dr] = val;
849                 break;
850         case 4:
851                 /* fall through */
852         case 6:
853                 if (val & 0xffffffff00000000ULL)
854                         return -1; /* #GP */
855                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
856                 kvm_update_dr6(vcpu);
857                 break;
858         case 5:
859                 /* fall through */
860         default: /* 7 */
861                 if (val & 0xffffffff00000000ULL)
862                         return -1; /* #GP */
863                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
864                 kvm_update_dr7(vcpu);
865                 break;
866         }
867
868         return 0;
869 }
870
871 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
872 {
873         if (__kvm_set_dr(vcpu, dr, val)) {
874                 kvm_inject_gp(vcpu, 0);
875                 return 1;
876         }
877         return 0;
878 }
879 EXPORT_SYMBOL_GPL(kvm_set_dr);
880
881 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
882 {
883         switch (dr) {
884         case 0 ... 3:
885                 *val = vcpu->arch.db[dr];
886                 break;
887         case 4:
888                 /* fall through */
889         case 6:
890                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
891                         *val = vcpu->arch.dr6;
892                 else
893                         *val = kvm_x86_ops->get_dr6(vcpu);
894                 break;
895         case 5:
896                 /* fall through */
897         default: /* 7 */
898                 *val = vcpu->arch.dr7;
899                 break;
900         }
901         return 0;
902 }
903 EXPORT_SYMBOL_GPL(kvm_get_dr);
904
905 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
906 {
907         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
908         u64 data;
909         int err;
910
911         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
912         if (err)
913                 return err;
914         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
915         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
916         return err;
917 }
918 EXPORT_SYMBOL_GPL(kvm_rdpmc);
919
920 /*
921  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
922  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
923  *
924  * This list is modified at module load time to reflect the
925  * capabilities of the host cpu. This capabilities test skips MSRs that are
926  * kvm-specific. Those are put in the beginning of the list.
927  */
928
929 #define KVM_SAVE_MSRS_BEGIN     12
930 static u32 msrs_to_save[] = {
931         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
932         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
933         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
934         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
935         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
936         MSR_KVM_PV_EOI_EN,
937         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
938         MSR_STAR,
939 #ifdef CONFIG_X86_64
940         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
941 #endif
942         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
943         MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
944 };
945
946 static unsigned num_msrs_to_save;
947
948 static const u32 emulated_msrs[] = {
949         MSR_IA32_TSC_ADJUST,
950         MSR_IA32_TSCDEADLINE,
951         MSR_IA32_MISC_ENABLE,
952         MSR_IA32_MCG_STATUS,
953         MSR_IA32_MCG_CTL,
954 };
955
956 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
957 {
958         if (efer & efer_reserved_bits)
959                 return false;
960
961         if (efer & EFER_FFXSR) {
962                 struct kvm_cpuid_entry2 *feat;
963
964                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
965                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
966                         return false;
967         }
968
969         if (efer & EFER_SVME) {
970                 struct kvm_cpuid_entry2 *feat;
971
972                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
973                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
974                         return false;
975         }
976
977         return true;
978 }
979 EXPORT_SYMBOL_GPL(kvm_valid_efer);
980
981 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
982 {
983         u64 old_efer = vcpu->arch.efer;
984
985         if (!kvm_valid_efer(vcpu, efer))
986                 return 1;
987
988         if (is_paging(vcpu)
989             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
990                 return 1;
991
992         efer &= ~EFER_LMA;
993         efer |= vcpu->arch.efer & EFER_LMA;
994
995         kvm_x86_ops->set_efer(vcpu, efer);
996
997         /* Update reserved bits */
998         if ((efer ^ old_efer) & EFER_NX)
999                 kvm_mmu_reset_context(vcpu);
1000
1001         return 0;
1002 }
1003
1004 void kvm_enable_efer_bits(u64 mask)
1005 {
1006        efer_reserved_bits &= ~mask;
1007 }
1008 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1009
1010 /*
1011  * Writes msr value into into the appropriate "register".
1012  * Returns 0 on success, non-0 otherwise.
1013  * Assumes vcpu_load() was already called.
1014  */
1015 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1016 {
1017         switch (msr->index) {
1018         case MSR_FS_BASE:
1019         case MSR_GS_BASE:
1020         case MSR_KERNEL_GS_BASE:
1021         case MSR_CSTAR:
1022         case MSR_LSTAR:
1023                 if (is_noncanonical_address(msr->data))
1024                         return 1;
1025                 break;
1026         case MSR_IA32_SYSENTER_EIP:
1027         case MSR_IA32_SYSENTER_ESP:
1028                 /*
1029                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1030                  * non-canonical address is written on Intel but not on
1031                  * AMD (which ignores the top 32-bits, because it does
1032                  * not implement 64-bit SYSENTER).
1033                  *
1034                  * 64-bit code should hence be able to write a non-canonical
1035                  * value on AMD.  Making the address canonical ensures that
1036                  * vmentry does not fail on Intel after writing a non-canonical
1037                  * value, and that something deterministic happens if the guest
1038                  * invokes 64-bit SYSENTER.
1039                  */
1040                 msr->data = get_canonical(msr->data);
1041         }
1042         return kvm_x86_ops->set_msr(vcpu, msr);
1043 }
1044 EXPORT_SYMBOL_GPL(kvm_set_msr);
1045
1046 /*
1047  * Adapt set_msr() to msr_io()'s calling convention
1048  */
1049 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1050 {
1051         struct msr_data msr;
1052
1053         msr.data = *data;
1054         msr.index = index;
1055         msr.host_initiated = true;
1056         return kvm_set_msr(vcpu, &msr);
1057 }
1058
1059 #ifdef CONFIG_X86_64
1060 struct pvclock_gtod_data {
1061         seqcount_t      seq;
1062
1063         struct { /* extract of a clocksource struct */
1064                 int vclock_mode;
1065                 cycle_t cycle_last;
1066                 cycle_t mask;
1067                 u32     mult;
1068                 u32     shift;
1069         } clock;
1070
1071         u64             boot_ns;
1072         u64             nsec_base;
1073 };
1074
1075 static struct pvclock_gtod_data pvclock_gtod_data;
1076
1077 static void update_pvclock_gtod(struct timekeeper *tk)
1078 {
1079         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1080         u64 boot_ns;
1081
1082         boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1083
1084         write_seqcount_begin(&vdata->seq);
1085
1086         /* copy pvclock gtod data */
1087         vdata->clock.vclock_mode        = tk->tkr_mono.clock->archdata.vclock_mode;
1088         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1089         vdata->clock.mask               = tk->tkr_mono.mask;
1090         vdata->clock.mult               = tk->tkr_mono.mult;
1091         vdata->clock.shift              = tk->tkr_mono.shift;
1092
1093         vdata->boot_ns                  = boot_ns;
1094         vdata->nsec_base                = tk->tkr_mono.xtime_nsec;
1095
1096         write_seqcount_end(&vdata->seq);
1097 }
1098 #endif
1099
1100 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1101 {
1102         /*
1103          * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1104          * vcpu_enter_guest.  This function is only called from
1105          * the physical CPU that is running vcpu.
1106          */
1107         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1108 }
1109
1110 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1111 {
1112         int version;
1113         int r;
1114         struct pvclock_wall_clock wc;
1115         struct timespec boot;
1116
1117         if (!wall_clock)
1118                 return;
1119
1120         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1121         if (r)
1122                 return;
1123
1124         if (version & 1)
1125                 ++version;  /* first time write, random junk */
1126
1127         ++version;
1128
1129         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1130
1131         /*
1132          * The guest calculates current wall clock time by adding
1133          * system time (updated by kvm_guest_time_update below) to the
1134          * wall clock specified here.  guest system time equals host
1135          * system time for us, thus we must fill in host boot time here.
1136          */
1137         getboottime(&boot);
1138
1139         if (kvm->arch.kvmclock_offset) {
1140                 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1141                 boot = timespec_sub(boot, ts);
1142         }
1143         wc.sec = boot.tv_sec;
1144         wc.nsec = boot.tv_nsec;
1145         wc.version = version;
1146
1147         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1148
1149         version++;
1150         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1151 }
1152
1153 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1154 {
1155         uint32_t quotient, remainder;
1156
1157         /* Don't try to replace with do_div(), this one calculates
1158          * "(dividend << 32) / divisor" */
1159         __asm__ ( "divl %4"
1160                   : "=a" (quotient), "=d" (remainder)
1161                   : "0" (0), "1" (dividend), "r" (divisor) );
1162         return quotient;
1163 }
1164
1165 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1166                                s8 *pshift, u32 *pmultiplier)
1167 {
1168         uint64_t scaled64;
1169         int32_t  shift = 0;
1170         uint64_t tps64;
1171         uint32_t tps32;
1172
1173         tps64 = base_khz * 1000LL;
1174         scaled64 = scaled_khz * 1000LL;
1175         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1176                 tps64 >>= 1;
1177                 shift--;
1178         }
1179
1180         tps32 = (uint32_t)tps64;
1181         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1182                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1183                         scaled64 >>= 1;
1184                 else
1185                         tps32 <<= 1;
1186                 shift++;
1187         }
1188
1189         *pshift = shift;
1190         *pmultiplier = div_frac(scaled64, tps32);
1191
1192         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1193                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
1194 }
1195
1196 static inline u64 get_kernel_ns(void)
1197 {
1198         return ktime_get_boot_ns();
1199 }
1200
1201 #ifdef CONFIG_X86_64
1202 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1203 #endif
1204
1205 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1206 static unsigned long max_tsc_khz;
1207
1208 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1209 {
1210         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1211                                    vcpu->arch.virtual_tsc_shift);
1212 }
1213
1214 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1215 {
1216         u64 v = (u64)khz * (1000000 + ppm);
1217         do_div(v, 1000000);
1218         return v;
1219 }
1220
1221 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1222 {
1223         u32 thresh_lo, thresh_hi;
1224         int use_scaling = 0;
1225
1226         /* tsc_khz can be zero if TSC calibration fails */
1227         if (this_tsc_khz == 0)
1228                 return;
1229
1230         /* Compute a scale to convert nanoseconds in TSC cycles */
1231         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1232                            &vcpu->arch.virtual_tsc_shift,
1233                            &vcpu->arch.virtual_tsc_mult);
1234         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1235
1236         /*
1237          * Compute the variation in TSC rate which is acceptable
1238          * within the range of tolerance and decide if the
1239          * rate being applied is within that bounds of the hardware
1240          * rate.  If so, no scaling or compensation need be done.
1241          */
1242         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1243         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1244         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1245                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1246                 use_scaling = 1;
1247         }
1248         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1249 }
1250
1251 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1252 {
1253         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1254                                       vcpu->arch.virtual_tsc_mult,
1255                                       vcpu->arch.virtual_tsc_shift);
1256         tsc += vcpu->arch.this_tsc_write;
1257         return tsc;
1258 }
1259
1260 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1261 {
1262 #ifdef CONFIG_X86_64
1263         bool vcpus_matched;
1264         struct kvm_arch *ka = &vcpu->kvm->arch;
1265         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1266
1267         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1268                          atomic_read(&vcpu->kvm->online_vcpus));
1269
1270         /*
1271          * Once the masterclock is enabled, always perform request in
1272          * order to update it.
1273          *
1274          * In order to enable masterclock, the host clocksource must be TSC
1275          * and the vcpus need to have matched TSCs.  When that happens,
1276          * perform request to enable masterclock.
1277          */
1278         if (ka->use_master_clock ||
1279             (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1280                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1281
1282         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1283                             atomic_read(&vcpu->kvm->online_vcpus),
1284                             ka->use_master_clock, gtod->clock.vclock_mode);
1285 #endif
1286 }
1287
1288 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1289 {
1290         u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1291         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1292 }
1293
1294 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1295 {
1296         struct kvm *kvm = vcpu->kvm;
1297         u64 offset, ns, elapsed;
1298         unsigned long flags;
1299         s64 usdiff;
1300         bool matched;
1301         bool already_matched;
1302         u64 data = msr->data;
1303
1304         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1305         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1306         ns = get_kernel_ns();
1307         elapsed = ns - kvm->arch.last_tsc_nsec;
1308
1309         if (vcpu->arch.virtual_tsc_khz) {
1310                 int faulted = 0;
1311
1312                 /* n.b - signed multiplication and division required */
1313                 usdiff = data - kvm->arch.last_tsc_write;
1314 #ifdef CONFIG_X86_64
1315                 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1316 #else
1317                 /* do_div() only does unsigned */
1318                 asm("1: idivl %[divisor]\n"
1319                     "2: xor %%edx, %%edx\n"
1320                     "   movl $0, %[faulted]\n"
1321                     "3:\n"
1322                     ".section .fixup,\"ax\"\n"
1323                     "4: movl $1, %[faulted]\n"
1324                     "   jmp  3b\n"
1325                     ".previous\n"
1326
1327                 _ASM_EXTABLE(1b, 4b)
1328
1329                 : "=A"(usdiff), [faulted] "=r" (faulted)
1330                 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1331
1332 #endif
1333                 do_div(elapsed, 1000);
1334                 usdiff -= elapsed;
1335                 if (usdiff < 0)
1336                         usdiff = -usdiff;
1337
1338                 /* idivl overflow => difference is larger than USEC_PER_SEC */
1339                 if (faulted)
1340                         usdiff = USEC_PER_SEC;
1341         } else
1342                 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1343
1344         /*
1345          * Special case: TSC write with a small delta (1 second) of virtual
1346          * cycle time against real time is interpreted as an attempt to
1347          * synchronize the CPU.
1348          *
1349          * For a reliable TSC, we can match TSC offsets, and for an unstable
1350          * TSC, we add elapsed time in this computation.  We could let the
1351          * compensation code attempt to catch up if we fall behind, but
1352          * it's better to try to match offsets from the beginning.
1353          */
1354         if (usdiff < USEC_PER_SEC &&
1355             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1356                 if (!check_tsc_unstable()) {
1357                         offset = kvm->arch.cur_tsc_offset;
1358                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1359                 } else {
1360                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1361                         data += delta;
1362                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1363                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1364                 }
1365                 matched = true;
1366                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1367         } else {
1368                 /*
1369                  * We split periods of matched TSC writes into generations.
1370                  * For each generation, we track the original measured
1371                  * nanosecond time, offset, and write, so if TSCs are in
1372                  * sync, we can match exact offset, and if not, we can match
1373                  * exact software computation in compute_guest_tsc()
1374                  *
1375                  * These values are tracked in kvm->arch.cur_xxx variables.
1376                  */
1377                 kvm->arch.cur_tsc_generation++;
1378                 kvm->arch.cur_tsc_nsec = ns;
1379                 kvm->arch.cur_tsc_write = data;
1380                 kvm->arch.cur_tsc_offset = offset;
1381                 matched = false;
1382                 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1383                          kvm->arch.cur_tsc_generation, data);
1384         }
1385
1386         /*
1387          * We also track th most recent recorded KHZ, write and time to
1388          * allow the matching interval to be extended at each write.
1389          */
1390         kvm->arch.last_tsc_nsec = ns;
1391         kvm->arch.last_tsc_write = data;
1392         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1393
1394         vcpu->arch.last_guest_tsc = data;
1395
1396         /* Keep track of which generation this VCPU has synchronized to */
1397         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1398         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1399         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1400
1401         if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1402                 update_ia32_tsc_adjust_msr(vcpu, offset);
1403         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1404         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1405
1406         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1407         if (!matched) {
1408                 kvm->arch.nr_vcpus_matched_tsc = 0;
1409         } else if (!already_matched) {
1410                 kvm->arch.nr_vcpus_matched_tsc++;
1411         }
1412
1413         kvm_track_tsc_matching(vcpu);
1414         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1415 }
1416
1417 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1418
1419 #ifdef CONFIG_X86_64
1420
1421 static cycle_t read_tsc(void)
1422 {
1423         cycle_t ret;
1424         u64 last;
1425
1426         /*
1427          * Empirically, a fence (of type that depends on the CPU)
1428          * before rdtsc is enough to ensure that rdtsc is ordered
1429          * with respect to loads.  The various CPU manuals are unclear
1430          * as to whether rdtsc can be reordered with later loads,
1431          * but no one has ever seen it happen.
1432          */
1433         rdtsc_barrier();
1434         ret = (cycle_t)vget_cycles();
1435
1436         last = pvclock_gtod_data.clock.cycle_last;
1437
1438         if (likely(ret >= last))
1439                 return ret;
1440
1441         /*
1442          * GCC likes to generate cmov here, but this branch is extremely
1443          * predictable (it's just a funciton of time and the likely is
1444          * very likely) and there's a data dependence, so force GCC
1445          * to generate a branch instead.  I don't barrier() because
1446          * we don't actually need a barrier, and if this function
1447          * ever gets inlined it will generate worse code.
1448          */
1449         asm volatile ("");
1450         return last;
1451 }
1452
1453 static inline u64 vgettsc(cycle_t *cycle_now)
1454 {
1455         long v;
1456         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1457
1458         *cycle_now = read_tsc();
1459
1460         v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1461         return v * gtod->clock.mult;
1462 }
1463
1464 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1465 {
1466         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1467         unsigned long seq;
1468         int mode;
1469         u64 ns;
1470
1471         do {
1472                 seq = read_seqcount_begin(&gtod->seq);
1473                 mode = gtod->clock.vclock_mode;
1474                 ns = gtod->nsec_base;
1475                 ns += vgettsc(cycle_now);
1476                 ns >>= gtod->clock.shift;
1477                 ns += gtod->boot_ns;
1478         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1479         *t = ns;
1480
1481         return mode;
1482 }
1483
1484 /* returns true if host is using tsc clocksource */
1485 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1486 {
1487         /* checked again under seqlock below */
1488         if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1489                 return false;
1490
1491         return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1492 }
1493 #endif
1494
1495 /*
1496  *
1497  * Assuming a stable TSC across physical CPUS, and a stable TSC
1498  * across virtual CPUs, the following condition is possible.
1499  * Each numbered line represents an event visible to both
1500  * CPUs at the next numbered event.
1501  *
1502  * "timespecX" represents host monotonic time. "tscX" represents
1503  * RDTSC value.
1504  *
1505  *              VCPU0 on CPU0           |       VCPU1 on CPU1
1506  *
1507  * 1.  read timespec0,tsc0
1508  * 2.                                   | timespec1 = timespec0 + N
1509  *                                      | tsc1 = tsc0 + M
1510  * 3. transition to guest               | transition to guest
1511  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1512  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
1513  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1514  *
1515  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1516  *
1517  *      - ret0 < ret1
1518  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1519  *              ...
1520  *      - 0 < N - M => M < N
1521  *
1522  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1523  * always the case (the difference between two distinct xtime instances
1524  * might be smaller then the difference between corresponding TSC reads,
1525  * when updating guest vcpus pvclock areas).
1526  *
1527  * To avoid that problem, do not allow visibility of distinct
1528  * system_timestamp/tsc_timestamp values simultaneously: use a master
1529  * copy of host monotonic time values. Update that master copy
1530  * in lockstep.
1531  *
1532  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1533  *
1534  */
1535
1536 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1537 {
1538 #ifdef CONFIG_X86_64
1539         struct kvm_arch *ka = &kvm->arch;
1540         int vclock_mode;
1541         bool host_tsc_clocksource, vcpus_matched;
1542
1543         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1544                         atomic_read(&kvm->online_vcpus));
1545
1546         /*
1547          * If the host uses TSC clock, then passthrough TSC as stable
1548          * to the guest.
1549          */
1550         host_tsc_clocksource = kvm_get_time_and_clockread(
1551                                         &ka->master_kernel_ns,
1552                                         &ka->master_cycle_now);
1553
1554         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1555                                 && !backwards_tsc_observed
1556                                 && !ka->boot_vcpu_runs_old_kvmclock;
1557
1558         if (ka->use_master_clock)
1559                 atomic_set(&kvm_guest_has_master_clock, 1);
1560
1561         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1562         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1563                                         vcpus_matched);
1564 #endif
1565 }
1566
1567 static void kvm_gen_update_masterclock(struct kvm *kvm)
1568 {
1569 #ifdef CONFIG_X86_64
1570         int i;
1571         struct kvm_vcpu *vcpu;
1572         struct kvm_arch *ka = &kvm->arch;
1573
1574         spin_lock(&ka->pvclock_gtod_sync_lock);
1575         kvm_make_mclock_inprogress_request(kvm);
1576         /* no guest entries from this point */
1577         pvclock_update_vm_gtod_copy(kvm);
1578
1579         kvm_for_each_vcpu(i, vcpu, kvm)
1580                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1581
1582         /* guest entries allowed */
1583         kvm_for_each_vcpu(i, vcpu, kvm)
1584                 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1585
1586         spin_unlock(&ka->pvclock_gtod_sync_lock);
1587 #endif
1588 }
1589
1590 static int kvm_guest_time_update(struct kvm_vcpu *v)
1591 {
1592         unsigned long flags, this_tsc_khz;
1593         struct kvm_vcpu_arch *vcpu = &v->arch;
1594         struct kvm_arch *ka = &v->kvm->arch;
1595         s64 kernel_ns;
1596         u64 tsc_timestamp, host_tsc;
1597         struct pvclock_vcpu_time_info guest_hv_clock;
1598         u8 pvclock_flags;
1599         bool use_master_clock;
1600
1601         kernel_ns = 0;
1602         host_tsc = 0;
1603
1604         /*
1605          * If the host uses TSC clock, then passthrough TSC as stable
1606          * to the guest.
1607          */
1608         spin_lock(&ka->pvclock_gtod_sync_lock);
1609         use_master_clock = ka->use_master_clock;
1610         if (use_master_clock) {
1611                 host_tsc = ka->master_cycle_now;
1612                 kernel_ns = ka->master_kernel_ns;
1613         }
1614         spin_unlock(&ka->pvclock_gtod_sync_lock);
1615
1616         /* Keep irq disabled to prevent changes to the clock */
1617         local_irq_save(flags);
1618         this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1619         if (unlikely(this_tsc_khz == 0)) {
1620                 local_irq_restore(flags);
1621                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1622                 return 1;
1623         }
1624         if (!use_master_clock) {
1625                 host_tsc = native_read_tsc();
1626                 kernel_ns = get_kernel_ns();
1627         }
1628
1629         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1630
1631         /*
1632          * We may have to catch up the TSC to match elapsed wall clock
1633          * time for two reasons, even if kvmclock is used.
1634          *   1) CPU could have been running below the maximum TSC rate
1635          *   2) Broken TSC compensation resets the base at each VCPU
1636          *      entry to avoid unknown leaps of TSC even when running
1637          *      again on the same CPU.  This may cause apparent elapsed
1638          *      time to disappear, and the guest to stand still or run
1639          *      very slowly.
1640          */
1641         if (vcpu->tsc_catchup) {
1642                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1643                 if (tsc > tsc_timestamp) {
1644                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1645                         tsc_timestamp = tsc;
1646                 }
1647         }
1648
1649         local_irq_restore(flags);
1650
1651         if (!vcpu->pv_time_enabled)
1652                 return 0;
1653
1654         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1655                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1656                                    &vcpu->hv_clock.tsc_shift,
1657                                    &vcpu->hv_clock.tsc_to_system_mul);
1658                 vcpu->hw_tsc_khz = this_tsc_khz;
1659         }
1660
1661         /* With all the info we got, fill in the values */
1662         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1663         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1664         vcpu->last_guest_tsc = tsc_timestamp;
1665
1666         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1667                 &guest_hv_clock, sizeof(guest_hv_clock))))
1668                 return 0;
1669
1670         /* This VCPU is paused, but it's legal for a guest to read another
1671          * VCPU's kvmclock, so we really have to follow the specification where
1672          * it says that version is odd if data is being modified, and even after
1673          * it is consistent.
1674          *
1675          * Version field updates must be kept separate.  This is because
1676          * kvm_write_guest_cached might use a "rep movs" instruction, and
1677          * writes within a string instruction are weakly ordered.  So there
1678          * are three writes overall.
1679          *
1680          * As a small optimization, only write the version field in the first
1681          * and third write.  The vcpu->pv_time cache is still valid, because the
1682          * version field is the first in the struct.
1683          */
1684         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1685
1686         vcpu->hv_clock.version = guest_hv_clock.version + 1;
1687         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1688                                 &vcpu->hv_clock,
1689                                 sizeof(vcpu->hv_clock.version));
1690
1691         smp_wmb();
1692
1693         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1694         pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1695
1696         if (vcpu->pvclock_set_guest_stopped_request) {
1697                 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1698                 vcpu->pvclock_set_guest_stopped_request = false;
1699         }
1700
1701         /* If the host uses TSC clocksource, then it is stable */
1702         if (use_master_clock)
1703                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1704
1705         vcpu->hv_clock.flags = pvclock_flags;
1706
1707         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1708
1709         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1710                                 &vcpu->hv_clock,
1711                                 sizeof(vcpu->hv_clock));
1712
1713         smp_wmb();
1714
1715         vcpu->hv_clock.version++;
1716         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1717                                 &vcpu->hv_clock,
1718                                 sizeof(vcpu->hv_clock.version));
1719         return 0;
1720 }
1721
1722 /*
1723  * kvmclock updates which are isolated to a given vcpu, such as
1724  * vcpu->cpu migration, should not allow system_timestamp from
1725  * the rest of the vcpus to remain static. Otherwise ntp frequency
1726  * correction applies to one vcpu's system_timestamp but not
1727  * the others.
1728  *
1729  * So in those cases, request a kvmclock update for all vcpus.
1730  * We need to rate-limit these requests though, as they can
1731  * considerably slow guests that have a large number of vcpus.
1732  * The time for a remote vcpu to update its kvmclock is bound
1733  * by the delay we use to rate-limit the updates.
1734  */
1735
1736 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1737
1738 static void kvmclock_update_fn(struct work_struct *work)
1739 {
1740         int i;
1741         struct delayed_work *dwork = to_delayed_work(work);
1742         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1743                                            kvmclock_update_work);
1744         struct kvm *kvm = container_of(ka, struct kvm, arch);
1745         struct kvm_vcpu *vcpu;
1746
1747         kvm_for_each_vcpu(i, vcpu, kvm) {
1748                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1749                 kvm_vcpu_kick(vcpu);
1750         }
1751 }
1752
1753 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1754 {
1755         struct kvm *kvm = v->kvm;
1756
1757         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1758         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1759                                         KVMCLOCK_UPDATE_DELAY);
1760 }
1761
1762 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1763
1764 static void kvmclock_sync_fn(struct work_struct *work)
1765 {
1766         struct delayed_work *dwork = to_delayed_work(work);
1767         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1768                                            kvmclock_sync_work);
1769         struct kvm *kvm = container_of(ka, struct kvm, arch);
1770
1771         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1772         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1773                                         KVMCLOCK_SYNC_PERIOD);
1774 }
1775
1776 static bool msr_mtrr_valid(unsigned msr)
1777 {
1778         switch (msr) {
1779         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1780         case MSR_MTRRfix64K_00000:
1781         case MSR_MTRRfix16K_80000:
1782         case MSR_MTRRfix16K_A0000:
1783         case MSR_MTRRfix4K_C0000:
1784         case MSR_MTRRfix4K_C8000:
1785         case MSR_MTRRfix4K_D0000:
1786         case MSR_MTRRfix4K_D8000:
1787         case MSR_MTRRfix4K_E0000:
1788         case MSR_MTRRfix4K_E8000:
1789         case MSR_MTRRfix4K_F0000:
1790         case MSR_MTRRfix4K_F8000:
1791         case MSR_MTRRdefType:
1792         case MSR_IA32_CR_PAT:
1793                 return true;
1794         case 0x2f8:
1795                 return true;
1796         }
1797         return false;
1798 }
1799
1800 static bool valid_pat_type(unsigned t)
1801 {
1802         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1803 }
1804
1805 static bool valid_mtrr_type(unsigned t)
1806 {
1807         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1808 }
1809
1810 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1811 {
1812         int i;
1813         u64 mask;
1814
1815         if (!msr_mtrr_valid(msr))
1816                 return false;
1817
1818         if (msr == MSR_IA32_CR_PAT) {
1819                 for (i = 0; i < 8; i++)
1820                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1821                                 return false;
1822                 return true;
1823         } else if (msr == MSR_MTRRdefType) {
1824                 if (data & ~0xcff)
1825                         return false;
1826                 return valid_mtrr_type(data & 0xff);
1827         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1828                 for (i = 0; i < 8 ; i++)
1829                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1830                                 return false;
1831                 return true;
1832         }
1833
1834         /* variable MTRRs */
1835         WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1836
1837         mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
1838         if ((msr & 1) == 0) {
1839                 /* MTRR base */
1840                 if (!valid_mtrr_type(data & 0xff))
1841                         return false;
1842                 mask |= 0xf00;
1843         } else
1844                 /* MTRR mask */
1845                 mask |= 0x7ff;
1846         if (data & mask) {
1847                 kvm_inject_gp(vcpu, 0);
1848                 return false;
1849         }
1850
1851         return true;
1852 }
1853 EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
1854
1855 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1856 {
1857         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1858
1859         if (!kvm_mtrr_valid(vcpu, msr, data))
1860                 return 1;
1861
1862         if (msr == MSR_MTRRdefType) {
1863                 vcpu->arch.mtrr_state.def_type = data;
1864                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1865         } else if (msr == MSR_MTRRfix64K_00000)
1866                 p[0] = data;
1867         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1868                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1869         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1870                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1871         else if (msr == MSR_IA32_CR_PAT)
1872                 vcpu->arch.pat = data;
1873         else {  /* Variable MTRRs */
1874                 int idx, is_mtrr_mask;
1875                 u64 *pt;
1876
1877                 idx = (msr - 0x200) / 2;
1878                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1879                 if (!is_mtrr_mask)
1880                         pt =
1881                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1882                 else
1883                         pt =
1884                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1885                 *pt = data;
1886         }
1887
1888         kvm_mmu_reset_context(vcpu);
1889         return 0;
1890 }
1891
1892 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1893 {
1894         u64 mcg_cap = vcpu->arch.mcg_cap;
1895         unsigned bank_num = mcg_cap & 0xff;
1896
1897         switch (msr) {
1898         case MSR_IA32_MCG_STATUS:
1899                 vcpu->arch.mcg_status = data;
1900                 break;
1901         case MSR_IA32_MCG_CTL:
1902                 if (!(mcg_cap & MCG_CTL_P))
1903                         return 1;
1904                 if (data != 0 && data != ~(u64)0)
1905                         return -1;
1906                 vcpu->arch.mcg_ctl = data;
1907                 break;
1908         default:
1909                 if (msr >= MSR_IA32_MC0_CTL &&
1910                     msr < MSR_IA32_MCx_CTL(bank_num)) {
1911                         u32 offset = msr - MSR_IA32_MC0_CTL;
1912                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1913                          * some Linux kernels though clear bit 10 in bank 4 to
1914                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1915                          * this to avoid an uncatched #GP in the guest
1916                          */
1917                         if ((offset & 0x3) == 0 &&
1918                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1919                                 return -1;
1920                         vcpu->arch.mce_banks[offset] = data;
1921                         break;
1922                 }
1923                 return 1;
1924         }
1925         return 0;
1926 }
1927
1928 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1929 {
1930         struct kvm *kvm = vcpu->kvm;
1931         int lm = is_long_mode(vcpu);
1932         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1933                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1934         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1935                 : kvm->arch.xen_hvm_config.blob_size_32;
1936         u32 page_num = data & ~PAGE_MASK;
1937         u64 page_addr = data & PAGE_MASK;
1938         u8 *page;
1939         int r;
1940
1941         r = -E2BIG;
1942         if (page_num >= blob_size)
1943                 goto out;
1944         r = -ENOMEM;
1945         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1946         if (IS_ERR(page)) {
1947                 r = PTR_ERR(page);
1948                 goto out;
1949         }
1950         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1951                 goto out_free;
1952         r = 0;
1953 out_free:
1954         kfree(page);
1955 out:
1956         return r;
1957 }
1958
1959 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1960 {
1961         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1962 }
1963
1964 static bool kvm_hv_msr_partition_wide(u32 msr)
1965 {
1966         bool r = false;
1967         switch (msr) {
1968         case HV_X64_MSR_GUEST_OS_ID:
1969         case HV_X64_MSR_HYPERCALL:
1970         case HV_X64_MSR_REFERENCE_TSC:
1971         case HV_X64_MSR_TIME_REF_COUNT:
1972                 r = true;
1973                 break;
1974         }
1975
1976         return r;
1977 }
1978
1979 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1980 {
1981         struct kvm *kvm = vcpu->kvm;
1982
1983         switch (msr) {
1984         case HV_X64_MSR_GUEST_OS_ID:
1985                 kvm->arch.hv_guest_os_id = data;
1986                 /* setting guest os id to zero disables hypercall page */
1987                 if (!kvm->arch.hv_guest_os_id)
1988                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1989                 break;
1990         case HV_X64_MSR_HYPERCALL: {
1991                 u64 gfn;
1992                 unsigned long addr;
1993                 u8 instructions[4];
1994
1995                 /* if guest os id is not set hypercall should remain disabled */
1996                 if (!kvm->arch.hv_guest_os_id)
1997                         break;
1998                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1999                         kvm->arch.hv_hypercall = data;
2000                         break;
2001                 }
2002                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
2003                 addr = gfn_to_hva(kvm, gfn);
2004                 if (kvm_is_error_hva(addr))
2005                         return 1;
2006                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
2007                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
2008                 if (__copy_to_user((void __user *)addr, instructions, 4))
2009                         return 1;
2010                 kvm->arch.hv_hypercall = data;
2011                 mark_page_dirty(kvm, gfn);
2012                 break;
2013         }
2014         case HV_X64_MSR_REFERENCE_TSC: {
2015                 u64 gfn;
2016                 HV_REFERENCE_TSC_PAGE tsc_ref;
2017                 memset(&tsc_ref, 0, sizeof(tsc_ref));
2018                 kvm->arch.hv_tsc_page = data;
2019                 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
2020                         break;
2021                 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
2022                 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
2023                         &tsc_ref, sizeof(tsc_ref)))
2024                         return 1;
2025                 mark_page_dirty(kvm, gfn);
2026                 break;
2027         }
2028         default:
2029                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2030                             "data 0x%llx\n", msr, data);
2031                 return 1;
2032         }
2033         return 0;
2034 }
2035
2036 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2037 {
2038         switch (msr) {
2039         case HV_X64_MSR_APIC_ASSIST_PAGE: {
2040                 u64 gfn;
2041                 unsigned long addr;
2042
2043                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2044                         vcpu->arch.hv_vapic = data;
2045                         if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2046                                 return 1;
2047                         break;
2048                 }
2049                 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2050                 addr = gfn_to_hva(vcpu->kvm, gfn);
2051                 if (kvm_is_error_hva(addr))
2052                         return 1;
2053                 if (__clear_user((void __user *)addr, PAGE_SIZE))
2054                         return 1;
2055                 vcpu->arch.hv_vapic = data;
2056                 mark_page_dirty(vcpu->kvm, gfn);
2057                 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2058                         return 1;
2059                 break;
2060         }
2061         case HV_X64_MSR_EOI:
2062                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2063         case HV_X64_MSR_ICR:
2064                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2065         case HV_X64_MSR_TPR:
2066                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2067         default:
2068                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2069                             "data 0x%llx\n", msr, data);
2070                 return 1;
2071         }
2072
2073         return 0;
2074 }
2075
2076 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2077 {
2078         gpa_t gpa = data & ~0x3f;
2079
2080         /* Bits 2:5 are reserved, Should be zero */
2081         if (data & 0x3c)
2082                 return 1;
2083
2084         vcpu->arch.apf.msr_val = data;
2085
2086         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2087                 kvm_clear_async_pf_completion_queue(vcpu);
2088                 kvm_async_pf_hash_reset(vcpu);
2089                 return 0;
2090         }
2091
2092         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2093                                         sizeof(u32)))
2094                 return 1;
2095
2096         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2097         kvm_async_pf_wakeup_all(vcpu);
2098         return 0;
2099 }
2100
2101 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2102 {
2103         vcpu->arch.pv_time_enabled = false;
2104 }
2105
2106 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2107 {
2108         u64 delta;
2109
2110         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2111                 return;
2112
2113         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2114         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2115         vcpu->arch.st.accum_steal = delta;
2116 }
2117
2118 static void record_steal_time(struct kvm_vcpu *vcpu)
2119 {
2120         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2121                 return;
2122
2123         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2124                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2125                 return;
2126
2127         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2128         vcpu->arch.st.steal.version += 2;
2129         vcpu->arch.st.accum_steal = 0;
2130
2131         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2132                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2133 }
2134
2135 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2136 {
2137         bool pr = false;
2138         u32 msr = msr_info->index;
2139         u64 data = msr_info->data;
2140
2141         switch (msr) {
2142         case MSR_AMD64_NB_CFG:
2143         case MSR_IA32_UCODE_REV:
2144         case MSR_IA32_UCODE_WRITE:
2145         case MSR_VM_HSAVE_PA:
2146         case MSR_AMD64_PATCH_LOADER:
2147         case MSR_AMD64_BU_CFG2:
2148                 break;
2149
2150         case MSR_EFER:
2151                 return set_efer(vcpu, data);
2152         case MSR_K7_HWCR:
2153                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2154                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2155                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2156                 data &= ~(u64)0x40000;  /* ignore Mc status write enable */
2157                 if (data != 0) {
2158                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2159                                     data);
2160                         return 1;
2161                 }
2162                 break;
2163         case MSR_FAM10H_MMIO_CONF_BASE:
2164                 if (data != 0) {
2165                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2166                                     "0x%llx\n", data);
2167                         return 1;
2168                 }
2169                 break;
2170         case MSR_IA32_DEBUGCTLMSR:
2171                 if (!data) {
2172                         /* We support the non-activated case already */
2173                         break;
2174                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2175                         /* Values other than LBR and BTF are vendor-specific,
2176                            thus reserved and should throw a #GP */
2177                         return 1;
2178                 }
2179                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2180                             __func__, data);
2181                 break;
2182         case 0x200 ... 0x2ff:
2183                 return set_msr_mtrr(vcpu, msr, data);
2184         case MSR_IA32_APICBASE:
2185                 return kvm_set_apic_base(vcpu, msr_info);
2186         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2187                 return kvm_x2apic_msr_write(vcpu, msr, data);
2188         case MSR_IA32_TSCDEADLINE:
2189                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2190                 break;
2191         case MSR_IA32_TSC_ADJUST:
2192                 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2193                         if (!msr_info->host_initiated) {
2194                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2195                                 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2196                         }
2197                         vcpu->arch.ia32_tsc_adjust_msr = data;
2198                 }
2199                 break;
2200         case MSR_IA32_MISC_ENABLE:
2201                 vcpu->arch.ia32_misc_enable_msr = data;
2202                 break;
2203         case MSR_KVM_WALL_CLOCK_NEW:
2204         case MSR_KVM_WALL_CLOCK:
2205                 vcpu->kvm->arch.wall_clock = data;
2206                 kvm_write_wall_clock(vcpu->kvm, data);
2207                 break;
2208         case MSR_KVM_SYSTEM_TIME_NEW:
2209         case MSR_KVM_SYSTEM_TIME: {
2210                 u64 gpa_offset;
2211                 struct kvm_arch *ka = &vcpu->kvm->arch;
2212
2213                 kvmclock_reset(vcpu);
2214
2215                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2216                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2217
2218                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2219                                 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2220                                         &vcpu->requests);
2221
2222                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2223                 }
2224
2225                 vcpu->arch.time = data;
2226                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2227
2228                 /* we verify if the enable bit is set... */
2229                 if (!(data & 1))
2230                         break;
2231
2232                 gpa_offset = data & ~(PAGE_MASK | 1);
2233
2234                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2235                      &vcpu->arch.pv_time, data & ~1ULL,
2236                      sizeof(struct pvclock_vcpu_time_info)))
2237                         vcpu->arch.pv_time_enabled = false;
2238                 else
2239                         vcpu->arch.pv_time_enabled = true;
2240
2241                 break;
2242         }
2243         case MSR_KVM_ASYNC_PF_EN:
2244                 if (kvm_pv_enable_async_pf(vcpu, data))
2245                         return 1;
2246                 break;
2247         case MSR_KVM_STEAL_TIME:
2248
2249                 if (unlikely(!sched_info_on()))
2250                         return 1;
2251
2252                 if (data & KVM_STEAL_RESERVED_MASK)
2253                         return 1;
2254
2255                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2256                                                 data & KVM_STEAL_VALID_BITS,
2257                                                 sizeof(struct kvm_steal_time)))
2258                         return 1;
2259
2260                 vcpu->arch.st.msr_val = data;
2261
2262                 if (!(data & KVM_MSR_ENABLED))
2263                         break;
2264
2265                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2266
2267                 preempt_disable();
2268                 accumulate_steal_time(vcpu);
2269                 preempt_enable();
2270
2271                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2272
2273                 break;
2274         case MSR_KVM_PV_EOI_EN:
2275                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2276                         return 1;
2277                 break;
2278
2279         case MSR_IA32_MCG_CTL:
2280         case MSR_IA32_MCG_STATUS:
2281         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2282                 return set_msr_mce(vcpu, msr, data);
2283
2284         /* Performance counters are not protected by a CPUID bit,
2285          * so we should check all of them in the generic path for the sake of
2286          * cross vendor migration.
2287          * Writing a zero into the event select MSRs disables them,
2288          * which we perfectly emulate ;-). Any other value should be at least
2289          * reported, some guests depend on them.
2290          */
2291         case MSR_K7_EVNTSEL0:
2292         case MSR_K7_EVNTSEL1:
2293         case MSR_K7_EVNTSEL2:
2294         case MSR_K7_EVNTSEL3:
2295                 if (data != 0)
2296                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2297                                     "0x%x data 0x%llx\n", msr, data);
2298                 break;
2299         /* at least RHEL 4 unconditionally writes to the perfctr registers,
2300          * so we ignore writes to make it happy.
2301          */
2302         case MSR_K7_PERFCTR0:
2303         case MSR_K7_PERFCTR1:
2304         case MSR_K7_PERFCTR2:
2305         case MSR_K7_PERFCTR3:
2306                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2307                             "0x%x data 0x%llx\n", msr, data);
2308                 break;
2309         case MSR_P6_PERFCTR0:
2310         case MSR_P6_PERFCTR1:
2311                 pr = true;
2312         case MSR_P6_EVNTSEL0:
2313         case MSR_P6_EVNTSEL1:
2314                 if (kvm_pmu_msr(vcpu, msr))
2315                         return kvm_pmu_set_msr(vcpu, msr_info);
2316
2317                 if (pr || data != 0)
2318                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2319                                     "0x%x data 0x%llx\n", msr, data);
2320                 break;
2321         case MSR_K7_CLK_CTL:
2322                 /*
2323                  * Ignore all writes to this no longer documented MSR.
2324                  * Writes are only relevant for old K7 processors,
2325                  * all pre-dating SVM, but a recommended workaround from
2326                  * AMD for these chips. It is possible to specify the
2327                  * affected processor models on the command line, hence
2328                  * the need to ignore the workaround.
2329                  */
2330                 break;
2331         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2332                 if (kvm_hv_msr_partition_wide(msr)) {
2333                         int r;
2334                         mutex_lock(&vcpu->kvm->lock);
2335                         r = set_msr_hyperv_pw(vcpu, msr, data);
2336                         mutex_unlock(&vcpu->kvm->lock);
2337                         return r;
2338                 } else
2339                         return set_msr_hyperv(vcpu, msr, data);
2340                 break;
2341         case MSR_IA32_BBL_CR_CTL3:
2342                 /* Drop writes to this legacy MSR -- see rdmsr
2343                  * counterpart for further detail.
2344                  */
2345                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2346                 break;
2347         case MSR_AMD64_OSVW_ID_LENGTH:
2348                 if (!guest_cpuid_has_osvw(vcpu))
2349                         return 1;
2350                 vcpu->arch.osvw.length = data;
2351                 break;
2352         case MSR_AMD64_OSVW_STATUS:
2353                 if (!guest_cpuid_has_osvw(vcpu))
2354                         return 1;
2355                 vcpu->arch.osvw.status = data;
2356                 break;
2357         default:
2358                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2359                         return xen_hvm_config(vcpu, data);
2360                 if (kvm_pmu_msr(vcpu, msr))
2361                         return kvm_pmu_set_msr(vcpu, msr_info);
2362                 if (!ignore_msrs) {
2363                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2364                                     msr, data);
2365                         return 1;
2366                 } else {
2367                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2368                                     msr, data);
2369                         break;
2370                 }
2371         }
2372         return 0;
2373 }
2374 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2375
2376
2377 /*
2378  * Reads an msr value (of 'msr_index') into 'pdata'.
2379  * Returns 0 on success, non-0 otherwise.
2380  * Assumes vcpu_load() was already called.
2381  */
2382 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2383 {
2384         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2385 }
2386 EXPORT_SYMBOL_GPL(kvm_get_msr);
2387
2388 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2389 {
2390         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2391
2392         if (!msr_mtrr_valid(msr))
2393                 return 1;
2394
2395         if (msr == MSR_MTRRdefType)
2396                 *pdata = vcpu->arch.mtrr_state.def_type +
2397                          (vcpu->arch.mtrr_state.enabled << 10);
2398         else if (msr == MSR_MTRRfix64K_00000)
2399                 *pdata = p[0];
2400         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2401                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2402         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2403                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2404         else if (msr == MSR_IA32_CR_PAT)
2405                 *pdata = vcpu->arch.pat;
2406         else {  /* Variable MTRRs */
2407                 int idx, is_mtrr_mask;
2408                 u64 *pt;
2409
2410                 idx = (msr - 0x200) / 2;
2411                 is_mtrr_mask = msr - 0x200 - 2 * idx;
2412                 if (!is_mtrr_mask)
2413                         pt =
2414                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2415                 else
2416                         pt =
2417                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2418                 *pdata = *pt;
2419         }
2420
2421         return 0;
2422 }
2423
2424 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2425 {
2426         u64 data;
2427         u64 mcg_cap = vcpu->arch.mcg_cap;
2428         unsigned bank_num = mcg_cap & 0xff;
2429
2430         switch (msr) {
2431         case MSR_IA32_P5_MC_ADDR:
2432         case MSR_IA32_P5_MC_TYPE:
2433                 data = 0;
2434                 break;
2435         case MSR_IA32_MCG_CAP:
2436                 data = vcpu->arch.mcg_cap;
2437                 break;
2438         case MSR_IA32_MCG_CTL:
2439                 if (!(mcg_cap & MCG_CTL_P))
2440                         return 1;
2441                 data = vcpu->arch.mcg_ctl;
2442                 break;
2443         case MSR_IA32_MCG_STATUS:
2444                 data = vcpu->arch.mcg_status;
2445                 break;
2446         default:
2447                 if (msr >= MSR_IA32_MC0_CTL &&
2448                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2449                         u32 offset = msr - MSR_IA32_MC0_CTL;
2450                         data = vcpu->arch.mce_banks[offset];
2451                         break;
2452                 }
2453                 return 1;
2454         }
2455         *pdata = data;
2456         return 0;
2457 }
2458
2459 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2460 {
2461         u64 data = 0;
2462         struct kvm *kvm = vcpu->kvm;
2463
2464         switch (msr) {
2465         case HV_X64_MSR_GUEST_OS_ID:
2466                 data = kvm->arch.hv_guest_os_id;
2467                 break;
2468         case HV_X64_MSR_HYPERCALL:
2469                 data = kvm->arch.hv_hypercall;
2470                 break;
2471         case HV_X64_MSR_TIME_REF_COUNT: {
2472                 data =
2473                      div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2474                 break;
2475         }
2476         case HV_X64_MSR_REFERENCE_TSC:
2477                 data = kvm->arch.hv_tsc_page;
2478                 break;
2479         default:
2480                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2481                 return 1;
2482         }
2483
2484         *pdata = data;
2485         return 0;
2486 }
2487
2488 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2489 {
2490         u64 data = 0;
2491
2492         switch (msr) {
2493         case HV_X64_MSR_VP_INDEX: {
2494                 int r;
2495                 struct kvm_vcpu *v;
2496                 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2497                         if (v == vcpu) {
2498                                 data = r;
2499                                 break;
2500                         }
2501                 }
2502                 break;
2503         }
2504         case HV_X64_MSR_EOI:
2505                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2506         case HV_X64_MSR_ICR:
2507                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2508         case HV_X64_MSR_TPR:
2509                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2510         case HV_X64_MSR_APIC_ASSIST_PAGE:
2511                 data = vcpu->arch.hv_vapic;
2512                 break;
2513         default:
2514                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2515                 return 1;
2516         }
2517         *pdata = data;
2518         return 0;
2519 }
2520
2521 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2522 {
2523         u64 data;
2524
2525         switch (msr) {
2526         case MSR_IA32_PLATFORM_ID:
2527         case MSR_IA32_EBL_CR_POWERON:
2528         case MSR_IA32_DEBUGCTLMSR:
2529         case MSR_IA32_LASTBRANCHFROMIP:
2530         case MSR_IA32_LASTBRANCHTOIP:
2531         case MSR_IA32_LASTINTFROMIP:
2532         case MSR_IA32_LASTINTTOIP:
2533         case MSR_K8_SYSCFG:
2534         case MSR_K7_HWCR:
2535         case MSR_VM_HSAVE_PA:
2536         case MSR_K7_EVNTSEL0:
2537         case MSR_K7_EVNTSEL1:
2538         case MSR_K7_EVNTSEL2:
2539         case MSR_K7_EVNTSEL3:
2540         case MSR_K7_PERFCTR0:
2541         case MSR_K7_PERFCTR1:
2542         case MSR_K7_PERFCTR2:
2543         case MSR_K7_PERFCTR3:
2544         case MSR_K8_INT_PENDING_MSG:
2545         case MSR_AMD64_NB_CFG:
2546         case MSR_FAM10H_MMIO_CONF_BASE:
2547         case MSR_AMD64_BU_CFG2:
2548                 data = 0;
2549                 break;
2550         case MSR_P6_PERFCTR0:
2551         case MSR_P6_PERFCTR1:
2552         case MSR_P6_EVNTSEL0:
2553         case MSR_P6_EVNTSEL1:
2554                 if (kvm_pmu_msr(vcpu, msr))
2555                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2556                 data = 0;
2557                 break;
2558         case MSR_IA32_UCODE_REV:
2559                 data = 0x100000000ULL;
2560                 break;
2561         case MSR_MTRRcap:
2562                 data = 0x500 | KVM_NR_VAR_MTRR;
2563                 break;
2564         case 0x200 ... 0x2ff:
2565                 return get_msr_mtrr(vcpu, msr, pdata);
2566         case 0xcd: /* fsb frequency */
2567                 data = 3;
2568                 break;
2569                 /*
2570                  * MSR_EBC_FREQUENCY_ID
2571                  * Conservative value valid for even the basic CPU models.
2572                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2573                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2574                  * and 266MHz for model 3, or 4. Set Core Clock
2575                  * Frequency to System Bus Frequency Ratio to 1 (bits
2576                  * 31:24) even though these are only valid for CPU
2577                  * models > 2, however guests may end up dividing or
2578                  * multiplying by zero otherwise.
2579                  */
2580         case MSR_EBC_FREQUENCY_ID:
2581                 data = 1 << 24;
2582                 break;
2583         case MSR_IA32_APICBASE:
2584                 data = kvm_get_apic_base(vcpu);
2585                 break;
2586         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2587                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2588                 break;
2589         case MSR_IA32_TSCDEADLINE:
2590                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2591                 break;
2592         case MSR_IA32_TSC_ADJUST:
2593                 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2594                 break;
2595         case MSR_IA32_MISC_ENABLE:
2596                 data = vcpu->arch.ia32_misc_enable_msr;
2597                 break;
2598         case MSR_IA32_PERF_STATUS:
2599                 /* TSC increment by tick */
2600                 data = 1000ULL;
2601                 /* CPU multiplier */
2602                 data |= (((uint64_t)4ULL) << 40);
2603                 break;
2604         case MSR_EFER:
2605                 data = vcpu->arch.efer;
2606                 break;
2607         case MSR_KVM_WALL_CLOCK:
2608         case MSR_KVM_WALL_CLOCK_NEW:
2609                 data = vcpu->kvm->arch.wall_clock;
2610                 break;
2611         case MSR_KVM_SYSTEM_TIME:
2612         case MSR_KVM_SYSTEM_TIME_NEW:
2613                 data = vcpu->arch.time;
2614                 break;
2615         case MSR_KVM_ASYNC_PF_EN:
2616                 data = vcpu->arch.apf.msr_val;
2617                 break;
2618         case MSR_KVM_STEAL_TIME:
2619                 data = vcpu->arch.st.msr_val;
2620                 break;
2621         case MSR_KVM_PV_EOI_EN:
2622                 data = vcpu->arch.pv_eoi.msr_val;
2623                 break;
2624         case MSR_IA32_P5_MC_ADDR:
2625         case MSR_IA32_P5_MC_TYPE:
2626         case MSR_IA32_MCG_CAP:
2627         case MSR_IA32_MCG_CTL:
2628         case MSR_IA32_MCG_STATUS:
2629         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2630                 return get_msr_mce(vcpu, msr, pdata);
2631         case MSR_K7_CLK_CTL:
2632                 /*
2633                  * Provide expected ramp-up count for K7. All other
2634                  * are set to zero, indicating minimum divisors for
2635                  * every field.
2636                  *
2637                  * This prevents guest kernels on AMD host with CPU
2638                  * type 6, model 8 and higher from exploding due to
2639                  * the rdmsr failing.
2640                  */
2641                 data = 0x20000000;
2642                 break;
2643         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2644                 if (kvm_hv_msr_partition_wide(msr)) {
2645                         int r;
2646                         mutex_lock(&vcpu->kvm->lock);
2647                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2648                         mutex_unlock(&vcpu->kvm->lock);
2649                         return r;
2650                 } else
2651                         return get_msr_hyperv(vcpu, msr, pdata);
2652                 break;
2653         case MSR_IA32_BBL_CR_CTL3:
2654                 /* This legacy MSR exists but isn't fully documented in current
2655                  * silicon.  It is however accessed by winxp in very narrow
2656                  * scenarios where it sets bit #19, itself documented as
2657                  * a "reserved" bit.  Best effort attempt to source coherent
2658                  * read data here should the balance of the register be
2659                  * interpreted by the guest:
2660                  *
2661                  * L2 cache control register 3: 64GB range, 256KB size,
2662                  * enabled, latency 0x1, configured
2663                  */
2664                 data = 0xbe702111;
2665                 break;
2666         case MSR_AMD64_OSVW_ID_LENGTH:
2667                 if (!guest_cpuid_has_osvw(vcpu))
2668                         return 1;
2669                 data = vcpu->arch.osvw.length;
2670                 break;
2671         case MSR_AMD64_OSVW_STATUS:
2672                 if (!guest_cpuid_has_osvw(vcpu))
2673                         return 1;
2674                 data = vcpu->arch.osvw.status;
2675                 break;
2676         default:
2677                 if (kvm_pmu_msr(vcpu, msr))
2678                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2679                 if (!ignore_msrs) {
2680                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2681                         return 1;
2682                 } else {
2683                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2684                         data = 0;
2685                 }
2686                 break;
2687         }
2688         *pdata = data;
2689         return 0;
2690 }
2691 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2692
2693 /*
2694  * Read or write a bunch of msrs. All parameters are kernel addresses.
2695  *
2696  * @return number of msrs set successfully.
2697  */
2698 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2699                     struct kvm_msr_entry *entries,
2700                     int (*do_msr)(struct kvm_vcpu *vcpu,
2701                                   unsigned index, u64 *data))
2702 {
2703         int i, idx;
2704
2705         idx = srcu_read_lock(&vcpu->kvm->srcu);
2706         for (i = 0; i < msrs->nmsrs; ++i)
2707                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2708                         break;
2709         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2710
2711         return i;
2712 }
2713
2714 /*
2715  * Read or write a bunch of msrs. Parameters are user addresses.
2716  *
2717  * @return number of msrs set successfully.
2718  */
2719 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2720                   int (*do_msr)(struct kvm_vcpu *vcpu,
2721                                 unsigned index, u64 *data),
2722                   int writeback)
2723 {
2724         struct kvm_msrs msrs;
2725         struct kvm_msr_entry *entries;
2726         int r, n;
2727         unsigned size;
2728
2729         r = -EFAULT;
2730         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2731                 goto out;
2732
2733         r = -E2BIG;
2734         if (msrs.nmsrs >= MAX_IO_MSRS)
2735                 goto out;
2736
2737         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2738         entries = memdup_user(user_msrs->entries, size);
2739         if (IS_ERR(entries)) {
2740                 r = PTR_ERR(entries);
2741                 goto out;
2742         }
2743
2744         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2745         if (r < 0)
2746                 goto out_free;
2747
2748         r = -EFAULT;
2749         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2750                 goto out_free;
2751
2752         r = n;
2753
2754 out_free:
2755         kfree(entries);
2756 out:
2757         return r;
2758 }
2759
2760 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2761 {
2762         int r;
2763
2764         switch (ext) {
2765         case KVM_CAP_IRQCHIP:
2766         case KVM_CAP_HLT:
2767         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2768         case KVM_CAP_SET_TSS_ADDR:
2769         case KVM_CAP_EXT_CPUID:
2770         case KVM_CAP_EXT_EMUL_CPUID:
2771         case KVM_CAP_CLOCKSOURCE:
2772         case KVM_CAP_PIT:
2773         case KVM_CAP_NOP_IO_DELAY:
2774         case KVM_CAP_MP_STATE:
2775         case KVM_CAP_SYNC_MMU:
2776         case KVM_CAP_USER_NMI:
2777         case KVM_CAP_REINJECT_CONTROL:
2778         case KVM_CAP_IRQ_INJECT_STATUS:
2779         case KVM_CAP_IOEVENTFD:
2780         case KVM_CAP_IOEVENTFD_NO_LENGTH:
2781         case KVM_CAP_PIT2:
2782         case KVM_CAP_PIT_STATE2:
2783         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2784         case KVM_CAP_XEN_HVM:
2785         case KVM_CAP_ADJUST_CLOCK:
2786         case KVM_CAP_VCPU_EVENTS:
2787         case KVM_CAP_HYPERV:
2788         case KVM_CAP_HYPERV_VAPIC:
2789         case KVM_CAP_HYPERV_SPIN:
2790         case KVM_CAP_PCI_SEGMENT:
2791         case KVM_CAP_DEBUGREGS:
2792         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2793         case KVM_CAP_XSAVE:
2794         case KVM_CAP_ASYNC_PF:
2795         case KVM_CAP_GET_TSC_KHZ:
2796         case KVM_CAP_KVMCLOCK_CTRL:
2797         case KVM_CAP_READONLY_MEM:
2798         case KVM_CAP_HYPERV_TIME:
2799         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2800         case KVM_CAP_TSC_DEADLINE_TIMER:
2801 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2802         case KVM_CAP_ASSIGN_DEV_IRQ:
2803         case KVM_CAP_PCI_2_3:
2804 #endif
2805                 r = 1;
2806                 break;
2807         case KVM_CAP_COALESCED_MMIO:
2808                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2809                 break;
2810         case KVM_CAP_VAPIC:
2811                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2812                 break;
2813         case KVM_CAP_NR_VCPUS:
2814                 r = KVM_SOFT_MAX_VCPUS;
2815                 break;
2816         case KVM_CAP_MAX_VCPUS:
2817                 r = KVM_MAX_VCPUS;
2818                 break;
2819         case KVM_CAP_NR_MEMSLOTS:
2820                 r = KVM_USER_MEM_SLOTS;
2821                 break;
2822         case KVM_CAP_PV_MMU:    /* obsolete */
2823                 r = 0;
2824                 break;
2825 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2826         case KVM_CAP_IOMMU:
2827                 r = iommu_present(&pci_bus_type);
2828                 break;
2829 #endif
2830         case KVM_CAP_MCE:
2831                 r = KVM_MAX_MCE_BANKS;
2832                 break;
2833         case KVM_CAP_XCRS:
2834                 r = cpu_has_xsave;
2835                 break;
2836         case KVM_CAP_TSC_CONTROL:
2837                 r = kvm_has_tsc_control;
2838                 break;
2839         default:
2840                 r = 0;
2841                 break;
2842         }
2843         return r;
2844
2845 }
2846
2847 long kvm_arch_dev_ioctl(struct file *filp,
2848                         unsigned int ioctl, unsigned long arg)
2849 {
2850         void __user *argp = (void __user *)arg;
2851         long r;
2852
2853         switch (ioctl) {
2854         case KVM_GET_MSR_INDEX_LIST: {
2855                 struct kvm_msr_list __user *user_msr_list = argp;
2856                 struct kvm_msr_list msr_list;
2857                 unsigned n;
2858
2859                 r = -EFAULT;
2860                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2861                         goto out;
2862                 n = msr_list.nmsrs;
2863                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2864                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2865                         goto out;
2866                 r = -E2BIG;
2867                 if (n < msr_list.nmsrs)
2868                         goto out;
2869                 r = -EFAULT;
2870                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2871                                  num_msrs_to_save * sizeof(u32)))
2872                         goto out;
2873                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2874                                  &emulated_msrs,
2875                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2876                         goto out;
2877                 r = 0;
2878                 break;
2879         }
2880         case KVM_GET_SUPPORTED_CPUID:
2881         case KVM_GET_EMULATED_CPUID: {
2882                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2883                 struct kvm_cpuid2 cpuid;
2884
2885                 r = -EFAULT;
2886                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2887                         goto out;
2888
2889                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2890                                             ioctl);
2891                 if (r)
2892                         goto out;
2893
2894                 r = -EFAULT;
2895                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2896                         goto out;
2897                 r = 0;
2898                 break;
2899         }
2900         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2901                 u64 mce_cap;
2902
2903                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2904                 r = -EFAULT;
2905                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2906                         goto out;
2907                 r = 0;
2908                 break;
2909         }
2910         default:
2911                 r = -EINVAL;
2912         }
2913 out:
2914         return r;
2915 }
2916
2917 static void wbinvd_ipi(void *garbage)
2918 {
2919         wbinvd();
2920 }
2921
2922 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2923 {
2924         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2925 }
2926
2927 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2928 {
2929         /* Address WBINVD may be executed by guest */
2930         if (need_emulate_wbinvd(vcpu)) {
2931                 if (kvm_x86_ops->has_wbinvd_exit())
2932                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2933                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2934                         smp_call_function_single(vcpu->cpu,
2935                                         wbinvd_ipi, NULL, 1);
2936         }
2937
2938         kvm_x86_ops->vcpu_load(vcpu, cpu);
2939
2940         /* Apply any externally detected TSC adjustments (due to suspend) */
2941         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2942                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2943                 vcpu->arch.tsc_offset_adjustment = 0;
2944                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2945         }
2946
2947         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2948                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2949                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2950                 if (tsc_delta < 0)
2951                         mark_tsc_unstable("KVM discovered backwards TSC");
2952                 if (check_tsc_unstable()) {
2953                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2954                                                 vcpu->arch.last_guest_tsc);
2955                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2956                         vcpu->arch.tsc_catchup = 1;
2957                 }
2958                 /*
2959                  * On a host with synchronized TSC, there is no need to update
2960                  * kvmclock on vcpu->cpu migration
2961                  */
2962                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2963                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2964                 if (vcpu->cpu != cpu)
2965                         kvm_migrate_timers(vcpu);
2966                 vcpu->cpu = cpu;
2967         }
2968
2969         accumulate_steal_time(vcpu);
2970         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2971 }
2972
2973 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2974 {
2975         kvm_x86_ops->vcpu_put(vcpu);
2976         kvm_put_guest_fpu(vcpu);
2977         vcpu->arch.last_host_tsc = native_read_tsc();
2978 }
2979
2980 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2981                                     struct kvm_lapic_state *s)
2982 {
2983         kvm_x86_ops->sync_pir_to_irr(vcpu);
2984         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2985
2986         return 0;
2987 }
2988
2989 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2990                                     struct kvm_lapic_state *s)
2991 {
2992         kvm_apic_post_state_restore(vcpu, s);
2993         update_cr8_intercept(vcpu);
2994
2995         return 0;
2996 }
2997
2998 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2999                                     struct kvm_interrupt *irq)
3000 {
3001         if (irq->irq >= KVM_NR_INTERRUPTS)
3002                 return -EINVAL;
3003         if (irqchip_in_kernel(vcpu->kvm))
3004                 return -ENXIO;
3005
3006         kvm_queue_interrupt(vcpu, irq->irq, false);
3007         kvm_make_request(KVM_REQ_EVENT, vcpu);
3008
3009         return 0;
3010 }
3011
3012 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3013 {
3014         kvm_inject_nmi(vcpu);
3015
3016         return 0;
3017 }
3018
3019 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3020                                            struct kvm_tpr_access_ctl *tac)
3021 {
3022         if (tac->flags)
3023                 return -EINVAL;
3024         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3025         return 0;
3026 }
3027
3028 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3029                                         u64 mcg_cap)
3030 {
3031         int r;
3032         unsigned bank_num = mcg_cap & 0xff, bank;
3033
3034         r = -EINVAL;
3035         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3036                 goto out;
3037         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3038                 goto out;
3039         r = 0;
3040         vcpu->arch.mcg_cap = mcg_cap;
3041         /* Init IA32_MCG_CTL to all 1s */
3042         if (mcg_cap & MCG_CTL_P)
3043                 vcpu->arch.mcg_ctl = ~(u64)0;
3044         /* Init IA32_MCi_CTL to all 1s */
3045         for (bank = 0; bank < bank_num; bank++)
3046                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3047 out:
3048         return r;
3049 }
3050
3051 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3052                                       struct kvm_x86_mce *mce)
3053 {
3054         u64 mcg_cap = vcpu->arch.mcg_cap;
3055         unsigned bank_num = mcg_cap & 0xff;
3056         u64 *banks = vcpu->arch.mce_banks;
3057
3058         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3059                 return -EINVAL;
3060         /*
3061          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3062          * reporting is disabled
3063          */
3064         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3065             vcpu->arch.mcg_ctl != ~(u64)0)
3066                 return 0;
3067         banks += 4 * mce->bank;
3068         /*
3069          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3070          * reporting is disabled for the bank
3071          */
3072         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3073                 return 0;
3074         if (mce->status & MCI_STATUS_UC) {
3075                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3076                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3077                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3078                         return 0;
3079                 }
3080                 if (banks[1] & MCI_STATUS_VAL)
3081                         mce->status |= MCI_STATUS_OVER;
3082                 banks[2] = mce->addr;
3083                 banks[3] = mce->misc;
3084                 vcpu->arch.mcg_status = mce->mcg_status;
3085                 banks[1] = mce->status;
3086                 kvm_queue_exception(vcpu, MC_VECTOR);
3087         } else if (!(banks[1] & MCI_STATUS_VAL)
3088                    || !(banks[1] & MCI_STATUS_UC)) {
3089                 if (banks[1] & MCI_STATUS_VAL)
3090                         mce->status |= MCI_STATUS_OVER;
3091                 banks[2] = mce->addr;
3092                 banks[3] = mce->misc;
3093                 banks[1] = mce->status;
3094         } else
3095                 banks[1] |= MCI_STATUS_OVER;
3096         return 0;
3097 }
3098
3099 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3100                                                struct kvm_vcpu_events *events)
3101 {
3102         process_nmi(vcpu);
3103         events->exception.injected =
3104                 vcpu->arch.exception.pending &&
3105                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3106         events->exception.nr = vcpu->arch.exception.nr;
3107         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3108         events->exception.pad = 0;
3109         events->exception.error_code = vcpu->arch.exception.error_code;
3110
3111         events->interrupt.injected =
3112                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3113         events->interrupt.nr = vcpu->arch.interrupt.nr;
3114         events->interrupt.soft = 0;
3115         events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3116
3117         events->nmi.injected = vcpu->arch.nmi_injected;
3118         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3119         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3120         events->nmi.pad = 0;
3121
3122         events->sipi_vector = 0; /* never valid when reporting to user space */
3123
3124         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3125                          | KVM_VCPUEVENT_VALID_SHADOW);
3126         memset(&events->reserved, 0, sizeof(events->reserved));
3127 }
3128
3129 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3130                                               struct kvm_vcpu_events *events)
3131 {
3132         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3133                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3134                               | KVM_VCPUEVENT_VALID_SHADOW))
3135                 return -EINVAL;
3136
3137         process_nmi(vcpu);
3138         vcpu->arch.exception.pending = events->exception.injected;
3139         vcpu->arch.exception.nr = events->exception.nr;
3140         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3141         vcpu->arch.exception.error_code = events->exception.error_code;
3142
3143         vcpu->arch.interrupt.pending = events->interrupt.injected;
3144         vcpu->arch.interrupt.nr = events->interrupt.nr;
3145         vcpu->arch.interrupt.soft = events->interrupt.soft;
3146         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3147                 kvm_x86_ops->set_interrupt_shadow(vcpu,
3148                                                   events->interrupt.shadow);
3149
3150         vcpu->arch.nmi_injected = events->nmi.injected;
3151         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3152                 vcpu->arch.nmi_pending = events->nmi.pending;
3153         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3154
3155         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3156             kvm_vcpu_has_lapic(vcpu))
3157                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3158
3159         kvm_make_request(KVM_REQ_EVENT, vcpu);
3160
3161         return 0;
3162 }
3163
3164 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3165                                              struct kvm_debugregs *dbgregs)
3166 {
3167         unsigned long val;
3168
3169         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3170         kvm_get_dr(vcpu, 6, &val);
3171         dbgregs->dr6 = val;
3172         dbgregs->dr7 = vcpu->arch.dr7;
3173         dbgregs->flags = 0;
3174         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3175 }
3176
3177 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3178                                             struct kvm_debugregs *dbgregs)
3179 {
3180         if (dbgregs->flags)
3181                 return -EINVAL;
3182
3183         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3184         kvm_update_dr0123(vcpu);
3185         vcpu->arch.dr6 = dbgregs->dr6;
3186         kvm_update_dr6(vcpu);
3187         vcpu->arch.dr7 = dbgregs->dr7;
3188         kvm_update_dr7(vcpu);
3189
3190         return 0;
3191 }
3192
3193 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3194
3195 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3196 {
3197         struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3198         u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3199         u64 valid;
3200
3201         /*
3202          * Copy legacy XSAVE area, to avoid complications with CPUID
3203          * leaves 0 and 1 in the loop below.
3204          */
3205         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3206
3207         /* Set XSTATE_BV */
3208         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3209
3210         /*
3211          * Copy each region from the possibly compacted offset to the
3212          * non-compacted offset.
3213          */
3214         valid = xstate_bv & ~XSTATE_FPSSE;
3215         while (valid) {
3216                 u64 feature = valid & -valid;
3217                 int index = fls64(feature) - 1;
3218                 void *src = get_xsave_addr(xsave, feature);
3219
3220                 if (src) {
3221                         u32 size, offset, ecx, edx;
3222                         cpuid_count(XSTATE_CPUID, index,
3223                                     &size, &offset, &ecx, &edx);
3224                         memcpy(dest + offset, src, size);
3225                 }
3226
3227                 valid -= feature;
3228         }
3229 }
3230
3231 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3232 {
3233         struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3234         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3235         u64 valid;
3236
3237         /*
3238          * Copy legacy XSAVE area, to avoid complications with CPUID
3239          * leaves 0 and 1 in the loop below.
3240          */
3241         memcpy(xsave, src, XSAVE_HDR_OFFSET);
3242
3243         /* Set XSTATE_BV and possibly XCOMP_BV.  */
3244         xsave->xsave_hdr.xstate_bv = xstate_bv;
3245         if (cpu_has_xsaves)
3246                 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3247
3248         /*
3249          * Copy each region from the non-compacted offset to the
3250          * possibly compacted offset.
3251          */
3252         valid = xstate_bv & ~XSTATE_FPSSE;
3253         while (valid) {
3254                 u64 feature = valid & -valid;
3255                 int index = fls64(feature) - 1;
3256                 void *dest = get_xsave_addr(xsave, feature);
3257
3258                 if (dest) {
3259                         u32 size, offset, ecx, edx;
3260                         cpuid_count(XSTATE_CPUID, index,
3261                                     &size, &offset, &ecx, &edx);
3262                         memcpy(dest, src + offset, size);
3263                 } else
3264                         WARN_ON_ONCE(1);
3265
3266                 valid -= feature;
3267         }
3268 }
3269
3270 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3271                                          struct kvm_xsave *guest_xsave)
3272 {
3273         if (cpu_has_xsave) {
3274                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3275                 fill_xsave((u8 *) guest_xsave->region, vcpu);
3276         } else {
3277                 memcpy(guest_xsave->region,
3278                         &vcpu->arch.guest_fpu.state->fxsave,
3279                         sizeof(struct i387_fxsave_struct));
3280                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3281                         XSTATE_FPSSE;
3282         }
3283 }
3284
3285 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3286                                         struct kvm_xsave *guest_xsave)
3287 {
3288         u64 xstate_bv =
3289                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3290
3291         if (cpu_has_xsave) {
3292                 /*
3293                  * Here we allow setting states that are not present in
3294                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3295                  * with old userspace.
3296                  */
3297                 if (xstate_bv & ~kvm_supported_xcr0())
3298                         return -EINVAL;
3299                 load_xsave(vcpu, (u8 *)guest_xsave->region);
3300         } else {
3301                 if (xstate_bv & ~XSTATE_FPSSE)
3302                         return -EINVAL;
3303                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3304                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
3305         }
3306         return 0;
3307 }
3308
3309 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3310                                         struct kvm_xcrs *guest_xcrs)
3311 {
3312         if (!cpu_has_xsave) {
3313                 guest_xcrs->nr_xcrs = 0;
3314                 return;
3315         }
3316