KVM: x86: improve the usability of the 'kvm_pio' tracepoint
[sfrench/cifs-2.6.git] / arch / x86 / kvm / x86.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * derived from drivers/kvm/kvm_main.c
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright (C) 2008 Qumranet, Inc.
8  * Copyright IBM Corporation, 2008
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Amit Shah    <amit.shah@qumranet.com>
15  *   Ben-Ami Yassour <benami@il.ibm.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75  * - enable syscall per default because its emulated by KVM
76  * - enable LME and LMA per default on 64 bit KVM
77  */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 unsigned int min_timer_period_us = 500;
98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32  kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
109 #define KVM_NR_SHARED_MSRS 16
110
111 struct kvm_shared_msrs_global {
112         int nr;
113         u32 msrs[KVM_NR_SHARED_MSRS];
114 };
115
116 struct kvm_shared_msrs {
117         struct user_return_notifier urn;
118         bool registered;
119         struct kvm_shared_msr_values {
120                 u64 host;
121                 u64 curr;
122         } values[KVM_NR_SHARED_MSRS];
123 };
124
125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
126 static struct kvm_shared_msrs __percpu *shared_msrs;
127
128 struct kvm_stats_debugfs_item debugfs_entries[] = {
129         { "pf_fixed", VCPU_STAT(pf_fixed) },
130         { "pf_guest", VCPU_STAT(pf_guest) },
131         { "tlb_flush", VCPU_STAT(tlb_flush) },
132         { "invlpg", VCPU_STAT(invlpg) },
133         { "exits", VCPU_STAT(exits) },
134         { "io_exits", VCPU_STAT(io_exits) },
135         { "mmio_exits", VCPU_STAT(mmio_exits) },
136         { "signal_exits", VCPU_STAT(signal_exits) },
137         { "irq_window", VCPU_STAT(irq_window_exits) },
138         { "nmi_window", VCPU_STAT(nmi_window_exits) },
139         { "halt_exits", VCPU_STAT(halt_exits) },
140         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
141         { "hypercalls", VCPU_STAT(hypercalls) },
142         { "request_irq", VCPU_STAT(request_irq_exits) },
143         { "irq_exits", VCPU_STAT(irq_exits) },
144         { "host_state_reload", VCPU_STAT(host_state_reload) },
145         { "efer_reload", VCPU_STAT(efer_reload) },
146         { "fpu_reload", VCPU_STAT(fpu_reload) },
147         { "insn_emulation", VCPU_STAT(insn_emulation) },
148         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
149         { "irq_injections", VCPU_STAT(irq_injections) },
150         { "nmi_injections", VCPU_STAT(nmi_injections) },
151         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155         { "mmu_flooded", VM_STAT(mmu_flooded) },
156         { "mmu_recycled", VM_STAT(mmu_recycled) },
157         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
158         { "mmu_unsync", VM_STAT(mmu_unsync) },
159         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
160         { "largepages", VM_STAT(lpages) },
161         { NULL }
162 };
163
164 u64 __read_mostly host_xcr0;
165
166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
167
168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169 {
170         int i;
171         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172                 vcpu->arch.apf.gfns[i] = ~0;
173 }
174
175 static void kvm_on_user_return(struct user_return_notifier *urn)
176 {
177         unsigned slot;
178         struct kvm_shared_msrs *locals
179                 = container_of(urn, struct kvm_shared_msrs, urn);
180         struct kvm_shared_msr_values *values;
181
182         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
183                 values = &locals->values[slot];
184                 if (values->host != values->curr) {
185                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
186                         values->curr = values->host;
187                 }
188         }
189         locals->registered = false;
190         user_return_notifier_unregister(urn);
191 }
192
193 static void shared_msr_update(unsigned slot, u32 msr)
194 {
195         u64 value;
196         unsigned int cpu = smp_processor_id();
197         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
198
199         /* only read, and nobody should modify it at this time,
200          * so don't need lock */
201         if (slot >= shared_msrs_global.nr) {
202                 printk(KERN_ERR "kvm: invalid MSR slot!");
203                 return;
204         }
205         rdmsrl_safe(msr, &value);
206         smsr->values[slot].host = value;
207         smsr->values[slot].curr = value;
208 }
209
210 void kvm_define_shared_msr(unsigned slot, u32 msr)
211 {
212         if (slot >= shared_msrs_global.nr)
213                 shared_msrs_global.nr = slot + 1;
214         shared_msrs_global.msrs[slot] = msr;
215         /* we need ensured the shared_msr_global have been updated */
216         smp_wmb();
217 }
218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220 static void kvm_shared_msr_cpu_online(void)
221 {
222         unsigned i;
223
224         for (i = 0; i < shared_msrs_global.nr; ++i)
225                 shared_msr_update(i, shared_msrs_global.msrs[i]);
226 }
227
228 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
229 {
230         unsigned int cpu = smp_processor_id();
231         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
232
233         if (((value ^ smsr->values[slot].curr) & mask) == 0)
234                 return;
235         smsr->values[slot].curr = value;
236         wrmsrl(shared_msrs_global.msrs[slot], value);
237         if (!smsr->registered) {
238                 smsr->urn.on_user_return = kvm_on_user_return;
239                 user_return_notifier_register(&smsr->urn);
240                 smsr->registered = true;
241         }
242 }
243 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
245 static void drop_user_return_notifiers(void *ignore)
246 {
247         unsigned int cpu = smp_processor_id();
248         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
249
250         if (smsr->registered)
251                 kvm_on_user_return(&smsr->urn);
252 }
253
254 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255 {
256         return vcpu->arch.apic_base;
257 }
258 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
260 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261 {
262         u64 old_state = vcpu->arch.apic_base &
263                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264         u64 new_state = msr_info->data &
265                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267                 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269         if (!msr_info->host_initiated &&
270             ((msr_info->data & reserved_bits) != 0 ||
271              new_state == X2APIC_ENABLE ||
272              (new_state == MSR_IA32_APICBASE_ENABLE &&
273               old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274              (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275               old_state == 0)))
276                 return 1;
277
278         kvm_lapic_set_base(vcpu, msr_info->data);
279         return 0;
280 }
281 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
283 asmlinkage void kvm_spurious_fault(void)
284 {
285         /* Fault while not rebooting.  We want the trace. */
286         BUG();
287 }
288 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
290 #define EXCPT_BENIGN            0
291 #define EXCPT_CONTRIBUTORY      1
292 #define EXCPT_PF                2
293
294 static int exception_class(int vector)
295 {
296         switch (vector) {
297         case PF_VECTOR:
298                 return EXCPT_PF;
299         case DE_VECTOR:
300         case TS_VECTOR:
301         case NP_VECTOR:
302         case SS_VECTOR:
303         case GP_VECTOR:
304                 return EXCPT_CONTRIBUTORY;
305         default:
306                 break;
307         }
308         return EXCPT_BENIGN;
309 }
310
311 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
312                 unsigned nr, bool has_error, u32 error_code,
313                 bool reinject)
314 {
315         u32 prev_nr;
316         int class1, class2;
317
318         kvm_make_request(KVM_REQ_EVENT, vcpu);
319
320         if (!vcpu->arch.exception.pending) {
321         queue:
322                 vcpu->arch.exception.pending = true;
323                 vcpu->arch.exception.has_error_code = has_error;
324                 vcpu->arch.exception.nr = nr;
325                 vcpu->arch.exception.error_code = error_code;
326                 vcpu->arch.exception.reinject = reinject;
327                 return;
328         }
329
330         /* to check exception */
331         prev_nr = vcpu->arch.exception.nr;
332         if (prev_nr == DF_VECTOR) {
333                 /* triple fault -> shutdown */
334                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
335                 return;
336         }
337         class1 = exception_class(prev_nr);
338         class2 = exception_class(nr);
339         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341                 /* generate double fault per SDM Table 5-5 */
342                 vcpu->arch.exception.pending = true;
343                 vcpu->arch.exception.has_error_code = true;
344                 vcpu->arch.exception.nr = DF_VECTOR;
345                 vcpu->arch.exception.error_code = 0;
346         } else
347                 /* replace previous exception with a new one in a hope
348                    that instruction re-execution will regenerate lost
349                    exception */
350                 goto queue;
351 }
352
353 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354 {
355         kvm_multiple_exception(vcpu, nr, false, 0, false);
356 }
357 EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
359 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360 {
361         kvm_multiple_exception(vcpu, nr, false, 0, true);
362 }
363 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
365 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
366 {
367         if (err)
368                 kvm_inject_gp(vcpu, 0);
369         else
370                 kvm_x86_ops->skip_emulated_instruction(vcpu);
371 }
372 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
373
374 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
375 {
376         ++vcpu->stat.pf_guest;
377         vcpu->arch.cr2 = fault->address;
378         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
379 }
380 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
381
382 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
383 {
384         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
386         else
387                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
388 }
389
390 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391 {
392         atomic_inc(&vcpu->arch.nmi_queued);
393         kvm_make_request(KVM_REQ_NMI, vcpu);
394 }
395 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
397 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398 {
399         kvm_multiple_exception(vcpu, nr, true, error_code, false);
400 }
401 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
403 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404 {
405         kvm_multiple_exception(vcpu, nr, true, error_code, true);
406 }
407 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
409 /*
410  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
411  * a #GP and return false.
412  */
413 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
414 {
415         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416                 return true;
417         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418         return false;
419 }
420 EXPORT_SYMBOL_GPL(kvm_require_cpl);
421
422 /*
423  * This function will be used to read from the physical memory of the currently
424  * running guest. The difference to kvm_read_guest_page is that this function
425  * can read from guest physical or from the guest's guest physical memory.
426  */
427 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428                             gfn_t ngfn, void *data, int offset, int len,
429                             u32 access)
430 {
431         gfn_t real_gfn;
432         gpa_t ngpa;
433
434         ngpa     = gfn_to_gpa(ngfn);
435         real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436         if (real_gfn == UNMAPPED_GVA)
437                 return -EFAULT;
438
439         real_gfn = gpa_to_gfn(real_gfn);
440
441         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442 }
443 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
445 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446                                void *data, int offset, int len, u32 access)
447 {
448         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449                                        data, offset, len, access);
450 }
451
452 /*
453  * Load the pae pdptrs.  Return true is they are all valid.
454  */
455 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
456 {
457         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459         int i;
460         int ret;
461         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
462
463         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464                                       offset * sizeof(u64), sizeof(pdpte),
465                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
466         if (ret < 0) {
467                 ret = 0;
468                 goto out;
469         }
470         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
471                 if (is_present_gpte(pdpte[i]) &&
472                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
473                         ret = 0;
474                         goto out;
475                 }
476         }
477         ret = 1;
478
479         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
480         __set_bit(VCPU_EXREG_PDPTR,
481                   (unsigned long *)&vcpu->arch.regs_avail);
482         __set_bit(VCPU_EXREG_PDPTR,
483                   (unsigned long *)&vcpu->arch.regs_dirty);
484 out:
485
486         return ret;
487 }
488 EXPORT_SYMBOL_GPL(load_pdptrs);
489
490 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491 {
492         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
493         bool changed = true;
494         int offset;
495         gfn_t gfn;
496         int r;
497
498         if (is_long_mode(vcpu) || !is_pae(vcpu))
499                 return false;
500
501         if (!test_bit(VCPU_EXREG_PDPTR,
502                       (unsigned long *)&vcpu->arch.regs_avail))
503                 return true;
504
505         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
507         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
509         if (r < 0)
510                 goto out;
511         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
512 out:
513
514         return changed;
515 }
516
517 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
518 {
519         unsigned long old_cr0 = kvm_read_cr0(vcpu);
520         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521                                     X86_CR0_CD | X86_CR0_NW;
522
523         cr0 |= X86_CR0_ET;
524
525 #ifdef CONFIG_X86_64
526         if (cr0 & 0xffffffff00000000UL)
527                 return 1;
528 #endif
529
530         cr0 &= ~CR0_RESERVED_BITS;
531
532         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533                 return 1;
534
535         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536                 return 1;
537
538         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539 #ifdef CONFIG_X86_64
540                 if ((vcpu->arch.efer & EFER_LME)) {
541                         int cs_db, cs_l;
542
543                         if (!is_pae(vcpu))
544                                 return 1;
545                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
546                         if (cs_l)
547                                 return 1;
548                 } else
549 #endif
550                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
551                                                  kvm_read_cr3(vcpu)))
552                         return 1;
553         }
554
555         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556                 return 1;
557
558         kvm_x86_ops->set_cr0(vcpu, cr0);
559
560         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
561                 kvm_clear_async_pf_completion_queue(vcpu);
562                 kvm_async_pf_hash_reset(vcpu);
563         }
564
565         if ((cr0 ^ old_cr0) & update_bits)
566                 kvm_mmu_reset_context(vcpu);
567         return 0;
568 }
569 EXPORT_SYMBOL_GPL(kvm_set_cr0);
570
571 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
572 {
573         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
574 }
575 EXPORT_SYMBOL_GPL(kvm_lmsw);
576
577 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578 {
579         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580                         !vcpu->guest_xcr0_loaded) {
581                 /* kvm_set_xcr() also depends on this */
582                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583                 vcpu->guest_xcr0_loaded = 1;
584         }
585 }
586
587 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588 {
589         if (vcpu->guest_xcr0_loaded) {
590                 if (vcpu->arch.xcr0 != host_xcr0)
591                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592                 vcpu->guest_xcr0_loaded = 0;
593         }
594 }
595
596 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597 {
598         u64 xcr0 = xcr;
599         u64 old_xcr0 = vcpu->arch.xcr0;
600         u64 valid_bits;
601
602         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
603         if (index != XCR_XFEATURE_ENABLED_MASK)
604                 return 1;
605         if (!(xcr0 & XSTATE_FP))
606                 return 1;
607         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608                 return 1;
609
610         /*
611          * Do not allow the guest to set bits that we do not support
612          * saving.  However, xcr0 bit 0 is always set, even if the
613          * emulated CPU does not support XSAVE (see fx_init).
614          */
615         valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616         if (xcr0 & ~valid_bits)
617                 return 1;
618
619         if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
620                 return 1;
621
622         kvm_put_guest_xcr0(vcpu);
623         vcpu->arch.xcr0 = xcr0;
624
625         if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
626                 kvm_update_cpuid(vcpu);
627         return 0;
628 }
629
630 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
631 {
632         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
633             __kvm_set_xcr(vcpu, index, xcr)) {
634                 kvm_inject_gp(vcpu, 0);
635                 return 1;
636         }
637         return 0;
638 }
639 EXPORT_SYMBOL_GPL(kvm_set_xcr);
640
641 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
642 {
643         unsigned long old_cr4 = kvm_read_cr4(vcpu);
644         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
645                                    X86_CR4_PAE | X86_CR4_SMEP;
646         if (cr4 & CR4_RESERVED_BITS)
647                 return 1;
648
649         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
650                 return 1;
651
652         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
653                 return 1;
654
655         if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
656                 return 1;
657
658         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
659                 return 1;
660
661         if (is_long_mode(vcpu)) {
662                 if (!(cr4 & X86_CR4_PAE))
663                         return 1;
664         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
665                    && ((cr4 ^ old_cr4) & pdptr_bits)
666                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
667                                    kvm_read_cr3(vcpu)))
668                 return 1;
669
670         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
671                 if (!guest_cpuid_has_pcid(vcpu))
672                         return 1;
673
674                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
675                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
676                         return 1;
677         }
678
679         if (kvm_x86_ops->set_cr4(vcpu, cr4))
680                 return 1;
681
682         if (((cr4 ^ old_cr4) & pdptr_bits) ||
683             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
684                 kvm_mmu_reset_context(vcpu);
685
686         if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
687                 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
688
689         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
690                 kvm_update_cpuid(vcpu);
691
692         return 0;
693 }
694 EXPORT_SYMBOL_GPL(kvm_set_cr4);
695
696 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
697 {
698         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
699                 kvm_mmu_sync_roots(vcpu);
700                 kvm_mmu_flush_tlb(vcpu);
701                 return 0;
702         }
703
704         if (is_long_mode(vcpu) && (cr3 & CR3_L_MODE_RESERVED_BITS))
705                 return 1;
706         if (is_pae(vcpu) && is_paging(vcpu) &&
707             !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
708                 return 1;
709
710         vcpu->arch.cr3 = cr3;
711         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
712         kvm_mmu_new_cr3(vcpu);
713         return 0;
714 }
715 EXPORT_SYMBOL_GPL(kvm_set_cr3);
716
717 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
718 {
719         if (cr8 & CR8_RESERVED_BITS)
720                 return 1;
721         if (irqchip_in_kernel(vcpu->kvm))
722                 kvm_lapic_set_tpr(vcpu, cr8);
723         else
724                 vcpu->arch.cr8 = cr8;
725         return 0;
726 }
727 EXPORT_SYMBOL_GPL(kvm_set_cr8);
728
729 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
730 {
731         if (irqchip_in_kernel(vcpu->kvm))
732                 return kvm_lapic_get_cr8(vcpu);
733         else
734                 return vcpu->arch.cr8;
735 }
736 EXPORT_SYMBOL_GPL(kvm_get_cr8);
737
738 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
739 {
740         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
741                 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
742 }
743
744 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
745 {
746         unsigned long dr7;
747
748         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
749                 dr7 = vcpu->arch.guest_debug_dr7;
750         else
751                 dr7 = vcpu->arch.dr7;
752         kvm_x86_ops->set_dr7(vcpu, dr7);
753         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
754         if (dr7 & DR7_BP_EN_MASK)
755                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
756 }
757
758 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
759 {
760         switch (dr) {
761         case 0 ... 3:
762                 vcpu->arch.db[dr] = val;
763                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
764                         vcpu->arch.eff_db[dr] = val;
765                 break;
766         case 4:
767                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
768                         return 1; /* #UD */
769                 /* fall through */
770         case 6:
771                 if (val & 0xffffffff00000000ULL)
772                         return -1; /* #GP */
773                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
774                 kvm_update_dr6(vcpu);
775                 break;
776         case 5:
777                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
778                         return 1; /* #UD */
779                 /* fall through */
780         default: /* 7 */
781                 if (val & 0xffffffff00000000ULL)
782                         return -1; /* #GP */
783                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
784                 kvm_update_dr7(vcpu);
785                 break;
786         }
787
788         return 0;
789 }
790
791 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
792 {
793         int res;
794
795         res = __kvm_set_dr(vcpu, dr, val);
796         if (res > 0)
797                 kvm_queue_exception(vcpu, UD_VECTOR);
798         else if (res < 0)
799                 kvm_inject_gp(vcpu, 0);
800
801         return res;
802 }
803 EXPORT_SYMBOL_GPL(kvm_set_dr);
804
805 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
806 {
807         switch (dr) {
808         case 0 ... 3:
809                 *val = vcpu->arch.db[dr];
810                 break;
811         case 4:
812                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
813                         return 1;
814                 /* fall through */
815         case 6:
816                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
817                         *val = vcpu->arch.dr6;
818                 else
819                         *val = kvm_x86_ops->get_dr6(vcpu);
820                 break;
821         case 5:
822                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
823                         return 1;
824                 /* fall through */
825         default: /* 7 */
826                 *val = vcpu->arch.dr7;
827                 break;
828         }
829
830         return 0;
831 }
832
833 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
834 {
835         if (_kvm_get_dr(vcpu, dr, val)) {
836                 kvm_queue_exception(vcpu, UD_VECTOR);
837                 return 1;
838         }
839         return 0;
840 }
841 EXPORT_SYMBOL_GPL(kvm_get_dr);
842
843 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
844 {
845         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
846         u64 data;
847         int err;
848
849         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
850         if (err)
851                 return err;
852         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
853         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
854         return err;
855 }
856 EXPORT_SYMBOL_GPL(kvm_rdpmc);
857
858 /*
859  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
860  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
861  *
862  * This list is modified at module load time to reflect the
863  * capabilities of the host cpu. This capabilities test skips MSRs that are
864  * kvm-specific. Those are put in the beginning of the list.
865  */
866
867 #define KVM_SAVE_MSRS_BEGIN     12
868 static u32 msrs_to_save[] = {
869         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
870         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
871         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
872         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
873         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
874         MSR_KVM_PV_EOI_EN,
875         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
876         MSR_STAR,
877 #ifdef CONFIG_X86_64
878         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
879 #endif
880         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
881         MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
882 };
883
884 static unsigned num_msrs_to_save;
885
886 static const u32 emulated_msrs[] = {
887         MSR_IA32_TSC_ADJUST,
888         MSR_IA32_TSCDEADLINE,
889         MSR_IA32_MISC_ENABLE,
890         MSR_IA32_MCG_STATUS,
891         MSR_IA32_MCG_CTL,
892 };
893
894 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
895 {
896         if (efer & efer_reserved_bits)
897                 return false;
898
899         if (efer & EFER_FFXSR) {
900                 struct kvm_cpuid_entry2 *feat;
901
902                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
903                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
904                         return false;
905         }
906
907         if (efer & EFER_SVME) {
908                 struct kvm_cpuid_entry2 *feat;
909
910                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
911                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
912                         return false;
913         }
914
915         return true;
916 }
917 EXPORT_SYMBOL_GPL(kvm_valid_efer);
918
919 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
920 {
921         u64 old_efer = vcpu->arch.efer;
922
923         if (!kvm_valid_efer(vcpu, efer))
924                 return 1;
925
926         if (is_paging(vcpu)
927             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
928                 return 1;
929
930         efer &= ~EFER_LMA;
931         efer |= vcpu->arch.efer & EFER_LMA;
932
933         kvm_x86_ops->set_efer(vcpu, efer);
934
935         /* Update reserved bits */
936         if ((efer ^ old_efer) & EFER_NX)
937                 kvm_mmu_reset_context(vcpu);
938
939         return 0;
940 }
941
942 void kvm_enable_efer_bits(u64 mask)
943 {
944        efer_reserved_bits &= ~mask;
945 }
946 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
947
948
949 /*
950  * Writes msr value into into the appropriate "register".
951  * Returns 0 on success, non-0 otherwise.
952  * Assumes vcpu_load() was already called.
953  */
954 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
955 {
956         return kvm_x86_ops->set_msr(vcpu, msr);
957 }
958
959 /*
960  * Adapt set_msr() to msr_io()'s calling convention
961  */
962 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
963 {
964         struct msr_data msr;
965
966         msr.data = *data;
967         msr.index = index;
968         msr.host_initiated = true;
969         return kvm_set_msr(vcpu, &msr);
970 }
971
972 #ifdef CONFIG_X86_64
973 struct pvclock_gtod_data {
974         seqcount_t      seq;
975
976         struct { /* extract of a clocksource struct */
977                 int vclock_mode;
978                 cycle_t cycle_last;
979                 cycle_t mask;
980                 u32     mult;
981                 u32     shift;
982         } clock;
983
984         /* open coded 'struct timespec' */
985         u64             monotonic_time_snsec;
986         time_t          monotonic_time_sec;
987 };
988
989 static struct pvclock_gtod_data pvclock_gtod_data;
990
991 static void update_pvclock_gtod(struct timekeeper *tk)
992 {
993         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
994
995         write_seqcount_begin(&vdata->seq);
996
997         /* copy pvclock gtod data */
998         vdata->clock.vclock_mode        = tk->clock->archdata.vclock_mode;
999         vdata->clock.cycle_last         = tk->clock->cycle_last;
1000         vdata->clock.mask               = tk->clock->mask;
1001         vdata->clock.mult               = tk->mult;
1002         vdata->clock.shift              = tk->shift;
1003
1004         vdata->monotonic_time_sec       = tk->xtime_sec
1005                                         + tk->wall_to_monotonic.tv_sec;
1006         vdata->monotonic_time_snsec     = tk->xtime_nsec
1007                                         + (tk->wall_to_monotonic.tv_nsec
1008                                                 << tk->shift);
1009         while (vdata->monotonic_time_snsec >=
1010                                         (((u64)NSEC_PER_SEC) << tk->shift)) {
1011                 vdata->monotonic_time_snsec -=
1012                                         ((u64)NSEC_PER_SEC) << tk->shift;
1013                 vdata->monotonic_time_sec++;
1014         }
1015
1016         write_seqcount_end(&vdata->seq);
1017 }
1018 #endif
1019
1020
1021 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1022 {
1023         int version;
1024         int r;
1025         struct pvclock_wall_clock wc;
1026         struct timespec boot;
1027
1028         if (!wall_clock)
1029                 return;
1030
1031         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1032         if (r)
1033                 return;
1034
1035         if (version & 1)
1036                 ++version;  /* first time write, random junk */
1037
1038         ++version;
1039
1040         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1041
1042         /*
1043          * The guest calculates current wall clock time by adding
1044          * system time (updated by kvm_guest_time_update below) to the
1045          * wall clock specified here.  guest system time equals host
1046          * system time for us, thus we must fill in host boot time here.
1047          */
1048         getboottime(&boot);
1049
1050         if (kvm->arch.kvmclock_offset) {
1051                 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1052                 boot = timespec_sub(boot, ts);
1053         }
1054         wc.sec = boot.tv_sec;
1055         wc.nsec = boot.tv_nsec;
1056         wc.version = version;
1057
1058         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1059
1060         version++;
1061         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1062 }
1063
1064 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1065 {
1066         uint32_t quotient, remainder;
1067
1068         /* Don't try to replace with do_div(), this one calculates
1069          * "(dividend << 32) / divisor" */
1070         __asm__ ( "divl %4"
1071                   : "=a" (quotient), "=d" (remainder)
1072                   : "0" (0), "1" (dividend), "r" (divisor) );
1073         return quotient;
1074 }
1075
1076 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1077                                s8 *pshift, u32 *pmultiplier)
1078 {
1079         uint64_t scaled64;
1080         int32_t  shift = 0;
1081         uint64_t tps64;
1082         uint32_t tps32;
1083
1084         tps64 = base_khz * 1000LL;
1085         scaled64 = scaled_khz * 1000LL;
1086         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1087                 tps64 >>= 1;
1088                 shift--;
1089         }
1090
1091         tps32 = (uint32_t)tps64;
1092         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1093                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1094                         scaled64 >>= 1;
1095                 else
1096                         tps32 <<= 1;
1097                 shift++;
1098         }
1099
1100         *pshift = shift;
1101         *pmultiplier = div_frac(scaled64, tps32);
1102
1103         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1104                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
1105 }
1106
1107 static inline u64 get_kernel_ns(void)
1108 {
1109         struct timespec ts;
1110
1111         ktime_get_ts(&ts);
1112         monotonic_to_bootbased(&ts);
1113         return timespec_to_ns(&ts);
1114 }
1115
1116 #ifdef CONFIG_X86_64
1117 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1118 #endif
1119
1120 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1121 unsigned long max_tsc_khz;
1122
1123 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1124 {
1125         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1126                                    vcpu->arch.virtual_tsc_shift);
1127 }
1128
1129 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1130 {
1131         u64 v = (u64)khz * (1000000 + ppm);
1132         do_div(v, 1000000);
1133         return v;
1134 }
1135
1136 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1137 {
1138         u32 thresh_lo, thresh_hi;
1139         int use_scaling = 0;
1140
1141         /* tsc_khz can be zero if TSC calibration fails */
1142         if (this_tsc_khz == 0)
1143                 return;
1144
1145         /* Compute a scale to convert nanoseconds in TSC cycles */
1146         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1147                            &vcpu->arch.virtual_tsc_shift,
1148                            &vcpu->arch.virtual_tsc_mult);
1149         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1150
1151         /*
1152          * Compute the variation in TSC rate which is acceptable
1153          * within the range of tolerance and decide if the
1154          * rate being applied is within that bounds of the hardware
1155          * rate.  If so, no scaling or compensation need be done.
1156          */
1157         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1158         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1159         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1160                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1161                 use_scaling = 1;
1162         }
1163         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1164 }
1165
1166 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1167 {
1168         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1169                                       vcpu->arch.virtual_tsc_mult,
1170                                       vcpu->arch.virtual_tsc_shift);
1171         tsc += vcpu->arch.this_tsc_write;
1172         return tsc;
1173 }
1174
1175 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1176 {
1177 #ifdef CONFIG_X86_64
1178         bool vcpus_matched;
1179         bool do_request = false;
1180         struct kvm_arch *ka = &vcpu->kvm->arch;
1181         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1182
1183         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1184                          atomic_read(&vcpu->kvm->online_vcpus));
1185
1186         if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1187                 if (!ka->use_master_clock)
1188                         do_request = 1;
1189
1190         if (!vcpus_matched && ka->use_master_clock)
1191                         do_request = 1;
1192
1193         if (do_request)
1194                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1195
1196         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1197                             atomic_read(&vcpu->kvm->online_vcpus),
1198                             ka->use_master_clock, gtod->clock.vclock_mode);
1199 #endif
1200 }
1201
1202 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1203 {
1204         u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1205         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1206 }
1207
1208 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1209 {
1210         struct kvm *kvm = vcpu->kvm;
1211         u64 offset, ns, elapsed;
1212         unsigned long flags;
1213         s64 usdiff;
1214         bool matched;
1215         u64 data = msr->data;
1216
1217         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1218         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1219         ns = get_kernel_ns();
1220         elapsed = ns - kvm->arch.last_tsc_nsec;
1221
1222         if (vcpu->arch.virtual_tsc_khz) {
1223                 int faulted = 0;
1224
1225                 /* n.b - signed multiplication and division required */
1226                 usdiff = data - kvm->arch.last_tsc_write;
1227 #ifdef CONFIG_X86_64
1228                 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1229 #else
1230                 /* do_div() only does unsigned */
1231                 asm("1: idivl %[divisor]\n"
1232                     "2: xor %%edx, %%edx\n"
1233                     "   movl $0, %[faulted]\n"
1234                     "3:\n"
1235                     ".section .fixup,\"ax\"\n"
1236                     "4: movl $1, %[faulted]\n"
1237                     "   jmp  3b\n"
1238                     ".previous\n"
1239
1240                 _ASM_EXTABLE(1b, 4b)
1241
1242                 : "=A"(usdiff), [faulted] "=r" (faulted)
1243                 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1244
1245 #endif
1246                 do_div(elapsed, 1000);
1247                 usdiff -= elapsed;
1248                 if (usdiff < 0)
1249                         usdiff = -usdiff;
1250
1251                 /* idivl overflow => difference is larger than USEC_PER_SEC */
1252                 if (faulted)
1253                         usdiff = USEC_PER_SEC;
1254         } else
1255                 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1256
1257         /*
1258          * Special case: TSC write with a small delta (1 second) of virtual
1259          * cycle time against real time is interpreted as an attempt to
1260          * synchronize the CPU.
1261          *
1262          * For a reliable TSC, we can match TSC offsets, and for an unstable
1263          * TSC, we add elapsed time in this computation.  We could let the
1264          * compensation code attempt to catch up if we fall behind, but
1265          * it's better to try to match offsets from the beginning.
1266          */
1267         if (usdiff < USEC_PER_SEC &&
1268             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1269                 if (!check_tsc_unstable()) {
1270                         offset = kvm->arch.cur_tsc_offset;
1271                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1272                 } else {
1273                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1274                         data += delta;
1275                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1276                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1277                 }
1278                 matched = true;
1279         } else {
1280                 /*
1281                  * We split periods of matched TSC writes into generations.
1282                  * For each generation, we track the original measured
1283                  * nanosecond time, offset, and write, so if TSCs are in
1284                  * sync, we can match exact offset, and if not, we can match
1285                  * exact software computation in compute_guest_tsc()
1286                  *
1287                  * These values are tracked in kvm->arch.cur_xxx variables.
1288                  */
1289                 kvm->arch.cur_tsc_generation++;
1290                 kvm->arch.cur_tsc_nsec = ns;
1291                 kvm->arch.cur_tsc_write = data;
1292                 kvm->arch.cur_tsc_offset = offset;
1293                 matched = false;
1294                 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1295                          kvm->arch.cur_tsc_generation, data);
1296         }
1297
1298         /*
1299          * We also track th most recent recorded KHZ, write and time to
1300          * allow the matching interval to be extended at each write.
1301          */
1302         kvm->arch.last_tsc_nsec = ns;
1303         kvm->arch.last_tsc_write = data;
1304         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1305
1306         vcpu->arch.last_guest_tsc = data;
1307
1308         /* Keep track of which generation this VCPU has synchronized to */
1309         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1310         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1311         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1312
1313         if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1314                 update_ia32_tsc_adjust_msr(vcpu, offset);
1315         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1316         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1317
1318         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1319         if (matched)
1320                 kvm->arch.nr_vcpus_matched_tsc++;
1321         else
1322                 kvm->arch.nr_vcpus_matched_tsc = 0;
1323
1324         kvm_track_tsc_matching(vcpu);
1325         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1326 }
1327
1328 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1329
1330 #ifdef CONFIG_X86_64
1331
1332 static cycle_t read_tsc(void)
1333 {
1334         cycle_t ret;
1335         u64 last;
1336
1337         /*
1338          * Empirically, a fence (of type that depends on the CPU)
1339          * before rdtsc is enough to ensure that rdtsc is ordered
1340          * with respect to loads.  The various CPU manuals are unclear
1341          * as to whether rdtsc can be reordered with later loads,
1342          * but no one has ever seen it happen.
1343          */
1344         rdtsc_barrier();
1345         ret = (cycle_t)vget_cycles();
1346
1347         last = pvclock_gtod_data.clock.cycle_last;
1348
1349         if (likely(ret >= last))
1350                 return ret;
1351
1352         /*
1353          * GCC likes to generate cmov here, but this branch is extremely
1354          * predictable (it's just a funciton of time and the likely is
1355          * very likely) and there's a data dependence, so force GCC
1356          * to generate a branch instead.  I don't barrier() because
1357          * we don't actually need a barrier, and if this function
1358          * ever gets inlined it will generate worse code.
1359          */
1360         asm volatile ("");
1361         return last;
1362 }
1363
1364 static inline u64 vgettsc(cycle_t *cycle_now)
1365 {
1366         long v;
1367         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1368
1369         *cycle_now = read_tsc();
1370
1371         v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1372         return v * gtod->clock.mult;
1373 }
1374
1375 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1376 {
1377         unsigned long seq;
1378         u64 ns;
1379         int mode;
1380         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1381
1382         ts->tv_nsec = 0;
1383         do {
1384                 seq = read_seqcount_begin(&gtod->seq);
1385                 mode = gtod->clock.vclock_mode;
1386                 ts->tv_sec = gtod->monotonic_time_sec;
1387                 ns = gtod->monotonic_time_snsec;
1388                 ns += vgettsc(cycle_now);
1389                 ns >>= gtod->clock.shift;
1390         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1391         timespec_add_ns(ts, ns);
1392
1393         return mode;
1394 }
1395
1396 /* returns true if host is using tsc clocksource */
1397 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1398 {
1399         struct timespec ts;
1400
1401         /* checked again under seqlock below */
1402         if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1403                 return false;
1404
1405         if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1406                 return false;
1407
1408         monotonic_to_bootbased(&ts);
1409         *kernel_ns = timespec_to_ns(&ts);
1410
1411         return true;
1412 }
1413 #endif
1414
1415 /*
1416  *
1417  * Assuming a stable TSC across physical CPUS, and a stable TSC
1418  * across virtual CPUs, the following condition is possible.
1419  * Each numbered line represents an event visible to both
1420  * CPUs at the next numbered event.
1421  *
1422  * "timespecX" represents host monotonic time. "tscX" represents
1423  * RDTSC value.
1424  *
1425  *              VCPU0 on CPU0           |       VCPU1 on CPU1
1426  *
1427  * 1.  read timespec0,tsc0
1428  * 2.                                   | timespec1 = timespec0 + N
1429  *                                      | tsc1 = tsc0 + M
1430  * 3. transition to guest               | transition to guest
1431  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1432  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
1433  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1434  *
1435  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1436  *
1437  *      - ret0 < ret1
1438  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1439  *              ...
1440  *      - 0 < N - M => M < N
1441  *
1442  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1443  * always the case (the difference between two distinct xtime instances
1444  * might be smaller then the difference between corresponding TSC reads,
1445  * when updating guest vcpus pvclock areas).
1446  *
1447  * To avoid that problem, do not allow visibility of distinct
1448  * system_timestamp/tsc_timestamp values simultaneously: use a master
1449  * copy of host monotonic time values. Update that master copy
1450  * in lockstep.
1451  *
1452  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1453  *
1454  */
1455
1456 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1457 {
1458 #ifdef CONFIG_X86_64
1459         struct kvm_arch *ka = &kvm->arch;
1460         int vclock_mode;
1461         bool host_tsc_clocksource, vcpus_matched;
1462
1463         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1464                         atomic_read(&kvm->online_vcpus));
1465
1466         /*
1467          * If the host uses TSC clock, then passthrough TSC as stable
1468          * to the guest.
1469          */
1470         host_tsc_clocksource = kvm_get_time_and_clockread(
1471                                         &ka->master_kernel_ns,
1472                                         &ka->master_cycle_now);
1473
1474         ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1475
1476         if (ka->use_master_clock)
1477                 atomic_set(&kvm_guest_has_master_clock, 1);
1478
1479         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1480         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1481                                         vcpus_matched);
1482 #endif
1483 }
1484
1485 static void kvm_gen_update_masterclock(struct kvm *kvm)
1486 {
1487 #ifdef CONFIG_X86_64
1488         int i;
1489         struct kvm_vcpu *vcpu;
1490         struct kvm_arch *ka = &kvm->arch;
1491
1492         spin_lock(&ka->pvclock_gtod_sync_lock);
1493         kvm_make_mclock_inprogress_request(kvm);
1494         /* no guest entries from this point */
1495         pvclock_update_vm_gtod_copy(kvm);
1496
1497         kvm_for_each_vcpu(i, vcpu, kvm)
1498                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1499
1500         /* guest entries allowed */
1501         kvm_for_each_vcpu(i, vcpu, kvm)
1502                 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1503
1504         spin_unlock(&ka->pvclock_gtod_sync_lock);
1505 #endif
1506 }
1507
1508 static int kvm_guest_time_update(struct kvm_vcpu *v)
1509 {
1510         unsigned long flags, this_tsc_khz;
1511         struct kvm_vcpu_arch *vcpu = &v->arch;
1512         struct kvm_arch *ka = &v->kvm->arch;
1513         s64 kernel_ns;
1514         u64 tsc_timestamp, host_tsc;
1515         struct pvclock_vcpu_time_info guest_hv_clock;
1516         u8 pvclock_flags;
1517         bool use_master_clock;
1518
1519         kernel_ns = 0;
1520         host_tsc = 0;
1521
1522         /*
1523          * If the host uses TSC clock, then passthrough TSC as stable
1524          * to the guest.
1525          */
1526         spin_lock(&ka->pvclock_gtod_sync_lock);
1527         use_master_clock = ka->use_master_clock;
1528         if (use_master_clock) {
1529                 host_tsc = ka->master_cycle_now;
1530                 kernel_ns = ka->master_kernel_ns;
1531         }
1532         spin_unlock(&ka->pvclock_gtod_sync_lock);
1533
1534         /* Keep irq disabled to prevent changes to the clock */
1535         local_irq_save(flags);
1536         this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1537         if (unlikely(this_tsc_khz == 0)) {
1538                 local_irq_restore(flags);
1539                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1540                 return 1;
1541         }
1542         if (!use_master_clock) {
1543                 host_tsc = native_read_tsc();
1544                 kernel_ns = get_kernel_ns();
1545         }
1546
1547         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1548
1549         /*
1550          * We may have to catch up the TSC to match elapsed wall clock
1551          * time for two reasons, even if kvmclock is used.
1552          *   1) CPU could have been running below the maximum TSC rate
1553          *   2) Broken TSC compensation resets the base at each VCPU
1554          *      entry to avoid unknown leaps of TSC even when running
1555          *      again on the same CPU.  This may cause apparent elapsed
1556          *      time to disappear, and the guest to stand still or run
1557          *      very slowly.
1558          */
1559         if (vcpu->tsc_catchup) {
1560                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1561                 if (tsc > tsc_timestamp) {
1562                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1563                         tsc_timestamp = tsc;
1564                 }
1565         }
1566
1567         local_irq_restore(flags);
1568
1569         if (!vcpu->pv_time_enabled)
1570                 return 0;
1571
1572         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1573                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1574                                    &vcpu->hv_clock.tsc_shift,
1575                                    &vcpu->hv_clock.tsc_to_system_mul);
1576                 vcpu->hw_tsc_khz = this_tsc_khz;
1577         }
1578
1579         /* With all the info we got, fill in the values */
1580         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1581         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1582         vcpu->last_guest_tsc = tsc_timestamp;
1583
1584         /*
1585          * The interface expects us to write an even number signaling that the
1586          * update is finished. Since the guest won't see the intermediate
1587          * state, we just increase by 2 at the end.
1588          */
1589         vcpu->hv_clock.version += 2;
1590
1591         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1592                 &guest_hv_clock, sizeof(guest_hv_clock))))
1593                 return 0;
1594
1595         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1596         pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1597
1598         if (vcpu->pvclock_set_guest_stopped_request) {
1599                 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1600                 vcpu->pvclock_set_guest_stopped_request = false;
1601         }
1602
1603         /* If the host uses TSC clocksource, then it is stable */
1604         if (use_master_clock)
1605                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1606
1607         vcpu->hv_clock.flags = pvclock_flags;
1608
1609         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1610                                 &vcpu->hv_clock,
1611                                 sizeof(vcpu->hv_clock));
1612         return 0;
1613 }
1614
1615 /*
1616  * kvmclock updates which are isolated to a given vcpu, such as
1617  * vcpu->cpu migration, should not allow system_timestamp from
1618  * the rest of the vcpus to remain static. Otherwise ntp frequency
1619  * correction applies to one vcpu's system_timestamp but not
1620  * the others.
1621  *
1622  * So in those cases, request a kvmclock update for all vcpus.
1623  * We need to rate-limit these requests though, as they can
1624  * considerably slow guests that have a large number of vcpus.
1625  * The time for a remote vcpu to update its kvmclock is bound
1626  * by the delay we use to rate-limit the updates.
1627  */
1628
1629 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1630
1631 static void kvmclock_update_fn(struct work_struct *work)
1632 {
1633         int i;
1634         struct delayed_work *dwork = to_delayed_work(work);
1635         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1636                                            kvmclock_update_work);
1637         struct kvm *kvm = container_of(ka, struct kvm, arch);
1638         struct kvm_vcpu *vcpu;
1639
1640         kvm_for_each_vcpu(i, vcpu, kvm) {
1641                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1642                 kvm_vcpu_kick(vcpu);
1643         }
1644 }
1645
1646 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1647 {
1648         struct kvm *kvm = v->kvm;
1649
1650         set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1651         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1652                                         KVMCLOCK_UPDATE_DELAY);
1653 }
1654
1655 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1656
1657 static void kvmclock_sync_fn(struct work_struct *work)
1658 {
1659         struct delayed_work *dwork = to_delayed_work(work);
1660         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1661                                            kvmclock_sync_work);
1662         struct kvm *kvm = container_of(ka, struct kvm, arch);
1663
1664         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1665         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1666                                         KVMCLOCK_SYNC_PERIOD);
1667 }
1668
1669 static bool msr_mtrr_valid(unsigned msr)
1670 {
1671         switch (msr) {
1672         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1673         case MSR_MTRRfix64K_00000:
1674         case MSR_MTRRfix16K_80000:
1675         case MSR_MTRRfix16K_A0000:
1676         case MSR_MTRRfix4K_C0000:
1677         case MSR_MTRRfix4K_C8000:
1678         case MSR_MTRRfix4K_D0000:
1679         case MSR_MTRRfix4K_D8000:
1680         case MSR_MTRRfix4K_E0000:
1681         case MSR_MTRRfix4K_E8000:
1682         case MSR_MTRRfix4K_F0000:
1683         case MSR_MTRRfix4K_F8000:
1684         case MSR_MTRRdefType:
1685         case MSR_IA32_CR_PAT:
1686                 return true;
1687         case 0x2f8:
1688                 return true;
1689         }
1690         return false;
1691 }
1692
1693 static bool valid_pat_type(unsigned t)
1694 {
1695         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1696 }
1697
1698 static bool valid_mtrr_type(unsigned t)
1699 {
1700         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1701 }
1702
1703 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1704 {
1705         int i;
1706
1707         if (!msr_mtrr_valid(msr))
1708                 return false;
1709
1710         if (msr == MSR_IA32_CR_PAT) {
1711                 for (i = 0; i < 8; i++)
1712                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1713                                 return false;
1714                 return true;
1715         } else if (msr == MSR_MTRRdefType) {
1716                 if (data & ~0xcff)
1717                         return false;
1718                 return valid_mtrr_type(data & 0xff);
1719         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1720                 for (i = 0; i < 8 ; i++)
1721                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1722                                 return false;
1723                 return true;
1724         }
1725
1726         /* variable MTRRs */
1727         return valid_mtrr_type(data & 0xff);
1728 }
1729
1730 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1731 {
1732         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1733
1734         if (!mtrr_valid(vcpu, msr, data))
1735                 return 1;
1736
1737         if (msr == MSR_MTRRdefType) {
1738                 vcpu->arch.mtrr_state.def_type = data;
1739                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1740         } else if (msr == MSR_MTRRfix64K_00000)
1741                 p[0] = data;
1742         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1743                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1744         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1745                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1746         else if (msr == MSR_IA32_CR_PAT)
1747                 vcpu->arch.pat = data;
1748         else {  /* Variable MTRRs */
1749                 int idx, is_mtrr_mask;
1750                 u64 *pt;
1751
1752                 idx = (msr - 0x200) / 2;
1753                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1754                 if (!is_mtrr_mask)
1755                         pt =
1756                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1757                 else
1758                         pt =
1759                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1760                 *pt = data;
1761         }
1762
1763         kvm_mmu_reset_context(vcpu);
1764         return 0;
1765 }
1766
1767 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1768 {
1769         u64 mcg_cap = vcpu->arch.mcg_cap;
1770         unsigned bank_num = mcg_cap & 0xff;
1771
1772         switch (msr) {
1773         case MSR_IA32_MCG_STATUS:
1774                 vcpu->arch.mcg_status = data;
1775                 break;
1776         case MSR_IA32_MCG_CTL:
1777                 if (!(mcg_cap & MCG_CTL_P))
1778                         return 1;
1779                 if (data != 0 && data != ~(u64)0)
1780                         return -1;
1781                 vcpu->arch.mcg_ctl = data;
1782                 break;
1783         default:
1784                 if (msr >= MSR_IA32_MC0_CTL &&
1785                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1786                         u32 offset = msr - MSR_IA32_MC0_CTL;
1787                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1788                          * some Linux kernels though clear bit 10 in bank 4 to
1789                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1790                          * this to avoid an uncatched #GP in the guest
1791                          */
1792                         if ((offset & 0x3) == 0 &&
1793                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1794                                 return -1;
1795                         vcpu->arch.mce_banks[offset] = data;
1796                         break;
1797                 }
1798                 return 1;
1799         }
1800         return 0;
1801 }
1802
1803 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1804 {
1805         struct kvm *kvm = vcpu->kvm;
1806         int lm = is_long_mode(vcpu);
1807         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1808                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1809         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1810                 : kvm->arch.xen_hvm_config.blob_size_32;
1811         u32 page_num = data & ~PAGE_MASK;
1812         u64 page_addr = data & PAGE_MASK;
1813         u8 *page;
1814         int r;
1815
1816         r = -E2BIG;
1817         if (page_num >= blob_size)
1818                 goto out;
1819         r = -ENOMEM;
1820         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1821         if (IS_ERR(page)) {
1822                 r = PTR_ERR(page);
1823                 goto out;
1824         }
1825         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1826                 goto out_free;
1827         r = 0;
1828 out_free:
1829         kfree(page);
1830 out:
1831         return r;
1832 }
1833
1834 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1835 {
1836         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1837 }
1838
1839 static bool kvm_hv_msr_partition_wide(u32 msr)
1840 {
1841         bool r = false;
1842         switch (msr) {
1843         case HV_X64_MSR_GUEST_OS_ID:
1844         case HV_X64_MSR_HYPERCALL:
1845         case HV_X64_MSR_REFERENCE_TSC:
1846         case HV_X64_MSR_TIME_REF_COUNT:
1847                 r = true;
1848                 break;
1849         }
1850
1851         return r;
1852 }
1853
1854 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1855 {
1856         struct kvm *kvm = vcpu->kvm;
1857
1858         switch (msr) {
1859         case HV_X64_MSR_GUEST_OS_ID:
1860                 kvm->arch.hv_guest_os_id = data;
1861                 /* setting guest os id to zero disables hypercall page */
1862                 if (!kvm->arch.hv_guest_os_id)
1863                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1864                 break;
1865         case HV_X64_MSR_HYPERCALL: {
1866                 u64 gfn;
1867                 unsigned long addr;
1868                 u8 instructions[4];
1869
1870                 /* if guest os id is not set hypercall should remain disabled */
1871                 if (!kvm->arch.hv_guest_os_id)
1872                         break;
1873                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1874                         kvm->arch.hv_hypercall = data;
1875                         break;
1876                 }
1877                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1878                 addr = gfn_to_hva(kvm, gfn);
1879                 if (kvm_is_error_hva(addr))
1880                         return 1;
1881                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1882                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1883                 if (__copy_to_user((void __user *)addr, instructions, 4))
1884                         return 1;
1885                 kvm->arch.hv_hypercall = data;
1886                 mark_page_dirty(kvm, gfn);
1887                 break;
1888         }
1889         case HV_X64_MSR_REFERENCE_TSC: {
1890                 u64 gfn;
1891                 HV_REFERENCE_TSC_PAGE tsc_ref;
1892                 memset(&tsc_ref, 0, sizeof(tsc_ref));
1893                 kvm->arch.hv_tsc_page = data;
1894                 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1895                         break;
1896                 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1897                 if (kvm_write_guest(kvm, data,
1898                         &tsc_ref, sizeof(tsc_ref)))
1899                         return 1;
1900                 mark_page_dirty(kvm, gfn);
1901                 break;
1902         }
1903         default:
1904                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1905                             "data 0x%llx\n", msr, data);
1906                 return 1;
1907         }
1908         return 0;
1909 }
1910
1911 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1912 {
1913         switch (msr) {
1914         case HV_X64_MSR_APIC_ASSIST_PAGE: {
1915                 u64 gfn;
1916                 unsigned long addr;
1917
1918                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1919                         vcpu->arch.hv_vapic = data;
1920                         break;
1921                 }
1922                 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1923                 addr = gfn_to_hva(vcpu->kvm, gfn);
1924                 if (kvm_is_error_hva(addr))
1925                         return 1;
1926                 if (__clear_user((void __user *)addr, PAGE_SIZE))
1927                         return 1;
1928                 vcpu->arch.hv_vapic = data;
1929                 mark_page_dirty(vcpu->kvm, gfn);
1930                 break;
1931         }
1932         case HV_X64_MSR_EOI:
1933                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1934         case HV_X64_MSR_ICR:
1935                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1936         case HV_X64_MSR_TPR:
1937                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1938         default:
1939                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1940                             "data 0x%llx\n", msr, data);
1941                 return 1;
1942         }
1943
1944         return 0;
1945 }
1946
1947 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1948 {
1949         gpa_t gpa = data & ~0x3f;
1950
1951         /* Bits 2:5 are reserved, Should be zero */
1952         if (data & 0x3c)
1953                 return 1;
1954
1955         vcpu->arch.apf.msr_val = data;
1956
1957         if (!(data & KVM_ASYNC_PF_ENABLED)) {
1958                 kvm_clear_async_pf_completion_queue(vcpu);
1959                 kvm_async_pf_hash_reset(vcpu);
1960                 return 0;
1961         }
1962
1963         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1964                                         sizeof(u32)))
1965                 return 1;
1966
1967         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1968         kvm_async_pf_wakeup_all(vcpu);
1969         return 0;
1970 }
1971
1972 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1973 {
1974         vcpu->arch.pv_time_enabled = false;
1975 }
1976
1977 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1978 {
1979         u64 delta;
1980
1981         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1982                 return;
1983
1984         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1985         vcpu->arch.st.last_steal = current->sched_info.run_delay;
1986         vcpu->arch.st.accum_steal = delta;
1987 }
1988
1989 static void record_steal_time(struct kvm_vcpu *vcpu)
1990 {
1991         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1992                 return;
1993
1994         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1995                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1996                 return;
1997
1998         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1999         vcpu->arch.st.steal.version += 2;
2000         vcpu->arch.st.accum_steal = 0;
2001
2002         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2003                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2004 }
2005
2006 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2007 {
2008         bool pr = false;
2009         u32 msr = msr_info->index;
2010         u64 data = msr_info->data;
2011
2012         switch (msr) {
2013         case MSR_AMD64_NB_CFG:
2014         case MSR_IA32_UCODE_REV:
2015         case MSR_IA32_UCODE_WRITE:
2016         case MSR_VM_HSAVE_PA:
2017         case MSR_AMD64_PATCH_LOADER:
2018         case MSR_AMD64_BU_CFG2:
2019                 break;
2020
2021         case MSR_EFER:
2022                 return set_efer(vcpu, data);
2023         case MSR_K7_HWCR:
2024                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2025                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2026                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2027                 if (data != 0) {
2028                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2029                                     data);
2030                         return 1;
2031                 }
2032                 break;
2033         case MSR_FAM10H_MMIO_CONF_BASE:
2034                 if (data != 0) {
2035                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2036                                     "0x%llx\n", data);
2037                         return 1;
2038                 }
2039                 break;
2040         case MSR_IA32_DEBUGCTLMSR:
2041                 if (!data) {
2042                         /* We support the non-activated case already */
2043                         break;
2044                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2045                         /* Values other than LBR and BTF are vendor-specific,
2046                            thus reserved and should throw a #GP */
2047                         return 1;
2048                 }
2049                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2050                             __func__, data);
2051                 break;
2052         case 0x200 ... 0x2ff:
2053                 return set_msr_mtrr(vcpu, msr, data);
2054         case MSR_IA32_APICBASE:
2055                 return kvm_set_apic_base(vcpu, msr_info);
2056         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2057                 return kvm_x2apic_msr_write(vcpu, msr, data);
2058         case MSR_IA32_TSCDEADLINE:
2059                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2060                 break;
2061         case MSR_IA32_TSC_ADJUST:
2062                 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2063                         if (!msr_info->host_initiated) {
2064                                 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2065                                 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2066                         }
2067                         vcpu->arch.ia32_tsc_adjust_msr = data;
2068                 }
2069                 break;
2070         case MSR_IA32_MISC_ENABLE:
2071                 vcpu->arch.ia32_misc_enable_msr = data;
2072                 break;
2073         case MSR_KVM_WALL_CLOCK_NEW:
2074         case MSR_KVM_WALL_CLOCK:
2075                 vcpu->kvm->arch.wall_clock = data;
2076                 kvm_write_wall_clock(vcpu->kvm, data);
2077                 break;
2078         case MSR_KVM_SYSTEM_TIME_NEW:
2079         case MSR_KVM_SYSTEM_TIME: {
2080                 u64 gpa_offset;
2081                 kvmclock_reset(vcpu);
2082
2083                 vcpu->arch.time = data;
2084                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2085
2086                 /* we verify if the enable bit is set... */
2087                 if (!(data & 1))
2088                         break;
2089
2090                 gpa_offset = data & ~(PAGE_MASK | 1);
2091
2092                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2093                      &vcpu->arch.pv_time, data & ~1ULL,
2094                      sizeof(struct pvclock_vcpu_time_info)))
2095                         vcpu->arch.pv_time_enabled = false;
2096                 else
2097                         vcpu->arch.pv_time_enabled = true;
2098
2099                 break;
2100         }
2101         case MSR_KVM_ASYNC_PF_EN:
2102                 if (kvm_pv_enable_async_pf(vcpu, data))
2103                         return 1;
2104                 break;
2105         case MSR_KVM_STEAL_TIME:
2106
2107                 if (unlikely(!sched_info_on()))
2108                         return 1;
2109
2110                 if (data & KVM_STEAL_RESERVED_MASK)
2111                         return 1;
2112
2113                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2114                                                 data & KVM_STEAL_VALID_BITS,
2115                                                 sizeof(struct kvm_steal_time)))
2116                         return 1;
2117
2118                 vcpu->arch.st.msr_val = data;
2119
2120                 if (!(data & KVM_MSR_ENABLED))
2121                         break;
2122
2123                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2124
2125                 preempt_disable();
2126                 accumulate_steal_time(vcpu);
2127                 preempt_enable();
2128
2129                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2130
2131                 break;
2132         case MSR_KVM_PV_EOI_EN:
2133                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2134                         return 1;
2135                 break;
2136
2137         case MSR_IA32_MCG_CTL:
2138         case MSR_IA32_MCG_STATUS:
2139         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2140                 return set_msr_mce(vcpu, msr, data);
2141
2142         /* Performance counters are not protected by a CPUID bit,
2143          * so we should check all of them in the generic path for the sake of
2144          * cross vendor migration.
2145          * Writing a zero into the event select MSRs disables them,
2146          * which we perfectly emulate ;-). Any other value should be at least
2147          * reported, some guests depend on them.
2148          */
2149         case MSR_K7_EVNTSEL0:
2150         case MSR_K7_EVNTSEL1:
2151         case MSR_K7_EVNTSEL2:
2152         case MSR_K7_EVNTSEL3:
2153                 if (data != 0)
2154                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2155                                     "0x%x data 0x%llx\n", msr, data);
2156                 break;
2157         /* at least RHEL 4 unconditionally writes to the perfctr registers,
2158          * so we ignore writes to make it happy.
2159          */
2160         case MSR_K7_PERFCTR0:
2161         case MSR_K7_PERFCTR1:
2162         case MSR_K7_PERFCTR2:
2163         case MSR_K7_PERFCTR3:
2164                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2165                             "0x%x data 0x%llx\n", msr, data);
2166                 break;
2167         case MSR_P6_PERFCTR0:
2168         case MSR_P6_PERFCTR1:
2169                 pr = true;
2170         case MSR_P6_EVNTSEL0:
2171         case MSR_P6_EVNTSEL1:
2172                 if (kvm_pmu_msr(vcpu, msr))
2173                         return kvm_pmu_set_msr(vcpu, msr_info);
2174
2175                 if (pr || data != 0)
2176                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2177                                     "0x%x data 0x%llx\n", msr, data);
2178                 break;
2179         case MSR_K7_CLK_CTL:
2180                 /*
2181                  * Ignore all writes to this no longer documented MSR.
2182                  * Writes are only relevant for old K7 processors,
2183                  * all pre-dating SVM, but a recommended workaround from
2184                  * AMD for these chips. It is possible to specify the
2185                  * affected processor models on the command line, hence
2186                  * the need to ignore the workaround.
2187                  */
2188                 break;
2189         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2190                 if (kvm_hv_msr_partition_wide(msr)) {
2191                         int r;
2192                         mutex_lock(&vcpu->kvm->lock);
2193                         r = set_msr_hyperv_pw(vcpu, msr, data);
2194                         mutex_unlock(&vcpu->kvm->lock);
2195                         return r;
2196                 } else
2197                         return set_msr_hyperv(vcpu, msr, data);
2198                 break;
2199         case MSR_IA32_BBL_CR_CTL3:
2200                 /* Drop writes to this legacy MSR -- see rdmsr
2201                  * counterpart for further detail.
2202                  */
2203                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2204                 break;
2205         case MSR_AMD64_OSVW_ID_LENGTH:
2206                 if (!guest_cpuid_has_osvw(vcpu))
2207                         return 1;
2208                 vcpu->arch.osvw.length = data;
2209                 break;
2210         case MSR_AMD64_OSVW_STATUS:
2211                 if (!guest_cpuid_has_osvw(vcpu))
2212                         return 1;
2213                 vcpu->arch.osvw.status = data;
2214                 break;
2215         default:
2216                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2217                         return xen_hvm_config(vcpu, data);
2218                 if (kvm_pmu_msr(vcpu, msr))
2219                         return kvm_pmu_set_msr(vcpu, msr_info);
2220                 if (!ignore_msrs) {
2221                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2222                                     msr, data);
2223                         return 1;
2224                 } else {
2225                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2226                                     msr, data);
2227                         break;
2228                 }
2229         }
2230         return 0;
2231 }
2232 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2233
2234
2235 /*
2236  * Reads an msr value (of 'msr_index') into 'pdata'.
2237  * Returns 0 on success, non-0 otherwise.
2238  * Assumes vcpu_load() was already called.
2239  */
2240 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2241 {
2242         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2243 }
2244
2245 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2246 {
2247         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2248
2249         if (!msr_mtrr_valid(msr))
2250                 return 1;
2251
2252         if (msr == MSR_MTRRdefType)
2253                 *pdata = vcpu->arch.mtrr_state.def_type +
2254                          (vcpu->arch.mtrr_state.enabled << 10);
2255         else if (msr == MSR_MTRRfix64K_00000)
2256                 *pdata = p[0];
2257         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2258                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2259         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2260                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2261         else if (msr == MSR_IA32_CR_PAT)
2262                 *pdata = vcpu->arch.pat;
2263         else {  /* Variable MTRRs */
2264                 int idx, is_mtrr_mask;
2265                 u64 *pt;
2266
2267                 idx = (msr - 0x200) / 2;
2268                 is_mtrr_mask = msr - 0x200 - 2 * idx;
2269                 if (!is_mtrr_mask)
2270                         pt =
2271                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2272                 else
2273                         pt =
2274                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2275                 *pdata = *pt;
2276         }
2277
2278         return 0;
2279 }
2280
2281 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2282 {
2283         u64 data;
2284         u64 mcg_cap = vcpu->arch.mcg_cap;
2285         unsigned bank_num = mcg_cap & 0xff;
2286
2287         switch (msr) {
2288         case MSR_IA32_P5_MC_ADDR:
2289         case MSR_IA32_P5_MC_TYPE:
2290                 data = 0;
2291                 break;
2292         case MSR_IA32_MCG_CAP:
2293                 data = vcpu->arch.mcg_cap;
2294                 break;
2295         case MSR_IA32_MCG_CTL:
2296                 if (!(mcg_cap & MCG_CTL_P))
2297                         return 1;
2298                 data = vcpu->arch.mcg_ctl;
2299                 break;
2300         case MSR_IA32_MCG_STATUS:
2301                 data = vcpu->arch.mcg_status;
2302                 break;
2303         default:
2304                 if (msr >= MSR_IA32_MC0_CTL &&
2305                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2306                         u32 offset = msr - MSR_IA32_MC0_CTL;
2307                         data = vcpu->arch.mce_banks[offset];
2308                         break;
2309                 }
2310                 return 1;
2311         }
2312         *pdata = data;
2313         return 0;
2314 }
2315
2316 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2317 {
2318         u64 data = 0;
2319         struct kvm *kvm = vcpu->kvm;
2320
2321         switch (msr) {
2322         case HV_X64_MSR_GUEST_OS_ID:
2323                 data = kvm->arch.hv_guest_os_id;
2324                 break;
2325         case HV_X64_MSR_HYPERCALL:
2326                 data = kvm->arch.hv_hypercall;
2327                 break;
2328         case HV_X64_MSR_TIME_REF_COUNT: {
2329                 data =
2330                      div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2331                 break;
2332         }
2333         case HV_X64_MSR_REFERENCE_TSC:
2334                 data = kvm->arch.hv_tsc_page;
2335                 break;
2336         default:
2337                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2338                 return 1;
2339         }
2340
2341         *pdata = data;
2342         return 0;
2343 }
2344
2345 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2346 {
2347         u64 data = 0;
2348
2349         switch (msr) {
2350         case HV_X64_MSR_VP_INDEX: {
2351                 int r;
2352                 struct kvm_vcpu *v;
2353                 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2354                         if (v == vcpu) {
2355                                 data = r;
2356                                 break;
2357                         }
2358                 }
2359                 break;
2360         }
2361         case HV_X64_MSR_EOI:
2362                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2363         case HV_X64_MSR_ICR:
2364                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2365         case HV_X64_MSR_TPR:
2366                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2367         case HV_X64_MSR_APIC_ASSIST_PAGE:
2368                 data = vcpu->arch.hv_vapic;
2369                 break;
2370         default:
2371                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2372                 return 1;
2373         }
2374         *pdata = data;
2375         return 0;
2376 }
2377
2378 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2379 {
2380         u64 data;
2381
2382         switch (msr) {
2383         case MSR_IA32_PLATFORM_ID:
2384         case MSR_IA32_EBL_CR_POWERON:
2385         case MSR_IA32_DEBUGCTLMSR:
2386         case MSR_IA32_LASTBRANCHFROMIP:
2387         case MSR_IA32_LASTBRANCHTOIP:
2388         case MSR_IA32_LASTINTFROMIP:
2389         case MSR_IA32_LASTINTTOIP:
2390         case MSR_K8_SYSCFG:
2391         case MSR_K7_HWCR:
2392         case MSR_VM_HSAVE_PA:
2393         case MSR_K7_EVNTSEL0:
2394         case MSR_K7_PERFCTR0:
2395         case MSR_K8_INT_PENDING_MSG:
2396         case MSR_AMD64_NB_CFG:
2397         case MSR_FAM10H_MMIO_CONF_BASE:
2398         case MSR_AMD64_BU_CFG2:
2399                 data = 0;
2400                 break;
2401         case MSR_P6_PERFCTR0:
2402         case MSR_P6_PERFCTR1:
2403         case MSR_P6_EVNTSEL0:
2404         case MSR_P6_EVNTSEL1:
2405                 if (kvm_pmu_msr(vcpu, msr))
2406                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2407                 data = 0;
2408                 break;
2409         case MSR_IA32_UCODE_REV:
2410                 data = 0x100000000ULL;
2411                 break;
2412         case MSR_MTRRcap:
2413                 data = 0x500 | KVM_NR_VAR_MTRR;
2414                 break;
2415         case 0x200 ... 0x2ff:
2416                 return get_msr_mtrr(vcpu, msr, pdata);
2417         case 0xcd: /* fsb frequency */
2418                 data = 3;
2419                 break;
2420                 /*
2421                  * MSR_EBC_FREQUENCY_ID
2422                  * Conservative value valid for even the basic CPU models.
2423                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2424                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2425                  * and 266MHz for model 3, or 4. Set Core Clock
2426                  * Frequency to System Bus Frequency Ratio to 1 (bits
2427                  * 31:24) even though these are only valid for CPU
2428                  * models > 2, however guests may end up dividing or
2429                  * multiplying by zero otherwise.
2430                  */
2431         case MSR_EBC_FREQUENCY_ID:
2432                 data = 1 << 24;
2433                 break;
2434         case MSR_IA32_APICBASE:
2435                 data = kvm_get_apic_base(vcpu);
2436                 break;
2437         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2438                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2439                 break;
2440         case MSR_IA32_TSCDEADLINE:
2441                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2442                 break;
2443         case MSR_IA32_TSC_ADJUST:
2444                 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2445                 break;
2446         case MSR_IA32_MISC_ENABLE:
2447                 data = vcpu->arch.ia32_misc_enable_msr;
2448                 break;
2449         case MSR_IA32_PERF_STATUS:
2450                 /* TSC increment by tick */
2451                 data = 1000ULL;
2452                 /* CPU multiplier */
2453                 data |= (((uint64_t)4ULL) << 40);
2454                 break;
2455         case MSR_EFER:
2456                 data = vcpu->arch.efer;
2457                 break;
2458         case MSR_KVM_WALL_CLOCK:
2459         case MSR_KVM_WALL_CLOCK_NEW:
2460                 data = vcpu->kvm->arch.wall_clock;
2461                 break;
2462         case MSR_KVM_SYSTEM_TIME:
2463         case MSR_KVM_SYSTEM_TIME_NEW:
2464                 data = vcpu->arch.time;
2465                 break;
2466         case MSR_KVM_ASYNC_PF_EN:
2467                 data = vcpu->arch.apf.msr_val;
2468                 break;
2469         case MSR_KVM_STEAL_TIME:
2470                 data = vcpu->arch.st.msr_val;
2471                 break;
2472         case MSR_KVM_PV_EOI_EN:
2473                 data = vcpu->arch.pv_eoi.msr_val;
2474                 break;
2475         case MSR_IA32_P5_MC_ADDR:
2476         case MSR_IA32_P5_MC_TYPE:
2477         case MSR_IA32_MCG_CAP:
2478         case MSR_IA32_MCG_CTL:
2479         case MSR_IA32_MCG_STATUS:
2480         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2481                 return get_msr_mce(vcpu, msr, pdata);
2482         case MSR_K7_CLK_CTL:
2483                 /*
2484                  * Provide expected ramp-up count for K7. All other
2485                  * are set to zero, indicating minimum divisors for
2486                  * every field.
2487                  *
2488                  * This prevents guest kernels on AMD host with CPU
2489                  * type 6, model 8 and higher from exploding due to
2490                  * the rdmsr failing.
2491                  */
2492                 data = 0x20000000;
2493                 break;
2494         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2495                 if (kvm_hv_msr_partition_wide(msr)) {
2496                         int r;
2497                         mutex_lock(&vcpu->kvm->lock);
2498                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2499                         mutex_unlock(&vcpu->kvm->lock);
2500                         return r;
2501                 } else
2502                         return get_msr_hyperv(vcpu, msr, pdata);
2503                 break;
2504         case MSR_IA32_BBL_CR_CTL3:
2505                 /* This legacy MSR exists but isn't fully documented in current
2506                  * silicon.  It is however accessed by winxp in very narrow
2507                  * scenarios where it sets bit #19, itself documented as
2508                  * a "reserved" bit.  Best effort attempt to source coherent
2509                  * read data here should the balance of the register be
2510                  * interpreted by the guest:
2511                  *
2512                  * L2 cache control register 3: 64GB range, 256KB size,
2513                  * enabled, latency 0x1, configured
2514                  */
2515                 data = 0xbe702111;
2516                 break;
2517         case MSR_AMD64_OSVW_ID_LENGTH:
2518                 if (!guest_cpuid_has_osvw(vcpu))
2519                         return 1;
2520                 data = vcpu->arch.osvw.length;
2521                 break;
2522         case MSR_AMD64_OSVW_STATUS:
2523                 if (!guest_cpuid_has_osvw(vcpu))
2524                         return 1;
2525                 data = vcpu->arch.osvw.status;
2526                 break;
2527         default:
2528                 if (kvm_pmu_msr(vcpu, msr))
2529                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2530                 if (!ignore_msrs) {
2531                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2532                         return 1;
2533                 } else {
2534                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2535                         data = 0;
2536                 }
2537                 break;
2538         }
2539         *pdata = data;
2540         return 0;
2541 }
2542 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2543
2544 /*
2545  * Read or write a bunch of msrs. All parameters are kernel addresses.
2546  *
2547  * @return number of msrs set successfully.
2548  */
2549 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2550                     struct kvm_msr_entry *entries,
2551                     int (*do_msr)(struct kvm_vcpu *vcpu,
2552                                   unsigned index, u64 *data))
2553 {
2554         int i, idx;
2555
2556         idx = srcu_read_lock(&vcpu->kvm->srcu);
2557         for (i = 0; i < msrs->nmsrs; ++i)
2558                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2559                         break;
2560         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2561
2562         return i;
2563 }
2564
2565 /*
2566  * Read or write a bunch of msrs. Parameters are user addresses.
2567  *
2568  * @return number of msrs set successfully.
2569  */
2570 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2571                   int (*do_msr)(struct kvm_vcpu *vcpu,
2572                                 unsigned index, u64 *data),
2573                   int writeback)
2574 {
2575         struct kvm_msrs msrs;
2576         struct kvm_msr_entry *entries;
2577         int r, n;
2578         unsigned size;
2579
2580         r = -EFAULT;
2581         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2582                 goto out;
2583
2584         r = -E2BIG;
2585         if (msrs.nmsrs >= MAX_IO_MSRS)
2586                 goto out;
2587
2588         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2589         entries = memdup_user(user_msrs->entries, size);
2590         if (IS_ERR(entries)) {
2591                 r = PTR_ERR(entries);
2592                 goto out;
2593         }
2594
2595         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2596         if (r < 0)
2597                 goto out_free;
2598
2599         r = -EFAULT;
2600         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2601                 goto out_free;
2602
2603         r = n;
2604
2605 out_free:
2606         kfree(entries);
2607 out:
2608         return r;
2609 }
2610
2611 int kvm_dev_ioctl_check_extension(long ext)
2612 {
2613         int r;
2614
2615         switch (ext) {
2616         case KVM_CAP_IRQCHIP:
2617         case KVM_CAP_HLT:
2618         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2619         case KVM_CAP_SET_TSS_ADDR:
2620         case KVM_CAP_EXT_CPUID:
2621         case KVM_CAP_EXT_EMUL_CPUID:
2622         case KVM_CAP_CLOCKSOURCE:
2623         case KVM_CAP_PIT:
2624         case KVM_CAP_NOP_IO_DELAY:
2625         case KVM_CAP_MP_STATE:
2626         case KVM_CAP_SYNC_MMU:
2627         case KVM_CAP_USER_NMI:
2628         case KVM_CAP_REINJECT_CONTROL:
2629         case KVM_CAP_IRQ_INJECT_STATUS:
2630         case KVM_CAP_IRQFD:
2631         case KVM_CAP_IOEVENTFD:
2632         case KVM_CAP_IOEVENTFD_NO_LENGTH:
2633         case KVM_CAP_PIT2:
2634         case KVM_CAP_PIT_STATE2:
2635         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2636         case KVM_CAP_XEN_HVM:
2637         case KVM_CAP_ADJUST_CLOCK:
2638         case KVM_CAP_VCPU_EVENTS:
2639         case KVM_CAP_HYPERV:
2640         case KVM_CAP_HYPERV_VAPIC:
2641         case KVM_CAP_HYPERV_SPIN:
2642         case KVM_CAP_PCI_SEGMENT:
2643         case KVM_CAP_DEBUGREGS:
2644         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2645         case KVM_CAP_XSAVE:
2646         case KVM_CAP_ASYNC_PF:
2647         case KVM_CAP_GET_TSC_KHZ:
2648         case KVM_CAP_KVMCLOCK_CTRL:
2649         case KVM_CAP_READONLY_MEM:
2650         case KVM_CAP_HYPERV_TIME:
2651         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2652 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2653         case KVM_CAP_ASSIGN_DEV_IRQ:
2654         case KVM_CAP_PCI_2_3:
2655 #endif
2656                 r = 1;
2657                 break;
2658         case KVM_CAP_COALESCED_MMIO:
2659                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2660                 break;
2661         case KVM_CAP_VAPIC:
2662                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2663                 break;
2664         case KVM_CAP_NR_VCPUS:
2665                 r = KVM_SOFT_MAX_VCPUS;
2666                 break;
2667         case KVM_CAP_MAX_VCPUS:
2668                 r = KVM_MAX_VCPUS;
2669                 break;
2670         case KVM_CAP_NR_MEMSLOTS:
2671                 r = KVM_USER_MEM_SLOTS;
2672                 break;
2673         case KVM_CAP_PV_MMU:    /* obsolete */
2674                 r = 0;
2675                 break;
2676 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2677         case KVM_CAP_IOMMU:
2678                 r = iommu_present(&pci_bus_type);
2679                 break;
2680 #endif
2681         case KVM_CAP_MCE:
2682                 r = KVM_MAX_MCE_BANKS;
2683                 break;
2684         case KVM_CAP_XCRS:
2685                 r = cpu_has_xsave;
2686                 break;
2687         case KVM_CAP_TSC_CONTROL:
2688                 r = kvm_has_tsc_control;
2689                 break;
2690         case KVM_CAP_TSC_DEADLINE_TIMER:
2691                 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2692                 break;
2693         default:
2694                 r = 0;
2695                 break;
2696         }
2697         return r;
2698
2699 }
2700
2701 long kvm_arch_dev_ioctl(struct file *filp,
2702                         unsigned int ioctl, unsigned long arg)
2703 {
2704         void __user *argp = (void __user *)arg;
2705         long r;
2706
2707         switch (ioctl) {
2708         case KVM_GET_MSR_INDEX_LIST: {
2709                 struct kvm_msr_list __user *user_msr_list = argp;
2710                 struct kvm_msr_list msr_list;
2711                 unsigned n;
2712
2713                 r = -EFAULT;
2714                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2715                         goto out;
2716                 n = msr_list.nmsrs;
2717                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2718                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2719                         goto out;
2720                 r = -E2BIG;
2721                 if (n < msr_list.nmsrs)
2722                         goto out;
2723                 r = -EFAULT;
2724                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2725                                  num_msrs_to_save * sizeof(u32)))
2726                         goto out;
2727                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2728                                  &emulated_msrs,
2729                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2730                         goto out;
2731                 r = 0;
2732                 break;
2733         }
2734         case KVM_GET_SUPPORTED_CPUID:
2735         case KVM_GET_EMULATED_CPUID: {
2736                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2737                 struct kvm_cpuid2 cpuid;
2738
2739                 r = -EFAULT;
2740                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2741                         goto out;
2742
2743                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2744                                             ioctl);
2745                 if (r)
2746                         goto out;
2747
2748                 r = -EFAULT;
2749                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2750                         goto out;
2751                 r = 0;
2752                 break;
2753         }
2754         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2755                 u64 mce_cap;
2756
2757                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2758                 r = -EFAULT;
2759                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2760                         goto out;
2761                 r = 0;
2762                 break;
2763         }
2764         default:
2765                 r = -EINVAL;
2766         }
2767 out:
2768         return r;
2769 }
2770
2771 static void wbinvd_ipi(void *garbage)
2772 {
2773         wbinvd();
2774 }
2775
2776 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2777 {
2778         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2779 }
2780
2781 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2782 {
2783         /* Address WBINVD may be executed by guest */
2784         if (need_emulate_wbinvd(vcpu)) {
2785                 if (kvm_x86_ops->has_wbinvd_exit())
2786                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2787                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2788                         smp_call_function_single(vcpu->cpu,
2789                                         wbinvd_ipi, NULL, 1);
2790         }
2791
2792         kvm_x86_ops->vcpu_load(vcpu, cpu);
2793
2794         /* Apply any externally detected TSC adjustments (due to suspend) */
2795         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2796                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2797                 vcpu->arch.tsc_offset_adjustment = 0;
2798                 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2799         }
2800
2801         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2802                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2803                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2804                 if (tsc_delta < 0)
2805                         mark_tsc_unstable("KVM discovered backwards TSC");
2806                 if (check_tsc_unstable()) {
2807                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2808                                                 vcpu->arch.last_guest_tsc);
2809                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2810                         vcpu->arch.tsc_catchup = 1;
2811                 }
2812                 /*
2813                  * On a host with synchronized TSC, there is no need to update
2814                  * kvmclock on vcpu->cpu migration
2815                  */
2816                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2817                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2818                 if (vcpu->cpu != cpu)
2819                         kvm_migrate_timers(vcpu);
2820                 vcpu->cpu = cpu;
2821         }
2822
2823         accumulate_steal_time(vcpu);
2824         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2825 }
2826
2827 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2828 {
2829         kvm_x86_ops->vcpu_put(vcpu);
2830         kvm_put_guest_fpu(vcpu);
2831         vcpu->arch.last_host_tsc = native_read_tsc();
2832 }
2833
2834 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2835                                     struct kvm_lapic_state *s)
2836 {
2837         kvm_x86_ops->sync_pir_to_irr(vcpu);
2838         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2839
2840         return 0;
2841 }
2842
2843 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2844                                     struct kvm_lapic_state *s)
2845 {
2846         kvm_apic_post_state_restore(vcpu, s);
2847         update_cr8_intercept(vcpu);
2848
2849         return 0;
2850 }
2851
2852 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2853                                     struct kvm_interrupt *irq)
2854 {
2855         if (irq->irq >= KVM_NR_INTERRUPTS)
2856                 return -EINVAL;
2857         if (irqchip_in_kernel(vcpu->kvm))
2858                 return -ENXIO;
2859
2860         kvm_queue_interrupt(vcpu, irq->irq, false);
2861         kvm_make_request(KVM_REQ_EVENT, vcpu);
2862
2863         return 0;
2864 }
2865
2866 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2867 {
2868         kvm_inject_nmi(vcpu);
2869
2870         return 0;
2871 }
2872
2873 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2874                                            struct kvm_tpr_access_ctl *tac)
2875 {
2876         if (tac->flags)
2877                 return -EINVAL;
2878         vcpu->arch.tpr_access_reporting = !!tac->enabled;
2879         return 0;
2880 }
2881
2882 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2883                                         u64 mcg_cap)
2884 {
2885         int r;
2886         unsigned bank_num = mcg_cap & 0xff, bank;
2887
2888         r = -EINVAL;
2889         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2890                 goto out;
2891         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2892                 goto out;
2893         r = 0;
2894         vcpu->arch.mcg_cap = mcg_cap;
2895         /* Init IA32_MCG_CTL to all 1s */
2896         if (mcg_cap & MCG_CTL_P)
2897                 vcpu->arch.mcg_ctl = ~(u64)0;
2898         /* Init IA32_MCi_CTL to all 1s */
2899         for (bank = 0; bank < bank_num; bank++)
2900                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2901 out:
2902         return r;
2903 }
2904
2905 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2906                                       struct kvm_x86_mce *mce)
2907 {
2908         u64 mcg_cap = vcpu->arch.mcg_cap;
2909         unsigned bank_num = mcg_cap & 0xff;
2910         u64 *banks = vcpu->arch.mce_banks;
2911
2912         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2913                 return -EINVAL;
2914         /*
2915          * if IA32_MCG_CTL is not all 1s, the uncorrected error
2916          * reporting is disabled
2917          */
2918         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2919             vcpu->arch.mcg_ctl != ~(u64)0)
2920                 return 0;
2921         banks += 4 * mce->bank;
2922         /*
2923          * if IA32_MCi_CTL is not all 1s, the uncorrected error
2924          * reporting is disabled for the bank
2925          */
2926         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2927                 return 0;
2928         if (mce->status & MCI_STATUS_UC) {
2929                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2930                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2931                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2932                         return 0;
2933                 }
2934                 if (banks[1] & MCI_STATUS_VAL)
2935                         mce->status |= MCI_STATUS_OVER;
2936                 banks[2] = mce->addr;
2937                 banks[3] = mce->misc;
2938                 vcpu->arch.mcg_status = mce->mcg_status;
2939                 banks[1] = mce->status;
2940                 kvm_queue_exception(vcpu, MC_VECTOR);
2941         } else if (!(banks[1] & MCI_STATUS_VAL)
2942                    || !(banks[1] & MCI_STATUS_UC)) {
2943                 if (banks[1] & MCI_STATUS_VAL)
2944                         mce->status |= MCI_STATUS_OVER;
2945                 banks[2] = mce->addr;
2946                 banks[3] = mce->misc;
2947                 banks[1] = mce->status;
2948         } else
2949                 banks[1] |= MCI_STATUS_OVER;
2950         return 0;
2951 }
2952
2953 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2954                                                struct kvm_vcpu_events *events)
2955 {
2956         process_nmi(vcpu);
2957         events->exception.injected =
2958                 vcpu->arch.exception.pending &&
2959                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2960         events->exception.nr = vcpu->arch.exception.nr;
2961         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2962         events->exception.pad = 0;
2963         events->exception.error_code = vcpu->arch.exception.error_code;
2964
2965         events->interrupt.injected =
2966                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2967         events->interrupt.nr = vcpu->arch.interrupt.nr;
2968         events->interrupt.soft = 0;
2969         events->interrupt.shadow =
2970                 kvm_x86_ops->get_interrupt_shadow(vcpu,
2971                         KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2972
2973         events->nmi.injected = vcpu->arch.nmi_injected;
2974         events->nmi.pending = vcpu->arch.nmi_pending != 0;
2975         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2976         events->nmi.pad = 0;
2977
2978         events->sipi_vector = 0; /* never valid when reporting to user space */
2979
2980         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2981                          | KVM_VCPUEVENT_VALID_SHADOW);
2982         memset(&events->reserved, 0, sizeof(events->reserved));
2983 }
2984
2985 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2986                                               struct kvm_vcpu_events *events)
2987 {
2988         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2989                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2990                               | KVM_VCPUEVENT_VALID_SHADOW))
2991                 return -EINVAL;
2992
2993         process_nmi(vcpu);
2994         vcpu->arch.exception.pending = events->exception.injected;
2995         vcpu->arch.exception.nr = events->exception.nr;
2996         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2997         vcpu->arch.exception.error_code = events->exception.error_code;
2998
2999         vcpu->arch.interrupt.pending = events->interrupt.injected;
3000         vcpu->arch.interrupt.nr = events->interrupt.nr;
3001         vcpu->arch.interrupt.soft = events->interrupt.soft;
3002         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3003                 kvm_x86_ops->set_interrupt_shadow(vcpu,
3004                                                   events->interrupt.shadow);
3005
3006         vcpu->arch.nmi_injected = events->nmi.injected;
3007         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3008                 vcpu->arch.nmi_pending = events->nmi.pending;
3009         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3010
3011         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3012             kvm_vcpu_has_lapic(vcpu))
3013                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3014
3015         kvm_make_request(KVM_REQ_EVENT, vcpu);
3016
3017         return 0;
3018 }
3019
3020 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3021                                              struct kvm_debugregs *dbgregs)
3022 {
3023         unsigned long val;
3024
3025         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3026         _kvm_get_dr(vcpu, 6, &val);
3027         dbgregs->dr6 = val;
3028         dbgregs->dr7 = vcpu->arch.dr7;
3029         dbgregs->flags = 0;
3030         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3031 }
3032
3033 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3034                                             struct kvm_debugregs *dbgregs)
3035 {
3036         if (dbgregs->flags)
3037                 return -EINVAL;
3038
3039         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3040         vcpu->arch.dr6 = dbgregs->dr6;
3041         kvm_update_dr6(vcpu);
3042         vcpu->arch.dr7 = dbgregs->dr7;
3043         kvm_update_dr7(vcpu);
3044
3045         return 0;
3046 }
3047
3048 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3049                                          struct kvm_xsave *guest_xsave)
3050 {
3051         if (cpu_has_xsave) {
3052                 memcpy(guest_xsave->region,
3053                         &vcpu->arch.guest_fpu.state->xsave,
3054                         vcpu->arch.guest_xstate_size);
3055                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3056                         vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3057         } else {
3058                 memcpy(guest_xsave->region,
3059                         &vcpu->arch.guest_fpu.state->fxsave,
3060                         sizeof(struct i387_fxsave_struct));
3061                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3062                         XSTATE_FPSSE;
3063         }
3064 }
3065
3066 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3067                                         struct kvm_xsave *guest_xsave)
3068 {
3069         u64 xstate_bv =
3070                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3071
3072         if (cpu_has_xsave) {
3073                 /*
3074                  * Here we allow setting states that are not present in
3075                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3076                  * with old userspace.
3077                  */
3078                 if (xstate_bv & ~kvm_supported_xcr0())
3079                         return -EINVAL;
3080                 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3081                         guest_xsave->region, vcpu->arch.guest_xstate_size);
3082         } else {
3083                 if (xstate_bv & ~XSTATE_FPSSE)
3084                         return -EINVAL;
3085                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3086                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
3087         }
3088         return 0;
3089 }
3090
3091 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3092                                         struct kvm_xcrs *guest_xcrs)
3093 {
3094         if (!cpu_has_xsave) {
3095                 guest_xcrs->nr_xcrs = 0;
3096                 return;
3097         }
3098
3099         guest_xcrs->nr_xcrs = 1;
3100         guest_xcrs->flags = 0;
3101         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3102         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3103 }
3104
3105 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3106                                        struct kvm_xcrs *guest_xcrs)
3107 {
3108         int i, r = 0;
3109
3110         if (!cpu_has_xsave)
3111                 return -EINVAL;
3112
3113         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3114                 return -EINVAL;
3115
3116         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3117                 /* Only support XCR0 currently */
3118                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3119                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3120                                 guest_xcrs->xcrs[i].value);
3121                         break;
3122                 }
3123         if (r)
3124                 r = -EINVAL;
3125         return r;
3126 }
3127
3128 /*
3129  * kvm_set_guest_paused() indicates to the guest kernel that it has been
3130  * stopped by the hypervisor.  This function will be called from the host only.
3131  * EINVAL is returned when the host attempts to set the flag for a guest that
3132  * does not support pv clocks.
3133  */
3134 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3135 {
3136         if (!vcpu->arch.pv_time_enabled)
3137                 return -EINVAL;
3138         vcpu->arch.pvclock_set_guest_stopped_request = true;
3139         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3140         return 0;
3141 }
3142
3143 long kvm_arch_vcpu_ioctl(struct file *filp,
3144                          unsigned int ioctl, unsigned long arg)
3145 {
3146         struct kvm_vcpu *vcpu = filp->private_data;
3147         void __user *argp = (void __user *)arg;
3148         int r;
3149         union {
3150                 struct kvm_lapic_state *lapic;
3151                 struct kvm_xsave *xsave;
3152                 struct kvm_xcrs *xcrs;
3153                 void *buffer;
3154         } u;
3155
3156         u.buffer = NULL;
3157         switch (ioctl) {
3158         case KVM_GET_LAPIC: {
3159                 r = -EINVAL;
3160                 if (!vcpu->arch.apic)
3161                         goto out;
3162                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3163
3164                 r = -ENOMEM;
3165                 if (!u.lapic)
3166                         goto out;
3167                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3168                 if (r)
3169                         goto out;
3170                 r = -EFAULT;
3171                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3172                         goto out;
3173                 r = 0;
3174                 break;
3175         }
3176         case KVM_SET_LAPIC: {
3177                 r = -EINVAL;
3178                 if (!vcpu->arch.apic)
3179                         goto out;
3180                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3181                 if (IS_ERR(u.lapic))
3182                         return PTR_ERR(u.lapic);
3183
3184                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3185                 break;
3186         }
3187         case KVM_INTERRUPT: {
3188                 struct kvm_interrupt irq;
3189
3190                 r = -EFAULT;
3191                 if (copy_from_user(&irq, argp, sizeof irq))
3192                         goto out;
3193                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3194                 break;
3195         }
3196         case KVM_NMI: {
3197                 r = kvm_vcpu_ioctl_nmi(vcpu);
3198                 break;
3199         }
3200         case KVM_SET_CPUID: {
3201                 struct kvm_cpuid __user *cpuid_arg = argp;
3202                 struct kvm_cpuid cpuid;
3203
3204                 r = -EFAULT;
3205                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3206                         goto out;
3207                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3208                 break;
3209         }
3210         case KVM_SET_CPUID2: {
3211                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3212                 struct kvm_cpuid2 cpuid;
3213
3214                 r = -EFAULT;
3215                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3216                         goto out;
3217                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3218                                               cpuid_arg->entries);
3219                 break;
3220         }
3221         case KVM_GET_CPUID2: {
3222                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3223                 struct kvm_cpuid2 cpuid;
3224
3225                 r = -EFAULT;
3226                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3227                         goto out;
3228                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3229                                               cpuid_arg->entries);
3230                 if (r)
3231                         goto out;
3232                 r = -EFAULT;
3233                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3234                         goto out;
3235                 r = 0;
3236                 break;
3237         }
3238         case KVM_GET_MSRS:
3239                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3240                 break;
3241         case KVM_SET_MSRS:
3242                 r = msr_io(vcpu, argp, do_set_msr, 0);
3243                 break;
3244         case KVM_TPR_ACCESS_REPORTING: {
3245                 struct kvm_tpr_access_ctl tac;
3246
3247                 r = -EFAULT;
3248                 if (copy_from_user(&tac, argp, sizeof tac))
3249                         goto out;
3250                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3251                 if (r)
3252                         goto out;
3253                 r = -EFAULT;
3254                 if (copy_to_user(argp, &tac, sizeof tac))
3255                         goto out;
3256                 r = 0;
3257                 break;
3258         };
3259         case KVM_SET_VAPIC_ADDR: {
3260                 struct kvm_vapic_addr va;
3261
3262                 r = -EINVAL;
3263                 if (!irqchip_in_kernel(vcpu->kvm))
3264                         goto out;
3265                 r = -EFAULT;
3266                 if (copy_from_user(&va, argp, sizeof va))
3267                         goto out;
3268                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3269                 break;
3270         }
3271         case KVM_X86_SETUP_MCE: {
3272                 u64 mcg_cap;
3273
3274                 r = -EFAULT;
3275                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3276                         goto out;
3277                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3278                 break;
3279         }
3280         case KVM_X86_SET_MCE: {
3281                 struct kvm_x86_mce mce;
3282
3283                 r = -EFAULT;
3284                 if (copy_from_user(&mce, argp, sizeof mce))
3285                         goto out;
3286                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3287                 break;
3288         }
3289         case KVM_GET_VCPU_EVENTS: {
3290                 struct kvm_vcpu_events events;
3291
3292                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3293
3294                 r = -EFAULT;
3295                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3296                         break;
3297                 r = 0;
3298                 break;
3299         }
3300         case KVM_SET_VCPU_EVENTS: {
3301                 struct kvm_vcpu_events events;
3302
3303                 r = -EFAULT;
3304                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3305                         break;
3306
3307                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &