2d7f65daa8d0983538c9fe6d577fcc06937e76c8
[sfrench/cifs-2.6.git] / arch / x86 / kvm / x86.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * derived from drivers/kvm/kvm_main.c
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright (C) 2008 Qumranet, Inc.
8  * Copyright IBM Corporation, 2008
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Amit Shah    <amit.shah@qumranet.com>
15  *   Ben-Ami Yassour <benami@il.ibm.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75  * - enable syscall per default because its emulated by KVM
76  * - enable LME and LMA per default on 64 bit KVM
77  */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
91
92 struct kvm_x86_ops *kvm_x86_ops;
93 EXPORT_SYMBOL_GPL(kvm_x86_ops);
94
95 static bool ignore_msrs = 0;
96 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
97
98 unsigned int min_timer_period_us = 500;
99 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
101 bool kvm_has_tsc_control;
102 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103 u32  kvm_max_guest_tsc_khz;
104 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
106 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107 static u32 tsc_tolerance_ppm = 250;
108 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
110 static bool backwards_tsc_observed = false;
111
112 #define KVM_NR_SHARED_MSRS 16
113
114 struct kvm_shared_msrs_global {
115         int nr;
116         u32 msrs[KVM_NR_SHARED_MSRS];
117 };
118
119 struct kvm_shared_msrs {
120         struct user_return_notifier urn;
121         bool registered;
122         struct kvm_shared_msr_values {
123                 u64 host;
124                 u64 curr;
125         } values[KVM_NR_SHARED_MSRS];
126 };
127
128 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
129 static struct kvm_shared_msrs __percpu *shared_msrs;
130
131 struct kvm_stats_debugfs_item debugfs_entries[] = {
132         { "pf_fixed", VCPU_STAT(pf_fixed) },
133         { "pf_guest", VCPU_STAT(pf_guest) },
134         { "tlb_flush", VCPU_STAT(tlb_flush) },
135         { "invlpg", VCPU_STAT(invlpg) },
136         { "exits", VCPU_STAT(exits) },
137         { "io_exits", VCPU_STAT(io_exits) },
138         { "mmio_exits", VCPU_STAT(mmio_exits) },
139         { "signal_exits", VCPU_STAT(signal_exits) },
140         { "irq_window", VCPU_STAT(irq_window_exits) },
141         { "nmi_window", VCPU_STAT(nmi_window_exits) },
142         { "halt_exits", VCPU_STAT(halt_exits) },
143         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
144         { "hypercalls", VCPU_STAT(hypercalls) },
145         { "request_irq", VCPU_STAT(request_irq_exits) },
146         { "irq_exits", VCPU_STAT(irq_exits) },
147         { "host_state_reload", VCPU_STAT(host_state_reload) },
148         { "efer_reload", VCPU_STAT(efer_reload) },
149         { "fpu_reload", VCPU_STAT(fpu_reload) },
150         { "insn_emulation", VCPU_STAT(insn_emulation) },
151         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
152         { "irq_injections", VCPU_STAT(irq_injections) },
153         { "nmi_injections", VCPU_STAT(nmi_injections) },
154         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158         { "mmu_flooded", VM_STAT(mmu_flooded) },
159         { "mmu_recycled", VM_STAT(mmu_recycled) },
160         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
161         { "mmu_unsync", VM_STAT(mmu_unsync) },
162         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
163         { "largepages", VM_STAT(lpages) },
164         { NULL }
165 };
166
167 u64 __read_mostly host_xcr0;
168
169 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
170
171 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
172 {
173         int i;
174         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175                 vcpu->arch.apf.gfns[i] = ~0;
176 }
177
178 static void kvm_on_user_return(struct user_return_notifier *urn)
179 {
180         unsigned slot;
181         struct kvm_shared_msrs *locals
182                 = container_of(urn, struct kvm_shared_msrs, urn);
183         struct kvm_shared_msr_values *values;
184
185         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
186                 values = &locals->values[slot];
187                 if (values->host != values->curr) {
188                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
189                         values->curr = values->host;
190                 }
191         }
192         locals->registered = false;
193         user_return_notifier_unregister(urn);
194 }
195
196 static void shared_msr_update(unsigned slot, u32 msr)
197 {
198         u64 value;
199         unsigned int cpu = smp_processor_id();
200         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
201
202         /* only read, and nobody should modify it at this time,
203          * so don't need lock */
204         if (slot >= shared_msrs_global.nr) {
205                 printk(KERN_ERR "kvm: invalid MSR slot!");
206                 return;
207         }
208         rdmsrl_safe(msr, &value);
209         smsr->values[slot].host = value;
210         smsr->values[slot].curr = value;
211 }
212
213 void kvm_define_shared_msr(unsigned slot, u32 msr)
214 {
215         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
216         if (slot >= shared_msrs_global.nr)
217                 shared_msrs_global.nr = slot + 1;
218         shared_msrs_global.msrs[slot] = msr;
219         /* we need ensured the shared_msr_global have been updated */
220         smp_wmb();
221 }
222 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
223
224 static void kvm_shared_msr_cpu_online(void)
225 {
226         unsigned i;
227
228         for (i = 0; i < shared_msrs_global.nr; ++i)
229                 shared_msr_update(i, shared_msrs_global.msrs[i]);
230 }
231
232 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
233 {
234         unsigned int cpu = smp_processor_id();
235         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
236
237         if (((value ^ smsr->values[slot].curr) & mask) == 0)
238                 return;
239         smsr->values[slot].curr = value;
240         wrmsrl(shared_msrs_global.msrs[slot], value);
241         if (!smsr->registered) {
242                 smsr->urn.on_user_return = kvm_on_user_return;
243                 user_return_notifier_register(&smsr->urn);
244                 smsr->registered = true;
245         }
246 }
247 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
248
249 static void drop_user_return_notifiers(void)
250 {
251         unsigned int cpu = smp_processor_id();
252         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
253
254         if (smsr->registered)
255                 kvm_on_user_return(&smsr->urn);
256 }
257
258 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
259 {
260         return vcpu->arch.apic_base;
261 }
262 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
263
264 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
265 {
266         u64 old_state = vcpu->arch.apic_base &
267                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268         u64 new_state = msr_info->data &
269                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
270         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
271                 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
272
273         if (!msr_info->host_initiated &&
274             ((msr_info->data & reserved_bits) != 0 ||
275              new_state == X2APIC_ENABLE ||
276              (new_state == MSR_IA32_APICBASE_ENABLE &&
277               old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
278              (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
279               old_state == 0)))
280                 return 1;
281
282         kvm_lapic_set_base(vcpu, msr_info->data);
283         return 0;
284 }
285 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
286
287 asmlinkage __visible void kvm_spurious_fault(void)
288 {
289         /* Fault while not rebooting.  We want the trace. */
290         BUG();
291 }
292 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
293
294 #define EXCPT_BENIGN            0
295 #define EXCPT_CONTRIBUTORY      1
296 #define EXCPT_PF                2
297
298 static int exception_class(int vector)
299 {
300         switch (vector) {
301         case PF_VECTOR:
302                 return EXCPT_PF;
303         case DE_VECTOR:
304         case TS_VECTOR:
305         case NP_VECTOR:
306         case SS_VECTOR:
307         case GP_VECTOR:
308                 return EXCPT_CONTRIBUTORY;
309         default:
310                 break;
311         }
312         return EXCPT_BENIGN;
313 }
314
315 #define EXCPT_FAULT             0
316 #define EXCPT_TRAP              1
317 #define EXCPT_ABORT             2
318 #define EXCPT_INTERRUPT         3
319
320 static int exception_type(int vector)
321 {
322         unsigned int mask;
323
324         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
325                 return EXCPT_INTERRUPT;
326
327         mask = 1 << vector;
328
329         /* #DB is trap, as instruction watchpoints are handled elsewhere */
330         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
331                 return EXCPT_TRAP;
332
333         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
334                 return EXCPT_ABORT;
335
336         /* Reserved exceptions will result in fault */
337         return EXCPT_FAULT;
338 }
339
340 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
341                 unsigned nr, bool has_error, u32 error_code,
342                 bool reinject)
343 {
344         u32 prev_nr;
345         int class1, class2;
346
347         kvm_make_request(KVM_REQ_EVENT, vcpu);
348
349         if (!vcpu->arch.exception.pending) {
350         queue:
351                 vcpu->arch.exception.pending = true;
352                 vcpu->arch.exception.has_error_code = has_error;
353                 vcpu->arch.exception.nr = nr;
354                 vcpu->arch.exception.error_code = error_code;
355                 vcpu->arch.exception.reinject = reinject;
356                 return;
357         }
358
359         /* to check exception */
360         prev_nr = vcpu->arch.exception.nr;
361         if (prev_nr == DF_VECTOR) {
362                 /* triple fault -> shutdown */
363                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
364                 return;
365         }
366         class1 = exception_class(prev_nr);
367         class2 = exception_class(nr);
368         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
369                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
370                 /* generate double fault per SDM Table 5-5 */
371                 vcpu->arch.exception.pending = true;
372                 vcpu->arch.exception.has_error_code = true;
373                 vcpu->arch.exception.nr = DF_VECTOR;
374                 vcpu->arch.exception.error_code = 0;
375         } else
376                 /* replace previous exception with a new one in a hope
377                    that instruction re-execution will regenerate lost
378                    exception */
379                 goto queue;
380 }
381
382 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
383 {
384         kvm_multiple_exception(vcpu, nr, false, 0, false);
385 }
386 EXPORT_SYMBOL_GPL(kvm_queue_exception);
387
388 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
389 {
390         kvm_multiple_exception(vcpu, nr, false, 0, true);
391 }
392 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
393
394 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
395 {
396         if (err)
397                 kvm_inject_gp(vcpu, 0);
398         else
399                 kvm_x86_ops->skip_emulated_instruction(vcpu);
400 }
401 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
402
403 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
404 {
405         ++vcpu->stat.pf_guest;
406         vcpu->arch.cr2 = fault->address;
407         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
408 }
409 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
410
411 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
412 {
413         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
414                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
415         else
416                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
417
418         return fault->nested_page_fault;
419 }
420
421 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
422 {
423         atomic_inc(&vcpu->arch.nmi_queued);
424         kvm_make_request(KVM_REQ_NMI, vcpu);
425 }
426 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
427
428 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
429 {
430         kvm_multiple_exception(vcpu, nr, true, error_code, false);
431 }
432 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
433
434 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
435 {
436         kvm_multiple_exception(vcpu, nr, true, error_code, true);
437 }
438 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
439
440 /*
441  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
442  * a #GP and return false.
443  */
444 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
445 {
446         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
447                 return true;
448         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
449         return false;
450 }
451 EXPORT_SYMBOL_GPL(kvm_require_cpl);
452
453 /*
454  * This function will be used to read from the physical memory of the currently
455  * running guest. The difference to kvm_read_guest_page is that this function
456  * can read from guest physical or from the guest's guest physical memory.
457  */
458 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
459                             gfn_t ngfn, void *data, int offset, int len,
460                             u32 access)
461 {
462         struct x86_exception exception;
463         gfn_t real_gfn;
464         gpa_t ngpa;
465
466         ngpa     = gfn_to_gpa(ngfn);
467         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
468         if (real_gfn == UNMAPPED_GVA)
469                 return -EFAULT;
470
471         real_gfn = gpa_to_gfn(real_gfn);
472
473         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
474 }
475 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
476
477 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
478                                void *data, int offset, int len, u32 access)
479 {
480         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
481                                        data, offset, len, access);
482 }
483
484 /*
485  * Load the pae pdptrs.  Return true is they are all valid.
486  */
487 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
488 {
489         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
490         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
491         int i;
492         int ret;
493         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
494
495         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
496                                       offset * sizeof(u64), sizeof(pdpte),
497                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
498         if (ret < 0) {
499                 ret = 0;
500                 goto out;
501         }
502         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
503                 if (is_present_gpte(pdpte[i]) &&
504                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
505                         ret = 0;
506                         goto out;
507                 }
508         }
509         ret = 1;
510
511         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
512         __set_bit(VCPU_EXREG_PDPTR,
513                   (unsigned long *)&vcpu->arch.regs_avail);
514         __set_bit(VCPU_EXREG_PDPTR,
515                   (unsigned long *)&vcpu->arch.regs_dirty);
516 out:
517
518         return ret;
519 }
520 EXPORT_SYMBOL_GPL(load_pdptrs);
521
522 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
523 {
524         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
525         bool changed = true;
526         int offset;
527         gfn_t gfn;
528         int r;
529
530         if (is_long_mode(vcpu) || !is_pae(vcpu))
531                 return false;
532
533         if (!test_bit(VCPU_EXREG_PDPTR,
534                       (unsigned long *)&vcpu->arch.regs_avail))
535                 return true;
536
537         gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
538         offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
539         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
540                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
541         if (r < 0)
542                 goto out;
543         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
544 out:
545
546         return changed;
547 }
548
549 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
550 {
551         unsigned long old_cr0 = kvm_read_cr0(vcpu);
552         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
553                                     X86_CR0_CD | X86_CR0_NW;
554
555         cr0 |= X86_CR0_ET;
556
557 #ifdef CONFIG_X86_64
558         if (cr0 & 0xffffffff00000000UL)
559                 return 1;
560 #endif
561
562         cr0 &= ~CR0_RESERVED_BITS;
563
564         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
565                 return 1;
566
567         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
568                 return 1;
569
570         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
571 #ifdef CONFIG_X86_64
572                 if ((vcpu->arch.efer & EFER_LME)) {
573                         int cs_db, cs_l;
574
575                         if (!is_pae(vcpu))
576                                 return 1;
577                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
578                         if (cs_l)
579                                 return 1;
580                 } else
581 #endif
582                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
583                                                  kvm_read_cr3(vcpu)))
584                         return 1;
585         }
586
587         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
588                 return 1;
589
590         kvm_x86_ops->set_cr0(vcpu, cr0);
591
592         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
593                 kvm_clear_async_pf_completion_queue(vcpu);
594                 kvm_async_pf_hash_reset(vcpu);
595         }
596
597         if ((cr0 ^ old_cr0) & update_bits)
598                 kvm_mmu_reset_context(vcpu);
599         return 0;
600 }
601 EXPORT_SYMBOL_GPL(kvm_set_cr0);
602
603 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
604 {
605         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
606 }
607 EXPORT_SYMBOL_GPL(kvm_lmsw);
608
609 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
610 {
611         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
612                         !vcpu->guest_xcr0_loaded) {
613                 /* kvm_set_xcr() also depends on this */
614                 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
615                 vcpu->guest_xcr0_loaded = 1;
616         }
617 }
618
619 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
620 {
621         if (vcpu->guest_xcr0_loaded) {
622                 if (vcpu->arch.xcr0 != host_xcr0)
623                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
624                 vcpu->guest_xcr0_loaded = 0;
625         }
626 }
627
628 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
629 {
630         u64 xcr0 = xcr;
631         u64 old_xcr0 = vcpu->arch.xcr0;
632         u64 valid_bits;
633
634         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
635         if (index != XCR_XFEATURE_ENABLED_MASK)
636                 return 1;
637         if (!(xcr0 & XSTATE_FP))
638                 return 1;
639         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
640                 return 1;
641
642         /*
643          * Do not allow the guest to set bits that we do not support
644          * saving.  However, xcr0 bit 0 is always set, even if the
645          * emulated CPU does not support XSAVE (see fx_init).
646          */
647         valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
648         if (xcr0 & ~valid_bits)
649                 return 1;
650
651         if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
652                 return 1;
653
654         kvm_put_guest_xcr0(vcpu);
655         vcpu->arch.xcr0 = xcr0;
656
657         if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
658                 kvm_update_cpuid(vcpu);
659         return 0;
660 }
661
662 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
663 {
664         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
665             __kvm_set_xcr(vcpu, index, xcr)) {
666                 kvm_inject_gp(vcpu, 0);
667                 return 1;
668         }
669         return 0;
670 }
671 EXPORT_SYMBOL_GPL(kvm_set_xcr);
672
673 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
674 {
675         unsigned long old_cr4 = kvm_read_cr4(vcpu);
676         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
677                                    X86_CR4_PAE | X86_CR4_SMEP;
678         if (cr4 & CR4_RESERVED_BITS)
679                 return 1;
680
681         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
682                 return 1;
683
684         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
685                 return 1;
686
687         if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
688                 return 1;
689
690         if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
691                 return 1;
692
693         if (is_long_mode(vcpu)) {
694                 if (!(cr4 & X86_CR4_PAE))
695                         return 1;
696         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
697                    && ((cr4 ^ old_cr4) & pdptr_bits)
698                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
699                                    kvm_read_cr3(vcpu)))
700                 return 1;
701
702         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
703                 if (!guest_cpuid_has_pcid(vcpu))
704                         return 1;
705
706                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
707                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
708                         return 1;
709         }
710
711         if (kvm_x86_ops->set_cr4(vcpu, cr4))
712                 return 1;
713
714         if (((cr4 ^ old_cr4) & pdptr_bits) ||
715             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
716                 kvm_mmu_reset_context(vcpu);
717
718         if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
719                 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
720
721         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
722                 kvm_update_cpuid(vcpu);
723
724         return 0;
725 }
726 EXPORT_SYMBOL_GPL(kvm_set_cr4);
727
728 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
729 {
730         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
731                 kvm_mmu_sync_roots(vcpu);
732                 kvm_mmu_flush_tlb(vcpu);
733                 return 0;
734         }
735
736         if (is_long_mode(vcpu)) {
737                 if (cr3 & CR3_L_MODE_RESERVED_BITS)
738                         return 1;
739         } else if (is_pae(vcpu) && is_paging(vcpu) &&
740                    !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
741                 return 1;
742
743         vcpu->arch.cr3 = cr3;
744         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
745         kvm_mmu_new_cr3(vcpu);
746         return 0;
747 }
748 EXPORT_SYMBOL_GPL(kvm_set_cr3);
749
750 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
751 {
752         if (cr8 & CR8_RESERVED_BITS)
753                 return 1;
754         if (irqchip_in_kernel(vcpu->kvm))
755                 kvm_lapic_set_tpr(vcpu, cr8);
756         else
757                 vcpu->arch.cr8 = cr8;
758         return 0;
759 }
760 EXPORT_SYMBOL_GPL(kvm_set_cr8);
761
762 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
763 {
764         if (irqchip_in_kernel(vcpu->kvm))
765                 return kvm_lapic_get_cr8(vcpu);
766         else
767                 return vcpu->arch.cr8;
768 }
769 EXPORT_SYMBOL_GPL(kvm_get_cr8);
770
771 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
772 {
773         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
774                 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
775 }
776
777 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
778 {
779         unsigned long dr7;
780
781         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
782                 dr7 = vcpu->arch.guest_debug_dr7;
783         else
784                 dr7 = vcpu->arch.dr7;
785         kvm_x86_ops->set_dr7(vcpu, dr7);
786         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
787         if (dr7 & DR7_BP_EN_MASK)
788                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
789 }
790
791 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
792 {
793         u64 fixed = DR6_FIXED_1;
794
795         if (!guest_cpuid_has_rtm(vcpu))
796                 fixed |= DR6_RTM;
797         return fixed;
798 }
799
800 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
801 {
802         switch (dr) {
803         case 0 ... 3:
804                 vcpu->arch.db[dr] = val;
805                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
806                         vcpu->arch.eff_db[dr] = val;
807                 break;
808         case 4:
809                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
810                         return 1; /* #UD */
811                 /* fall through */
812         case 6:
813                 if (val & 0xffffffff00000000ULL)
814                         return -1; /* #GP */
815                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
816                 kvm_update_dr6(vcpu);
817                 break;
818         case 5:
819                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
820                         return 1; /* #UD */
821                 /* fall through */
822         default: /* 7 */
823                 if (val & 0xffffffff00000000ULL)
824                         return -1; /* #GP */
825                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
826                 kvm_update_dr7(vcpu);
827                 break;
828         }
829
830         return 0;
831 }
832
833 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
834 {
835         int res;
836
837         res = __kvm_set_dr(vcpu, dr, val);
838         if (res > 0)
839                 kvm_queue_exception(vcpu, UD_VECTOR);
840         else if (res < 0)
841                 kvm_inject_gp(vcpu, 0);
842
843         return res;
844 }
845 EXPORT_SYMBOL_GPL(kvm_set_dr);
846
847 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
848 {
849         switch (dr) {
850         case 0 ... 3:
851                 *val = vcpu->arch.db[dr];
852                 break;
853         case 4:
854                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
855                         return 1;
856                 /* fall through */
857         case 6:
858                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
859                         *val = vcpu->arch.dr6;
860                 else
861                         *val = kvm_x86_ops->get_dr6(vcpu);
862                 break;
863         case 5:
864                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
865                         return 1;
866                 /* fall through */
867         default: /* 7 */
868                 *val = vcpu->arch.dr7;
869                 break;
870         }
871
872         return 0;
873 }
874
875 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
876 {
877         if (_kvm_get_dr(vcpu, dr, val)) {
878                 kvm_queue_exception(vcpu, UD_VECTOR);
879                 return 1;
880         }
881         return 0;
882 }
883 EXPORT_SYMBOL_GPL(kvm_get_dr);
884
885 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
886 {
887         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
888         u64 data;
889         int err;
890
891         err = kvm_pmu_read_pmc(vcpu, ecx, &data);
892         if (err)
893                 return err;
894         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
895         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
896         return err;
897 }
898 EXPORT_SYMBOL_GPL(kvm_rdpmc);
899
900 /*
901  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
902  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
903  *
904  * This list is modified at module load time to reflect the
905  * capabilities of the host cpu. This capabilities test skips MSRs that are
906  * kvm-specific. Those are put in the beginning of the list.
907  */
908
909 #define KVM_SAVE_MSRS_BEGIN     12
910 static u32 msrs_to_save[] = {
911         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
912         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
913         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
914         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
915         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
916         MSR_KVM_PV_EOI_EN,
917         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
918         MSR_STAR,
919 #ifdef CONFIG_X86_64
920         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
921 #endif
922         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
923         MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
924 };
925
926 static unsigned num_msrs_to_save;
927
928 static const u32 emulated_msrs[] = {
929         MSR_IA32_TSC_ADJUST,
930         MSR_IA32_TSCDEADLINE,
931         MSR_IA32_MISC_ENABLE,
932         MSR_IA32_MCG_STATUS,
933         MSR_IA32_MCG_CTL,
934 };
935
936 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
937 {
938         if (efer & efer_reserved_bits)
939                 return false;
940
941         if (efer & EFER_FFXSR) {
942                 struct kvm_cpuid_entry2 *feat;
943
944                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
945                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
946                         return false;
947         }
948
949         if (efer & EFER_SVME) {
950                 struct kvm_cpuid_entry2 *feat;
951
952                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
953                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
954                         return false;
955         }
956
957         return true;
958 }
959 EXPORT_SYMBOL_GPL(kvm_valid_efer);
960
961 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
962 {
963         u64 old_efer = vcpu->arch.efer;
964
965         if (!kvm_valid_efer(vcpu, efer))
966                 return 1;
967
968         if (is_paging(vcpu)
969             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
970                 return 1;
971
972         efer &= ~EFER_LMA;
973         efer |= vcpu->arch.efer & EFER_LMA;
974
975         kvm_x86_ops->set_efer(vcpu, efer);
976
977         /* Update reserved bits */
978         if ((efer ^ old_efer) & EFER_NX)
979                 kvm_mmu_reset_context(vcpu);
980
981         return 0;
982 }
983
984 void kvm_enable_efer_bits(u64 mask)
985 {
986        efer_reserved_bits &= ~mask;
987 }
988 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
989
990
991 /*
992  * Writes msr value into into the appropriate "register".
993  * Returns 0 on success, non-0 otherwise.
994  * Assumes vcpu_load() was already called.
995  */
996 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
997 {
998         return kvm_x86_ops->set_msr(vcpu, msr);
999 }
1000
1001 /*
1002  * Adapt set_msr() to msr_io()'s calling convention
1003  */
1004 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1005 {
1006         struct msr_data msr;
1007
1008         msr.data = *data;
1009         msr.index = index;
1010         msr.host_initiated = true;
1011         return kvm_set_msr(vcpu, &msr);
1012 }
1013
1014 #ifdef CONFIG_X86_64
1015 struct pvclock_gtod_data {
1016         seqcount_t      seq;
1017
1018         struct { /* extract of a clocksource struct */
1019                 int vclock_mode;
1020                 cycle_t cycle_last;
1021                 cycle_t mask;
1022                 u32     mult;
1023                 u32     shift;
1024         } clock;
1025
1026         u64             boot_ns;
1027         u64             nsec_base;
1028 };
1029
1030 static struct pvclock_gtod_data pvclock_gtod_data;
1031
1032 static void update_pvclock_gtod(struct timekeeper *tk)
1033 {
1034         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1035         u64 boot_ns;
1036
1037         boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
1038
1039         write_seqcount_begin(&vdata->seq);
1040
1041         /* copy pvclock gtod data */
1042         vdata->clock.vclock_mode        = tk->tkr.clock->archdata.vclock_mode;
1043         vdata->clock.cycle_last         = tk->tkr.cycle_last;
1044         vdata->clock.mask               = tk->tkr.mask;
1045         vdata->clock.mult               = tk->tkr.mult;
1046         vdata->clock.shift              = tk->tkr.shift;
1047
1048         vdata->boot_ns                  = boot_ns;
1049         vdata->nsec_base                = tk->tkr.xtime_nsec;
1050
1051         write_seqcount_end(&vdata->seq);
1052 }
1053 #endif
1054
1055
1056 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1057 {
1058         int version;
1059         int r;
1060         struct pvclock_wall_clock wc;
1061         struct timespec boot;
1062
1063         if (!wall_clock)
1064                 return;
1065
1066         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1067         if (r)
1068                 return;
1069
1070         if (version & 1)
1071                 ++version;  /* first time write, random junk */
1072
1073         ++version;
1074
1075         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1076
1077         /*
1078          * The guest calculates current wall clock time by adding
1079          * system time (updated by kvm_guest_time_update below) to the
1080          * wall clock specified here.  guest system time equals host
1081          * system time for us, thus we must fill in host boot time here.
1082          */
1083         getboottime(&boot);
1084
1085         if (kvm->arch.kvmclock_offset) {
1086                 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1087                 boot = timespec_sub(boot, ts);
1088         }
1089         wc.sec = boot.tv_sec;
1090         wc.nsec = boot.tv_nsec;
1091         wc.version = version;
1092
1093         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1094
1095         version++;
1096         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1097 }
1098
1099 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1100 {
1101         uint32_t quotient, remainder;
1102
1103         /* Don't try to replace with do_div(), this one calculates
1104          * "(dividend << 32) / divisor" */
1105         __asm__ ( "divl %4"
1106                   : "=a" (quotient), "=d" (remainder)
1107                   : "0" (0), "1" (dividend), "r" (divisor) );
1108         return quotient;
1109 }
1110
1111 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1112                                s8 *pshift, u32 *pmultiplier)
1113 {
1114         uint64_t scaled64;
1115         int32_t  shift = 0;
1116         uint64_t tps64;
1117         uint32_t tps32;
1118
1119         tps64 = base_khz * 1000LL;
1120         scaled64 = scaled_khz * 1000LL;
1121         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1122                 tps64 >>= 1;
1123                 shift--;
1124         }
1125
1126         tps32 = (uint32_t)tps64;
1127         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1128                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1129                         scaled64 >>= 1;
1130                 else
1131                         tps32 <<= 1;
1132                 shift++;
1133         }
1134
1135         *pshift = shift;
1136         *pmultiplier = div_frac(scaled64, tps32);
1137
1138         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1139                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
1140 }
1141
1142 static inline u64 get_kernel_ns(void)
1143 {
1144         return ktime_get_boot_ns();
1145 }
1146
1147 #ifdef CONFIG_X86_64
1148 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1149 #endif
1150
1151 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1152 unsigned long max_tsc_khz;
1153
1154 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1155 {
1156         return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1157                                    vcpu->arch.virtual_tsc_shift);
1158 }
1159
1160 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1161 {
1162         u64 v = (u64)khz * (1000000 + ppm);
1163         do_div(v, 1000000);
1164         return v;
1165 }
1166
1167 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1168 {
1169         u32 thresh_lo, thresh_hi;
1170         int use_scaling = 0;
1171
1172         /* tsc_khz can be zero if TSC calibration fails */
1173         if (this_tsc_khz == 0)
1174                 return;
1175
1176         /* Compute a scale to convert nanoseconds in TSC cycles */
1177         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1178                            &vcpu->arch.virtual_tsc_shift,
1179                            &vcpu->arch.virtual_tsc_mult);
1180         vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1181
1182         /*
1183          * Compute the variation in TSC rate which is acceptable
1184          * within the range of tolerance and decide if the
1185          * rate being applied is within that bounds of the hardware
1186          * rate.  If so, no scaling or compensation need be done.
1187          */
1188         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1189         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1190         if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1191                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1192                 use_scaling = 1;
1193         }
1194         kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1195 }
1196
1197 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1198 {
1199         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1200                                       vcpu->arch.virtual_tsc_mult,
1201                                       vcpu->arch.virtual_tsc_shift);
1202         tsc += vcpu->arch.this_tsc_write;
1203         return tsc;
1204 }
1205
1206 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1207 {
1208 #ifdef CONFIG_X86_64
1209         bool vcpus_matched;
1210         bool do_request = false;
1211         struct kvm_arch *ka = &vcpu->kvm->arch;
1212         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1213
1214         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1215                          atomic_read(&vcpu->kvm->online_vcpus));
1216
1217         if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1218                 if (!ka->use_master_clock)
1219                         do_request = 1;
1220
1221         if (!vcpus_matched && ka->use_master_clock)
1222                         do_request = 1;
1223
1224         if (do_request)
1225                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1226
1227         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1228                             atomic_read(&vcpu->kvm->online_vcpus),
1229                             ka->use_master_clock, gtod->clock.vclock_mode);
1230 #endif
1231 }
1232
1233 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1234 {
1235         u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1236         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1237 }
1238
1239 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1240 {
1241         struct kvm *kvm = vcpu->kvm;
1242         u64 offset, ns, elapsed;
1243         unsigned long flags;
1244         s64 usdiff;
1245         bool matched;
1246         bool already_matched;
1247         u64 data = msr->data;
1248
1249         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1250         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1251         ns = get_kernel_ns();
1252         elapsed = ns - kvm->arch.last_tsc_nsec;
1253
1254         if (vcpu->arch.virtual_tsc_khz) {
1255                 int faulted = 0;
1256
1257                 /* n.b - signed multiplication and division required */
1258                 usdiff = data - kvm->arch.last_tsc_write;
1259 #ifdef CONFIG_X86_64
1260                 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1261 #else
1262                 /* do_div() only does unsigned */
1263                 asm("1: idivl %[divisor]\n"
1264                     "2: xor %%edx, %%edx\n"
1265                     "   movl $0, %[faulted]\n"
1266                     "3:\n"
1267                     ".section .fixup,\"ax\"\n"
1268                     "4: movl $1, %[faulted]\n"
1269                     "   jmp  3b\n"
1270                     ".previous\n"
1271
1272                 _ASM_EXTABLE(1b, 4b)
1273
1274                 : "=A"(usdiff), [faulted] "=r" (faulted)
1275                 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1276
1277 #endif
1278                 do_div(elapsed, 1000);
1279                 usdiff -= elapsed;
1280                 if (usdiff < 0)
1281                         usdiff = -usdiff;
1282
1283                 /* idivl overflow => difference is larger than USEC_PER_SEC */
1284                 if (faulted)
1285                         usdiff = USEC_PER_SEC;
1286         } else
1287                 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1288
1289         /*
1290          * Special case: TSC write with a small delta (1 second) of virtual
1291          * cycle time against real time is interpreted as an attempt to
1292          * synchronize the CPU.
1293          *
1294          * For a reliable TSC, we can match TSC offsets, and for an unstable
1295          * TSC, we add elapsed time in this computation.  We could let the
1296          * compensation code attempt to catch up if we fall behind, but
1297          * it's better to try to match offsets from the beginning.
1298          */
1299         if (usdiff < USEC_PER_SEC &&
1300             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1301                 if (!check_tsc_unstable()) {
1302                         offset = kvm->arch.cur_tsc_offset;
1303                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1304                 } else {
1305                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1306                         data += delta;
1307                         offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1308                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1309                 }
1310                 matched = true;
1311                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1312         } else {
1313                 /*
1314                  * We split periods of matched TSC writes into generations.
1315                  * For each generation, we track the original measured
1316                  * nanosecond time, offset, and write, so if TSCs are in
1317                  * sync, we can match exact offset, and if not, we can match
1318                  * exact software computation in compute_guest_tsc()
1319                  *
1320                  * These values are tracked in kvm->arch.cur_xxx variables.
1321                  */
1322                 kvm->arch.cur_tsc_generation++;
1323                 kvm->arch.cur_tsc_nsec = ns;
1324                 kvm->arch.cur_tsc_write = data;
1325                 kvm->arch.cur_tsc_offset = offset;
1326                 matched = false;
1327                 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1328                          kvm->arch.cur_tsc_generation, data);
1329         }
1330
1331         /*
1332          * We also track th most recent recorded KHZ, write and time to
1333          * allow the matching interval to be extended at each write.
1334          */
1335         kvm->arch.last_tsc_nsec = ns;
1336         kvm->arch.last_tsc_write = data;
1337         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1338
1339         vcpu->arch.last_guest_tsc = data;
1340
1341         /* Keep track of which generation this VCPU has synchronized to */
1342         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1343         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1344         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1345
1346         if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1347                 update_ia32_tsc_adjust_msr(vcpu, offset);
1348         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1349         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1350
1351         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1352         if (!matched) {
1353                 kvm->arch.nr_vcpus_matched_tsc = 0;
1354         } else if (!already_matched) {
1355                 kvm->arch.nr_vcpus_matched_tsc++;
1356         }
1357
1358         kvm_track_tsc_matching(vcpu);
1359         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1360 }
1361
1362 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1363
1364 #ifdef CONFIG_X86_64
1365
1366 static cycle_t read_tsc(void)
1367 {
1368         cycle_t ret;
1369         u64 last;
1370
1371         /*
1372          * Empirically, a fence (of type that depends on the CPU)
1373          * before rdtsc is enough to ensure that rdtsc is ordered
1374          * with respect to loads.  The various CPU manuals are unclear
1375          * as to whether rdtsc can be reordered with later loads,
1376          * but no one has ever seen it happen.
1377          */
1378         rdtsc_barrier();
1379         ret = (cycle_t)vget_cycles();
1380
1381         last = pvclock_gtod_data.clock.cycle_last;
1382
1383         if (likely(ret >= last))
1384                 return ret;
1385
1386         /*
1387          * GCC likes to generate cmov here, but this branch is extremely
1388          * predictable (it's just a funciton of time and the likely is
1389          * very likely) and there's a data dependence, so force GCC
1390          * to generate a branch instead.  I don't barrier() because
1391          * we don't actually need a barrier, and if this function
1392          * ever gets inlined it will generate worse code.
1393          */
1394         asm volatile ("");
1395         return last;
1396 }
1397
1398 static inline u64 vgettsc(cycle_t *cycle_now)
1399 {
1400         long v;
1401         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1402
1403         *cycle_now = read_tsc();
1404
1405         v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1406         return v * gtod->clock.mult;
1407 }
1408
1409 static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
1410 {
1411         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1412         unsigned long seq;
1413         int mode;
1414         u64 ns;
1415
1416         do {
1417                 seq = read_seqcount_begin(&gtod->seq);
1418                 mode = gtod->clock.vclock_mode;
1419                 ns = gtod->nsec_base;
1420                 ns += vgettsc(cycle_now);
1421                 ns >>= gtod->clock.shift;
1422                 ns += gtod->boot_ns;
1423         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1424         *t = ns;
1425
1426         return mode;
1427 }
1428
1429 /* returns true if host is using tsc clocksource */
1430 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1431 {
1432         /* checked again under seqlock below */
1433         if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1434                 return false;
1435
1436         return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
1437 }
1438 #endif
1439
1440 /*
1441  *
1442  * Assuming a stable TSC across physical CPUS, and a stable TSC
1443  * across virtual CPUs, the following condition is possible.
1444  * Each numbered line represents an event visible to both
1445  * CPUs at the next numbered event.
1446  *
1447  * "timespecX" represents host monotonic time. "tscX" represents
1448  * RDTSC value.
1449  *
1450  *              VCPU0 on CPU0           |       VCPU1 on CPU1
1451  *
1452  * 1.  read timespec0,tsc0
1453  * 2.                                   | timespec1 = timespec0 + N
1454  *                                      | tsc1 = tsc0 + M
1455  * 3. transition to guest               | transition to guest
1456  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1457  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
1458  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1459  *
1460  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1461  *
1462  *      - ret0 < ret1
1463  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1464  *              ...
1465  *      - 0 < N - M => M < N
1466  *
1467  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1468  * always the case (the difference between two distinct xtime instances
1469  * might be smaller then the difference between corresponding TSC reads,
1470  * when updating guest vcpus pvclock areas).
1471  *
1472  * To avoid that problem, do not allow visibility of distinct
1473  * system_timestamp/tsc_timestamp values simultaneously: use a master
1474  * copy of host monotonic time values. Update that master copy
1475  * in lockstep.
1476  *
1477  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1478  *
1479  */
1480
1481 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1482 {
1483 #ifdef CONFIG_X86_64
1484         struct kvm_arch *ka = &kvm->arch;
1485         int vclock_mode;
1486         bool host_tsc_clocksource, vcpus_matched;
1487
1488         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1489                         atomic_read(&kvm->online_vcpus));
1490
1491         /*
1492          * If the host uses TSC clock, then passthrough TSC as stable
1493          * to the guest.
1494          */
1495         host_tsc_clocksource = kvm_get_time_and_clockread(
1496                                         &ka->master_kernel_ns,
1497                                         &ka->master_cycle_now);
1498
1499         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1500                                 && !backwards_tsc_observed;
1501
1502         if (ka->use_master_clock)
1503                 atomic_set(&kvm_guest_has_master_clock, 1);
1504
1505         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1506         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1507                                         vcpus_matched);
1508 #endif
1509 }
1510
1511 static void kvm_gen_update_masterclock(struct kvm *kvm)
1512 {
1513 #ifdef CONFIG_X86_64
1514         int i;
1515         struct kvm_vcpu *vcpu;
1516         struct kvm_arch *ka = &kvm->arch;
1517
1518         spin_lock(&ka->pvclock_gtod_sync_lock);
1519         kvm_make_mclock_inprogress_request(kvm);
1520         /* no guest entries from this point */
1521         pvclock_update_vm_gtod_copy(kvm);
1522
1523         kvm_for_each_vcpu(i, vcpu, kvm)
1524                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1525
1526         /* guest entries allowed */
1527         kvm_for_each_vcpu(i, vcpu, kvm)
1528                 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1529
1530         spin_unlock(&ka->pvclock_gtod_sync_lock);
1531 #endif
1532 }
1533
1534 static int kvm_guest_time_update(struct kvm_vcpu *v)
1535 {
1536         unsigned long flags, this_tsc_khz;
1537         struct kvm_vcpu_arch *vcpu = &v->arch;
1538         struct kvm_arch *ka = &v->kvm->arch;
1539         s64 kernel_ns;
1540         u64 tsc_timestamp, host_tsc;
1541         struct pvclock_vcpu_time_info guest_hv_clock;
1542         u8 pvclock_flags;
1543         bool use_master_clock;
1544
1545         kernel_ns = 0;
1546         host_tsc = 0;
1547
1548         /*
1549          * If the host uses TSC clock, then passthrough TSC as stable
1550          * to the guest.
1551          */
1552         spin_lock(&ka->pvclock_gtod_sync_lock);
1553         use_master_clock = ka->use_master_clock;
1554         if (use_master_clock) {
1555                 host_tsc = ka->master_cycle_now;
1556                 kernel_ns = ka->master_kernel_ns;
1557         }
1558         spin_unlock(&ka->pvclock_gtod_sync_lock);
1559
1560         /* Keep irq disabled to prevent changes to the clock */
1561         local_irq_save(flags);
1562         this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1563         if (unlikely(this_tsc_khz == 0)) {
1564                 local_irq_restore(flags);
1565                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1566                 return 1;
1567         }
1568         if (!use_master_clock) {
1569                 host_tsc = native_read_tsc();
1570                 kernel_ns = get_kernel_ns();
1571         }
1572
1573         tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1574
1575         /*
1576          * We may have to catch up the TSC to match elapsed wall clock
1577          * time for two reasons, even if kvmclock is used.
1578          *   1) CPU could have been running below the maximum TSC rate
1579          *   2) Broken TSC compensation resets the base at each VCPU
1580          *      entry to avoid unknown leaps of TSC even when running
1581          *      again on the same CPU.  This may cause apparent elapsed
1582          *      time to disappear, and the guest to stand still or run
1583          *      very slowly.
1584          */
1585         if (vcpu->tsc_catchup) {
1586                 u64 tsc = compute_guest_tsc(v, kernel_ns);
1587                 if (tsc > tsc_timestamp) {
1588                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1589                         tsc_timestamp = tsc;
1590                 }
1591         }
1592
1593         local_irq_restore(flags);
1594
1595         if (!vcpu->pv_time_enabled)
1596                 return 0;
1597
1598         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1599                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1600                                    &vcpu->hv_clock.tsc_shift,
1601                                    &vcpu->hv_clock.tsc_to_system_mul);
1602                 vcpu->hw_tsc_khz = this_tsc_khz;
1603         }
1604
1605         /* With all the info we got, fill in the values */
1606         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1607         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1608         vcpu->last_guest_tsc = tsc_timestamp;
1609
1610         /*
1611          * The interface expects us to write an even number signaling that the
1612          * update is finished. Since the guest won't see the intermediate
1613          * state, we just increase by 2 at the end.
1614          */
1615         vcpu->hv_clock.version += 2;
1616
1617         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1618                 &guest_hv_clock, sizeof(guest_hv_clock))))
1619                 return 0;
1620
1621         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1622         pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1623
1624         if (vcpu->pvclock_set_guest_stopped_request) {
1625                 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1626                 vcpu->pvclock_set_guest_stopped_request = false;
1627         }
1628
1629         /* If the host uses TSC clocksource, then it is stable */
1630         if (use_master_clock)
1631                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1632
1633         vcpu->hv_clock.flags = pvclock_flags;
1634
1635         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1636                                 &vcpu->hv_clock,
1637                                 sizeof(vcpu->hv_clock));
1638         return 0;
1639 }
1640
1641 /*
1642  * kvmclock updates which are isolated to a given vcpu, such as
1643  * vcpu->cpu migration, should not allow system_timestamp from
1644  * the rest of the vcpus to remain static. Otherwise ntp frequency
1645  * correction applies to one vcpu's system_timestamp but not
1646  * the others.
1647  *
1648  * So in those cases, request a kvmclock update for all vcpus.
1649  * We need to rate-limit these requests though, as they can
1650  * considerably slow guests that have a large number of vcpus.
1651  * The time for a remote vcpu to update its kvmclock is bound
1652  * by the delay we use to rate-limit the updates.
1653  */
1654
1655 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1656
1657 static void kvmclock_update_fn(struct work_struct *work)
1658 {
1659         int i;
1660         struct delayed_work *dwork = to_delayed_work(work);
1661         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1662                                            kvmclock_update_work);
1663         struct kvm *kvm = container_of(ka, struct kvm, arch);
1664         struct kvm_vcpu *vcpu;
1665
1666         kvm_for_each_vcpu(i, vcpu, kvm) {
1667                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1668                 kvm_vcpu_kick(vcpu);
1669         }
1670 }
1671
1672 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1673 {
1674         struct kvm *kvm = v->kvm;
1675
1676         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1677         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1678                                         KVMCLOCK_UPDATE_DELAY);
1679 }
1680
1681 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1682
1683 static void kvmclock_sync_fn(struct work_struct *work)
1684 {
1685         struct delayed_work *dwork = to_delayed_work(work);
1686         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1687                                            kvmclock_sync_work);
1688         struct kvm *kvm = container_of(ka, struct kvm, arch);
1689
1690         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1691         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1692                                         KVMCLOCK_SYNC_PERIOD);
1693 }
1694
1695 static bool msr_mtrr_valid(unsigned msr)
1696 {
1697         switch (msr) {
1698         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1699         case MSR_MTRRfix64K_00000:
1700         case MSR_MTRRfix16K_80000:
1701         case MSR_MTRRfix16K_A0000:
1702         case MSR_MTRRfix4K_C0000:
1703         case MSR_MTRRfix4K_C8000:
1704         case MSR_MTRRfix4K_D0000:
1705         case MSR_MTRRfix4K_D8000:
1706         case MSR_MTRRfix4K_E0000:
1707         case MSR_MTRRfix4K_E8000:
1708         case MSR_MTRRfix4K_F0000:
1709         case MSR_MTRRfix4K_F8000:
1710         case MSR_MTRRdefType:
1711         case MSR_IA32_CR_PAT:
1712                 return true;
1713         case 0x2f8:
1714                 return true;
1715         }
1716         return false;
1717 }
1718
1719 static bool valid_pat_type(unsigned t)
1720 {
1721         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1722 }
1723
1724 static bool valid_mtrr_type(unsigned t)
1725 {
1726         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1727 }
1728
1729 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1730 {
1731         int i;
1732         u64 mask;
1733
1734         if (!msr_mtrr_valid(msr))
1735                 return false;
1736
1737         if (msr == MSR_IA32_CR_PAT) {
1738                 for (i = 0; i < 8; i++)
1739                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1740                                 return false;
1741                 return true;
1742         } else if (msr == MSR_MTRRdefType) {
1743                 if (data & ~0xcff)
1744                         return false;
1745                 return valid_mtrr_type(data & 0xff);
1746         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1747                 for (i = 0; i < 8 ; i++)
1748                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1749                                 return false;
1750                 return true;
1751         }
1752
1753         /* variable MTRRs */
1754         WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1755
1756         mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
1757         if ((msr & 1) == 0) {
1758                 /* MTRR base */
1759                 if (!valid_mtrr_type(data & 0xff))
1760                         return false;
1761                 mask |= 0xf00;
1762         } else
1763                 /* MTRR mask */
1764                 mask |= 0x7ff;
1765         if (data & mask) {
1766                 kvm_inject_gp(vcpu, 0);
1767                 return false;
1768         }
1769
1770         return true;
1771 }
1772
1773 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1774 {
1775         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1776
1777         if (!mtrr_valid(vcpu, msr, data))
1778                 return 1;
1779
1780         if (msr == MSR_MTRRdefType) {
1781                 vcpu->arch.mtrr_state.def_type = data;
1782                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1783         } else if (msr == MSR_MTRRfix64K_00000)
1784                 p[0] = data;
1785         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1786                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1787         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1788                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1789         else if (msr == MSR_IA32_CR_PAT)
1790                 vcpu->arch.pat = data;
1791         else {  /* Variable MTRRs */
1792                 int idx, is_mtrr_mask;
1793                 u64 *pt;
1794
1795                 idx = (msr - 0x200) / 2;
1796                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1797                 if (!is_mtrr_mask)
1798                         pt =
1799                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1800                 else
1801                         pt =
1802                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1803                 *pt = data;
1804         }
1805
1806         kvm_mmu_reset_context(vcpu);
1807         return 0;
1808 }
1809
1810 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1811 {
1812         u64 mcg_cap = vcpu->arch.mcg_cap;
1813         unsigned bank_num = mcg_cap & 0xff;
1814
1815         switch (msr) {
1816         case MSR_IA32_MCG_STATUS:
1817                 vcpu->arch.mcg_status = data;
1818                 break;
1819         case MSR_IA32_MCG_CTL:
1820                 if (!(mcg_cap & MCG_CTL_P))
1821                         return 1;
1822                 if (data != 0 && data != ~(u64)0)
1823                         return -1;
1824                 vcpu->arch.mcg_ctl = data;
1825                 break;
1826         default:
1827                 if (msr >= MSR_IA32_MC0_CTL &&
1828                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1829                         u32 offset = msr - MSR_IA32_MC0_CTL;
1830                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1831                          * some Linux kernels though clear bit 10 in bank 4 to
1832                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1833                          * this to avoid an uncatched #GP in the guest
1834                          */
1835                         if ((offset & 0x3) == 0 &&
1836                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1837                                 return -1;
1838                         vcpu->arch.mce_banks[offset] = data;
1839                         break;
1840                 }
1841                 return 1;
1842         }
1843         return 0;
1844 }
1845
1846 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1847 {
1848         struct kvm *kvm = vcpu->kvm;
1849         int lm = is_long_mode(vcpu);
1850         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1851                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1852         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1853                 : kvm->arch.xen_hvm_config.blob_size_32;
1854         u32 page_num = data & ~PAGE_MASK;
1855         u64 page_addr = data & PAGE_MASK;
1856         u8 *page;
1857         int r;
1858
1859         r = -E2BIG;
1860         if (page_num >= blob_size)
1861                 goto out;
1862         r = -ENOMEM;
1863         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1864         if (IS_ERR(page)) {
1865                 r = PTR_ERR(page);
1866                 goto out;
1867         }
1868         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1869                 goto out_free;
1870         r = 0;
1871 out_free:
1872         kfree(page);
1873 out:
1874         return r;
1875 }
1876
1877 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1878 {
1879         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1880 }
1881
1882 static bool kvm_hv_msr_partition_wide(u32 msr)
1883 {
1884         bool r = false;
1885         switch (msr) {
1886         case HV_X64_MSR_GUEST_OS_ID:
1887         case HV_X64_MSR_HYPERCALL:
1888         case HV_X64_MSR_REFERENCE_TSC:
1889         case HV_X64_MSR_TIME_REF_COUNT:
1890                 r = true;
1891                 break;
1892         }
1893
1894         return r;
1895 }
1896
1897 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1898 {
1899         struct kvm *kvm = vcpu->kvm;
1900
1901         switch (msr) {
1902         case HV_X64_MSR_GUEST_OS_ID:
1903                 kvm->arch.hv_guest_os_id = data;
1904                 /* setting guest os id to zero disables hypercall page */
1905                 if (!kvm->arch.hv_guest_os_id)
1906                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1907                 break;
1908         case HV_X64_MSR_HYPERCALL: {
1909                 u64 gfn;
1910                 unsigned long addr;
1911                 u8 instructions[4];
1912
1913                 /* if guest os id is not set hypercall should remain disabled */
1914                 if (!kvm->arch.hv_guest_os_id)
1915                         break;
1916                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1917                         kvm->arch.hv_hypercall = data;
1918                         break;
1919                 }
1920                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1921                 addr = gfn_to_hva(kvm, gfn);
1922                 if (kvm_is_error_hva(addr))
1923                         return 1;
1924                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1925                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1926                 if (__copy_to_user((void __user *)addr, instructions, 4))
1927                         return 1;
1928                 kvm->arch.hv_hypercall = data;
1929                 mark_page_dirty(kvm, gfn);
1930                 break;
1931         }
1932         case HV_X64_MSR_REFERENCE_TSC: {
1933                 u64 gfn;
1934                 HV_REFERENCE_TSC_PAGE tsc_ref;
1935                 memset(&tsc_ref, 0, sizeof(tsc_ref));
1936                 kvm->arch.hv_tsc_page = data;
1937                 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1938                         break;
1939                 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1940                 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
1941                         &tsc_ref, sizeof(tsc_ref)))
1942                         return 1;
1943                 mark_page_dirty(kvm, gfn);
1944                 break;
1945         }
1946         default:
1947                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1948                             "data 0x%llx\n", msr, data);
1949                 return 1;
1950         }
1951         return 0;
1952 }
1953
1954 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1955 {
1956         switch (msr) {
1957         case HV_X64_MSR_APIC_ASSIST_PAGE: {
1958                 u64 gfn;
1959                 unsigned long addr;
1960
1961                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1962                         vcpu->arch.hv_vapic = data;
1963                         if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1964                                 return 1;
1965                         break;
1966                 }
1967                 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1968                 addr = gfn_to_hva(vcpu->kvm, gfn);
1969                 if (kvm_is_error_hva(addr))
1970                         return 1;
1971                 if (__clear_user((void __user *)addr, PAGE_SIZE))
1972                         return 1;
1973                 vcpu->arch.hv_vapic = data;
1974                 mark_page_dirty(vcpu->kvm, gfn);
1975                 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1976                         return 1;
1977                 break;
1978         }
1979         case HV_X64_MSR_EOI:
1980                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1981         case HV_X64_MSR_ICR:
1982                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1983         case HV_X64_MSR_TPR:
1984                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1985         default:
1986                 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1987                             "data 0x%llx\n", msr, data);
1988                 return 1;
1989         }
1990
1991         return 0;
1992 }
1993
1994 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1995 {
1996         gpa_t gpa = data & ~0x3f;
1997
1998         /* Bits 2:5 are reserved, Should be zero */
1999         if (data & 0x3c)
2000                 return 1;
2001
2002         vcpu->arch.apf.msr_val = data;
2003
2004         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2005                 kvm_clear_async_pf_completion_queue(vcpu);
2006                 kvm_async_pf_hash_reset(vcpu);
2007                 return 0;
2008         }
2009
2010         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2011                                         sizeof(u32)))
2012                 return 1;
2013
2014         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2015         kvm_async_pf_wakeup_all(vcpu);
2016         return 0;
2017 }
2018
2019 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2020 {
2021         vcpu->arch.pv_time_enabled = false;
2022 }
2023
2024 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2025 {
2026         u64 delta;
2027
2028         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2029                 return;
2030
2031         delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2032         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2033         vcpu->arch.st.accum_steal = delta;
2034 }
2035
2036 static void record_steal_time(struct kvm_vcpu *vcpu)
2037 {
2038         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2039                 return;
2040
2041         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2042                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2043                 return;
2044
2045         vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2046         vcpu->arch.st.steal.version += 2;
2047         vcpu->arch.st.accum_steal = 0;
2048
2049         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2050                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2051 }
2052
2053 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2054 {
2055         bool pr = false;
2056         u32 msr = msr_info->index;
2057         u64 data = msr_info->data;
2058
2059         switch (msr) {
2060         case MSR_AMD64_NB_CFG:
2061         case MSR_IA32_UCODE_REV:
2062         case MSR_IA32_UCODE_WRITE:
2063         case MSR_VM_HSAVE_PA:
2064         case MSR_AMD64_PATCH_LOADER:
2065         case MSR_AMD64_BU_CFG2:
2066                 break;
2067
2068         case MSR_EFER:
2069                 return set_efer(vcpu, data);
2070         case MSR_K7_HWCR:
2071                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2072                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2073                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2074                 data &= ~(u64)0x40000;  /* ignore Mc status write enable */
2075                 if (data != 0) {
2076                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2077                                     data);
2078                         return 1;
2079                 }
2080                 break;
2081         case MSR_FAM10H_MMIO_CONF_BASE:
2082                 if (data != 0) {
2083                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2084                                     "0x%llx\n", data);
2085                         return 1;
2086                 }
2087                 break;
2088         case MSR_IA32_DEBUGCTLMSR:
2089                 if (!data) {
2090                         /* We support the non-activated case already */
2091                         break;
2092                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2093                         /* Values other than LBR and BTF are vendor-specific,
2094                            thus reserved and should throw a #GP */
2095                         return 1;
2096                 }
2097                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2098                             __func__, data);
2099                 break;
2100         case 0x200 ... 0x2ff:
2101                 return set_msr_mtrr(vcpu, msr, data);
2102         case MSR_IA32_APICBASE:
2103                 return kvm_set_apic_base(vcpu, msr_info);
2104         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2105                 return kvm_x2apic_msr_write(vcpu, msr, data);
2106         case MSR_IA32_TSCDEADLINE:
2107                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2108                 break;
2109         case MSR_IA32_TSC_ADJUST:
2110                 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2111                         if (!msr_info->host_initiated) {
2112                                 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2113                                 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2114                         }
2115                         vcpu->arch.ia32_tsc_adjust_msr = data;
2116                 }
2117                 break;
2118         case MSR_IA32_MISC_ENABLE:
2119                 vcpu->arch.ia32_misc_enable_msr = data;
2120                 break;
2121         case MSR_KVM_WALL_CLOCK_NEW:
2122         case MSR_KVM_WALL_CLOCK:
2123                 vcpu->kvm->arch.wall_clock = data;
2124                 kvm_write_wall_clock(vcpu->kvm, data);
2125                 break;
2126         case MSR_KVM_SYSTEM_TIME_NEW:
2127         case MSR_KVM_SYSTEM_TIME: {
2128                 u64 gpa_offset;
2129                 kvmclock_reset(vcpu);
2130
2131                 vcpu->arch.time = data;
2132                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2133
2134                 /* we verify if the enable bit is set... */
2135                 if (!(data & 1))
2136                         break;
2137
2138                 gpa_offset = data & ~(PAGE_MASK | 1);
2139
2140                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2141                      &vcpu->arch.pv_time, data & ~1ULL,
2142                      sizeof(struct pvclock_vcpu_time_info)))
2143                         vcpu->arch.pv_time_enabled = false;
2144                 else
2145                         vcpu->arch.pv_time_enabled = true;
2146
2147                 break;
2148         }
2149         case MSR_KVM_ASYNC_PF_EN:
2150                 if (kvm_pv_enable_async_pf(vcpu, data))
2151                         return 1;
2152                 break;
2153         case MSR_KVM_STEAL_TIME:
2154
2155                 if (unlikely(!sched_info_on()))
2156                         return 1;
2157
2158                 if (data & KVM_STEAL_RESERVED_MASK)
2159                         return 1;
2160
2161                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2162                                                 data & KVM_STEAL_VALID_BITS,
2163                                                 sizeof(struct kvm_steal_time)))
2164                         return 1;
2165
2166                 vcpu->arch.st.msr_val = data;
2167
2168                 if (!(data & KVM_MSR_ENABLED))
2169                         break;
2170
2171                 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2172
2173                 preempt_disable();
2174                 accumulate_steal_time(vcpu);
2175                 preempt_enable();
2176
2177                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2178
2179                 break;
2180         case MSR_KVM_PV_EOI_EN:
2181                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2182                         return 1;
2183                 break;
2184
2185         case MSR_IA32_MCG_CTL:
2186         case MSR_IA32_MCG_STATUS:
2187         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2188                 return set_msr_mce(vcpu, msr, data);
2189
2190         /* Performance counters are not protected by a CPUID bit,
2191          * so we should check all of them in the generic path for the sake of
2192          * cross vendor migration.
2193          * Writing a zero into the event select MSRs disables them,
2194          * which we perfectly emulate ;-). Any other value should be at least
2195          * reported, some guests depend on them.
2196          */
2197         case MSR_K7_EVNTSEL0:
2198         case MSR_K7_EVNTSEL1:
2199         case MSR_K7_EVNTSEL2:
2200         case MSR_K7_EVNTSEL3:
2201                 if (data != 0)
2202                         vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2203                                     "0x%x data 0x%llx\n", msr, data);
2204                 break;
2205         /* at least RHEL 4 unconditionally writes to the perfctr registers,
2206          * so we ignore writes to make it happy.
2207          */
2208         case MSR_K7_PERFCTR0:
2209         case MSR_K7_PERFCTR1:
2210         case MSR_K7_PERFCTR2:
2211         case MSR_K7_PERFCTR3:
2212                 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2213                             "0x%x data 0x%llx\n", msr, data);
2214                 break;
2215         case MSR_P6_PERFCTR0:
2216         case MSR_P6_PERFCTR1:
2217                 pr = true;
2218         case MSR_P6_EVNTSEL0:
2219         case MSR_P6_EVNTSEL1:
2220                 if (kvm_pmu_msr(vcpu, msr))
2221                         return kvm_pmu_set_msr(vcpu, msr_info);
2222
2223                 if (pr || data != 0)
2224                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2225                                     "0x%x data 0x%llx\n", msr, data);
2226                 break;
2227         case MSR_K7_CLK_CTL:
2228                 /*
2229                  * Ignore all writes to this no longer documented MSR.
2230                  * Writes are only relevant for old K7 processors,
2231                  * all pre-dating SVM, but a recommended workaround from
2232                  * AMD for these chips. It is possible to specify the
2233                  * affected processor models on the command line, hence
2234                  * the need to ignore the workaround.
2235                  */
2236                 break;
2237         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2238                 if (kvm_hv_msr_partition_wide(msr)) {
2239                         int r;
2240                         mutex_lock(&vcpu->kvm->lock);
2241                         r = set_msr_hyperv_pw(vcpu, msr, data);
2242                         mutex_unlock(&vcpu->kvm->lock);
2243                         return r;
2244                 } else
2245                         return set_msr_hyperv(vcpu, msr, data);
2246                 break;
2247         case MSR_IA32_BBL_CR_CTL3:
2248                 /* Drop writes to this legacy MSR -- see rdmsr
2249                  * counterpart for further detail.
2250                  */
2251                 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2252                 break;
2253         case MSR_AMD64_OSVW_ID_LENGTH:
2254                 if (!guest_cpuid_has_osvw(vcpu))
2255                         return 1;
2256                 vcpu->arch.osvw.length = data;
2257                 break;
2258         case MSR_AMD64_OSVW_STATUS:
2259                 if (!guest_cpuid_has_osvw(vcpu))
2260                         return 1;
2261                 vcpu->arch.osvw.status = data;
2262                 break;
2263         default:
2264                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2265                         return xen_hvm_config(vcpu, data);
2266                 if (kvm_pmu_msr(vcpu, msr))
2267                         return kvm_pmu_set_msr(vcpu, msr_info);
2268                 if (!ignore_msrs) {
2269                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2270                                     msr, data);
2271                         return 1;
2272                 } else {
2273                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2274                                     msr, data);
2275                         break;
2276                 }
2277         }
2278         return 0;
2279 }
2280 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2281
2282
2283 /*
2284  * Reads an msr value (of 'msr_index') into 'pdata'.
2285  * Returns 0 on success, non-0 otherwise.
2286  * Assumes vcpu_load() was already called.
2287  */
2288 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2289 {
2290         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2291 }
2292
2293 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2294 {
2295         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2296
2297         if (!msr_mtrr_valid(msr))
2298                 return 1;
2299
2300         if (msr == MSR_MTRRdefType)
2301                 *pdata = vcpu->arch.mtrr_state.def_type +
2302                          (vcpu->arch.mtrr_state.enabled << 10);
2303         else if (msr == MSR_MTRRfix64K_00000)
2304                 *pdata = p[0];
2305         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2306                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2307         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2308                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2309         else if (msr == MSR_IA32_CR_PAT)
2310                 *pdata = vcpu->arch.pat;
2311         else {  /* Variable MTRRs */
2312                 int idx, is_mtrr_mask;
2313                 u64 *pt;
2314
2315                 idx = (msr - 0x200) / 2;
2316                 is_mtrr_mask = msr - 0x200 - 2 * idx;
2317                 if (!is_mtrr_mask)
2318                         pt =
2319                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2320                 else
2321                         pt =
2322                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2323                 *pdata = *pt;
2324         }
2325
2326         return 0;
2327 }
2328
2329 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2330 {
2331         u64 data;
2332         u64 mcg_cap = vcpu->arch.mcg_cap;
2333         unsigned bank_num = mcg_cap & 0xff;
2334
2335         switch (msr) {
2336         case MSR_IA32_P5_MC_ADDR:
2337         case MSR_IA32_P5_MC_TYPE:
2338                 data = 0;
2339                 break;
2340         case MSR_IA32_MCG_CAP:
2341                 data = vcpu->arch.mcg_cap;
2342                 break;
2343         case MSR_IA32_MCG_CTL:
2344                 if (!(mcg_cap & MCG_CTL_P))
2345                         return 1;
2346                 data = vcpu->arch.mcg_ctl;
2347                 break;
2348         case MSR_IA32_MCG_STATUS:
2349                 data = vcpu->arch.mcg_status;
2350                 break;
2351         default:
2352                 if (msr >= MSR_IA32_MC0_CTL &&
2353                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2354                         u32 offset = msr - MSR_IA32_MC0_CTL;
2355                         data = vcpu->arch.mce_banks[offset];
2356                         break;
2357                 }
2358                 return 1;
2359         }
2360         *pdata = data;
2361         return 0;
2362 }
2363
2364 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2365 {
2366         u64 data = 0;
2367         struct kvm *kvm = vcpu->kvm;
2368
2369         switch (msr) {
2370         case HV_X64_MSR_GUEST_OS_ID:
2371                 data = kvm->arch.hv_guest_os_id;
2372                 break;
2373         case HV_X64_MSR_HYPERCALL:
2374                 data = kvm->arch.hv_hypercall;
2375                 break;
2376         case HV_X64_MSR_TIME_REF_COUNT: {
2377                 data =
2378                      div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2379                 break;
2380         }
2381         case HV_X64_MSR_REFERENCE_TSC:
2382                 data = kvm->arch.hv_tsc_page;
2383                 break;
2384         default:
2385                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2386                 return 1;
2387         }
2388
2389         *pdata = data;
2390         return 0;
2391 }
2392
2393 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2394 {
2395         u64 data = 0;
2396
2397         switch (msr) {
2398         case HV_X64_MSR_VP_INDEX: {
2399                 int r;
2400                 struct kvm_vcpu *v;
2401                 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2402                         if (v == vcpu) {
2403                                 data = r;
2404                                 break;
2405                         }
2406                 }
2407                 break;
2408         }
2409         case HV_X64_MSR_EOI:
2410                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2411         case HV_X64_MSR_ICR:
2412                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2413         case HV_X64_MSR_TPR:
2414                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2415         case HV_X64_MSR_APIC_ASSIST_PAGE:
2416                 data = vcpu->arch.hv_vapic;
2417                 break;
2418         default:
2419                 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2420                 return 1;
2421         }
2422         *pdata = data;
2423         return 0;
2424 }
2425
2426 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2427 {
2428         u64 data;
2429
2430         switch (msr) {
2431         case MSR_IA32_PLATFORM_ID:
2432         case MSR_IA32_EBL_CR_POWERON:
2433         case MSR_IA32_DEBUGCTLMSR:
2434         case MSR_IA32_LASTBRANCHFROMIP:
2435         case MSR_IA32_LASTBRANCHTOIP:
2436         case MSR_IA32_LASTINTFROMIP:
2437         case MSR_IA32_LASTINTTOIP:
2438         case MSR_K8_SYSCFG:
2439         case MSR_K7_HWCR:
2440         case MSR_VM_HSAVE_PA:
2441         case MSR_K7_EVNTSEL0:
2442         case MSR_K7_EVNTSEL1:
2443         case MSR_K7_EVNTSEL2:
2444         case MSR_K7_EVNTSEL3:
2445         case MSR_K7_PERFCTR0:
2446         case MSR_K7_PERFCTR1:
2447         case MSR_K7_PERFCTR2:
2448         case MSR_K7_PERFCTR3:
2449         case MSR_K8_INT_PENDING_MSG:
2450         case MSR_AMD64_NB_CFG:
2451         case MSR_FAM10H_MMIO_CONF_BASE:
2452         case MSR_AMD64_BU_CFG2:
2453                 data = 0;
2454                 break;
2455         case MSR_P6_PERFCTR0:
2456         case MSR_P6_PERFCTR1:
2457         case MSR_P6_EVNTSEL0:
2458         case MSR_P6_EVNTSEL1:
2459                 if (kvm_pmu_msr(vcpu, msr))
2460                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2461                 data = 0;
2462                 break;
2463         case MSR_IA32_UCODE_REV:
2464                 data = 0x100000000ULL;
2465                 break;
2466         case MSR_MTRRcap:
2467                 data = 0x500 | KVM_NR_VAR_MTRR;
2468                 break;
2469         case 0x200 ... 0x2ff:
2470                 return get_msr_mtrr(vcpu, msr, pdata);
2471         case 0xcd: /* fsb frequency */
2472                 data = 3;
2473                 break;
2474                 /*
2475                  * MSR_EBC_FREQUENCY_ID
2476                  * Conservative value valid for even the basic CPU models.
2477                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2478                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2479                  * and 266MHz for model 3, or 4. Set Core Clock
2480                  * Frequency to System Bus Frequency Ratio to 1 (bits
2481                  * 31:24) even though these are only valid for CPU
2482                  * models > 2, however guests may end up dividing or
2483                  * multiplying by zero otherwise.
2484                  */
2485         case MSR_EBC_FREQUENCY_ID:
2486                 data = 1 << 24;
2487                 break;
2488         case MSR_IA32_APICBASE:
2489                 data = kvm_get_apic_base(vcpu);
2490                 break;
2491         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2492                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2493                 break;
2494         case MSR_IA32_TSCDEADLINE:
2495                 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2496                 break;
2497         case MSR_IA32_TSC_ADJUST:
2498                 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2499                 break;
2500         case MSR_IA32_MISC_ENABLE:
2501                 data = vcpu->arch.ia32_misc_enable_msr;
2502                 break;
2503         case MSR_IA32_PERF_STATUS:
2504                 /* TSC increment by tick */
2505                 data = 1000ULL;
2506                 /* CPU multiplier */
2507                 data |= (((uint64_t)4ULL) << 40);
2508                 break;
2509         case MSR_EFER:
2510                 data = vcpu->arch.efer;
2511                 break;
2512         case MSR_KVM_WALL_CLOCK:
2513         case MSR_KVM_WALL_CLOCK_NEW:
2514                 data = vcpu->kvm->arch.wall_clock;
2515                 break;
2516         case MSR_KVM_SYSTEM_TIME:
2517         case MSR_KVM_SYSTEM_TIME_NEW:
2518                 data = vcpu->arch.time;
2519                 break;
2520         case MSR_KVM_ASYNC_PF_EN:
2521                 data = vcpu->arch.apf.msr_val;
2522                 break;
2523         case MSR_KVM_STEAL_TIME:
2524                 data = vcpu->arch.st.msr_val;
2525                 break;
2526         case MSR_KVM_PV_EOI_EN:
2527                 data = vcpu->arch.pv_eoi.msr_val;
2528                 break;
2529         case MSR_IA32_P5_MC_ADDR:
2530         case MSR_IA32_P5_MC_TYPE:
2531         case MSR_IA32_MCG_CAP:
2532         case MSR_IA32_MCG_CTL:
2533         case MSR_IA32_MCG_STATUS:
2534         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2535                 return get_msr_mce(vcpu, msr, pdata);
2536         case MSR_K7_CLK_CTL:
2537                 /*
2538                  * Provide expected ramp-up count for K7. All other
2539                  * are set to zero, indicating minimum divisors for
2540                  * every field.
2541                  *
2542                  * This prevents guest kernels on AMD host with CPU
2543                  * type 6, model 8 and higher from exploding due to
2544                  * the rdmsr failing.
2545                  */
2546                 data = 0x20000000;
2547                 break;
2548         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2549                 if (kvm_hv_msr_partition_wide(msr)) {
2550                         int r;
2551                         mutex_lock(&vcpu->kvm->lock);
2552                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
2553                         mutex_unlock(&vcpu->kvm->lock);
2554                         return r;
2555                 } else
2556                         return get_msr_hyperv(vcpu, msr, pdata);
2557                 break;
2558         case MSR_IA32_BBL_CR_CTL3:
2559                 /* This legacy MSR exists but isn't fully documented in current
2560                  * silicon.  It is however accessed by winxp in very narrow
2561                  * scenarios where it sets bit #19, itself documented as
2562                  * a "reserved" bit.  Best effort attempt to source coherent
2563                  * read data here should the balance of the register be
2564                  * interpreted by the guest:
2565                  *
2566                  * L2 cache control register 3: 64GB range, 256KB size,
2567                  * enabled, latency 0x1, configured
2568                  */
2569                 data = 0xbe702111;
2570                 break;
2571         case MSR_AMD64_OSVW_ID_LENGTH:
2572                 if (!guest_cpuid_has_osvw(vcpu))
2573                         return 1;
2574                 data = vcpu->arch.osvw.length;
2575                 break;
2576         case MSR_AMD64_OSVW_STATUS:
2577                 if (!guest_cpuid_has_osvw(vcpu))
2578                         return 1;
2579                 data = vcpu->arch.osvw.status;
2580                 break;
2581         default:
2582                 if (kvm_pmu_msr(vcpu, msr))
2583                         return kvm_pmu_get_msr(vcpu, msr, pdata);
2584                 if (!ignore_msrs) {
2585                         vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2586                         return 1;
2587                 } else {
2588                         vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2589                         data = 0;
2590                 }
2591                 break;
2592         }
2593         *pdata = data;
2594         return 0;
2595 }
2596 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2597
2598 /*
2599  * Read or write a bunch of msrs. All parameters are kernel addresses.
2600  *
2601  * @return number of msrs set successfully.
2602  */
2603 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2604                     struct kvm_msr_entry *entries,
2605                     int (*do_msr)(struct kvm_vcpu *vcpu,
2606                                   unsigned index, u64 *data))
2607 {
2608         int i, idx;
2609
2610         idx = srcu_read_lock(&vcpu->kvm->srcu);
2611         for (i = 0; i < msrs->nmsrs; ++i)
2612                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2613                         break;
2614         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2615
2616         return i;
2617 }
2618
2619 /*
2620  * Read or write a bunch of msrs. Parameters are user addresses.
2621  *
2622  * @return number of msrs set successfully.
2623  */
2624 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2625                   int (*do_msr)(struct kvm_vcpu *vcpu,
2626                                 unsigned index, u64 *data),
2627                   int writeback)
2628 {
2629         struct kvm_msrs msrs;
2630         struct kvm_msr_entry *entries;
2631         int r, n;
2632         unsigned size;
2633
2634         r = -EFAULT;
2635         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2636                 goto out;
2637
2638         r = -E2BIG;
2639         if (msrs.nmsrs >= MAX_IO_MSRS)
2640                 goto out;
2641
2642         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2643         entries = memdup_user(user_msrs->entries, size);
2644         if (IS_ERR(entries)) {
2645                 r = PTR_ERR(entries);
2646                 goto out;
2647         }
2648
2649         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2650         if (r < 0)
2651                 goto out_free;
2652
2653         r = -EFAULT;
2654         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2655                 goto out_free;
2656
2657         r = n;
2658
2659 out_free:
2660         kfree(entries);
2661 out:
2662         return r;
2663 }
2664
2665 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2666 {
2667         int r;
2668
2669         switch (ext) {
2670         case KVM_CAP_IRQCHIP:
2671         case KVM_CAP_HLT:
2672         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2673         case KVM_CAP_SET_TSS_ADDR:
2674         case KVM_CAP_EXT_CPUID:
2675         case KVM_CAP_EXT_EMUL_CPUID:
2676         case KVM_CAP_CLOCKSOURCE:
2677         case KVM_CAP_PIT:
2678         case KVM_CAP_NOP_IO_DELAY:
2679         case KVM_CAP_MP_STATE:
2680         case KVM_CAP_SYNC_MMU:
2681         case KVM_CAP_USER_NMI:
2682         case KVM_CAP_REINJECT_CONTROL:
2683         case KVM_CAP_IRQ_INJECT_STATUS:
2684         case KVM_CAP_IRQFD:
2685         case KVM_CAP_IOEVENTFD:
2686         case KVM_CAP_IOEVENTFD_NO_LENGTH:
2687         case KVM_CAP_PIT2:
2688         case KVM_CAP_PIT_STATE2:
2689         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2690         case KVM_CAP_XEN_HVM:
2691         case KVM_CAP_ADJUST_CLOCK:
2692         case KVM_CAP_VCPU_EVENTS:
2693         case KVM_CAP_HYPERV:
2694         case KVM_CAP_HYPERV_VAPIC:
2695         case KVM_CAP_HYPERV_SPIN:
2696         case KVM_CAP_PCI_SEGMENT:
2697         case KVM_CAP_DEBUGREGS:
2698         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2699         case KVM_CAP_XSAVE:
2700         case KVM_CAP_ASYNC_PF:
2701         case KVM_CAP_GET_TSC_KHZ:
2702         case KVM_CAP_KVMCLOCK_CTRL:
2703         case KVM_CAP_READONLY_MEM:
2704         case KVM_CAP_HYPERV_TIME:
2705         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2706 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2707         case KVM_CAP_ASSIGN_DEV_IRQ:
2708         case KVM_CAP_PCI_2_3:
2709 #endif
2710                 r = 1;
2711                 break;
2712         case KVM_CAP_COALESCED_MMIO:
2713                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2714                 break;
2715         case KVM_CAP_VAPIC:
2716                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2717                 break;
2718         case KVM_CAP_NR_VCPUS:
2719                 r = KVM_SOFT_MAX_VCPUS;
2720                 break;
2721         case KVM_CAP_MAX_VCPUS:
2722                 r = KVM_MAX_VCPUS;
2723                 break;
2724         case KVM_CAP_NR_MEMSLOTS:
2725                 r = KVM_USER_MEM_SLOTS;
2726                 break;
2727         case KVM_CAP_PV_MMU:    /* obsolete */
2728                 r = 0;
2729                 break;
2730 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2731         case KVM_CAP_IOMMU:
2732                 r = iommu_present(&pci_bus_type);
2733                 break;
2734 #endif
2735         case KVM_CAP_MCE:
2736                 r = KVM_MAX_MCE_BANKS;
2737                 break;
2738         case KVM_CAP_XCRS:
2739                 r = cpu_has_xsave;
2740                 break;
2741         case KVM_CAP_TSC_CONTROL:
2742                 r = kvm_has_tsc_control;
2743                 break;
2744         case KVM_CAP_TSC_DEADLINE_TIMER:
2745                 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2746                 break;
2747         default:
2748                 r = 0;
2749                 break;
2750         }
2751         return r;
2752
2753 }
2754
2755 long kvm_arch_dev_ioctl(struct file *filp,
2756                         unsigned int ioctl, unsigned long arg)
2757 {
2758         void __user *argp = (void __user *)arg;
2759         long r;
2760
2761         switch (ioctl) {
2762         case KVM_GET_MSR_INDEX_LIST: {
2763                 struct kvm_msr_list __user *user_msr_list = argp;
2764                 struct kvm_msr_list msr_list;
2765                 unsigned n;
2766
2767                 r = -EFAULT;
2768                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2769                         goto out;
2770                 n = msr_list.nmsrs;
2771                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2772                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2773                         goto out;
2774                 r = -E2BIG;
2775                 if (n < msr_list.nmsrs)
2776                         goto out;
2777                 r = -EFAULT;
2778                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2779                                  num_msrs_to_save * sizeof(u32)))
2780                         goto out;
2781                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2782                                  &emulated_msrs,
2783                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2784                         goto out;
2785                 r = 0;
2786                 break;
2787         }
2788         case KVM_GET_SUPPORTED_CPUID:
2789         case KVM_GET_EMULATED_CPUID: {
2790                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2791                 struct kvm_cpuid2 cpuid;
2792
2793                 r = -EFAULT;
2794                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2795                         goto out;
2796
2797                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2798                                             ioctl);
2799                 if (r)
2800                         goto out;
2801
2802                 r = -EFAULT;
2803                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2804                         goto out;
2805                 r = 0;
2806                 break;
2807         }
2808         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2809                 u64 mce_cap;
2810
2811                 mce_cap = KVM_MCE_CAP_SUPPORTED;
2812                 r = -EFAULT;
2813                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2814                         goto out;
2815                 r = 0;
2816                 break;
2817         }
2818         default:
2819                 r = -EINVAL;
2820         }
2821 out:
2822         return r;
2823 }
2824
2825 static void wbinvd_ipi(void *garbage)
2826 {
2827         wbinvd();
2828 }
2829
2830 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2831 {
2832         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
2833 }
2834
2835 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2836 {
2837         /* Address WBINVD may be executed by guest */
2838         if (need_emulate_wbinvd(vcpu)) {
2839                 if (kvm_x86_ops->has_wbinvd_exit())
2840                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2841                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2842                         smp_call_function_single(vcpu->cpu,
2843                                         wbinvd_ipi, NULL, 1);
2844         }
2845
2846         kvm_x86_ops->vcpu_load(vcpu, cpu);
2847
2848         /* Apply any externally detected TSC adjustments (due to suspend) */
2849         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2850                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2851                 vcpu->arch.tsc_offset_adjustment = 0;
2852                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2853         }
2854
2855         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2856                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2857                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2858                 if (tsc_delta < 0)
2859                         mark_tsc_unstable("KVM discovered backwards TSC");
2860                 if (check_tsc_unstable()) {
2861                         u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2862                                                 vcpu->arch.last_guest_tsc);
2863                         kvm_x86_ops->write_tsc_offset(vcpu, offset);
2864                         vcpu->arch.tsc_catchup = 1;
2865                 }
2866                 /*
2867                  * On a host with synchronized TSC, there is no need to update
2868                  * kvmclock on vcpu->cpu migration
2869                  */
2870                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2871                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2872                 if (vcpu->cpu != cpu)
2873                         kvm_migrate_timers(vcpu);
2874                 vcpu->cpu = cpu;
2875         }
2876
2877         accumulate_steal_time(vcpu);
2878         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2879 }
2880
2881 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2882 {
2883         kvm_x86_ops->vcpu_put(vcpu);
2884         kvm_put_guest_fpu(vcpu);
2885         vcpu->arch.last_host_tsc = native_read_tsc();
2886 }
2887
2888 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2889                                     struct kvm_lapic_state *s)
2890 {
2891         kvm_x86_ops->sync_pir_to_irr(vcpu);
2892         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2893
2894         return 0;
2895 }
2896
2897 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2898                                     struct kvm_lapic_state *s)
2899 {
2900         kvm_apic_post_state_restore(vcpu, s);
2901         update_cr8_intercept(vcpu);
2902
2903         return 0;
2904 }
2905
2906 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2907                                     struct kvm_interrupt *irq)
2908 {
2909         if (irq->irq >= KVM_NR_INTERRUPTS)
2910                 return -EINVAL;
2911         if (irqchip_in_kernel(vcpu->kvm))
2912                 return -ENXIO;
2913
2914         kvm_queue_interrupt(vcpu, irq->irq, false);
2915         kvm_make_request(KVM_REQ_EVENT, vcpu);
2916
2917         return 0;
2918 }
2919
2920 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2921 {
2922         kvm_inject_nmi(vcpu);
2923
2924         return 0;
2925 }
2926
2927 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2928                                            struct kvm_tpr_access_ctl *tac)
2929 {
2930         if (tac->flags)
2931                 return -EINVAL;
2932         vcpu->arch.tpr_access_reporting = !!tac->enabled;
2933         return 0;
2934 }
2935
2936 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2937                                         u64 mcg_cap)
2938 {
2939         int r;
2940         unsigned bank_num = mcg_cap & 0xff, bank;
2941
2942         r = -EINVAL;
2943         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2944                 goto out;
2945         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2946                 goto out;
2947         r = 0;
2948         vcpu->arch.mcg_cap = mcg_cap;
2949         /* Init IA32_MCG_CTL to all 1s */
2950         if (mcg_cap & MCG_CTL_P)
2951                 vcpu->arch.mcg_ctl = ~(u64)0;
2952         /* Init IA32_MCi_CTL to all 1s */
2953         for (bank = 0; bank < bank_num; bank++)
2954                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2955 out:
2956         return r;
2957 }
2958
2959 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2960                                       struct kvm_x86_mce *mce)
2961 {
2962         u64 mcg_cap = vcpu->arch.mcg_cap;
2963         unsigned bank_num = mcg_cap & 0xff;
2964         u64 *banks = vcpu->arch.mce_banks;
2965
2966         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2967                 return -EINVAL;
2968         /*
2969          * if IA32_MCG_CTL is not all 1s, the uncorrected error
2970          * reporting is disabled
2971          */
2972         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2973             vcpu->arch.mcg_ctl != ~(u64)0)
2974                 return 0;
2975         banks += 4 * mce->bank;
2976         /*
2977          * if IA32_MCi_CTL is not all 1s, the uncorrected error
2978          * reporting is disabled for the bank
2979          */
2980         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2981                 return 0;
2982         if (mce->status & MCI_STATUS_UC) {
2983                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2984                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2985                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2986                         return 0;
2987                 }
2988                 if (banks[1] & MCI_STATUS_VAL)
2989                         mce->status |= MCI_STATUS_OVER;
2990                 banks[2] = mce->addr;
2991                 banks[3] = mce->misc;
2992                 vcpu->arch.mcg_status = mce->mcg_status;
2993                 banks[1] = mce->status;
2994                 kvm_queue_exception(vcpu, MC_VECTOR);
2995         } else if (!(banks[1] & MCI_STATUS_VAL)
2996                    || !(banks[1] & MCI_STATUS_UC)) {
2997                 if (banks[1] & MCI_STATUS_VAL)
2998                         mce->status |= MCI_STATUS_OVER;
2999                 banks[2] = mce->addr;
3000                 banks[3] = mce->misc;
3001                 banks[1] = mce->status;
3002         } else
3003                 banks[1] |= MCI_STATUS_OVER;
3004         return 0;
3005 }
3006
3007 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3008                                                struct kvm_vcpu_events *events)
3009 {
3010         process_nmi(vcpu);
3011         events->exception.injected =
3012                 vcpu->arch.exception.pending &&
3013                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3014         events->exception.nr = vcpu->arch.exception.nr;
3015         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3016         events->exception.pad = 0;
3017         events->exception.error_code = vcpu->arch.exception.error_code;
3018
3019         events->interrupt.injected =
3020                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3021         events->interrupt.nr = vcpu->arch.interrupt.nr;
3022         events->interrupt.soft = 0;
3023         events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3024
3025         events->nmi.injected = vcpu->arch.nmi_injected;
3026         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3027         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
3028         events->nmi.pad = 0;
3029
3030         events->sipi_vector = 0; /* never valid when reporting to user space */
3031
3032         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3033                          | KVM_VCPUEVENT_VALID_SHADOW);
3034         memset(&events->reserved, 0, sizeof(events->reserved));
3035 }
3036
3037 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3038                                               struct kvm_vcpu_events *events)
3039 {
3040         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3041                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3042                               | KVM_VCPUEVENT_VALID_SHADOW))
3043                 return -EINVAL;
3044
3045         process_nmi(vcpu);
3046         vcpu->arch.exception.pending = events->exception.injected;
3047         vcpu->arch.exception.nr = events->exception.nr;
3048         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3049         vcpu->arch.exception.error_code = events->exception.error_code;
3050
3051         vcpu->arch.interrupt.pending = events->interrupt.injected;
3052         vcpu->arch.interrupt.nr = events->interrupt.nr;
3053         vcpu->arch.interrupt.soft = events->interrupt.soft;
3054         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3055                 kvm_x86_ops->set_interrupt_shadow(vcpu,
3056                                                   events->interrupt.shadow);
3057
3058         vcpu->arch.nmi_injected = events->nmi.injected;
3059         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3060                 vcpu->arch.nmi_pending = events->nmi.pending;
3061         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3062
3063         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3064             kvm_vcpu_has_lapic(vcpu))
3065                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3066
3067         kvm_make_request(KVM_REQ_EVENT, vcpu);
3068
3069         return 0;
3070 }
3071
3072 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3073                                              struct kvm_debugregs *dbgregs)
3074 {
3075         unsigned long val;
3076
3077         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
3078         _kvm_get_dr(vcpu, 6, &val);
3079         dbgregs->dr6 = val;
3080         dbgregs->dr7 = vcpu->arch.dr7;
3081         dbgregs->flags = 0;
3082         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
3083 }
3084
3085 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3086                                             struct kvm_debugregs *dbgregs)
3087 {
3088         if (dbgregs->flags)
3089                 return -EINVAL;
3090
3091         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3092         vcpu->arch.dr6 = dbgregs->dr6;
3093         kvm_update_dr6(vcpu);
3094         vcpu->arch.dr7 = dbgregs->dr7;
3095         kvm_update_dr7(vcpu);
3096
3097         return 0;
3098 }
3099
3100 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3101                                          struct kvm_xsave *guest_xsave)
3102 {
3103         if (cpu_has_xsave) {
3104                 memcpy(guest_xsave->region,
3105                         &vcpu->arch.guest_fpu.state->xsave,
3106                         vcpu->arch.guest_xstate_size);
3107                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3108                         vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3109         } else {
3110                 memcpy(guest_xsave->region,
3111                         &vcpu->arch.guest_fpu.state->fxsave,
3112                         sizeof(struct i387_fxsave_struct));
3113                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3114                         XSTATE_FPSSE;
3115         }
3116 }
3117
3118 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3119                                         struct kvm_xsave *guest_xsave)
3120 {
3121         u64 xstate_bv =
3122                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3123
3124         if (cpu_has_xsave) {
3125                 /*
3126                  * Here we allow setting states that are not present in
3127                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
3128                  * with old userspace.
3129                  */
3130                 if (xstate_bv & ~kvm_supported_xcr0())
3131                         return -EINVAL;
3132                 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3133                         guest_xsave->region, vcpu->arch.guest_xstate_size);
3134         } else {
3135                 if (xstate_bv & ~XSTATE_FPSSE)
3136                         return -EINVAL;
3137                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3138                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
3139         }
3140         return 0;
3141 }
3142
3143 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3144                                         struct kvm_xcrs *guest_xcrs)
3145 {
3146         if (!cpu_has_xsave) {
3147                 guest_xcrs->nr_xcrs = 0;
3148                 return;
3149         }
3150
3151         guest_xcrs->nr_xcrs = 1;
3152         guest_xcrs->flags = 0;
3153         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3154         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3155 }
3156
3157 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3158                                        struct kvm_xcrs *guest_xcrs)
3159 {
3160         int i, r = 0;
3161
3162         if (!cpu_has_xsave)
3163                 return -EINVAL;
3164
3165         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3166                 return -EINVAL;
3167
3168         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3169                 /* Only support XCR0 currently */
3170                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
3171                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3172                                 guest_xcrs->xcrs[i].value);
3173                         break;
3174                 }
3175         if (r)
3176                 r = -EINVAL;
3177         return r;
3178 }
3179
3180 /*
3181  * kvm_set_guest_paused() indicates to the guest kernel that it has been
3182  * stopped by the hypervisor.  This function will be called from the host only.
3183  * EINVAL is returned when the host attempts to set the flag for a guest that
3184  * does not support pv clocks.
3185  */
3186 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3187 {
3188         if (!vcpu->arch.pv_time_enabled)
3189                 return -EINVAL;
3190         vcpu->arch.pvclock_set_guest_stopped_request = true;
3191         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3192         return 0;
3193 }
3194
3195 long kvm_arch_vcpu_ioctl(struct file *filp,
3196                          unsigned int ioctl, unsigned long arg)
3197 {
3198         struct kvm_vcpu *vcpu = filp->private_data;
3199         void __user *argp = (void __user *)arg;
3200         int r;
3201         union {
3202                 struct kvm_lapic_state *lapic;
3203                 struct kvm_xsave *xsave;
3204                 struct kvm_xcrs *xcrs;
3205                 void *buffer;
3206         } u;
3207
3208         u.buffer = NULL;
3209         switch (ioctl) {
3210         case KVM_GET_LAPIC: {
3211                 r = -EINVAL;
3212                 if (!vcpu->arch.apic)
3213                         goto out;
3214                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3215
3216                 r = -ENOMEM;
3217                 if (!u.lapic)
3218                         goto out;
3219                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3220                 if (r)
3221                         goto out;
3222                 r = -EFAULT;
3223                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3224                         goto out;
3225                 r = 0;
3226                 break;
3227         }
3228         case KVM_SET_LAPIC: {
3229                 r = -EINVAL;
3230                 if (!vcpu->arch.apic)
3231                         goto out;
3232                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3233                 if (IS_ERR(u.lapic))
3234                         return PTR_ERR(u.lapic);
3235
3236                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3237                 break;
3238         }
3239         case KVM_INTERRUPT: {
3240                 struct kvm_interrupt irq;
3241
3242                 r = -EFAULT;
3243                 if (copy_from_user(&irq, argp, sizeof irq))
3244                         goto out;
3245                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3246                 break;
3247         }
3248         case KVM_NMI: {
3249                 r = kvm_vcpu_ioctl_nmi(vcpu);
3250                 break;
3251         }
3252         case KVM_SET_CPUID: {
3253                 struct kvm_cpuid __user *cpuid_arg = argp;
3254                 struct kvm_cpuid cpuid;
3255
3256                 r = -EFAULT;
3257                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3258                         goto out;
3259                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3260                 break;
3261         }
3262         case KVM_SET_CPUID2: {
3263                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3264                 struct kvm_cpuid2 cpuid;
3265
3266                 r = -EFAULT;
3267                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3268                         goto out;
3269                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3270                                               cpuid_arg->entries);
3271                 break;
3272         }
3273         case KVM_GET_CPUID2: {
3274                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3275                 struct kvm_cpuid2 cpuid;
3276
3277                 r = -EFAULT;
3278                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3279                         goto out;
3280                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3281                                               cpuid_arg->entries);
3282                 if (r)
3283                         goto out;
3284                 r = -EFAULT;
3285                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3286                         goto out;
3287                 r = 0;
3288                 break;
3289         }
3290         case KVM_GET_MSRS:
3291                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3292                 break;
3293         case KVM_SET_MSRS:
3294                 r = msr_io(vcpu, argp, do_set_msr, 0);
3295                 break;
3296         case KVM_TPR_ACCESS_REPORTING: {
3297                 struct kvm_tpr_access_ctl tac;
3298
3299                 r = -EFAULT;
3300                 if (copy_from_user(&tac, argp, sizeof tac))
3301                         goto out;
3302                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3303                 if (r)
3304                         goto out;
3305                 r = -EFAULT;
3306                 if (copy_to_user(argp, &tac, sizeof tac))
3307                         goto out;
3308                 r = 0;
3309                 break;
3310         };
3311         case KVM_SET_VAPIC_ADDR: {
3312                 struct kvm_vapic_addr va;
3313
3314                 r = -EINVAL;
3315                 if (!irqchip_in_kernel(vcpu->kvm))
3316                         goto out;
3317                 r = -EFAULT;
3318                 if (copy_from_user(&va, argp, sizeof va))
3319                         goto out;
3320                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3321                 break;
3322         }
3323         case KVM_X86_SETUP_MCE: {
3324                 u64 mcg_cap;
3325
3326                 r = -EFAULT;
3327                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3328                         goto out;
3329                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3330                 break;
3331         }
3332         case KVM_X86_SET_MCE: {
3333                 struct kvm_x86_mce mce;
3334
3335                 r = -EFAULT;
3336                 if (copy_from_user(&mce, argp, sizeof mce))
3337                         goto out;
3338                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3339                 break;
3340         }
3341         case KVM_GET_VCPU_EVENTS: {
3342                 struct kvm_vcpu_events events;
3343
3344                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3345
3346                 r = -EFAULT;
3347                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3348                         break;
3349                 r = 0;
3350                 break;
3351         }
3352         case KVM_SET_VCPU_EVENTS: {
3353                 struct kvm_vcpu_events events;
3354
3355                 r = -EFAULT;
3356                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3357                         break;
3358
3359                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3360                 break;
3361         }
3362         case KVM_GET_DEBUGREGS: {
3363                 struct kvm_debugregs dbgregs;
3364
3365                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3366
3367                 r = -EFAULT;
3368                 if (copy_to_user(argp, &dbgregs,
3369                                  sizeof(struct kvm_debugregs)))
3370                         break;
3371                 r = 0;
3372                 break;
3373         }
3374         case KVM_SET_DEBUGREGS: {
3375                 struct kvm_debugregs dbgregs;
3376
3377                 r = -EFAULT;
3378                 if (copy_from_user(&dbgregs, argp,
3379                                    sizeof(struct kvm_debugregs)))
3380                         break;
3381
3382                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3383                 break;
3384         }
3385         case KVM_GET_XSAVE: {
3386                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3387                 r = -ENOMEM;
3388                 if (!u.xsave)
3389                         break;
3390
3391                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3392
3393                 r = -EFAULT;
3394                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3395                         break;
3396                 r = 0;
3397                 break;
3398         }
3399         case KVM_SET_XSAVE: {
3400                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3401                 if (IS_ERR(u.xsave))
3402                         return PTR_ERR(u.xsave);
3403
3404                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3405                 break;
3406         }
3407         case KVM_GET_XCRS: {
3408                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3409                 r = -ENOMEM;
3410                 if (!u.xcrs)
3411                         break;
3412
3413                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3414
3415                 r = -EFAULT;
3416                 if (copy_to_user(argp, u.xcrs,
3417                                  sizeof(struct kvm_xcrs)))
3418                         break;
3419                 r = 0;
3420                 break;
3421         }
3422         case KVM_SET_XCRS: {
3423                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3424                 if (IS_ERR(u.xcrs))
3425                         return PTR_ERR(u.xcrs);
3426
3427                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3428                 break;
3429         }
3430         case KVM_SET_TSC_KHZ: {
3431                 u32 user_tsc_khz;
3432
3433                 r = -EINVAL;
3434                 user_tsc_khz = (u32)arg;
3435
3436                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3437                         goto out;
3438
3439                 if (user_tsc_khz == 0)
3440                         user_tsc_khz = tsc_khz;
3441
3442                 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3443
3444                 r = 0;
3445                 goto out;
3446         }
3447         case KVM_GET_TSC_KHZ: {
3448                 r = vcpu->arch.virtual_tsc_khz;
3449                 goto out;
3450         }
3451         case KVM_KVMCLOCK_CTRL: {
3452                 r = kvm_set_guest_paused(vcpu);
3453                 goto out;
3454         }
3455         default:
3456                 r = -EINVAL;
3457         }
3458 out:
3459         kfree(u.buffer);
3460         return r;
3461 }
3462
3463 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3464 {
3465         return VM_FAULT_SIGBUS;
3466 }
3467
3468 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3469 {
3470         int ret;
3471
3472         if (addr > (unsigned int)(-3 * PAGE_SIZE))
3473                 return -EINVAL;
3474         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3475         return ret;
3476 }
3477
3478 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3479                                               u64 ident_addr)
3480 {
3481         kvm->arch.ept_identity_map_addr = ident_addr;
3482         return 0;
3483 }
3484
3485 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3486                                           u32 kvm_nr_mmu_pages)
3487 {
3488         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3489                 return -EINVAL;
3490
3491         mutex_lock(&kvm->slots_lock);
3492
3493         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3494         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3495
3496         mutex_unlock(&kvm->slots_lock);
3497         return 0;
3498 }
3499
3500 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3501 {
3502         return kvm->arch.n_max_mmu_pages;
3503 }
3504
3505 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3506 {
3507         int r;
3508
3509         r = 0;
3510         switch (chip->chip_id) {
3511         case KVM_IRQCHIP_PIC_MASTER:
3512                 memcpy(&chip->chip.pic,
3513                         &pic_irqchip(kvm)->pics[0],
3514                         sizeof(struct kvm_pic_state));
3515                 break;
3516         case KVM_IRQCHIP_PIC_SLAVE:
3517                 memcpy(&chip->chip.pic,
3518                         &pic_irqchip(kvm)->pics[1],
3519                         sizeof(struct kvm_pic_state));
3520                 break;
3521         case KVM_IRQCHIP_IOAPIC:
3522                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3523                 break;
3524         default:
3525                 r = -EINVAL;
3526                 break;
3527         }
3528         return r;
3529 }
3530
3531 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3532 {
3533         int r;
3534
3535         r = 0;
3536         switch (chip->chip_id) {
3537         case KVM_IRQCHIP_PIC_MASTER:
3538                 spin_lock(&pic_irqchip(kvm)->lock);
3539                 memcpy(&pic_irqchip(kvm)->pics[0],
3540                         &chip->chip.pic,
3541                         sizeof(struct kvm_pic_state));
3542                 spin_unlock(&pic_irqchip(kvm)->lock);
3543                 break;
3544         case KVM_IRQCHIP_PIC_SLAVE:
3545                 spin_lock(&pic_irqchip(kvm)->lock);
3546                 memcpy(&pic_irqchip(kvm)->pics[1],
3547                         &chip->chip.pic,
3548                         sizeof(struct kvm_pic_state));
3549                 spin_unlock(&pic_irqchip(kvm)->lock);
3550                 break;
3551         case KVM_IRQCHIP_IOAPIC:
3552                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3553                 break;
3554         default:
3555                 r = -EINVAL;
3556                 break;
3557         }
3558         kvm_pic_update_irq(pic_irqchip(kvm));
3559         return r;
3560 }
3561
3562 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3563 {
3564         int r = 0;
3565
3566         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3567         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3568         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3569         return r;
3570 }
3571
3572 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3573 {
3574         int r = 0;
3575
3576         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3577         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3578         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3579         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3580         return r;
3581 }
3582
3583 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3584 {
3585         int r = 0;
3586
3587         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3588         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3589                 sizeof(ps->channels));
3590         ps->flags = kvm->arch.vpit->pit_state.flags;
3591         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3592         memset(&ps->reserved, 0, sizeof(ps->reserved));
3593         return r;
3594 }
3595
3596 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3597 {
3598         int r = 0, start = 0;
3599         u32 prev_legacy, cur_legacy;
3600         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3601         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3602         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3603         if (!prev_legacy && cur_legacy)
3604                 start = 1;
3605         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3606                sizeof(kvm->arch.vpit->pit_state.channels));
3607         kvm->arch.vpit->pit_state.flags = ps->flags;
3608         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3609         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3610         return r;
3611 }
3612
3613 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3614                                  struct kvm_reinject_control *control)
3615 {
3616         if (!kvm->arch.vpit)
3617                 return -ENXIO;
3618         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3619         kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3620         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3621         return 0;
3622 }
3623
3624 /**
3625  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3626  * @kvm: kvm instance
3627  * @log: slot id and address to which we copy the log
3628  *
3629  * We need to keep it in mind that VCPU threads can write to the bitmap
3630  * concurrently.  So, to avoid losing data, we keep the following order for
3631  * each bit:
3632  *
3633  *   1. Take a snapshot of the bit and clear it if needed.
3634  *   2. Write protect the corresponding page.
3635  *   3. Flush TLB's if needed.
3636  *   4. Copy the snapshot to the userspace.
3637  *
3638  * Between 2 and 3, the guest may write to the page using the remaining TLB
3639  * entry.  This is not a problem because the page will be reported dirty at
3640  * step 4 using the snapshot taken before and step 3 ensures that successive
3641  * writes will be logged for the next call.
3642  */
3643 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3644 {
3645         int r;
3646         struct kvm_memory_slot *memslot;
3647         unsigned long n, i;
3648         unsigned long *dirty_bitmap;
3649         unsigned long *dirty_bitmap_buffer;
3650         bool is_dirty = false;
3651
3652         mutex_lock(&kvm->slots_lock);
3653
3654         r = -EINVAL;
3655         if (log->slot >= KVM_USER_MEM_SLOTS)
3656                 goto out;
3657
3658         memslot = id_to_memslot(kvm->memslots, log->slot);
3659
3660         dirty_bitmap = memslot->dirty_bitmap;
3661         r = -ENOENT;
3662         if (!dirty_bitmap)
3663                 goto out;
3664
3665         n = kvm_dirty_bitmap_bytes(memslot);
3666
3667         dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3668         memset(dirty_bitmap_buffer, 0, n);
3669
3670         spin_lock(&kvm->mmu_lock);
3671
3672         for (i = 0; i < n / sizeof(long); i++) {
3673                 unsigned long mask;
3674                 gfn_t offset;
3675
3676                 if (!dirty_bitmap[i])
3677                         continue;
3678
3679                 is_dirty = true;
3680
3681                 mask = xchg(&dirty_bitmap[i], 0);
3682                 dirty_bitmap_buffer[i] = mask;
3683
3684                 offset = i * BITS_PER_LONG;
3685                 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3686         }
3687
3688         spin_unlock(&kvm->mmu_lock);
3689
3690         /* See the comments in kvm_mmu_slot_remove_write_access(). */
3691         lockdep_assert_held(&kvm->slots_lock);
3692
3693         /*
3694          * All the TLBs can be flushed out of mmu lock, see the comments in
3695          * kvm_mmu_slot_remove_write_access().
3696          */
3697         if (is_dirty)
3698                 kvm_flush_remote_tlbs(kvm);
3699
3700         r = -EFAULT;
3701         if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3702                 goto out;
3703
3704         r = 0;
3705 out:
3706         mutex_unlock(&kvm->slots_lock);
3707         return r;
3708 }
3709
3710 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3711                         bool line_status)
3712 {
3713         if (!irqchip_in_kernel(kvm))
3714                 return -ENXIO;
3715
3716         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3717                                         irq_event->irq, irq_event->level,
3718                                         line_status);
3719         return 0;
3720 }
3721
3722 long kvm_arch_vm_ioctl(struct file *filp,
3723                        unsigned int ioctl, unsigned long arg)
3724 {
3725         struct kvm *kvm = filp->private_data;
3726         void __user *argp = (void __user *)arg;
3727         int r = -ENOTTY;
3728         /*
3729          * This union makes it completely explicit to gcc-3.x
3730          * that these two variables' stack usage should be
3731          * combined, not added together.
3732          */
3733         union {
3734                 struct kvm_pit_state ps;
3735                 struct kvm_pit_state2 ps2;
3736                 struct kvm_pit_config pit_config;
3737         } u;
3738
3739         switch (ioctl) {
3740         case KVM_SET_TSS_ADDR:
3741                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3742                 break;
3743         case KVM_SET_IDENTITY_MAP_ADDR: {
3744                 u64 ident_addr;
3745
3746                 r = -EFAULT;
3747                 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3748                         goto out;
3749                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3750                 break;
3751         }
3752         case KVM_SET_NR_MMU_PAGES:
3753                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3754                 break;
3755         case KVM_GET_NR_MMU_PAGES:
3756                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3757                 break;
3758         case KVM_CREATE_IRQCHIP: {
3759                 struct kvm_pic *vpic;
3760
3761                 mutex_lock(&kvm->lock);
3762                 r = -EEXIST;
3763                 if (kvm->arch.vpic)
3764                         goto create_irqchip_unlock;
3765                 r = -EINVAL;
3766                 if (atomic_read(&kvm->online_vcpus))
3767                         goto create_irqchip_unlock;
3768                 r = -ENOMEM;
3769                 vpic = kvm_create_pic(kvm);
3770                 if (vpic) {
3771                         r = kvm_ioapic_init(kvm);
3772                         if (r) {
3773                                 mutex_lock(&kvm->slots_lock);
3774                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3775                                                           &vpic->dev_master);
3776                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3777                                                           &vpic->dev_slave);
3778                                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3779                                                           &vpic->dev_eclr);
3780                                 mutex_unlock(&kvm->slots_lock);
3781                                 kfree(vpic);
3782                                 goto create_irqchip_unlock;
3783                         }
3784                 } else
3785                         goto create_irqchip_unlock;
3786                 smp_wmb();
3787                 kvm->arch.vpic = vpic;
3788                 smp_wmb();
3789                 r = kvm_setup_default_irq_routing(kvm);
3790                 if (r) {
3791                         mutex_lock(&kvm->slots_lock);
3792                         mutex_lock(&kvm->irq_lock);
3793                         kvm_ioapic_destroy(kvm);
3794                         kvm_destroy_pic(kvm);
3795                         mutex_unlock(&kvm->irq_lock);
3796                         mutex_unlock(&kvm->slots_lock);
3797                 }
3798         create_irqchip_unlock:
3799                 mutex_unlock(&kvm->lock);
3800                 break;
3801         }
3802         case KVM_CREATE_PIT:
3803                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3804                 goto create_pit;
3805         case KVM_CREATE_PIT2:
3806                 r = -EFAULT;
3807                 if (copy_from_user(&u.pit_config, argp,
3808                                    sizeof(struct kvm_pit_config)))
3809                         goto out;
3810         create_pit:
3811                 mutex_lock(&kvm->slots_lock);
3812                 r = -EEXIST;
3813                 if (kvm->arch.vpit)
3814                         goto create_pit_unlock;
3815                 r = -ENOMEM;
3816                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3817                 if (kvm->arch.vpit)
3818                         r = 0;
3819         create_pit_unlock:
3820                 mutex_unlock(&kvm->slots_lock);
3821                 break;
3822         case KVM_GET_IRQCHIP: {
3823                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3824                 struct kvm_irqchip *chip;
3825
3826                 chip = memdup_user(argp, sizeof(*chip));
3827                 if (IS_ERR(chip)) {
3828                         r = PTR_ERR(chip);
3829                         goto out;
3830                 }
3831
3832                 r = -ENXIO;
3833                 if (!irqchip_in_kernel(kvm))
3834                         goto get_irqchip_out;
3835                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3836                 if (r)
3837                         goto get_irqchip_out;
3838                 r = -EFAULT;
3839                 if (copy_to_user(argp, chip, sizeof *chip))
3840                         goto get_irqchip_out;
3841                 r = 0;
3842         get_irqchip_out: