Merge branch 'akpm' (patches from Andrew)
[sfrench/cifs-2.6.git] / arch / x86 / kvm / x86.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * derived from drivers/kvm/kvm_main.c
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright (C) 2008 Qumranet, Inc.
8  * Copyright IBM Corporation, 2008
9  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10  *
11  * Authors:
12  *   Avi Kivity   <avi@qumranet.com>
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Amit Shah    <amit.shah@qumranet.com>
15  *   Ben-Ami Yassour <benami@il.ibm.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30 #include "pmu.h"
31 #include "hyperv.h"
32
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
36 #include <linux/fs.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/mem_encrypt.h>
58
59 #include <trace/events/kvm.h>
60
61 #include <asm/debugreg.h>
62 #include <asm/msr.h>
63 #include <asm/desc.h>
64 #include <asm/mce.h>
65 #include <linux/kernel_stat.h>
66 #include <asm/fpu/internal.h> /* Ugh! */
67 #include <asm/pvclock.h>
68 #include <asm/div64.h>
69 #include <asm/irq_remapping.h>
70 #include <asm/mshyperv.h>
71 #include <asm/hypervisor.h>
72
73 #define CREATE_TRACE_POINTS
74 #include "trace.h"
75
76 #define MAX_IO_MSRS 256
77 #define KVM_MAX_MCE_BANKS 32
78 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
80
81 #define emul_to_vcpu(ctxt) \
82         container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
84 /* EFER defaults:
85  * - enable syscall per default because its emulated by KVM
86  * - enable LME and LMA per default on 64 bit KVM
87  */
88 #ifdef CONFIG_X86_64
89 static
90 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
91 #else
92 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
93 #endif
94
95 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
97
98 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
100
101 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
102 static void process_nmi(struct kvm_vcpu *vcpu);
103 static void enter_smm(struct kvm_vcpu *vcpu);
104 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
105 static void store_regs(struct kvm_vcpu *vcpu);
106 static int sync_regs(struct kvm_vcpu *vcpu);
107
108 struct kvm_x86_ops *kvm_x86_ops __read_mostly;
109 EXPORT_SYMBOL_GPL(kvm_x86_ops);
110
111 static bool __read_mostly ignore_msrs = 0;
112 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
113
114 static bool __read_mostly report_ignored_msrs = true;
115 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
117 unsigned int min_timer_period_us = 200;
118 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
120 static bool __read_mostly kvmclock_periodic_sync = true;
121 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
123 bool __read_mostly kvm_has_tsc_control;
124 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
125 u32  __read_mostly kvm_max_guest_tsc_khz;
126 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
127 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129 u64  __read_mostly kvm_max_tsc_scaling_ratio;
130 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
131 u64 __read_mostly kvm_default_tsc_scaling_ratio;
132 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
133
134 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
135 static u32 __read_mostly tsc_tolerance_ppm = 250;
136 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
138 /* lapic timer advance (tscdeadline mode only) in nanoseconds */
139 unsigned int __read_mostly lapic_timer_advance_ns = 0;
140 module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
141
142 static bool __read_mostly vector_hashing = true;
143 module_param(vector_hashing, bool, S_IRUGO);
144
145 bool __read_mostly enable_vmware_backdoor = false;
146 module_param(enable_vmware_backdoor, bool, S_IRUGO);
147 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
148
149 static bool __read_mostly force_emulation_prefix = false;
150 module_param(force_emulation_prefix, bool, S_IRUGO);
151
152 #define KVM_NR_SHARED_MSRS 16
153
154 struct kvm_shared_msrs_global {
155         int nr;
156         u32 msrs[KVM_NR_SHARED_MSRS];
157 };
158
159 struct kvm_shared_msrs {
160         struct user_return_notifier urn;
161         bool registered;
162         struct kvm_shared_msr_values {
163                 u64 host;
164                 u64 curr;
165         } values[KVM_NR_SHARED_MSRS];
166 };
167
168 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
169 static struct kvm_shared_msrs __percpu *shared_msrs;
170
171 struct kvm_stats_debugfs_item debugfs_entries[] = {
172         { "pf_fixed", VCPU_STAT(pf_fixed) },
173         { "pf_guest", VCPU_STAT(pf_guest) },
174         { "tlb_flush", VCPU_STAT(tlb_flush) },
175         { "invlpg", VCPU_STAT(invlpg) },
176         { "exits", VCPU_STAT(exits) },
177         { "io_exits", VCPU_STAT(io_exits) },
178         { "mmio_exits", VCPU_STAT(mmio_exits) },
179         { "signal_exits", VCPU_STAT(signal_exits) },
180         { "irq_window", VCPU_STAT(irq_window_exits) },
181         { "nmi_window", VCPU_STAT(nmi_window_exits) },
182         { "halt_exits", VCPU_STAT(halt_exits) },
183         { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
184         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
185         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
186         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
187         { "hypercalls", VCPU_STAT(hypercalls) },
188         { "request_irq", VCPU_STAT(request_irq_exits) },
189         { "irq_exits", VCPU_STAT(irq_exits) },
190         { "host_state_reload", VCPU_STAT(host_state_reload) },
191         { "fpu_reload", VCPU_STAT(fpu_reload) },
192         { "insn_emulation", VCPU_STAT(insn_emulation) },
193         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
194         { "irq_injections", VCPU_STAT(irq_injections) },
195         { "nmi_injections", VCPU_STAT(nmi_injections) },
196         { "req_event", VCPU_STAT(req_event) },
197         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
198         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
199         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
200         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
201         { "mmu_flooded", VM_STAT(mmu_flooded) },
202         { "mmu_recycled", VM_STAT(mmu_recycled) },
203         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
204         { "mmu_unsync", VM_STAT(mmu_unsync) },
205         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
206         { "largepages", VM_STAT(lpages) },
207         { "max_mmu_page_hash_collisions",
208                 VM_STAT(max_mmu_page_hash_collisions) },
209         { NULL }
210 };
211
212 u64 __read_mostly host_xcr0;
213
214 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
215
216 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
217 {
218         int i;
219         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
220                 vcpu->arch.apf.gfns[i] = ~0;
221 }
222
223 static void kvm_on_user_return(struct user_return_notifier *urn)
224 {
225         unsigned slot;
226         struct kvm_shared_msrs *locals
227                 = container_of(urn, struct kvm_shared_msrs, urn);
228         struct kvm_shared_msr_values *values;
229         unsigned long flags;
230
231         /*
232          * Disabling irqs at this point since the following code could be
233          * interrupted and executed through kvm_arch_hardware_disable()
234          */
235         local_irq_save(flags);
236         if (locals->registered) {
237                 locals->registered = false;
238                 user_return_notifier_unregister(urn);
239         }
240         local_irq_restore(flags);
241         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
242                 values = &locals->values[slot];
243                 if (values->host != values->curr) {
244                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
245                         values->curr = values->host;
246                 }
247         }
248 }
249
250 static void shared_msr_update(unsigned slot, u32 msr)
251 {
252         u64 value;
253         unsigned int cpu = smp_processor_id();
254         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
255
256         /* only read, and nobody should modify it at this time,
257          * so don't need lock */
258         if (slot >= shared_msrs_global.nr) {
259                 printk(KERN_ERR "kvm: invalid MSR slot!");
260                 return;
261         }
262         rdmsrl_safe(msr, &value);
263         smsr->values[slot].host = value;
264         smsr->values[slot].curr = value;
265 }
266
267 void kvm_define_shared_msr(unsigned slot, u32 msr)
268 {
269         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
270         shared_msrs_global.msrs[slot] = msr;
271         if (slot >= shared_msrs_global.nr)
272                 shared_msrs_global.nr = slot + 1;
273 }
274 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
275
276 static void kvm_shared_msr_cpu_online(void)
277 {
278         unsigned i;
279
280         for (i = 0; i < shared_msrs_global.nr; ++i)
281                 shared_msr_update(i, shared_msrs_global.msrs[i]);
282 }
283
284 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
285 {
286         unsigned int cpu = smp_processor_id();
287         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
288         int err;
289
290         if (((value ^ smsr->values[slot].curr) & mask) == 0)
291                 return 0;
292         smsr->values[slot].curr = value;
293         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
294         if (err)
295                 return 1;
296
297         if (!smsr->registered) {
298                 smsr->urn.on_user_return = kvm_on_user_return;
299                 user_return_notifier_register(&smsr->urn);
300                 smsr->registered = true;
301         }
302         return 0;
303 }
304 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
305
306 static void drop_user_return_notifiers(void)
307 {
308         unsigned int cpu = smp_processor_id();
309         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
310
311         if (smsr->registered)
312                 kvm_on_user_return(&smsr->urn);
313 }
314
315 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
316 {
317         return vcpu->arch.apic_base;
318 }
319 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
320
321 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
322 {
323         u64 old_state = vcpu->arch.apic_base &
324                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
325         u64 new_state = msr_info->data &
326                 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
327         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
328                 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
329
330         if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
331                 return 1;
332         if (!msr_info->host_initiated &&
333             ((new_state == MSR_IA32_APICBASE_ENABLE &&
334               old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
335              (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
336               old_state == 0)))
337                 return 1;
338
339         kvm_lapic_set_base(vcpu, msr_info->data);
340         return 0;
341 }
342 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
343
344 asmlinkage __visible void kvm_spurious_fault(void)
345 {
346         /* Fault while not rebooting.  We want the trace. */
347         BUG();
348 }
349 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
350
351 #define EXCPT_BENIGN            0
352 #define EXCPT_CONTRIBUTORY      1
353 #define EXCPT_PF                2
354
355 static int exception_class(int vector)
356 {
357         switch (vector) {
358         case PF_VECTOR:
359                 return EXCPT_PF;
360         case DE_VECTOR:
361         case TS_VECTOR:
362         case NP_VECTOR:
363         case SS_VECTOR:
364         case GP_VECTOR:
365                 return EXCPT_CONTRIBUTORY;
366         default:
367                 break;
368         }
369         return EXCPT_BENIGN;
370 }
371
372 #define EXCPT_FAULT             0
373 #define EXCPT_TRAP              1
374 #define EXCPT_ABORT             2
375 #define EXCPT_INTERRUPT         3
376
377 static int exception_type(int vector)
378 {
379         unsigned int mask;
380
381         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
382                 return EXCPT_INTERRUPT;
383
384         mask = 1 << vector;
385
386         /* #DB is trap, as instruction watchpoints are handled elsewhere */
387         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
388                 return EXCPT_TRAP;
389
390         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
391                 return EXCPT_ABORT;
392
393         /* Reserved exceptions will result in fault */
394         return EXCPT_FAULT;
395 }
396
397 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
398                 unsigned nr, bool has_error, u32 error_code,
399                 bool reinject)
400 {
401         u32 prev_nr;
402         int class1, class2;
403
404         kvm_make_request(KVM_REQ_EVENT, vcpu);
405
406         if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
407         queue:
408                 if (has_error && !is_protmode(vcpu))
409                         has_error = false;
410                 if (reinject) {
411                         /*
412                          * On vmentry, vcpu->arch.exception.pending is only
413                          * true if an event injection was blocked by
414                          * nested_run_pending.  In that case, however,
415                          * vcpu_enter_guest requests an immediate exit,
416                          * and the guest shouldn't proceed far enough to
417                          * need reinjection.
418                          */
419                         WARN_ON_ONCE(vcpu->arch.exception.pending);
420                         vcpu->arch.exception.injected = true;
421                 } else {
422                         vcpu->arch.exception.pending = true;
423                         vcpu->arch.exception.injected = false;
424                 }
425                 vcpu->arch.exception.has_error_code = has_error;
426                 vcpu->arch.exception.nr = nr;
427                 vcpu->arch.exception.error_code = error_code;
428                 return;
429         }
430
431         /* to check exception */
432         prev_nr = vcpu->arch.exception.nr;
433         if (prev_nr == DF_VECTOR) {
434                 /* triple fault -> shutdown */
435                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
436                 return;
437         }
438         class1 = exception_class(prev_nr);
439         class2 = exception_class(nr);
440         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
441                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
442                 /*
443                  * Generate double fault per SDM Table 5-5.  Set
444                  * exception.pending = true so that the double fault
445                  * can trigger a nested vmexit.
446                  */
447                 vcpu->arch.exception.pending = true;
448                 vcpu->arch.exception.injected = false;
449                 vcpu->arch.exception.has_error_code = true;
450                 vcpu->arch.exception.nr = DF_VECTOR;
451                 vcpu->arch.exception.error_code = 0;
452         } else
453                 /* replace previous exception with a new one in a hope
454                    that instruction re-execution will regenerate lost
455                    exception */
456                 goto queue;
457 }
458
459 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
460 {
461         kvm_multiple_exception(vcpu, nr, false, 0, false);
462 }
463 EXPORT_SYMBOL_GPL(kvm_queue_exception);
464
465 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
466 {
467         kvm_multiple_exception(vcpu, nr, false, 0, true);
468 }
469 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
470
471 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
472 {
473         if (err)
474                 kvm_inject_gp(vcpu, 0);
475         else
476                 return kvm_skip_emulated_instruction(vcpu);
477
478         return 1;
479 }
480 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
481
482 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
483 {
484         ++vcpu->stat.pf_guest;
485         vcpu->arch.exception.nested_apf =
486                 is_guest_mode(vcpu) && fault->async_page_fault;
487         if (vcpu->arch.exception.nested_apf)
488                 vcpu->arch.apf.nested_apf_token = fault->address;
489         else
490                 vcpu->arch.cr2 = fault->address;
491         kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
492 }
493 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
494
495 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
496 {
497         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
498                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
499         else
500                 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
501
502         return fault->nested_page_fault;
503 }
504
505 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
506 {
507         atomic_inc(&vcpu->arch.nmi_queued);
508         kvm_make_request(KVM_REQ_NMI, vcpu);
509 }
510 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
511
512 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
513 {
514         kvm_multiple_exception(vcpu, nr, true, error_code, false);
515 }
516 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
517
518 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
519 {
520         kvm_multiple_exception(vcpu, nr, true, error_code, true);
521 }
522 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
523
524 /*
525  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
526  * a #GP and return false.
527  */
528 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
529 {
530         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
531                 return true;
532         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
533         return false;
534 }
535 EXPORT_SYMBOL_GPL(kvm_require_cpl);
536
537 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
538 {
539         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
540                 return true;
541
542         kvm_queue_exception(vcpu, UD_VECTOR);
543         return false;
544 }
545 EXPORT_SYMBOL_GPL(kvm_require_dr);
546
547 /*
548  * This function will be used to read from the physical memory of the currently
549  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
550  * can read from guest physical or from the guest's guest physical memory.
551  */
552 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
553                             gfn_t ngfn, void *data, int offset, int len,
554                             u32 access)
555 {
556         struct x86_exception exception;
557         gfn_t real_gfn;
558         gpa_t ngpa;
559
560         ngpa     = gfn_to_gpa(ngfn);
561         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
562         if (real_gfn == UNMAPPED_GVA)
563                 return -EFAULT;
564
565         real_gfn = gpa_to_gfn(real_gfn);
566
567         return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
568 }
569 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
570
571 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
572                                void *data, int offset, int len, u32 access)
573 {
574         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
575                                        data, offset, len, access);
576 }
577
578 /*
579  * Load the pae pdptrs.  Return true is they are all valid.
580  */
581 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
582 {
583         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
584         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
585         int i;
586         int ret;
587         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
588
589         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
590                                       offset * sizeof(u64), sizeof(pdpte),
591                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
592         if (ret < 0) {
593                 ret = 0;
594                 goto out;
595         }
596         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
597                 if ((pdpte[i] & PT_PRESENT_MASK) &&
598                     (pdpte[i] &
599                      vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
600                         ret = 0;
601                         goto out;
602                 }
603         }
604         ret = 1;
605
606         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
607         __set_bit(VCPU_EXREG_PDPTR,
608                   (unsigned long *)&vcpu->arch.regs_avail);
609         __set_bit(VCPU_EXREG_PDPTR,
610                   (unsigned long *)&vcpu->arch.regs_dirty);
611 out:
612
613         return ret;
614 }
615 EXPORT_SYMBOL_GPL(load_pdptrs);
616
617 bool pdptrs_changed(struct kvm_vcpu *vcpu)
618 {
619         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
620         bool changed = true;
621         int offset;
622         gfn_t gfn;
623         int r;
624
625         if (is_long_mode(vcpu) || !is_pae(vcpu))
626                 return false;
627
628         if (!test_bit(VCPU_EXREG_PDPTR,
629                       (unsigned long *)&vcpu->arch.regs_avail))
630                 return true;
631
632         gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
633         offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
634         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
635                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
636         if (r < 0)
637                 goto out;
638         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
639 out:
640
641         return changed;
642 }
643 EXPORT_SYMBOL_GPL(pdptrs_changed);
644
645 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
646 {
647         unsigned long old_cr0 = kvm_read_cr0(vcpu);
648         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
649
650         cr0 |= X86_CR0_ET;
651
652 #ifdef CONFIG_X86_64
653         if (cr0 & 0xffffffff00000000UL)
654                 return 1;
655 #endif
656
657         cr0 &= ~CR0_RESERVED_BITS;
658
659         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
660                 return 1;
661
662         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
663                 return 1;
664
665         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
666 #ifdef CONFIG_X86_64
667                 if ((vcpu->arch.efer & EFER_LME)) {
668                         int cs_db, cs_l;
669
670                         if (!is_pae(vcpu))
671                                 return 1;
672                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
673                         if (cs_l)
674                                 return 1;
675                 } else
676 #endif
677                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
678                                                  kvm_read_cr3(vcpu)))
679                         return 1;
680         }
681
682         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
683                 return 1;
684
685         kvm_x86_ops->set_cr0(vcpu, cr0);
686
687         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
688                 kvm_clear_async_pf_completion_queue(vcpu);
689                 kvm_async_pf_hash_reset(vcpu);
690         }
691
692         if ((cr0 ^ old_cr0) & update_bits)
693                 kvm_mmu_reset_context(vcpu);
694
695         if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
696             kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
697             !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
698                 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
699
700         return 0;
701 }
702 EXPORT_SYMBOL_GPL(kvm_set_cr0);
703
704 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
705 {
706         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
707 }
708 EXPORT_SYMBOL_GPL(kvm_lmsw);
709
710 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
711 {
712         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
713                         !vcpu->guest_xcr0_loaded) {
714                 /* kvm_set_xcr() also depends on this */
715                 if (vcpu->arch.xcr0 != host_xcr0)
716                         xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
717                 vcpu->guest_xcr0_loaded = 1;
718         }
719 }
720
721 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
722 {
723         if (vcpu->guest_xcr0_loaded) {
724                 if (vcpu->arch.xcr0 != host_xcr0)
725                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
726                 vcpu->guest_xcr0_loaded = 0;
727         }
728 }
729
730 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
731 {
732         u64 xcr0 = xcr;
733         u64 old_xcr0 = vcpu->arch.xcr0;
734         u64 valid_bits;
735
736         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
737         if (index != XCR_XFEATURE_ENABLED_MASK)
738                 return 1;
739         if (!(xcr0 & XFEATURE_MASK_FP))
740                 return 1;
741         if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
742                 return 1;
743
744         /*
745          * Do not allow the guest to set bits that we do not support
746          * saving.  However, xcr0 bit 0 is always set, even if the
747          * emulated CPU does not support XSAVE (see fx_init).
748          */
749         valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
750         if (xcr0 & ~valid_bits)
751                 return 1;
752
753         if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
754             (!(xcr0 & XFEATURE_MASK_BNDCSR)))
755                 return 1;
756
757         if (xcr0 & XFEATURE_MASK_AVX512) {
758                 if (!(xcr0 & XFEATURE_MASK_YMM))
759                         return 1;
760                 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
761                         return 1;
762         }
763         vcpu->arch.xcr0 = xcr0;
764
765         if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
766                 kvm_update_cpuid(vcpu);
767         return 0;
768 }
769
770 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
771 {
772         if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
773             __kvm_set_xcr(vcpu, index, xcr)) {
774                 kvm_inject_gp(vcpu, 0);
775                 return 1;
776         }
777         return 0;
778 }
779 EXPORT_SYMBOL_GPL(kvm_set_xcr);
780
781 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
782 {
783         unsigned long old_cr4 = kvm_read_cr4(vcpu);
784         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
785                                    X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
786
787         if (cr4 & CR4_RESERVED_BITS)
788                 return 1;
789
790         if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
791                 return 1;
792
793         if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
794                 return 1;
795
796         if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
797                 return 1;
798
799         if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
800                 return 1;
801
802         if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
803                 return 1;
804
805         if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
806                 return 1;
807
808         if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
809                 return 1;
810
811         if (is_long_mode(vcpu)) {
812                 if (!(cr4 & X86_CR4_PAE))
813                         return 1;
814         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
815                    && ((cr4 ^ old_cr4) & pdptr_bits)
816                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
817                                    kvm_read_cr3(vcpu)))
818                 return 1;
819
820         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
821                 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
822                         return 1;
823
824                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
825                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
826                         return 1;
827         }
828
829         if (kvm_x86_ops->set_cr4(vcpu, cr4))
830                 return 1;
831
832         if (((cr4 ^ old_cr4) & pdptr_bits) ||
833             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
834                 kvm_mmu_reset_context(vcpu);
835
836         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
837                 kvm_update_cpuid(vcpu);
838
839         return 0;
840 }
841 EXPORT_SYMBOL_GPL(kvm_set_cr4);
842
843 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
844 {
845 #ifdef CONFIG_X86_64
846         bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
847
848         if (pcid_enabled)
849                 cr3 &= ~CR3_PCID_INVD;
850 #endif
851
852         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
853                 kvm_mmu_sync_roots(vcpu);
854                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
855                 return 0;
856         }
857
858         if (is_long_mode(vcpu) &&
859             (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
860                 return 1;
861         else if (is_pae(vcpu) && is_paging(vcpu) &&
862                    !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
863                 return 1;
864
865         vcpu->arch.cr3 = cr3;
866         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
867         kvm_mmu_new_cr3(vcpu);
868         return 0;
869 }
870 EXPORT_SYMBOL_GPL(kvm_set_cr3);
871
872 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
873 {
874         if (cr8 & CR8_RESERVED_BITS)
875                 return 1;
876         if (lapic_in_kernel(vcpu))
877                 kvm_lapic_set_tpr(vcpu, cr8);
878         else
879                 vcpu->arch.cr8 = cr8;
880         return 0;
881 }
882 EXPORT_SYMBOL_GPL(kvm_set_cr8);
883
884 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
885 {
886         if (lapic_in_kernel(vcpu))
887                 return kvm_lapic_get_cr8(vcpu);
888         else
889                 return vcpu->arch.cr8;
890 }
891 EXPORT_SYMBOL_GPL(kvm_get_cr8);
892
893 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
894 {
895         int i;
896
897         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
898                 for (i = 0; i < KVM_NR_DB_REGS; i++)
899                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
900                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
901         }
902 }
903
904 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
905 {
906         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
907                 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
908 }
909
910 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
911 {
912         unsigned long dr7;
913
914         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
915                 dr7 = vcpu->arch.guest_debug_dr7;
916         else
917                 dr7 = vcpu->arch.dr7;
918         kvm_x86_ops->set_dr7(vcpu, dr7);
919         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
920         if (dr7 & DR7_BP_EN_MASK)
921                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
922 }
923
924 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
925 {
926         u64 fixed = DR6_FIXED_1;
927
928         if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
929                 fixed |= DR6_RTM;
930         return fixed;
931 }
932
933 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
934 {
935         switch (dr) {
936         case 0 ... 3:
937                 vcpu->arch.db[dr] = val;
938                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
939                         vcpu->arch.eff_db[dr] = val;
940                 break;
941         case 4:
942                 /* fall through */
943         case 6:
944                 if (val & 0xffffffff00000000ULL)
945                         return -1; /* #GP */
946                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
947                 kvm_update_dr6(vcpu);
948                 break;
949         case 5:
950                 /* fall through */
951         default: /* 7 */
952                 if (val & 0xffffffff00000000ULL)
953                         return -1; /* #GP */
954                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
955                 kvm_update_dr7(vcpu);
956                 break;
957         }
958
959         return 0;
960 }
961
962 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
963 {
964         if (__kvm_set_dr(vcpu, dr, val)) {
965                 kvm_inject_gp(vcpu, 0);
966                 return 1;
967         }
968         return 0;
969 }
970 EXPORT_SYMBOL_GPL(kvm_set_dr);
971
972 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
973 {
974         switch (dr) {
975         case 0 ... 3:
976                 *val = vcpu->arch.db[dr];
977                 break;
978         case 4:
979                 /* fall through */
980         case 6:
981                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
982                         *val = vcpu->arch.dr6;
983                 else
984                         *val = kvm_x86_ops->get_dr6(vcpu);
985                 break;
986         case 5:
987                 /* fall through */
988         default: /* 7 */
989                 *val = vcpu->arch.dr7;
990                 break;
991         }
992         return 0;
993 }
994 EXPORT_SYMBOL_GPL(kvm_get_dr);
995
996 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
997 {
998         u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
999         u64 data;
1000         int err;
1001
1002         err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1003         if (err)
1004                 return err;
1005         kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1006         kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1007         return err;
1008 }
1009 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1010
1011 /*
1012  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1013  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1014  *
1015  * This list is modified at module load time to reflect the
1016  * capabilities of the host cpu. This capabilities test skips MSRs that are
1017  * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1018  * may depend on host virtualization features rather than host cpu features.
1019  */
1020
1021 static u32 msrs_to_save[] = {
1022         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1023         MSR_STAR,
1024 #ifdef CONFIG_X86_64
1025         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1026 #endif
1027         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1028         MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1029         MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
1030 };
1031
1032 static unsigned num_msrs_to_save;
1033
1034 static u32 emulated_msrs[] = {
1035         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1036         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1037         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1038         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1039         HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1040         HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1041         HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1042         HV_X64_MSR_RESET,
1043         HV_X64_MSR_VP_INDEX,
1044         HV_X64_MSR_VP_RUNTIME,
1045         HV_X64_MSR_SCONTROL,
1046         HV_X64_MSR_STIMER0_CONFIG,
1047         HV_X64_MSR_VP_ASSIST_PAGE,
1048         HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1049         HV_X64_MSR_TSC_EMULATION_STATUS,
1050
1051         MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1052         MSR_KVM_PV_EOI_EN,
1053
1054         MSR_IA32_TSC_ADJUST,
1055         MSR_IA32_TSCDEADLINE,
1056         MSR_IA32_MISC_ENABLE,
1057         MSR_IA32_MCG_STATUS,
1058         MSR_IA32_MCG_CTL,
1059         MSR_IA32_MCG_EXT_CTL,
1060         MSR_IA32_SMBASE,
1061         MSR_SMI_COUNT,
1062         MSR_PLATFORM_INFO,
1063         MSR_MISC_FEATURES_ENABLES,
1064         MSR_AMD64_VIRT_SPEC_CTRL,
1065 };
1066
1067 static unsigned num_emulated_msrs;
1068
1069 /*
1070  * List of msr numbers which are used to expose MSR-based features that
1071  * can be used by a hypervisor to validate requested CPU features.
1072  */
1073 static u32 msr_based_features[] = {
1074         MSR_IA32_VMX_BASIC,
1075         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1076         MSR_IA32_VMX_PINBASED_CTLS,
1077         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1078         MSR_IA32_VMX_PROCBASED_CTLS,
1079         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1080         MSR_IA32_VMX_EXIT_CTLS,
1081         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1082         MSR_IA32_VMX_ENTRY_CTLS,
1083         MSR_IA32_VMX_MISC,
1084         MSR_IA32_VMX_CR0_FIXED0,
1085         MSR_IA32_VMX_CR0_FIXED1,
1086         MSR_IA32_VMX_CR4_FIXED0,
1087         MSR_IA32_VMX_CR4_FIXED1,
1088         MSR_IA32_VMX_VMCS_ENUM,
1089         MSR_IA32_VMX_PROCBASED_CTLS2,
1090         MSR_IA32_VMX_EPT_VPID_CAP,
1091         MSR_IA32_VMX_VMFUNC,
1092
1093         MSR_F10H_DECFG,
1094         MSR_IA32_UCODE_REV,
1095 };
1096
1097 static unsigned int num_msr_based_features;
1098
1099 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1100 {
1101         switch (msr->index) {
1102         case MSR_IA32_UCODE_REV:
1103                 rdmsrl(msr->index, msr->data);
1104                 break;
1105         default:
1106                 if (kvm_x86_ops->get_msr_feature(msr))
1107                         return 1;
1108         }
1109         return 0;
1110 }
1111
1112 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1113 {
1114         struct kvm_msr_entry msr;
1115         int r;
1116
1117         msr.index = index;
1118         r = kvm_get_msr_feature(&msr);
1119         if (r)
1120                 return r;
1121
1122         *data = msr.data;
1123
1124         return 0;
1125 }
1126
1127 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1128 {
1129         if (efer & efer_reserved_bits)
1130                 return false;
1131
1132         if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1133                         return false;
1134
1135         if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1136                         return false;
1137
1138         return true;
1139 }
1140 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1141
1142 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1143 {
1144         u64 old_efer = vcpu->arch.efer;
1145
1146         if (!kvm_valid_efer(vcpu, efer))
1147                 return 1;
1148
1149         if (is_paging(vcpu)
1150             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1151                 return 1;
1152
1153         efer &= ~EFER_LMA;
1154         efer |= vcpu->arch.efer & EFER_LMA;
1155
1156         kvm_x86_ops->set_efer(vcpu, efer);
1157
1158         /* Update reserved bits */
1159         if ((efer ^ old_efer) & EFER_NX)
1160                 kvm_mmu_reset_context(vcpu);
1161
1162         return 0;
1163 }
1164
1165 void kvm_enable_efer_bits(u64 mask)
1166 {
1167        efer_reserved_bits &= ~mask;
1168 }
1169 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1170
1171 /*
1172  * Writes msr value into into the appropriate "register".
1173  * Returns 0 on success, non-0 otherwise.
1174  * Assumes vcpu_load() was already called.
1175  */
1176 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
1177 {
1178         switch (msr->index) {
1179         case MSR_FS_BASE:
1180         case MSR_GS_BASE:
1181         case MSR_KERNEL_GS_BASE:
1182         case MSR_CSTAR:
1183         case MSR_LSTAR:
1184                 if (is_noncanonical_address(msr->data, vcpu))
1185                         return 1;
1186                 break;
1187         case MSR_IA32_SYSENTER_EIP:
1188         case MSR_IA32_SYSENTER_ESP:
1189                 /*
1190                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1191                  * non-canonical address is written on Intel but not on
1192                  * AMD (which ignores the top 32-bits, because it does
1193                  * not implement 64-bit SYSENTER).
1194                  *
1195                  * 64-bit code should hence be able to write a non-canonical
1196                  * value on AMD.  Making the address canonical ensures that
1197                  * vmentry does not fail on Intel after writing a non-canonical
1198                  * value, and that something deterministic happens if the guest
1199                  * invokes 64-bit SYSENTER.
1200                  */
1201                 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
1202         }
1203         return kvm_x86_ops->set_msr(vcpu, msr);
1204 }
1205 EXPORT_SYMBOL_GPL(kvm_set_msr);
1206
1207 /*
1208  * Adapt set_msr() to msr_io()'s calling convention
1209  */
1210 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1211 {
1212         struct msr_data msr;
1213         int r;
1214
1215         msr.index = index;
1216         msr.host_initiated = true;
1217         r = kvm_get_msr(vcpu, &msr);
1218         if (r)
1219                 return r;
1220
1221         *data = msr.data;
1222         return 0;
1223 }
1224
1225 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1226 {
1227         struct msr_data msr;
1228
1229         msr.data = *data;
1230         msr.index = index;
1231         msr.host_initiated = true;
1232         return kvm_set_msr(vcpu, &msr);
1233 }
1234
1235 #ifdef CONFIG_X86_64
1236 struct pvclock_gtod_data {
1237         seqcount_t      seq;
1238
1239         struct { /* extract of a clocksource struct */
1240                 int vclock_mode;
1241                 u64     cycle_last;
1242                 u64     mask;
1243                 u32     mult;
1244                 u32     shift;
1245         } clock;
1246
1247         u64             boot_ns;
1248         u64             nsec_base;
1249         u64             wall_time_sec;
1250 };
1251
1252 static struct pvclock_gtod_data pvclock_gtod_data;
1253
1254 static void update_pvclock_gtod(struct timekeeper *tk)
1255 {
1256         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1257         u64 boot_ns;
1258
1259         boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
1260
1261         write_seqcount_begin(&vdata->seq);
1262
1263         /* copy pvclock gtod data */
1264         vdata->clock.vclock_mode        = tk->tkr_mono.clock->archdata.vclock_mode;
1265         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1266         vdata->clock.mask               = tk->tkr_mono.mask;
1267         vdata->clock.mult               = tk->tkr_mono.mult;
1268         vdata->clock.shift              = tk->tkr_mono.shift;
1269
1270         vdata->boot_ns                  = boot_ns;
1271         vdata->nsec_base                = tk->tkr_mono.xtime_nsec;
1272
1273         vdata->wall_time_sec            = tk->xtime_sec;
1274
1275         write_seqcount_end(&vdata->seq);
1276 }
1277 #endif
1278
1279 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1280 {
1281         /*
1282          * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1283          * vcpu_enter_guest.  This function is only called from
1284          * the physical CPU that is running vcpu.
1285          */
1286         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1287 }
1288
1289 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1290 {
1291         int version;
1292         int r;
1293         struct pvclock_wall_clock wc;
1294         struct timespec64 boot;
1295
1296         if (!wall_clock)
1297                 return;
1298
1299         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1300         if (r)
1301                 return;
1302
1303         if (version & 1)
1304                 ++version;  /* first time write, random junk */
1305
1306         ++version;
1307
1308         if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1309                 return;
1310
1311         /*
1312          * The guest calculates current wall clock time by adding
1313          * system time (updated by kvm_guest_time_update below) to the
1314          * wall clock specified here.  guest system time equals host
1315          * system time for us, thus we must fill in host boot time here.
1316          */
1317         getboottime64(&boot);
1318
1319         if (kvm->arch.kvmclock_offset) {
1320                 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1321                 boot = timespec64_sub(boot, ts);
1322         }
1323         wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
1324         wc.nsec = boot.tv_nsec;
1325         wc.version = version;
1326
1327         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1328
1329         version++;
1330         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1331 }
1332
1333 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1334 {
1335         do_shl32_div32(dividend, divisor);
1336         return dividend;
1337 }
1338
1339 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1340                                s8 *pshift, u32 *pmultiplier)
1341 {
1342         uint64_t scaled64;
1343         int32_t  shift = 0;
1344         uint64_t tps64;
1345         uint32_t tps32;
1346
1347         tps64 = base_hz;
1348         scaled64 = scaled_hz;
1349         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1350                 tps64 >>= 1;
1351                 shift--;
1352         }
1353
1354         tps32 = (uint32_t)tps64;
1355         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1356                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1357                         scaled64 >>= 1;
1358                 else
1359                         tps32 <<= 1;
1360                 shift++;
1361         }
1362
1363         *pshift = shift;
1364         *pmultiplier = div_frac(scaled64, tps32);
1365
1366         pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1367                  __func__, base_hz, scaled_hz, shift, *pmultiplier);
1368 }
1369
1370 #ifdef CONFIG_X86_64
1371 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1372 #endif
1373
1374 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1375 static unsigned long max_tsc_khz;
1376
1377 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1378 {
1379         u64 v = (u64)khz * (1000000 + ppm);
1380         do_div(v, 1000000);
1381         return v;
1382 }
1383
1384 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1385 {
1386         u64 ratio;
1387
1388         /* Guest TSC same frequency as host TSC? */
1389         if (!scale) {
1390                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1391                 return 0;
1392         }
1393
1394         /* TSC scaling supported? */
1395         if (!kvm_has_tsc_control) {
1396                 if (user_tsc_khz > tsc_khz) {
1397                         vcpu->arch.tsc_catchup = 1;
1398                         vcpu->arch.tsc_always_catchup = 1;
1399                         return 0;
1400                 } else {
1401                         WARN(1, "user requested TSC rate below hardware speed\n");
1402                         return -1;
1403                 }
1404         }
1405
1406         /* TSC scaling required  - calculate ratio */
1407         ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1408                                 user_tsc_khz, tsc_khz);
1409
1410         if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1411                 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1412                           user_tsc_khz);
1413                 return -1;
1414         }
1415
1416         vcpu->arch.tsc_scaling_ratio = ratio;
1417         return 0;
1418 }
1419
1420 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1421 {
1422         u32 thresh_lo, thresh_hi;
1423         int use_scaling = 0;
1424
1425         /* tsc_khz can be zero if TSC calibration fails */
1426         if (user_tsc_khz == 0) {
1427                 /* set tsc_scaling_ratio to a safe value */
1428                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1429                 return -1;
1430         }
1431
1432         /* Compute a scale to convert nanoseconds in TSC cycles */
1433         kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1434                            &vcpu->arch.virtual_tsc_shift,
1435                            &vcpu->arch.virtual_tsc_mult);
1436         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1437
1438         /*
1439          * Compute the variation in TSC rate which is acceptable
1440          * within the range of tolerance and decide if the
1441          * rate being applied is within that bounds of the hardware
1442          * rate.  If so, no scaling or compensation need be done.
1443          */
1444         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1445         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1446         if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1447                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1448                 use_scaling = 1;
1449         }
1450         return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1451 }
1452
1453 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1454 {
1455         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1456                                       vcpu->arch.virtual_tsc_mult,
1457                                       vcpu->arch.virtual_tsc_shift);
1458         tsc += vcpu->arch.this_tsc_write;
1459         return tsc;
1460 }
1461
1462 static inline int gtod_is_based_on_tsc(int mode)
1463 {
1464         return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1465 }
1466
1467 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1468 {
1469 #ifdef CONFIG_X86_64
1470         bool vcpus_matched;
1471         struct kvm_arch *ka = &vcpu->kvm->arch;
1472         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1473
1474         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1475                          atomic_read(&vcpu->kvm->online_vcpus));
1476
1477         /*
1478          * Once the masterclock is enabled, always perform request in
1479          * order to update it.
1480          *
1481          * In order to enable masterclock, the host clocksource must be TSC
1482          * and the vcpus need to have matched TSCs.  When that happens,
1483          * perform request to enable masterclock.
1484          */
1485         if (ka->use_master_clock ||
1486             (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1487                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1488
1489         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1490                             atomic_read(&vcpu->kvm->online_vcpus),
1491                             ka->use_master_clock, gtod->clock.vclock_mode);
1492 #endif
1493 }
1494
1495 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1496 {
1497         u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1498         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1499 }
1500
1501 /*
1502  * Multiply tsc by a fixed point number represented by ratio.
1503  *
1504  * The most significant 64-N bits (mult) of ratio represent the
1505  * integral part of the fixed point number; the remaining N bits
1506  * (frac) represent the fractional part, ie. ratio represents a fixed
1507  * point number (mult + frac * 2^(-N)).
1508  *
1509  * N equals to kvm_tsc_scaling_ratio_frac_bits.
1510  */
1511 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1512 {
1513         return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1514 }
1515
1516 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1517 {
1518         u64 _tsc = tsc;
1519         u64 ratio = vcpu->arch.tsc_scaling_ratio;
1520
1521         if (ratio != kvm_default_tsc_scaling_ratio)
1522                 _tsc = __scale_tsc(ratio, tsc);
1523
1524         return _tsc;
1525 }
1526 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1527
1528 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1529 {
1530         u64 tsc;
1531
1532         tsc = kvm_scale_tsc(vcpu, rdtsc());
1533
1534         return target_tsc - tsc;
1535 }
1536
1537 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1538 {
1539         u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1540
1541         return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1542 }
1543 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1544
1545 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1546 {
1547         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1548         vcpu->arch.tsc_offset = offset;
1549 }
1550
1551 static inline bool kvm_check_tsc_unstable(void)
1552 {
1553 #ifdef CONFIG_X86_64
1554         /*
1555          * TSC is marked unstable when we're running on Hyper-V,
1556          * 'TSC page' clocksource is good.
1557          */
1558         if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1559                 return false;
1560 #endif
1561         return check_tsc_unstable();
1562 }
1563
1564 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1565 {
1566         struct kvm *kvm = vcpu->kvm;
1567         u64 offset, ns, elapsed;
1568         unsigned long flags;
1569         bool matched;
1570         bool already_matched;
1571         u64 data = msr->data;
1572         bool synchronizing = false;
1573
1574         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1575         offset = kvm_compute_tsc_offset(vcpu, data);
1576         ns = ktime_get_boot_ns();
1577         elapsed = ns - kvm->arch.last_tsc_nsec;
1578
1579         if (vcpu->arch.virtual_tsc_khz) {
1580                 if (data == 0 && msr->host_initiated) {
1581                         /*
1582                          * detection of vcpu initialization -- need to sync
1583                          * with other vCPUs. This particularly helps to keep
1584                          * kvm_clock stable after CPU hotplug
1585                          */
1586                         synchronizing = true;
1587                 } else {
1588                         u64 tsc_exp = kvm->arch.last_tsc_write +
1589                                                 nsec_to_cycles(vcpu, elapsed);
1590                         u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1591                         /*
1592                          * Special case: TSC write with a small delta (1 second)
1593                          * of virtual cycle time against real time is
1594                          * interpreted as an attempt to synchronize the CPU.
1595                          */
1596                         synchronizing = data < tsc_exp + tsc_hz &&
1597                                         data + tsc_hz > tsc_exp;
1598                 }
1599         }
1600
1601         /*
1602          * For a reliable TSC, we can match TSC offsets, and for an unstable
1603          * TSC, we add elapsed time in this computation.  We could let the
1604          * compensation code attempt to catch up if we fall behind, but
1605          * it's better to try to match offsets from the beginning.
1606          */
1607         if (synchronizing &&
1608             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1609                 if (!kvm_check_tsc_unstable()) {
1610                         offset = kvm->arch.cur_tsc_offset;
1611                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1612                 } else {
1613                         u64 delta = nsec_to_cycles(vcpu, elapsed);
1614                         data += delta;
1615                         offset = kvm_compute_tsc_offset(vcpu, data);
1616                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1617                 }
1618                 matched = true;
1619                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
1620         } else {
1621                 /*
1622                  * We split periods of matched TSC writes into generations.
1623                  * For each generation, we track the original measured
1624                  * nanosecond time, offset, and write, so if TSCs are in
1625                  * sync, we can match exact offset, and if not, we can match
1626                  * exact software computation in compute_guest_tsc()
1627                  *
1628                  * These values are tracked in kvm->arch.cur_xxx variables.
1629                  */
1630                 kvm->arch.cur_tsc_generation++;
1631                 kvm->arch.cur_tsc_nsec = ns;
1632                 kvm->arch.cur_tsc_write = data;
1633                 kvm->arch.cur_tsc_offset = offset;
1634                 matched = false;
1635                 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
1636                          kvm->arch.cur_tsc_generation, data);
1637         }
1638
1639         /*
1640          * We also track th most recent recorded KHZ, write and time to
1641          * allow the matching interval to be extended at each write.
1642          */
1643         kvm->arch.last_tsc_nsec = ns;
1644         kvm->arch.last_tsc_write = data;
1645         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1646
1647         vcpu->arch.last_guest_tsc = data;
1648
1649         /* Keep track of which generation this VCPU has synchronized to */
1650         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1651         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1652         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1653
1654         if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
1655                 update_ia32_tsc_adjust_msr(vcpu, offset);
1656
1657         kvm_vcpu_write_tsc_offset(vcpu, offset);
1658         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1659
1660         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1661         if (!matched) {
1662                 kvm->arch.nr_vcpus_matched_tsc = 0;
1663         } else if (!already_matched) {
1664                 kvm->arch.nr_vcpus_matched_tsc++;
1665         }
1666
1667         kvm_track_tsc_matching(vcpu);
1668         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1669 }
1670
1671 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1672
1673 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1674                                            s64 adjustment)
1675 {
1676         kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
1677 }
1678
1679 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1680 {
1681         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1682                 WARN_ON(adjustment < 0);
1683         adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1684         adjust_tsc_offset_guest(vcpu, adjustment);
1685 }
1686
1687 #ifdef CONFIG_X86_64
1688
1689 static u64 read_tsc(void)
1690 {
1691         u64 ret = (u64)rdtsc_ordered();
1692         u64 last = pvclock_gtod_data.clock.cycle_last;
1693
1694         if (likely(ret >= last))
1695                 return ret;
1696
1697         /*
1698          * GCC likes to generate cmov here, but this branch is extremely
1699          * predictable (it's just a function of time and the likely is
1700          * very likely) and there's a data dependence, so force GCC
1701          * to generate a branch instead.  I don't barrier() because
1702          * we don't actually need a barrier, and if this function
1703          * ever gets inlined it will generate worse code.
1704          */
1705         asm volatile ("");
1706         return last;
1707 }
1708
1709 static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
1710 {
1711         long v;
1712         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1713         u64 tsc_pg_val;
1714
1715         switch (gtod->clock.vclock_mode) {
1716         case VCLOCK_HVCLOCK:
1717                 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1718                                                   tsc_timestamp);
1719                 if (tsc_pg_val != U64_MAX) {
1720                         /* TSC page valid */
1721                         *mode = VCLOCK_HVCLOCK;
1722                         v = (tsc_pg_val - gtod->clock.cycle_last) &
1723                                 gtod->clock.mask;
1724                 } else {
1725                         /* TSC page invalid */
1726                         *mode = VCLOCK_NONE;
1727                 }
1728                 break;
1729         case VCLOCK_TSC:
1730                 *mode = VCLOCK_TSC;
1731                 *tsc_timestamp = read_tsc();
1732                 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1733                         gtod->clock.mask;
1734                 break;
1735         default:
1736                 *mode = VCLOCK_NONE;
1737         }
1738
1739         if (*mode == VCLOCK_NONE)
1740                 *tsc_timestamp = v = 0;
1741
1742         return v * gtod->clock.mult;
1743 }
1744
1745 static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
1746 {
1747         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1748         unsigned long seq;
1749         int mode;
1750         u64 ns;
1751
1752         do {
1753                 seq = read_seqcount_begin(&gtod->seq);
1754                 ns = gtod->nsec_base;
1755                 ns += vgettsc(tsc_timestamp, &mode);
1756                 ns >>= gtod->clock.shift;
1757                 ns += gtod->boot_ns;
1758         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1759         *t = ns;
1760
1761         return mode;
1762 }
1763
1764 static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
1765 {
1766         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1767         unsigned long seq;
1768         int mode;
1769         u64 ns;
1770
1771         do {
1772                 seq = read_seqcount_begin(&gtod->seq);
1773                 ts->tv_sec = gtod->wall_time_sec;
1774                 ns = gtod->nsec_base;
1775                 ns += vgettsc(tsc_timestamp, &mode);
1776                 ns >>= gtod->clock.shift;
1777         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1778
1779         ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1780         ts->tv_nsec = ns;
1781
1782         return mode;
1783 }
1784
1785 /* returns true if host is using TSC based clocksource */
1786 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
1787 {
1788         /* checked again under seqlock below */
1789         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1790                 return false;
1791
1792         return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1793                                                       tsc_timestamp));
1794 }
1795
1796 /* returns true if host is using TSC based clocksource */
1797 static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1798                                            u64 *tsc_timestamp)
1799 {
1800         /* checked again under seqlock below */
1801         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
1802                 return false;
1803
1804         return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
1805 }
1806 #endif
1807
1808 /*
1809  *
1810  * Assuming a stable TSC across physical CPUS, and a stable TSC
1811  * across virtual CPUs, the following condition is possible.
1812  * Each numbered line represents an event visible to both
1813  * CPUs at the next numbered event.
1814  *
1815  * "timespecX" represents host monotonic time. "tscX" represents
1816  * RDTSC value.
1817  *
1818  *              VCPU0 on CPU0           |       VCPU1 on CPU1
1819  *
1820  * 1.  read timespec0,tsc0
1821  * 2.                                   | timespec1 = timespec0 + N
1822  *                                      | tsc1 = tsc0 + M
1823  * 3. transition to guest               | transition to guest
1824  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1825  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
1826  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1827  *
1828  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1829  *
1830  *      - ret0 < ret1
1831  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1832  *              ...
1833  *      - 0 < N - M => M < N
1834  *
1835  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1836  * always the case (the difference between two distinct xtime instances
1837  * might be smaller then the difference between corresponding TSC reads,
1838  * when updating guest vcpus pvclock areas).
1839  *
1840  * To avoid that problem, do not allow visibility of distinct
1841  * system_timestamp/tsc_timestamp values simultaneously: use a master
1842  * copy of host monotonic time values. Update that master copy
1843  * in lockstep.
1844  *
1845  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1846  *
1847  */
1848
1849 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1850 {
1851 #ifdef CONFIG_X86_64
1852         struct kvm_arch *ka = &kvm->arch;
1853         int vclock_mode;
1854         bool host_tsc_clocksource, vcpus_matched;
1855
1856         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1857                         atomic_read(&kvm->online_vcpus));
1858
1859         /*
1860          * If the host uses TSC clock, then passthrough TSC as stable
1861          * to the guest.
1862          */
1863         host_tsc_clocksource = kvm_get_time_and_clockread(
1864                                         &ka->master_kernel_ns,
1865                                         &ka->master_cycle_now);
1866
1867         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1868                                 && !ka->backwards_tsc_observed
1869                                 && !ka->boot_vcpu_runs_old_kvmclock;
1870
1871         if (ka->use_master_clock)
1872                 atomic_set(&kvm_guest_has_master_clock, 1);
1873
1874         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1875         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1876                                         vcpus_matched);
1877 #endif
1878 }
1879
1880 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1881 {
1882         kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1883 }
1884
1885 static void kvm_gen_update_masterclock(struct kvm *kvm)
1886 {
1887 #ifdef CONFIG_X86_64
1888         int i;
1889         struct kvm_vcpu *vcpu;
1890         struct kvm_arch *ka = &kvm->arch;
1891
1892         spin_lock(&ka->pvclock_gtod_sync_lock);
1893         kvm_make_mclock_inprogress_request(kvm);
1894         /* no guest entries from this point */
1895         pvclock_update_vm_gtod_copy(kvm);
1896
1897         kvm_for_each_vcpu(i, vcpu, kvm)
1898                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1899
1900         /* guest entries allowed */
1901         kvm_for_each_vcpu(i, vcpu, kvm)
1902                 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
1903
1904         spin_unlock(&ka->pvclock_gtod_sync_lock);
1905 #endif
1906 }
1907
1908 u64 get_kvmclock_ns(struct kvm *kvm)
1909 {
1910         struct kvm_arch *ka = &kvm->arch;
1911         struct pvclock_vcpu_time_info hv_clock;
1912         u64 ret;
1913
1914         spin_lock(&ka->pvclock_gtod_sync_lock);
1915         if (!ka->use_master_clock) {
1916                 spin_unlock(&ka->pvclock_gtod_sync_lock);
1917                 return ktime_get_boot_ns() + ka->kvmclock_offset;
1918         }
1919
1920         hv_clock.tsc_timestamp = ka->master_cycle_now;
1921         hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1922         spin_unlock(&ka->pvclock_gtod_sync_lock);
1923
1924         /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1925         get_cpu();
1926
1927         if (__this_cpu_read(cpu_tsc_khz)) {
1928                 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1929                                    &hv_clock.tsc_shift,
1930                                    &hv_clock.tsc_to_system_mul);
1931                 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1932         } else
1933                 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
1934
1935         put_cpu();
1936
1937         return ret;
1938 }
1939
1940 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1941 {
1942         struct kvm_vcpu_arch *vcpu = &v->arch;
1943         struct pvclock_vcpu_time_info guest_hv_clock;
1944
1945         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1946                 &guest_hv_clock, sizeof(guest_hv_clock))))
1947                 return;
1948
1949         /* This VCPU is paused, but it's legal for a guest to read another
1950          * VCPU's kvmclock, so we really have to follow the specification where
1951          * it says that version is odd if data is being modified, and even after
1952          * it is consistent.
1953          *
1954          * Version field updates must be kept separate.  This is because
1955          * kvm_write_guest_cached might use a "rep movs" instruction, and
1956          * writes within a string instruction are weakly ordered.  So there
1957          * are three writes overall.
1958          *
1959          * As a small optimization, only write the version field in the first
1960          * and third write.  The vcpu->pv_time cache is still valid, because the
1961          * version field is the first in the struct.
1962          */
1963         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1964
1965         if (guest_hv_clock.version & 1)
1966                 ++guest_hv_clock.version;  /* first time write, random junk */
1967
1968         vcpu->hv_clock.version = guest_hv_clock.version + 1;
1969         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1970                                 &vcpu->hv_clock,
1971                                 sizeof(vcpu->hv_clock.version));
1972
1973         smp_wmb();
1974
1975         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1976         vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1977
1978         if (vcpu->pvclock_set_guest_stopped_request) {
1979                 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1980                 vcpu->pvclock_set_guest_stopped_request = false;
1981         }
1982
1983         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1984
1985         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1986                                 &vcpu->hv_clock,
1987                                 sizeof(vcpu->hv_clock));
1988
1989         smp_wmb();
1990
1991         vcpu->hv_clock.version++;
1992         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1993                                 &vcpu->hv_clock,
1994                                 sizeof(vcpu->hv_clock.version));
1995 }
1996
1997 static int kvm_guest_time_update(struct kvm_vcpu *v)
1998 {
1999         unsigned long flags, tgt_tsc_khz;
2000         struct kvm_vcpu_arch *vcpu = &v->arch;
2001         struct kvm_arch *ka = &v->kvm->arch;
2002         s64 kernel_ns;
2003         u64 tsc_timestamp, host_tsc;
2004         u8 pvclock_flags;
2005         bool use_master_clock;
2006
2007         kernel_ns = 0;
2008         host_tsc = 0;
2009
2010         /*
2011          * If the host uses TSC clock, then passthrough TSC as stable
2012          * to the guest.
2013          */
2014         spin_lock(&ka->pvclock_gtod_sync_lock);
2015         use_master_clock = ka->use_master_clock;
2016         if (use_master_clock) {
2017                 host_tsc = ka->master_cycle_now;
2018                 kernel_ns = ka->master_kernel_ns;
2019         }
2020         spin_unlock(&ka->pvclock_gtod_sync_lock);
2021
2022         /* Keep irq disabled to prevent changes to the clock */
2023         local_irq_save(flags);
2024         tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2025         if (unlikely(tgt_tsc_khz == 0)) {
2026                 local_irq_restore(flags);
2027                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2028                 return 1;
2029         }
2030         if (!use_master_clock) {
2031                 host_tsc = rdtsc();
2032                 kernel_ns = ktime_get_boot_ns();
2033         }
2034
2035         tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2036
2037         /*
2038          * We may have to catch up the TSC to match elapsed wall clock
2039          * time for two reasons, even if kvmclock is used.
2040          *   1) CPU could have been running below the maximum TSC rate
2041          *   2) Broken TSC compensation resets the base at each VCPU
2042          *      entry to avoid unknown leaps of TSC even when running
2043          *      again on the same CPU.  This may cause apparent elapsed
2044          *      time to disappear, and the guest to stand still or run
2045          *      very slowly.
2046          */
2047         if (vcpu->tsc_catchup) {
2048                 u64 tsc = compute_guest_tsc(v, kernel_ns);
2049                 if (tsc > tsc_timestamp) {
2050                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2051                         tsc_timestamp = tsc;
2052                 }
2053         }
2054
2055         local_irq_restore(flags);
2056
2057         /* With all the info we got, fill in the values */
2058
2059         if (kvm_has_tsc_control)
2060                 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2061
2062         if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2063                 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2064                                    &vcpu->hv_clock.tsc_shift,
2065                                    &vcpu->hv_clock.tsc_to_system_mul);
2066                 vcpu->hw_tsc_khz = tgt_tsc_khz;
2067         }
2068
2069         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2070         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2071         vcpu->last_guest_tsc = tsc_timestamp;
2072
2073         /* If the host uses TSC clocksource, then it is stable */
2074         pvclock_flags = 0;
2075         if (use_master_clock)
2076                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2077
2078         vcpu->hv_clock.flags = pvclock_flags;
2079
2080         if (vcpu->pv_time_enabled)
2081                 kvm_setup_pvclock_page(v);
2082         if (v == kvm_get_vcpu(v->kvm, 0))
2083                 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2084         return 0;
2085 }
2086
2087 /*
2088  * kvmclock updates which are isolated to a given vcpu, such as
2089  * vcpu->cpu migration, should not allow system_timestamp from
2090  * the rest of the vcpus to remain static. Otherwise ntp frequency
2091  * correction applies to one vcpu's system_timestamp but not
2092  * the others.
2093  *
2094  * So in those cases, request a kvmclock update for all vcpus.
2095  * We need to rate-limit these requests though, as they can
2096  * considerably slow guests that have a large number of vcpus.
2097  * The time for a remote vcpu to update its kvmclock is bound
2098  * by the delay we use to rate-limit the updates.
2099  */
2100
2101 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2102
2103 static void kvmclock_update_fn(struct work_struct *work)
2104 {
2105         int i;
2106         struct delayed_work *dwork = to_delayed_work(work);
2107         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2108                                            kvmclock_update_work);
2109         struct kvm *kvm = container_of(ka, struct kvm, arch);
2110         struct kvm_vcpu *vcpu;
2111
2112         kvm_for_each_vcpu(i, vcpu, kvm) {
2113                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2114                 kvm_vcpu_kick(vcpu);
2115         }
2116 }
2117
2118 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2119 {
2120         struct kvm *kvm = v->kvm;
2121
2122         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2123         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2124                                         KVMCLOCK_UPDATE_DELAY);
2125 }
2126
2127 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2128
2129 static void kvmclock_sync_fn(struct work_struct *work)
2130 {
2131         struct delayed_work *dwork = to_delayed_work(work);
2132         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2133                                            kvmclock_sync_work);
2134         struct kvm *kvm = container_of(ka, struct kvm, arch);
2135
2136         if (!kvmclock_periodic_sync)
2137                 return;
2138
2139         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2140         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2141                                         KVMCLOCK_SYNC_PERIOD);
2142 }
2143
2144 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2145 {
2146         u64 mcg_cap = vcpu->arch.mcg_cap;
2147         unsigned bank_num = mcg_cap & 0xff;
2148         u32 msr = msr_info->index;
2149         u64 data = msr_info->data;
2150
2151         switch (msr) {
2152         case MSR_IA32_MCG_STATUS:
2153                 vcpu->arch.mcg_status = data;
2154                 break;
2155         case MSR_IA32_MCG_CTL:
2156                 if (!(mcg_cap & MCG_CTL_P))
2157                         return 1;
2158                 if (data != 0 && data != ~(u64)0)
2159                         return -1;
2160                 vcpu->arch.mcg_ctl = data;
2161                 break;
2162         default:
2163                 if (msr >= MSR_IA32_MC0_CTL &&
2164                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2165                         u32 offset = msr - MSR_IA32_MC0_CTL;
2166                         /* only 0 or all 1s can be written to IA32_MCi_CTL
2167                          * some Linux kernels though clear bit 10 in bank 4 to
2168                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2169                          * this to avoid an uncatched #GP in the guest
2170                          */
2171                         if ((offset & 0x3) == 0 &&
2172                             data != 0 && (data | (1 << 10)) != ~(u64)0)
2173                                 return -1;
2174                         if (!msr_info->host_initiated &&
2175                                 (offset & 0x3) == 1 && data != 0)
2176                                 return -1;
2177                         vcpu->arch.mce_banks[offset] = data;
2178                         break;
2179                 }
2180                 return 1;
2181         }
2182         return 0;
2183 }
2184
2185 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2186 {
2187         struct kvm *kvm = vcpu->kvm;
2188         int lm = is_long_mode(vcpu);
2189         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2190                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2191         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2192                 : kvm->arch.xen_hvm_config.blob_size_32;
2193         u32 page_num = data & ~PAGE_MASK;
2194         u64 page_addr = data & PAGE_MASK;
2195         u8 *page;
2196         int r;
2197
2198         r = -E2BIG;
2199         if (page_num >= blob_size)
2200                 goto out;
2201         r = -ENOMEM;
2202         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2203         if (IS_ERR(page)) {
2204                 r = PTR_ERR(page);
2205                 goto out;
2206         }
2207         if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2208                 goto out_free;
2209         r = 0;
2210 out_free:
2211         kfree(page);
2212 out:
2213         return r;
2214 }
2215
2216 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2217 {
2218         gpa_t gpa = data & ~0x3f;
2219
2220         /* Bits 3:5 are reserved, Should be zero */
2221         if (data & 0x38)
2222                 return 1;
2223
2224         vcpu->arch.apf.msr_val = data;
2225
2226         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2227                 kvm_clear_async_pf_completion_queue(vcpu);
2228                 kvm_async_pf_hash_reset(vcpu);
2229                 return 0;
2230         }
2231
2232         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2233                                         sizeof(u32)))
2234                 return 1;
2235
2236         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2237         vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2238         kvm_async_pf_wakeup_all(vcpu);
2239         return 0;
2240 }
2241
2242 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2243 {
2244         vcpu->arch.pv_time_enabled = false;
2245 }
2246
2247 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2248 {
2249         ++vcpu->stat.tlb_flush;
2250         kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2251 }
2252
2253 static void record_steal_time(struct kvm_vcpu *vcpu)
2254 {
2255         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2256                 return;
2257
2258         if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2259                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2260                 return;
2261
2262         /*
2263          * Doing a TLB flush here, on the guest's behalf, can avoid
2264          * expensive IPIs.
2265          */
2266         if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2267                 kvm_vcpu_flush_tlb(vcpu, false);
2268
2269         if (vcpu->arch.st.steal.version & 1)
2270                 vcpu->arch.st.steal.version += 1;  /* first time write, random junk */
2271
2272         vcpu->arch.st.steal.version += 1;
2273
2274         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2275                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2276
2277         smp_wmb();
2278
2279         vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2280                 vcpu->arch.st.last_steal;
2281         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2282
2283         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2284                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2285
2286         smp_wmb();
2287
2288         vcpu->arch.st.steal.version += 1;
2289
2290         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2291                 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2292 }
2293
2294 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2295 {
2296         bool pr = false;
2297         u32 msr = msr_info->index;
2298         u64 data = msr_info->data;
2299
2300         switch (msr) {
2301         case MSR_AMD64_NB_CFG:
2302         case MSR_IA32_UCODE_WRITE:
2303         case MSR_VM_HSAVE_PA:
2304         case MSR_AMD64_PATCH_LOADER:
2305         case MSR_AMD64_BU_CFG2:
2306         case MSR_AMD64_DC_CFG:
2307                 break;
2308
2309         case MSR_IA32_UCODE_REV:
2310                 if (msr_info->host_initiated)
2311                         vcpu->arch.microcode_version = data;
2312                 break;
2313         case MSR_EFER:
2314                 return set_efer(vcpu, data);
2315         case MSR_K7_HWCR:
2316                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2317                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2318                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2319                 data &= ~(u64)0x40000;  /* ignore Mc status write enable */
2320                 if (data != 0) {
2321                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2322                                     data);
2323                         return 1;
2324                 }
2325                 break;
2326         case MSR_FAM10H_MMIO_CONF_BASE:
2327                 if (data != 0) {
2328                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2329                                     "0x%llx\n", data);
2330                         return 1;
2331                 }
2332                 break;
2333         case MSR_IA32_DEBUGCTLMSR:
2334                 if (!data) {
2335                         /* We support the non-activated case already */
2336                         break;
2337                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2338                         /* Values other than LBR and BTF are vendor-specific,
2339                            thus reserved and should throw a #GP */
2340                         return 1;
2341                 }
2342                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2343                             __func__, data);
2344                 break;
2345         case 0x200 ... 0x2ff:
2346                 return kvm_mtrr_set_msr(vcpu, msr, data);
2347         case MSR_IA32_APICBASE:
2348                 return kvm_set_apic_base(vcpu, msr_info);
2349         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2350                 return kvm_x2apic_msr_write(vcpu, msr, data);
2351         case MSR_IA32_TSCDEADLINE:
2352                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2353                 break;
2354         case MSR_IA32_TSC_ADJUST:
2355                 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2356                         if (!msr_info->host_initiated) {
2357                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2358                                 adjust_tsc_offset_guest(vcpu, adj);
2359                         }
2360                         vcpu->arch.ia32_tsc_adjust_msr = data;
2361                 }
2362                 break;
2363         case MSR_IA32_MISC_ENABLE:
2364                 vcpu->arch.ia32_misc_enable_msr = data;
2365                 break;
2366         case MSR_IA32_SMBASE:
2367                 if (!msr_info->host_initiated)
2368                         return 1;
2369                 vcpu->arch.smbase = data;
2370                 break;
2371         case MSR_IA32_TSC:
2372                 kvm_write_tsc(vcpu, msr_info);
2373                 break;
2374         case MSR_SMI_COUNT:
2375                 if (!msr_info->host_initiated)
2376                         return 1;
2377                 vcpu->arch.smi_count = data;
2378                 break;
2379         case MSR_KVM_WALL_CLOCK_NEW:
2380         case MSR_KVM_WALL_CLOCK:
2381                 vcpu->kvm->arch.wall_clock = data;
2382                 kvm_write_wall_clock(vcpu->kvm, data);
2383                 break;
2384         case MSR_KVM_SYSTEM_TIME_NEW:
2385         case MSR_KVM_SYSTEM_TIME: {
2386                 struct kvm_arch *ka = &vcpu->kvm->arch;
2387
2388                 kvmclock_reset(vcpu);
2389
2390                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2391                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2392
2393                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2394                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2395
2396                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2397                 }
2398
2399                 vcpu->arch.time = data;
2400                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2401
2402                 /* we verify if the enable bit is set... */
2403                 if (!(data & 1))
2404                         break;
2405
2406                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2407                      &vcpu->arch.pv_time, data & ~1ULL,
2408                      sizeof(struct pvclock_vcpu_time_info)))
2409                         vcpu->arch.pv_time_enabled = false;
2410                 else
2411                         vcpu->arch.pv_time_enabled = true;
2412
2413                 break;
2414         }
2415         case MSR_KVM_ASYNC_PF_EN:
2416                 if (kvm_pv_enable_async_pf(vcpu, data))
2417                         return 1;
2418                 break;
2419         case MSR_KVM_STEAL_TIME:
2420
2421                 if (unlikely(!sched_info_on()))
2422                         return 1;
2423
2424                 if (data & KVM_STEAL_RESERVED_MASK)
2425                         return 1;
2426
2427                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2428                                                 data & KVM_STEAL_VALID_BITS,
2429                                                 sizeof(struct kvm_steal_time)))
2430                         return 1;
2431
2432                 vcpu->arch.st.msr_val = data;
2433
2434                 if (!(data & KVM_MSR_ENABLED))
2435                         break;
2436
2437                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2438
2439                 break;
2440         case MSR_KVM_PV_EOI_EN:
2441                 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2442                         return 1;
2443                 break;
2444
2445         case MSR_IA32_MCG_CTL:
2446         case MSR_IA32_MCG_STATUS:
2447         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2448                 return set_msr_mce(vcpu, msr_info);
2449
2450         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2451         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2452                 pr = true; /* fall through */
2453         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2454         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2455                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2456                         return kvm_pmu_set_msr(vcpu, msr_info);
2457
2458                 if (pr || data != 0)
2459                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2460                                     "0x%x data 0x%llx\n", msr, data);
2461                 break;
2462         case MSR_K7_CLK_CTL:
2463                 /*
2464                  * Ignore all writes to this no longer documented MSR.
2465                  * Writes are only relevant for old K7 processors,
2466                  * all pre-dating SVM, but a recommended workaround from
2467                  * AMD for these chips. It is possible to specify the
2468                  * affected processor models on the command line, hence
2469                  * the need to ignore the workaround.
2470                  */
2471                 break;
2472         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2473         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2474         case HV_X64_MSR_CRASH_CTL:
2475         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2476         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2477         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2478         case HV_X64_MSR_TSC_EMULATION_STATUS:
2479                 return kvm_hv_set_msr_common(vcpu, msr, data,
2480                                              msr_info->host_initiated);
2481         case MSR_IA32_BBL_CR_CTL3:
2482                 /* Drop writes to this legacy MSR -- see rdmsr
2483                  * counterpart for further detail.
2484                  */
2485                 if (report_ignored_msrs)
2486                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2487                                 msr, data);
2488                 break;
2489         case MSR_AMD64_OSVW_ID_LENGTH:
2490                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2491                         return 1;
2492                 vcpu->arch.osvw.length = data;
2493                 break;
2494         case MSR_AMD64_OSVW_STATUS:
2495                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2496                         return 1;
2497                 vcpu->arch.osvw.status = data;
2498                 break;
2499         case MSR_PLATFORM_INFO:
2500                 if (!msr_info->host_initiated ||
2501                     data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2502                     (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2503                      cpuid_fault_enabled(vcpu)))
2504                         return 1;
2505                 vcpu->arch.msr_platform_info = data;
2506                 break;
2507         case MSR_MISC_FEATURES_ENABLES:
2508                 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2509                     (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2510                      !supports_cpuid_fault(vcpu)))
2511                         return 1;
2512                 vcpu->arch.msr_misc_features_enables = data;
2513                 break;
2514         default:
2515                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2516                         return xen_hvm_config(vcpu, data);
2517                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2518                         return kvm_pmu_set_msr(vcpu, msr_info);
2519                 if (!ignore_msrs) {
2520                         vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2521                                     msr, data);
2522                         return 1;
2523                 } else {
2524                         if (report_ignored_msrs)
2525                                 vcpu_unimpl(vcpu,
2526                                         "ignored wrmsr: 0x%x data 0x%llx\n",
2527                                         msr, data);
2528                         break;
2529                 }
2530         }
2531         return 0;
2532 }
2533 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2534
2535
2536 /*
2537  * Reads an msr value (of 'msr_index') into 'pdata'.
2538  * Returns 0 on success, non-0 otherwise.
2539  * Assumes vcpu_load() was already called.
2540  */
2541 int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2542 {
2543         return kvm_x86_ops->get_msr(vcpu, msr);
2544 }
2545 EXPORT_SYMBOL_GPL(kvm_get_msr);
2546
2547 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2548 {
2549         u64 data;
2550         u64 mcg_cap = vcpu->arch.mcg_cap;
2551         unsigned bank_num = mcg_cap & 0xff;
2552
2553         switch (msr) {
2554         case MSR_IA32_P5_MC_ADDR:
2555         case MSR_IA32_P5_MC_TYPE:
2556                 data = 0;
2557                 break;
2558         case MSR_IA32_MCG_CAP:
2559                 data = vcpu->arch.mcg_cap;
2560                 break;
2561         case MSR_IA32_MCG_CTL:
2562                 if (!(mcg_cap & MCG_CTL_P))
2563                         return 1;
2564                 data = vcpu->arch.mcg_ctl;
2565                 break;
2566         case MSR_IA32_MCG_STATUS:
2567                 data = vcpu->arch.mcg_status;
2568                 break;
2569         default:
2570                 if (msr >= MSR_IA32_MC0_CTL &&
2571                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2572                         u32 offset = msr - MSR_IA32_MC0_CTL;
2573                         data = vcpu->arch.mce_banks[offset];
2574                         break;
2575                 }
2576                 return 1;
2577         }
2578         *pdata = data;
2579         return 0;
2580 }
2581
2582 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2583 {
2584         switch (msr_info->index) {
2585         case MSR_IA32_PLATFORM_ID:
2586         case MSR_IA32_EBL_CR_POWERON:
2587         case MSR_IA32_DEBUGCTLMSR:
2588         case MSR_IA32_LASTBRANCHFROMIP:
2589         case MSR_IA32_LASTBRANCHTOIP:
2590         case MSR_IA32_LASTINTFROMIP:
2591         case MSR_IA32_LASTINTTOIP:
2592         case MSR_K8_SYSCFG:
2593         case MSR_K8_TSEG_ADDR:
2594         case MSR_K8_TSEG_MASK:
2595         case MSR_K7_HWCR:
2596         case MSR_VM_HSAVE_PA:
2597         case MSR_K8_INT_PENDING_MSG:
2598         case MSR_AMD64_NB_CFG:
2599         case MSR_FAM10H_MMIO_CONF_BASE:
2600         case MSR_AMD64_BU_CFG2:
2601         case MSR_IA32_PERF_CTL:
2602         case MSR_AMD64_DC_CFG:
2603                 msr_info->data = 0;
2604                 break;
2605         case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
2606         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2607         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2608         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2609         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2610                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2611                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2612                 msr_info->data = 0;
2613                 break;
2614         case MSR_IA32_UCODE_REV:
2615                 msr_info->data = vcpu->arch.microcode_version;
2616                 break;
2617         case MSR_IA32_TSC:
2618                 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2619                 break;
2620         case MSR_MTRRcap:
2621         case 0x200 ... 0x2ff:
2622                 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
2623         case 0xcd: /* fsb frequency */
2624                 msr_info->data = 3;
2625                 break;
2626                 /*
2627                  * MSR_EBC_FREQUENCY_ID
2628                  * Conservative value valid for even the basic CPU models.
2629                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2630                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2631                  * and 266MHz for model 3, or 4. Set Core Clock
2632                  * Frequency to System Bus Frequency Ratio to 1 (bits
2633                  * 31:24) even though these are only valid for CPU
2634                  * models > 2, however guests may end up dividing or
2635                  * multiplying by zero otherwise.
2636                  */
2637         case MSR_EBC_FREQUENCY_ID:
2638                 msr_info->data = 1 << 24;
2639                 break;
2640         case MSR_IA32_APICBASE:
2641                 msr_info->data = kvm_get_apic_base(vcpu);
2642                 break;
2643         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2644                 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
2645                 break;
2646         case MSR_IA32_TSCDEADLINE:
2647                 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
2648                 break;
2649         case MSR_IA32_TSC_ADJUST:
2650                 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2651                 break;
2652         case MSR_IA32_MISC_ENABLE:
2653                 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
2654                 break;
2655         case MSR_IA32_SMBASE:
2656                 if (!msr_info->host_initiated)
2657                         return 1;
2658                 msr_info->data = vcpu->arch.smbase;
2659                 break;
2660         case MSR_SMI_COUNT:
2661                 msr_info->data = vcpu->arch.smi_count;
2662                 break;
2663         case MSR_IA32_PERF_STATUS:
2664                 /* TSC increment by tick */
2665                 msr_info->data = 1000ULL;
2666                 /* CPU multiplier */
2667                 msr_info->data |= (((uint64_t)4ULL) << 40);
2668                 break;
2669         case MSR_EFER:
2670                 msr_info->data = vcpu->arch.efer;
2671                 break;
2672         case MSR_KVM_WALL_CLOCK:
2673         case MSR_KVM_WALL_CLOCK_NEW:
2674                 msr_info->data = vcpu->kvm->arch.wall_clock;
2675                 break;
2676         case MSR_KVM_SYSTEM_TIME:
2677         case MSR_KVM_SYSTEM_TIME_NEW:
2678                 msr_info->data = vcpu->arch.time;
2679                 break;
2680         case MSR_KVM_ASYNC_PF_EN:
2681                 msr_info->data = vcpu->arch.apf.msr_val;
2682                 break;
2683         case MSR_KVM_STEAL_TIME:
2684                 msr_info->data = vcpu->arch.st.msr_val;
2685                 break;
2686         case MSR_KVM_PV_EOI_EN:
2687                 msr_info->data = vcpu->arch.pv_eoi.msr_val;
2688                 break;
2689         case MSR_IA32_P5_MC_ADDR:
2690         case MSR_IA32_P5_MC_TYPE:
2691         case MSR_IA32_MCG_CAP:
2692         case MSR_IA32_MCG_CTL:
2693         case MSR_IA32_MCG_STATUS:
2694         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2695                 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
2696         case MSR_K7_CLK_CTL:
2697                 /*
2698                  * Provide expected ramp-up count for K7. All other
2699                  * are set to zero, indicating minimum divisors for
2700                  * every field.
2701                  *
2702                  * This prevents guest kernels on AMD host with CPU
2703                  * type 6, model 8 and higher from exploding due to
2704                  * the rdmsr failing.
2705                  */
2706                 msr_info->data = 0x20000000;
2707                 break;
2708         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2709         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2710         case HV_X64_MSR_CRASH_CTL:
2711         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2712         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2713         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2714         case HV_X64_MSR_TSC_EMULATION_STATUS:
2715                 return kvm_hv_get_msr_common(vcpu,
2716                                              msr_info->index, &msr_info->data);
2717                 break;
2718         case MSR_IA32_BBL_CR_CTL3:
2719                 /* This legacy MSR exists but isn't fully documented in current
2720                  * silicon.  It is however accessed by winxp in very narrow
2721                  * scenarios where it sets bit #19, itself documented as
2722                  * a "reserved" bit.  Best effort attempt to source coherent
2723                  * read data here should the balance of the register be
2724                  * interpreted by the guest:
2725                  *
2726                  * L2 cache control register 3: 64GB range, 256KB size,
2727                  * enabled, latency 0x1, configured
2728                  */
2729                 msr_info->data = 0xbe702111;
2730                 break;
2731         case MSR_AMD64_OSVW_ID_LENGTH:
2732                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2733                         return 1;
2734                 msr_info->data = vcpu->arch.osvw.length;
2735                 break;
2736         case MSR_AMD64_OSVW_STATUS:
2737                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2738                         return 1;
2739                 msr_info->data = vcpu->arch.osvw.status;
2740                 break;
2741         case MSR_PLATFORM_INFO:
2742                 msr_info->data = vcpu->arch.msr_platform_info;
2743                 break;
2744         case MSR_MISC_FEATURES_ENABLES:
2745                 msr_info->data = vcpu->arch.msr_misc_features_enables;
2746                 break;
2747         default:
2748                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
2749                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2750                 if (!ignore_msrs) {
2751                         vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2752                                                msr_info->index);
2753                         return 1;
2754                 } else {
2755                         if (report_ignored_msrs)
2756                                 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2757                                         msr_info->index);
2758                         msr_info->data = 0;
2759                 }
2760                 break;
2761         }
2762         return 0;
2763 }
2764 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2765
2766 /*
2767  * Read or write a bunch of msrs. All parameters are kernel addresses.
2768  *
2769  * @return number of msrs set successfully.
2770  */
2771 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2772                     struct kvm_msr_entry *entries,
2773                     int (*do_msr)(struct kvm_vcpu *vcpu,
2774                                   unsigned index, u64 *data))
2775 {
2776         int i;
2777
2778         for (i = 0; i < msrs->nmsrs; ++i)
2779                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2780                         break;
2781
2782         return i;
2783 }
2784
2785 /*
2786  * Read or write a bunch of msrs. Parameters are user addresses.
2787  *
2788  * @return number of msrs set successfully.
2789  */
2790 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2791                   int (*do_msr)(struct kvm_vcpu *vcpu,
2792                                 unsigned index, u64 *data),
2793                   int writeback)
2794 {
2795         struct kvm_msrs msrs;
2796         struct kvm_msr_entry *entries;
2797         int r, n;
2798         unsigned size;
2799
2800         r = -EFAULT;
2801         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2802                 goto out;
2803
2804         r = -E2BIG;
2805         if (msrs.nmsrs >= MAX_IO_MSRS)
2806                 goto out;
2807
2808         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2809         entries = memdup_user(user_msrs->entries, size);
2810         if (IS_ERR(entries)) {
2811                 r = PTR_ERR(entries);
2812                 goto out;
2813         }
2814
2815         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2816         if (r < 0)
2817                 goto out_free;
2818
2819         r = -EFAULT;
2820         if (writeback && copy_to_user(user_msrs->entries, entries, size))
2821                 goto out_free;
2822
2823         r = n;
2824
2825 out_free:
2826         kfree(entries);
2827 out:
2828         return r;
2829 }
2830
2831 static inline bool kvm_can_mwait_in_guest(void)
2832 {
2833         return boot_cpu_has(X86_FEATURE_MWAIT) &&
2834                 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2835                 boot_cpu_has(X86_FEATURE_ARAT);
2836 }
2837
2838 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
2839 {
2840         int r = 0;
2841
2842         switch (ext) {
2843         case KVM_CAP_IRQCHIP:
2844         case KVM_CAP_HLT:
2845         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2846         case KVM_CAP_SET_TSS_ADDR:
2847         case KVM_CAP_EXT_CPUID:
2848         case KVM_CAP_EXT_EMUL_CPUID:
2849         case KVM_CAP_CLOCKSOURCE:
2850         case KVM_CAP_PIT:
2851         case KVM_CAP_NOP_IO_DELAY:
2852         case KVM_CAP_MP_STATE:
2853         case KVM_CAP_SYNC_MMU:
2854         case KVM_CAP_USER_NMI:
2855         case KVM_CAP_REINJECT_CONTROL:
2856         case KVM_CAP_IRQ_INJECT_STATUS:
2857         case KVM_CAP_IOEVENTFD:
2858         case KVM_CAP_IOEVENTFD_NO_LENGTH:
2859         case KVM_CAP_PIT2:
2860         case KVM_CAP_PIT_STATE2:
2861         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2862         case KVM_CAP_XEN_HVM:
2863         case KVM_CAP_VCPU_EVENTS:
2864         case KVM_CAP_HYPERV:
2865         case KVM_CAP_HYPERV_VAPIC:
2866         case KVM_CAP_HYPERV_SPIN:
2867         case KVM_CAP_HYPERV_SYNIC:
2868         case KVM_CAP_HYPERV_SYNIC2:
2869         case KVM_CAP_HYPERV_VP_INDEX:
2870         case KVM_CAP_HYPERV_EVENTFD:
2871         case KVM_CAP_PCI_SEGMENT:
2872         case KVM_CAP_DEBUGREGS:
2873         case KVM_CAP_X86_ROBUST_SINGLESTEP:
2874         case KVM_CAP_XSAVE:
2875         case KVM_CAP_ASYNC_PF:
2876         case KVM_CAP_GET_TSC_KHZ:
2877         case KVM_CAP_KVMCLOCK_CTRL:
2878         case KVM_CAP_READONLY_MEM:
2879         case KVM_CAP_HYPERV_TIME:
2880         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2881         case KVM_CAP_TSC_DEADLINE_TIMER:
2882         case KVM_CAP_ENABLE_CAP_VM:
2883         case KVM_CAP_DISABLE_QUIRKS:
2884         case KVM_CAP_SET_BOOT_CPU_ID:
2885         case KVM_CAP_SPLIT_IRQCHIP:
2886         case KVM_CAP_IMMEDIATE_EXIT:
2887         case KVM_CAP_GET_MSR_FEATURES:
2888                 r = 1;
2889                 break;
2890         case KVM_CAP_SYNC_REGS:
2891                 r = KVM_SYNC_X86_VALID_FIELDS;
2892                 break;
2893         case KVM_CAP_ADJUST_CLOCK:
2894                 r = KVM_CLOCK_TSC_STABLE;
2895                 break;
2896         case KVM_CAP_X86_DISABLE_EXITS:
2897                 r |=  KVM_X86_DISABLE_EXITS_HTL | KVM_X86_DISABLE_EXITS_PAUSE;
2898                 if(kvm_can_mwait_in_guest())
2899                         r |= KVM_X86_DISABLE_EXITS_MWAIT;
2900                 break;
2901         case KVM_CAP_X86_SMM:
2902                 /* SMBASE is usually relocated above 1M on modern chipsets,
2903                  * and SMM handlers might indeed rely on 4G segment limits,
2904                  * so do not report SMM to be available if real mode is
2905                  * emulated via vm86 mode.  Still, do not go to great lengths
2906                  * to avoid userspace's usage of the feature, because it is a
2907                  * fringe case that is not enabled except via specific settings
2908                  * of the module parameters.
2909                  */
2910                 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
2911                 break;
2912         case KVM_CAP_VAPIC:
2913                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2914                 break;
2915         case KVM_CAP_NR_VCPUS:
2916                 r = KVM_SOFT_MAX_VCPUS;
2917                 break;
2918         case KVM_CAP_MAX_VCPUS:
2919                 r = KVM_MAX_VCPUS;
2920                 break;
2921         case KVM_CAP_NR_MEMSLOTS:
2922                 r = KVM_USER_MEM_SLOTS;
2923                 break;
2924         case KVM_CAP_PV_MMU:    /* obsolete */
2925                 r = 0;
2926                 break;
2927         case KVM_CAP_MCE:
2928                 r = KVM_MAX_MCE_BANKS;
2929                 break;
2930         case KVM_CAP_XCRS:
2931                 r = boot_cpu_has(X86_FEATURE_XSAVE);
2932                 break;
2933         case KVM_CAP_TSC_CONTROL:
2934                 r = kvm_has_tsc_control;
2935                 break;
2936         case KVM_CAP_X2APIC_API:
2937                 r = KVM_X2APIC_API_VALID_FLAGS;
2938                 break;
2939         default:
2940                 break;
2941         }
2942         return r;
2943
2944 }
2945
2946 long kvm_arch_dev_ioctl(struct file *filp,
2947                         unsigned int ioctl, unsigned long arg)
2948 {
2949         void __user *argp = (void __user *)arg;
2950         long r;
2951
2952         switch (ioctl) {
2953         case KVM_GET_MSR_INDEX_LIST: {
2954                 struct kvm_msr_list __user *user_msr_list = argp;
2955                 struct kvm_msr_list msr_list;
2956                 unsigned n;
2957
2958                 r = -EFAULT;
2959                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2960                         goto out;
2961                 n = msr_list.nmsrs;
2962                 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
2963                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2964                         goto out;
2965                 r = -E2BIG;
2966                 if (n < msr_list.nmsrs)
2967                         goto out;
2968                 r = -EFAULT;
2969                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2970                                  num_msrs_to_save * sizeof(u32)))
2971                         goto out;
2972                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2973                                  &emulated_msrs,
2974                                  num_emulated_msrs * sizeof(u32)))
2975                         goto out;
2976                 r = 0;
2977                 break;
2978         }
2979         case KVM_GET_SUPPORTED_CPUID:
2980         case KVM_GET_EMULATED_CPUID: {
2981                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2982                 struct kvm_cpuid2 cpuid;
2983
2984                 r = -EFAULT;
2985                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2986                         goto out;
2987
2988                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2989                                             ioctl);
2990                 if (r)
2991                         goto out;
2992
2993                 r = -EFAULT;
2994                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2995                         goto out;
2996                 r = 0;
2997                 break;
2998         }
2999         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
3000                 r = -EFAULT;
3001                 if (copy_to_user(argp, &kvm_mce_cap_supported,
3002                                  sizeof(kvm_mce_cap_supported)))
3003                         goto out;
3004                 r = 0;
3005                 break;
3006         case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3007                 struct kvm_msr_list __user *user_msr_list = argp;
3008                 struct kvm_msr_list msr_list;
3009                 unsigned int n;
3010
3011                 r = -EFAULT;
3012                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3013                         goto out;
3014                 n = msr_list.nmsrs;
3015                 msr_list.nmsrs = num_msr_based_features;
3016                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3017                         goto out;
3018                 r = -E2BIG;
3019                 if (n < msr_list.nmsrs)
3020                         goto out;
3021                 r = -EFAULT;
3022                 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3023                                  num_msr_based_features * sizeof(u32)))
3024                         goto out;
3025                 r = 0;
3026                 break;
3027         }
3028         case KVM_GET_MSRS:
3029                 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3030                 break;
3031         }
3032         default:
3033                 r = -EINVAL;
3034         }
3035 out:
3036         return r;
3037 }
3038
3039 static void wbinvd_ipi(void *garbage)
3040 {
3041         wbinvd();
3042 }
3043
3044 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3045 {
3046         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3047 }
3048
3049 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3050 {
3051         /* Address WBINVD may be executed by guest */
3052         if (need_emulate_wbinvd(vcpu)) {
3053                 if (kvm_x86_ops->has_wbinvd_exit())
3054                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3055                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3056                         smp_call_function_single(vcpu->cpu,
3057                                         wbinvd_ipi, NULL, 1);
3058         }
3059
3060         kvm_x86_ops->vcpu_load(vcpu, cpu);
3061
3062         /* Apply any externally detected TSC adjustments (due to suspend) */
3063         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3064                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3065                 vcpu->arch.tsc_offset_adjustment = 0;
3066                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3067         }
3068
3069         if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3070                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3071                                 rdtsc() - vcpu->arch.last_host_tsc;
3072                 if (tsc_delta < 0)
3073                         mark_tsc_unstable("KVM discovered backwards TSC");
3074
3075                 if (kvm_check_tsc_unstable()) {
3076                         u64 offset = kvm_compute_tsc_offset(vcpu,
3077                                                 vcpu->arch.last_guest_tsc);
3078                         kvm_vcpu_write_tsc_offset(vcpu, offset);
3079                         vcpu->arch.tsc_catchup = 1;
3080                 }
3081
3082                 if (kvm_lapic_hv_timer_in_use(vcpu))
3083                         kvm_lapic_restart_hv_timer(vcpu);
3084
3085                 /*
3086                  * On a host with synchronized TSC, there is no need to update
3087                  * kvmclock on vcpu->cpu migration
3088                  */
3089                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3090                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3091                 if (vcpu->cpu != cpu)
3092                         kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3093                 vcpu->cpu = cpu;
3094         }
3095
3096         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3097 }
3098
3099 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3100 {
3101         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3102                 return;
3103
3104         vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
3105
3106         kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
3107                         &vcpu->arch.st.steal.preempted,
3108                         offsetof(struct kvm_steal_time, preempted),
3109                         sizeof(vcpu->arch.st.steal.preempted));
3110 }
3111
3112 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3113 {
3114         int idx;
3115
3116         if (vcpu->preempted)
3117                 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3118
3119         /*
3120          * Disable page faults because we're in atomic context here.
3121          * kvm_write_guest_offset_cached() would call might_fault()
3122          * that relies on pagefault_disable() to tell if there's a
3123          * bug. NOTE: the write to guest memory may not go through if
3124          * during postcopy live migration or if there's heavy guest
3125          * paging.
3126          */
3127         pagefault_disable();
3128         /*
3129          * kvm_memslots() will be called by
3130          * kvm_write_guest_offset_cached() so take the srcu lock.
3131          */
3132         idx = srcu_read_lock(&vcpu->kvm->srcu);
3133         kvm_steal_time_set_preempted(vcpu);
3134         srcu_read_unlock(&vcpu->kvm->srcu, idx);
3135         pagefault_enable();
3136         kvm_x86_ops->vcpu_put(vcpu);
3137         vcpu->arch.last_host_tsc = rdtsc();
3138         /*
3139          * If userspace has set any breakpoints or watchpoints, dr6 is restored
3140          * on every vmexit, but if not, we might have a stale dr6 from the
3141          * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3142          */
3143         set_debugreg(0, 6);
3144 }
3145
3146 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3147                                     struct kvm_lapic_state *s)
3148 {
3149         if (vcpu->arch.apicv_active)
3150                 kvm_x86_ops->sync_pir_to_irr(vcpu);
3151
3152         return kvm_apic_get_state(vcpu, s);
3153 }
3154
3155 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3156                                     struct kvm_lapic_state *s)
3157 {
3158         int r;
3159
3160         r = kvm_apic_set_state(vcpu, s);
3161         if (r)
3162                 return r;
3163         update_cr8_intercept(vcpu);
3164
3165         return 0;
3166 }
3167
3168 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3169 {
3170         return (!lapic_in_kernel(vcpu) ||
3171                 kvm_apic_accept_pic_intr(vcpu));
3172 }
3173
3174 /*
3175  * if userspace requested an interrupt window, check that the
3176  * interrupt window is open.
3177  *
3178  * No need to exit to userspace if we already have an interrupt queued.
3179  */
3180 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3181 {
3182         return kvm_arch_interrupt_allowed(vcpu) &&
3183                 !kvm_cpu_has_interrupt(vcpu) &&
3184                 !kvm_event_needs_reinjection(vcpu) &&
3185                 kvm_cpu_accept_dm_intr(vcpu);
3186 }
3187
3188 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3189                                     struct kvm_interrupt *irq)
3190 {
3191         if (irq->irq >= KVM_NR_INTERRUPTS)
3192                 return -EINVAL;
3193
3194         if (!irqchip_in_kernel(vcpu->kvm)) {
3195                 kvm_queue_interrupt(vcpu, irq->irq, false);
3196                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3197                 return 0;
3198         }
3199
3200         /*
3201          * With in-kernel LAPIC, we only use this to inject EXTINT, so
3202          * fail for in-kernel 8259.
3203          */
3204         if (pic_in_kernel(vcpu->kvm))
3205                 return -ENXIO;
3206
3207         if (vcpu->arch.pending_external_vector != -1)
3208                 return -EEXIST;
3209
3210         vcpu->arch.pending_external_vector = irq->irq;
3211         kvm_make_request(KVM_REQ_EVENT, vcpu);
3212         return 0;
3213 }
3214
3215 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3216 {
3217         kvm_inject_nmi(vcpu);
3218
3219         return 0;
3220 }
3221
3222 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3223 {
3224         kvm_make_request(KVM_REQ_SMI, vcpu);
3225
3226         return 0;
3227 }
3228
3229 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3230                                            struct kvm_tpr_access_ctl *tac)
3231 {
3232         if (tac->flags)
3233                 return -EINVAL;
3234         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3235         return 0;
3236 }
3237
3238 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3239                                         u64 mcg_cap)
3240 {
3241         int r;
3242         unsigned bank_num = mcg_cap & 0xff, bank;
3243
3244         r = -EINVAL;
3245         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3246                 goto out;
3247         if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3248                 goto out;
3249         r = 0;
3250         vcpu->arch.mcg_cap = mcg_cap;
3251         /* Init IA32_MCG_CTL to all 1s */
3252         if (mcg_cap & MCG_CTL_P)
3253                 vcpu->arch.mcg_ctl = ~(u64)0;
3254         /* Init IA32_MCi_CTL to all 1s */
3255         for (bank = 0; bank < bank_num; bank++)
3256                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3257
3258         if (kvm_x86_ops->setup_mce)
3259                 kvm_x86_ops->setup_mce(vcpu);
3260 out:
3261         return r;
3262 }
3263
3264 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3265                                       struct kvm_x86_mce *mce)
3266 {
3267         u64 mcg_cap = vcpu->arch.mcg_cap;
3268         unsigned bank_num = mcg_cap & 0xff;
3269         u64 *banks = vcpu->arch.mce_banks;
3270
3271         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3272                 return -EINVAL;
3273         /*
3274          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3275          * reporting is disabled
3276          */
3277         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3278             vcpu->arch.mcg_ctl != ~(u64)0)
3279                 return 0;
3280         banks += 4 * mce->bank;
3281         /*
3282          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3283          * reporting is disabled for the bank
3284          */
3285         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3286                 return 0;
3287         if (mce->status & MCI_STATUS_UC) {
3288                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3289                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3290                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3291                         return 0;
3292                 }
3293                 if (banks[1] & MCI_STATUS_VAL)
3294                         mce->status |= MCI_STATUS_OVER;
3295                 banks[2] = mce->addr;
3296                 banks[3] = mce->misc;
3297                 vcpu->arch.mcg_status = mce->mcg_status;
3298                 banks[1] = mce->status;
3299                 kvm_queue_exception(vcpu, MC_VECTOR);
3300         } else if (!(banks[1] & MCI_STATUS_VAL)
3301                    || !(banks[1] & MCI_STATUS_UC)) {
3302                 if (banks[1] & MCI_STATUS_VAL)
3303                         mce->status |= MCI_STATUS_OVER;
3304                 banks[2] = mce->addr;
3305                 banks[3] = mce->misc;
3306                 banks[1] = mce->status;
3307         } else
3308                 banks[1] |= MCI_STATUS_OVER;
3309         return 0;
3310 }
3311
3312 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3313                                                struct kvm_vcpu_events *events)
3314 {
3315         process_nmi(vcpu);
3316         /*
3317          * FIXME: pass injected and pending separately.  This is only
3318          * needed for nested virtualization, whose state cannot be
3319          * migrated yet.  For now we can combine them.
3320          */
3321         events->exception.injected =
3322                 (vcpu->arch.exception.pending ||
3323                  vcpu->arch.exception.injected) &&
3324                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3325         events->exception.nr = vcpu->arch.exception.nr;
3326         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3327         events->exception.pad = 0;