arch/x86/kvm/vmx/vmx.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __KVM_X86_VMX_H
   3 #define __KVM_X86_VMX_H
   4
   5 #include <linux/kvm_host.h>
   6
   7 #include <asm/kvm.h>
   8 #include <asm/intel_pt.h>
   9
  10 #include "capabilities.h"
  11 #include "ops.h"
  12 #include "vmcs.h"
  13
  14 extern const u32 vmx_msr_index[];
  15 extern u64 host_efer;
  16
  17 #define MSR_TYPE_R      1
  18 #define MSR_TYPE_W      2
  19 #define MSR_TYPE_RW     3
  20
  21 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
  22
  23 #define NR_AUTOLOAD_MSRS 8
  24
  25 struct vmx_msrs {
  26         unsigned int            nr;
  27         struct vmx_msr_entry    val[NR_AUTOLOAD_MSRS];
  28 };
  29
  30 struct shared_msr_entry {
  31         unsigned index;
  32         u64 data;
  33         u64 mask;
  34 };
  35
  36 enum segment_cache_field {
  37         SEG_FIELD_SEL = 0,
  38         SEG_FIELD_BASE = 1,
  39         SEG_FIELD_LIMIT = 2,
  40         SEG_FIELD_AR = 3,
  41
  42         SEG_FIELD_NR = 4
  43 };
  44
  45 /* Posted-Interrupt Descriptor */
  46 struct pi_desc {
  47         u32 pir[8];     /* Posted interrupt requested */
  48         union {
  49                 struct {
  50                                 /* bit 256 - Outstanding Notification */
  51                         u16     on      : 1,
  52                                 /* bit 257 - Suppress Notification */
  53                                 sn      : 1,
  54                                 /* bit 271:258 - Reserved */
  55                                 rsvd_1  : 14;
  56                                 /* bit 279:272 - Notification Vector */
  57                         u8      nv;
  58                                 /* bit 287:280 - Reserved */
  59                         u8      rsvd_2;
  60                                 /* bit 319:288 - Notification Destination */
  61                         u32     ndst;
  62                 };
  63                 u64 control;
  64         };
  65         u32 rsvd[6];
  66 } __aligned(64);
  67
  68 #define RTIT_ADDR_RANGE         4
  69
  70 struct pt_ctx {
  71         u64 ctl;
  72         u64 status;
  73         u64 output_base;
  74         u64 output_mask;
  75         u64 cr3_match;
  76         u64 addr_a[RTIT_ADDR_RANGE];
  77         u64 addr_b[RTIT_ADDR_RANGE];
  78 };
  79
  80 struct pt_desc {
  81         u64 ctl_bitmask;
  82         u32 addr_range;
  83         u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
  84         struct pt_ctx host;
  85         struct pt_ctx guest;
  86 };
  87
  88 /*
  89  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
  90  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
  91  */
  92 struct nested_vmx {
  93         /* Has the level1 guest done vmxon? */
  94         bool vmxon;
  95         gpa_t vmxon_ptr;
  96         bool pml_full;
  97
  98         /* The guest-physical address of the current VMCS L1 keeps for L2 */
  99         gpa_t current_vmptr;
 100         /*
 101          * Cache of the guest's VMCS, existing outside of guest memory.
 102          * Loaded from guest memory during VMPTRLD. Flushed to guest
 103          * memory during VMCLEAR and VMPTRLD.
 104          */
 105         struct vmcs12 *cached_vmcs12;
 106         /*
 107          * Cache of the guest's shadow VMCS, existing outside of guest
 108          * memory. Loaded from guest memory during VM entry. Flushed
 109          * to guest memory during VM exit.
 110          */
 111         struct vmcs12 *cached_shadow_vmcs12;
 112         /*
 113          * Indicates if the shadow vmcs or enlightened vmcs must be updated
 114          * with the data held by struct vmcs12.
 115          */
 116         bool need_vmcs12_sync;
 117         bool dirty_vmcs12;
 118
 119         /*
 120          * vmcs02 has been initialized, i.e. state that is constant for
 121          * vmcs02 has been written to the backing VMCS.  Initialization
 122          * is delayed until L1 actually attempts to run a nested VM.
 123          */
 124         bool vmcs02_initialized;
 125
 126         bool change_vmcs01_virtual_apic_mode;
 127
 128         /*
 129          * Enlightened VMCS has been enabled. It does not mean that L1 has to
 130          * use it. However, VMX features available to L1 will be limited based
 131          * on what the enlightened VMCS supports.
 132          */
 133         bool enlightened_vmcs_enabled;
 134
 135         /* L2 must run next, and mustn't decide to exit to L1. */
 136         bool nested_run_pending;
 137
 138         struct loaded_vmcs vmcs02;
 139
 140         /*
 141          * Guest pages referred to in the vmcs02 with host-physical
 142          * pointers, so we must keep them pinned while L2 runs.
 143          */
 144         struct page *apic_access_page;
 145         struct page *virtual_apic_page;
 146         struct page *pi_desc_page;
 147         struct pi_desc *pi_desc;
 148         bool pi_pending;
 149         u16 posted_intr_nv;
 150
 151         struct hrtimer preemption_timer;
 152         bool preemption_timer_expired;
 153
 154         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 155         u64 vmcs01_debugctl;
 156         u64 vmcs01_guest_bndcfgs;
 157
 158         u16 vpid02;
 159         u16 last_vpid;
 160
 161         struct nested_vmx_msrs msrs;
 162
 163         /* SMM related state */
 164         struct {
 165                 /* in VMX operation on SMM entry? */
 166                 bool vmxon;
 167                 /* in guest mode on SMM entry? */
 168                 bool guest_mode;
 169         } smm;
 170
 171         gpa_t hv_evmcs_vmptr;
 172         struct page *hv_evmcs_page;
 173         struct hv_enlightened_vmcs *hv_evmcs;
 174 };
 175
 176 struct vcpu_vmx {
 177         struct kvm_vcpu       vcpu;
 178         unsigned long         host_rsp;
 179         u8                    fail;
 180         u8                    msr_bitmap_mode;
 181         u32                   exit_intr_info;
 182         u32                   idt_vectoring_info;
 183         ulong                 rflags;
 184         struct shared_msr_entry *guest_msrs;
 185         int                   nmsrs;
 186         int                   save_nmsrs;
 187         bool                  guest_msrs_dirty;
 188         unsigned long         host_idt_base;
 189 #ifdef CONFIG_X86_64
 190         u64                   msr_host_kernel_gs_base;
 191         u64                   msr_guest_kernel_gs_base;
 192 #endif
 193
 194         u64                   arch_capabilities;
 195         u64                   spec_ctrl;
 196
 197         u32 vm_entry_controls_shadow;
 198         u32 vm_exit_controls_shadow;
 199         u32 secondary_exec_control;
 200
 201         /*
 202          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 203          * non-nested (L1) guest, it always points to vmcs01. For a nested
 204          * guest (L2), it points to a different VMCS.  loaded_cpu_state points
 205          * to the VMCS whose state is loaded into the CPU registers that only
 206          * need to be switched when transitioning to/from the kernel; a NULL
 207          * value indicates that host state is loaded.
 208          */
 209         struct loaded_vmcs    vmcs01;
 210         struct loaded_vmcs   *loaded_vmcs;
 211         struct loaded_vmcs   *loaded_cpu_state;
 212         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 213         struct msr_autoload {
 214                 struct vmx_msrs guest;
 215                 struct vmx_msrs host;
 216         } msr_autoload;
 217
 218         struct {
 219                 int vm86_active;
 220                 ulong save_rflags;
 221                 struct kvm_segment segs[8];
 222         } rmode;
 223         struct {
 224                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 225                 struct kvm_save_segment {
 226                         u16 selector;
 227                         unsigned long base;
 228                         u32 limit;
 229                         u32 ar;
 230                 } seg[8];
 231         } segment_cache;
 232         int vpid;
 233         bool emulation_required;
 234
 235         u32 exit_reason;
 236
 237         /* Posted interrupt descriptor */
 238         struct pi_desc pi_desc;
 239
 240         /* Support for a guest hypervisor (nested VMX) */
 241         struct nested_vmx nested;
 242
 243         /* Dynamic PLE window. */
 244         int ple_window;
 245         bool ple_window_dirty;
 246
 247         bool req_immediate_exit;
 248
 249         /* Support for PML */
 250 #define PML_ENTITY_NUM          512
 251         struct page *pml_pg;
 252
 253         /* apic deadline value in host tsc */
 254         u64 hv_deadline_tsc;
 255
 256         u64 current_tsc_ratio;
 257
 258         u32 host_pkru;
 259
 260         unsigned long host_debugctlmsr;
 261
 262         /*
 263          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 264          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 265          * in msr_ia32_feature_control_valid_bits.
 266          */
 267         u64 msr_ia32_feature_control;
 268         u64 msr_ia32_feature_control_valid_bits;
 269         u64 ept_pointer;
 270
 271         struct pt_desc pt_desc;
 272 };
 273
 274 enum ept_pointers_status {
 275         EPT_POINTERS_CHECK = 0,
 276         EPT_POINTERS_MATCH = 1,
 277         EPT_POINTERS_MISMATCH = 2
 278 };
 279
 280 struct kvm_vmx {
 281         struct kvm kvm;
 282
 283         unsigned int tss_addr;
 284         bool ept_identity_pagetable_done;
 285         gpa_t ept_identity_map_addr;
 286
 287         enum ept_pointers_status ept_pointers_match;
 288         spinlock_t ept_pointer_lock;
 289 };
 290
 291 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
 292 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 293 void vmx_vcpu_put(struct kvm_vcpu *vcpu);
 294 int allocate_vpid(void);
 295 void free_vpid(int vpid);
 296 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
 297 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
 298 int vmx_get_cpl(struct kvm_vcpu *vcpu);
 299 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
 300 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 301 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
 302 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
 303 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
 304 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 305 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 306 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
 307 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
 308 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 309 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 310 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 311 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 312 void update_exception_bitmap(struct kvm_vcpu *vcpu);
 313 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
 314 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 315 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 316 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
 317 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr);
 318 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);
 319
 320 #define POSTED_INTR_ON  0
 321 #define POSTED_INTR_SN  1
 322
 323 static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
 324 {
 325         return test_and_set_bit(POSTED_INTR_ON,
 326                         (unsigned long *)&pi_desc->control);
 327 }
 328
 329 static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 330 {
 331         return test_and_clear_bit(POSTED_INTR_ON,
 332                         (unsigned long *)&pi_desc->control);
 333 }
 334
 335 static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 336 {
 337         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 338 }
 339
 340 static inline void pi_set_sn(struct pi_desc *pi_desc)
 341 {
 342         return set_bit(POSTED_INTR_SN,
 343                         (unsigned long *)&pi_desc->control);
 344 }
 345
 346 static inline void pi_set_on(struct pi_desc *pi_desc)
 347 {
 348         set_bit(POSTED_INTR_ON,
 349                 (unsigned long *)&pi_desc->control);
 350 }
 351
 352 static inline void pi_clear_on(struct pi_desc *pi_desc)
 353 {
 354         clear_bit(POSTED_INTR_ON,
 355                 (unsigned long *)&pi_desc->control);
 356 }
 357
 358 static inline int pi_test_on(struct pi_desc *pi_desc)
 359 {
 360         return test_bit(POSTED_INTR_ON,
 361                         (unsigned long *)&pi_desc->control);
 362 }
 363
 364 static inline int pi_test_sn(struct pi_desc *pi_desc)
 365 {
 366         return test_bit(POSTED_INTR_SN,
 367                         (unsigned long *)&pi_desc->control);
 368 }
 369
 370 static inline u8 vmx_get_rvi(void)
 371 {
 372         return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
 373 }
 374
 375 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
 376 {
 377         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
 378 }
 379
 380 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
 381 {
 382         vmcs_write32(VM_ENTRY_CONTROLS, val);
 383         vmx->vm_entry_controls_shadow = val;
 384 }
 385
 386 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
 387 {
 388         if (vmx->vm_entry_controls_shadow != val)
 389                 vm_entry_controls_init(vmx, val);
 390 }
 391
 392 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
 393 {
 394         return vmx->vm_entry_controls_shadow;
 395 }
 396
 397 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
 398 {
 399         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
 400 }
 401
 402 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
 403 {
 404         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
 405 }
 406
 407 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
 408 {
 409         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
 410 }
 411
 412 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
 413 {
 414         vmcs_write32(VM_EXIT_CONTROLS, val);
 415         vmx->vm_exit_controls_shadow = val;
 416 }
 417
 418 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
 419 {
 420         if (vmx->vm_exit_controls_shadow != val)
 421                 vm_exit_controls_init(vmx, val);
 422 }
 423
 424 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
 425 {
 426         return vmx->vm_exit_controls_shadow;
 427 }
 428
 429 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
 430 {
 431         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
 432 }
 433
 434 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
 435 {
 436         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
 437 }
 438
 439 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
 440 {
 441         vmx->segment_cache.bitmask = 0;
 442 }
 443
 444 static inline u32 vmx_vmentry_ctrl(void)
 445 {
 446         u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
 447         if (pt_mode == PT_MODE_SYSTEM)
 448                 vmentry_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP | VM_EXIT_CLEAR_IA32_RTIT_CTL);
 449         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
 450         return vmentry_ctrl &
 451                 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
 452 }
 453
 454 static inline u32 vmx_vmexit_ctrl(void)
 455 {
 456         u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
 457         if (pt_mode == PT_MODE_SYSTEM)
 458                 vmexit_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP | VM_ENTRY_LOAD_IA32_RTIT_CTL);
 459         /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
 460         return vmcs_config.vmexit_ctrl &
 461                 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
 462 }
 463
 464 u32 vmx_exec_control(struct vcpu_vmx *vmx);
 465
 466 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
 467 {
 468         return container_of(kvm, struct kvm_vmx, kvm);
 469 }
 470
 471 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 472 {
 473         return container_of(vcpu, struct vcpu_vmx, vcpu);
 474 }
 475
 476 static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 477 {
 478         return &(to_vmx(vcpu)->pi_desc);
 479 }
 480
 481 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu);
 482 void free_vmcs(struct vmcs *vmcs);
 483 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
 484 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
 485 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs);
 486 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
 487
 488 static inline struct vmcs *alloc_vmcs(bool shadow)
 489 {
 490         return alloc_vmcs_cpu(shadow, raw_smp_processor_id());
 491 }
 492
 493 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 494
 495 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
 496                                 bool invalidate_gpa)
 497 {
 498         if (enable_ept && (invalidate_gpa || !enable_vpid)) {
 499                 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
 500                         return;
 501                 ept_sync_context(construct_eptp(vcpu,
 502                                                 vcpu->arch.mmu->root_hpa));
 503         } else {
 504                 vpid_sync_context(vpid);
 505         }
 506 }
 507
 508 static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
 509 {
 510         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
 511 }
 512
 513 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
 514 {
 515         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
 516         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
 517 }
 518
 519 #endif /* __KVM_X86_VMX_H */