arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include "kvm_cache_regs.h"
  38 #include "x86.h"
  39
  40 #include <asm/cpu.h>
  41 #include <asm/io.h>
  42 #include <asm/desc.h>
  43 #include <asm/vmx.h>
  44 #include <asm/virtext.h>
  45 #include <asm/mce.h>
  46 #include <asm/fpu/internal.h>
  47 #include <asm/perf_event.h>
  48 #include <asm/debugreg.h>
  49 #include <asm/kexec.h>
  50 #include <asm/apic.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/mmu_context.h>
  53
  54 #include "trace.h"
  55 #include "pmu.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58 #define __ex_clear(x, reg) \
  59         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  60
  61 MODULE_AUTHOR("Qumranet");
  62 MODULE_LICENSE("GPL");
  63
  64 static const struct x86_cpu_id vmx_cpu_id[] = {
  65         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  66         {}
  67 };
  68 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  69
  70 static bool __read_mostly enable_vpid = 1;
  71 module_param_named(vpid, enable_vpid, bool, 0444);
  72
  73 static bool __read_mostly flexpriority_enabled = 1;
  74 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_ept = 1;
  77 module_param_named(ept, enable_ept, bool, S_IRUGO);
  78
  79 static bool __read_mostly enable_unrestricted_guest = 1;
  80 module_param_named(unrestricted_guest,
  81                         enable_unrestricted_guest, bool, S_IRUGO);
  82
  83 static bool __read_mostly enable_ept_ad_bits = 1;
  84 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  85
  86 static bool __read_mostly emulate_invalid_guest_state = true;
  87 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 113 static int __read_mostly cpu_preemption_timer_multi;
 114 static bool __read_mostly enable_preemption_timer = 1;
 115 #ifdef CONFIG_X86_64
 116 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 117 #endif
 118
 119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 121 #define KVM_VM_CR0_ALWAYS_ON                                            \
 122         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 123 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 124         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 125          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 126
 127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 129
 130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 131
 132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 133
 134 /*
 135  * Hyper-V requires all of these, so mark them as supported even though
 136  * they are just treated the same as all-context.
 137  */
 138 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 139         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 140         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 141         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 143
 144 /*
 145  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 146  * ple_gap:    upper bound on the amount of time between two successive
 147  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 148  *             According to test, this time is usually smaller than 128 cycles.
 149  * ple_window: upper bound on the amount of time a guest is allowed to execute
 150  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 151  *             less than 2^12 cycles
 152  * Time is measured based on a counter that runs at the same rate as the TSC,
 153  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 154  */
 155 #define KVM_VMX_DEFAULT_PLE_GAP           128
 156 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 160                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 161
 162 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 163 module_param(ple_gap, int, S_IRUGO);
 164
 165 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 166 module_param(ple_window, int, S_IRUGO);
 167
 168 /* Default doubles per-vcpu window every exit. */
 169 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 170 module_param(ple_window_grow, int, S_IRUGO);
 171
 172 /* Default resets per-vcpu window every exit to ple_window. */
 173 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 174 module_param(ple_window_shrink, int, S_IRUGO);
 175
 176 /* Default is to compute the maximum so we can never overflow. */
 177 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 178 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, int, S_IRUGO);
 180
 181 extern const ulong vmx_return;
 182
 183 #define NR_AUTOLOAD_MSRS 8
 184 #define VMCS02_POOL_SIZE 1
 185
 186 struct vmcs {
 187         u32 revision_id;
 188         u32 abort;
 189         char data[0];
 190 };
 191
 192 /*
 193  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 194  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 195  * loaded on this CPU (so we can clear them if the CPU goes down).
 196  */
 197 struct loaded_vmcs {
 198         struct vmcs *vmcs;
 199         struct vmcs *shadow_vmcs;
 200         int cpu;
 201         bool launched;
 202         bool nmi_known_unmasked;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 ept_pointer;
 247         u64 eoi_exit_bitmap0;
 248         u64 eoi_exit_bitmap1;
 249         u64 eoi_exit_bitmap2;
 250         u64 eoi_exit_bitmap3;
 251         u64 xss_exit_bitmap;
 252         u64 guest_physical_address;
 253         u64 vmcs_link_pointer;
 254         u64 pml_address;
 255         u64 guest_ia32_debugctl;
 256         u64 guest_ia32_pat;
 257         u64 guest_ia32_efer;
 258         u64 guest_ia32_perf_global_ctrl;
 259         u64 guest_pdptr0;
 260         u64 guest_pdptr1;
 261         u64 guest_pdptr2;
 262         u64 guest_pdptr3;
 263         u64 guest_bndcfgs;
 264         u64 host_ia32_pat;
 265         u64 host_ia32_efer;
 266         u64 host_ia32_perf_global_ctrl;
 267         u64 padding64[8]; /* room for future expansion */
 268         /*
 269          * To allow migration of L1 (complete with its L2 guests) between
 270          * machines of different natural widths (32 or 64 bit), we cannot have
 271          * unsigned long fields with no explict size. We use u64 (aliased
 272          * natural_width) instead. Luckily, x86 is little-endian.
 273          */
 274         natural_width cr0_guest_host_mask;
 275         natural_width cr4_guest_host_mask;
 276         natural_width cr0_read_shadow;
 277         natural_width cr4_read_shadow;
 278         natural_width cr3_target_value0;
 279         natural_width cr3_target_value1;
 280         natural_width cr3_target_value2;
 281         natural_width cr3_target_value3;
 282         natural_width exit_qualification;
 283         natural_width guest_linear_address;
 284         natural_width guest_cr0;
 285         natural_width guest_cr3;
 286         natural_width guest_cr4;
 287         natural_width guest_es_base;
 288         natural_width guest_cs_base;
 289         natural_width guest_ss_base;
 290         natural_width guest_ds_base;
 291         natural_width guest_fs_base;
 292         natural_width guest_gs_base;
 293         natural_width guest_ldtr_base;
 294         natural_width guest_tr_base;
 295         natural_width guest_gdtr_base;
 296         natural_width guest_idtr_base;
 297         natural_width guest_dr7;
 298         natural_width guest_rsp;
 299         natural_width guest_rip;
 300         natural_width guest_rflags;
 301         natural_width guest_pending_dbg_exceptions;
 302         natural_width guest_sysenter_esp;
 303         natural_width guest_sysenter_eip;
 304         natural_width host_cr0;
 305         natural_width host_cr3;
 306         natural_width host_cr4;
 307         natural_width host_fs_base;
 308         natural_width host_gs_base;
 309         natural_width host_tr_base;
 310         natural_width host_gdtr_base;
 311         natural_width host_idtr_base;
 312         natural_width host_ia32_sysenter_esp;
 313         natural_width host_ia32_sysenter_eip;
 314         natural_width host_rsp;
 315         natural_width host_rip;
 316         natural_width paddingl[8]; /* room for future expansion */
 317         u32 pin_based_vm_exec_control;
 318         u32 cpu_based_vm_exec_control;
 319         u32 exception_bitmap;
 320         u32 page_fault_error_code_mask;
 321         u32 page_fault_error_code_match;
 322         u32 cr3_target_count;
 323         u32 vm_exit_controls;
 324         u32 vm_exit_msr_store_count;
 325         u32 vm_exit_msr_load_count;
 326         u32 vm_entry_controls;
 327         u32 vm_entry_msr_load_count;
 328         u32 vm_entry_intr_info_field;
 329         u32 vm_entry_exception_error_code;
 330         u32 vm_entry_instruction_len;
 331         u32 tpr_threshold;
 332         u32 secondary_vm_exec_control;
 333         u32 vm_instruction_error;
 334         u32 vm_exit_reason;
 335         u32 vm_exit_intr_info;
 336         u32 vm_exit_intr_error_code;
 337         u32 idt_vectoring_info_field;
 338         u32 idt_vectoring_error_code;
 339         u32 vm_exit_instruction_len;
 340         u32 vmx_instruction_info;
 341         u32 guest_es_limit;
 342         u32 guest_cs_limit;
 343         u32 guest_ss_limit;
 344         u32 guest_ds_limit;
 345         u32 guest_fs_limit;
 346         u32 guest_gs_limit;
 347         u32 guest_ldtr_limit;
 348         u32 guest_tr_limit;
 349         u32 guest_gdtr_limit;
 350         u32 guest_idtr_limit;
 351         u32 guest_es_ar_bytes;
 352         u32 guest_cs_ar_bytes;
 353         u32 guest_ss_ar_bytes;
 354         u32 guest_ds_ar_bytes;
 355         u32 guest_fs_ar_bytes;
 356         u32 guest_gs_ar_bytes;
 357         u32 guest_ldtr_ar_bytes;
 358         u32 guest_tr_ar_bytes;
 359         u32 guest_interruptibility_info;
 360         u32 guest_activity_state;
 361         u32 guest_sysenter_cs;
 362         u32 host_ia32_sysenter_cs;
 363         u32 vmx_preemption_timer_value;
 364         u32 padding32[7]; /* room for future expansion */
 365         u16 virtual_processor_id;
 366         u16 posted_intr_nv;
 367         u16 guest_es_selector;
 368         u16 guest_cs_selector;
 369         u16 guest_ss_selector;
 370         u16 guest_ds_selector;
 371         u16 guest_fs_selector;
 372         u16 guest_gs_selector;
 373         u16 guest_ldtr_selector;
 374         u16 guest_tr_selector;
 375         u16 guest_intr_status;
 376         u16 guest_pml_index;
 377         u16 host_es_selector;
 378         u16 host_cs_selector;
 379         u16 host_ss_selector;
 380         u16 host_ds_selector;
 381         u16 host_fs_selector;
 382         u16 host_gs_selector;
 383         u16 host_tr_selector;
 384 };
 385
 386 /*
 387  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 388  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 389  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 390  */
 391 #define VMCS12_REVISION 0x11e57ed0
 392
 393 /*
 394  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 395  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 396  * current implementation, 4K are reserved to avoid future complications.
 397  */
 398 #define VMCS12_SIZE 0x1000
 399
 400 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 401 struct vmcs02_list {
 402         struct list_head list;
 403         gpa_t vmptr;
 404         struct loaded_vmcs vmcs02;
 405 };
 406
 407 /*
 408  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 409  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 410  */
 411 struct nested_vmx {
 412         /* Has the level1 guest done vmxon? */
 413         bool vmxon;
 414         gpa_t vmxon_ptr;
 415         bool pml_full;
 416
 417         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 418         gpa_t current_vmptr;
 419         /* The host-usable pointer to the above */
 420         struct page *current_vmcs12_page;
 421         struct vmcs12 *current_vmcs12;
 422         /*
 423          * Cache of the guest's VMCS, existing outside of guest memory.
 424          * Loaded from guest memory during VMPTRLD. Flushed to guest
 425          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 426          */
 427         struct vmcs12 *cached_vmcs12;
 428         /*
 429          * Indicates if the shadow vmcs must be updated with the
 430          * data hold by vmcs12
 431          */
 432         bool sync_shadow_vmcs;
 433
 434         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 435         struct list_head vmcs02_pool;
 436         int vmcs02_num;
 437         bool change_vmcs01_virtual_x2apic_mode;
 438         /* L2 must run next, and mustn't decide to exit to L1. */
 439         bool nested_run_pending;
 440         /*
 441          * Guest pages referred to in vmcs02 with host-physical pointers, so
 442          * we must keep them pinned while L2 runs.
 443          */
 444         struct page *apic_access_page;
 445         struct page *virtual_apic_page;
 446         struct page *pi_desc_page;
 447         struct pi_desc *pi_desc;
 448         bool pi_pending;
 449         u16 posted_intr_nv;
 450
 451         unsigned long *msr_bitmap;
 452
 453         struct hrtimer preemption_timer;
 454         bool preemption_timer_expired;
 455
 456         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 457         u64 vmcs01_debugctl;
 458
 459         u16 vpid02;
 460         u16 last_vpid;
 461
 462         /*
 463          * We only store the "true" versions of the VMX capability MSRs. We
 464          * generate the "non-true" versions by setting the must-be-1 bits
 465          * according to the SDM.
 466          */
 467         u32 nested_vmx_procbased_ctls_low;
 468         u32 nested_vmx_procbased_ctls_high;
 469         u32 nested_vmx_secondary_ctls_low;
 470         u32 nested_vmx_secondary_ctls_high;
 471         u32 nested_vmx_pinbased_ctls_low;
 472         u32 nested_vmx_pinbased_ctls_high;
 473         u32 nested_vmx_exit_ctls_low;
 474         u32 nested_vmx_exit_ctls_high;
 475         u32 nested_vmx_entry_ctls_low;
 476         u32 nested_vmx_entry_ctls_high;
 477         u32 nested_vmx_misc_low;
 478         u32 nested_vmx_misc_high;
 479         u32 nested_vmx_ept_caps;
 480         u32 nested_vmx_vpid_caps;
 481         u64 nested_vmx_basic;
 482         u64 nested_vmx_cr0_fixed0;
 483         u64 nested_vmx_cr0_fixed1;
 484         u64 nested_vmx_cr4_fixed0;
 485         u64 nested_vmx_cr4_fixed1;
 486         u64 nested_vmx_vmcs_enum;
 487 };
 488
 489 #define POSTED_INTR_ON  0
 490 #define POSTED_INTR_SN  1
 491
 492 /* Posted-Interrupt Descriptor */
 493 struct pi_desc {
 494         u32 pir[8];     /* Posted interrupt requested */
 495         union {
 496                 struct {
 497                                 /* bit 256 - Outstanding Notification */
 498                         u16     on      : 1,
 499                                 /* bit 257 - Suppress Notification */
 500                                 sn      : 1,
 501                                 /* bit 271:258 - Reserved */
 502                                 rsvd_1  : 14;
 503                                 /* bit 279:272 - Notification Vector */
 504                         u8      nv;
 505                                 /* bit 287:280 - Reserved */
 506                         u8      rsvd_2;
 507                                 /* bit 319:288 - Notification Destination */
 508                         u32     ndst;
 509                 };
 510                 u64 control;
 511         };
 512         u32 rsvd[6];
 513 } __aligned(64);
 514
 515 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 516 {
 517         return test_and_set_bit(POSTED_INTR_ON,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 522 {
 523         return test_and_clear_bit(POSTED_INTR_ON,
 524                         (unsigned long *)&pi_desc->control);
 525 }
 526
 527 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 528 {
 529         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 530 }
 531
 532 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 533 {
 534         return clear_bit(POSTED_INTR_SN,
 535                         (unsigned long *)&pi_desc->control);
 536 }
 537
 538 static inline void pi_set_sn(struct pi_desc *pi_desc)
 539 {
 540         return set_bit(POSTED_INTR_SN,
 541                         (unsigned long *)&pi_desc->control);
 542 }
 543
 544 static inline void pi_clear_on(struct pi_desc *pi_desc)
 545 {
 546         clear_bit(POSTED_INTR_ON,
 547                   (unsigned long *)&pi_desc->control);
 548 }
 549
 550 static inline int pi_test_on(struct pi_desc *pi_desc)
 551 {
 552         return test_bit(POSTED_INTR_ON,
 553                         (unsigned long *)&pi_desc->control);
 554 }
 555
 556 static inline int pi_test_sn(struct pi_desc *pi_desc)
 557 {
 558         return test_bit(POSTED_INTR_SN,
 559                         (unsigned long *)&pi_desc->control);
 560 }
 561
 562 struct vcpu_vmx {
 563         struct kvm_vcpu       vcpu;
 564         unsigned long         host_rsp;
 565         u8                    fail;
 566         bool                  nmi_known_unmasked;
 567         u32                   exit_intr_info;
 568         u32                   idt_vectoring_info;
 569         ulong                 rflags;
 570         struct shared_msr_entry *guest_msrs;
 571         int                   nmsrs;
 572         int                   save_nmsrs;
 573         unsigned long         host_idt_base;
 574 #ifdef CONFIG_X86_64
 575         u64                   msr_host_kernel_gs_base;
 576         u64                   msr_guest_kernel_gs_base;
 577 #endif
 578         u32 vm_entry_controls_shadow;
 579         u32 vm_exit_controls_shadow;
 580         /*
 581          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 582          * non-nested (L1) guest, it always points to vmcs01. For a nested
 583          * guest (L2), it points to a different VMCS.
 584          */
 585         struct loaded_vmcs    vmcs01;
 586         struct loaded_vmcs   *loaded_vmcs;
 587         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 588         struct msr_autoload {
 589                 unsigned nr;
 590                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 591                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 592         } msr_autoload;
 593         struct {
 594                 int           loaded;
 595                 u16           fs_sel, gs_sel, ldt_sel;
 596 #ifdef CONFIG_X86_64
 597                 u16           ds_sel, es_sel;
 598 #endif
 599                 int           gs_ldt_reload_needed;
 600                 int           fs_reload_needed;
 601                 u64           msr_host_bndcfgs;
 602                 unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 603                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 604         } host_state;
 605         struct {
 606                 int vm86_active;
 607                 ulong save_rflags;
 608                 struct kvm_segment segs[8];
 609         } rmode;
 610         struct {
 611                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 612                 struct kvm_save_segment {
 613                         u16 selector;
 614                         unsigned long base;
 615                         u32 limit;
 616                         u32 ar;
 617                 } seg[8];
 618         } segment_cache;
 619         int vpid;
 620         bool emulation_required;
 621
 622         u32 exit_reason;
 623
 624         /* Posted interrupt descriptor */
 625         struct pi_desc pi_desc;
 626
 627         /* Support for a guest hypervisor (nested VMX) */
 628         struct nested_vmx nested;
 629
 630         /* Dynamic PLE window. */
 631         int ple_window;
 632         bool ple_window_dirty;
 633
 634         /* Support for PML */
 635 #define PML_ENTITY_NUM          512
 636         struct page *pml_pg;
 637
 638         /* apic deadline value in host tsc */
 639         u64 hv_deadline_tsc;
 640
 641         u64 current_tsc_ratio;
 642
 643         bool guest_pkru_valid;
 644         u32 guest_pkru;
 645         u32 host_pkru;
 646
 647         /*
 648          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 649          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 650          * in msr_ia32_feature_control_valid_bits.
 651          */
 652         u64 msr_ia32_feature_control;
 653         u64 msr_ia32_feature_control_valid_bits;
 654 };
 655
 656 enum segment_cache_field {
 657         SEG_FIELD_SEL = 0,
 658         SEG_FIELD_BASE = 1,
 659         SEG_FIELD_LIMIT = 2,
 660         SEG_FIELD_AR = 3,
 661
 662         SEG_FIELD_NR = 4
 663 };
 664
 665 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 666 {
 667         return container_of(vcpu, struct vcpu_vmx, vcpu);
 668 }
 669
 670 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 671 {
 672         return &(to_vmx(vcpu)->pi_desc);
 673 }
 674
 675 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 676 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 677 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 678                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 679
 680
 681 static unsigned long shadow_read_only_fields[] = {
 682         /*
 683          * We do NOT shadow fields that are modified when L0
 684          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 685          * VMXON...) executed by L1.
 686          * For example, VM_INSTRUCTION_ERROR is read
 687          * by L1 if a vmx instruction fails (part of the error path).
 688          * Note the code assumes this logic. If for some reason
 689          * we start shadowing these fields then we need to
 690          * force a shadow sync when L0 emulates vmx instructions
 691          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 692          * by nested_vmx_failValid)
 693          */
 694         VM_EXIT_REASON,
 695         VM_EXIT_INTR_INFO,
 696         VM_EXIT_INSTRUCTION_LEN,
 697         IDT_VECTORING_INFO_FIELD,
 698         IDT_VECTORING_ERROR_CODE,
 699         VM_EXIT_INTR_ERROR_CODE,
 700         EXIT_QUALIFICATION,
 701         GUEST_LINEAR_ADDRESS,
 702         GUEST_PHYSICAL_ADDRESS
 703 };
 704 static int max_shadow_read_only_fields =
 705         ARRAY_SIZE(shadow_read_only_fields);
 706
 707 static unsigned long shadow_read_write_fields[] = {
 708         TPR_THRESHOLD,
 709         GUEST_RIP,
 710         GUEST_RSP,
 711         GUEST_CR0,
 712         GUEST_CR3,
 713         GUEST_CR4,
 714         GUEST_INTERRUPTIBILITY_INFO,
 715         GUEST_RFLAGS,
 716         GUEST_CS_SELECTOR,
 717         GUEST_CS_AR_BYTES,
 718         GUEST_CS_LIMIT,
 719         GUEST_CS_BASE,
 720         GUEST_ES_BASE,
 721         GUEST_BNDCFGS,
 722         CR0_GUEST_HOST_MASK,
 723         CR0_READ_SHADOW,
 724         CR4_READ_SHADOW,
 725         TSC_OFFSET,
 726         EXCEPTION_BITMAP,
 727         CPU_BASED_VM_EXEC_CONTROL,
 728         VM_ENTRY_EXCEPTION_ERROR_CODE,
 729         VM_ENTRY_INTR_INFO_FIELD,
 730         VM_ENTRY_INSTRUCTION_LEN,
 731         VM_ENTRY_EXCEPTION_ERROR_CODE,
 732         HOST_FS_BASE,
 733         HOST_GS_BASE,
 734         HOST_FS_SELECTOR,
 735         HOST_GS_SELECTOR
 736 };
 737 static int max_shadow_read_write_fields =
 738         ARRAY_SIZE(shadow_read_write_fields);
 739
 740 static const unsigned short vmcs_field_to_offset_table[] = {
 741         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 742         FIELD(POSTED_INTR_NV, posted_intr_nv),
 743         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 744         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 745         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 746         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 747         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 748         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 749         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 750         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 751         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 752         FIELD(GUEST_PML_INDEX, guest_pml_index),
 753         FIELD(HOST_ES_SELECTOR, host_es_selector),
 754         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 755         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 756         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 757         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 758         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 759         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 760         FIELD64(IO_BITMAP_A, io_bitmap_a),
 761         FIELD64(IO_BITMAP_B, io_bitmap_b),
 762         FIELD64(MSR_BITMAP, msr_bitmap),
 763         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 764         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 765         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 766         FIELD64(TSC_OFFSET, tsc_offset),
 767         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 768         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 769         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 770         FIELD64(EPT_POINTER, ept_pointer),
 771         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 772         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 773         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 774         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 775         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 776         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 777         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 778         FIELD64(PML_ADDRESS, pml_address),
 779         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 780         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 781         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 782         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 783         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 784         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 785         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 786         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 787         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 788         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 789         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 790         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 791         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 792         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 793         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 794         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 795         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 796         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 797         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 798         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 799         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 800         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 801         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 802         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 803         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 804         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 805         FIELD(TPR_THRESHOLD, tpr_threshold),
 806         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 807         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 808         FIELD(VM_EXIT_REASON, vm_exit_reason),
 809         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 810         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 811         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 812         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 813         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 814         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 815         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 816         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 817         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 818         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 819         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 820         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 821         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 822         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 823         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 824         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 825         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 826         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 827         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 828         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 829         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 830         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 831         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 832         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 833         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 834         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 835         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 836         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 837         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 838         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 839         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 840         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 841         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 842         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 843         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 844         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 845         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 846         FIELD(EXIT_QUALIFICATION, exit_qualification),
 847         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 848         FIELD(GUEST_CR0, guest_cr0),
 849         FIELD(GUEST_CR3, guest_cr3),
 850         FIELD(GUEST_CR4, guest_cr4),
 851         FIELD(GUEST_ES_BASE, guest_es_base),
 852         FIELD(GUEST_CS_BASE, guest_cs_base),
 853         FIELD(GUEST_SS_BASE, guest_ss_base),
 854         FIELD(GUEST_DS_BASE, guest_ds_base),
 855         FIELD(GUEST_FS_BASE, guest_fs_base),
 856         FIELD(GUEST_GS_BASE, guest_gs_base),
 857         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 858         FIELD(GUEST_TR_BASE, guest_tr_base),
 859         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 860         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 861         FIELD(GUEST_DR7, guest_dr7),
 862         FIELD(GUEST_RSP, guest_rsp),
 863         FIELD(GUEST_RIP, guest_rip),
 864         FIELD(GUEST_RFLAGS, guest_rflags),
 865         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 866         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 867         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 868         FIELD(HOST_CR0, host_cr0),
 869         FIELD(HOST_CR3, host_cr3),
 870         FIELD(HOST_CR4, host_cr4),
 871         FIELD(HOST_FS_BASE, host_fs_base),
 872         FIELD(HOST_GS_BASE, host_gs_base),
 873         FIELD(HOST_TR_BASE, host_tr_base),
 874         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 875         FIELD(HOST_IDTR_BASE, host_idtr_base),
 876         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 877         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 878         FIELD(HOST_RSP, host_rsp),
 879         FIELD(HOST_RIP, host_rip),
 880 };
 881
 882 static inline short vmcs_field_to_offset(unsigned long field)
 883 {
 884         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 885
 886         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 887             vmcs_field_to_offset_table[field] == 0)
 888                 return -ENOENT;
 889
 890         return vmcs_field_to_offset_table[field];
 891 }
 892
 893 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 894 {
 895         return to_vmx(vcpu)->nested.cached_vmcs12;
 896 }
 897
 898 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 899 {
 900         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 901         if (is_error_page(page))
 902                 return NULL;
 903
 904         return page;
 905 }
 906
 907 static void nested_release_page(struct page *page)
 908 {
 909         kvm_release_page_dirty(page);
 910 }
 911
 912 static void nested_release_page_clean(struct page *page)
 913 {
 914         kvm_release_page_clean(page);
 915 }
 916
 917 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
 918 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 919 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 920 static bool vmx_xsaves_supported(void);
 921 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 922 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 923                             struct kvm_segment *var, int seg);
 924 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 925                             struct kvm_segment *var, int seg);
 926 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 927 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 928 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 929 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 930 static int alloc_identity_pagetable(struct kvm *kvm);
 931
 932 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 933 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 934 /*
 935  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 936  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 937  */
 938 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 939
 940 /*
 941  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 942  * can find which vCPU should be waken up.
 943  */
 944 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 945 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 946
 947 enum {
 948         VMX_IO_BITMAP_A,
 949         VMX_IO_BITMAP_B,
 950         VMX_MSR_BITMAP_LEGACY,
 951         VMX_MSR_BITMAP_LONGMODE,
 952         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 953         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 954         VMX_MSR_BITMAP_LEGACY_X2APIC,
 955         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 956         VMX_VMREAD_BITMAP,
 957         VMX_VMWRITE_BITMAP,
 958         VMX_BITMAP_NR
 959 };
 960
 961 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 962
 963 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 964 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 965 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 966 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 967 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 968 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 969 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 970 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 971 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 972 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 973
 974 static bool cpu_has_load_ia32_efer;
 975 static bool cpu_has_load_perf_global_ctrl;
 976
 977 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 978 static DEFINE_SPINLOCK(vmx_vpid_lock);
 979
 980 static struct vmcs_config {
 981         int size;
 982         int order;
 983         u32 basic_cap;
 984         u32 revision_id;
 985         u32 pin_based_exec_ctrl;
 986         u32 cpu_based_exec_ctrl;
 987         u32 cpu_based_2nd_exec_ctrl;
 988         u32 vmexit_ctrl;
 989         u32 vmentry_ctrl;
 990 } vmcs_config;
 991
 992 static struct vmx_capability {
 993         u32 ept;
 994         u32 vpid;
 995 } vmx_capability;
 996
 997 #define VMX_SEGMENT_FIELD(seg)                                  \
 998         [VCPU_SREG_##seg] = {                                   \
 999                 .selector = GUEST_##seg##_SELECTOR,             \
1000                 .base = GUEST_##seg##_BASE,                     \
1001                 .limit = GUEST_##seg##_LIMIT,                   \
1002                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1003         }
1004
1005 static const struct kvm_vmx_segment_field {
1006         unsigned selector;
1007         unsigned base;
1008         unsigned limit;
1009         unsigned ar_bytes;
1010 } kvm_vmx_segment_fields[] = {
1011         VMX_SEGMENT_FIELD(CS),
1012         VMX_SEGMENT_FIELD(DS),
1013         VMX_SEGMENT_FIELD(ES),
1014         VMX_SEGMENT_FIELD(FS),
1015         VMX_SEGMENT_FIELD(GS),
1016         VMX_SEGMENT_FIELD(SS),
1017         VMX_SEGMENT_FIELD(TR),
1018         VMX_SEGMENT_FIELD(LDTR),
1019 };
1020
1021 static u64 host_efer;
1022
1023 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1024
1025 /*
1026  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1027  * away by decrementing the array size.
1028  */
1029 static const u32 vmx_msr_index[] = {
1030 #ifdef CONFIG_X86_64
1031         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1032 #endif
1033         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1034 };
1035
1036 static inline bool is_exception_n(u32 intr_info, u8 vector)
1037 {
1038         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1039                              INTR_INFO_VALID_MASK)) ==
1040                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1041 }
1042
1043 static inline bool is_debug(u32 intr_info)
1044 {
1045         return is_exception_n(intr_info, DB_VECTOR);
1046 }
1047
1048 static inline bool is_breakpoint(u32 intr_info)
1049 {
1050         return is_exception_n(intr_info, BP_VECTOR);
1051 }
1052
1053 static inline bool is_page_fault(u32 intr_info)
1054 {
1055         return is_exception_n(intr_info, PF_VECTOR);
1056 }
1057
1058 static inline bool is_no_device(u32 intr_info)
1059 {
1060         return is_exception_n(intr_info, NM_VECTOR);
1061 }
1062
1063 static inline bool is_invalid_opcode(u32 intr_info)
1064 {
1065         return is_exception_n(intr_info, UD_VECTOR);
1066 }
1067
1068 static inline bool is_external_interrupt(u32 intr_info)
1069 {
1070         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1071                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1072 }
1073
1074 static inline bool is_machine_check(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1077                              INTR_INFO_VALID_MASK)) ==
1078                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1079 }
1080
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1082 {
1083         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1084 }
1085
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1087 {
1088         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1089 }
1090
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1092 {
1093         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1094 }
1095
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1097 {
1098         return vmcs_config.cpu_based_exec_ctrl &
1099                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1100 }
1101
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1103 {
1104         return vmcs_config.cpu_based_2nd_exec_ctrl &
1105                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1106 }
1107
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1109 {
1110         return vmcs_config.cpu_based_2nd_exec_ctrl &
1111                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1112 }
1113
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1115 {
1116         return vmcs_config.cpu_based_2nd_exec_ctrl &
1117                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1118 }
1119
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1121 {
1122         return vmcs_config.cpu_based_2nd_exec_ctrl &
1123                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1124 }
1125
1126 /*
1127  * Comment's format: document - errata name - stepping - processor name.
1128  * Refer from
1129  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1130  */
1131 static u32 vmx_preemption_cpu_tfms[] = {
1132 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1133 0x000206E6,
1134 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 0x00020652,
1138 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1139 0x00020655,
1140 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1142 /*
1143  * 320767.pdf - AAP86  - B1 -
1144  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1145  */
1146 0x000106E5,
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1148 0x000106A0,
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1150 0x000106A1,
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1152 0x000106A4,
1153  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1156 0x000106A5,
1157 };
1158
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1160 {
1161         u32 eax = cpuid_eax(0x00000001), i;
1162
1163         /* Clear the reserved bits */
1164         eax &= ~(0x3U << 14 | 0xfU << 28);
1165         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1166                 if (eax == vmx_preemption_cpu_tfms[i])
1167                         return true;
1168
1169         return false;
1170 }
1171
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1173 {
1174         return vmcs_config.pin_based_exec_ctrl &
1175                 PIN_BASED_VMX_PREEMPTION_TIMER;
1176 }
1177
1178 static inline bool cpu_has_vmx_posted_intr(void)
1179 {
1180         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1181                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1182 }
1183
1184 static inline bool cpu_has_vmx_apicv(void)
1185 {
1186         return cpu_has_vmx_apic_register_virt() &&
1187                 cpu_has_vmx_virtual_intr_delivery() &&
1188                 cpu_has_vmx_posted_intr();
1189 }
1190
1191 static inline bool cpu_has_vmx_flexpriority(void)
1192 {
1193         return cpu_has_vmx_tpr_shadow() &&
1194                 cpu_has_vmx_virtualize_apic_accesses();
1195 }
1196
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1198 {
1199         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1200 }
1201
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1203 {
1204         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1205 }
1206
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1208 {
1209         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1210 }
1211
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1213 {
1214         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1215 }
1216
1217 static inline bool cpu_has_vmx_ept_ad_bits(void)
1218 {
1219         return vmx_capability.ept & VMX_EPT_AD_BIT;
1220 }
1221
1222 static inline bool cpu_has_vmx_invept_context(void)
1223 {
1224         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1225 }
1226
1227 static inline bool cpu_has_vmx_invept_global(void)
1228 {
1229         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1230 }
1231
1232 static inline bool cpu_has_vmx_invvpid_single(void)
1233 {
1234         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1235 }
1236
1237 static inline bool cpu_has_vmx_invvpid_global(void)
1238 {
1239         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1240 }
1241
1242 static inline bool cpu_has_vmx_invvpid(void)
1243 {
1244         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1245 }
1246
1247 static inline bool cpu_has_vmx_ept(void)
1248 {
1249         return vmcs_config.cpu_based_2nd_exec_ctrl &
1250                 SECONDARY_EXEC_ENABLE_EPT;
1251 }
1252
1253 static inline bool cpu_has_vmx_unrestricted_guest(void)
1254 {
1255         return vmcs_config.cpu_based_2nd_exec_ctrl &
1256                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1257 }
1258
1259 static inline bool cpu_has_vmx_ple(void)
1260 {
1261         return vmcs_config.cpu_based_2nd_exec_ctrl &
1262                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1263 }
1264
1265 static inline bool cpu_has_vmx_basic_inout(void)
1266 {
1267         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1268 }
1269
1270 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1271 {
1272         return flexpriority_enabled && lapic_in_kernel(vcpu);
1273 }
1274
1275 static inline bool cpu_has_vmx_vpid(void)
1276 {
1277         return vmcs_config.cpu_based_2nd_exec_ctrl &
1278                 SECONDARY_EXEC_ENABLE_VPID;
1279 }
1280
1281 static inline bool cpu_has_vmx_rdtscp(void)
1282 {
1283         return vmcs_config.cpu_based_2nd_exec_ctrl &
1284                 SECONDARY_EXEC_RDTSCP;
1285 }
1286
1287 static inline bool cpu_has_vmx_invpcid(void)
1288 {
1289         return vmcs_config.cpu_based_2nd_exec_ctrl &
1290                 SECONDARY_EXEC_ENABLE_INVPCID;
1291 }
1292
1293 static inline bool cpu_has_vmx_wbinvd_exit(void)
1294 {
1295         return vmcs_config.cpu_based_2nd_exec_ctrl &
1296                 SECONDARY_EXEC_WBINVD_EXITING;
1297 }
1298
1299 static inline bool cpu_has_vmx_shadow_vmcs(void)
1300 {
1301         u64 vmx_msr;
1302         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1303         /* check if the cpu supports writing r/o exit information fields */
1304         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1305                 return false;
1306
1307         return vmcs_config.cpu_based_2nd_exec_ctrl &
1308                 SECONDARY_EXEC_SHADOW_VMCS;
1309 }
1310
1311 static inline bool cpu_has_vmx_pml(void)
1312 {
1313         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1314 }
1315
1316 static inline bool cpu_has_vmx_tsc_scaling(void)
1317 {
1318         return vmcs_config.cpu_based_2nd_exec_ctrl &
1319                 SECONDARY_EXEC_TSC_SCALING;
1320 }
1321
1322 static inline bool report_flexpriority(void)
1323 {
1324         return flexpriority_enabled;
1325 }
1326
1327 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1328 {
1329         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1330 }
1331
1332 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1333 {
1334         return vmcs12->cpu_based_vm_exec_control & bit;
1335 }
1336
1337 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1338 {
1339         return (vmcs12->cpu_based_vm_exec_control &
1340                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1341                 (vmcs12->secondary_vm_exec_control & bit);
1342 }
1343
1344 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1345 {
1346         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1347 }
1348
1349 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1350 {
1351         return vmcs12->pin_based_vm_exec_control &
1352                 PIN_BASED_VMX_PREEMPTION_TIMER;
1353 }
1354
1355 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1356 {
1357         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1358 }
1359
1360 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1361 {
1362         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1363                 vmx_xsaves_supported();
1364 }
1365
1366 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1367 {
1368         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1369 }
1370
1371 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1372 {
1373         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1374 }
1375
1376 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1377 {
1378         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1379 }
1380
1381 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1382 {
1383         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1384 }
1385
1386 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1387 {
1388         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1389 }
1390
1391 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1392 {
1393         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1394 }
1395
1396 static inline bool is_nmi(u32 intr_info)
1397 {
1398         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1399                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1400 }
1401
1402 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1403                               u32 exit_intr_info,
1404                               unsigned long exit_qualification);
1405 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1406                         struct vmcs12 *vmcs12,
1407                         u32 reason, unsigned long qualification);
1408
1409 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1410 {
1411         int i;
1412
1413         for (i = 0; i < vmx->nmsrs; ++i)
1414                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1415                         return i;
1416         return -1;
1417 }
1418
1419 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1420 {
1421     struct {
1422         u64 vpid : 16;
1423         u64 rsvd : 48;
1424         u64 gva;
1425     } operand = { vpid, 0, gva };
1426
1427     asm volatile (__ex(ASM_VMX_INVVPID)
1428                   /* CF==1 or ZF==1 --> rc = -1 */
1429                   "; ja 1f ; ud2 ; 1:"
1430                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1431 }
1432
1433 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1434 {
1435         struct {
1436                 u64 eptp, gpa;
1437         } operand = {eptp, gpa};
1438
1439         asm volatile (__ex(ASM_VMX_INVEPT)
1440                         /* CF==1 or ZF==1 --> rc = -1 */
1441                         "; ja 1f ; ud2 ; 1:\n"
1442                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1443 }
1444
1445 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1446 {
1447         int i;
1448
1449         i = __find_msr_index(vmx, msr);
1450         if (i >= 0)
1451                 return &vmx->guest_msrs[i];
1452         return NULL;
1453 }
1454
1455 static void vmcs_clear(struct vmcs *vmcs)
1456 {
1457         u64 phys_addr = __pa(vmcs);
1458         u8 error;
1459
1460         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1461                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1462                       : "cc", "memory");
1463         if (error)
1464                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1465                        vmcs, phys_addr);
1466 }
1467
1468 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1469 {
1470         vmcs_clear(loaded_vmcs->vmcs);
1471         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1472                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1473         loaded_vmcs->cpu = -1;
1474         loaded_vmcs->launched = 0;
1475 }
1476
1477 static void vmcs_load(struct vmcs *vmcs)
1478 {
1479         u64 phys_addr = __pa(vmcs);
1480         u8 error;
1481
1482         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1483                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1484                         : "cc", "memory");
1485         if (error)
1486                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1487                        vmcs, phys_addr);
1488 }
1489
1490 #ifdef CONFIG_KEXEC_CORE
1491 /*
1492  * This bitmap is used to indicate whether the vmclear
1493  * operation is enabled on all cpus. All disabled by
1494  * default.
1495  */
1496 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1497
1498 static inline void crash_enable_local_vmclear(int cpu)
1499 {
1500         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1501 }
1502
1503 static inline void crash_disable_local_vmclear(int cpu)
1504 {
1505         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1506 }
1507
1508 static inline int crash_local_vmclear_enabled(int cpu)
1509 {
1510         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1511 }
1512
1513 static void crash_vmclear_local_loaded_vmcss(void)
1514 {
1515         int cpu = raw_smp_processor_id();
1516         struct loaded_vmcs *v;
1517
1518         if (!crash_local_vmclear_enabled(cpu))
1519                 return;
1520
1521         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1522                             loaded_vmcss_on_cpu_link)
1523                 vmcs_clear(v->vmcs);
1524 }
1525 #else
1526 static inline void crash_enable_local_vmclear(int cpu) { }
1527 static inline void crash_disable_local_vmclear(int cpu) { }
1528 #endif /* CONFIG_KEXEC_CORE */
1529
1530 static void __loaded_vmcs_clear(void *arg)
1531 {
1532         struct loaded_vmcs *loaded_vmcs = arg;
1533         int cpu = raw_smp_processor_id();
1534
1535         if (loaded_vmcs->cpu != cpu)
1536                 return; /* vcpu migration can race with cpu offline */
1537         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1538                 per_cpu(current_vmcs, cpu) = NULL;
1539         crash_disable_local_vmclear(cpu);
1540         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1541
1542         /*
1543          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1544          * is before setting loaded_vmcs->vcpu to -1 which is done in
1545          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1546          * then adds the vmcs into percpu list before it is deleted.
1547          */
1548         smp_wmb();
1549
1550         loaded_vmcs_init(loaded_vmcs);
1551         crash_enable_local_vmclear(cpu);
1552 }
1553
1554 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1555 {
1556         int cpu = loaded_vmcs->cpu;
1557
1558         if (cpu != -1)
1559                 smp_call_function_single(cpu,
1560                          __loaded_vmcs_clear, loaded_vmcs, 1);
1561 }
1562
1563 static inline void vpid_sync_vcpu_single(int vpid)
1564 {
1565         if (vpid == 0)
1566                 return;
1567
1568         if (cpu_has_vmx_invvpid_single())
1569                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1570 }
1571
1572 static inline void vpid_sync_vcpu_global(void)
1573 {
1574         if (cpu_has_vmx_invvpid_global())
1575                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1576 }
1577
1578 static inline void vpid_sync_context(int vpid)
1579 {
1580         if (cpu_has_vmx_invvpid_single())
1581                 vpid_sync_vcpu_single(vpid);
1582         else
1583                 vpid_sync_vcpu_global();
1584 }
1585
1586 static inline void ept_sync_global(void)
1587 {
1588         if (cpu_has_vmx_invept_global())
1589                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1590 }
1591
1592 static inline void ept_sync_context(u64 eptp)
1593 {
1594         if (enable_ept) {
1595                 if (cpu_has_vmx_invept_context())
1596                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1597                 else
1598                         ept_sync_global();
1599         }
1600 }
1601
1602 static __always_inline void vmcs_check16(unsigned long field)
1603 {
1604         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1605                          "16-bit accessor invalid for 64-bit field");
1606         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1607                          "16-bit accessor invalid for 64-bit high field");
1608         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1609                          "16-bit accessor invalid for 32-bit high field");
1610         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1611                          "16-bit accessor invalid for natural width field");
1612 }
1613
1614 static __always_inline void vmcs_check32(unsigned long field)
1615 {
1616         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1617                          "32-bit accessor invalid for 16-bit field");
1618         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1619                          "32-bit accessor invalid for natural width field");
1620 }
1621
1622 static __always_inline void vmcs_check64(unsigned long field)
1623 {
1624         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1625                          "64-bit accessor invalid for 16-bit field");
1626         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1627                          "64-bit accessor invalid for 64-bit high field");
1628         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1629                          "64-bit accessor invalid for 32-bit field");
1630         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1631                          "64-bit accessor invalid for natural width field");
1632 }
1633
1634 static __always_inline void vmcs_checkl(unsigned long field)
1635 {
1636         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1637                          "Natural width accessor invalid for 16-bit field");
1638         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1639                          "Natural width accessor invalid for 64-bit field");
1640         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1641                          "Natural width accessor invalid for 64-bit high field");
1642         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1643                          "Natural width accessor invalid for 32-bit field");
1644 }
1645
1646 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1647 {
1648         unsigned long value;
1649
1650         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1651                       : "=a"(value) : "d"(field) : "cc");
1652         return value;
1653 }
1654
1655 static __always_inline u16 vmcs_read16(unsigned long field)
1656 {
1657         vmcs_check16(field);
1658         return __vmcs_readl(field);
1659 }
1660
1661 static __always_inline u32 vmcs_read32(unsigned long field)
1662 {
1663         vmcs_check32(field);
1664         return __vmcs_readl(field);
1665 }
1666
1667 static __always_inline u64 vmcs_read64(unsigned long field)
1668 {
1669         vmcs_check64(field);
1670 #ifdef CONFIG_X86_64
1671         return __vmcs_readl(field);
1672 #else
1673         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1674 #endif
1675 }
1676
1677 static __always_inline unsigned long vmcs_readl(unsigned long field)
1678 {
1679         vmcs_checkl(field);
1680         return __vmcs_readl(field);
1681 }
1682
1683 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1684 {
1685         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1686                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1687         dump_stack();
1688 }
1689
1690 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1691 {
1692         u8 error;
1693
1694         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1695                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1696         if (unlikely(error))
1697                 vmwrite_error(field, value);
1698 }
1699
1700 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1701 {
1702         vmcs_check16(field);
1703         __vmcs_writel(field, value);
1704 }
1705
1706 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1707 {
1708         vmcs_check32(field);
1709         __vmcs_writel(field, value);
1710 }
1711
1712 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1713 {
1714         vmcs_check64(field);
1715         __vmcs_writel(field, value);
1716 #ifndef CONFIG_X86_64
1717         asm volatile ("");
1718         __vmcs_writel(field+1, value >> 32);
1719 #endif
1720 }
1721
1722 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1723 {
1724         vmcs_checkl(field);
1725         __vmcs_writel(field, value);
1726 }
1727
1728 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1729 {
1730         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1731                          "vmcs_clear_bits does not support 64-bit fields");
1732         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1733 }
1734
1735 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1736 {
1737         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1738                          "vmcs_set_bits does not support 64-bit fields");
1739         __vmcs_writel(field, __vmcs_readl(field) | mask);
1740 }
1741
1742 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1743 {
1744         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1745 }
1746
1747 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1748 {
1749         vmcs_write32(VM_ENTRY_CONTROLS, val);
1750         vmx->vm_entry_controls_shadow = val;
1751 }
1752
1753 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1754 {
1755         if (vmx->vm_entry_controls_shadow != val)
1756                 vm_entry_controls_init(vmx, val);
1757 }
1758
1759 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1760 {
1761         return vmx->vm_entry_controls_shadow;
1762 }
1763
1764
1765 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1766 {
1767         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1768 }
1769
1770 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1771 {
1772         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1773 }
1774
1775 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1776 {
1777         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1778 }
1779
1780 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1781 {
1782         vmcs_write32(VM_EXIT_CONTROLS, val);
1783         vmx->vm_exit_controls_shadow = val;
1784 }
1785
1786 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1787 {
1788         if (vmx->vm_exit_controls_shadow != val)
1789                 vm_exit_controls_init(vmx, val);
1790 }
1791
1792 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1793 {
1794         return vmx->vm_exit_controls_shadow;
1795 }
1796
1797
1798 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1799 {
1800         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1801 }
1802
1803 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1804 {
1805         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1806 }
1807
1808 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1809 {
1810         vmx->segment_cache.bitmask = 0;
1811 }
1812
1813 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1814                                        unsigned field)
1815 {
1816         bool ret;
1817         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1818
1819         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1820                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1821                 vmx->segment_cache.bitmask = 0;
1822         }
1823         ret = vmx->segment_cache.bitmask & mask;
1824         vmx->segment_cache.bitmask |= mask;
1825         return ret;
1826 }
1827
1828 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1829 {
1830         u16 *p = &vmx->segment_cache.seg[seg].selector;
1831
1832         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1833                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1834         return *p;
1835 }
1836
1837 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1838 {
1839         ulong *p = &vmx->segment_cache.seg[seg].base;
1840
1841         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1842                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1843         return *p;
1844 }
1845
1846 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1847 {
1848         u32 *p = &vmx->segment_cache.seg[seg].limit;
1849
1850         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1851                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1852         return *p;
1853 }
1854
1855 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1856 {
1857         u32 *p = &vmx->segment_cache.seg[seg].ar;
1858
1859         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1860                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1861         return *p;
1862 }
1863
1864 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1865 {
1866         u32 eb;
1867
1868         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1869              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1870         if ((vcpu->guest_debug &
1871              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1872             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1873                 eb |= 1u << BP_VECTOR;
1874         if (to_vmx(vcpu)->rmode.vm86_active)
1875                 eb = ~0;
1876         if (enable_ept)
1877                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1878
1879         /* When we are running a nested L2 guest and L1 specified for it a
1880          * certain exception bitmap, we must trap the same exceptions and pass
1881          * them to L1. When running L2, we will only handle the exceptions
1882          * specified above if L1 did not want them.
1883          */
1884         if (is_guest_mode(vcpu))
1885                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1886
1887         vmcs_write32(EXCEPTION_BITMAP, eb);
1888 }
1889
1890 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1891                 unsigned long entry, unsigned long exit)
1892 {
1893         vm_entry_controls_clearbit(vmx, entry);
1894         vm_exit_controls_clearbit(vmx, exit);
1895 }
1896
1897 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1898 {
1899         unsigned i;
1900         struct msr_autoload *m = &vmx->msr_autoload;
1901
1902         switch (msr) {
1903         case MSR_EFER:
1904                 if (cpu_has_load_ia32_efer) {
1905                         clear_atomic_switch_msr_special(vmx,
1906                                         VM_ENTRY_LOAD_IA32_EFER,
1907                                         VM_EXIT_LOAD_IA32_EFER);
1908                         return;
1909                 }
1910                 break;
1911         case MSR_CORE_PERF_GLOBAL_CTRL:
1912                 if (cpu_has_load_perf_global_ctrl) {
1913                         clear_atomic_switch_msr_special(vmx,
1914                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1915                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1916                         return;
1917                 }
1918                 break;
1919         }
1920
1921         for (i = 0; i < m->nr; ++i)
1922                 if (m->guest[i].index == msr)
1923                         break;
1924
1925         if (i == m->nr)
1926                 return;
1927         --m->nr;
1928         m->guest[i] = m->guest[m->nr];
1929         m->host[i] = m->host[m->nr];
1930         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1931         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1932 }
1933
1934 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1935                 unsigned long entry, unsigned long exit,
1936                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1937                 u64 guest_val, u64 host_val)
1938 {
1939         vmcs_write64(guest_val_vmcs, guest_val);
1940         vmcs_write64(host_val_vmcs, host_val);
1941         vm_entry_controls_setbit(vmx, entry);
1942         vm_exit_controls_setbit(vmx, exit);
1943 }
1944
1945 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1946                                   u64 guest_val, u64 host_val)
1947 {
1948         unsigned i;
1949         struct msr_autoload *m = &vmx->msr_autoload;
1950
1951         switch (msr) {
1952         case MSR_EFER:
1953                 if (cpu_has_load_ia32_efer) {
1954                         add_atomic_switch_msr_special(vmx,
1955                                         VM_ENTRY_LOAD_IA32_EFER,
1956                                         VM_EXIT_LOAD_IA32_EFER,
1957                                         GUEST_IA32_EFER,
1958                                         HOST_IA32_EFER,
1959                                         guest_val, host_val);
1960                         return;
1961                 }
1962                 break;
1963         case MSR_CORE_PERF_GLOBAL_CTRL:
1964                 if (cpu_has_load_perf_global_ctrl) {
1965                         add_atomic_switch_msr_special(vmx,
1966                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1967                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1968                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1969                                         HOST_IA32_PERF_GLOBAL_CTRL,
1970                                         guest_val, host_val);
1971                         return;
1972                 }
1973                 break;
1974         case MSR_IA32_PEBS_ENABLE:
1975                 /* PEBS needs a quiescent period after being disabled (to write
1976                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1977                  * provide that period, so a CPU could write host's record into
1978                  * guest's memory.
1979                  */
1980                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1981         }
1982
1983         for (i = 0; i < m->nr; ++i)
1984                 if (m->guest[i].index == msr)
1985                         break;
1986
1987         if (i == NR_AUTOLOAD_MSRS) {
1988                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1989                                 "Can't add msr %x\n", msr);
1990                 return;
1991         } else if (i == m->nr) {
1992                 ++m->nr;
1993                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1994                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1995         }
1996
1997         m->guest[i].index = msr;
1998         m->guest[i].value = guest_val;
1999         m->host[i].index = msr;
2000         m->host[i].value = host_val;
2001 }
2002
2003 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2004 {
2005         u64 guest_efer = vmx->vcpu.arch.efer;
2006         u64 ignore_bits = 0;
2007
2008         if (!enable_ept) {
2009                 /*
2010                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2011                  * host CPUID is more efficient than testing guest CPUID
2012                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2013                  */
2014                 if (boot_cpu_has(X86_FEATURE_SMEP))
2015                         guest_efer |= EFER_NX;
2016                 else if (!(guest_efer & EFER_NX))
2017                         ignore_bits |= EFER_NX;
2018         }
2019
2020         /*
2021          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2022          */
2023         ignore_bits |= EFER_SCE;
2024 #ifdef CONFIG_X86_64
2025         ignore_bits |= EFER_LMA | EFER_LME;
2026         /* SCE is meaningful only in long mode on Intel */
2027         if (guest_efer & EFER_LMA)
2028                 ignore_bits &= ~(u64)EFER_SCE;
2029 #endif
2030
2031         clear_atomic_switch_msr(vmx, MSR_EFER);
2032
2033         /*
2034          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2035          * On CPUs that support "load IA32_EFER", always switch EFER
2036          * atomically, since it's faster than switching it manually.
2037          */
2038         if (cpu_has_load_ia32_efer ||
2039             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2040                 if (!(guest_efer & EFER_LMA))
2041                         guest_efer &= ~EFER_LME;
2042                 if (guest_efer != host_efer)
2043                         add_atomic_switch_msr(vmx, MSR_EFER,
2044                                               guest_efer, host_efer);
2045                 return false;
2046         } else {
2047                 guest_efer &= ~ignore_bits;
2048                 guest_efer |= host_efer & ignore_bits;
2049
2050                 vmx->guest_msrs[efer_offset].data = guest_efer;
2051                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2052
2053                 return true;
2054         }
2055 }
2056
2057 #ifdef CONFIG_X86_32
2058 /*
2059  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2060  * VMCS rather than the segment table.  KVM uses this helper to figure
2061  * out the current bases to poke them into the VMCS before entry.
2062  */
2063 static unsigned long segment_base(u16 selector)
2064 {
2065         struct desc_struct *table;
2066         unsigned long v;
2067
2068         if (!(selector & ~SEGMENT_RPL_MASK))
2069                 return 0;
2070
2071         table = get_current_gdt_ro();
2072
2073         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2074                 u16 ldt_selector = kvm_read_ldt();
2075
2076                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2077                         return 0;
2078
2079                 table = (struct desc_struct *)segment_base(ldt_selector);
2080         }
2081         v = get_desc_base(&table[selector >> 3]);
2082         return v;
2083 }
2084 #endif
2085
2086 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2087 {
2088         struct vcpu_vmx *vmx = to_vmx(vcpu);
2089         int i;
2090
2091         if (vmx->host_state.loaded)
2092                 return;
2093
2094         vmx->host_state.loaded = 1;
2095         /*
2096          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2097          * allow segment selectors with cpl > 0 or ti == 1.
2098          */
2099         vmx->host_state.ldt_sel = kvm_read_ldt();
2100         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2101         savesegment(fs, vmx->host_state.fs_sel);
2102         if (!(vmx->host_state.fs_sel & 7)) {
2103                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2104                 vmx->host_state.fs_reload_needed = 0;
2105         } else {
2106                 vmcs_write16(HOST_FS_SELECTOR, 0);
2107                 vmx->host_state.fs_reload_needed = 1;
2108         }
2109         savesegment(gs, vmx->host_state.gs_sel);
2110         if (!(vmx->host_state.gs_sel & 7))
2111                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2112         else {
2113                 vmcs_write16(HOST_GS_SELECTOR, 0);
2114                 vmx->host_state.gs_ldt_reload_needed = 1;
2115         }
2116
2117 #ifdef CONFIG_X86_64
2118         savesegment(ds, vmx->host_state.ds_sel);
2119         savesegment(es, vmx->host_state.es_sel);
2120 #endif
2121
2122 #ifdef CONFIG_X86_64
2123         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2124         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2125 #else
2126         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2127         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2128 #endif
2129
2130 #ifdef CONFIG_X86_64
2131         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2132         if (is_long_mode(&vmx->vcpu))
2133                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2134 #endif
2135         if (boot_cpu_has(X86_FEATURE_MPX))
2136                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2137         for (i = 0; i < vmx->save_nmsrs; ++i)
2138                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2139                                    vmx->guest_msrs[i].data,
2140                                    vmx->guest_msrs[i].mask);
2141 }
2142
2143 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2144 {
2145         if (!vmx->host_state.loaded)
2146                 return;
2147
2148         ++vmx->vcpu.stat.host_state_reload;
2149         vmx->host_state.loaded = 0;
2150 #ifdef CONFIG_X86_64
2151         if (is_long_mode(&vmx->vcpu))
2152                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2153 #endif
2154         if (vmx->host_state.gs_ldt_reload_needed) {
2155                 kvm_load_ldt(vmx->host_state.ldt_sel);
2156 #ifdef CONFIG_X86_64
2157                 load_gs_index(vmx->host_state.gs_sel);
2158 #else
2159                 loadsegment(gs, vmx->host_state.gs_sel);
2160 #endif
2161         }
2162         if (vmx->host_state.fs_reload_needed)
2163                 loadsegment(fs, vmx->host_state.fs_sel);
2164 #ifdef CONFIG_X86_64
2165         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2166                 loadsegment(ds, vmx->host_state.ds_sel);
2167                 loadsegment(es, vmx->host_state.es_sel);
2168         }
2169 #endif
2170         invalidate_tss_limit();
2171 #ifdef CONFIG_X86_64
2172         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2173 #endif
2174         if (vmx->host_state.msr_host_bndcfgs)
2175                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2176         load_fixmap_gdt(raw_smp_processor_id());
2177 }
2178
2179 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2180 {
2181         preempt_disable();
2182         __vmx_load_host_state(vmx);
2183         preempt_enable();
2184 }
2185
2186 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2187 {
2188         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2189         struct pi_desc old, new;
2190         unsigned int dest;
2191
2192         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2193                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2194                 !kvm_vcpu_apicv_active(vcpu))
2195                 return;
2196
2197         do {
2198                 old.control = new.control = pi_desc->control;
2199
2200                 /*
2201                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2202                  * are two possible cases:
2203                  * 1. After running 'pre_block', context switch
2204                  *    happened. For this case, 'sn' was set in
2205                  *    vmx_vcpu_put(), so we need to clear it here.
2206                  * 2. After running 'pre_block', we were blocked,
2207                  *    and woken up by some other guy. For this case,
2208                  *    we don't need to do anything, 'pi_post_block'
2209                  *    will do everything for us. However, we cannot
2210                  *    check whether it is case #1 or case #2 here
2211                  *    (maybe, not needed), so we also clear sn here,
2212                  *    I think it is not a big deal.
2213                  */
2214                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2215                         if (vcpu->cpu != cpu) {
2216                                 dest = cpu_physical_id(cpu);
2217
2218                                 if (x2apic_enabled())
2219                                         new.ndst = dest;
2220                                 else
2221                                         new.ndst = (dest << 8) & 0xFF00;
2222                         }
2223
2224                         /* set 'NV' to 'notification vector' */
2225                         new.nv = POSTED_INTR_VECTOR;
2226                 }
2227
2228                 /* Allow posting non-urgent interrupts */
2229                 new.sn = 0;
2230         } while (cmpxchg(&pi_desc->control, old.control,
2231                         new.control) != old.control);
2232 }
2233
2234 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2235 {
2236         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2237         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2238 }
2239
2240 /*
2241  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2242  * vcpu mutex is already taken.
2243  */
2244 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2245 {
2246         struct vcpu_vmx *vmx = to_vmx(vcpu);
2247         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2248
2249         if (!already_loaded) {
2250                 loaded_vmcs_clear(vmx->loaded_vmcs);
2251                 local_irq_disable();
2252                 crash_disable_local_vmclear(cpu);
2253
2254                 /*
2255                  * Read loaded_vmcs->cpu should be before fetching
2256                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2257                  * See the comments in __loaded_vmcs_clear().
2258                  */
2259                 smp_rmb();
2260
2261                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2262                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2263                 crash_enable_local_vmclear(cpu);
2264                 local_irq_enable();
2265         }
2266
2267         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2268                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2269                 vmcs_load(vmx->loaded_vmcs->vmcs);
2270         }
2271
2272         if (!already_loaded) {
2273                 void *gdt = get_current_gdt_ro();
2274                 unsigned long sysenter_esp;
2275
2276                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2277
2278                 /*
2279                  * Linux uses per-cpu TSS and GDT, so set these when switching
2280                  * processors.  See 22.2.4.
2281                  */
2282                 vmcs_writel(HOST_TR_BASE,
2283                             (unsigned long)this_cpu_ptr(&cpu_tss));
2284                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2285
2286                 /*
2287                  * VM exits change the host TR limit to 0x67 after a VM
2288                  * exit.  This is okay, since 0x67 covers everything except
2289                  * the IO bitmap and have have code to handle the IO bitmap
2290                  * being lost after a VM exit.
2291                  */
2292                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2293
2294                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2295                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2296
2297                 vmx->loaded_vmcs->cpu = cpu;
2298         }
2299
2300         /* Setup TSC multiplier */
2301         if (kvm_has_tsc_control &&
2302             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2303                 decache_tsc_multiplier(vmx);
2304
2305         vmx_vcpu_pi_load(vcpu, cpu);
2306         vmx->host_pkru = read_pkru();
2307 }
2308
2309 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2310 {
2311         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2312
2313         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2314                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2315                 !kvm_vcpu_apicv_active(vcpu))
2316                 return;
2317
2318         /* Set SN when the vCPU is preempted */
2319         if (vcpu->preempted)
2320                 pi_set_sn(pi_desc);
2321 }
2322
2323 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2324 {
2325         vmx_vcpu_pi_put(vcpu);
2326
2327         __vmx_load_host_state(to_vmx(vcpu));
2328 }
2329
2330 static bool emulation_required(struct kvm_vcpu *vcpu)
2331 {
2332         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2333 }
2334
2335 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2336
2337 /*
2338  * Return the cr0 value that a nested guest would read. This is a combination
2339  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2340  * its hypervisor (cr0_read_shadow).
2341  */
2342 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2343 {
2344         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2345                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2346 }
2347 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2348 {
2349         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2350                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2351 }
2352
2353 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2354 {
2355         unsigned long rflags, save_rflags;
2356
2357         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2358                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2359                 rflags = vmcs_readl(GUEST_RFLAGS);
2360                 if (to_vmx(vcpu)->rmode.vm86_active) {
2361                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2362                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2363                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2364                 }
2365                 to_vmx(vcpu)->rflags = rflags;
2366         }
2367         return to_vmx(vcpu)->rflags;
2368 }
2369
2370 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2371 {
2372         unsigned long old_rflags = vmx_get_rflags(vcpu);
2373
2374         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2375         to_vmx(vcpu)->rflags = rflags;
2376         if (to_vmx(vcpu)->rmode.vm86_active) {
2377                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2378                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2379         }
2380         vmcs_writel(GUEST_RFLAGS, rflags);
2381
2382         if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2383                 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2384 }
2385
2386 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2387 {
2388         return to_vmx(vcpu)->guest_pkru;
2389 }
2390
2391 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2392 {
2393         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2394         int ret = 0;
2395
2396         if (interruptibility & GUEST_INTR_STATE_STI)
2397                 ret |= KVM_X86_SHADOW_INT_STI;
2398         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2399                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2400
2401         return ret;
2402 }
2403
2404 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2405 {
2406         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2407         u32 interruptibility = interruptibility_old;
2408
2409         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2410
2411         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2412                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2413         else if (mask & KVM_X86_SHADOW_INT_STI)
2414                 interruptibility |= GUEST_INTR_STATE_STI;
2415
2416         if ((interruptibility != interruptibility_old))
2417                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2418 }
2419
2420 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2421 {
2422         unsigned long rip;
2423
2424         rip = kvm_rip_read(vcpu);
2425         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2426         kvm_rip_write(vcpu, rip);
2427
2428         /* skipping an emulated instruction also counts */
2429         vmx_set_interrupt_shadow(vcpu, 0);
2430 }
2431
2432 /*
2433  * KVM wants to inject page-faults which it got to the guest. This function
2434  * checks whether in a nested guest, we need to inject them to L1 or L2.
2435  */
2436 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu)
2437 {
2438         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2439         unsigned int nr = vcpu->arch.exception.nr;
2440
2441         if (!((vmcs12->exception_bitmap & (1u << nr)) ||
2442                 (nr == PF_VECTOR && vcpu->arch.exception.nested_apf)))
2443                 return 0;
2444
2445         if (vcpu->arch.exception.nested_apf) {
2446                 vmcs_write32(VM_EXIT_INTR_ERROR_CODE, vcpu->arch.exception.error_code);
2447                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
2448                         PF_VECTOR | INTR_TYPE_HARD_EXCEPTION |
2449                         INTR_INFO_DELIVER_CODE_MASK | INTR_INFO_VALID_MASK,
2450                         vcpu->arch.apf.nested_apf_token);
2451                 return 1;
2452         }
2453
2454         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
2455                           vmcs_read32(VM_EXIT_INTR_INFO),
2456                           vmcs_readl(EXIT_QUALIFICATION));
2457         return 1;
2458 }
2459
2460 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2461 {
2462         struct vcpu_vmx *vmx = to_vmx(vcpu);
2463         unsigned nr = vcpu->arch.exception.nr;
2464         bool has_error_code = vcpu->arch.exception.has_error_code;
2465         bool reinject = vcpu->arch.exception.reinject;
2466         u32 error_code = vcpu->arch.exception.error_code;
2467         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2468
2469         if (!reinject && is_guest_mode(vcpu) &&
2470             nested_vmx_check_exception(vcpu))
2471                 return;
2472
2473         if (has_error_code) {
2474                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2475                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2476         }
2477
2478         if (vmx->rmode.vm86_active) {
2479                 int inc_eip = 0;
2480                 if (kvm_exception_is_soft(nr))
2481                         inc_eip = vcpu->arch.event_exit_inst_len;
2482                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2483                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2484                 return;
2485         }
2486
2487         if (kvm_exception_is_soft(nr)) {
2488                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2489                              vmx->vcpu.arch.event_exit_inst_len);
2490                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2491         } else
2492                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2493
2494         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2495 }
2496
2497 static bool vmx_rdtscp_supported(void)
2498 {
2499         return cpu_has_vmx_rdtscp();
2500 }
2501
2502 static bool vmx_invpcid_supported(void)
2503 {
2504         return cpu_has_vmx_invpcid() && enable_ept;
2505 }
2506
2507 /*
2508  * Swap MSR entry in host/guest MSR entry array.
2509  */
2510 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2511 {
2512         struct shared_msr_entry tmp;
2513
2514         tmp = vmx->guest_msrs[to];
2515         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2516         vmx->guest_msrs[from] = tmp;
2517 }
2518
2519 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2520 {
2521         unsigned long *msr_bitmap;
2522
2523         if (is_guest_mode(vcpu))
2524                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2525         else if (cpu_has_secondary_exec_ctrls() &&
2526                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2527                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2528                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2529                         if (is_long_mode(vcpu))
2530                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2531                         else
2532                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2533                 } else {
2534                         if (is_long_mode(vcpu))
2535                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2536                         else
2537                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2538                 }
2539         } else {
2540                 if (is_long_mode(vcpu))
2541                         msr_bitmap = vmx_msr_bitmap_longmode;
2542                 else
2543                         msr_bitmap = vmx_msr_bitmap_legacy;
2544         }
2545
2546         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2547 }
2548
2549 /*
2550  * Set up the vmcs to automatically save and restore system
2551  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2552  * mode, as fiddling with msrs is very expensive.
2553  */
2554 static void setup_msrs(struct vcpu_vmx *vmx)
2555 {
2556         int save_nmsrs, index;
2557
2558         save_nmsrs = 0;
2559 #ifdef CONFIG_X86_64
2560         if (is_long_mode(&vmx->vcpu)) {
2561                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2562                 if (index >= 0)
2563                         move_msr_up(vmx, index, save_nmsrs++);
2564                 index = __find_msr_index(vmx, MSR_LSTAR);
2565                 if (index >= 0)
2566                         move_msr_up(vmx, index, save_nmsrs++);
2567                 index = __find_msr_index(vmx, MSR_CSTAR);
2568                 if (index >= 0)
2569                         move_msr_up(vmx, index, save_nmsrs++);
2570                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2571                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2572                         move_msr_up(vmx, index, save_nmsrs++);
2573                 /*
2574                  * MSR_STAR is only needed on long mode guests, and only
2575                  * if efer.sce is enabled.
2576                  */
2577                 index = __find_msr_index(vmx, MSR_STAR);
2578                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2579                         move_msr_up(vmx, index, save_nmsrs++);
2580         }
2581 #endif
2582         index = __find_msr_index(vmx, MSR_EFER);
2583         if (index >= 0 && update_transition_efer(vmx, index))
2584                 move_msr_up(vmx, index, save_nmsrs++);
2585
2586         vmx->save_nmsrs = save_nmsrs;
2587
2588         if (cpu_has_vmx_msr_bitmap())
2589                 vmx_set_msr_bitmap(&vmx->vcpu);
2590 }
2591
2592 /*
2593  * reads and returns guest's timestamp counter "register"
2594  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2595  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2596  */
2597 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2598 {
2599         u64 host_tsc, tsc_offset;
2600
2601         host_tsc = rdtsc();
2602         tsc_offset = vmcs_read64(TSC_OFFSET);
2603         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2604 }
2605
2606 /*
2607  * writes 'offset' into guest's timestamp counter offset register
2608  */
2609 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2610 {
2611         if (is_guest_mode(vcpu)) {
2612                 /*
2613                  * We're here if L1 chose not to trap WRMSR to TSC. According
2614                  * to the spec, this should set L1's TSC; The offset that L1
2615                  * set for L2 remains unchanged, and still needs to be added
2616                  * to the newly set TSC to get L2's TSC.
2617                  */
2618                 struct vmcs12 *vmcs12;
2619                 /* recalculate vmcs02.TSC_OFFSET: */
2620                 vmcs12 = get_vmcs12(vcpu);
2621                 vmcs_write64(TSC_OFFSET, offset +
2622                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2623                          vmcs12->tsc_offset : 0));
2624         } else {
2625                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2626                                            vmcs_read64(TSC_OFFSET), offset);
2627                 vmcs_write64(TSC_OFFSET, offset);
2628         }
2629 }
2630
2631 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2632 {
2633         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2634         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2635 }
2636
2637 /*
2638  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2639  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2640  * all guests if the "nested" module option is off, and can also be disabled
2641  * for a single guest by disabling its VMX cpuid bit.
2642  */
2643 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2644 {
2645         return nested && guest_cpuid_has_vmx(vcpu);
2646 }
2647
2648 /*
2649  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2650  * returned for the various VMX controls MSRs when nested VMX is enabled.
2651  * The same values should also be used to verify that vmcs12 control fields are
2652  * valid during nested entry from L1 to L2.
2653  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2654  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2655  * bit in the high half is on if the corresponding bit in the control field
2656  * may be on. See also vmx_control_verify().
2657  */
2658 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2659 {
2660         /*
2661          * Note that as a general rule, the high half of the MSRs (bits in
2662          * the control fields which may be 1) should be initialized by the
2663          * intersection of the underlying hardware's MSR (i.e., features which
2664          * can be supported) and the list of features we want to expose -
2665          * because they are known to be properly supported in our code.
2666          * Also, usually, the low half of the MSRs (bits which must be 1) can
2667          * be set to 0, meaning that L1 may turn off any of these bits. The
2668          * reason is that if one of these bits is necessary, it will appear
2669          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2670          * fields of vmcs01 and vmcs02, will turn these bits off - and
2671          * nested_vmx_exit_handled() will not pass related exits to L1.
2672          * These rules have exceptions below.
2673          */
2674
2675         /* pin-based controls */
2676         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2677                 vmx->nested.nested_vmx_pinbased_ctls_low,
2678                 vmx->nested.nested_vmx_pinbased_ctls_high);
2679         vmx->nested.nested_vmx_pinbased_ctls_low |=
2680                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2681         vmx->nested.nested_vmx_pinbased_ctls_high &=
2682                 PIN_BASED_EXT_INTR_MASK |
2683                 PIN_BASED_NMI_EXITING |
2684                 PIN_BASED_VIRTUAL_NMIS;
2685         vmx->nested.nested_vmx_pinbased_ctls_high |=
2686                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2687                 PIN_BASED_VMX_PREEMPTION_TIMER;
2688         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2689                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2690                         PIN_BASED_POSTED_INTR;
2691
2692         /* exit controls */
2693         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2694                 vmx->nested.nested_vmx_exit_ctls_low,
2695                 vmx->nested.nested_vmx_exit_ctls_high);
2696         vmx->nested.nested_vmx_exit_ctls_low =
2697                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2698
2699         vmx->nested.nested_vmx_exit_ctls_high &=
2700 #ifdef CONFIG_X86_64
2701                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2702 #endif
2703                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2704         vmx->nested.nested_vmx_exit_ctls_high |=
2705                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2706                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2707                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2708
2709         if (kvm_mpx_supported())
2710                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2711
2712         /* We support free control of debug control saving. */
2713         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2714
2715         /* entry controls */
2716         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2717                 vmx->nested.nested_vmx_entry_ctls_low,
2718                 vmx->nested.nested_vmx_entry_ctls_high);
2719         vmx->nested.nested_vmx_entry_ctls_low =
2720                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2721         vmx->nested.nested_vmx_entry_ctls_high &=
2722 #ifdef CONFIG_X86_64
2723                 VM_ENTRY_IA32E_MODE |
2724 #endif
2725                 VM_ENTRY_LOAD_IA32_PAT;
2726         vmx->nested.nested_vmx_entry_ctls_high |=
2727                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2728         if (kvm_mpx_supported())
2729                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2730
2731         /* We support free control of debug control loading. */
2732         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2733
2734         /* cpu-based controls */
2735         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2736                 vmx->nested.nested_vmx_procbased_ctls_low,
2737                 vmx->nested.nested_vmx_procbased_ctls_high);
2738         vmx->nested.nested_vmx_procbased_ctls_low =
2739                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2740         vmx->nested.nested_vmx_procbased_ctls_high &=
2741                 CPU_BASED_VIRTUAL_INTR_PENDING |
2742                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2743                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2744                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2745                 CPU_BASED_CR3_STORE_EXITING |
2746 #ifdef CONFIG_X86_64
2747                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2748 #endif
2749                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2750                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2751                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2752                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2753                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2754         /*
2755          * We can allow some features even when not supported by the
2756          * hardware. For example, L1 can specify an MSR bitmap - and we
2757          * can use it to avoid exits to L1 - even when L0 runs L2
2758          * without MSR bitmaps.
2759          */
2760         vmx->nested.nested_vmx_procbased_ctls_high |=
2761                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2762                 CPU_BASED_USE_MSR_BITMAPS;
2763
2764         /* We support free control of CR3 access interception. */
2765         vmx->nested.nested_vmx_procbased_ctls_low &=
2766                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2767
2768         /* secondary cpu-based controls */
2769         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2770                 vmx->nested.nested_vmx_secondary_ctls_low,
2771                 vmx->nested.nested_vmx_secondary_ctls_high);
2772         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2773         vmx->nested.nested_vmx_secondary_ctls_high &=
2774                 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
2775                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2776                 SECONDARY_EXEC_RDTSCP |
2777                 SECONDARY_EXEC_DESC |
2778                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2779                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2780                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2781                 SECONDARY_EXEC_WBINVD_EXITING |
2782                 SECONDARY_EXEC_XSAVES;
2783
2784         if (enable_ept) {
2785                 /* nested EPT: emulate EPT also to L1 */
2786                 vmx->nested.nested_vmx_secondary_ctls_high |=
2787                         SECONDARY_EXEC_ENABLE_EPT;
2788                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2789                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2790                 if (cpu_has_vmx_ept_execute_only())
2791                         vmx->nested.nested_vmx_ept_caps |=
2792                                 VMX_EPT_EXECUTE_ONLY_BIT;
2793                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2794                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2795                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2796                         VMX_EPT_1GB_PAGE_BIT;
2797                 if (enable_ept_ad_bits) {
2798                         vmx->nested.nested_vmx_secondary_ctls_high |=
2799                                 SECONDARY_EXEC_ENABLE_PML;
2800                         vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2801                 }
2802         } else
2803                 vmx->nested.nested_vmx_ept_caps = 0;
2804
2805         /*
2806          * Old versions of KVM use the single-context version without
2807          * checking for support, so declare that it is supported even
2808          * though it is treated as global context.  The alternative is
2809          * not failing the single-context invvpid, and it is worse.
2810          */
2811         if (enable_vpid) {
2812                 vmx->nested.nested_vmx_secondary_ctls_high |=
2813                         SECONDARY_EXEC_ENABLE_VPID;
2814                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2815                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2816         } else
2817                 vmx->nested.nested_vmx_vpid_caps = 0;
2818
2819         if (enable_unrestricted_guest)
2820                 vmx->nested.nested_vmx_secondary_ctls_high |=
2821                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2822
2823         /* miscellaneous data */
2824         rdmsr(MSR_IA32_VMX_MISC,
2825                 vmx->nested.nested_vmx_misc_low,
2826                 vmx->nested.nested_vmx_misc_high);
2827         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2828         vmx->nested.nested_vmx_misc_low |=
2829                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2830                 VMX_MISC_ACTIVITY_HLT;
2831         vmx->nested.nested_vmx_misc_high = 0;
2832
2833         /*
2834          * This MSR reports some information about VMX support. We
2835          * should return information about the VMX we emulate for the
2836          * guest, and the VMCS structure we give it - not about the
2837          * VMX support of the underlying hardware.
2838          */
2839         vmx->nested.nested_vmx_basic =
2840                 VMCS12_REVISION |
2841                 VMX_BASIC_TRUE_CTLS |
2842                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2843                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2844
2845         if (cpu_has_vmx_basic_inout())
2846                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2847
2848         /*
2849          * These MSRs specify bits which the guest must keep fixed on
2850          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2851          * We picked the standard core2 setting.
2852          */
2853 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2854 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2855         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2856         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2857
2858         /* These MSRs specify bits which the guest must keep fixed off. */
2859         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2860         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2861
2862         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2863         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2864 }
2865
2866 /*
2867  * if fixed0[i] == 1: val[i] must be 1
2868  * if fixed1[i] == 0: val[i] must be 0
2869  */
2870 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2871 {
2872         return ((val & fixed1) | fixed0) == val;
2873 }
2874
2875 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2876 {
2877         return fixed_bits_valid(control, low, high);
2878 }
2879
2880 static inline u64 vmx_control_msr(u32 low, u32 high)
2881 {
2882         return low | ((u64)high << 32);
2883 }
2884
2885 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2886 {
2887         superset &= mask;
2888         subset &= mask;
2889
2890         return (superset | subset) == superset;
2891 }
2892
2893 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2894 {
2895         const u64 feature_and_reserved =
2896                 /* feature (except bit 48; see below) */
2897                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2898                 /* reserved */
2899                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2900         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2901
2902         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2903                 return -EINVAL;
2904
2905         /*
2906          * KVM does not emulate a version of VMX that constrains physical
2907          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2908          */
2909         if (data & BIT_ULL(48))
2910                 return -EINVAL;
2911
2912         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2913             vmx_basic_vmcs_revision_id(data))
2914                 return -EINVAL;
2915
2916         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2917                 return -EINVAL;
2918
2919         vmx->nested.nested_vmx_basic = data;
2920         return 0;
2921 }
2922
2923 static int
2924 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2925 {
2926         u64 supported;
2927         u32 *lowp, *highp;
2928
2929         switch (msr_index) {
2930         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2931                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2932                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2933                 break;
2934         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2935                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2936                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2937                 break;
2938         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2939                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2940                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2941                 break;
2942         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2943                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2944                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2945                 break;
2946         case MSR_IA32_VMX_PROCBASED_CTLS2:
2947                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2948                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2949                 break;
2950         default:
2951                 BUG();
2952         }
2953
2954         supported = vmx_control_msr(*lowp, *highp);
2955
2956         /* Check must-be-1 bits are still 1. */
2957         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2958                 return -EINVAL;
2959
2960         /* Check must-be-0 bits are still 0. */
2961         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2962                 return -EINVAL;
2963
2964         *lowp = data;
2965         *highp = data >> 32;
2966         return 0;
2967 }
2968
2969 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2970 {
2971         const u64 feature_and_reserved_bits =
2972                 /* feature */
2973                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2974                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2975                 /* reserved */
2976                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2977         u64 vmx_misc;
2978
2979         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2980                                    vmx->nested.nested_vmx_misc_high);
2981
2982         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2983                 return -EINVAL;
2984
2985         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2986              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2987             vmx_misc_preemption_timer_rate(data) !=
2988             vmx_misc_preemption_timer_rate(vmx_misc))
2989                 return -EINVAL;
2990
2991         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2992                 return -EINVAL;
2993
2994         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2995                 return -EINVAL;
2996
2997         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2998                 return -EINVAL;
2999
3000         vmx->nested.nested_vmx_misc_low = data;
3001         vmx->nested.nested_vmx_misc_high = data >> 32;
3002         return 0;
3003 }
3004
3005 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3006 {
3007         u64 vmx_ept_vpid_cap;
3008
3009         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3010                                            vmx->nested.nested_vmx_vpid_caps);
3011
3012         /* Every bit is either reserved or a feature bit. */
3013         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3014                 return -EINVAL;
3015
3016         vmx->nested.nested_vmx_ept_caps = data;
3017         vmx->nested.nested_vmx_vpid_caps = data >> 32;
3018         return 0;
3019 }
3020
3021 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3022 {
3023         u64 *msr;
3024
3025         switch (msr_index) {
3026         case MSR_IA32_VMX_CR0_FIXED0:
3027                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3028                 break;
3029         case MSR_IA32_VMX_CR4_FIXED0:
3030                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3031                 break;
3032         default:
3033                 BUG();
3034         }
3035
3036         /*
3037          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3038          * must be 1 in the restored value.
3039          */
3040         if (!is_bitwise_subset(data, *msr, -1ULL))
3041                 return -EINVAL;
3042
3043         *msr = data;
3044         return 0;
3045 }
3046
3047 /*
3048  * Called when userspace is restoring VMX MSRs.
3049  *
3050  * Returns 0 on success, non-0 otherwise.
3051  */
3052 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3053 {
3054         struct vcpu_vmx *vmx = to_vmx(vcpu);
3055
3056         switch (msr_index) {
3057         case MSR_IA32_VMX_BASIC:
3058                 return vmx_restore_vmx_basic(vmx, data);
3059         case MSR_IA32_VMX_PINBASED_CTLS:
3060         case MSR_IA32_VMX_PROCBASED_CTLS:
3061         case MSR_IA32_VMX_EXIT_CTLS:
3062         case MSR_IA32_VMX_ENTRY_CTLS:
3063                 /*
3064                  * The "non-true" VMX capability MSRs are generated from the
3065                  * "true" MSRs, so we do not support restoring them directly.
3066                  *
3067                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3068                  * should restore the "true" MSRs with the must-be-1 bits
3069                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3070                  * DEFAULT SETTINGS".
3071                  */
3072                 return -EINVAL;
3073         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3074         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3075         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3076         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3077         case MSR_IA32_VMX_PROCBASED_CTLS2:
3078                 return vmx_restore_control_msr(vmx, msr_index, data);
3079         case MSR_IA32_VMX_MISC:
3080                 return vmx_restore_vmx_misc(vmx, data);
3081         case MSR_IA32_VMX_CR0_FIXED0:
3082         case MSR_IA32_VMX_CR4_FIXED0:
3083                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3084         case MSR_IA32_VMX_CR0_FIXED1:
3085         case MSR_IA32_VMX_CR4_FIXED1:
3086                 /*
3087                  * These MSRs are generated based on the vCPU's CPUID, so we
3088                  * do not support restoring them directly.
3089                  */
3090                 return -EINVAL;
3091         case MSR_IA32_VMX_EPT_VPID_CAP:
3092                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3093         case MSR_IA32_VMX_VMCS_ENUM:
3094                 vmx->nested.nested_vmx_vmcs_enum = data;
3095                 return 0;
3096         default:
3097                 /*
3098                  * The rest of the VMX capability MSRs do not support restore.
3099                  */
3100                 return -EINVAL;
3101         }
3102 }
3103
3104 /* Returns 0 on success, non-0 otherwise. */
3105 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3106 {
3107         struct vcpu_vmx *vmx = to_vmx(vcpu);
3108
3109         switch (msr_index) {
3110         case MSR_IA32_VMX_BASIC:
3111                 *pdata = vmx->nested.nested_vmx_basic;
3112                 break;
3113         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3114         case MSR_IA32_VMX_PINBASED_CTLS:
3115                 *pdata = vmx_control_msr(
3116                         vmx->nested.nested_vmx_pinbased_ctls_low,
3117                         vmx->nested.nested_vmx_pinbased_ctls_high);
3118                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3119                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3120                 break;
3121         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3122         case MSR_IA32_VMX_PROCBASED_CTLS:
3123                 *pdata = vmx_control_msr(
3124                         vmx->nested.nested_vmx_procbased_ctls_low,
3125                         vmx->nested.nested_vmx_procbased_ctls_high);
3126                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3127                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3128                 break;
3129         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3130         case MSR_IA32_VMX_EXIT_CTLS:
3131                 *pdata = vmx_control_msr(
3132                         vmx->nested.nested_vmx_exit_ctls_low,
3133                         vmx->nested.nested_vmx_exit_ctls_high);
3134                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3135                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3136                 break;
3137         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3138         case MSR_IA32_VMX_ENTRY_CTLS:
3139                 *pdata = vmx_control_msr(
3140                         vmx->nested.nested_vmx_entry_ctls_low,
3141                         vmx->nested.nested_vmx_entry_ctls_high);
3142                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3143                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3144                 break;
3145         case MSR_IA32_VMX_MISC:
3146                 *pdata = vmx_control_msr(
3147                         vmx->nested.nested_vmx_misc_low,
3148                         vmx->nested.nested_vmx_misc_high);
3149                 break;
3150         case MSR_IA32_VMX_CR0_FIXED0:
3151                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3152                 break;
3153         case MSR_IA32_VMX_CR0_FIXED1:
3154                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3155                 break;
3156         case MSR_IA32_VMX_CR4_FIXED0:
3157                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3158                 break;
3159         case MSR_IA32_VMX_CR4_FIXED1:
3160                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3161                 break;
3162         case MSR_IA32_VMX_VMCS_ENUM:
3163                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3164                 break;
3165         case MSR_IA32_VMX_PROCBASED_CTLS2:
3166                 *pdata = vmx_control_msr(
3167                         vmx->nested.nested_vmx_secondary_ctls_low,
3168                         vmx->nested.nested_vmx_secondary_ctls_high);
3169                 break;
3170         case MSR_IA32_VMX_EPT_VPID_CAP:
3171                 *pdata = vmx->nested.nested_vmx_ept_caps |
3172                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3173                 break;
3174         default:
3175                 return 1;
3176         }
3177
3178         return 0;
3179 }
3180
3181 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3182                                                  uint64_t val)
3183 {
3184         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3185
3186         return !(val & ~valid_bits);
3187 }
3188
3189 /*
3190  * Reads an msr value (of 'msr_index') into 'pdata'.
3191  * Returns 0 on success, non-0 otherwise.
3192  * Assumes vcpu_load() was already called.
3193  */
3194 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3195 {
3196         struct shared_msr_entry *msr;
3197
3198         switch (msr_info->index) {
3199 #ifdef CONFIG_X86_64
3200         case MSR_FS_BASE:
3201                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3202                 break;
3203         case MSR_GS_BASE:
3204                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3205                 break;
3206         case MSR_KERNEL_GS_BASE:
3207                 vmx_load_host_state(to_vmx(vcpu));
3208                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3209                 break;
3210 #endif
3211         case MSR_EFER:
3212                 return kvm_get_msr_common(vcpu, msr_info);
3213         case MSR_IA32_TSC:
3214                 msr_info->data = guest_read_tsc(vcpu);
3215                 break;
3216         case MSR_IA32_SYSENTER_CS:
3217                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3218                 break;
3219         case MSR_IA32_SYSENTER_EIP:
3220                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3221                 break;
3222         case MSR_IA32_SYSENTER_ESP:
3223                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3224                 break;
3225         case MSR_IA32_BNDCFGS:
3226                 if (!kvm_mpx_supported() ||
3227                     (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3228                         return 1;
3229                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3230                 break;
3231         case MSR_IA32_MCG_EXT_CTL:
3232                 if (!msr_info->host_initiated &&
3233                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3234                       FEATURE_CONTROL_LMCE))
3235                         return 1;
3236                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3237                 break;
3238         case MSR_IA32_FEATURE_CONTROL:
3239                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3240                 break;
3241         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3242                 if (!nested_vmx_allowed(vcpu))
3243                         return 1;
3244                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3245         case MSR_IA32_XSS:
3246                 if (!vmx_xsaves_supported())
3247                         return 1;
3248                 msr_info->data = vcpu->arch.ia32_xss;
3249                 break;
3250         case MSR_TSC_AUX:
3251                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3252                         return 1;
3253                 /* Otherwise falls through */
3254         default:
3255                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3256                 if (msr) {
3257                         msr_info->data = msr->data;
3258                         break;
3259                 }
3260                 return kvm_get_msr_common(vcpu, msr_info);
3261         }
3262
3263         return 0;
3264 }
3265
3266 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3267
3268 /*
3269  * Writes msr value into into the appropriate "register".
3270  * Returns 0 on success, non-0 otherwise.
3271  * Assumes vcpu_load() was already called.
3272  */
3273 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3274 {
3275         struct vcpu_vmx *vmx = to_vmx(vcpu);
3276         struct shared_msr_entry *msr;
3277         int ret = 0;
3278         u32 msr_index = msr_info->index;
3279         u64 data = msr_info->data;
3280
3281         switch (msr_index) {
3282         case MSR_EFER:
3283                 ret = kvm_set_msr_common(vcpu, msr_info);
3284                 break;
3285 #ifdef CONFIG_X86_64
3286         case MSR_FS_BASE:
3287                 vmx_segment_cache_clear(vmx);
3288                 vmcs_writel(GUEST_FS_BASE, data);
3289                 break;
3290         case MSR_GS_BASE:
3291                 vmx_segment_cache_clear(vmx);
3292                 vmcs_writel(GUEST_GS_BASE, data);
3293                 break;
3294         case MSR_KERNEL_GS_BASE:
3295                 vmx_load_host_state(vmx);
3296                 vmx->msr_guest_kernel_gs_base = data;
3297                 break;
3298 #endif
3299         case MSR_IA32_SYSENTER_CS:
3300                 vmcs_write32(GUEST_SYSENTER_CS, data);
3301                 break;
3302         case MSR_IA32_SYSENTER_EIP:
3303                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3304                 break;
3305         case MSR_IA32_SYSENTER_ESP:
3306                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3307                 break;
3308         case MSR_IA32_BNDCFGS:
3309                 if (!kvm_mpx_supported() ||
3310                     (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3311                         return 1;
3312                 if (is_noncanonical_address(data & PAGE_MASK) ||
3313                     (data & MSR_IA32_BNDCFGS_RSVD))
3314                         return 1;
3315                 vmcs_write64(GUEST_BNDCFGS, data);
3316                 break;
3317         case MSR_IA32_TSC:
3318                 kvm_write_tsc(vcpu, msr_info);
3319                 break;
3320         case MSR_IA32_CR_PAT:
3321                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3322                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3323                                 return 1;
3324                         vmcs_write64(GUEST_IA32_PAT, data);
3325                         vcpu->arch.pat = data;
3326                         break;
3327                 }
3328                 ret = kvm_set_msr_common(vcpu, msr_info);
3329                 break;
3330         case MSR_IA32_TSC_ADJUST:
3331                 ret = kvm_set_msr_common(vcpu, msr_info);
3332                 break;
3333         case MSR_IA32_MCG_EXT_CTL:
3334                 if ((!msr_info->host_initiated &&
3335                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3336                        FEATURE_CONTROL_LMCE)) ||
3337                     (data & ~MCG_EXT_CTL_LMCE_EN))
3338                         return 1;
3339                 vcpu->arch.mcg_ext_ctl = data;
3340                 break;
3341         case MSR_IA32_FEATURE_CONTROL:
3342                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3343                     (to_vmx(vcpu)->msr_ia32_feature_control &
3344                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3345                         return 1;
3346                 vmx->msr_ia32_feature_control = data;
3347                 if (msr_info->host_initiated && data == 0)
3348                         vmx_leave_nested(vcpu);
3349                 break;
3350         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3351                 if (!msr_info->host_initiated)
3352                         return 1; /* they are read-only */
3353                 if (!nested_vmx_allowed(vcpu))
3354                         return 1;
3355                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3356         case MSR_IA32_XSS:
3357                 if (!vmx_xsaves_supported())
3358                         return 1;
3359                 /*
3360                  * The only supported bit as of Skylake is bit 8, but
3361                  * it is not supported on KVM.
3362                  */
3363                 if (data != 0)
3364                         return 1;
3365                 vcpu->arch.ia32_xss = data;
3366                 if (vcpu->arch.ia32_xss != host_xss)
3367                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3368                                 vcpu->arch.ia32_xss, host_xss);
3369                 else
3370                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3371                 break;
3372         case MSR_TSC_AUX:
3373                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3374                         return 1;
3375                 /* Check reserved bit, higher 32 bits should be zero */
3376                 if ((data >> 32) != 0)
3377                         return 1;
3378                 /* Otherwise falls through */
3379         default:
3380                 msr = find_msr_entry(vmx, msr_index);
3381                 if (msr) {
3382                         u64 old_msr_data = msr->data;
3383                         msr->data = data;
3384                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3385                                 preempt_disable();
3386                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3387                                                          msr->mask);
3388                                 preempt_enable();
3389                                 if (ret)
3390                                         msr->data = old_msr_data;
3391                         }
3392                         break;
3393                 }
3394                 ret = kvm_set_msr_common(vcpu, msr_info);
3395         }
3396
3397         return ret;
3398 }
3399
3400 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3401 {
3402         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3403         switch (reg) {
3404         case VCPU_REGS_RSP:
3405                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3406                 break;
3407         case VCPU_REGS_RIP:
3408                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3409                 break;
3410         case VCPU_EXREG_PDPTR:
3411                 if (enable_ept)
3412                         ept_save_pdptrs(vcpu);
3413                 break;
3414         default:
3415                 break;
3416         }
3417 }
3418
3419 static __init int cpu_has_kvm_support(void)
3420 {
3421         return cpu_has_vmx();
3422 }
3423
3424 static __init int vmx_disabled_by_bios(void)
3425 {
3426         u64 msr;
3427
3428         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3429         if (msr & FEATURE_CONTROL_LOCKED) {
3430                 /* launched w/ TXT and VMX disabled */
3431                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3432                         && tboot_enabled())
3433                         return 1;
3434                 /* launched w/o TXT and VMX only enabled w/ TXT */
3435                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3436                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3437                         && !tboot_enabled()) {
3438                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3439                                 "activate TXT before enabling KVM\n");
3440                         return 1;
3441                 }
3442                 /* launched w/o TXT and VMX disabled */
3443                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3444                         && !tboot_enabled())
3445                         return 1;
3446         }
3447
3448         return 0;
3449 }
3450
3451 static void kvm_cpu_vmxon(u64 addr)
3452 {
3453         cr4_set_bits(X86_CR4_VMXE);
3454         intel_pt_handle_vmx(1);
3455
3456         asm volatile (ASM_VMX_VMXON_RAX
3457                         : : "a"(&addr), "m"(addr)
3458                         : "memory", "cc");
3459 }
3460
3461 static int hardware_enable(void)
3462 {
3463         int cpu = raw_smp_processor_id();
3464         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3465         u64 old, test_bits;
3466
3467         if (cr4_read_shadow() & X86_CR4_VMXE)
3468                 return -EBUSY;
3469
3470         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3471         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3472         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3473
3474         /*
3475          * Now we can enable the vmclear operation in kdump
3476          * since the loaded_vmcss_on_cpu list on this cpu
3477          * has been initialized.
3478          *
3479          * Though the cpu is not in VMX operation now, there
3480          * is no problem to enable the vmclear operation
3481          * for the loaded_vmcss_on_cpu list is empty!
3482          */
3483         crash_enable_local_vmclear(cpu);
3484
3485         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3486
3487         test_bits = FEATURE_CONTROL_LOCKED;
3488         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3489         if (tboot_enabled())
3490                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3491
3492         if ((old & test_bits) != test_bits) {
3493                 /* enable and lock */
3494                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3495         }
3496         kvm_cpu_vmxon(phys_addr);
3497         ept_sync_global();
3498
3499         return 0;
3500 }
3501
3502 static void vmclear_local_loaded_vmcss(void)
3503 {
3504         int cpu = raw_smp_processor_id();
3505         struct loaded_vmcs *v, *n;
3506
3507         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3508                                  loaded_vmcss_on_cpu_link)
3509                 __loaded_vmcs_clear(v);
3510 }
3511
3512
3513 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3514  * tricks.
3515  */
3516 static void kvm_cpu_vmxoff(void)
3517 {
3518         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3519
3520         intel_pt_handle_vmx(0);
3521         cr4_clear_bits(X86_CR4_VMXE);
3522 }
3523
3524 static void hardware_disable(void)
3525 {
3526         vmclear_local_loaded_vmcss();
3527         kvm_cpu_vmxoff();
3528 }
3529
3530 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3531                                       u32 msr, u32 *result)
3532 {
3533         u32 vmx_msr_low, vmx_msr_high;
3534         u32 ctl = ctl_min | ctl_opt;
3535
3536         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3537
3538         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3539         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3540
3541         /* Ensure minimum (required) set of control bits are supported. */
3542         if (ctl_min & ~ctl)
3543                 return -EIO;
3544
3545         *result = ctl;
3546         return 0;
3547 }
3548
3549 static __init bool allow_1_setting(u32 msr, u32 ctl)
3550 {
3551         u32 vmx_msr_low, vmx_msr_high;
3552
3553         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3554         return vmx_msr_high & ctl;
3555 }
3556
3557 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3558 {
3559         u32 vmx_msr_low, vmx_msr_high;
3560         u32 min, opt, min2, opt2;
3561         u32 _pin_based_exec_control = 0;
3562         u32 _cpu_based_exec_control = 0;
3563         u32 _cpu_based_2nd_exec_control = 0;
3564         u32 _vmexit_control = 0;
3565         u32 _vmentry_control = 0;
3566
3567         min = CPU_BASED_HLT_EXITING |
3568 #ifdef CONFIG_X86_64
3569               CPU_BASED_CR8_LOAD_EXITING |
3570               CPU_BASED_CR8_STORE_EXITING |
3571 #endif
3572               CPU_BASED_CR3_LOAD_EXITING |
3573               CPU_BASED_CR3_STORE_EXITING |
3574               CPU_BASED_USE_IO_BITMAPS |
3575               CPU_BASED_MOV_DR_EXITING |
3576               CPU_BASED_USE_TSC_OFFSETING |
3577               CPU_BASED_INVLPG_EXITING |
3578               CPU_BASED_RDPMC_EXITING;
3579
3580         if (!kvm_mwait_in_guest())
3581                 min |= CPU_BASED_MWAIT_EXITING |
3582                         CPU_BASED_MONITOR_EXITING;
3583
3584         opt = CPU_BASED_TPR_SHADOW |
3585               CPU_BASED_USE_MSR_BITMAPS |
3586               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3587         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3588                                 &_cpu_based_exec_control) < 0)
3589                 return -EIO;
3590 #ifdef CONFIG_X86_64
3591         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3592                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3593                                            ~CPU_BASED_CR8_STORE_EXITING;
3594 #endif
3595         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3596                 min2 = 0;
3597                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3598                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3599                         SECONDARY_EXEC_WBINVD_EXITING |
3600                         SECONDARY_EXEC_ENABLE_VPID |
3601                         SECONDARY_EXEC_ENABLE_EPT |
3602                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3603                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3604                         SECONDARY_EXEC_RDTSCP |
3605                         SECONDARY_EXEC_ENABLE_INVPCID |
3606                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3607                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3608                         SECONDARY_EXEC_SHADOW_VMCS |
3609                         SECONDARY_EXEC_XSAVES |
3610                         SECONDARY_EXEC_ENABLE_PML |
3611                         SECONDARY_EXEC_TSC_SCALING;
3612                 if (adjust_vmx_controls(min2, opt2,
3613                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3614                                         &_cpu_based_2nd_exec_control) < 0)
3615                         return -EIO;
3616         }
3617 #ifndef CONFIG_X86_64
3618         if (!(_cpu_based_2nd_exec_control &
3619                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3620                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3621 #endif
3622
3623         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3624                 _cpu_based_2nd_exec_control &= ~(
3625                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3626                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3627                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3628
3629         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3630                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3631                    enabled */
3632                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3633                                              CPU_BASED_CR3_STORE_EXITING |
3634                                              CPU_BASED_INVLPG_EXITING);
3635                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3636                       vmx_capability.ept, vmx_capability.vpid);
3637         }
3638
3639         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3640 #ifdef CONFIG_X86_64
3641         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3642 #endif
3643         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3644                 VM_EXIT_CLEAR_BNDCFGS;
3645         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3646                                 &_vmexit_control) < 0)
3647                 return -EIO;
3648
3649         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3650                 PIN_BASED_VIRTUAL_NMIS;
3651         opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3652         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3653                                 &_pin_based_exec_control) < 0)
3654                 return -EIO;
3655
3656         if (cpu_has_broken_vmx_preemption_timer())
3657                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3658         if (!(_cpu_based_2nd_exec_control &
3659                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3660                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3661
3662         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3663         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3664         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3665                                 &_vmentry_control) < 0)
3666                 return -EIO;
3667
3668         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3669
3670         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3671         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3672                 return -EIO;
3673
3674 #ifdef CONFIG_X86_64
3675         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3676         if (vmx_msr_high & (1u<<16))
3677                 return -EIO;
3678 #endif
3679
3680         /* Require Write-Back (WB) memory type for VMCS accesses. */
3681         if (((vmx_msr_high >> 18) & 15) != 6)
3682                 return -EIO;
3683
3684         vmcs_conf->size = vmx_msr_high & 0x1fff;
3685         vmcs_conf->order = get_order(vmcs_conf->size);
3686         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3687         vmcs_conf->revision_id = vmx_msr_low;
3688
3689         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3690         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3691         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3692         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3693         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3694
3695         cpu_has_load_ia32_efer =
3696                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3697                                 VM_ENTRY_LOAD_IA32_EFER)
3698                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3699                                    VM_EXIT_LOAD_IA32_EFER);
3700
3701         cpu_has_load_perf_global_ctrl =
3702                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3703                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3704                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3705                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3706
3707         /*
3708          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3709          * but due to errata below it can't be used. Workaround is to use
3710          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3711          *
3712          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3713          *
3714          * AAK155             (model 26)
3715          * AAP115             (model 30)
3716          * AAT100             (model 37)
3717          * BC86,AAY89,BD102   (model 44)
3718          * BA97               (model 46)
3719          *
3720          */
3721         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3722                 switch (boot_cpu_data.x86_model) {
3723                 case 26:
3724                 case 30:
3725                 case 37:
3726                 case 44:
3727                 case 46:
3728                         cpu_has_load_perf_global_ctrl = false;
3729                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3730                                         "does not work properly. Using workaround\n");
3731                         break;
3732                 default:
3733                         break;
3734                 }
3735         }
3736
3737         if (boot_cpu_has(X86_FEATURE_XSAVES))
3738                 rdmsrl(MSR_IA32_XSS, host_xss);
3739
3740         return 0;
3741 }
3742
3743 static struct vmcs *alloc_vmcs_cpu(int cpu)
3744 {
3745         int node = cpu_to_node(cpu);
3746         struct page *pages;
3747         struct vmcs *vmcs;
3748
3749         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3750         if (!pages)
3751                 return NULL;
3752         vmcs = page_address(pages);
3753         memset(vmcs, 0, vmcs_config.size);
3754         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3755         return vmcs;
3756 }
3757
3758 static struct vmcs *alloc_vmcs(void)
3759 {
3760         return alloc_vmcs_cpu(raw_smp_processor_id());
3761 }
3762
3763 static void free_vmcs(struct vmcs *vmcs)
3764 {
3765         free_pages((unsigned long)vmcs, vmcs_config.order);
3766 }
3767
3768 /*
3769  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3770  */
3771 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3772 {
3773         if (!loaded_vmcs->vmcs)
3774                 return;
3775         loaded_vmcs_clear(loaded_vmcs);
3776         free_vmcs(loaded_vmcs->vmcs);
3777         loaded_vmcs->vmcs = NULL;
3778         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3779 }
3780
3781 static void free_kvm_area(void)
3782 {
3783         int cpu;
3784
3785         for_each_possible_cpu(cpu) {
3786                 free_vmcs(per_cpu(vmxarea, cpu));
3787                 per_cpu(vmxarea, cpu) = NULL;
3788         }
3789 }
3790
3791 enum vmcs_field_type {
3792         VMCS_FIELD_TYPE_U16 = 0,
3793         VMCS_FIELD_TYPE_U64 = 1,
3794         VMCS_FIELD_TYPE_U32 = 2,
3795         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
3796 };
3797
3798 static inline int vmcs_field_type(unsigned long field)
3799 {
3800         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
3801                 return VMCS_FIELD_TYPE_U32;
3802         return (field >> 13) & 0x3 ;
3803 }
3804
3805 static inline int vmcs_field_readonly(unsigned long field)
3806 {
3807         return (((field >> 10) & 0x3) == 1);
3808 }
3809
3810 static void init_vmcs_shadow_fields(void)
3811 {
3812         int i, j;
3813
3814         /* No checks for read only fields yet */
3815
3816         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3817                 switch (shadow_read_write_fields[i]) {
3818                 case GUEST_BNDCFGS:
3819                         if (!kvm_mpx_supported())
3820                                 continue;
3821                         break;
3822                 default:
3823                         break;
3824                 }
3825
3826                 if (j < i)
3827                         shadow_read_write_fields[j] =
3828                                 shadow_read_write_fields[i];
3829                 j++;
3830         }
3831         max_shadow_read_write_fields = j;
3832
3833         /* shadowed fields guest access without vmexit */
3834         for (i = 0; i < max_shadow_read_write_fields; i++) {
3835                 unsigned long field = shadow_read_write_fields[i];
3836
3837                 clear_bit(field, vmx_vmwrite_bitmap);
3838                 clear_bit(field, vmx_vmread_bitmap);
3839                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64) {
3840                         clear_bit(field + 1, vmx_vmwrite_bitmap);
3841                         clear_bit(field + 1, vmx_vmread_bitmap);
3842                 }
3843         }
3844         for (i = 0; i < max_shadow_read_only_fields; i++) {
3845                 unsigned long field = shadow_read_only_fields[i];
3846
3847                 clear_bit(field, vmx_vmread_bitmap);
3848                 if (vmcs_field_type(field) == VMCS_FIELD_TYPE_U64)
3849                         clear_bit(field + 1, vmx_vmread_bitmap);
3850         }
3851 }
3852
3853 static __init int alloc_kvm_area(void)
3854 {
3855         int cpu;
3856
3857         for_each_possible_cpu(cpu) {
3858                 struct vmcs *vmcs;
3859
3860                 vmcs = alloc_vmcs_cpu(cpu);
3861                 if (!vmcs) {
3862                         free_kvm_area();
3863                         return -ENOMEM;
3864                 }
3865
3866                 per_cpu(vmxarea, cpu) = vmcs;
3867         }
3868         return 0;
3869 }
3870
3871 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3872                 struct kvm_segment *save)
3873 {
3874         if (!emulate_invalid_guest_state) {
3875                 /*
3876                  * CS and SS RPL should be equal during guest entry according
3877                  * to VMX spec, but in reality it is not always so. Since vcpu
3878                  * is in the middle of the transition from real mode to
3879                  * protected mode it is safe to assume that RPL 0 is a good
3880                  * default value.
3881                  */
3882                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3883                         save->selector &= ~SEGMENT_RPL_MASK;
3884                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3885                 save->s = 1;
3886         }
3887         vmx_set_segment(vcpu, save, seg);
3888 }
3889
3890 static void enter_pmode(struct kvm_vcpu *vcpu)
3891 {
3892         unsigned long flags;
3893         struct vcpu_vmx *vmx = to_vmx(vcpu);
3894
3895         /*
3896          * Update real mode segment cache. It may be not up-to-date if sement
3897          * register was written while vcpu was in a guest mode.
3898          */
3899         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3900         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3901         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3902         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3903         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3904         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3905
3906         vmx->rmode.vm86_active = 0;
3907
3908         vmx_segment_cache_clear(vmx);
3909
3910         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3911
3912         flags = vmcs_readl(GUEST_RFLAGS);
3913         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3914         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3915         vmcs_writel(GUEST_RFLAGS, flags);
3916
3917         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3918                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3919
3920         update_exception_bitmap(vcpu);
3921
3922         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3923         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3924         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3925         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3926         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3927         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3928 }
3929
3930 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3931 {
3932         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3933         struct kvm_segment var = *save;
3934
3935         var.dpl = 0x3;
3936         if (seg == VCPU_SREG_CS)
3937                 var.type = 0x3;
3938
3939         if (!emulate_invalid_guest_state) {
3940                 var.selector = var.base >> 4;
3941                 var.base = var.base & 0xffff0;
3942                 var.limit = 0xffff;
3943                 var.g = 0;
3944                 var.db = 0;
3945                 var.present = 1;
3946                 var.s = 1;
3947                 var.l = 0;
3948                 var.unusable = 0;
3949                 var.type = 0x3;
3950                 var.avl = 0;
3951                 if (save->base & 0xf)
3952                         printk_once(KERN_WARNING "kvm: segment base is not "
3953                                         "paragraph aligned when entering "
3954                                         "protected mode (seg=%d)", seg);
3955         }
3956
3957         vmcs_write16(sf->selector, var.selector);
3958         vmcs_writel(sf->base, var.base);
3959         vmcs_write32(sf->limit, var.limit);
3960         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3961 }
3962
3963 static void enter_rmode(struct kvm_vcpu *vcpu)
3964 {
3965         unsigned long flags;
3966         struct vcpu_vmx *vmx = to_vmx(vcpu);
3967
3968         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3969         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3970         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3971         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3972         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3973         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3974         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3975
3976         vmx->rmode.vm86_active = 1;
3977
3978         /*
3979          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3980          * vcpu. Warn the user that an update is overdue.
3981          */
3982         if (!vcpu->kvm->arch.tss_addr)
3983                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3984                              "called before entering vcpu\n");
3985
3986         vmx_segment_cache_clear(vmx);
3987
3988         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3989         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3990         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3991
3992         flags = vmcs_readl(GUEST_RFLAGS);
3993         vmx->rmode.save_rflags = flags;
3994
3995         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3996
3997         vmcs_writel(GUEST_RFLAGS, flags);
3998         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3999         update_exception_bitmap(vcpu);
4000
4001         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
4002         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
4003         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
4004         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
4005         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
4006         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
4007
4008         kvm_mmu_reset_context(vcpu);
4009 }
4010
4011 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
4012 {
4013         struct vcpu_vmx *vmx = to_vmx(vcpu);
4014         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
4015
4016         if (!msr)
4017                 return;
4018
4019         /*
4020          * Force kernel_gs_base reloading before EFER changes, as control
4021          * of this msr depends on is_long_mode().
4022          */
4023         vmx_load_host_state(to_vmx(vcpu));
4024         vcpu->arch.efer = efer;
4025         if (efer & EFER_LMA) {
4026                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4027                 msr->data = efer;
4028         } else {
4029                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4030
4031                 msr->data = efer & ~EFER_LME;
4032         }
4033         setup_msrs(vmx);
4034 }
4035
4036 #ifdef CONFIG_X86_64
4037
4038 static void enter_lmode(struct kvm_vcpu *vcpu)
4039 {
4040         u32 guest_tr_ar;
4041
4042         vmx_segment_cache_clear(to_vmx(vcpu));
4043
4044         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4045         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4046                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4047                                      __func__);
4048                 vmcs_write32(GUEST_TR_AR_BYTES,
4049                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4050                              | VMX_AR_TYPE_BUSY_64_TSS);
4051         }
4052         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4053 }
4054
4055 static void exit_lmode(struct kvm_vcpu *vcpu)
4056 {
4057         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4058         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4059 }
4060
4061 #endif
4062
4063 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4064 {
4065         if (enable_ept) {
4066                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4067                         return;
4068                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4069         } else {
4070                 vpid_sync_context(vpid);
4071         }
4072 }
4073
4074 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4075 {
4076         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4077 }
4078
4079 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4080 {
4081         if (enable_ept)
4082                 vmx_flush_tlb(vcpu);
4083 }
4084
4085 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4086 {
4087         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4088
4089         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4090         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4091 }
4092
4093 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4094 {
4095         if (enable_ept && is_paging(vcpu))
4096                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4097         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4098 }
4099
4100 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4101 {
4102         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4103
4104         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4105         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4106 }
4107
4108 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4109 {
4110         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4111
4112         if (!test_bit(VCPU_EXREG_PDPTR,
4113                       (unsigned long *)&vcpu->arch.regs_dirty))
4114                 return;
4115
4116         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4117                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4118                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4119                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4120                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4121         }
4122 }
4123
4124 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4125 {
4126         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4127
4128         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4129                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4130                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4131                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4132                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4133         }
4134
4135         __set_bit(VCPU_EXREG_PDPTR,
4136                   (unsigned long *)&vcpu->arch.regs_avail);
4137         __set_bit(VCPU_EXREG_PDPTR,
4138                   (unsigned long *)&vcpu->arch.regs_dirty);
4139 }
4140
4141 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4142 {
4143         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4144         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4145         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4146
4147         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4148                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4149             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4150                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4151
4152         return fixed_bits_valid(val, fixed0, fixed1);
4153 }
4154
4155 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4156 {
4157         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4158         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4159
4160         return fixed_bits_valid(val, fixed0, fixed1);
4161 }
4162
4163 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4164 {
4165         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4166         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4167
4168         return fixed_bits_valid(val, fixed0, fixed1);
4169 }
4170
4171 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4172 #define nested_guest_cr4_valid  nested_cr4_valid
4173 #define nested_host_cr4_valid   nested_cr4_valid
4174
4175 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4176
4177 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4178                                         unsigned long cr0,
4179                                         struct kvm_vcpu *vcpu)
4180 {
4181         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4182                 vmx_decache_cr3(vcpu);
4183         if (!(cr0 & X86_CR0_PG)) {
4184                 /* From paging/starting to nonpaging */
4185                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4186                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4187                              (CPU_BASED_CR3_LOAD_EXITING |
4188                               CPU_BASED_CR3_STORE_EXITING));
4189                 vcpu->arch.cr0 = cr0;
4190                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4191         } else if (!is_paging(vcpu)) {
4192                 /* From nonpaging to paging */
4193                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4194                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4195                              ~(CPU_BASED_CR3_LOAD_EXITING |
4196                                CPU_BASED_CR3_STORE_EXITING));
4197                 vcpu->arch.cr0 = cr0;
4198                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4199         }
4200
4201         if (!(cr0 & X86_CR0_WP))
4202                 *hw_cr0 &= ~X86_CR0_WP;
4203 }
4204
4205 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4206 {
4207         struct vcpu_vmx *vmx = to_vmx(vcpu);
4208         unsigned long hw_cr0;
4209
4210         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4211         if (enable_unrestricted_guest)
4212                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4213         else {
4214                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4215
4216                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4217                         enter_pmode(vcpu);
4218
4219                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4220                         enter_rmode(vcpu);
4221         }
4222
4223 #ifdef CONFIG_X86_64
4224         if (vcpu->arch.efer & EFER_LME) {
4225                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4226                         enter_lmode(vcpu);
4227                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4228                         exit_lmode(vcpu);
4229         }
4230 #endif
4231
4232         if (enable_ept)
4233                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4234
4235         vmcs_writel(CR0_READ_SHADOW, cr0);
4236         vmcs_writel(GUEST_CR0, hw_cr0);
4237         vcpu->arch.cr0 = cr0;
4238
4239         /* depends on vcpu->arch.cr0 to be set to a new value */
4240         vmx->emulation_required = emulation_required(vcpu);
4241 }
4242
4243 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4244 {
4245         u64 eptp;
4246
4247         /* TODO write the value reading from MSR */
4248         eptp = VMX_EPT_DEFAULT_MT |
4249                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4250         if (enable_ept_ad_bits &&
4251             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4252                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4253         eptp |= (root_hpa & PAGE_MASK);
4254
4255         return eptp;
4256 }
4257
4258 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4259 {
4260         unsigned long guest_cr3;
4261         u64 eptp;
4262
4263         guest_cr3 = cr3;
4264         if (enable_ept) {
4265                 eptp = construct_eptp(vcpu, cr3);
4266                 vmcs_write64(EPT_POINTER, eptp);
4267                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4268                         guest_cr3 = kvm_read_cr3(vcpu);
4269                 else
4270                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4271                 ept_load_pdptrs(vcpu);
4272         }
4273
4274         vmx_flush_tlb(vcpu);
4275         vmcs_writel(GUEST_CR3, guest_cr3);
4276 }
4277
4278 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4279 {
4280         /*
4281          * Pass through host's Machine Check Enable value to hw_cr4, which
4282          * is in force while we are in guest mode.  Do not let guests control
4283          * this bit, even if host CR4.MCE == 0.
4284          */
4285         unsigned long hw_cr4 =
4286                 (cr4_read_shadow() & X86_CR4_MCE) |
4287                 (cr4 & ~X86_CR4_MCE) |
4288                 (to_vmx(vcpu)->rmode.vm86_active ?
4289                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4290
4291         if (cr4 & X86_CR4_VMXE) {
4292                 /*
4293                  * To use VMXON (and later other VMX instructions), a guest
4294                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4295                  * So basically the check on whether to allow nested VMX
4296                  * is here.
4297                  */
4298                 if (!nested_vmx_allowed(vcpu))
4299                         return 1;
4300         }
4301
4302         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4303                 return 1;
4304
4305         vcpu->arch.cr4 = cr4;
4306         if (enable_ept) {
4307                 if (!is_paging(vcpu)) {
4308                         hw_cr4 &= ~X86_CR4_PAE;
4309                         hw_cr4 |= X86_CR4_PSE;
4310                 } else if (!(cr4 & X86_CR4_PAE)) {
4311                         hw_cr4 &= ~X86_CR4_PAE;
4312                 }
4313         }
4314
4315         if (!enable_unrestricted_guest && !is_paging(vcpu))
4316                 /*
4317                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4318                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4319                  * to be manually disabled when guest switches to non-paging
4320                  * mode.
4321                  *
4322                  * If !enable_unrestricted_guest, the CPU is always running
4323                  * with CR0.PG=1 and CR4 needs to be modified.
4324                  * If enable_unrestricted_guest, the CPU automatically
4325                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4326                  */
4327                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4328
4329         vmcs_writel(CR4_READ_SHADOW, cr4);
4330         vmcs_writel(GUEST_CR4, hw_cr4);
4331         return 0;
4332 }
4333
4334 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4335                             struct kvm_segment *var, int seg)
4336 {
4337         struct vcpu_vmx *vmx = to_vmx(vcpu);
4338         u32 ar;
4339
4340         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4341                 *var = vmx->rmode.segs[seg];
4342                 if (seg == VCPU_SREG_TR
4343                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4344                         return;
4345                 var->base = vmx_read_guest_seg_base(vmx, seg);
4346                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4347                 return;
4348         }
4349         var->base = vmx_read_guest_seg_base(vmx, seg);
4350         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4351         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4352         ar = vmx_read_guest_seg_ar(vmx, seg);
4353         var->unusable = (ar >> 16) & 1;
4354         var->type = ar & 15;
4355         var->s = (ar >> 4) & 1;
4356         var->dpl = (ar >> 5) & 3;
4357         /*
4358          * Some userspaces do not preserve unusable property. Since usable
4359          * segment has to be present according to VMX spec we can use present
4360          * property to amend userspace bug by making unusable segment always
4361          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4362          * segment as unusable.
4363          */
4364         var->present = !var->unusable;
4365         var->avl = (ar >> 12) & 1;
4366         var->l = (ar >> 13) & 1;
4367         var->db = (ar >> 14) & 1;
4368         var->g = (ar >> 15) & 1;
4369 }
4370
4371 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4372 {
4373         struct kvm_segment s;
4374
4375         if (to_vmx(vcpu)->rmode.vm86_active) {
4376                 vmx_get_segment(vcpu, &s, seg);
4377                 return s.base;
4378         }
4379         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4380 }
4381
4382 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4383 {
4384         struct vcpu_vmx *vmx = to_vmx(vcpu);
4385
4386         if (unlikely(vmx->rmode.vm86_active))
4387                 return 0;
4388         else {
4389                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4390                 return VMX_AR_DPL(ar);
4391         }
4392 }
4393
4394 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4395 {
4396         u32 ar;
4397
4398         if (var->unusable || !var->present)
4399                 ar = 1 << 16;
4400         else {
4401                 ar = var->type & 15;
4402                 ar |= (var->s & 1) << 4;
4403                 ar |= (var->dpl & 3) << 5;
4404                 ar |= (var->present & 1) << 7;
4405                 ar |= (var->avl & 1) << 12;
4406                 ar |= (var->l & 1) << 13;
4407                 ar |= (var->db & 1) << 14;
4408                 ar |= (var->g & 1) << 15;
4409         }
4410
4411         return ar;
4412 }
4413
4414 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4415                             struct kvm_segment *var, int seg)
4416 {
4417         struct vcpu_vmx *vmx = to_vmx(vcpu);
4418         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4419
4420         vmx_segment_cache_clear(vmx);
4421
4422         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4423                 vmx->rmode.segs[seg] = *var;
4424                 if (seg == VCPU_SREG_TR)
4425                         vmcs_write16(sf->selector, var->selector);
4426                 else if (var->s)
4427                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4428                 goto out;
4429         }
4430
4431         vmcs_writel(sf->base, var->base);
4432         vmcs_write32(sf->limit, var->limit);
4433         vmcs_write16(sf->selector, var->selector);
4434
4435         /*
4436          *   Fix the "Accessed" bit in AR field of segment registers for older
4437          * qemu binaries.
4438          *   IA32 arch specifies that at the time of processor reset the
4439          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4440          * is setting it to 0 in the userland code. This causes invalid guest
4441          * state vmexit when "unrestricted guest" mode is turned on.
4442          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4443          * tree. Newer qemu binaries with that qemu fix would not need this
4444          * kvm hack.
4445          */
4446         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4447                 var->type |= 0x1; /* Accessed */
4448
4449         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4450
4451 out:
4452         vmx->emulation_required = emulation_required(vcpu);
4453 }
4454
4455 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4456 {
4457         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4458
4459         *db = (ar >> 14) & 1;
4460         *l = (ar >> 13) & 1;
4461 }
4462
4463 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4464 {
4465         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4466         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4467 }
4468
4469 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4470 {
4471         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4472         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4473 }
4474
4475 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4476 {
4477         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4478         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4479 }
4480
4481 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4482 {
4483         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4484         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4485 }
4486
4487 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4488 {
4489         struct kvm_segment var;
4490         u32 ar;
4491
4492         vmx_get_segment(vcpu, &var, seg);
4493         var.dpl = 0x3;
4494         if (seg == VCPU_SREG_CS)
4495                 var.type = 0x3;
4496         ar = vmx_segment_access_rights(&var);
4497
4498         if (var.base != (var.selector << 4))
4499                 return false;
4500         if (var.limit != 0xffff)
4501                 return false;
4502         if (ar != 0xf3)
4503                 return false;
4504
4505         return true;
4506 }
4507
4508 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4509 {
4510         struct kvm_segment cs;
4511         unsigned int cs_rpl;
4512
4513         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4514         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4515
4516         if (cs.unusable)
4517                 return false;
4518         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4519                 return false;
4520         if (!cs.s)
4521                 return false;
4522         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4523                 if (cs.dpl > cs_rpl)
4524                         return false;
4525         } else {
4526                 if (cs.dpl != cs_rpl)
4527                         return false;
4528         }
4529         if (!cs.present)
4530                 return false;
4531
4532         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4533         return true;
4534 }
4535
4536 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4537 {
4538         struct kvm_segment ss;
4539         unsigned int ss_rpl;
4540
4541         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4542         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4543
4544         if (ss.unusable)
4545                 return true;
4546         if (ss.type != 3 && ss.type != 7)
4547                 return false;
4548         if (!ss.s)
4549                 return false;
4550         if (ss.dpl != ss_rpl) /* DPL != RPL */
4551                 return false;
4552         if (!ss.present)
4553                 return false;
4554
4555         return true;
4556 }
4557
4558 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4559 {
4560         struct kvm_segment var;
4561         unsigned int rpl;
4562
4563         vmx_get_segment(vcpu, &var, seg);
4564         rpl = var.selector & SEGMENT_RPL_MASK;
4565
4566         if (var.unusable)
4567                 return true;
4568         if (!var.s)
4569                 return false;
4570         if (!var.present)
4571                 return false;
4572         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4573                 if (var.dpl < rpl) /* DPL < RPL */
4574                         return false;
4575         }
4576
4577         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4578          * rights flags
4579          */
4580         return true;
4581 }
4582
4583 static bool tr_valid(struct kvm_vcpu *vcpu)
4584 {
4585         struct kvm_segment tr;
4586
4587         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4588
4589         if (tr.unusable)
4590                 return false;
4591         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4592                 return false;
4593         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4594                 return false;
4595         if (!tr.present)
4596                 return false;
4597
4598         return true;
4599 }
4600
4601 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4602 {
4603         struct kvm_segment ldtr;
4604
4605         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4606
4607         if (ldtr.unusable)
4608                 return true;
4609         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4610                 return false;
4611         if (ldtr.type != 2)
4612                 return false;
4613         if (!ldtr.present)
4614                 return false;
4615
4616         return true;
4617 }
4618
4619 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4620 {
4621         struct kvm_segment cs, ss;
4622
4623         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4624         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4625
4626         return ((cs.selector & SEGMENT_RPL_MASK) ==
4627                  (ss.selector & SEGMENT_RPL_MASK));
4628 }
4629
4630 /*
4631  * Check if guest state is valid. Returns true if valid, false if
4632  * not.
4633  * We assume that registers are always usable
4634  */
4635 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4636 {
4637         if (enable_unrestricted_guest)
4638                 return true;
4639
4640         /* real mode guest state checks */
4641         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4642                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4643                         return false;
4644                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4645                         return false;
4646                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4647                         return false;
4648                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4649                         return false;
4650                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4651                         return false;
4652                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4653                         return false;
4654         } else {
4655         /* protected mode guest state checks */
4656                 if (!cs_ss_rpl_check(vcpu))
4657                         return false;
4658                 if (!code_segment_valid(vcpu))
4659                         return false;
4660                 if (!stack_segment_valid(vcpu))
4661                         return false;
4662                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4663                         return false;
4664                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4665                         return false;
4666                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4667                         return false;
4668                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4669                         return false;
4670                 if (!tr_valid(vcpu))
4671                         return false;
4672                 if (!ldtr_valid(vcpu))
4673                         return false;
4674         }
4675         /* TODO:
4676          * - Add checks on RIP
4677          * - Add checks on RFLAGS
4678          */
4679
4680         return true;
4681 }
4682
4683 static bool page_address_valid(struct kvm_vcpu *vcpu, gpa_t gpa)
4684 {
4685         return PAGE_ALIGNED(gpa) && !(gpa >> cpuid_maxphyaddr(vcpu));
4686 }
4687
4688 static int init_rmode_tss(struct kvm *kvm)
4689 {
4690         gfn_t fn;
4691         u16 data = 0;
4692         int idx, r;
4693
4694         idx = srcu_read_lock(&kvm->srcu);
4695         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4696         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4697         if (r < 0)
4698                 goto out;
4699         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4700         r = kvm_write_guest_page(kvm, fn++, &data,
4701                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4702         if (r < 0)
4703                 goto out;
4704         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4705         if (r < 0)
4706                 goto out;
4707         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4708         if (r < 0)
4709                 goto out;
4710         data = ~0;
4711         r = kvm_write_guest_page(kvm, fn, &data,
4712                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4713                                  sizeof(u8));
4714 out:
4715         srcu_read_unlock(&kvm->srcu, idx);
4716         return r;
4717 }
4718
4719 static int init_rmode_identity_map(struct kvm *kvm)
4720 {
4721         int i, idx, r = 0;
4722         kvm_pfn_t identity_map_pfn;
4723         u32 tmp;
4724
4725         if (!enable_ept)
4726                 return 0;
4727
4728         /* Protect kvm->arch.ept_identity_pagetable_done. */
4729         mutex_lock(&kvm->slots_lock);
4730
4731         if (likely(kvm->arch.ept_identity_pagetable_done))
4732                 goto out2;
4733
4734         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4735
4736         r = alloc_identity_pagetable(kvm);
4737         if (r < 0)
4738                 goto out2;
4739
4740         idx = srcu_read_lock(&kvm->srcu);
4741         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4742         if (r < 0)
4743                 goto out;
4744         /* Set up identity-mapping pagetable for EPT in real mode */
4745         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4746                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4747                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4748                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4749                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4750                 if (r < 0)
4751                         goto out;
4752         }
4753         kvm->arch.ept_identity_pagetable_done = true;
4754
4755 out:
4756         srcu_read_unlock(&kvm->srcu, idx);
4757
4758 out2:
4759         mutex_unlock(&kvm->slots_lock);
4760         return r;
4761 }
4762
4763 static void seg_setup(int seg)
4764 {
4765         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4766         unsigned int ar;
4767
4768         vmcs_write16(sf->selector, 0);
4769         vmcs_writel(sf->base, 0);
4770         vmcs_write32(sf->limit, 0xffff);
4771         ar = 0x93;
4772         if (seg == VCPU_SREG_CS)
4773                 ar |= 0x08; /* code segment */
4774
4775         vmcs_write32(sf->ar_bytes, ar);
4776 }
4777
4778 static int alloc_apic_access_page(struct kvm *kvm)
4779 {
4780         struct page *page;
4781         int r = 0;
4782
4783         mutex_lock(&kvm->slots_lock);
4784         if (kvm->arch.apic_access_page_done)
4785                 goto out;
4786         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4787                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4788         if (r)
4789                 goto out;
4790
4791         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4792         if (is_error_page(page)) {
4793                 r = -EFAULT;
4794                 goto out;
4795         }
4796
4797         /*
4798          * Do not pin the page in memory, so that memory hot-unplug
4799          * is able to migrate it.
4800          */
4801         put_page(page);
4802         kvm->arch.apic_access_page_done = true;
4803 out:
4804         mutex_unlock(&kvm->slots_lock);
4805         return r;
4806 }
4807
4808 static int alloc_identity_pagetable(struct kvm *kvm)
4809 {
4810         /* Called with kvm->slots_lock held. */
4811
4812         int r = 0;
4813
4814         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4815
4816         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4817                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4818
4819         return r;
4820 }
4821
4822 static int allocate_vpid(void)
4823 {
4824         int vpid;
4825
4826         if (!enable_vpid)
4827                 return 0;
4828         spin_lock(&vmx_vpid_lock);
4829         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4830         if (vpid < VMX_NR_VPIDS)
4831                 __set_bit(vpid, vmx_vpid_bitmap);
4832         else
4833                 vpid = 0;
4834         spin_unlock(&vmx_vpid_lock);
4835         return vpid;
4836 }
4837
4838 static void free_vpid(int vpid)
4839 {
4840         if (!enable_vpid || vpid == 0)
4841                 return;
4842         spin_lock(&vmx_vpid_lock);
4843         __clear_bit(vpid, vmx_vpid_bitmap);
4844         spin_unlock(&vmx_vpid_lock);
4845 }
4846
4847 #define MSR_TYPE_R      1
4848 #define MSR_TYPE_W      2
4849 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4850                                                 u32 msr, int type)
4851 {
4852         int f = sizeof(unsigned long);
4853
4854         if (!cpu_has_vmx_msr_bitmap())
4855                 return;
4856
4857         /*
4858          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4859          * have the write-low and read-high bitmap offsets the wrong way round.
4860          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4861          */
4862         if (msr <= 0x1fff) {
4863                 if (type & MSR_TYPE_R)
4864                         /* read-low */
4865                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4866
4867                 if (type & MSR_TYPE_W)
4868                         /* write-low */
4869                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4870
4871         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4872                 msr &= 0x1fff;
4873                 if (type & MSR_TYPE_R)
4874                         /* read-high */
4875                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4876
4877                 if (type & MSR_TYPE_W)
4878                         /* write-high */
4879                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4880
4881         }
4882 }
4883
4884 /*
4885  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4886  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4887  */
4888 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4889                                                unsigned long *msr_bitmap_nested,
4890                                                u32 msr, int type)
4891 {
4892         int f = sizeof(unsigned long);
4893
4894         if (!cpu_has_vmx_msr_bitmap()) {
4895                 WARN_ON(1);
4896                 return;
4897         }
4898
4899         /*
4900          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4901          * have the write-low and read-high bitmap offsets the wrong way round.
4902          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4903          */
4904         if (msr <= 0x1fff) {
4905                 if (type & MSR_TYPE_R &&
4906                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4907                         /* read-low */
4908                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4909
4910                 if (type & MSR_TYPE_W &&
4911                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4912                         /* write-low */
4913                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4914
4915         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4916                 msr &= 0x1fff;
4917                 if (type & MSR_TYPE_R &&
4918                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4919                         /* read-high */
4920                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4921
4922                 if (type & MSR_TYPE_W &&
4923                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4924                         /* write-high */
4925                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4926
4927         }
4928 }
4929
4930 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4931 {
4932         if (!longmode_only)
4933                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4934                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4935         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4936                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4937 }
4938
4939 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4940 {
4941         if (apicv_active) {
4942                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4943                                 msr, type);
4944                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4945                                 msr, type);
4946         } else {
4947                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4948                                 msr, type);
4949                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4950                                 msr, type);
4951         }
4952 }
4953
4954 static bool vmx_get_enable_apicv(void)
4955 {
4956         return enable_apicv;
4957 }
4958
4959 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4960 {
4961         struct vcpu_vmx *vmx = to_vmx(vcpu);
4962         int max_irr;
4963         void *vapic_page;
4964         u16 status;
4965
4966         if (vmx->nested.pi_desc &&
4967             vmx->nested.pi_pending) {
4968                 vmx->nested.pi_pending = false;
4969                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4970                         return;
4971
4972                 max_irr = find_last_bit(
4973                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4974
4975                 if (max_irr == 256)
4976                         return;
4977
4978                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4979                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4980                 kunmap(vmx->nested.virtual_apic_page);
4981
4982                 status = vmcs_read16(GUEST_INTR_STATUS);
4983                 if ((u8)max_irr > ((u8)status & 0xff)) {
4984                         status &= ~0xff;
4985                         status |= (u8)max_irr;
4986                         vmcs_write16(GUEST_INTR_STATUS, status);
4987                 }
4988         }
4989 }
4990
4991 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4992 {
4993 #ifdef CONFIG_SMP
4994         if (vcpu->mode == IN_GUEST_MODE) {
4995                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4996
4997                 /*
4998                  * Currently, we don't support urgent interrupt,
4999                  * all interrupts are recognized as non-urgent
5000                  * interrupt, so we cannot post interrupts when
5001                  * 'SN' is set.
5002                  *
5003                  * If the vcpu is in guest mode, it means it is
5004                  * running instead of being scheduled out and
5005                  * waiting in the run queue, and that's the only
5006                  * case when 'SN' is set currently, warning if
5007                  * 'SN' is set.
5008                  */
5009                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
5010
5011                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
5012                                 POSTED_INTR_VECTOR);
5013                 return true;
5014         }
5015 #endif
5016         return false;
5017 }
5018
5019 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
5020                                                 int vector)
5021 {
5022         struct vcpu_vmx *vmx = to_vmx(vcpu);
5023
5024         if (is_guest_mode(vcpu) &&
5025             vector == vmx->nested.posted_intr_nv) {
5026                 /* the PIR and ON have been set by L1. */
5027                 kvm_vcpu_trigger_posted_interrupt(vcpu);
5028                 /*
5029                  * If a posted intr is not recognized by hardware,
5030                  * we will accomplish it in the next vmentry.
5031                  */
5032                 vmx->nested.pi_pending = true;
5033                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5034                 return 0;
5035         }
5036         return -1;
5037 }
5038 /*
5039  * Send interrupt to vcpu via posted interrupt way.
5040  * 1. If target vcpu is running(non-root mode), send posted interrupt
5041  * notification to vcpu and hardware will sync PIR to vIRR atomically.
5042  * 2. If target vcpu isn't running(root mode), kick it to pick up the
5043  * interrupt from PIR in next vmentry.
5044  */
5045 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
5046 {
5047         struct vcpu_vmx *vmx = to_vmx(vcpu);
5048         int r;
5049
5050         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5051         if (!r)
5052                 return;
5053
5054         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5055                 return;
5056
5057         /* If a previous notification has sent the IPI, nothing to do.  */
5058         if (pi_test_and_set_on(&vmx->pi_desc))
5059                 return;
5060
5061         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5062                 kvm_vcpu_kick(vcpu);
5063 }
5064
5065 /*
5066  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5067  * will not change in the lifetime of the guest.
5068  * Note that host-state that does change is set elsewhere. E.g., host-state
5069  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5070  */
5071 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5072 {
5073         u32 low32, high32;
5074         unsigned long tmpl;
5075         struct desc_ptr dt;
5076         unsigned long cr0, cr3, cr4;
5077
5078         cr0 = read_cr0();
5079         WARN_ON(cr0 & X86_CR0_TS);
5080         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5081
5082         /*
5083          * Save the most likely value for this task's CR3 in the VMCS.
5084          * We can't use __get_current_cr3_fast() because we're not atomic.
5085          */
5086         cr3 = __read_cr3();
5087         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5088         vmx->host_state.vmcs_host_cr3 = cr3;
5089
5090         /* Save the most likely value for this task's CR4 in the VMCS. */
5091         cr4 = cr4_read_shadow();
5092         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5093         vmx->host_state.vmcs_host_cr4 = cr4;
5094
5095         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5096 #ifdef CONFIG_X86_64
5097         /*
5098          * Load null selectors, so we can avoid reloading them in
5099          * __vmx_load_host_state(), in case userspace uses the null selectors
5100          * too (the expected case).
5101          */
5102         vmcs_write16(HOST_DS_SELECTOR, 0);
5103         vmcs_write16(HOST_ES_SELECTOR, 0);
5104 #else
5105         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5106         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5107 #endif
5108         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5109         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5110
5111         native_store_idt(&dt);
5112         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5113         vmx->host_idt_base = dt.address;
5114
5115         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5116
5117         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5118         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5119         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5120         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5121
5122         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5123                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5124                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5125         }
5126 }
5127
5128 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5129 {
5130         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5131         if (enable_ept)
5132                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5133         if (is_guest_mode(&vmx->vcpu))
5134                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5135                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5136         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5137 }
5138
5139 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5140 {
5141         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5142
5143         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5144                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5145         /* Enable the preemption timer dynamically */
5146         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5147         return pin_based_exec_ctrl;
5148 }
5149
5150 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5151 {
5152         struct vcpu_vmx *vmx = to_vmx(vcpu);
5153
5154         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5155         if (cpu_has_secondary_exec_ctrls()) {
5156                 if (kvm_vcpu_apicv_active(vcpu))
5157                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5158                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5159                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5160                 else
5161                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5162                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5163                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5164         }
5165
5166         if (cpu_has_vmx_msr_bitmap())
5167                 vmx_set_msr_bitmap(vcpu);
5168 }
5169
5170 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5171 {
5172         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5173
5174         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5175                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5176
5177         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5178                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5179 #ifdef CONFIG_X86_64
5180                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5181                                 CPU_BASED_CR8_LOAD_EXITING;
5182 #endif
5183         }
5184         if (!enable_ept)
5185                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5186                                 CPU_BASED_CR3_LOAD_EXITING  |
5187                                 CPU_BASED_INVLPG_EXITING;
5188         return exec_control;
5189 }
5190
5191 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5192 {
5193         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5194         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5195                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5196         if (vmx->vpid == 0)
5197                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5198         if (!enable_ept) {
5199                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5200                 enable_unrestricted_guest = 0;
5201                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5202                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5203         }
5204         if (!enable_unrestricted_guest)
5205                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5206         if (!ple_gap)
5207                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5208         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5209                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5210                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5211         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5212         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5213            (handle_vmptrld).
5214            We can NOT enable shadow_vmcs here because we don't have yet
5215            a current VMCS12
5216         */
5217         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5218
5219         if (!enable_pml)
5220                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5221
5222         return exec_control;
5223 }
5224
5225 static void ept_set_mmio_spte_mask(void)
5226 {
5227         /*
5228          * EPT Misconfigurations can be generated if the value of bits 2:0
5229          * of an EPT paging-structure entry is 110b (write/execute).
5230          */
5231         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5232                                    VMX_EPT_MISCONFIG_WX_VALUE);
5233 }
5234
5235 #define VMX_XSS_EXIT_BITMAP 0
5236 /*
5237  * Sets up the vmcs for emulated real mode.
5238  */
5239 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5240 {
5241 #ifdef CONFIG_X86_64
5242         unsigned long a;
5243 #endif
5244         int i;
5245
5246         /* I/O */
5247         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5248         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5249
5250         if (enable_shadow_vmcs) {
5251                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5252                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5253         }
5254         if (cpu_has_vmx_msr_bitmap())
5255                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5256
5257         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5258
5259         /* Control */
5260         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5261         vmx->hv_deadline_tsc = -1;
5262
5263         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5264
5265         if (cpu_has_secondary_exec_ctrls()) {
5266                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5267                                 vmx_secondary_exec_control(vmx));
5268         }
5269
5270         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5271                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5272                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5273                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5274                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5275
5276                 vmcs_write16(GUEST_INTR_STATUS, 0);
5277
5278                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5279                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5280         }
5281
5282         if (ple_gap) {
5283                 vmcs_write32(PLE_GAP, ple_gap);
5284                 vmx->ple_window = ple_window;
5285                 vmx->ple_window_dirty = true;
5286         }
5287
5288         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5289         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5290         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5291
5292         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5293         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5294         vmx_set_constant_host_state(vmx);
5295 #ifdef CONFIG_X86_64
5296         rdmsrl(MSR_FS_BASE, a);
5297         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5298         rdmsrl(MSR_GS_BASE, a);
5299         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5300 #else
5301         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5302         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5303 #endif
5304
5305         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5306         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5307         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5308         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5309         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5310
5311         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5312                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5313
5314         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5315                 u32 index = vmx_msr_index[i];
5316                 u32 data_low, data_high;
5317                 int j = vmx->nmsrs;
5318
5319                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5320                         continue;
5321                 if (wrmsr_safe(index, data_low, data_high) < 0)
5322                         continue;
5323                 vmx->guest_msrs[j].index = i;
5324                 vmx->guest_msrs[j].data = 0;
5325                 vmx->guest_msrs[j].mask = -1ull;
5326                 ++vmx->nmsrs;
5327         }
5328
5329
5330         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5331
5332         /* 22.2.1, 20.8.1 */
5333         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5334
5335         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5336         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5337
5338         set_cr4_guest_host_mask(vmx);
5339
5340         if (vmx_xsaves_supported())
5341                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5342
5343         if (enable_pml) {
5344                 ASSERT(vmx->pml_pg);
5345                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5346                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5347         }
5348
5349         return 0;
5350 }
5351
5352 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5353 {
5354         struct vcpu_vmx *vmx = to_vmx(vcpu);
5355         struct msr_data apic_base_msr;
5356         u64 cr0;
5357
5358         vmx->rmode.vm86_active = 0;
5359
5360         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5361         kvm_set_cr8(vcpu, 0);
5362
5363         if (!init_event) {
5364                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5365                                      MSR_IA32_APICBASE_ENABLE;
5366                 if (kvm_vcpu_is_reset_bsp(vcpu))
5367                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5368                 apic_base_msr.host_initiated = true;
5369                 kvm_set_apic_base(vcpu, &apic_base_msr);
5370         }
5371
5372         vmx_segment_cache_clear(vmx);
5373
5374         seg_setup(VCPU_SREG_CS);
5375         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5376         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5377
5378         seg_setup(VCPU_SREG_DS);
5379         seg_setup(VCPU_SREG_ES);
5380         seg_setup(VCPU_SREG_FS);
5381         seg_setup(VCPU_SREG_GS);
5382         seg_setup(VCPU_SREG_SS);
5383
5384         vmcs_write16(GUEST_TR_SELECTOR, 0);
5385         vmcs_writel(GUEST_TR_BASE, 0);
5386         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5387         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5388
5389         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5390         vmcs_writel(GUEST_LDTR_BASE, 0);
5391         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5392         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5393
5394         if (!init_event) {
5395                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5396                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5397                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5398                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5399         }
5400
5401         vmcs_writel(GUEST_RFLAGS, 0x02);
5402         kvm_rip_write(vcpu, 0xfff0);
5403
5404         vmcs_writel(GUEST_GDTR_BASE, 0);
5405         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5406
5407         vmcs_writel(GUEST_IDTR_BASE, 0);
5408         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5409
5410         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5411         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5412         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5413
5414         setup_msrs(vmx);
5415
5416         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5417
5418         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5419                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5420                 if (cpu_need_tpr_shadow(vcpu))
5421                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5422                                      __pa(vcpu->arch.apic->regs));
5423                 vmcs_write32(TPR_THRESHOLD, 0);
5424         }
5425
5426         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5427
5428         if (kvm_vcpu_apicv_active(vcpu))
5429                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5430
5431         if (vmx->vpid != 0)
5432                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5433
5434         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5435         vmx->vcpu.arch.cr0 = cr0;
5436         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5437         vmx_set_cr4(vcpu, 0);
5438         vmx_set_efer(vcpu, 0);
5439
5440         update_exception_bitmap(vcpu);
5441
5442         vpid_sync_context(vmx->vpid);
5443 }
5444
5445 /*
5446  * In nested virtualization, check if L1 asked to exit on external interrupts.
5447  * For most existing hypervisors, this will always return true.
5448  */
5449 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5450 {
5451         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5452                 PIN_BASED_EXT_INTR_MASK;
5453 }
5454
5455 /*
5456  * In nested virtualization, check if L1 has set
5457  * VM_EXIT_ACK_INTR_ON_EXIT
5458  */
5459 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5460 {
5461         return get_vmcs12(vcpu)->vm_exit_controls &
5462                 VM_EXIT_ACK_INTR_ON_EXIT;
5463 }
5464
5465 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5466 {
5467         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5468                 PIN_BASED_NMI_EXITING;
5469 }
5470
5471 static void enable_irq_window(struct kvm_vcpu *vcpu)
5472 {
5473         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5474                       CPU_BASED_VIRTUAL_INTR_PENDING);
5475 }
5476
5477 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5478 {
5479         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5480                 enable_irq_window(vcpu);
5481                 return;
5482         }
5483
5484         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5485                       CPU_BASED_VIRTUAL_NMI_PENDING);
5486 }
5487
5488 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5489 {
5490         struct vcpu_vmx *vmx = to_vmx(vcpu);
5491         uint32_t intr;
5492         int irq = vcpu->arch.interrupt.nr;
5493
5494         trace_kvm_inj_virq(irq);
5495
5496         ++vcpu->stat.irq_injections;
5497         if (vmx->rmode.vm86_active) {
5498                 int inc_eip = 0;
5499                 if (vcpu->arch.interrupt.soft)
5500                         inc_eip = vcpu->arch.event_exit_inst_len;
5501                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5502                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5503                 return;
5504         }
5505         intr = irq | INTR_INFO_VALID_MASK;
5506         if (vcpu->arch.interrupt.soft) {
5507                 intr |= INTR_TYPE_SOFT_INTR;
5508                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5509                              vmx->vcpu.arch.event_exit_inst_len);
5510         } else
5511                 intr |= INTR_TYPE_EXT_INTR;
5512         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5513 }
5514
5515 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5516 {
5517         struct vcpu_vmx *vmx = to_vmx(vcpu);
5518
5519         ++vcpu->stat.nmi_injections;
5520         vmx->loaded_vmcs->nmi_known_unmasked = false;
5521
5522         if (vmx->rmode.vm86_active) {
5523                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5524                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5525                 return;
5526         }
5527
5528         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5529                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5530 }
5531
5532 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5533 {
5534         struct vcpu_vmx *vmx = to_vmx(vcpu);
5535         bool masked;
5536
5537         if (vmx->loaded_vmcs->nmi_known_unmasked)
5538                 return false;
5539         masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5540         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5541         return masked;
5542 }
5543
5544 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5545 {
5546         struct vcpu_vmx *vmx = to_vmx(vcpu);
5547
5548         vmx->loaded_vmcs->nmi_known_unmasked = !masked;
5549         if (masked)
5550                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5551                               GUEST_INTR_STATE_NMI);
5552         else
5553                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5554                                 GUEST_INTR_STATE_NMI);
5555 }
5556
5557 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5558 {
5559         if (to_vmx(vcpu)->nested.nested_run_pending)
5560                 return 0;
5561
5562         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5563                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5564                    | GUEST_INTR_STATE_NMI));
5565 }
5566
5567 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5568 {
5569         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5570                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5571                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5572                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5573 }
5574
5575 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5576 {
5577         int ret;
5578
5579         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5580                                     PAGE_SIZE * 3);
5581         if (ret)
5582                 return ret;
5583         kvm->arch.tss_addr = addr;
5584         return init_rmode_tss(kvm);
5585 }
5586
5587 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5588 {
5589         switch (vec) {
5590         case BP_VECTOR:
5591                 /*
5592                  * Update instruction length as we may reinject the exception
5593                  * from user space while in guest debugging mode.
5594                  */
5595                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5596                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5597                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5598                         return false;
5599                 /* fall through */
5600         case DB_VECTOR:
5601                 if (vcpu->guest_debug &
5602                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5603                         return false;
5604                 /* fall through */
5605         case DE_VECTOR:
5606         case OF_VECTOR:
5607         case BR_VECTOR:
5608         case UD_VECTOR:
5609         case DF_VECTOR:
5610         case SS_VECTOR:
5611         case GP_VECTOR:
5612         case MF_VECTOR:
5613                 return true;
5614         break;
5615         }
5616         return false;
5617 }
5618
5619 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5620                                   int vec, u32 err_code)
5621 {
5622         /*
5623          * Instruction with address size override prefix opcode 0x67
5624          * Cause the #SS fault with 0 error code in VM86 mode.
5625          */
5626         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5627                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5628                         if (vcpu->arch.halt_request) {
5629                                 vcpu->arch.halt_request = 0;
5630                                 return kvm_vcpu_halt(vcpu);
5631                         }
5632                         return 1;
5633                 }
5634                 return 0;
5635         }
5636
5637         /*
5638          * Forward all other exceptions that are valid in real mode.
5639          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5640          *        the required debugging infrastructure rework.
5641          */
5642         kvm_queue_exception(vcpu, vec);
5643         return 1;
5644 }
5645
5646 /*
5647  * Trigger machine check on the host. We assume all the MSRs are already set up
5648  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5649  * We pass a fake environment to the machine check handler because we want
5650  * the guest to be always treated like user space, no matter what context
5651  * it used internally.
5652  */
5653 static void kvm_machine_check(void)
5654 {
5655 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5656         struct pt_regs regs = {
5657                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5658                 .flags = X86_EFLAGS_IF,
5659         };
5660
5661         do_machine_check(&regs, 0);
5662 #endif
5663 }
5664
5665 static int handle_machine_check(struct kvm_vcpu *vcpu)
5666 {
5667         /* already handled by vcpu_run */
5668         return 1;
5669 }
5670
5671 static int handle_exception(struct kvm_vcpu *vcpu)
5672 {
5673         struct vcpu_vmx *vmx = to_vmx(vcpu);
5674         struct kvm_run *kvm_run = vcpu->run;
5675         u32 intr_info, ex_no, error_code;
5676         unsigned long cr2, rip, dr6;
5677         u32 vect_info;
5678         enum emulation_result er;
5679
5680         vect_info = vmx->idt_vectoring_info;
5681         intr_info = vmx->exit_intr_info;
5682
5683         if (is_machine_check(intr_info))
5684                 return handle_machine_check(vcpu);
5685
5686         if (is_nmi(intr_info))
5687                 return 1;  /* already handled by vmx_vcpu_run() */
5688
5689         if (is_invalid_opcode(intr_info)) {
5690                 if (is_guest_mode(vcpu)) {
5691                         kvm_queue_exception(vcpu, UD_VECTOR);
5692                         return 1;
5693                 }
5694                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5695                 if (er != EMULATE_DONE)
5696                         kvm_queue_exception(vcpu, UD_VECTOR);
5697                 return 1;
5698         }
5699
5700         error_code = 0;
5701         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5702                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5703
5704         /*
5705          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5706          * MMIO, it is better to report an internal error.
5707          * See the comments in vmx_handle_exit.
5708          */
5709         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5710             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5711                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5712                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5713                 vcpu->run->internal.ndata = 3;
5714                 vcpu->run->internal.data[0] = vect_info;
5715                 vcpu->run->internal.data[1] = intr_info;
5716                 vcpu->run->internal.data[2] = error_code;
5717                 return 0;
5718         }
5719
5720         if (is_page_fault(intr_info)) {
5721                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5722                 /* EPT won't cause page fault directly */
5723                 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
5724                 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0,
5725                                 true);
5726         }
5727
5728         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5729
5730         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5731                 return handle_rmode_exception(vcpu, ex_no, error_code);
5732
5733         switch (ex_no) {
5734         case AC_VECTOR:
5735                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5736                 return 1;
5737         case DB_VECTOR:
5738                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5739                 if (!(vcpu->guest_debug &
5740                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5741                         vcpu->arch.dr6 &= ~15;
5742                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5743                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5744                                 skip_emulated_instruction(vcpu);
5745
5746                         kvm_queue_exception(vcpu, DB_VECTOR);
5747                         return 1;
5748                 }
5749                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5750                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5751                 /* fall through */
5752         case BP_VECTOR:
5753                 /*
5754                  * Update instruction length as we may reinject #BP from
5755                  * user space while in guest debugging mode. Reading it for
5756                  * #DB as well causes no harm, it is not used in that case.
5757                  */
5758                 vmx->vcpu.arch.event_exit_inst_len =
5759                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5760                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5761                 rip = kvm_rip_read(vcpu);
5762                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5763                 kvm_run->debug.arch.exception = ex_no;
5764                 break;
5765         default:
5766                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5767                 kvm_run->ex.exception = ex_no;
5768                 kvm_run->ex.error_code = error_code;
5769                 break;
5770         }
5771         return 0;
5772 }
5773
5774 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5775 {
5776         ++vcpu->stat.irq_exits;
5777         return 1;
5778 }
5779
5780 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5781 {
5782         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5783         return 0;
5784 }
5785
5786 static int handle_io(struct kvm_vcpu *vcpu)
5787 {
5788         unsigned long exit_qualification;
5789         int size, in, string, ret;
5790         unsigned port;
5791
5792         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5793         string = (exit_qualification & 16) != 0;
5794         in = (exit_qualification & 8) != 0;
5795
5796         ++vcpu->stat.io_exits;
5797
5798         if (string || in)
5799                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5800
5801         port = exit_qualification >> 16;
5802         size = (exit_qualification & 7) + 1;
5803
5804         ret = kvm_skip_emulated_instruction(vcpu);
5805
5806         /*
5807          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5808          * KVM_EXIT_DEBUG here.
5809          */
5810         return kvm_fast_pio_out(vcpu, size, port) && ret;
5811 }
5812
5813 static void
5814 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5815 {
5816         /*
5817          * Patch in the VMCALL instruction:
5818          */
5819         hypercall[0] = 0x0f;
5820         hypercall[1] = 0x01;
5821         hypercall[2] = 0xc1;
5822 }
5823
5824 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5825 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5826 {
5827         if (is_guest_mode(vcpu)) {
5828                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5829                 unsigned long orig_val = val;
5830
5831                 /*
5832                  * We get here when L2 changed cr0 in a way that did not change
5833                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5834                  * but did change L0 shadowed bits. So we first calculate the
5835                  * effective cr0 value that L1 would like to write into the
5836                  * hardware. It consists of the L2-owned bits from the new
5837                  * value combined with the L1-owned bits from L1's guest_cr0.
5838                  */
5839                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5840                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5841
5842                 if (!nested_guest_cr0_valid(vcpu, val))
5843                         return 1;
5844
5845                 if (kvm_set_cr0(vcpu, val))
5846                         return 1;
5847                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5848                 return 0;
5849         } else {
5850                 if (to_vmx(vcpu)->nested.vmxon &&
5851                     !nested_host_cr0_valid(vcpu, val))
5852                         return 1;
5853
5854                 return kvm_set_cr0(vcpu, val);
5855         }
5856 }
5857
5858 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5859 {
5860         if (is_guest_mode(vcpu)) {
5861                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5862                 unsigned long orig_val = val;
5863
5864                 /* analogously to handle_set_cr0 */
5865                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5866                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5867                 if (kvm_set_cr4(vcpu, val))
5868                         return 1;
5869                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5870                 return 0;
5871         } else
5872                 return kvm_set_cr4(vcpu, val);
5873 }
5874
5875 static int handle_cr(struct kvm_vcpu *vcpu)
5876 {
5877         unsigned long exit_qualification, val;
5878         int cr;
5879         int reg;
5880         int err;
5881         int ret;
5882
5883         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5884         cr = exit_qualification & 15;
5885         reg = (exit_qualification >> 8) & 15;
5886         switch ((exit_qualification >> 4) & 3) {
5887         case 0: /* mov to cr */
5888                 val = kvm_register_readl(vcpu, reg);
5889                 trace_kvm_cr_write(cr, val);
5890                 switch (cr) {
5891                 case 0:
5892                         err = handle_set_cr0(vcpu, val);
5893                         return kvm_complete_insn_gp(vcpu, err);
5894                 case 3:
5895                         err = kvm_set_cr3(vcpu, val);
5896                         return kvm_complete_insn_gp(vcpu, err);
5897                 case 4:
5898                         err = handle_set_cr4(vcpu, val);
5899                         return kvm_complete_insn_gp(vcpu, err);
5900                 case 8: {
5901                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5902                                 u8 cr8 = (u8)val;
5903                                 err = kvm_set_cr8(vcpu, cr8);
5904                                 ret = kvm_complete_insn_gp(vcpu, err);
5905                                 if (lapic_in_kernel(vcpu))
5906                                         return ret;
5907                                 if (cr8_prev <= cr8)
5908                                         return ret;
5909                                 /*
5910                                  * TODO: we might be squashing a
5911                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5912                                  * KVM_EXIT_DEBUG here.
5913                                  */
5914                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5915                                 return 0;
5916                         }
5917                 }
5918                 break;
5919         case 2: /* clts */
5920                 WARN_ONCE(1, "Guest should always own CR0.TS");
5921                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5922                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5923                 return kvm_skip_emulated_instruction(vcpu);
5924         case 1: /*mov from cr*/
5925                 switch (cr) {
5926                 case 3:
5927                         val = kvm_read_cr3(vcpu);
5928                         kvm_register_write(vcpu, reg, val);
5929                         trace_kvm_cr_read(cr, val);
5930                         return kvm_skip_emulated_instruction(vcpu);
5931                 case 8:
5932                         val = kvm_get_cr8(vcpu);
5933                         kvm_register_write(vcpu, reg, val);
5934                         trace_kvm_cr_read(cr, val);
5935                         return kvm_skip_emulated_instruction(vcpu);
5936                 }
5937                 break;
5938         case 3: /* lmsw */
5939                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5940                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5941                 kvm_lmsw(vcpu, val);
5942
5943                 return kvm_skip_emulated_instruction(vcpu);
5944         default:
5945                 break;
5946         }
5947         vcpu->run->exit_reason = 0;
5948         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5949                (int)(exit_qualification >> 4) & 3, cr);
5950         return 0;
5951 }
5952
5953 static int handle_dr(struct kvm_vcpu *vcpu)
5954 {
5955         unsigned long exit_qualification;
5956         int dr, dr7, reg;
5957
5958         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5959         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5960
5961         /* First, if DR does not exist, trigger UD */
5962         if (!kvm_require_dr(vcpu, dr))
5963                 return 1;
5964
5965         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5966         if (!kvm_require_cpl(vcpu, 0))
5967                 return 1;
5968         dr7 = vmcs_readl(GUEST_DR7);
5969         if (dr7 & DR7_GD) {
5970                 /*
5971                  * As the vm-exit takes precedence over the debug trap, we
5972                  * need to emulate the latter, either for the host or the
5973                  * guest debugging itself.
5974                  */
5975                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5976                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5977                         vcpu->run->debug.arch.dr7 = dr7;
5978                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5979                         vcpu->run->debug.arch.exception = DB_VECTOR;
5980                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5981                         return 0;
5982                 } else {
5983                         vcpu->arch.dr6 &= ~15;
5984                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5985                         kvm_queue_exception(vcpu, DB_VECTOR);
5986                         return 1;
5987                 }
5988         }
5989
5990         if (vcpu->guest_debug == 0) {
5991                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5992                                 CPU_BASED_MOV_DR_EXITING);
5993
5994                 /*
5995                  * No more DR vmexits; force a reload of the debug registers
5996                  * and reenter on this instruction.  The next vmexit will
5997                  * retrieve the full state of the debug registers.
5998                  */
5999                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
6000                 return 1;
6001         }
6002
6003         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
6004         if (exit_qualification & TYPE_MOV_FROM_DR) {
6005                 unsigned long val;
6006
6007                 if (kvm_get_dr(vcpu, dr, &val))
6008                         return 1;
6009                 kvm_register_write(vcpu, reg, val);
6010         } else
6011                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
6012                         return 1;
6013
6014         return kvm_skip_emulated_instruction(vcpu);
6015 }
6016
6017 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
6018 {
6019         return vcpu->arch.dr6;
6020 }
6021
6022 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
6023 {
6024 }
6025
6026 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
6027 {
6028         get_debugreg(vcpu->arch.db[0], 0);
6029         get_debugreg(vcpu->arch.db[1], 1);
6030         get_debugreg(vcpu->arch.db[2], 2);
6031         get_debugreg(vcpu->arch.db[3], 3);
6032         get_debugreg(vcpu->arch.dr6, 6);
6033         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6034
6035         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6036         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6037 }
6038
6039 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6040 {
6041         vmcs_writel(GUEST_DR7, val);
6042 }
6043
6044 static int handle_cpuid(struct kvm_vcpu *vcpu)
6045 {
6046         return kvm_emulate_cpuid(vcpu);
6047 }
6048
6049 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6050 {
6051         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6052         struct msr_data msr_info;
6053
6054         msr_info.index = ecx;
6055         msr_info.host_initiated = false;
6056         if (vmx_get_msr(vcpu, &msr_info)) {
6057                 trace_kvm_msr_read_ex(ecx);
6058                 kvm_inject_gp(vcpu, 0);
6059                 return 1;
6060         }
6061
6062         trace_kvm_msr_read(ecx, msr_info.data);
6063
6064         /* FIXME: handling of bits 32:63 of rax, rdx */
6065         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6066         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6067         return kvm_skip_emulated_instruction(vcpu);
6068 }
6069
6070 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6071 {
6072         struct msr_data msr;
6073         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6074         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6075                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6076
6077         msr.data = data;
6078         msr.index = ecx;
6079         msr.host_initiated = false;
6080         if (kvm_set_msr(vcpu, &msr) != 0) {
6081                 trace_kvm_msr_write_ex(ecx, data);
6082                 kvm_inject_gp(vcpu, 0);
6083                 return 1;
6084         }
6085
6086         trace_kvm_msr_write(ecx, data);
6087         return kvm_skip_emulated_instruction(vcpu);
6088 }
6089
6090 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6091 {
6092         kvm_apic_update_ppr(vcpu);
6093         return 1;
6094 }
6095
6096 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6097 {
6098         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6099                         CPU_BASED_VIRTUAL_INTR_PENDING);
6100
6101         kvm_make_request(KVM_REQ_EVENT, vcpu);
6102
6103         ++vcpu->stat.irq_window_exits;
6104         return 1;
6105 }
6106
6107 static int handle_halt(struct kvm_vcpu *vcpu)
6108 {
6109         return kvm_emulate_halt(vcpu);
6110 }
6111
6112 static int handle_vmcall(struct kvm_vcpu *vcpu)
6113 {
6114         return kvm_emulate_hypercall(vcpu);
6115 }
6116
6117 static int handle_invd(struct kvm_vcpu *vcpu)
6118 {
6119         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6120 }
6121
6122 static int handle_invlpg(struct kvm_vcpu *vcpu)
6123 {
6124         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6125
6126         kvm_mmu_invlpg(vcpu, exit_qualification);
6127         return kvm_skip_emulated_instruction(vcpu);
6128 }
6129
6130 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6131 {
6132         int err;
6133
6134         err = kvm_rdpmc(vcpu);
6135         return kvm_complete_insn_gp(vcpu, err);
6136 }
6137
6138 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6139 {
6140         return kvm_emulate_wbinvd(vcpu);
6141 }
6142
6143 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6144 {
6145         u64 new_bv = kvm_read_edx_eax(vcpu);
6146         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6147
6148         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6149                 return kvm_skip_emulated_instruction(vcpu);
6150         return 1;
6151 }
6152
6153 static int handle_xsaves(struct kvm_vcpu *vcpu)
6154 {
6155         kvm_skip_emulated_instruction(vcpu);
6156         WARN(1, "this should never happen\n");
6157         return 1;
6158 }
6159
6160 static int handle_xrstors(struct kvm_vcpu *vcpu)
6161 {
6162         kvm_skip_emulated_instruction(vcpu);
6163         WARN(1, "this should never happen\n");
6164         return 1;
6165 }
6166
6167 static int handle_apic_access(struct kvm_vcpu *vcpu)
6168 {
6169         if (likely(fasteoi)) {
6170                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6171                 int access_type, offset;
6172
6173                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6174                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6175                 /*
6176                  * Sane guest uses MOV to write EOI, with written value
6177                  * not cared. So make a short-circuit here by avoiding
6178                  * heavy instruction emulation.
6179                  */
6180                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6181                     (offset == APIC_EOI)) {
6182                         kvm_lapic_set_eoi(vcpu);
6183                         return kvm_skip_emulated_instruction(vcpu);
6184                 }
6185         }
6186         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6187 }
6188
6189 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6190 {
6191         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6192         int vector = exit_qualification & 0xff;
6193
6194         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6195         kvm_apic_set_eoi_accelerated(vcpu, vector);
6196         return 1;
6197 }
6198
6199 static int handle_apic_write(struct kvm_vcpu *vcpu)
6200 {
6201         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6202         u32 offset = exit_qualification & 0xfff;
6203
6204         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6205         kvm_apic_write_nodecode(vcpu, offset);
6206         return 1;
6207 }
6208
6209 static int handle_task_switch(struct kvm_vcpu *vcpu)
6210 {
6211         struct vcpu_vmx *vmx = to_vmx(vcpu);
6212         unsigned long exit_qualification;
6213         bool has_error_code = false;
6214         u32 error_code = 0;
6215         u16 tss_selector;
6216         int reason, type, idt_v, idt_index;
6217
6218         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6219         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6220         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6221
6222         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6223
6224         reason = (u32)exit_qualification >> 30;
6225         if (reason == TASK_SWITCH_GATE && idt_v) {
6226                 switch (type) {
6227                 case INTR_TYPE_NMI_INTR:
6228                         vcpu->arch.nmi_injected = false;
6229                         vmx_set_nmi_mask(vcpu, true);
6230                         break;
6231                 case INTR_TYPE_EXT_INTR:
6232                 case INTR_TYPE_SOFT_INTR:
6233                         kvm_clear_interrupt_queue(vcpu);
6234                         break;
6235                 case INTR_TYPE_HARD_EXCEPTION:
6236                         if (vmx->idt_vectoring_info &
6237                             VECTORING_INFO_DELIVER_CODE_MASK) {
6238                                 has_error_code = true;
6239                                 error_code =
6240                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6241                         }
6242                         /* fall through */
6243                 case INTR_TYPE_SOFT_EXCEPTION:
6244                         kvm_clear_exception_queue(vcpu);
6245                         break;
6246                 default:
6247                         break;
6248                 }
6249         }
6250         tss_selector = exit_qualification;
6251
6252         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6253                        type != INTR_TYPE_EXT_INTR &&
6254                        type != INTR_TYPE_NMI_INTR))
6255                 skip_emulated_instruction(vcpu);
6256
6257         if (kvm_task_switch(vcpu, tss_selector,
6258                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6259                             has_error_code, error_code) == EMULATE_FAIL) {
6260                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6261                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6262                 vcpu->run->internal.ndata = 0;
6263                 return 0;
6264         }
6265
6266         /*
6267          * TODO: What about debug traps on tss switch?
6268          *       Are we supposed to inject them and update dr6?
6269          */
6270
6271         return 1;
6272 }
6273
6274 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6275 {
6276         unsigned long exit_qualification;
6277         gpa_t gpa;
6278         u32 error_code;
6279
6280         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6281
6282         /*
6283          * EPT violation happened while executing iret from NMI,
6284          * "blocked by NMI" bit has to be set before next VM entry.
6285          * There are errata that may cause this bit to not be set:
6286          * AAK134, BY25.
6287          */
6288         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6289                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6290                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6291
6292         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6293         trace_kvm_page_fault(gpa, exit_qualification);
6294
6295         /* Is it a read fault? */
6296         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6297                      ? PFERR_USER_MASK : 0;
6298         /* Is it a write fault? */
6299         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6300                       ? PFERR_WRITE_MASK : 0;
6301         /* Is it a fetch fault? */
6302         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6303                       ? PFERR_FETCH_MASK : 0;
6304         /* ept page table entry is present? */
6305         error_code |= (exit_qualification &
6306                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6307                         EPT_VIOLATION_EXECUTABLE))
6308                       ? PFERR_PRESENT_MASK : 0;
6309
6310         vcpu->arch.gpa_available = true;
6311         vcpu->arch.exit_qualification = exit_qualification;
6312
6313         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6314 }
6315
6316 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6317 {
6318         int ret;
6319         gpa_t gpa;
6320
6321         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6322         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6323                 trace_kvm_fast_mmio(gpa);
6324                 return kvm_skip_emulated_instruction(vcpu);
6325         }
6326
6327         ret = handle_mmio_page_fault(vcpu, gpa, true);
6328         vcpu->arch.gpa_available = true;
6329         if (likely(ret == RET_MMIO_PF_EMULATE))
6330                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6331                                               EMULATE_DONE;
6332
6333         if (unlikely(ret == RET_MMIO_PF_INVALID))
6334                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6335
6336         if (unlikely(ret == RET_MMIO_PF_RETRY))
6337                 return 1;
6338
6339         /* It is the real ept misconfig */
6340         WARN_ON(1);
6341
6342         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6343         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6344
6345         return 0;
6346 }
6347
6348 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6349 {
6350         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6351                         CPU_BASED_VIRTUAL_NMI_PENDING);
6352         ++vcpu->stat.nmi_window_exits;
6353         kvm_make_request(KVM_REQ_EVENT, vcpu);
6354
6355         return 1;
6356 }
6357
6358 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6359 {
6360         struct vcpu_vmx *vmx = to_vmx(vcpu);
6361         enum emulation_result err = EMULATE_DONE;
6362         int ret = 1;
6363         u32 cpu_exec_ctrl;
6364         bool intr_window_requested;
6365         unsigned count = 130;
6366
6367         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6368         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6369
6370         while (vmx->emulation_required && count-- != 0) {
6371                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6372                         return handle_interrupt_window(&vmx->vcpu);
6373
6374                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6375                         return 1;
6376
6377                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6378
6379                 if (err == EMULATE_USER_EXIT) {
6380                         ++vcpu->stat.mmio_exits;
6381                         ret = 0;
6382                         goto out;
6383                 }
6384
6385                 if (err != EMULATE_DONE) {
6386                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6387                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6388                         vcpu->run->internal.ndata = 0;
6389                         return 0;
6390                 }
6391
6392                 if (vcpu->arch.halt_request) {
6393                         vcpu->arch.halt_request = 0;
6394                         ret = kvm_vcpu_halt(vcpu);
6395                         goto out;
6396                 }
6397
6398                 if (signal_pending(current))
6399                         goto out;
6400                 if (need_resched())
6401                         schedule();
6402         }
6403
6404 out:
6405         return ret;
6406 }
6407
6408 static int __grow_ple_window(int val)
6409 {
6410         if (ple_window_grow < 1)
6411                 return ple_window;
6412
6413         val = min(val, ple_window_actual_max);
6414
6415         if (ple_window_grow < ple_window)
6416                 val *= ple_window_grow;
6417         else
6418                 val += ple_window_grow;
6419
6420         return val;
6421 }
6422
6423 static int __shrink_ple_window(int val, int modifier, int minimum)
6424 {
6425         if (modifier < 1)
6426                 return ple_window;
6427
6428         if (modifier < ple_window)
6429                 val /= modifier;
6430         else
6431                 val -= modifier;
6432
6433         return max(val, minimum);
6434 }
6435
6436 static void grow_ple_window(struct kvm_vcpu *vcpu)
6437 {
6438         struct vcpu_vmx *vmx = to_vmx(vcpu);
6439         int old = vmx->ple_window;
6440
6441         vmx->ple_window = __grow_ple_window(old);
6442
6443         if (vmx->ple_window != old)
6444                 vmx->ple_window_dirty = true;
6445
6446         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6447 }
6448
6449 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6450 {
6451         struct vcpu_vmx *vmx = to_vmx(vcpu);
6452         int old = vmx->ple_window;
6453
6454         vmx->ple_window = __shrink_ple_window(old,
6455                                               ple_window_shrink, ple_window);
6456
6457         if (vmx->ple_window != old)
6458                 vmx->ple_window_dirty = true;
6459
6460         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6461 }
6462
6463 /*
6464  * ple_window_actual_max is computed to be one grow_ple_window() below
6465  * ple_window_max. (See __grow_ple_window for the reason.)
6466  * This prevents overflows, because ple_window_max is int.
6467  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6468  * this process.
6469  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6470  */
6471 static void update_ple_window_actual_max(void)
6472 {
6473         ple_window_actual_max =
6474                         __shrink_ple_window(max(ple_window_max, ple_window),
6475                                             ple_window_grow, INT_MIN);
6476 }
6477
6478 /*
6479  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6480  */
6481 static void wakeup_handler(void)
6482 {
6483         struct kvm_vcpu *vcpu;
6484         int cpu = smp_processor_id();
6485
6486         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6487         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6488                         blocked_vcpu_list) {
6489                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6490
6491                 if (pi_test_on(pi_desc) == 1)
6492                         kvm_vcpu_kick(vcpu);
6493         }
6494         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6495 }
6496
6497 void vmx_enable_tdp(void)
6498 {
6499         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6500                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6501                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6502                 0ull, VMX_EPT_EXECUTABLE_MASK,
6503                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6504                 VMX_EPT_RWX_MASK);
6505
6506         ept_set_mmio_spte_mask();
6507         kvm_enable_tdp();
6508 }
6509
6510 static __init int hardware_setup(void)
6511 {
6512         int r = -ENOMEM, i, msr;
6513
6514         rdmsrl_safe(MSR_EFER, &host_efer);
6515
6516         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6517                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6518
6519         for (i = 0; i < VMX_BITMAP_NR; i++) {
6520                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6521                 if (!vmx_bitmap[i])
6522                         goto out;
6523         }
6524
6525         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6526         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6527         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6528
6529         /*
6530          * Allow direct access to the PC debug port (it is often used for I/O
6531          * delays, but the vmexits simply slow things down).
6532          */
6533         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6534         clear_bit(0x80, vmx_io_bitmap_a);
6535
6536         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6537
6538         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6539         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6540
6541         if (setup_vmcs_config(&vmcs_config) < 0) {
6542                 r = -EIO;
6543                 goto out;
6544         }
6545
6546         if (boot_cpu_has(X86_FEATURE_NX))
6547                 kvm_enable_efer_bits(EFER_NX);
6548
6549         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6550                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6551                 enable_vpid = 0;
6552
6553         if (!cpu_has_vmx_shadow_vmcs())
6554                 enable_shadow_vmcs = 0;
6555         if (enable_shadow_vmcs)
6556                 init_vmcs_shadow_fields();
6557
6558         if (!cpu_has_vmx_ept() ||
6559             !cpu_has_vmx_ept_4levels()) {
6560                 enable_ept = 0;
6561                 enable_unrestricted_guest = 0;
6562                 enable_ept_ad_bits = 0;
6563         }
6564
6565         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6566                 enable_ept_ad_bits = 0;
6567
6568         if (!cpu_has_vmx_unrestricted_guest())
6569                 enable_unrestricted_guest = 0;
6570
6571         if (!cpu_has_vmx_flexpriority())
6572                 flexpriority_enabled = 0;
6573
6574         /*
6575          * set_apic_access_page_addr() is used to reload apic access
6576          * page upon invalidation.  No need to do anything if not
6577          * using the APIC_ACCESS_ADDR VMCS field.
6578          */
6579         if (!flexpriority_enabled)
6580                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6581
6582         if (!cpu_has_vmx_tpr_shadow())
6583                 kvm_x86_ops->update_cr8_intercept = NULL;
6584
6585         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6586                 kvm_disable_largepages();
6587
6588         if (!cpu_has_vmx_ple())
6589                 ple_gap = 0;
6590
6591         if (!cpu_has_vmx_apicv()) {
6592                 enable_apicv = 0;
6593                 kvm_x86_ops->sync_pir_to_irr = NULL;
6594         }
6595
6596         if (cpu_has_vmx_tsc_scaling()) {
6597                 kvm_has_tsc_control = true;
6598                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6599                 kvm_tsc_scaling_ratio_frac_bits = 48;
6600         }
6601
6602         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6603         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6604         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6605         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6606         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6607         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6608
6609         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6610                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6611         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6612                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6613         memcpy(vmx_msr_bitmap_legacy_x2apic,
6614                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6615         memcpy(vmx_msr_bitmap_longmode_x2apic,
6616                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6617
6618         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6619
6620         for (msr = 0x800; msr <= 0x8ff; msr++) {
6621                 if (msr == 0x839 /* TMCCT */)
6622                         continue;
6623                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6624         }
6625
6626         /*
6627          * TPR reads and writes can be virtualized even if virtual interrupt
6628          * delivery is not in use.
6629          */
6630         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6631         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6632
6633         /* EOI */
6634         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6635         /* SELF-IPI */
6636         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6637
6638         if (enable_ept)
6639                 vmx_enable_tdp();
6640         else
6641                 kvm_disable_tdp();
6642
6643         update_ple_window_actual_max();
6644
6645         /*
6646          * Only enable PML when hardware supports PML feature, and both EPT
6647          * and EPT A/D bit features are enabled -- PML depends on them to work.
6648          */
6649         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6650                 enable_pml = 0;
6651
6652         if (!enable_pml) {
6653                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6654                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6655                 kvm_x86_ops->flush_log_dirty = NULL;
6656                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6657         }
6658
6659         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6660                 u64 vmx_msr;
6661
6662                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6663                 cpu_preemption_timer_multi =
6664                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6665         } else {
6666                 kvm_x86_ops->set_hv_timer = NULL;
6667                 kvm_x86_ops->cancel_hv_timer = NULL;
6668         }
6669
6670         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6671
6672         kvm_mce_cap_supported |= MCG_LMCE_P;
6673
6674         return alloc_kvm_area();
6675
6676 out:
6677         for (i = 0; i < VMX_BITMAP_NR; i++)
6678                 free_page((unsigned long)vmx_bitmap[i]);
6679
6680     return r;
6681 }
6682
6683 static __exit void hardware_unsetup(void)
6684 {
6685         int i;
6686
6687         for (i = 0; i < VMX_BITMAP_NR; i++)
6688                 free_page((unsigned long)vmx_bitmap[i]);
6689
6690         free_kvm_area();
6691 }
6692
6693 /*
6694  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6695  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6696  */
6697 static int handle_pause(struct kvm_vcpu *vcpu)
6698 {
6699         if (ple_gap)
6700                 grow_ple_window(vcpu);
6701
6702         kvm_vcpu_on_spin(vcpu);
6703         return kvm_skip_emulated_instruction(vcpu);
6704 }
6705
6706 static int handle_nop(struct kvm_vcpu *vcpu)
6707 {
6708         return kvm_skip_emulated_instruction(vcpu);
6709 }
6710
6711 static int handle_mwait(struct kvm_vcpu *vcpu)
6712 {
6713         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6714         return handle_nop(vcpu);
6715 }
6716
6717 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6718 {
6719         return 1;
6720 }
6721
6722 static int handle_monitor(struct kvm_vcpu *vcpu)
6723 {
6724         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6725         return handle_nop(vcpu);
6726 }
6727
6728 /*
6729  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6730  * We could reuse a single VMCS for all the L2 guests, but we also want the
6731  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6732  * allows keeping them loaded on the processor, and in the future will allow
6733  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6734  * every entry if they never change.
6735  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6736  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6737  *
6738  * The following functions allocate and free a vmcs02 in this pool.
6739  */
6740
6741 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6742 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6743 {
6744         struct vmcs02_list *item;
6745         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6746                 if (item->vmptr == vmx->nested.current_vmptr) {
6747                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6748                         return &item->vmcs02;
6749                 }
6750
6751         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6752                 /* Recycle the least recently used VMCS. */
6753                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6754                                        struct vmcs02_list, list);
6755                 item->vmptr = vmx->nested.current_vmptr;
6756                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6757                 return &item->vmcs02;
6758         }
6759
6760         /* Create a new VMCS */
6761         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6762         if (!item)
6763                 return NULL;
6764         item->vmcs02.vmcs = alloc_vmcs();
6765         item->vmcs02.shadow_vmcs = NULL;
6766         if (!item->vmcs02.vmcs) {
6767                 kfree(item);
6768                 return NULL;
6769         }
6770         loaded_vmcs_init(&item->vmcs02);
6771         item->vmptr = vmx->nested.current_vmptr;
6772         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6773         vmx->nested.vmcs02_num++;
6774         return &item->vmcs02;
6775 }
6776
6777 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6778 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6779 {
6780         struct vmcs02_list *item;
6781         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6782                 if (item->vmptr == vmptr) {
6783                         free_loaded_vmcs(&item->vmcs02);
6784                         list_del(&item->list);
6785                         kfree(item);
6786                         vmx->nested.vmcs02_num--;
6787                         return;
6788                 }
6789 }
6790
6791 /*
6792  * Free all VMCSs saved for this vcpu, except the one pointed by
6793  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6794  * must be &vmx->vmcs01.
6795  */
6796 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6797 {
6798         struct vmcs02_list *item, *n;
6799
6800         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6801         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6802                 /*
6803                  * Something will leak if the above WARN triggers.  Better than
6804                  * a use-after-free.
6805                  */
6806                 if (vmx->loaded_vmcs == &item->vmcs02)
6807                         continue;
6808
6809                 free_loaded_vmcs(&item->vmcs02);
6810                 list_del(&item->list);
6811                 kfree(item);
6812                 vmx->nested.vmcs02_num--;
6813         }
6814 }
6815
6816 /*
6817  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6818  * set the success or error code of an emulated VMX instruction, as specified
6819  * by Vol 2B, VMX Instruction Reference, "Conventions".
6820  */
6821 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6822 {
6823         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6824                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6825                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6826 }
6827
6828 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6829 {
6830         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6831                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6832                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6833                         | X86_EFLAGS_CF);
6834 }
6835
6836 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6837                                         u32 vm_instruction_error)
6838 {
6839         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6840                 /*
6841                  * failValid writes the error number to the current VMCS, which
6842                  * can't be done there isn't a current VMCS.
6843                  */
6844                 nested_vmx_failInvalid(vcpu);
6845                 return;
6846         }
6847         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6848                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6849                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6850                         | X86_EFLAGS_ZF);
6851         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6852         /*
6853          * We don't need to force a shadow sync because
6854          * VM_INSTRUCTION_ERROR is not shadowed
6855          */
6856 }
6857
6858 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6859 {
6860         /* TODO: not to reset guest simply here. */
6861         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6862         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6863 }
6864
6865 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6866 {
6867         struct vcpu_vmx *vmx =
6868                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6869
6870         vmx->nested.preemption_timer_expired = true;
6871         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6872         kvm_vcpu_kick(&vmx->vcpu);
6873
6874         return HRTIMER_NORESTART;
6875 }
6876
6877 /*
6878  * Decode the memory-address operand of a vmx instruction, as recorded on an
6879  * exit caused by such an instruction (run by a guest hypervisor).
6880  * On success, returns 0. When the operand is invalid, returns 1 and throws
6881  * #UD or #GP.
6882  */
6883 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6884                                  unsigned long exit_qualification,
6885                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6886 {
6887         gva_t off;
6888         bool exn;
6889         struct kvm_segment s;
6890
6891         /*
6892          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6893          * Execution", on an exit, vmx_instruction_info holds most of the
6894          * addressing components of the operand. Only the displacement part
6895          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6896          * For how an actual address is calculated from all these components,
6897          * refer to Vol. 1, "Operand Addressing".
6898          */
6899         int  scaling = vmx_instruction_info & 3;
6900         int  addr_size = (vmx_instruction_info >> 7) & 7;
6901         bool is_reg = vmx_instruction_info & (1u << 10);
6902         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6903         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6904         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6905         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6906         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6907
6908         if (is_reg) {
6909                 kvm_queue_exception(vcpu, UD_VECTOR);
6910                 return 1;
6911         }
6912
6913         /* Addr = segment_base + offset */
6914         /* offset = base + [index * scale] + displacement */
6915         off = exit_qualification; /* holds the displacement */
6916         if (base_is_valid)
6917                 off += kvm_register_read(vcpu, base_reg);
6918         if (index_is_valid)
6919                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6920         vmx_get_segment(vcpu, &s, seg_reg);
6921         *ret = s.base + off;
6922
6923         if (addr_size == 1) /* 32 bit */
6924                 *ret &= 0xffffffff;
6925
6926         /* Checks for #GP/#SS exceptions. */
6927         exn = false;
6928         if (is_long_mode(vcpu)) {
6929                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6930                  * non-canonical form. This is the only check on the memory
6931                  * destination for long mode!
6932                  */
6933                 exn = is_noncanonical_address(*ret);
6934         } else if (is_protmode(vcpu)) {
6935                 /* Protected mode: apply checks for segment validity in the
6936                  * following order:
6937                  * - segment type check (#GP(0) may be thrown)
6938                  * - usability check (#GP(0)/#SS(0))
6939                  * - limit check (#GP(0)/#SS(0))
6940                  */
6941                 if (wr)
6942                         /* #GP(0) if the destination operand is located in a
6943                          * read-only data segment or any code segment.
6944                          */
6945                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6946                 else
6947                         /* #GP(0) if the source operand is located in an
6948                          * execute-only code segment
6949                          */
6950                         exn = ((s.type & 0xa) == 8);
6951                 if (exn) {
6952                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6953                         return 1;
6954                 }
6955                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6956                  */
6957                 exn = (s.unusable != 0);
6958                 /* Protected mode: #GP(0)/#SS(0) if the memory
6959                  * operand is outside the segment limit.
6960                  */
6961                 exn = exn || (off + sizeof(u64) > s.limit);
6962         }
6963         if (exn) {
6964                 kvm_queue_exception_e(vcpu,
6965                                       seg_reg == VCPU_SREG_SS ?
6966                                                 SS_VECTOR : GP_VECTOR,
6967                                       0);
6968                 return 1;
6969         }
6970
6971         return 0;
6972 }
6973
6974 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
6975 {
6976         gva_t gva;
6977         struct x86_exception e;
6978
6979         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6980                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6981                 return 1;
6982
6983         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
6984                                 sizeof(*vmpointer), &e)) {
6985                 kvm_inject_page_fault(vcpu, &e);
6986                 return 1;
6987         }
6988
6989         return 0;
6990 }
6991
6992 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
6993 {
6994         struct vcpu_vmx *vmx = to_vmx(vcpu);
6995         struct vmcs *shadow_vmcs;
6996
6997         if (cpu_has_vmx_msr_bitmap()) {
6998                 vmx->nested.msr_bitmap =
6999                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7000                 if (!vmx->nested.msr_bitmap)
7001                         goto out_msr_bitmap;
7002         }
7003
7004         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7005         if (!vmx->nested.cached_vmcs12)
7006                 goto out_cached_vmcs12;
7007
7008         if (enable_shadow_vmcs) {
7009                 shadow_vmcs = alloc_vmcs();
7010                 if (!shadow_vmcs)
7011                         goto out_shadow_vmcs;
7012                 /* mark vmcs as shadow */
7013                 shadow_vmcs->revision_id |= (1u << 31);
7014                 /* init shadow vmcs */
7015                 vmcs_clear(shadow_vmcs);
7016                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7017         }
7018
7019         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7020         vmx->nested.vmcs02_num = 0;
7021
7022         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7023                      HRTIMER_MODE_REL_PINNED);
7024         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7025
7026         vmx->nested.vmxon = true;
7027         return 0;
7028
7029 out_shadow_vmcs:
7030         kfree(vmx->nested.cached_vmcs12);
7031
7032 out_cached_vmcs12:
7033         free_page((unsigned long)vmx->nested.msr_bitmap);
7034
7035 out_msr_bitmap:
7036         return -ENOMEM;
7037 }
7038
7039 /*
7040  * Emulate the VMXON instruction.
7041  * Currently, we just remember that VMX is active, and do not save or even
7042  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7043  * do not currently need to store anything in that guest-allocated memory
7044  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7045  * argument is different from the VMXON pointer (which the spec says they do).
7046  */
7047 static int handle_vmon(struct kvm_vcpu *vcpu)
7048 {
7049         int ret;
7050         gpa_t vmptr;
7051         struct page *page;
7052         struct vcpu_vmx *vmx = to_vmx(vcpu);
7053         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7054                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7055
7056         /*
7057          * The Intel VMX Instruction Reference lists a bunch of bits that are
7058          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7059          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7060          * Otherwise, we should fail with #UD.  But most faulting conditions
7061          * have already been checked by hardware, prior to the VM-exit for
7062          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7063          * that bit set to 1 in non-root mode.
7064          */
7065         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7066                 kvm_queue_exception(vcpu, UD_VECTOR);
7067                 return 1;
7068         }
7069
7070         if (vmx->nested.vmxon) {
7071                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7072                 return kvm_skip_emulated_instruction(vcpu);
7073         }
7074
7075         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7076                         != VMXON_NEEDED_FEATURES) {
7077                 kvm_inject_gp(vcpu, 0);
7078                 return 1;
7079         }
7080
7081         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7082                 return 1;
7083
7084         /*
7085          * SDM 3: 24.11.5
7086          * The first 4 bytes of VMXON region contain the supported
7087          * VMCS revision identifier
7088          *
7089          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7090          * which replaces physical address width with 32
7091          */
7092         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7093                 nested_vmx_failInvalid(vcpu);
7094                 return kvm_skip_emulated_instruction(vcpu);
7095         }
7096
7097         page = nested_get_page(vcpu, vmptr);
7098         if (page == NULL) {
7099                 nested_vmx_failInvalid(vcpu);
7100                 return kvm_skip_emulated_instruction(vcpu);
7101         }
7102         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7103                 kunmap(page);
7104                 nested_release_page_clean(page);
7105                 nested_vmx_failInvalid(vcpu);
7106                 return kvm_skip_emulated_instruction(vcpu);
7107         }
7108         kunmap(page);
7109         nested_release_page_clean(page);
7110
7111         vmx->nested.vmxon_ptr = vmptr;
7112         ret = enter_vmx_operation(vcpu);
7113         if (ret)
7114                 return ret;
7115
7116         nested_vmx_succeed(vcpu);
7117         return kvm_skip_emulated_instruction(vcpu);
7118 }
7119
7120 /*
7121  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7122  * for running VMX instructions (except VMXON, whose prerequisites are
7123  * slightly different). It also specifies what exception to inject otherwise.
7124  * Note that many of these exceptions have priority over VM exits, so they
7125  * don't have to be checked again here.
7126  */
7127 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7128 {
7129         if (!to_vmx(vcpu)->nested.vmxon) {
7130                 kvm_queue_exception(vcpu, UD_VECTOR);
7131                 return 0;
7132         }
7133         return 1;
7134 }
7135
7136 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7137 {
7138         if (vmx->nested.current_vmptr == -1ull)
7139                 return;
7140
7141         /* current_vmptr and current_vmcs12 are always set/reset together */
7142         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7143                 return;
7144
7145         if (enable_shadow_vmcs) {
7146                 /* copy to memory all shadowed fields in case
7147                    they were modified */
7148                 copy_shadow_to_vmcs12(vmx);
7149                 vmx->nested.sync_shadow_vmcs = false;
7150                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7151                                 SECONDARY_EXEC_SHADOW_VMCS);
7152                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7153         }
7154         vmx->nested.posted_intr_nv = -1;
7155
7156         /* Flush VMCS12 to guest memory */
7157         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7158                VMCS12_SIZE);
7159
7160         kunmap(vmx->nested.current_vmcs12_page);
7161         nested_release_page(vmx->nested.current_vmcs12_page);
7162         vmx->nested.current_vmptr = -1ull;
7163         vmx->nested.current_vmcs12 = NULL;
7164 }
7165
7166 /*
7167  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7168  * just stops using VMX.
7169  */
7170 static void free_nested(struct vcpu_vmx *vmx)
7171 {
7172         if (!vmx->nested.vmxon)
7173                 return;
7174
7175         vmx->nested.vmxon = false;
7176         free_vpid(vmx->nested.vpid02);
7177         nested_release_vmcs12(vmx);
7178         if (vmx->nested.msr_bitmap) {
7179                 free_page((unsigned long)vmx->nested.msr_bitmap);
7180                 vmx->nested.msr_bitmap = NULL;
7181         }
7182         if (enable_shadow_vmcs) {
7183                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7184                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7185                 vmx->vmcs01.shadow_vmcs = NULL;
7186         }
7187         kfree(vmx->nested.cached_vmcs12);
7188         /* Unpin physical memory we referred to in current vmcs02 */
7189         if (vmx->nested.apic_access_page) {
7190                 nested_release_page(vmx->nested.apic_access_page);
7191                 vmx->nested.apic_access_page = NULL;
7192         }
7193         if (vmx->nested.virtual_apic_page) {
7194                 nested_release_page(vmx->nested.virtual_apic_page);
7195                 vmx->nested.virtual_apic_page = NULL;
7196         }
7197         if (vmx->nested.pi_desc_page) {
7198                 kunmap(vmx->nested.pi_desc_page);
7199                 nested_release_page(vmx->nested.pi_desc_page);
7200                 vmx->nested.pi_desc_page = NULL;
7201                 vmx->nested.pi_desc = NULL;
7202         }
7203
7204         nested_free_all_saved_vmcss(vmx);
7205 }
7206
7207 /* Emulate the VMXOFF instruction */
7208 static int handle_vmoff(struct kvm_vcpu *vcpu)
7209 {
7210         if (!nested_vmx_check_permission(vcpu))
7211                 return 1;
7212         free_nested(to_vmx(vcpu));
7213         nested_vmx_succeed(vcpu);
7214         return kvm_skip_emulated_instruction(vcpu);
7215 }
7216
7217 /* Emulate the VMCLEAR instruction */
7218 static int handle_vmclear(struct kvm_vcpu *vcpu)
7219 {
7220         struct vcpu_vmx *vmx = to_vmx(vcpu);
7221         u32 zero = 0;
7222         gpa_t vmptr;
7223
7224         if (!nested_vmx_check_permission(vcpu))
7225                 return 1;
7226
7227         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7228                 return 1;
7229
7230         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7231                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7232                 return kvm_skip_emulated_instruction(vcpu);
7233         }
7234
7235         if (vmptr == vmx->nested.vmxon_ptr) {
7236                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7237                 return kvm_skip_emulated_instruction(vcpu);
7238         }
7239
7240         if (vmptr == vmx->nested.current_vmptr)
7241                 nested_release_vmcs12(vmx);
7242
7243         kvm_vcpu_write_guest(vcpu,
7244                         vmptr + offsetof(struct vmcs12, launch_state),
7245                         &zero, sizeof(zero));
7246
7247         nested_free_vmcs02(vmx, vmptr);
7248
7249         nested_vmx_succeed(vcpu);
7250         return kvm_skip_emulated_instruction(vcpu);
7251 }
7252
7253 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7254
7255 /* Emulate the VMLAUNCH instruction */
7256 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7257 {
7258         return nested_vmx_run(vcpu, true);
7259 }
7260
7261 /* Emulate the VMRESUME instruction */
7262 static int handle_vmresume(struct kvm_vcpu *vcpu)
7263 {
7264
7265         return nested_vmx_run(vcpu, false);
7266 }
7267
7268 /*
7269  * Read a vmcs12 field. Since these can have varying lengths and we return
7270  * one type, we chose the biggest type (u64) and zero-extend the return value
7271  * to that size. Note that the caller, handle_vmread, might need to use only
7272  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7273  * 64-bit fields are to be returned).
7274  */
7275 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7276                                   unsigned long field, u64 *ret)
7277 {
7278         short offset = vmcs_field_to_offset(field);
7279         char *p;
7280
7281         if (offset < 0)
7282                 return offset;
7283
7284         p = ((char *)(get_vmcs12(vcpu))) + offset;
7285
7286         switch (vmcs_field_type(field)) {
7287         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7288                 *ret = *((natural_width *)p);
7289                 return 0;
7290         case VMCS_FIELD_TYPE_U16:
7291                 *ret = *((u16 *)p);
7292                 return 0;
7293         case VMCS_FIELD_TYPE_U32:
7294                 *ret = *((u32 *)p);
7295                 return 0;
7296         case VMCS_FIELD_TYPE_U64:
7297                 *ret = *((u64 *)p);
7298                 return 0;
7299         default:
7300                 WARN_ON(1);
7301                 return -ENOENT;
7302         }
7303 }
7304
7305
7306 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7307                                    unsigned long field, u64 field_value){
7308         short offset = vmcs_field_to_offset(field);
7309         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7310         if (offset < 0)
7311                 return offset;
7312
7313         switch (vmcs_field_type(field)) {
7314         case VMCS_FIELD_TYPE_U16:
7315                 *(u16 *)p = field_value;
7316                 return 0;
7317         case VMCS_FIELD_TYPE_U32:
7318                 *(u32 *)p = field_value;
7319                 return 0;
7320         case VMCS_FIELD_TYPE_U64:
7321                 *(u64 *)p = field_value;
7322                 return 0;
7323         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7324                 *(natural_width *)p = field_value;
7325                 return 0;
7326         default:
7327                 WARN_ON(1);
7328                 return -ENOENT;
7329         }
7330
7331 }
7332
7333 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7334 {
7335         int i;
7336         unsigned long field;
7337         u64 field_value;
7338         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7339         const unsigned long *fields = shadow_read_write_fields;
7340         const int num_fields = max_shadow_read_write_fields;
7341
7342         preempt_disable();
7343
7344         vmcs_load(shadow_vmcs);
7345
7346         for (i = 0; i < num_fields; i++) {
7347                 field = fields[i];
7348                 switch (vmcs_field_type(field)) {
7349                 case VMCS_FIELD_TYPE_U16:
7350                         field_value = vmcs_read16(field);
7351                         break;
7352                 case VMCS_FIELD_TYPE_U32:
7353                         field_value = vmcs_read32(field);
7354                         break;
7355                 case VMCS_FIELD_TYPE_U64:
7356                         field_value = vmcs_read64(field);
7357                         break;
7358                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7359                         field_value = vmcs_readl(field);
7360                         break;
7361                 default:
7362                         WARN_ON(1);
7363                         continue;
7364                 }
7365                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7366         }
7367
7368         vmcs_clear(shadow_vmcs);
7369         vmcs_load(vmx->loaded_vmcs->vmcs);
7370
7371         preempt_enable();
7372 }
7373
7374 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7375 {
7376         const unsigned long *fields[] = {
7377                 shadow_read_write_fields,
7378                 shadow_read_only_fields
7379         };
7380         const int max_fields[] = {
7381                 max_shadow_read_write_fields,
7382                 max_shadow_read_only_fields
7383         };
7384         int i, q;
7385         unsigned long field;
7386         u64 field_value = 0;
7387         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7388
7389         vmcs_load(shadow_vmcs);
7390
7391         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7392                 for (i = 0; i < max_fields[q]; i++) {
7393                         field = fields[q][i];
7394                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7395
7396                         switch (vmcs_field_type(field)) {
7397                         case VMCS_FIELD_TYPE_U16:
7398                                 vmcs_write16(field, (u16)field_value);
7399                                 break;
7400                         case VMCS_FIELD_TYPE_U32:
7401                                 vmcs_write32(field, (u32)field_value);
7402                                 break;
7403                         case VMCS_FIELD_TYPE_U64:
7404                                 vmcs_write64(field, (u64)field_value);
7405                                 break;
7406                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7407                                 vmcs_writel(field, (long)field_value);
7408                                 break;
7409                         default:
7410                                 WARN_ON(1);
7411                                 break;
7412                         }
7413                 }
7414         }
7415
7416         vmcs_clear(shadow_vmcs);
7417         vmcs_load(vmx->loaded_vmcs->vmcs);
7418 }
7419
7420 /*
7421  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7422  * used before) all generate the same failure when it is missing.
7423  */
7424 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7425 {
7426         struct vcpu_vmx *vmx = to_vmx(vcpu);
7427         if (vmx->nested.current_vmptr == -1ull) {
7428                 nested_vmx_failInvalid(vcpu);
7429                 return 0;
7430         }
7431         return 1;
7432 }
7433
7434 static int handle_vmread(struct kvm_vcpu *vcpu)
7435 {
7436         unsigned long field;
7437         u64 field_value;
7438         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7439         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7440         gva_t gva = 0;
7441
7442         if (!nested_vmx_check_permission(vcpu))
7443                 return 1;
7444
7445         if (!nested_vmx_check_vmcs12(vcpu))
7446                 return kvm_skip_emulated_instruction(vcpu);
7447
7448         /* Decode instruction info and find the field to read */
7449         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7450         /* Read the field, zero-extended to a u64 field_value */
7451         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7452                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7453                 return kvm_skip_emulated_instruction(vcpu);
7454         }
7455         /*
7456          * Now copy part of this value to register or memory, as requested.
7457          * Note that the number of bits actually copied is 32 or 64 depending
7458          * on the guest's mode (32 or 64 bit), not on the given field's length.
7459          */
7460         if (vmx_instruction_info & (1u << 10)) {
7461                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7462                         field_value);
7463         } else {
7464                 if (get_vmx_mem_address(vcpu, exit_qualification,
7465                                 vmx_instruction_info, true, &gva))
7466                         return 1;
7467                 /* _system ok, as hardware has verified cpl=0 */
7468                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7469                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7470         }
7471
7472         nested_vmx_succeed(vcpu);
7473         return kvm_skip_emulated_instruction(vcpu);
7474 }
7475
7476
7477 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7478 {
7479         unsigned long field;
7480         gva_t gva;
7481         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7482         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7483         /* The value to write might be 32 or 64 bits, depending on L1's long
7484          * mode, and eventually we need to write that into a field of several
7485          * possible lengths. The code below first zero-extends the value to 64
7486          * bit (field_value), and then copies only the appropriate number of
7487          * bits into the vmcs12 field.
7488          */
7489         u64 field_value = 0;
7490         struct x86_exception e;
7491
7492         if (!nested_vmx_check_permission(vcpu))
7493                 return 1;
7494
7495         if (!nested_vmx_check_vmcs12(vcpu))
7496                 return kvm_skip_emulated_instruction(vcpu);
7497
7498         if (vmx_instruction_info & (1u << 10))
7499                 field_value = kvm_register_readl(vcpu,
7500                         (((vmx_instruction_info) >> 3) & 0xf));
7501         else {
7502                 if (get_vmx_mem_address(vcpu, exit_qualification,
7503                                 vmx_instruction_info, false, &gva))
7504                         return 1;
7505                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7506                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7507                         kvm_inject_page_fault(vcpu, &e);
7508                         return 1;
7509                 }
7510         }
7511
7512
7513         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7514         if (vmcs_field_readonly(field)) {
7515                 nested_vmx_failValid(vcpu,
7516                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7517                 return kvm_skip_emulated_instruction(vcpu);
7518         }
7519
7520         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7521                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7522                 return kvm_skip_emulated_instruction(vcpu);
7523         }
7524
7525         nested_vmx_succeed(vcpu);
7526         return kvm_skip_emulated_instruction(vcpu);
7527 }
7528
7529 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7530 {
7531         vmx->nested.current_vmptr = vmptr;
7532         if (enable_shadow_vmcs) {
7533                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7534                               SECONDARY_EXEC_SHADOW_VMCS);
7535                 vmcs_write64(VMCS_LINK_POINTER,
7536                              __pa(vmx->vmcs01.shadow_vmcs));
7537                 vmx->nested.sync_shadow_vmcs = true;
7538         }
7539 }
7540
7541 /* Emulate the VMPTRLD instruction */
7542 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7543 {
7544         struct vcpu_vmx *vmx = to_vmx(vcpu);
7545         gpa_t vmptr;
7546
7547         if (!nested_vmx_check_permission(vcpu))
7548                 return 1;
7549
7550         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7551                 return 1;
7552
7553         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7554                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7555                 return kvm_skip_emulated_instruction(vcpu);
7556         }
7557
7558         if (vmptr == vmx->nested.vmxon_ptr) {
7559                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7560                 return kvm_skip_emulated_instruction(vcpu);
7561         }
7562
7563         if (vmx->nested.current_vmptr != vmptr) {
7564                 struct vmcs12 *new_vmcs12;
7565                 struct page *page;
7566                 page = nested_get_page(vcpu, vmptr);
7567                 if (page == NULL) {
7568                         nested_vmx_failInvalid(vcpu);
7569                         return kvm_skip_emulated_instruction(vcpu);
7570                 }
7571                 new_vmcs12 = kmap(page);
7572                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7573                         kunmap(page);
7574                         nested_release_page_clean(page);
7575                         nested_vmx_failValid(vcpu,
7576                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7577                         return kvm_skip_emulated_instruction(vcpu);
7578                 }
7579
7580                 nested_release_vmcs12(vmx);
7581                 vmx->nested.current_vmcs12 = new_vmcs12;
7582                 vmx->nested.current_vmcs12_page = page;
7583                 /*
7584                  * Load VMCS12 from guest memory since it is not already
7585                  * cached.
7586                  */
7587                 memcpy(vmx->nested.cached_vmcs12,
7588                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7589                 set_current_vmptr(vmx, vmptr);
7590         }
7591
7592         nested_vmx_succeed(vcpu);
7593         return kvm_skip_emulated_instruction(vcpu);
7594 }
7595
7596 /* Emulate the VMPTRST instruction */
7597 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7598 {
7599         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7600         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7601         gva_t vmcs_gva;
7602         struct x86_exception e;
7603
7604         if (!nested_vmx_check_permission(vcpu))
7605                 return 1;
7606
7607         if (get_vmx_mem_address(vcpu, exit_qualification,
7608                         vmx_instruction_info, true, &vmcs_gva))
7609                 return 1;
7610         /* ok to use *_system, as hardware has verified cpl=0 */
7611         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7612                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7613                                  sizeof(u64), &e)) {
7614                 kvm_inject_page_fault(vcpu, &e);
7615                 return 1;
7616         }
7617         nested_vmx_succeed(vcpu);
7618         return kvm_skip_emulated_instruction(vcpu);
7619 }
7620
7621 /* Emulate the INVEPT instruction */
7622 static int handle_invept(struct kvm_vcpu *vcpu)
7623 {
7624         struct vcpu_vmx *vmx = to_vmx(vcpu);
7625         u32 vmx_instruction_info, types;
7626         unsigned long type;
7627         gva_t gva;
7628         struct x86_exception e;
7629         struct {
7630                 u64 eptp, gpa;
7631         } operand;
7632
7633         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7634               SECONDARY_EXEC_ENABLE_EPT) ||
7635             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7636                 kvm_queue_exception(vcpu, UD_VECTOR);
7637                 return 1;
7638         }
7639
7640         if (!nested_vmx_check_permission(vcpu))
7641                 return 1;
7642
7643         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7644         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7645
7646         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7647
7648         if (type >= 32 || !(types & (1 << type))) {
7649                 nested_vmx_failValid(vcpu,
7650                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7651                 return kvm_skip_emulated_instruction(vcpu);
7652         }
7653
7654         /* According to the Intel VMX instruction reference, the memory
7655          * operand is read even if it isn't needed (e.g., for type==global)
7656          */
7657         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7658                         vmx_instruction_info, false, &gva))
7659                 return 1;
7660         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7661                                 sizeof(operand), &e)) {
7662                 kvm_inject_page_fault(vcpu, &e);
7663                 return 1;
7664         }
7665
7666         switch (type) {
7667         case VMX_EPT_EXTENT_GLOBAL:
7668         /*
7669          * TODO: track mappings and invalidate
7670          * single context requests appropriately
7671          */
7672         case VMX_EPT_EXTENT_CONTEXT:
7673                 kvm_mmu_sync_roots(vcpu);
7674                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7675                 nested_vmx_succeed(vcpu);
7676                 break;
7677         default:
7678                 BUG_ON(1);
7679                 break;
7680         }
7681
7682         return kvm_skip_emulated_instruction(vcpu);
7683 }
7684
7685 static int handle_invvpid(struct kvm_vcpu *vcpu)
7686 {
7687         struct vcpu_vmx *vmx = to_vmx(vcpu);
7688         u32 vmx_instruction_info;
7689         unsigned long type, types;
7690         gva_t gva;
7691         struct x86_exception e;
7692         struct {
7693                 u64 vpid;
7694                 u64 gla;
7695         } operand;
7696
7697         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7698               SECONDARY_EXEC_ENABLE_VPID) ||
7699                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7700                 kvm_queue_exception(vcpu, UD_VECTOR);
7701                 return 1;
7702         }
7703
7704         if (!nested_vmx_check_permission(vcpu))
7705                 return 1;
7706
7707         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7708         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7709
7710         types = (vmx->nested.nested_vmx_vpid_caps &
7711                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7712
7713         if (type >= 32 || !(types & (1 << type))) {
7714                 nested_vmx_failValid(vcpu,
7715                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7716                 return kvm_skip_emulated_instruction(vcpu);
7717         }
7718
7719         /* according to the intel vmx instruction reference, the memory
7720          * operand is read even if it isn't needed (e.g., for type==global)
7721          */
7722         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7723                         vmx_instruction_info, false, &gva))
7724                 return 1;
7725         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7726                                 sizeof(operand), &e)) {
7727                 kvm_inject_page_fault(vcpu, &e);
7728                 return 1;
7729         }
7730         if (operand.vpid >> 16) {
7731                 nested_vmx_failValid(vcpu,
7732                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7733                 return kvm_skip_emulated_instruction(vcpu);
7734         }
7735
7736         switch (type) {
7737         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7738                 if (is_noncanonical_address(operand.gla)) {
7739                         nested_vmx_failValid(vcpu,
7740                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7741                         return kvm_skip_emulated_instruction(vcpu);
7742                 }
7743                 /* fall through */
7744         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7745         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7746                 if (!operand.vpid) {
7747                         nested_vmx_failValid(vcpu,
7748                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7749                         return kvm_skip_emulated_instruction(vcpu);
7750                 }
7751                 break;
7752         case VMX_VPID_EXTENT_ALL_CONTEXT:
7753                 break;
7754         default:
7755                 WARN_ON_ONCE(1);
7756                 return kvm_skip_emulated_instruction(vcpu);
7757         }
7758
7759         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7760         nested_vmx_succeed(vcpu);
7761
7762         return kvm_skip_emulated_instruction(vcpu);
7763 }
7764
7765 static int handle_pml_full(struct kvm_vcpu *vcpu)
7766 {
7767         unsigned long exit_qualification;
7768
7769         trace_kvm_pml_full(vcpu->vcpu_id);
7770
7771         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7772
7773         /*
7774          * PML buffer FULL happened while executing iret from NMI,
7775          * "blocked by NMI" bit has to be set before next VM entry.
7776          */
7777         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7778                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7779                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7780                                 GUEST_INTR_STATE_NMI);
7781
7782         /*
7783          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7784          * here.., and there's no userspace involvement needed for PML.
7785          */
7786         return 1;
7787 }
7788
7789 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7790 {
7791         kvm_lapic_expired_hv_timer(vcpu);
7792         return 1;
7793 }
7794
7795 /*
7796  * The exit handlers return 1 if the exit was handled fully and guest execution
7797  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7798  * to be done to userspace and return 0.
7799  */
7800 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7801         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7802         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7803         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7804         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7805         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7806         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7807         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7808         [EXIT_REASON_CPUID]                   = handle_cpuid,
7809         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7810         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7811         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7812         [EXIT_REASON_HLT]                     = handle_halt,
7813         [EXIT_REASON_INVD]                    = handle_invd,
7814         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7815         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7816         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7817         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7818         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7819         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7820         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7821         [EXIT_REASON_VMREAD]                  = handle_vmread,
7822         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7823         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7824         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7825         [EXIT_REASON_VMON]                    = handle_vmon,
7826         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7827         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7828         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7829         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7830         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7831         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7832         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7833         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7834         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7835         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7836         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7837         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7838         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7839         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7840         [EXIT_REASON_INVEPT]                  = handle_invept,
7841         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7842         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7843         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7844         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7845         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7846 };
7847
7848 static const int kvm_vmx_max_exit_handlers =
7849         ARRAY_SIZE(kvm_vmx_exit_handlers);
7850
7851 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7852                                        struct vmcs12 *vmcs12)
7853 {
7854         unsigned long exit_qualification;
7855         gpa_t bitmap, last_bitmap;
7856         unsigned int port;
7857         int size;
7858         u8 b;
7859
7860         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7861                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7862
7863         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7864
7865         port = exit_qualification >> 16;
7866         size = (exit_qualification & 7) + 1;
7867
7868         last_bitmap = (gpa_t)-1;
7869         b = -1;
7870
7871         while (size > 0) {
7872                 if (port < 0x8000)
7873                         bitmap = vmcs12->io_bitmap_a;
7874                 else if (port < 0x10000)
7875                         bitmap = vmcs12->io_bitmap_b;
7876                 else
7877                         return true;
7878                 bitmap += (port & 0x7fff) / 8;
7879
7880                 if (last_bitmap != bitmap)
7881                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7882                                 return true;
7883                 if (b & (1 << (port & 7)))
7884                         return true;
7885
7886                 port++;
7887                 size--;
7888                 last_bitmap = bitmap;
7889         }
7890
7891         return false;
7892 }
7893
7894 /*
7895  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7896  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7897  * disinterest in the current event (read or write a specific MSR) by using an
7898  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7899  */
7900 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7901         struct vmcs12 *vmcs12, u32 exit_reason)
7902 {
7903         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7904         gpa_t bitmap;
7905
7906         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7907                 return true;
7908
7909         /*
7910          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7911          * for the four combinations of read/write and low/high MSR numbers.
7912          * First we need to figure out which of the four to use:
7913          */
7914         bitmap = vmcs12->msr_bitmap;
7915         if (exit_reason == EXIT_REASON_MSR_WRITE)
7916                 bitmap += 2048;
7917         if (msr_index >= 0xc0000000) {
7918                 msr_index -= 0xc0000000;
7919                 bitmap += 1024;
7920         }
7921
7922         /* Then read the msr_index'th bit from this bitmap: */
7923         if (msr_index < 1024*8) {
7924                 unsigned char b;
7925                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7926                         return true;
7927                 return 1 & (b >> (msr_index & 7));
7928         } else
7929                 return true; /* let L1 handle the wrong parameter */
7930 }
7931
7932 /*
7933  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7934  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7935  * intercept (via guest_host_mask etc.) the current event.
7936  */
7937 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7938         struct vmcs12 *vmcs12)
7939 {
7940         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7941         int cr = exit_qualification & 15;
7942         int reg;
7943         unsigned long val;
7944
7945         switch ((exit_qualification >> 4) & 3) {
7946         case 0: /* mov to cr */
7947                 reg = (exit_qualification >> 8) & 15;
7948                 val = kvm_register_readl(vcpu, reg);
7949                 switch (cr) {
7950                 case 0:
7951                         if (vmcs12->cr0_guest_host_mask &
7952                             (val ^ vmcs12->cr0_read_shadow))
7953                                 return true;
7954                         break;
7955                 case 3:
7956                         if ((vmcs12->cr3_target_count >= 1 &&
7957                                         vmcs12->cr3_target_value0 == val) ||
7958                                 (vmcs12->cr3_target_count >= 2 &&
7959                                         vmcs12->cr3_target_value1 == val) ||
7960                                 (vmcs12->cr3_target_count >= 3 &&
7961                                         vmcs12->cr3_target_value2 == val) ||
7962                                 (vmcs12->cr3_target_count >= 4 &&
7963                                         vmcs12->cr3_target_value3 == val))
7964                                 return false;
7965                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7966                                 return true;
7967                         break;
7968                 case 4:
7969                         if (vmcs12->cr4_guest_host_mask &
7970                             (vmcs12->cr4_read_shadow ^ val))
7971                                 return true;
7972                         break;
7973                 case 8:
7974                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7975                                 return true;
7976                         break;
7977                 }
7978                 break;
7979         case 2: /* clts */
7980                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7981                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7982                         return true;
7983                 break;
7984         case 1: /* mov from cr */
7985                 switch (cr) {
7986                 case 3:
7987                         if (vmcs12->cpu_based_vm_exec_control &
7988                             CPU_BASED_CR3_STORE_EXITING)
7989                                 return true;
7990                         break;
7991                 case 8:
7992                         if (vmcs12->cpu_based_vm_exec_control &
7993                             CPU_BASED_CR8_STORE_EXITING)
7994                                 return true;
7995                         break;
7996                 }
7997                 break;
7998         case 3: /* lmsw */
7999                 /*
8000                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8001                  * cr0. Other attempted changes are ignored, with no exit.
8002                  */
8003                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
8004                 if (vmcs12->cr0_guest_host_mask & 0xe &
8005                     (val ^ vmcs12->cr0_read_shadow))
8006                         return true;
8007                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8008                     !(vmcs12->cr0_read_shadow & 0x1) &&
8009                     (val & 0x1))
8010                         return true;
8011                 break;
8012         }
8013         return false;
8014 }
8015
8016 /*
8017  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8018  * should handle it ourselves in L0 (and then continue L2). Only call this
8019  * when in is_guest_mode (L2).
8020  */
8021 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8022 {
8023         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8024         struct vcpu_vmx *vmx = to_vmx(vcpu);
8025         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8026         u32 exit_reason = vmx->exit_reason;
8027
8028         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8029                                 vmcs_readl(EXIT_QUALIFICATION),
8030                                 vmx->idt_vectoring_info,
8031                                 intr_info,
8032                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8033                                 KVM_ISA_VMX);
8034
8035         if (vmx->nested.nested_run_pending)
8036                 return false;
8037
8038         if (unlikely(vmx->fail)) {
8039                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8040                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8041                 return true;
8042         }
8043
8044         switch (exit_reason) {
8045         case EXIT_REASON_EXCEPTION_NMI:
8046                 if (is_nmi(intr_info))
8047                         return false;
8048                 else if (is_page_fault(intr_info))
8049                         return !vmx->vcpu.arch.apf.host_apf_reason && enable_ept;
8050                 else if (is_no_device(intr_info) &&
8051                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8052                         return false;
8053                 else if (is_debug(intr_info) &&
8054                          vcpu->guest_debug &
8055                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8056                         return false;
8057                 else if (is_breakpoint(intr_info) &&
8058                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8059                         return false;
8060                 return vmcs12->exception_bitmap &
8061                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8062         case EXIT_REASON_EXTERNAL_INTERRUPT:
8063                 return false;
8064         case EXIT_REASON_TRIPLE_FAULT:
8065                 return true;
8066         case EXIT_REASON_PENDING_INTERRUPT:
8067                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8068         case EXIT_REASON_NMI_WINDOW:
8069                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8070         case EXIT_REASON_TASK_SWITCH:
8071                 return true;
8072         case EXIT_REASON_CPUID:
8073                 return true;
8074         case EXIT_REASON_HLT:
8075                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8076         case EXIT_REASON_INVD:
8077                 return true;
8078         case EXIT_REASON_INVLPG:
8079                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8080         case EXIT_REASON_RDPMC:
8081                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8082         case EXIT_REASON_RDRAND:
8083                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8084         case EXIT_REASON_RDSEED:
8085                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8086         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8087                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8088         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8089         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8090         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8091         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8092         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8093         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8094                 /*
8095                  * VMX instructions trap unconditionally. This allows L1 to
8096                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8097                  */
8098                 return true;
8099         case EXIT_REASON_CR_ACCESS:
8100                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8101         case EXIT_REASON_DR_ACCESS:
8102                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8103         case EXIT_REASON_IO_INSTRUCTION:
8104                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8105         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8106                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8107         case EXIT_REASON_MSR_READ:
8108         case EXIT_REASON_MSR_WRITE:
8109                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8110         case EXIT_REASON_INVALID_STATE:
8111                 return true;
8112         case EXIT_REASON_MWAIT_INSTRUCTION:
8113                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8114         case EXIT_REASON_MONITOR_TRAP_FLAG:
8115                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8116         case EXIT_REASON_MONITOR_INSTRUCTION:
8117                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8118         case EXIT_REASON_PAUSE_INSTRUCTION:
8119                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8120                         nested_cpu_has2(vmcs12,
8121                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8122         case EXIT_REASON_MCE_DURING_VMENTRY:
8123                 return false;
8124         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8125                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8126         case EXIT_REASON_APIC_ACCESS:
8127                 return nested_cpu_has2(vmcs12,
8128                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8129         case EXIT_REASON_APIC_WRITE:
8130         case EXIT_REASON_EOI_INDUCED:
8131                 /* apic_write and eoi_induced should exit unconditionally. */
8132                 return true;
8133         case EXIT_REASON_EPT_VIOLATION:
8134                 /*
8135                  * L0 always deals with the EPT violation. If nested EPT is
8136                  * used, and the nested mmu code discovers that the address is
8137                  * missing in the guest EPT table (EPT12), the EPT violation
8138                  * will be injected with nested_ept_inject_page_fault()
8139                  */
8140                 return false;
8141         case EXIT_REASON_EPT_MISCONFIG:
8142                 /*
8143                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8144                  * table (shadow on EPT) or a merged EPT table that L0 built
8145                  * (EPT on EPT). So any problems with the structure of the
8146                  * table is L0's fault.
8147                  */
8148                 return false;
8149         case EXIT_REASON_WBINVD:
8150                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8151         case EXIT_REASON_XSETBV:
8152                 return true;
8153         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8154                 /*
8155                  * This should never happen, since it is not possible to
8156                  * set XSS to a non-zero value---neither in L1 nor in L2.
8157                  * If if it were, XSS would have to be checked against
8158                  * the XSS exit bitmap in vmcs12.
8159                  */
8160                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8161         case EXIT_REASON_PREEMPTION_TIMER:
8162                 return false;
8163         case EXIT_REASON_PML_FULL:
8164                 /* We emulate PML support to L1. */
8165                 return false;
8166         default:
8167                 return true;
8168         }
8169 }
8170
8171 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8172 {
8173         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8174         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8175 }
8176
8177 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8178 {
8179         if (vmx->pml_pg) {
8180                 __free_page(vmx->pml_pg);
8181                 vmx->pml_pg = NULL;
8182         }
8183 }
8184
8185 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8186 {
8187         struct vcpu_vmx *vmx = to_vmx(vcpu);
8188         u64 *pml_buf;
8189         u16 pml_idx;
8190
8191         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8192
8193         /* Do nothing if PML buffer is empty */
8194         if (pml_idx == (PML_ENTITY_NUM - 1))
8195                 return;
8196
8197         /* PML index always points to next available PML buffer entity */
8198         if (pml_idx >= PML_ENTITY_NUM)
8199                 pml_idx = 0;
8200         else
8201                 pml_idx++;
8202
8203         pml_buf = page_address(vmx->pml_pg);
8204         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8205                 u64 gpa;
8206
8207                 gpa = pml_buf[pml_idx];
8208                 WARN_ON(gpa & (PAGE_SIZE - 1));
8209                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8210         }
8211
8212         /* reset PML index */
8213         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8214 }
8215
8216 /*
8217  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8218  * Called before reporting dirty_bitmap to userspace.
8219  */
8220 static void kvm_flush_pml_buffers(struct kvm *kvm)
8221 {
8222         int i;
8223         struct kvm_vcpu *vcpu;
8224         /*
8225          * We only need to kick vcpu out of guest mode here, as PML buffer
8226          * is flushed at beginning of all VMEXITs, and it's obvious that only
8227          * vcpus running in guest are possible to have unflushed GPAs in PML
8228          * buffer.
8229          */
8230         kvm_for_each_vcpu(i, vcpu, kvm)
8231                 kvm_vcpu_kick(vcpu);
8232 }
8233
8234 static void vmx_dump_sel(char *name, uint32_t sel)
8235 {
8236         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8237                name, vmcs_read16(sel),
8238                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8239                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8240                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8241 }
8242
8243 static void vmx_dump_dtsel(char *name, uint32_t limit)
8244 {
8245         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8246                name, vmcs_read32(limit),
8247                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8248 }
8249
8250 static void dump_vmcs(void)
8251 {
8252         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8253         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8254         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8255         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8256         u32 secondary_exec_control = 0;
8257         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8258         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8259         int i, n;
8260
8261         if (cpu_has_secondary_exec_ctrls())
8262                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8263
8264         pr_err("*** Guest State ***\n");
8265         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8266                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8267                vmcs_readl(CR0_GUEST_HOST_MASK));
8268         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8269                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8270         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8271         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8272             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8273         {
8274                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8275                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8276                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8277                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8278         }
8279         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8280                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8281         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8282                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8283         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8284                vmcs_readl(GUEST_SYSENTER_ESP),
8285                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8286         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8287         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8288         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8289         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8290         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8291         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8292         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8293         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8294         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8295         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8296         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8297             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8298                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8299                        efer, vmcs_read64(GUEST_IA32_PAT));
8300         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8301                vmcs_read64(GUEST_IA32_DEBUGCTL),
8302                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8303         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8304                 pr_err("PerfGlobCtl = 0x%016llx\n",
8305                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8306         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8307                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8308         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8309                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8310                vmcs_read32(GUEST_ACTIVITY_STATE));
8311         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8312                 pr_err("InterruptStatus = %04x\n",
8313                        vmcs_read16(GUEST_INTR_STATUS));
8314
8315         pr_err("*** Host State ***\n");
8316         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8317                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8318         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8319                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8320                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8321                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8322                vmcs_read16(HOST_TR_SELECTOR));
8323         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8324                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8325                vmcs_readl(HOST_TR_BASE));
8326         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8327                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8328         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8329                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8330                vmcs_readl(HOST_CR4));
8331         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8332                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8333                vmcs_read32(HOST_IA32_SYSENTER_CS),
8334                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8335         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8336                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8337                        vmcs_read64(HOST_IA32_EFER),
8338                        vmcs_read64(HOST_IA32_PAT));
8339         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8340                 pr_err("PerfGlobCtl = 0x%016llx\n",
8341                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8342
8343         pr_err("*** Control State ***\n");
8344         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8345                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8346         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8347         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8348                vmcs_read32(EXCEPTION_BITMAP),
8349                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8350                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8351         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8352                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8353                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8354                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8355         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8356                vmcs_read32(VM_EXIT_INTR_INFO),
8357                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8358                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8359         pr_err("        reason=%08x qualification=%016lx\n",
8360                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8361         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8362                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8363                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8364         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8365         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8366                 pr_err("TSC Multiplier = 0x%016llx\n",
8367                        vmcs_read64(TSC_MULTIPLIER));
8368         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8369                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8370         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8371                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8372         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8373                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8374         n = vmcs_read32(CR3_TARGET_COUNT);
8375         for (i = 0; i + 1 < n; i += 4)
8376                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8377                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8378                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8379         if (i < n)
8380                 pr_err("CR3 target%u=%016lx\n",
8381                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8382         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8383                 pr_err("PLE Gap=%08x Window=%08x\n",
8384                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8385         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8386                 pr_err("Virtual processor ID = 0x%04x\n",
8387                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8388 }
8389
8390 /*
8391  * The guest has exited.  See if we can fix it or if we need userspace
8392  * assistance.
8393  */
8394 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8395 {
8396         struct vcpu_vmx *vmx = to_vmx(vcpu);
8397         u32 exit_reason = vmx->exit_reason;
8398         u32 vectoring_info = vmx->idt_vectoring_info;
8399
8400         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8401         vcpu->arch.gpa_available = false;
8402
8403         /*
8404          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8405          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8406          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8407          * mode as if vcpus is in root mode, the PML buffer must has been
8408          * flushed already.
8409          */
8410         if (enable_pml)
8411                 vmx_flush_pml_buffer(vcpu);
8412
8413         /* If guest state is invalid, start emulating */
8414         if (vmx->emulation_required)
8415                 return handle_invalid_guest_state(vcpu);
8416
8417         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8418                 nested_vmx_vmexit(vcpu, exit_reason,
8419                                   vmcs_read32(VM_EXIT_INTR_INFO),
8420                                   vmcs_readl(EXIT_QUALIFICATION));
8421                 return 1;
8422         }
8423
8424         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8425                 dump_vmcs();
8426                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8427                 vcpu->run->fail_entry.hardware_entry_failure_reason
8428                         = exit_reason;
8429                 return 0;
8430         }
8431
8432         if (unlikely(vmx->fail)) {
8433                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8434                 vcpu->run->fail_entry.hardware_entry_failure_reason
8435                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8436                 return 0;
8437         }
8438
8439         /*
8440          * Note:
8441          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8442          * delivery event since it indicates guest is accessing MMIO.
8443          * The vm-exit can be triggered again after return to guest that
8444          * will cause infinite loop.
8445          */
8446         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8447                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8448                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8449                         exit_reason != EXIT_REASON_PML_FULL &&
8450                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8451                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8452                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8453                 vcpu->run->internal.ndata = 3;
8454                 vcpu->run->internal.data[0] = vectoring_info;
8455                 vcpu->run->internal.data[1] = exit_reason;
8456                 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
8457                 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
8458                         vcpu->run->internal.ndata++;
8459                         vcpu->run->internal.data[3] =
8460                                 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
8461                 }
8462                 return 0;
8463         }
8464
8465         if (exit_reason < kvm_vmx_max_exit_handlers
8466             && kvm_vmx_exit_handlers[exit_reason])
8467                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8468         else {
8469                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8470                                 exit_reason);
8471                 kvm_queue_exception(vcpu, UD_VECTOR);
8472                 return 1;
8473         }
8474 }
8475
8476 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8477 {
8478         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8479
8480         if (is_guest_mode(vcpu) &&
8481                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8482                 return;
8483
8484         if (irr == -1 || tpr < irr) {
8485                 vmcs_write32(TPR_THRESHOLD, 0);
8486                 return;
8487         }
8488
8489         vmcs_write32(TPR_THRESHOLD, irr);
8490 }
8491
8492 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8493 {
8494         u32 sec_exec_control;
8495
8496         /* Postpone execution until vmcs01 is the current VMCS. */
8497         if (is_guest_mode(vcpu)) {
8498                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8499                 return;
8500         }
8501
8502         if (!cpu_has_vmx_virtualize_x2apic_mode())
8503                 return;
8504
8505         if (!cpu_need_tpr_shadow(vcpu))
8506                 return;
8507
8508         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8509
8510         if (set) {
8511                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8512                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8513         } else {
8514                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8515                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8516                 vmx_flush_tlb_ept_only(vcpu);
8517         }
8518         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8519
8520         vmx_set_msr_bitmap(vcpu);
8521 }
8522
8523 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8524 {
8525         struct vcpu_vmx *vmx = to_vmx(vcpu);
8526
8527         /*
8528          * Currently we do not handle the nested case where L2 has an
8529          * APIC access page of its own; that page is still pinned.
8530          * Hence, we skip the case where the VCPU is in guest mode _and_
8531          * L1 prepared an APIC access page for L2.
8532          *
8533          * For the case where L1 and L2 share the same APIC access page
8534          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8535          * in the vmcs12), this function will only update either the vmcs01
8536          * or the vmcs02.  If the former, the vmcs02 will be updated by
8537          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8538          * the next L2->L1 exit.
8539          */
8540         if (!is_guest_mode(vcpu) ||
8541             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8542                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8543                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8544                 vmx_flush_tlb_ept_only(vcpu);
8545         }
8546 }
8547
8548 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8549 {
8550         u16 status;
8551         u8 old;
8552
8553         if (max_isr == -1)
8554                 max_isr = 0;
8555
8556         status = vmcs_read16(GUEST_INTR_STATUS);
8557         old = status >> 8;
8558         if (max_isr != old) {
8559                 status &= 0xff;
8560                 status |= max_isr << 8;
8561                 vmcs_write16(GUEST_INTR_STATUS, status);
8562         }
8563 }
8564
8565 static void vmx_set_rvi(int vector)
8566 {
8567         u16 status;
8568         u8 old;
8569
8570         if (vector == -1)
8571                 vector = 0;
8572
8573         status = vmcs_read16(GUEST_INTR_STATUS);
8574         old = (u8)status & 0xff;
8575         if ((u8)vector != old) {
8576                 status &= ~0xff;
8577                 status |= (u8)vector;
8578                 vmcs_write16(GUEST_INTR_STATUS, status);
8579         }
8580 }
8581
8582 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8583 {
8584         if (!is_guest_mode(vcpu)) {
8585                 vmx_set_rvi(max_irr);
8586                 return;
8587         }
8588
8589         if (max_irr == -1)
8590                 return;
8591
8592         /*
8593          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8594          * handles it.
8595          */
8596         if (nested_exit_on_intr(vcpu))
8597                 return;
8598
8599         /*
8600          * Else, fall back to pre-APICv interrupt injection since L2
8601          * is run without virtual interrupt delivery.
8602          */
8603         if (!kvm_event_needs_reinjection(vcpu) &&
8604             vmx_interrupt_allowed(vcpu)) {
8605                 kvm_queue_interrupt(vcpu, max_irr, false);
8606                 vmx_inject_irq(vcpu);
8607         }
8608 }
8609
8610 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8611 {
8612         struct vcpu_vmx *vmx = to_vmx(vcpu);
8613         int max_irr;
8614
8615         WARN_ON(!vcpu->arch.apicv_active);
8616         if (pi_test_on(&vmx->pi_desc)) {
8617                 pi_clear_on(&vmx->pi_desc);
8618                 /*
8619                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8620                  * But on x86 this is just a compiler barrier anyway.
8621                  */
8622                 smp_mb__after_atomic();
8623                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8624         } else {
8625                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8626         }
8627         vmx_hwapic_irr_update(vcpu, max_irr);
8628         return max_irr;
8629 }
8630
8631 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8632 {
8633         if (!kvm_vcpu_apicv_active(vcpu))
8634                 return;
8635
8636         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8637         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8638         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8639         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8640 }
8641
8642 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8643 {
8644         struct vcpu_vmx *vmx = to_vmx(vcpu);
8645
8646         pi_clear_on(&vmx->pi_desc);
8647         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8648 }
8649
8650 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8651 {
8652         u32 exit_intr_info = 0;
8653         u16 basic_exit_reason = (u16)vmx->exit_reason;
8654
8655         if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8656               || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
8657                 return;
8658
8659         if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
8660                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8661         vmx->exit_intr_info = exit_intr_info;
8662
8663         /* if exit due to PF check for async PF */
8664         if (is_page_fault(exit_intr_info))
8665                 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
8666
8667         /* Handle machine checks before interrupts are enabled */
8668         if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
8669             is_machine_check(exit_intr_info))
8670                 kvm_machine_check();
8671
8672         /* We need to handle NMIs before interrupts are enabled */
8673         if (is_nmi(exit_intr_info)) {
8674                 kvm_before_handle_nmi(&vmx->vcpu);
8675                 asm("int $2");
8676                 kvm_after_handle_nmi(&vmx->vcpu);
8677         }
8678 }
8679
8680 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8681 {
8682         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8683         register void *__sp asm(_ASM_SP);
8684
8685         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8686                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8687                 unsigned int vector;
8688                 unsigned long entry;
8689                 gate_desc *desc;
8690                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8691 #ifdef CONFIG_X86_64
8692                 unsigned long tmp;
8693 #endif
8694
8695                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8696                 desc = (gate_desc *)vmx->host_idt_base + vector;
8697                 entry = gate_offset(*desc);
8698                 asm volatile(
8699 #ifdef CONFIG_X86_64
8700                         "mov %%" _ASM_SP ", %[sp]\n\t"
8701                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8702                         "push $%c[ss]\n\t"
8703                         "push %[sp]\n\t"
8704 #endif
8705                         "pushf\n\t"
8706                         __ASM_SIZE(push) " $%c[cs]\n\t"
8707                         "call *%[entry]\n\t"
8708                         :
8709 #ifdef CONFIG_X86_64
8710                         [sp]"=&r"(tmp),
8711 #endif
8712                         "+r"(__sp)
8713                         :
8714                         [entry]"r"(entry),
8715                         [ss]"i"(__KERNEL_DS),
8716                         [cs]"i"(__KERNEL_CS)
8717                         );
8718         }
8719 }
8720 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
8721
8722 static bool vmx_has_high_real_mode_segbase(void)
8723 {
8724         return enable_unrestricted_guest || emulate_invalid_guest_state;
8725 }
8726
8727 static bool vmx_mpx_supported(void)
8728 {
8729         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8730                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8731 }
8732
8733 static bool vmx_xsaves_supported(void)
8734 {
8735         return vmcs_config.cpu_based_2nd_exec_ctrl &
8736                 SECONDARY_EXEC_XSAVES;
8737 }
8738
8739 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8740 {
8741         u32 exit_intr_info;
8742         bool unblock_nmi;
8743         u8 vector;
8744         bool idtv_info_valid;
8745
8746         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8747
8748         if (vmx->loaded_vmcs->nmi_known_unmasked)
8749                 return;
8750         /*
8751          * Can't use vmx->exit_intr_info since we're not sure what
8752          * the exit reason is.
8753          */
8754         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8755         unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8756         vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8757         /*
8758          * SDM 3: 27.7.1.2 (September 2008)
8759          * Re-set bit "block by NMI" before VM entry if vmexit caused by
8760          * a guest IRET fault.
8761          * SDM 3: 23.2.2 (September 2008)
8762          * Bit 12 is undefined in any of the following cases:
8763          *  If the VM exit sets the valid bit in the IDT-vectoring
8764          *   information field.
8765          *  If the VM exit is due to a double fault.
8766          */
8767         if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8768             vector != DF_VECTOR && !idtv_info_valid)
8769                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8770                               GUEST_INTR_STATE_NMI);
8771         else
8772                 vmx->loaded_vmcs->nmi_known_unmasked =
8773                         !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8774                           & GUEST_INTR_STATE_NMI);
8775 }
8776
8777 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8778                                       u32 idt_vectoring_info,
8779                                       int instr_len_field,
8780                                       int error_code_field)
8781 {
8782         u8 vector;
8783         int type;
8784         bool idtv_info_valid;
8785
8786         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8787
8788         vcpu->arch.nmi_injected = false;
8789         kvm_clear_exception_queue(vcpu);
8790         kvm_clear_interrupt_queue(vcpu);
8791
8792         if (!idtv_info_valid)
8793                 return;
8794
8795         kvm_make_request(KVM_REQ_EVENT, vcpu);
8796
8797         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8798         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8799
8800         switch (type) {
8801         case INTR_TYPE_NMI_INTR:
8802                 vcpu->arch.nmi_injected = true;
8803                 /*
8804                  * SDM 3: 27.7.1.2 (September 2008)
8805                  * Clear bit "block by NMI" before VM entry if a NMI
8806                  * delivery faulted.
8807                  */
8808                 vmx_set_nmi_mask(vcpu, false);
8809                 break;
8810         case INTR_TYPE_SOFT_EXCEPTION:
8811                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8812                 /* fall through */
8813         case INTR_TYPE_HARD_EXCEPTION:
8814                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8815                         u32 err = vmcs_read32(error_code_field);
8816                         kvm_requeue_exception_e(vcpu, vector, err);
8817                 } else
8818                         kvm_requeue_exception(vcpu, vector);
8819                 break;
8820         case INTR_TYPE_SOFT_INTR:
8821                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8822                 /* fall through */
8823         case INTR_TYPE_EXT_INTR:
8824                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8825                 break;
8826         default:
8827                 break;
8828         }
8829 }
8830
8831 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8832 {
8833         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8834                                   VM_EXIT_INSTRUCTION_LEN,
8835                                   IDT_VECTORING_ERROR_CODE);
8836 }
8837
8838 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8839 {
8840         __vmx_complete_interrupts(vcpu,
8841                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8842                                   VM_ENTRY_INSTRUCTION_LEN,
8843                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8844
8845         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8846 }
8847
8848 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8849 {
8850         int i, nr_msrs;
8851         struct perf_guest_switch_msr *msrs;
8852
8853         msrs = perf_guest_get_msrs(&nr_msrs);
8854
8855         if (!msrs)
8856                 return;
8857
8858         for (i = 0; i < nr_msrs; i++)
8859                 if (msrs[i].host == msrs[i].guest)
8860                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8861                 else
8862                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8863                                         msrs[i].host);
8864 }
8865
8866 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8867 {
8868         struct vcpu_vmx *vmx = to_vmx(vcpu);
8869         u64 tscl;
8870         u32 delta_tsc;
8871
8872         if (vmx->hv_deadline_tsc == -1)
8873                 return;
8874
8875         tscl = rdtsc();
8876         if (vmx->hv_deadline_tsc > tscl)
8877                 /* sure to be 32 bit only because checked on set_hv_timer */
8878                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8879                         cpu_preemption_timer_multi);
8880         else
8881                 delta_tsc = 0;
8882
8883         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8884 }
8885
8886 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8887 {
8888         struct vcpu_vmx *vmx = to_vmx(vcpu);
8889         unsigned long debugctlmsr, cr3, cr4;
8890
8891         /* Don't enter VMX if guest state is invalid, let the exit handler
8892            start emulation until we arrive back to a valid state */
8893         if (vmx->emulation_required)
8894                 return;
8895
8896         if (vmx->ple_window_dirty) {
8897                 vmx->ple_window_dirty = false;
8898                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8899         }
8900
8901         if (vmx->nested.sync_shadow_vmcs) {
8902                 copy_vmcs12_to_shadow(vmx);
8903                 vmx->nested.sync_shadow_vmcs = false;
8904         }
8905
8906         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8907                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8908         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8909                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8910
8911         cr3 = __get_current_cr3_fast();
8912         if (unlikely(cr3 != vmx->host_state.vmcs_host_cr3)) {
8913                 vmcs_writel(HOST_CR3, cr3);
8914                 vmx->host_state.vmcs_host_cr3 = cr3;
8915         }
8916
8917         cr4 = cr4_read_shadow();
8918         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8919                 vmcs_writel(HOST_CR4, cr4);
8920                 vmx->host_state.vmcs_host_cr4 = cr4;
8921         }
8922
8923         /* When single-stepping over STI and MOV SS, we must clear the
8924          * corresponding interruptibility bits in the guest state. Otherwise
8925          * vmentry fails as it then expects bit 14 (BS) in pending debug
8926          * exceptions being set, but that's not correct for the guest debugging
8927          * case. */
8928         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8929                 vmx_set_interrupt_shadow(vcpu, 0);
8930
8931         if (vmx->guest_pkru_valid)
8932                 __write_pkru(vmx->guest_pkru);
8933
8934         atomic_switch_perf_msrs(vmx);
8935         debugctlmsr = get_debugctlmsr();
8936
8937         vmx_arm_hv_timer(vcpu);
8938
8939         vmx->__launched = vmx->loaded_vmcs->launched;
8940         asm(
8941                 /* Store host registers */
8942                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8943                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8944                 "push %%" _ASM_CX " \n\t"
8945                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8946                 "je 1f \n\t"
8947                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8948                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8949                 "1: \n\t"
8950                 /* Reload cr2 if changed */
8951                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8952                 "mov %%cr2, %%" _ASM_DX " \n\t"
8953                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8954                 "je 2f \n\t"
8955                 "mov %%" _ASM_AX", %%cr2 \n\t"
8956                 "2: \n\t"
8957                 /* Check if vmlaunch of vmresume is needed */
8958                 "cmpl $0, %c[launched](%0) \n\t"
8959                 /* Load guest registers.  Don't clobber flags. */
8960                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8961                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8962                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8963                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8964                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8965                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8966 #ifdef CONFIG_X86_64
8967                 "mov %c[r8](%0),  %%r8  \n\t"
8968                 "mov %c[r9](%0),  %%r9  \n\t"
8969                 "mov %c[r10](%0), %%r10 \n\t"
8970                 "mov %c[r11](%0), %%r11 \n\t"
8971                 "mov %c[r12](%0), %%r12 \n\t"
8972                 "mov %c[r13](%0), %%r13 \n\t"
8973                 "mov %c[r14](%0), %%r14 \n\t"
8974                 "mov %c[r15](%0), %%r15 \n\t"
8975 #endif
8976                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8977
8978                 /* Enter guest mode */
8979                 "jne 1f \n\t"
8980                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8981                 "jmp 2f \n\t"
8982                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8983                 "2: "
8984                 /* Save guest registers, load host registers, keep flags */
8985                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8986                 "pop %0 \n\t"
8987                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8988                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8989                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8990                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8991                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8992                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8993                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8994 #ifdef CONFIG_X86_64
8995                 "mov %%r8,  %c[r8](%0) \n\t"
8996                 "mov %%r9,  %c[r9](%0) \n\t"
8997                 "mov %%r10, %c[r10](%0) \n\t"
8998                 "mov %%r11, %c[r11](%0) \n\t"
8999                 "mov %%r12, %c[r12](%0) \n\t"
9000                 "mov %%r13, %c[r13](%0) \n\t"
9001                 "mov %%r14, %c[r14](%0) \n\t"
9002                 "mov %%r15, %c[r15](%0) \n\t"
9003 #endif
9004                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9005                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9006
9007                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9008                 "setbe %c[fail](%0) \n\t"
9009                 ".pushsection .rodata \n\t"
9010                 ".global vmx_return \n\t"
9011                 "vmx_return: " _ASM_PTR " 2b \n\t"
9012                 ".popsection"
9013               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9014                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9015                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9016                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9017                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9018                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9019                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9020                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9021                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9022                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9023                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9024 #ifdef CONFIG_X86_64
9025                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9026                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9027                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9028                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9029                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9030                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9031                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9032                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9033 #endif
9034                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9035                 [wordsize]"i"(sizeof(ulong))
9036               : "cc", "memory"
9037 #ifdef CONFIG_X86_64
9038                 , "rax", "rbx", "rdi", "rsi"
9039                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9040 #else
9041                 , "eax", "ebx", "edi", "esi"
9042 #endif
9043               );
9044
9045         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9046         if (debugctlmsr)
9047                 update_debugctlmsr(debugctlmsr);
9048
9049 #ifndef CONFIG_X86_64
9050         /*
9051          * The sysexit path does not restore ds/es, so we must set them to
9052          * a reasonable value ourselves.
9053          *
9054          * We can't defer this to vmx_load_host_state() since that function
9055          * may be executed in interrupt context, which saves and restore segments
9056          * around it, nullifying its effect.
9057          */
9058         loadsegment(ds, __USER_DS);
9059         loadsegment(es, __USER_DS);
9060 #endif
9061
9062         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9063                                   | (1 << VCPU_EXREG_RFLAGS)
9064                                   | (1 << VCPU_EXREG_PDPTR)
9065                                   | (1 << VCPU_EXREG_SEGMENTS)
9066                                   | (1 << VCPU_EXREG_CR3));
9067         vcpu->arch.regs_dirty = 0;
9068
9069         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9070
9071         vmx->loaded_vmcs->launched = 1;
9072
9073         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9074
9075         /*
9076          * eager fpu is enabled if PKEY is supported and CR4 is switched
9077          * back on host, so it is safe to read guest PKRU from current
9078          * XSAVE.
9079          */
9080         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9081                 vmx->guest_pkru = __read_pkru();
9082                 if (vmx->guest_pkru != vmx->host_pkru) {
9083                         vmx->guest_pkru_valid = true;
9084                         __write_pkru(vmx->host_pkru);
9085                 } else
9086                         vmx->guest_pkru_valid = false;
9087         }
9088
9089         /*
9090          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9091          * we did not inject a still-pending event to L1 now because of
9092          * nested_run_pending, we need to re-enable this bit.
9093          */
9094         if (vmx->nested.nested_run_pending)
9095                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9096
9097         vmx->nested.nested_run_pending = 0;
9098
9099         vmx_complete_atomic_exit(vmx);
9100         vmx_recover_nmi_blocking(vmx);
9101         vmx_complete_interrupts(vmx);
9102 }
9103 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9104
9105 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9106 {
9107         struct vcpu_vmx *vmx = to_vmx(vcpu);
9108         int cpu;
9109
9110         if (vmx->loaded_vmcs == vmcs)
9111                 return;
9112
9113         cpu = get_cpu();
9114         vmx->loaded_vmcs = vmcs;
9115         vmx_vcpu_put(vcpu);
9116         vmx_vcpu_load(vcpu, cpu);
9117         vcpu->cpu = cpu;
9118         put_cpu();
9119 }
9120
9121 /*
9122  * Ensure that the current vmcs of the logical processor is the
9123  * vmcs01 of the vcpu before calling free_nested().
9124  */
9125 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9126 {
9127        struct vcpu_vmx *vmx = to_vmx(vcpu);
9128        int r;
9129
9130        r = vcpu_load(vcpu);
9131        BUG_ON(r);
9132        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9133        free_nested(vmx);
9134        vcpu_put(vcpu);
9135 }
9136
9137 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9138 {
9139         struct vcpu_vmx *vmx = to_vmx(vcpu);
9140
9141         if (enable_pml)
9142                 vmx_destroy_pml_buffer(vmx);
9143         free_vpid(vmx->vpid);
9144         leave_guest_mode(vcpu);
9145         vmx_free_vcpu_nested(vcpu);
9146         free_loaded_vmcs(vmx->loaded_vmcs);
9147         kfree(vmx->guest_msrs);
9148         kvm_vcpu_uninit(vcpu);
9149         kmem_cache_free(kvm_vcpu_cache, vmx);
9150 }
9151
9152 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9153 {
9154         int err;
9155         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9156         int cpu;
9157
9158         if (!vmx)
9159                 return ERR_PTR(-ENOMEM);
9160
9161         vmx->vpid = allocate_vpid();
9162
9163         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9164         if (err)
9165                 goto free_vcpu;
9166
9167         err = -ENOMEM;
9168
9169         /*
9170          * If PML is turned on, failure on enabling PML just results in failure
9171          * of creating the vcpu, therefore we can simplify PML logic (by
9172          * avoiding dealing with cases, such as enabling PML partially on vcpus
9173          * for the guest, etc.
9174          */
9175         if (enable_pml) {
9176                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9177                 if (!vmx->pml_pg)
9178                         goto uninit_vcpu;
9179         }
9180
9181         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9182         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9183                      > PAGE_SIZE);
9184
9185         if (!vmx->guest_msrs)
9186                 goto free_pml;
9187
9188         vmx->loaded_vmcs = &vmx->vmcs01;
9189         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9190         vmx->loaded_vmcs->shadow_vmcs = NULL;
9191         if (!vmx->loaded_vmcs->vmcs)
9192                 goto free_msrs;
9193         loaded_vmcs_init(vmx->loaded_vmcs);
9194
9195         cpu = get_cpu();
9196         vmx_vcpu_load(&vmx->vcpu, cpu);
9197         vmx->vcpu.cpu = cpu;
9198         err = vmx_vcpu_setup(vmx);
9199         vmx_vcpu_put(&vmx->vcpu);
9200         put_cpu();
9201         if (err)
9202                 goto free_vmcs;
9203         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9204                 err = alloc_apic_access_page(kvm);
9205                 if (err)
9206                         goto free_vmcs;
9207         }
9208
9209         if (enable_ept) {
9210                 if (!kvm->arch.ept_identity_map_addr)
9211                         kvm->arch.ept_identity_map_addr =
9212                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9213                 err = init_rmode_identity_map(kvm);
9214                 if (err)
9215                         goto free_vmcs;
9216         }
9217
9218         if (nested) {
9219                 nested_vmx_setup_ctls_msrs(vmx);
9220                 vmx->nested.vpid02 = allocate_vpid();
9221         }
9222
9223         vmx->nested.posted_intr_nv = -1;
9224         vmx->nested.current_vmptr = -1ull;
9225         vmx->nested.current_vmcs12 = NULL;
9226
9227         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9228
9229         return &vmx->vcpu;
9230
9231 free_vmcs:
9232         free_vpid(vmx->nested.vpid02);
9233         free_loaded_vmcs(vmx->loaded_vmcs);
9234 free_msrs:
9235         kfree(vmx->guest_msrs);
9236 free_pml:
9237         vmx_destroy_pml_buffer(vmx);
9238 uninit_vcpu:
9239         kvm_vcpu_uninit(&vmx->vcpu);
9240 free_vcpu:
9241         free_vpid(vmx->vpid);
9242         kmem_cache_free(kvm_vcpu_cache, vmx);
9243         return ERR_PTR(err);
9244 }
9245
9246 static void __init vmx_check_processor_compat(void *rtn)
9247 {
9248         struct vmcs_config vmcs_conf;
9249
9250         *(int *)rtn = 0;
9251         if (setup_vmcs_config(&vmcs_conf) < 0)
9252                 *(int *)rtn = -EIO;
9253         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9254                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9255                                 smp_processor_id());
9256                 *(int *)rtn = -EIO;
9257         }
9258 }
9259
9260 static int get_ept_level(void)
9261 {
9262         return VMX_EPT_DEFAULT_GAW + 1;
9263 }
9264
9265 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9266 {
9267         u8 cache;
9268         u64 ipat = 0;
9269
9270         /* For VT-d and EPT combination
9271          * 1. MMIO: always map as UC
9272          * 2. EPT with VT-d:
9273          *   a. VT-d without snooping control feature: can't guarantee the
9274          *      result, try to trust guest.
9275          *   b. VT-d with snooping control feature: snooping control feature of
9276          *      VT-d engine can guarantee the cache correctness. Just set it
9277          *      to WB to keep consistent with host. So the same as item 3.
9278          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9279          *    consistent with host MTRR
9280          */
9281         if (is_mmio) {
9282                 cache = MTRR_TYPE_UNCACHABLE;
9283                 goto exit;
9284         }
9285
9286         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9287                 ipat = VMX_EPT_IPAT_BIT;
9288                 cache = MTRR_TYPE_WRBACK;
9289                 goto exit;
9290         }
9291
9292         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9293                 ipat = VMX_EPT_IPAT_BIT;
9294                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9295                         cache = MTRR_TYPE_WRBACK;
9296                 else
9297                         cache = MTRR_TYPE_UNCACHABLE;
9298                 goto exit;
9299         }
9300
9301         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9302
9303 exit:
9304         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9305 }
9306
9307 static int vmx_get_lpage_level(void)
9308 {
9309         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9310                 return PT_DIRECTORY_LEVEL;
9311         else
9312                 /* For shadow and EPT supported 1GB page */
9313                 return PT_PDPE_LEVEL;
9314 }
9315
9316 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9317 {
9318         /*
9319          * These bits in the secondary execution controls field
9320          * are dynamic, the others are mostly based on the hypervisor
9321          * architecture and the guest's CPUID.  Do not touch the
9322          * dynamic bits.
9323          */
9324         u32 mask =
9325                 SECONDARY_EXEC_SHADOW_VMCS |
9326                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9327                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9328
9329         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9330
9331         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9332                      (new_ctl & ~mask) | (cur_ctl & mask));
9333 }
9334
9335 /*
9336  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9337  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9338  */
9339 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9340 {
9341         struct vcpu_vmx *vmx = to_vmx(vcpu);
9342         struct kvm_cpuid_entry2 *entry;
9343
9344         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9345         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9346
9347 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9348         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9349                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9350 } while (0)
9351
9352         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9353         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9354         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9355         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9356         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9357         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9358         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9359         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9360         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9361         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9362         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9363         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9364         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9365         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9366         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9367
9368         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9369         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9370         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9371         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9372         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9373         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9374         cr4_fixed1_update(bit(11),            ecx, bit(2));
9375
9376 #undef cr4_fixed1_update
9377 }
9378
9379 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9380 {
9381         struct kvm_cpuid_entry2 *best;
9382         struct vcpu_vmx *vmx = to_vmx(vcpu);
9383         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9384
9385         if (vmx_rdtscp_supported()) {
9386                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9387                 if (!rdtscp_enabled)
9388                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9389
9390                 if (nested) {
9391                         if (rdtscp_enabled)
9392                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9393                                         SECONDARY_EXEC_RDTSCP;
9394                         else
9395                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9396                                         ~SECONDARY_EXEC_RDTSCP;
9397                 }
9398         }
9399
9400         /* Exposing INVPCID only when PCID is exposed */
9401         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9402         if (vmx_invpcid_supported() &&
9403             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9404             !guest_cpuid_has_pcid(vcpu))) {
9405                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9406
9407                 if (best)
9408                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9409         }
9410
9411         if (cpu_has_secondary_exec_ctrls())
9412                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9413
9414         if (nested_vmx_allowed(vcpu))
9415                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9416                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9417         else
9418                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9419                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9420
9421         if (nested_vmx_allowed(vcpu))
9422                 nested_vmx_cr_fixed1_bits_update(vcpu);
9423 }
9424
9425 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9426 {
9427         if (func == 1 && nested)
9428                 entry->ecx |= bit(X86_FEATURE_VMX);
9429 }
9430
9431 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9432                 struct x86_exception *fault)
9433 {
9434         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9435         struct vcpu_vmx *vmx = to_vmx(vcpu);
9436         u32 exit_reason;
9437         unsigned long exit_qualification = vcpu->arch.exit_qualification;
9438
9439         if (vmx->nested.pml_full) {
9440                 exit_reason = EXIT_REASON_PML_FULL;
9441                 vmx->nested.pml_full = false;
9442                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9443         } else if (fault->error_code & PFERR_RSVD_MASK)
9444                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9445         else
9446                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9447
9448         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9449         vmcs12->guest_physical_address = fault->address;
9450 }
9451
9452 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9453 {
9454         return nested_ept_get_cr3(vcpu) & VMX_EPT_AD_ENABLE_BIT;
9455 }
9456
9457 /* Callbacks for nested_ept_init_mmu_context: */
9458
9459 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9460 {
9461         /* return the page table to be shadowed - in our case, EPT12 */
9462         return get_vmcs12(vcpu)->ept_pointer;
9463 }
9464
9465 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9466 {
9467         bool wants_ad;
9468
9469         WARN_ON(mmu_is_nested(vcpu));
9470         wants_ad = nested_ept_ad_enabled(vcpu);
9471         if (wants_ad && !enable_ept_ad_bits)
9472                 return 1;
9473
9474         kvm_mmu_unload(vcpu);
9475         kvm_init_shadow_ept_mmu(vcpu,
9476                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9477                         VMX_EPT_EXECUTE_ONLY_BIT,
9478                         wants_ad);
9479         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9480         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9481         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9482
9483         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9484         return 0;
9485 }
9486
9487 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9488 {
9489         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9490 }
9491
9492 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9493                                             u16 error_code)
9494 {
9495         bool inequality, bit;
9496
9497         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9498         inequality =
9499                 (error_code & vmcs12->page_fault_error_code_mask) !=
9500                  vmcs12->page_fault_error_code_match;
9501         return inequality ^ bit;
9502 }
9503
9504 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9505                 struct x86_exception *fault)
9506 {
9507         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9508
9509         WARN_ON(!is_guest_mode(vcpu));
9510
9511         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9512                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9513                                   vmcs_read32(VM_EXIT_INTR_INFO),
9514                                   vmcs_readl(EXIT_QUALIFICATION));
9515         else
9516                 kvm_inject_page_fault(vcpu, fault);
9517 }
9518
9519 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9520                                                struct vmcs12 *vmcs12);
9521
9522 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9523                                         struct vmcs12 *vmcs12)
9524 {
9525         struct vcpu_vmx *vmx = to_vmx(vcpu);
9526         u64 hpa;
9527
9528         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9529                 /*
9530                  * Translate L1 physical address to host physical
9531                  * address for vmcs02. Keep the page pinned, so this
9532                  * physical address remains valid. We keep a reference
9533                  * to it so we can release it later.
9534                  */
9535                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9536                         nested_release_page(vmx->nested.apic_access_page);
9537                 vmx->nested.apic_access_page =
9538                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9539                 /*
9540                  * If translation failed, no matter: This feature asks
9541                  * to exit when accessing the given address, and if it
9542                  * can never be accessed, this feature won't do
9543                  * anything anyway.
9544                  */
9545                 if (vmx->nested.apic_access_page) {
9546                         hpa = page_to_phys(vmx->nested.apic_access_page);
9547                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9548                 } else {
9549                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9550                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9551                 }
9552         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9553                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9554                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9555                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9556                 kvm_vcpu_reload_apic_access_page(vcpu);
9557         }
9558
9559         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9560                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9561                         nested_release_page(vmx->nested.virtual_apic_page);
9562                 vmx->nested.virtual_apic_page =
9563                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9564
9565                 /*
9566                  * If translation failed, VM entry will fail because
9567                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9568                  * Failing the vm entry is _not_ what the processor
9569                  * does but it's basically the only possibility we
9570                  * have.  We could still enter the guest if CR8 load
9571                  * exits are enabled, CR8 store exits are enabled, and
9572                  * virtualize APIC access is disabled; in this case
9573                  * the processor would never use the TPR shadow and we
9574                  * could simply clear the bit from the execution
9575                  * control.  But such a configuration is useless, so
9576                  * let's keep the code simple.
9577                  */
9578                 if (vmx->nested.virtual_apic_page) {
9579                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9580                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9581                 }
9582         }
9583
9584         if (nested_cpu_has_posted_intr(vmcs12)) {
9585                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9586                         kunmap(vmx->nested.pi_desc_page);
9587                         nested_release_page(vmx->nested.pi_desc_page);
9588                 }
9589                 vmx->nested.pi_desc_page =
9590                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9591                 vmx->nested.pi_desc =
9592                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9593                 if (!vmx->nested.pi_desc) {
9594                         nested_release_page_clean(vmx->nested.pi_desc_page);
9595                         return;
9596                 }
9597                 vmx->nested.pi_desc =
9598                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9599                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9600                         (PAGE_SIZE - 1)));
9601                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9602                         page_to_phys(vmx->nested.pi_desc_page) +
9603                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9604                         (PAGE_SIZE - 1)));
9605         }
9606         if (cpu_has_vmx_msr_bitmap() &&
9607             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9608             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9609                 ;
9610         else
9611                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9612                                 CPU_BASED_USE_MSR_BITMAPS);
9613 }
9614
9615 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9616 {
9617         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9618         struct vcpu_vmx *vmx = to_vmx(vcpu);
9619
9620         if (vcpu->arch.virtual_tsc_khz == 0)
9621                 return;
9622
9623         /* Make sure short timeouts reliably trigger an immediate vmexit.
9624          * hrtimer_start does not guarantee this. */
9625         if (preemption_timeout <= 1) {
9626                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9627                 return;
9628         }
9629
9630         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9631         preemption_timeout *= 1000000;
9632         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9633         hrtimer_start(&vmx->nested.preemption_timer,
9634                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9635 }
9636
9637 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu *vcpu,
9638                                                struct vmcs12 *vmcs12)
9639 {
9640         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
9641                 return 0;
9642
9643         if (!page_address_valid(vcpu, vmcs12->io_bitmap_a) ||
9644             !page_address_valid(vcpu, vmcs12->io_bitmap_b))
9645                 return -EINVAL;
9646
9647         return 0;
9648 }
9649
9650 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9651                                                 struct vmcs12 *vmcs12)
9652 {
9653         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9654                 return 0;
9655
9656         if (!page_address_valid(vcpu, vmcs12->msr_bitmap))
9657                 return -EINVAL;
9658
9659         return 0;
9660 }
9661
9662 /*
9663  * Merge L0's and L1's MSR bitmap, return false to indicate that
9664  * we do not use the hardware.
9665  */
9666 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9667                                                struct vmcs12 *vmcs12)
9668 {
9669         int msr;
9670         struct page *page;
9671         unsigned long *msr_bitmap_l1;
9672         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9673
9674         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9675         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9676                 return false;
9677
9678         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9679         if (!page)
9680                 return false;
9681         msr_bitmap_l1 = (unsigned long *)kmap(page);
9682
9683         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9684
9685         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9686                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9687                         for (msr = 0x800; msr <= 0x8ff; msr++)
9688                                 nested_vmx_disable_intercept_for_msr(
9689                                         msr_bitmap_l1, msr_bitmap_l0,
9690                                         msr, MSR_TYPE_R);
9691
9692                 nested_vmx_disable_intercept_for_msr(
9693                                 msr_bitmap_l1, msr_bitmap_l0,
9694                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9695                                 MSR_TYPE_R | MSR_TYPE_W);
9696
9697                 if (nested_cpu_has_vid(vmcs12)) {
9698                         nested_vmx_disable_intercept_for_msr(
9699                                 msr_bitmap_l1, msr_bitmap_l0,
9700                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9701                                 MSR_TYPE_W);
9702                         nested_vmx_disable_intercept_for_msr(
9703                                 msr_bitmap_l1, msr_bitmap_l0,
9704                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9705                                 MSR_TYPE_W);
9706                 }
9707         }
9708         kunmap(page);
9709         nested_release_page_clean(page);
9710
9711         return true;
9712 }
9713
9714 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9715                                            struct vmcs12 *vmcs12)
9716 {
9717         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9718             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9719             !nested_cpu_has_vid(vmcs12) &&
9720             !nested_cpu_has_posted_intr(vmcs12))
9721                 return 0;
9722
9723         /*
9724          * If virtualize x2apic mode is enabled,
9725          * virtualize apic access must be disabled.
9726          */
9727         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9728             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9729                 return -EINVAL;
9730
9731         /*
9732          * If virtual interrupt delivery is enabled,
9733          * we must exit on external interrupts.
9734          */
9735         if (nested_cpu_has_vid(vmcs12) &&
9736            !nested_exit_on_intr(vcpu))
9737                 return -EINVAL;
9738
9739         /*
9740          * bits 15:8 should be zero in posted_intr_nv,
9741          * the descriptor address has been already checked
9742          * in nested_get_vmcs12_pages.
9743          */
9744         if (nested_cpu_has_posted_intr(vmcs12) &&
9745            (!nested_cpu_has_vid(vmcs12) ||
9746             !nested_exit_intr_ack_set(vcpu) ||
9747             vmcs12->posted_intr_nv & 0xff00))
9748                 return -EINVAL;
9749
9750         /* tpr shadow is needed by all apicv features. */
9751         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9752                 return -EINVAL;
9753
9754         return 0;
9755 }
9756
9757 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9758                                        unsigned long count_field,
9759                                        unsigned long addr_field)
9760 {
9761         int maxphyaddr;
9762         u64 count, addr;
9763
9764         if (vmcs12_read_any(vcpu, count_field, &count) ||
9765             vmcs12_read_any(vcpu, addr_field, &addr)) {
9766                 WARN_ON(1);
9767                 return -EINVAL;
9768         }
9769         if (count == 0)
9770                 return 0;
9771         maxphyaddr = cpuid_maxphyaddr(vcpu);
9772         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9773             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9774                 pr_debug_ratelimited(
9775                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9776                         addr_field, maxphyaddr, count, addr);
9777                 return -EINVAL;
9778         }
9779         return 0;
9780 }
9781
9782 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9783                                                 struct vmcs12 *vmcs12)
9784 {
9785         if (vmcs12->vm_exit_msr_load_count == 0 &&
9786             vmcs12->vm_exit_msr_store_count == 0 &&
9787             vmcs12->vm_entry_msr_load_count == 0)
9788                 return 0; /* Fast path */
9789         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9790                                         VM_EXIT_MSR_LOAD_ADDR) ||
9791             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9792                                         VM_EXIT_MSR_STORE_ADDR) ||
9793             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9794                                         VM_ENTRY_MSR_LOAD_ADDR))
9795                 return -EINVAL;
9796         return 0;
9797 }
9798
9799 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9800                                          struct vmcs12 *vmcs12)
9801 {
9802         u64 address = vmcs12->pml_address;
9803         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9804
9805         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9806                 if (!nested_cpu_has_ept(vmcs12) ||
9807                     !IS_ALIGNED(address, 4096)  ||
9808                     address >> maxphyaddr)
9809                         return -EINVAL;
9810         }
9811
9812         return 0;
9813 }
9814
9815 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9816                                        struct vmx_msr_entry *e)
9817 {
9818         /* x2APIC MSR accesses are not allowed */
9819         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9820                 return -EINVAL;
9821         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9822             e->index == MSR_IA32_UCODE_REV)
9823                 return -EINVAL;
9824         if (e->reserved != 0)
9825                 return -EINVAL;
9826         return 0;
9827 }
9828
9829 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9830                                      struct vmx_msr_entry *e)
9831 {
9832         if (e->index == MSR_FS_BASE ||
9833             e->index == MSR_GS_BASE ||
9834             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9835             nested_vmx_msr_check_common(vcpu, e))
9836                 return -EINVAL;
9837         return 0;
9838 }
9839
9840 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9841                                       struct vmx_msr_entry *e)
9842 {
9843         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9844             nested_vmx_msr_check_common(vcpu, e))
9845                 return -EINVAL;
9846         return 0;
9847 }
9848
9849 /*
9850  * Load guest's/host's msr at nested entry/exit.
9851  * return 0 for success, entry index for failure.
9852  */
9853 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9854 {
9855         u32 i;
9856         struct vmx_msr_entry e;
9857         struct msr_data msr;
9858
9859         msr.host_initiated = false;
9860         for (i = 0; i < count; i++) {
9861                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9862                                         &e, sizeof(e))) {
9863                         pr_debug_ratelimited(
9864                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9865                                 __func__, i, gpa + i * sizeof(e));
9866                         goto fail;
9867                 }
9868                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9869                         pr_debug_ratelimited(
9870                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9871                                 __func__, i, e.index, e.reserved);
9872                         goto fail;
9873                 }
9874                 msr.index = e.index;
9875                 msr.data = e.value;
9876                 if (kvm_set_msr(vcpu, &msr)) {
9877                         pr_debug_ratelimited(
9878                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9879                                 __func__, i, e.index, e.value);
9880                         goto fail;
9881                 }
9882         }
9883         return 0;
9884 fail:
9885         return i + 1;
9886 }
9887
9888 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9889 {
9890         u32 i;
9891         struct vmx_msr_entry e;
9892
9893         for (i = 0; i < count; i++) {
9894                 struct msr_data msr_info;
9895                 if (kvm_vcpu_read_guest(vcpu,
9896                                         gpa + i * sizeof(e),
9897                                         &e, 2 * sizeof(u32))) {
9898                         pr_debug_ratelimited(
9899                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9900                                 __func__, i, gpa + i * sizeof(e));
9901                         return -EINVAL;
9902                 }
9903                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9904                         pr_debug_ratelimited(
9905                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9906                                 __func__, i, e.index, e.reserved);
9907                         return -EINVAL;
9908                 }
9909                 msr_info.host_initiated = false;
9910                 msr_info.index = e.index;
9911                 if (kvm_get_msr(vcpu, &msr_info)) {
9912                         pr_debug_ratelimited(
9913                                 "%s cannot read MSR (%u, 0x%x)\n",
9914                                 __func__, i, e.index);
9915                         return -EINVAL;
9916                 }
9917                 if (kvm_vcpu_write_guest(vcpu,
9918                                          gpa + i * sizeof(e) +
9919                                              offsetof(struct vmx_msr_entry, value),
9920                                          &msr_info.data, sizeof(msr_info.data))) {
9921                         pr_debug_ratelimited(
9922                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9923                                 __func__, i, e.index, msr_info.data);
9924                         return -EINVAL;
9925                 }
9926         }
9927         return 0;
9928 }
9929
9930 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9931 {
9932         unsigned long invalid_mask;
9933
9934         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9935         return (val & invalid_mask) == 0;
9936 }
9937
9938 /*
9939  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9940  * emulating VM entry into a guest with EPT enabled.
9941  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9942  * is assigned to entry_failure_code on failure.
9943  */
9944 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9945                                u32 *entry_failure_code)
9946 {
9947         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9948                 if (!nested_cr3_valid(vcpu, cr3)) {
9949                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9950                         return 1;
9951                 }
9952
9953                 /*
9954                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9955                  * must not be dereferenced.
9956                  */
9957                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9958                     !nested_ept) {
9959                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9960                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9961                                 return 1;
9962                         }
9963                 }
9964
9965                 vcpu->arch.cr3 = cr3;
9966                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9967         }
9968
9969         kvm_mmu_reset_context(vcpu);
9970         return 0;
9971 }
9972
9973 /*
9974  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9975  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9976  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9977  * guest in a way that will both be appropriate to L1's requests, and our
9978  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9979  * function also has additional necessary side-effects, like setting various
9980  * vcpu->arch fields.
9981  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9982  * is assigned to entry_failure_code on failure.
9983  */
9984 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9985                           bool from_vmentry, u32 *entry_failure_code)
9986 {
9987         struct vcpu_vmx *vmx = to_vmx(vcpu);
9988         u32 exec_control, vmcs12_exec_ctrl;
9989
9990         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9991         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9992         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9993         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9994         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9995         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9996         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9997         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9998         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9999         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10000         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10001         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10002         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10003         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10004         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10005         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10006         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10007         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10008         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10009         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10010         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10011         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10012         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10013         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10014         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10015         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10016         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10017         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10018         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10019         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10020         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10021         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10022         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10023         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10024         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10025         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10026
10027         if (from_vmentry &&
10028             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10029                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10030                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10031         } else {
10032                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10033                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10034         }
10035         if (from_vmentry) {
10036                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10037                              vmcs12->vm_entry_intr_info_field);
10038                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10039                              vmcs12->vm_entry_exception_error_code);
10040                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10041                              vmcs12->vm_entry_instruction_len);
10042                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10043                              vmcs12->guest_interruptibility_info);
10044         } else {
10045                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10046         }
10047         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10048         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10049         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10050                 vmcs12->guest_pending_dbg_exceptions);
10051         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10052         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10053
10054         if (nested_cpu_has_xsaves(vmcs12))
10055                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10056         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10057
10058         exec_control = vmcs12->pin_based_vm_exec_control;
10059
10060         /* Preemption timer setting is only taken from vmcs01.  */
10061         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10062         exec_control |= vmcs_config.pin_based_exec_ctrl;
10063         if (vmx->hv_deadline_tsc == -1)
10064                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10065
10066         /* Posted interrupts setting is only taken from vmcs12.  */
10067         if (nested_cpu_has_posted_intr(vmcs12)) {
10068                 /*
10069                  * Note that we use L0's vector here and in
10070                  * vmx_deliver_nested_posted_interrupt.
10071                  */
10072                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10073                 vmx->nested.pi_pending = false;
10074                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10075         } else {
10076                 exec_control &= ~PIN_BASED_POSTED_INTR;
10077         }
10078
10079         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10080
10081         vmx->nested.preemption_timer_expired = false;
10082         if (nested_cpu_has_preemption_timer(vmcs12))
10083                 vmx_start_preemption_timer(vcpu);
10084
10085         /*
10086          * Whether page-faults are trapped is determined by a combination of
10087          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10088          * If enable_ept, L0 doesn't care about page faults and we should
10089          * set all of these to L1's desires. However, if !enable_ept, L0 does
10090          * care about (at least some) page faults, and because it is not easy
10091          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10092          * to exit on each and every L2 page fault. This is done by setting
10093          * MASK=MATCH=0 and (see below) EB.PF=1.
10094          * Note that below we don't need special code to set EB.PF beyond the
10095          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10096          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10097          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10098          *
10099          * A problem with this approach (when !enable_ept) is that L1 may be
10100          * injected with more page faults than it asked for. This could have
10101          * caused problems, but in practice existing hypervisors don't care.
10102          * To fix this, we will need to emulate the PFEC checking (on the L1
10103          * page tables), using walk_addr(), when injecting PFs to L1.
10104          */
10105         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10106                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10107         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10108                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10109
10110         if (cpu_has_secondary_exec_ctrls()) {
10111                 exec_control = vmx_secondary_exec_control(vmx);
10112
10113                 /* Take the following fields only from vmcs12 */
10114                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10115                                   SECONDARY_EXEC_RDTSCP |
10116                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10117                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10118                 if (nested_cpu_has(vmcs12,
10119                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10120                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10121                                 ~SECONDARY_EXEC_ENABLE_PML;
10122                         exec_control |= vmcs12_exec_ctrl;
10123                 }
10124
10125                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10126                         vmcs_write64(EOI_EXIT_BITMAP0,
10127                                 vmcs12->eoi_exit_bitmap0);
10128                         vmcs_write64(EOI_EXIT_BITMAP1,
10129                                 vmcs12->eoi_exit_bitmap1);
10130                         vmcs_write64(EOI_EXIT_BITMAP2,
10131                                 vmcs12->eoi_exit_bitmap2);
10132                         vmcs_write64(EOI_EXIT_BITMAP3,
10133                                 vmcs12->eoi_exit_bitmap3);
10134                         vmcs_write16(GUEST_INTR_STATUS,
10135                                 vmcs12->guest_intr_status);
10136                 }
10137
10138                 /*
10139                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10140                  * nested_get_vmcs12_pages will either fix it up or
10141                  * remove the VM execution control.
10142                  */
10143                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10144                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10145
10146                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10147         }
10148
10149
10150         /*
10151          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10152          * Some constant fields are set here by vmx_set_constant_host_state().
10153          * Other fields are different per CPU, and will be set later when
10154          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10155          */
10156         vmx_set_constant_host_state(vmx);
10157
10158         /*
10159          * Set the MSR load/store lists to match L0's settings.
10160          */
10161         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10162         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10163         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10164         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10165         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10166
10167         /*
10168          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10169          * entry, but only if the current (host) sp changed from the value
10170          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10171          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10172          * here we just force the write to happen on entry.
10173          */
10174         vmx->host_rsp = 0;
10175
10176         exec_control = vmx_exec_control(vmx); /* L0's desires */
10177         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10178         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10179         exec_control &= ~CPU_BASED_TPR_SHADOW;
10180         exec_control |= vmcs12->cpu_based_vm_exec_control;
10181
10182         /*
10183          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10184          * nested_get_vmcs12_pages can't fix it up, the illegal value
10185          * will result in a VM entry failure.
10186          */
10187         if (exec_control & CPU_BASED_TPR_SHADOW) {
10188                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10189                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10190         }
10191
10192         /*
10193          * Merging of IO bitmap not currently supported.
10194          * Rather, exit every time.
10195          */
10196         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10197         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10198
10199         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10200
10201         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10202          * bitwise-or of what L1 wants to trap for L2, and what we want to
10203          * trap. Note that CR0.TS also needs updating - we do this later.
10204          */
10205         update_exception_bitmap(vcpu);
10206         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10207         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10208
10209         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10210          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10211          * bits are further modified by vmx_set_efer() below.
10212          */
10213         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10214
10215         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10216          * emulated by vmx_set_efer(), below.
10217          */
10218         vm_entry_controls_init(vmx,
10219                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10220                         ~VM_ENTRY_IA32E_MODE) |
10221                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10222
10223         if (from_vmentry &&
10224             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10225                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10226                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10227         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10228                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10229         }
10230
10231         set_cr4_guest_host_mask(vmx);
10232
10233         if (from_vmentry &&
10234             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10235                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10236
10237         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10238                 vmcs_write64(TSC_OFFSET,
10239                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10240         else
10241                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10242         if (kvm_has_tsc_control)
10243                 decache_tsc_multiplier(vmx);
10244
10245         if (enable_vpid) {
10246                 /*
10247                  * There is no direct mapping between vpid02 and vpid12, the
10248                  * vpid02 is per-vCPU for L0 and reused while the value of
10249                  * vpid12 is changed w/ one invvpid during nested vmentry.
10250                  * The vpid12 is allocated by L1 for L2, so it will not
10251                  * influence global bitmap(for vpid01 and vpid02 allocation)
10252                  * even if spawn a lot of nested vCPUs.
10253                  */
10254                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10255                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10256                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10257                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10258                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10259                         }
10260                 } else {
10261                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10262                         vmx_flush_tlb(vcpu);
10263                 }
10264
10265         }
10266
10267         if (enable_pml) {
10268                 /*
10269                  * Conceptually we want to copy the PML address and index from
10270                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10271                  * since we always flush the log on each vmexit, this happens
10272                  * to be equivalent to simply resetting the fields in vmcs02.
10273                  */
10274                 ASSERT(vmx->pml_pg);
10275                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10276                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10277         }
10278
10279         if (nested_cpu_has_ept(vmcs12)) {
10280                 if (nested_ept_init_mmu_context(vcpu)) {
10281                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10282                         return 1;
10283                 }
10284         } else if (nested_cpu_has2(vmcs12,
10285                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10286                 vmx_flush_tlb_ept_only(vcpu);
10287         }
10288
10289         /*
10290          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10291          * bits which we consider mandatory enabled.
10292          * The CR0_READ_SHADOW is what L2 should have expected to read given
10293          * the specifications by L1; It's not enough to take
10294          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10295          * have more bits than L1 expected.
10296          */
10297         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10298         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10299
10300         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10301         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10302
10303         if (from_vmentry &&
10304             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10305                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10306         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10307                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10308         else
10309                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10310         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10311         vmx_set_efer(vcpu, vcpu->arch.efer);
10312
10313         /* Shadow page tables on either EPT or shadow page tables. */
10314         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10315                                 entry_failure_code))
10316                 return 1;
10317
10318         if (!enable_ept)
10319                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10320
10321         /*
10322          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10323          */
10324         if (enable_ept) {
10325                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10326                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10327                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10328                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10329         }
10330
10331         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10332         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10333         return 0;
10334 }
10335
10336 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10337 {
10338         struct vcpu_vmx *vmx = to_vmx(vcpu);
10339
10340         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10341             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10342                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10343
10344         if (nested_vmx_check_io_bitmap_controls(vcpu, vmcs12))
10345                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10346
10347         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10348                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10349
10350         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10351                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10352
10353         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10354                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10355
10356         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10357                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10358
10359         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10360                                 vmx->nested.nested_vmx_procbased_ctls_low,
10361                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10362             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10363              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10364                                  vmx->nested.nested_vmx_secondary_ctls_low,
10365                                  vmx->nested.nested_vmx_secondary_ctls_high)) ||
10366             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10367                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10368                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10369             !vmx_control_verify(vmcs12->vm_exit_controls,
10370                                 vmx->nested.nested_vmx_exit_ctls_low,
10371                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10372             !vmx_control_verify(vmcs12->vm_entry_controls,
10373                                 vmx->nested.nested_vmx_entry_ctls_low,
10374                                 vmx->nested.nested_vmx_entry_ctls_high))
10375                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10376
10377         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10378                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10379
10380         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10381             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10382             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10383                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10384
10385         return 0;
10386 }
10387
10388 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10389                                   u32 *exit_qual)
10390 {
10391         bool ia32e;
10392
10393         *exit_qual = ENTRY_FAIL_DEFAULT;
10394
10395         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10396             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10397                 return 1;
10398
10399         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10400             vmcs12->vmcs_link_pointer != -1ull) {
10401                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10402                 return 1;
10403         }
10404
10405         /*
10406          * If the load IA32_EFER VM-entry control is 1, the following checks
10407          * are performed on the field for the IA32_EFER MSR:
10408          * - Bits reserved in the IA32_EFER MSR must be 0.
10409          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10410          *   the IA-32e mode guest VM-exit control. It must also be identical
10411          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10412          *   CR0.PG) is 1.
10413          */
10414         if (to_vmx(vcpu)->nested.nested_run_pending &&
10415             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10416                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10417                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10418                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10419                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10420                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10421                         return 1;
10422         }
10423
10424         /*
10425          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10426          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10427          * the values of the LMA and LME bits in the field must each be that of
10428          * the host address-space size VM-exit control.
10429          */
10430         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10431                 ia32e = (vmcs12->vm_exit_controls &
10432                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10433                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10434                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10435                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10436                         return 1;
10437         }
10438
10439         return 0;
10440 }
10441
10442 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10443 {
10444         struct vcpu_vmx *vmx = to_vmx(vcpu);
10445         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10446         struct loaded_vmcs *vmcs02;
10447         u32 msr_entry_idx;
10448         u32 exit_qual;
10449
10450         vmcs02 = nested_get_current_vmcs02(vmx);
10451         if (!vmcs02)
10452                 return -ENOMEM;
10453
10454         enter_guest_mode(vcpu);
10455
10456         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10457                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10458
10459         vmx_switch_vmcs(vcpu, vmcs02);
10460         vmx_segment_cache_clear(vmx);
10461
10462         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10463                 leave_guest_mode(vcpu);
10464                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10465                 nested_vmx_entry_failure(vcpu, vmcs12,
10466                                          EXIT_REASON_INVALID_STATE, exit_qual);
10467                 return 1;
10468         }
10469
10470         nested_get_vmcs12_pages(vcpu, vmcs12);
10471
10472         msr_entry_idx = nested_vmx_load_msr(vcpu,
10473                                             vmcs12->vm_entry_msr_load_addr,
10474                                             vmcs12->vm_entry_msr_load_count);
10475         if (msr_entry_idx) {
10476                 leave_guest_mode(vcpu);
10477                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10478                 nested_vmx_entry_failure(vcpu, vmcs12,
10479                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10480                 return 1;
10481         }
10482
10483         /*
10484          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10485          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10486          * returned as far as L1 is concerned. It will only return (and set
10487          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10488          */
10489         return 0;
10490 }
10491
10492 /*
10493  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10494  * for running an L2 nested guest.
10495  */
10496 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10497 {
10498         struct vmcs12 *vmcs12;
10499         struct vcpu_vmx *vmx = to_vmx(vcpu);
10500         u32 interrupt_shadow = vmx_get_interrupt_shadow(vcpu);
10501         u32 exit_qual;
10502         int ret;
10503
10504         if (!nested_vmx_check_permission(vcpu))
10505                 return 1;
10506
10507         if (!nested_vmx_check_vmcs12(vcpu))
10508                 goto out;
10509
10510         vmcs12 = get_vmcs12(vcpu);
10511
10512         if (enable_shadow_vmcs)
10513                 copy_shadow_to_vmcs12(vmx);
10514
10515         /*
10516          * The nested entry process starts with enforcing various prerequisites
10517          * on vmcs12 as required by the Intel SDM, and act appropriately when
10518          * they fail: As the SDM explains, some conditions should cause the
10519          * instruction to fail, while others will cause the instruction to seem
10520          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10521          * To speed up the normal (success) code path, we should avoid checking
10522          * for misconfigurations which will anyway be caught by the processor
10523          * when using the merged vmcs02.
10524          */
10525         if (interrupt_shadow & KVM_X86_SHADOW_INT_MOV_SS) {
10526                 nested_vmx_failValid(vcpu,
10527                                      VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS);
10528                 goto out;
10529         }
10530
10531         if (vmcs12->launch_state == launch) {
10532                 nested_vmx_failValid(vcpu,
10533                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10534                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10535                 goto out;
10536         }
10537
10538         ret = check_vmentry_prereqs(vcpu, vmcs12);
10539         if (ret) {
10540                 nested_vmx_failValid(vcpu, ret);
10541                 goto out;
10542         }
10543
10544         /*
10545          * After this point, the trap flag no longer triggers a singlestep trap
10546          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10547          * This is not 100% correct; for performance reasons, we delegate most
10548          * of the checks on host state to the processor.  If those fail,
10549          * the singlestep trap is missed.
10550          */
10551         skip_emulated_instruction(vcpu);
10552
10553         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10554         if (ret) {
10555                 nested_vmx_entry_failure(vcpu, vmcs12,
10556                                          EXIT_REASON_INVALID_STATE, exit_qual);
10557                 return 1;
10558         }
10559
10560         /*
10561          * We're finally done with prerequisite checking, and can start with
10562          * the nested entry.
10563          */
10564
10565         ret = enter_vmx_non_root_mode(vcpu, true);
10566         if (ret)
10567                 return ret;
10568
10569         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10570                 return kvm_vcpu_halt(vcpu);
10571
10572         vmx->nested.nested_run_pending = 1;
10573
10574         return 1;
10575
10576 out:
10577         return kvm_skip_emulated_instruction(vcpu);
10578 }
10579
10580 /*
10581  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10582  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10583  * This function returns the new value we should put in vmcs12.guest_cr0.
10584  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10585  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10586  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10587  *     didn't trap the bit, because if L1 did, so would L0).
10588  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10589  *     been modified by L2, and L1 knows it. So just leave the old value of
10590  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10591  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10592  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10593  *     changed these bits, and therefore they need to be updated, but L0
10594  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10595  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10596  */
10597 static inline unsigned long
10598 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10599 {
10600         return
10601         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10602         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10603         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10604                         vcpu->arch.cr0_guest_owned_bits));
10605 }
10606
10607 static inline unsigned long
10608 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10609 {
10610         return
10611         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10612         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10613         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10614                         vcpu->arch.cr4_guest_owned_bits));
10615 }
10616
10617 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10618                                        struct vmcs12 *vmcs12)
10619 {
10620         u32 idt_vectoring;
10621         unsigned int nr;
10622
10623         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10624                 nr = vcpu->arch.exception.nr;
10625                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10626
10627                 if (kvm_exception_is_soft(nr)) {
10628                         vmcs12->vm_exit_instruction_len =
10629                                 vcpu->arch.event_exit_inst_len;
10630                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10631                 } else
10632                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10633
10634                 if (vcpu->arch.exception.has_error_code) {
10635                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10636                         vmcs12->idt_vectoring_error_code =
10637                                 vcpu->arch.exception.error_code;
10638                 }
10639
10640                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10641         } else if (vcpu->arch.nmi_injected) {
10642                 vmcs12->idt_vectoring_info_field =
10643                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10644         } else if (vcpu->arch.interrupt.pending) {
10645                 nr = vcpu->arch.interrupt.nr;
10646                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10647
10648                 if (vcpu->arch.interrupt.soft) {
10649                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10650                         vmcs12->vm_entry_instruction_len =
10651                                 vcpu->arch.event_exit_inst_len;
10652                 } else
10653                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10654
10655                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10656         }
10657 }
10658
10659 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10660 {
10661         struct vcpu_vmx *vmx = to_vmx(vcpu);
10662
10663         if (vcpu->arch.exception.pending ||
10664                 vcpu->arch.nmi_injected ||
10665                 vcpu->arch.interrupt.pending)
10666                 return -EBUSY;
10667
10668         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10669             vmx->nested.preemption_timer_expired) {
10670                 if (vmx->nested.nested_run_pending)
10671                         return -EBUSY;
10672                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10673                 return 0;
10674         }
10675
10676         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10677                 if (vmx->nested.nested_run_pending)
10678                         return -EBUSY;
10679                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10680                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10681                                   INTR_INFO_VALID_MASK, 0);
10682                 /*
10683                  * The NMI-triggered VM exit counts as injection:
10684                  * clear this one and block further NMIs.
10685                  */
10686                 vcpu->arch.nmi_pending = 0;
10687                 vmx_set_nmi_mask(vcpu, true);
10688                 return 0;
10689         }
10690
10691         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10692             nested_exit_on_intr(vcpu)) {
10693                 if (vmx->nested.nested_run_pending)
10694                         return -EBUSY;
10695                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10696                 return 0;
10697         }
10698
10699         vmx_complete_nested_posted_interrupt(vcpu);
10700         return 0;
10701 }
10702
10703 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10704 {
10705         ktime_t remaining =
10706                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10707         u64 value;
10708
10709         if (ktime_to_ns(remaining) <= 0)
10710                 return 0;
10711
10712         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10713         do_div(value, 1000000);
10714         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10715 }
10716
10717 /*
10718  * Update the guest state fields of vmcs12 to reflect changes that
10719  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10720  * VM-entry controls is also updated, since this is really a guest
10721  * state bit.)
10722  */
10723 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10724 {
10725         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10726         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10727
10728         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10729         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10730         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10731
10732         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10733         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10734         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10735         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10736         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10737         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10738         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10739         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10740         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10741         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10742         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10743         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10744         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10745         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10746         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10747         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10748         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10749         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10750         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10751         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10752         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10753         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10754         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10755         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10756         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10757         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10758         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10759         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10760         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10761         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10762         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10763         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10764         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10765         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10766         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10767         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10768
10769         vmcs12->guest_interruptibility_info =
10770                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10771         vmcs12->guest_pending_dbg_exceptions =
10772                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10773         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10774                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10775         else
10776                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10777
10778         if (nested_cpu_has_preemption_timer(vmcs12)) {
10779                 if (vmcs12->vm_exit_controls &
10780                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10781                         vmcs12->vmx_preemption_timer_value =
10782                                 vmx_get_preemption_timer_value(vcpu);
10783                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10784         }
10785
10786         /*
10787          * In some cases (usually, nested EPT), L2 is allowed to change its
10788          * own CR3 without exiting. If it has changed it, we must keep it.
10789          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10790          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10791          *
10792          * Additionally, restore L2's PDPTR to vmcs12.
10793          */
10794         if (enable_ept) {
10795                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10796                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10797                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10798                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10799                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10800         }
10801
10802         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10803
10804         if (nested_cpu_has_vid(vmcs12))
10805                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10806
10807         vmcs12->vm_entry_controls =
10808                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10809                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10810
10811         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10812                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10813                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10814         }
10815
10816         /* TODO: These cannot have changed unless we have MSR bitmaps and
10817          * the relevant bit asks not to trap the change */
10818         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10819                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10820         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10821                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10822         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10823         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10824         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10825         if (kvm_mpx_supported())
10826                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10827 }
10828
10829 /*
10830  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10831  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10832  * and this function updates it to reflect the changes to the guest state while
10833  * L2 was running (and perhaps made some exits which were handled directly by L0
10834  * without going back to L1), and to reflect the exit reason.
10835  * Note that we do not have to copy here all VMCS fields, just those that
10836  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10837  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10838  * which already writes to vmcs12 directly.
10839  */
10840 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10841                            u32 exit_reason, u32 exit_intr_info,
10842                            unsigned long exit_qualification)
10843 {
10844         /* update guest state fields: */
10845         sync_vmcs12(vcpu, vmcs12);
10846
10847         /* update exit information fields: */
10848
10849         vmcs12->vm_exit_reason = exit_reason;
10850         vmcs12->exit_qualification = exit_qualification;
10851
10852         vmcs12->vm_exit_intr_info = exit_intr_info;
10853         if ((vmcs12->vm_exit_intr_info &
10854              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10855             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10856                 vmcs12->vm_exit_intr_error_code =
10857                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10858         vmcs12->idt_vectoring_info_field = 0;
10859         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10860         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10861
10862         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10863                 vmcs12->launch_state = 1;
10864
10865                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10866                  * instead of reading the real value. */
10867                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10868
10869                 /*
10870                  * Transfer the event that L0 or L1 may wanted to inject into
10871                  * L2 to IDT_VECTORING_INFO_FIELD.
10872                  */
10873                 vmcs12_save_pending_event(vcpu, vmcs12);
10874         }
10875
10876         /*
10877          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10878          * preserved above and would only end up incorrectly in L1.
10879          */
10880         vcpu->arch.nmi_injected = false;
10881         kvm_clear_exception_queue(vcpu);
10882         kvm_clear_interrupt_queue(vcpu);
10883 }
10884
10885 /*
10886  * A part of what we need to when the nested L2 guest exits and we want to
10887  * run its L1 parent, is to reset L1's guest state to the host state specified
10888  * in vmcs12.
10889  * This function is to be called not only on normal nested exit, but also on
10890  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10891  * Failures During or After Loading Guest State").
10892  * This function should be called when the active VMCS is L1's (vmcs01).
10893  */
10894 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10895                                    struct vmcs12 *vmcs12)
10896 {
10897         struct kvm_segment seg;
10898         u32 entry_failure_code;
10899
10900         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10901                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10902         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10903                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10904         else
10905                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10906         vmx_set_efer(vcpu, vcpu->arch.efer);
10907
10908         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10909         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10910         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10911         /*
10912          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10913          * actually changed, because vmx_set_cr0 refers to efer set above.
10914          *
10915          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10916          * (KVM doesn't change it);
10917          */
10918         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10919         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10920
10921         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10922         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10923         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10924
10925         nested_ept_uninit_mmu_context(vcpu);
10926
10927         /*
10928          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10929          * couldn't have changed.
10930          */
10931         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10932                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10933
10934         if (!enable_ept)
10935                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10936
10937         if (enable_vpid) {
10938                 /*
10939                  * Trivially support vpid by letting L2s share their parent
10940                  * L1's vpid. TODO: move to a more elaborate solution, giving
10941                  * each L2 its own vpid and exposing the vpid feature to L1.
10942                  */
10943                 vmx_flush_tlb(vcpu);
10944         }
10945
10946
10947         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10948         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10949         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10950         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10951         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10952
10953         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10954         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10955                 vmcs_write64(GUEST_BNDCFGS, 0);
10956
10957         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10958                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10959                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10960         }
10961         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10962                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10963                         vmcs12->host_ia32_perf_global_ctrl);
10964
10965         /* Set L1 segment info according to Intel SDM
10966             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10967         seg = (struct kvm_segment) {
10968                 .base = 0,
10969                 .limit = 0xFFFFFFFF,
10970                 .selector = vmcs12->host_cs_selector,
10971                 .type = 11,
10972                 .present = 1,
10973                 .s = 1,
10974                 .g = 1
10975         };
10976         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10977                 seg.l = 1;
10978         else
10979                 seg.db = 1;
10980         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10981         seg = (struct kvm_segment) {
10982                 .base = 0,
10983                 .limit = 0xFFFFFFFF,
10984                 .type = 3,
10985                 .present = 1,
10986                 .s = 1,
10987                 .db = 1,
10988                 .g = 1
10989         };
10990         seg.selector = vmcs12->host_ds_selector;
10991         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10992         seg.selector = vmcs12->host_es_selector;
10993         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10994         seg.selector = vmcs12->host_ss_selector;
10995         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10996         seg.selector = vmcs12->host_fs_selector;
10997         seg.base = vmcs12->host_fs_base;
10998         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10999         seg.selector = vmcs12->host_gs_selector;
11000         seg.base = vmcs12->host_gs_base;
11001         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
11002         seg = (struct kvm_segment) {
11003                 .base = vmcs12->host_tr_base,
11004                 .limit = 0x67,
11005                 .selector = vmcs12->host_tr_selector,
11006                 .type = 11,
11007                 .present = 1
11008         };
11009         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11010
11011         kvm_set_dr(vcpu, 7, 0x400);
11012         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11013
11014         if (cpu_has_vmx_msr_bitmap())
11015                 vmx_set_msr_bitmap(vcpu);
11016
11017         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11018                                 vmcs12->vm_exit_msr_load_count))
11019                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11020 }
11021
11022 /*
11023  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11024  * and modify vmcs12 to make it see what it would expect to see there if
11025  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11026  */
11027 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11028                               u32 exit_intr_info,
11029                               unsigned long exit_qualification)
11030 {
11031         struct vcpu_vmx *vmx = to_vmx(vcpu);
11032         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11033         u32 vm_inst_error = 0;
11034
11035         /* trying to cancel vmlaunch/vmresume is a bug */
11036         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11037
11038         leave_guest_mode(vcpu);
11039         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11040                        exit_qualification);
11041
11042         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11043                                  vmcs12->vm_exit_msr_store_count))
11044                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11045
11046         if (unlikely(vmx->fail))
11047                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11048
11049         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
11050
11051         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11052             && nested_exit_intr_ack_set(vcpu)) {
11053                 int irq = kvm_cpu_get_interrupt(vcpu);
11054                 WARN_ON(irq < 0);
11055                 vmcs12->vm_exit_intr_info = irq |
11056                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11057         }
11058
11059         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11060                                        vmcs12->exit_qualification,
11061                                        vmcs12->idt_vectoring_info_field,
11062                                        vmcs12->vm_exit_intr_info,
11063                                        vmcs12->vm_exit_intr_error_code,
11064                                        KVM_ISA_VMX);
11065
11066         vm_entry_controls_reset_shadow(vmx);
11067         vm_exit_controls_reset_shadow(vmx);
11068         vmx_segment_cache_clear(vmx);
11069
11070         /* if no vmcs02 cache requested, remove the one we used */
11071         if (VMCS02_POOL_SIZE == 0)
11072                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11073
11074         load_vmcs12_host_state(vcpu, vmcs12);
11075
11076         /* Update any VMCS fields that might have changed while L2 ran */
11077         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11078         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11079         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11080         if (vmx->hv_deadline_tsc == -1)
11081                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11082                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11083         else
11084                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11085                               PIN_BASED_VMX_PREEMPTION_TIMER);
11086         if (kvm_has_tsc_control)
11087                 decache_tsc_multiplier(vmx);
11088
11089         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11090                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11091                 vmx_set_virtual_x2apic_mode(vcpu,
11092                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11093         } else if (!nested_cpu_has_ept(vmcs12) &&
11094                    nested_cpu_has2(vmcs12,
11095                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11096                 vmx_flush_tlb_ept_only(vcpu);
11097         }
11098
11099         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11100         vmx->host_rsp = 0;
11101
11102         /* Unpin physical memory we referred to in vmcs02 */
11103         if (vmx->nested.apic_access_page) {
11104                 nested_release_page(vmx->nested.apic_access_page);
11105                 vmx->nested.apic_access_page = NULL;
11106         }
11107         if (vmx->nested.virtual_apic_page) {
11108                 nested_release_page(vmx->nested.virtual_apic_page);
11109                 vmx->nested.virtual_apic_page = NULL;
11110         }
11111         if (vmx->nested.pi_desc_page) {
11112                 kunmap(vmx->nested.pi_desc_page);
11113                 nested_release_page(vmx->nested.pi_desc_page);
11114                 vmx->nested.pi_desc_page = NULL;
11115                 vmx->nested.pi_desc = NULL;
11116         }
11117
11118         /*
11119          * We are now running in L2, mmu_notifier will force to reload the
11120          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11121          */
11122         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11123
11124         /*
11125          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11126          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11127          * success or failure flag accordingly.
11128          */
11129         if (unlikely(vmx->fail)) {
11130                 vmx->fail = 0;
11131                 nested_vmx_failValid(vcpu, vm_inst_error);
11132         } else
11133                 nested_vmx_succeed(vcpu);
11134         if (enable_shadow_vmcs)
11135                 vmx->nested.sync_shadow_vmcs = true;
11136
11137         /* in case we halted in L2 */
11138         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11139 }
11140
11141 /*
11142  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11143  */
11144 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11145 {
11146         if (is_guest_mode(vcpu)) {
11147                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11148                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11149         }
11150         free_nested(to_vmx(vcpu));
11151 }
11152
11153 /*
11154  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11155  * 23.7 "VM-entry failures during or after loading guest state" (this also
11156  * lists the acceptable exit-reason and exit-qualification parameters).
11157  * It should only be called before L2 actually succeeded to run, and when
11158  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11159  */
11160 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11161                         struct vmcs12 *vmcs12,
11162                         u32 reason, unsigned long qualification)
11163 {
11164         load_vmcs12_host_state(vcpu, vmcs12);
11165         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11166         vmcs12->exit_qualification = qualification;
11167         nested_vmx_succeed(vcpu);
11168         if (enable_shadow_vmcs)
11169                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11170 }
11171
11172 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11173                                struct x86_instruction_info *info,
11174                                enum x86_intercept_stage stage)
11175 {
11176         return X86EMUL_CONTINUE;
11177 }
11178
11179 #ifdef CONFIG_X86_64
11180 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11181 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11182                                   u64 divisor, u64 *result)
11183 {
11184         u64 low = a << shift, high = a >> (64 - shift);
11185
11186         /* To avoid the overflow on divq */
11187         if (high >= divisor)
11188                 return 1;
11189
11190         /* Low hold the result, high hold rem which is discarded */
11191         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11192             "rm" (divisor), "0" (low), "1" (high));
11193         *result = low;
11194
11195         return 0;
11196 }
11197
11198 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11199 {
11200         struct vcpu_vmx *vmx = to_vmx(vcpu);
11201         u64 tscl = rdtsc();
11202         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11203         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11204
11205         /* Convert to host delta tsc if tsc scaling is enabled */
11206         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11207                         u64_shl_div_u64(delta_tsc,
11208                                 kvm_tsc_scaling_ratio_frac_bits,
11209                                 vcpu->arch.tsc_scaling_ratio,
11210                                 &delta_tsc))
11211                 return -ERANGE;
11212
11213         /*
11214          * If the delta tsc can't fit in the 32 bit after the multi shift,
11215          * we can't use the preemption timer.
11216          * It's possible that it fits on later vmentries, but checking
11217          * on every vmentry is costly so we just use an hrtimer.
11218          */
11219         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11220                 return -ERANGE;
11221
11222         vmx->hv_deadline_tsc = tscl + delta_tsc;
11223         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11224                         PIN_BASED_VMX_PREEMPTION_TIMER);
11225
11226         return delta_tsc == 0;
11227 }
11228
11229 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11230 {
11231         struct vcpu_vmx *vmx = to_vmx(vcpu);
11232         vmx->hv_deadline_tsc = -1;
11233         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11234                         PIN_BASED_VMX_PREEMPTION_TIMER);
11235 }
11236 #endif
11237
11238 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11239 {
11240         if (ple_gap)
11241                 shrink_ple_window(vcpu);
11242 }
11243
11244 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11245                                      struct kvm_memory_slot *slot)
11246 {
11247         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11248         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11249 }
11250
11251 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11252                                        struct kvm_memory_slot *slot)
11253 {
11254         kvm_mmu_slot_set_dirty(kvm, slot);
11255 }
11256
11257 static void vmx_flush_log_dirty(struct kvm *kvm)
11258 {
11259         kvm_flush_pml_buffers(kvm);
11260 }
11261
11262 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11263 {
11264         struct vmcs12 *vmcs12;
11265         struct vcpu_vmx *vmx = to_vmx(vcpu);
11266         gpa_t gpa;
11267         struct page *page = NULL;
11268         u64 *pml_address;
11269
11270         if (is_guest_mode(vcpu)) {
11271                 WARN_ON_ONCE(vmx->nested.pml_full);
11272
11273                 /*
11274                  * Check if PML is enabled for the nested guest.
11275                  * Whether eptp bit 6 is set is already checked
11276                  * as part of A/D emulation.
11277                  */
11278                 vmcs12 = get_vmcs12(vcpu);
11279                 if (!nested_cpu_has_pml(vmcs12))
11280                         return 0;
11281
11282                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11283                         vmx->nested.pml_full = true;
11284                         return 1;
11285                 }
11286
11287                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11288
11289                 page = nested_get_page(vcpu, vmcs12->pml_address);
11290                 if (!page)
11291                         return 0;
11292
11293                 pml_address = kmap(page);
11294                 pml_address[vmcs12->guest_pml_index--] = gpa;
11295                 kunmap(page);
11296                 nested_release_page_clean(page);
11297         }
11298
11299         return 0;
11300 }
11301
11302 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11303                                            struct kvm_memory_slot *memslot,
11304                                            gfn_t offset, unsigned long mask)
11305 {
11306         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11307 }
11308
11309 /*
11310  * This routine does the following things for vCPU which is going
11311  * to be blocked if VT-d PI is enabled.
11312  * - Store the vCPU to the wakeup list, so when interrupts happen
11313  *   we can find the right vCPU to wake up.
11314  * - Change the Posted-interrupt descriptor as below:
11315  *      'NDST' <-- vcpu->pre_pcpu
11316  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11317  * - If 'ON' is set during this process, which means at least one
11318  *   interrupt is posted for this vCPU, we cannot block it, in
11319  *   this case, return 1, otherwise, return 0.
11320  *
11321  */
11322 static int pi_pre_block(struct kvm_vcpu *vcpu)
11323 {
11324         unsigned long flags;
11325         unsigned int dest;
11326         struct pi_desc old, new;
11327         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11328
11329         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11330                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11331                 !kvm_vcpu_apicv_active(vcpu))
11332                 return 0;
11333
11334         vcpu->pre_pcpu = vcpu->cpu;
11335         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11336                           vcpu->pre_pcpu), flags);
11337         list_add_tail(&vcpu->blocked_vcpu_list,
11338                       &per_cpu(blocked_vcpu_on_cpu,
11339                       vcpu->pre_pcpu));
11340         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11341                                vcpu->pre_pcpu), flags);
11342
11343         do {
11344                 old.control = new.control = pi_desc->control;
11345
11346                 /*
11347                  * We should not block the vCPU if
11348                  * an interrupt is posted for it.
11349                  */
11350                 if (pi_test_on(pi_desc) == 1) {
11351                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11352                                           vcpu->pre_pcpu), flags);
11353                         list_del(&vcpu->blocked_vcpu_list);
11354                         spin_unlock_irqrestore(
11355                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11356                                         vcpu->pre_pcpu), flags);
11357                         vcpu->pre_pcpu = -1;
11358
11359                         return 1;
11360                 }
11361
11362                 WARN((pi_desc->sn == 1),
11363                      "Warning: SN field of posted-interrupts "
11364                      "is set before blocking\n");
11365
11366                 /*
11367                  * Since vCPU can be preempted during this process,
11368                  * vcpu->cpu could be different with pre_pcpu, we
11369                  * need to set pre_pcpu as the destination of wakeup
11370                  * notification event, then we can find the right vCPU
11371                  * to wakeup in wakeup handler if interrupts happen
11372                  * when the vCPU is in blocked state.
11373                  */
11374                 dest = cpu_physical_id(vcpu->pre_pcpu);
11375
11376                 if (x2apic_enabled())
11377                         new.ndst = dest;
11378                 else
11379                         new.ndst = (dest << 8) & 0xFF00;
11380
11381                 /* set 'NV' to 'wakeup vector' */
11382                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11383         } while (cmpxchg(&pi_desc->control, old.control,
11384                         new.control) != old.control);
11385
11386         return 0;
11387 }
11388
11389 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11390 {
11391         if (pi_pre_block(vcpu))
11392                 return 1;
11393
11394         if (kvm_lapic_hv_timer_in_use(vcpu))
11395                 kvm_lapic_switch_to_sw_timer(vcpu);
11396
11397         return 0;
11398 }
11399
11400 static void pi_post_block(struct kvm_vcpu *vcpu)
11401 {
11402         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11403         struct pi_desc old, new;
11404         unsigned int dest;
11405         unsigned long flags;
11406
11407         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11408                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11409                 !kvm_vcpu_apicv_active(vcpu))
11410                 return;
11411
11412         do {
11413                 old.control = new.control = pi_desc->control;
11414
11415                 dest = cpu_physical_id(vcpu->cpu);
11416
11417                 if (x2apic_enabled())
11418                         new.ndst = dest;
11419                 else
11420                         new.ndst = (dest << 8) & 0xFF00;
11421
11422                 /* Allow posting non-urgent interrupts */
11423                 new.sn = 0;
11424
11425                 /* set 'NV' to 'notification vector' */
11426                 new.nv = POSTED_INTR_VECTOR;
11427         } while (cmpxchg(&pi_desc->control, old.control,
11428                         new.control) != old.control);
11429
11430         if(vcpu->pre_pcpu != -1) {
11431                 spin_lock_irqsave(
11432                         &per_cpu(blocked_vcpu_on_cpu_lock,
11433                         vcpu->pre_pcpu), flags);
11434                 list_del(&vcpu->blocked_vcpu_list);
11435                 spin_unlock_irqrestore(
11436                         &per_cpu(blocked_vcpu_on_cpu_lock,
11437                         vcpu->pre_pcpu), flags);
11438                 vcpu->pre_pcpu = -1;
11439         }
11440 }
11441
11442 static void vmx_post_block(struct kvm_vcpu *vcpu)
11443 {
11444         if (kvm_x86_ops->set_hv_timer)
11445                 kvm_lapic_switch_to_hv_timer(vcpu);
11446
11447         pi_post_block(vcpu);
11448 }
11449
11450 /*
11451  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11452  *
11453  * @kvm: kvm
11454  * @host_irq: host irq of the interrupt
11455  * @guest_irq: gsi of the interrupt
11456  * @set: set or unset PI
11457  * returns 0 on success, < 0 on failure
11458  */
11459 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11460                               uint32_t guest_irq, bool set)
11461 {
11462         struct kvm_kernel_irq_routing_entry *e;
11463         struct kvm_irq_routing_table *irq_rt;
11464         struct kvm_lapic_irq irq;
11465         struct kvm_vcpu *vcpu;
11466         struct vcpu_data vcpu_info;
11467         int idx, ret = -EINVAL;
11468
11469         if (!kvm_arch_has_assigned_device(kvm) ||
11470                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11471                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11472                 return 0;
11473
11474         idx = srcu_read_lock(&kvm->irq_srcu);
11475         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11476         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11477
11478         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11479                 if (e->type != KVM_IRQ_ROUTING_MSI)
11480                         continue;
11481                 /*
11482                  * VT-d PI cannot support posting multicast/broadcast
11483                  * interrupts to a vCPU, we still use interrupt remapping
11484                  * for these kind of interrupts.
11485                  *
11486                  * For lowest-priority interrupts, we only support
11487                  * those with single CPU as the destination, e.g. user
11488                  * configures the interrupts via /proc/irq or uses
11489                  * irqbalance to make the interrupts single-CPU.
11490                  *
11491                  * We will support full lowest-priority interrupt later.
11492                  */
11493
11494                 kvm_set_msi_irq(kvm, e, &irq);
11495                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11496                         /*
11497                          * Make sure the IRTE is in remapped mode if
11498                          * we don't handle it in posted mode.
11499                          */
11500                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11501                         if (ret < 0) {
11502                                 printk(KERN_INFO
11503                                    "failed to back to remapped mode, irq: %u\n",
11504                                    host_irq);
11505                                 goto out;
11506                         }
11507
11508                         continue;
11509                 }
11510
11511                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11512                 vcpu_info.vector = irq.vector;
11513
11514                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11515                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11516
11517                 if (set)
11518                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11519                 else {
11520                         /* suppress notification event before unposting */
11521                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11522                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11523                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11524                 }
11525
11526                 if (ret < 0) {
11527                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11528                                         __func__);
11529                         goto out;
11530                 }
11531         }
11532
11533         ret = 0;
11534 out:
11535         srcu_read_unlock(&kvm->irq_srcu, idx);
11536         return ret;
11537 }
11538
11539 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11540 {
11541         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11542                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11543                         FEATURE_CONTROL_LMCE;
11544         else
11545                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11546                         ~FEATURE_CONTROL_LMCE;
11547 }
11548
11549 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11550         .cpu_has_kvm_support = cpu_has_kvm_support,
11551         .disabled_by_bios = vmx_disabled_by_bios,
11552         .hardware_setup = hardware_setup,
11553         .hardware_unsetup = hardware_unsetup,
11554         .check_processor_compatibility = vmx_check_processor_compat,
11555         .hardware_enable = hardware_enable,
11556         .hardware_disable = hardware_disable,
11557         .cpu_has_accelerated_tpr = report_flexpriority,
11558         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11559
11560         .vcpu_create = vmx_create_vcpu,
11561         .vcpu_free = vmx_free_vcpu,
11562         .vcpu_reset = vmx_vcpu_reset,
11563
11564         .prepare_guest_switch = vmx_save_host_state,
11565         .vcpu_load = vmx_vcpu_load,
11566         .vcpu_put = vmx_vcpu_put,
11567
11568         .update_bp_intercept = update_exception_bitmap,
11569         .get_msr = vmx_get_msr,
11570         .set_msr = vmx_set_msr,
11571         .get_segment_base = vmx_get_segment_base,
11572         .get_segment = vmx_get_segment,
11573         .set_segment = vmx_set_segment,
11574         .get_cpl = vmx_get_cpl,
11575         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11576         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11577         .decache_cr3 = vmx_decache_cr3,
11578         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11579         .set_cr0 = vmx_set_cr0,
11580         .set_cr3 = vmx_set_cr3,
11581         .set_cr4 = vmx_set_cr4,
11582         .set_efer = vmx_set_efer,
11583         .get_idt = vmx_get_idt,
11584         .set_idt = vmx_set_idt,
11585         .get_gdt = vmx_get_gdt,
11586         .set_gdt = vmx_set_gdt,
11587         .get_dr6 = vmx_get_dr6,
11588         .set_dr6 = vmx_set_dr6,
11589         .set_dr7 = vmx_set_dr7,
11590         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11591         .cache_reg = vmx_cache_reg,
11592         .get_rflags = vmx_get_rflags,
11593         .set_rflags = vmx_set_rflags,
11594
11595         .get_pkru = vmx_get_pkru,
11596
11597         .tlb_flush = vmx_flush_tlb,
11598
11599         .run = vmx_vcpu_run,
11600         .handle_exit = vmx_handle_exit,
11601         .skip_emulated_instruction = skip_emulated_instruction,
11602         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11603         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11604         .patch_hypercall = vmx_patch_hypercall,
11605         .set_irq = vmx_inject_irq,
11606         .set_nmi = vmx_inject_nmi,
11607         .queue_exception = vmx_queue_exception,
11608         .cancel_injection = vmx_cancel_injection,
11609         .interrupt_allowed = vmx_interrupt_allowed,
11610         .nmi_allowed = vmx_nmi_allowed,
11611         .get_nmi_mask = vmx_get_nmi_mask,
11612         .set_nmi_mask = vmx_set_nmi_mask,
11613         .enable_nmi_window = enable_nmi_window,
11614         .enable_irq_window = enable_irq_window,
11615         .update_cr8_intercept = update_cr8_intercept,
11616         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11617         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11618         .get_enable_apicv = vmx_get_enable_apicv,
11619         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11620         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11621         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11622         .hwapic_irr_update = vmx_hwapic_irr_update,
11623         .hwapic_isr_update = vmx_hwapic_isr_update,
11624         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11625         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11626
11627         .set_tss_addr = vmx_set_tss_addr,
11628         .get_tdp_level = get_ept_level,
11629         .get_mt_mask = vmx_get_mt_mask,
11630
11631         .get_exit_info = vmx_get_exit_info,
11632
11633         .get_lpage_level = vmx_get_lpage_level,
11634
11635         .cpuid_update = vmx_cpuid_update,
11636
11637         .rdtscp_supported = vmx_rdtscp_supported,
11638         .invpcid_supported = vmx_invpcid_supported,
11639
11640         .set_supported_cpuid = vmx_set_supported_cpuid,
11641
11642         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11643
11644         .write_tsc_offset = vmx_write_tsc_offset,
11645
11646         .set_tdp_cr3 = vmx_set_cr3,
11647
11648         .check_intercept = vmx_check_intercept,
11649         .handle_external_intr = vmx_handle_external_intr,
11650         .mpx_supported = vmx_mpx_supported,
11651         .xsaves_supported = vmx_xsaves_supported,
11652
11653         .check_nested_events = vmx_check_nested_events,
11654
11655         .sched_in = vmx_sched_in,
11656
11657         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11658         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11659         .flush_log_dirty = vmx_flush_log_dirty,
11660         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11661         .write_log_dirty = vmx_write_pml_buffer,
11662
11663         .pre_block = vmx_pre_block,
11664         .post_block = vmx_post_block,
11665
11666         .pmu_ops = &intel_pmu_ops,
11667
11668         .update_pi_irte = vmx_update_pi_irte,
11669
11670 #ifdef CONFIG_X86_64
11671         .set_hv_timer = vmx_set_hv_timer,
11672         .cancel_hv_timer = vmx_cancel_hv_timer,
11673 #endif
11674
11675         .setup_mce = vmx_setup_mce,
11676 };
11677
11678 static int __init vmx_init(void)
11679 {
11680         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11681                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11682         if (r)
11683                 return r;
11684
11685 #ifdef CONFIG_KEXEC_CORE
11686         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11687                            crash_vmclear_local_loaded_vmcss);
11688 #endif
11689
11690         return 0;
11691 }
11692
11693 static void __exit vmx_exit(void)
11694 {
11695 #ifdef CONFIG_KEXEC_CORE
11696         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11697         synchronize_rcu();
11698 #endif
11699
11700         kvm_exit();
11701 }
11702
11703 module_init(vmx_init)
11704 module_exit(vmx_exit)