arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include <linux/slab.h>
  30 #include "kvm_cache_regs.h"
  31 #include "x86.h"
  32
  33 #include <asm/io.h>
  34 #include <asm/desc.h>
  35 #include <asm/vmx.h>
  36 #include <asm/virtext.h>
  37 #include <asm/mce.h>
  38
  39 #include "trace.h"
  40
  41 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  42
  43 MODULE_AUTHOR("Qumranet");
  44 MODULE_LICENSE("GPL");
  45
  46 static int __read_mostly bypass_guest_pf = 1;
  47 module_param(bypass_guest_pf, bool, S_IRUGO);
  48
  49 static int __read_mostly enable_vpid = 1;
  50 module_param_named(vpid, enable_vpid, bool, 0444);
  51
  52 static int __read_mostly flexpriority_enabled = 1;
  53 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  54
  55 static int __read_mostly enable_ept = 1;
  56 module_param_named(ept, enable_ept, bool, S_IRUGO);
  57
  58 static int __read_mostly enable_unrestricted_guest = 1;
  59 module_param_named(unrestricted_guest,
  60                         enable_unrestricted_guest, bool, S_IRUGO);
  61
  62 static int __read_mostly emulate_invalid_guest_state = 0;
  63 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  64
  65 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  66         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  67 #define KVM_GUEST_CR0_MASK                                              \
  68         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  69 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  70         (X86_CR0_WP | X86_CR0_NE)
  71 #define KVM_VM_CR0_ALWAYS_ON                                            \
  72         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  73 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  74         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  75          | X86_CR4_OSXMMEXCPT)
  76
  77 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  78 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  79
  80 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  81
  82 /*
  83  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  84  * ple_gap:    upper bound on the amount of time between two successive
  85  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  86  *             According to test, this time is usually small than 41 cycles.
  87  * ple_window: upper bound on the amount of time a guest is allowed to execute
  88  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  89  *             less than 2^12 cycles
  90  * Time is measured based on a counter that runs at the same rate as the TSC,
  91  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  92  */
  93 #define KVM_VMX_DEFAULT_PLE_GAP    41
  94 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
  95 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
  96 module_param(ple_gap, int, S_IRUGO);
  97
  98 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
  99 module_param(ple_window, int, S_IRUGO);
 100
 101 struct vmcs {
 102         u32 revision_id;
 103         u32 abort;
 104         char data[0];
 105 };
 106
 107 struct shared_msr_entry {
 108         unsigned index;
 109         u64 data;
 110         u64 mask;
 111 };
 112
 113 struct vcpu_vmx {
 114         struct kvm_vcpu       vcpu;
 115         struct list_head      local_vcpus_link;
 116         unsigned long         host_rsp;
 117         int                   launched;
 118         u8                    fail;
 119         u32                   idt_vectoring_info;
 120         struct shared_msr_entry *guest_msrs;
 121         int                   nmsrs;
 122         int                   save_nmsrs;
 123 #ifdef CONFIG_X86_64
 124         u64                   msr_host_kernel_gs_base;
 125         u64                   msr_guest_kernel_gs_base;
 126 #endif
 127         struct vmcs          *vmcs;
 128         struct {
 129                 int           loaded;
 130                 u16           fs_sel, gs_sel, ldt_sel;
 131                 int           gs_ldt_reload_needed;
 132                 int           fs_reload_needed;
 133         } host_state;
 134         struct {
 135                 int vm86_active;
 136                 ulong save_rflags;
 137                 struct kvm_save_segment {
 138                         u16 selector;
 139                         unsigned long base;
 140                         u32 limit;
 141                         u32 ar;
 142                 } tr, es, ds, fs, gs;
 143                 struct {
 144                         bool pending;
 145                         u8 vector;
 146                         unsigned rip;
 147                 } irq;
 148         } rmode;
 149         int vpid;
 150         bool emulation_required;
 151
 152         /* Support for vnmi-less CPUs */
 153         int soft_vnmi_blocked;
 154         ktime_t entry_time;
 155         s64 vnmi_blocked_time;
 156         u32 exit_reason;
 157
 158         bool rdtscp_enabled;
 159 };
 160
 161 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 162 {
 163         return container_of(vcpu, struct vcpu_vmx, vcpu);
 164 }
 165
 166 static int init_rmode(struct kvm *kvm);
 167 static u64 construct_eptp(unsigned long root_hpa);
 168
 169 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 170 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 171 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 172
 173 static unsigned long *vmx_io_bitmap_a;
 174 static unsigned long *vmx_io_bitmap_b;
 175 static unsigned long *vmx_msr_bitmap_legacy;
 176 static unsigned long *vmx_msr_bitmap_longmode;
 177
 178 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 179 static DEFINE_SPINLOCK(vmx_vpid_lock);
 180
 181 static struct vmcs_config {
 182         int size;
 183         int order;
 184         u32 revision_id;
 185         u32 pin_based_exec_ctrl;
 186         u32 cpu_based_exec_ctrl;
 187         u32 cpu_based_2nd_exec_ctrl;
 188         u32 vmexit_ctrl;
 189         u32 vmentry_ctrl;
 190 } vmcs_config;
 191
 192 static struct vmx_capability {
 193         u32 ept;
 194         u32 vpid;
 195 } vmx_capability;
 196
 197 #define VMX_SEGMENT_FIELD(seg)                                  \
 198         [VCPU_SREG_##seg] = {                                   \
 199                 .selector = GUEST_##seg##_SELECTOR,             \
 200                 .base = GUEST_##seg##_BASE,                     \
 201                 .limit = GUEST_##seg##_LIMIT,                   \
 202                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 203         }
 204
 205 static struct kvm_vmx_segment_field {
 206         unsigned selector;
 207         unsigned base;
 208         unsigned limit;
 209         unsigned ar_bytes;
 210 } kvm_vmx_segment_fields[] = {
 211         VMX_SEGMENT_FIELD(CS),
 212         VMX_SEGMENT_FIELD(DS),
 213         VMX_SEGMENT_FIELD(ES),
 214         VMX_SEGMENT_FIELD(FS),
 215         VMX_SEGMENT_FIELD(GS),
 216         VMX_SEGMENT_FIELD(SS),
 217         VMX_SEGMENT_FIELD(TR),
 218         VMX_SEGMENT_FIELD(LDTR),
 219 };
 220
 221 static u64 host_efer;
 222
 223 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 224
 225 /*
 226  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 227  * away by decrementing the array size.
 228  */
 229 static const u32 vmx_msr_index[] = {
 230 #ifdef CONFIG_X86_64
 231         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 232 #endif
 233         MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
 234 };
 235 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 236
 237 static inline int is_page_fault(u32 intr_info)
 238 {
 239         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 240                              INTR_INFO_VALID_MASK)) ==
 241                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 242 }
 243
 244 static inline int is_no_device(u32 intr_info)
 245 {
 246         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 247                              INTR_INFO_VALID_MASK)) ==
 248                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 249 }
 250
 251 static inline int is_invalid_opcode(u32 intr_info)
 252 {
 253         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 254                              INTR_INFO_VALID_MASK)) ==
 255                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 256 }
 257
 258 static inline int is_external_interrupt(u32 intr_info)
 259 {
 260         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 261                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 262 }
 263
 264 static inline int is_machine_check(u32 intr_info)
 265 {
 266         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 267                              INTR_INFO_VALID_MASK)) ==
 268                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 269 }
 270
 271 static inline int cpu_has_vmx_msr_bitmap(void)
 272 {
 273         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 274 }
 275
 276 static inline int cpu_has_vmx_tpr_shadow(void)
 277 {
 278         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 279 }
 280
 281 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 282 {
 283         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 284 }
 285
 286 static inline int cpu_has_secondary_exec_ctrls(void)
 287 {
 288         return vmcs_config.cpu_based_exec_ctrl &
 289                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 290 }
 291
 292 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 293 {
 294         return vmcs_config.cpu_based_2nd_exec_ctrl &
 295                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 296 }
 297
 298 static inline bool cpu_has_vmx_flexpriority(void)
 299 {
 300         return cpu_has_vmx_tpr_shadow() &&
 301                 cpu_has_vmx_virtualize_apic_accesses();
 302 }
 303
 304 static inline bool cpu_has_vmx_ept_execute_only(void)
 305 {
 306         return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
 307 }
 308
 309 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 310 {
 311         return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
 312 }
 313
 314 static inline bool cpu_has_vmx_eptp_writeback(void)
 315 {
 316         return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
 317 }
 318
 319 static inline bool cpu_has_vmx_ept_2m_page(void)
 320 {
 321         return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
 322 }
 323
 324 static inline bool cpu_has_vmx_ept_1g_page(void)
 325 {
 326         return !!(vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT);
 327 }
 328
 329 static inline int cpu_has_vmx_invept_individual_addr(void)
 330 {
 331         return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
 332 }
 333
 334 static inline int cpu_has_vmx_invept_context(void)
 335 {
 336         return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
 337 }
 338
 339 static inline int cpu_has_vmx_invept_global(void)
 340 {
 341         return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
 342 }
 343
 344 static inline int cpu_has_vmx_ept(void)
 345 {
 346         return vmcs_config.cpu_based_2nd_exec_ctrl &
 347                 SECONDARY_EXEC_ENABLE_EPT;
 348 }
 349
 350 static inline int cpu_has_vmx_unrestricted_guest(void)
 351 {
 352         return vmcs_config.cpu_based_2nd_exec_ctrl &
 353                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 354 }
 355
 356 static inline int cpu_has_vmx_ple(void)
 357 {
 358         return vmcs_config.cpu_based_2nd_exec_ctrl &
 359                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 360 }
 361
 362 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 363 {
 364         return flexpriority_enabled && irqchip_in_kernel(kvm);
 365 }
 366
 367 static inline int cpu_has_vmx_vpid(void)
 368 {
 369         return vmcs_config.cpu_based_2nd_exec_ctrl &
 370                 SECONDARY_EXEC_ENABLE_VPID;
 371 }
 372
 373 static inline int cpu_has_vmx_rdtscp(void)
 374 {
 375         return vmcs_config.cpu_based_2nd_exec_ctrl &
 376                 SECONDARY_EXEC_RDTSCP;
 377 }
 378
 379 static inline int cpu_has_virtual_nmis(void)
 380 {
 381         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 382 }
 383
 384 static inline bool report_flexpriority(void)
 385 {
 386         return flexpriority_enabled;
 387 }
 388
 389 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 390 {
 391         int i;
 392
 393         for (i = 0; i < vmx->nmsrs; ++i)
 394                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 395                         return i;
 396         return -1;
 397 }
 398
 399 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 400 {
 401     struct {
 402         u64 vpid : 16;
 403         u64 rsvd : 48;
 404         u64 gva;
 405     } operand = { vpid, 0, gva };
 406
 407     asm volatile (__ex(ASM_VMX_INVVPID)
 408                   /* CF==1 or ZF==1 --> rc = -1 */
 409                   "; ja 1f ; ud2 ; 1:"
 410                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 411 }
 412
 413 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 414 {
 415         struct {
 416                 u64 eptp, gpa;
 417         } operand = {eptp, gpa};
 418
 419         asm volatile (__ex(ASM_VMX_INVEPT)
 420                         /* CF==1 or ZF==1 --> rc = -1 */
 421                         "; ja 1f ; ud2 ; 1:\n"
 422                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 423 }
 424
 425 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 426 {
 427         int i;
 428
 429         i = __find_msr_index(vmx, msr);
 430         if (i >= 0)
 431                 return &vmx->guest_msrs[i];
 432         return NULL;
 433 }
 434
 435 static void vmcs_clear(struct vmcs *vmcs)
 436 {
 437         u64 phys_addr = __pa(vmcs);
 438         u8 error;
 439
 440         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 441                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 442                       : "cc", "memory");
 443         if (error)
 444                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 445                        vmcs, phys_addr);
 446 }
 447
 448 static void __vcpu_clear(void *arg)
 449 {
 450         struct vcpu_vmx *vmx = arg;
 451         int cpu = raw_smp_processor_id();
 452
 453         if (vmx->vcpu.cpu == cpu)
 454                 vmcs_clear(vmx->vmcs);
 455         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 456                 per_cpu(current_vmcs, cpu) = NULL;
 457         rdtscll(vmx->vcpu.arch.host_tsc);
 458         list_del(&vmx->local_vcpus_link);
 459         vmx->vcpu.cpu = -1;
 460         vmx->launched = 0;
 461 }
 462
 463 static void vcpu_clear(struct vcpu_vmx *vmx)
 464 {
 465         if (vmx->vcpu.cpu == -1)
 466                 return;
 467         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 468 }
 469
 470 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 471 {
 472         if (vmx->vpid == 0)
 473                 return;
 474
 475         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 476 }
 477
 478 static inline void ept_sync_global(void)
 479 {
 480         if (cpu_has_vmx_invept_global())
 481                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 482 }
 483
 484 static inline void ept_sync_context(u64 eptp)
 485 {
 486         if (enable_ept) {
 487                 if (cpu_has_vmx_invept_context())
 488                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 489                 else
 490                         ept_sync_global();
 491         }
 492 }
 493
 494 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 495 {
 496         if (enable_ept) {
 497                 if (cpu_has_vmx_invept_individual_addr())
 498                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 499                                         eptp, gpa);
 500                 else
 501                         ept_sync_context(eptp);
 502         }
 503 }
 504
 505 static unsigned long vmcs_readl(unsigned long field)
 506 {
 507         unsigned long value;
 508
 509         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 510                       : "=a"(value) : "d"(field) : "cc");
 511         return value;
 512 }
 513
 514 static u16 vmcs_read16(unsigned long field)
 515 {
 516         return vmcs_readl(field);
 517 }
 518
 519 static u32 vmcs_read32(unsigned long field)
 520 {
 521         return vmcs_readl(field);
 522 }
 523
 524 static u64 vmcs_read64(unsigned long field)
 525 {
 526 #ifdef CONFIG_X86_64
 527         return vmcs_readl(field);
 528 #else
 529         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 530 #endif
 531 }
 532
 533 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 534 {
 535         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 536                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 537         dump_stack();
 538 }
 539
 540 static void vmcs_writel(unsigned long field, unsigned long value)
 541 {
 542         u8 error;
 543
 544         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 545                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 546         if (unlikely(error))
 547                 vmwrite_error(field, value);
 548 }
 549
 550 static void vmcs_write16(unsigned long field, u16 value)
 551 {
 552         vmcs_writel(field, value);
 553 }
 554
 555 static void vmcs_write32(unsigned long field, u32 value)
 556 {
 557         vmcs_writel(field, value);
 558 }
 559
 560 static void vmcs_write64(unsigned long field, u64 value)
 561 {
 562         vmcs_writel(field, value);
 563 #ifndef CONFIG_X86_64
 564         asm volatile ("");
 565         vmcs_writel(field+1, value >> 32);
 566 #endif
 567 }
 568
 569 static void vmcs_clear_bits(unsigned long field, u32 mask)
 570 {
 571         vmcs_writel(field, vmcs_readl(field) & ~mask);
 572 }
 573
 574 static void vmcs_set_bits(unsigned long field, u32 mask)
 575 {
 576         vmcs_writel(field, vmcs_readl(field) | mask);
 577 }
 578
 579 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 580 {
 581         u32 eb;
 582
 583         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 584              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 585         if ((vcpu->guest_debug &
 586              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 587             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 588                 eb |= 1u << BP_VECTOR;
 589         if (to_vmx(vcpu)->rmode.vm86_active)
 590                 eb = ~0;
 591         if (enable_ept)
 592                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 593         if (vcpu->fpu_active)
 594                 eb &= ~(1u << NM_VECTOR);
 595         vmcs_write32(EXCEPTION_BITMAP, eb);
 596 }
 597
 598 static void reload_tss(void)
 599 {
 600         /*
 601          * VT restores TR but not its size.  Useless.
 602          */
 603         struct descriptor_table gdt;
 604         struct desc_struct *descs;
 605
 606         kvm_get_gdt(&gdt);
 607         descs = (void *)gdt.base;
 608         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 609         load_TR_desc();
 610 }
 611
 612 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 613 {
 614         u64 guest_efer;
 615         u64 ignore_bits;
 616
 617         guest_efer = vmx->vcpu.arch.efer;
 618
 619         /*
 620          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 621          * outside long mode
 622          */
 623         ignore_bits = EFER_NX | EFER_SCE;
 624 #ifdef CONFIG_X86_64
 625         ignore_bits |= EFER_LMA | EFER_LME;
 626         /* SCE is meaningful only in long mode on Intel */
 627         if (guest_efer & EFER_LMA)
 628                 ignore_bits &= ~(u64)EFER_SCE;
 629 #endif
 630         guest_efer &= ~ignore_bits;
 631         guest_efer |= host_efer & ignore_bits;
 632         vmx->guest_msrs[efer_offset].data = guest_efer;
 633         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 634         return true;
 635 }
 636
 637 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 638 {
 639         struct vcpu_vmx *vmx = to_vmx(vcpu);
 640         int i;
 641
 642         if (vmx->host_state.loaded)
 643                 return;
 644
 645         vmx->host_state.loaded = 1;
 646         /*
 647          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 648          * allow segment selectors with cpl > 0 or ti == 1.
 649          */
 650         vmx->host_state.ldt_sel = kvm_read_ldt();
 651         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 652         vmx->host_state.fs_sel = kvm_read_fs();
 653         if (!(vmx->host_state.fs_sel & 7)) {
 654                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 655                 vmx->host_state.fs_reload_needed = 0;
 656         } else {
 657                 vmcs_write16(HOST_FS_SELECTOR, 0);
 658                 vmx->host_state.fs_reload_needed = 1;
 659         }
 660         vmx->host_state.gs_sel = kvm_read_gs();
 661         if (!(vmx->host_state.gs_sel & 7))
 662                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 663         else {
 664                 vmcs_write16(HOST_GS_SELECTOR, 0);
 665                 vmx->host_state.gs_ldt_reload_needed = 1;
 666         }
 667
 668 #ifdef CONFIG_X86_64
 669         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 670         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 671 #else
 672         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 673         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 674 #endif
 675
 676 #ifdef CONFIG_X86_64
 677         if (is_long_mode(&vmx->vcpu)) {
 678                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 679                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 680         }
 681 #endif
 682         for (i = 0; i < vmx->save_nmsrs; ++i)
 683                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 684                                    vmx->guest_msrs[i].data,
 685                                    vmx->guest_msrs[i].mask);
 686 }
 687
 688 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 689 {
 690         unsigned long flags;
 691
 692         if (!vmx->host_state.loaded)
 693                 return;
 694
 695         ++vmx->vcpu.stat.host_state_reload;
 696         vmx->host_state.loaded = 0;
 697         if (vmx->host_state.fs_reload_needed)
 698                 kvm_load_fs(vmx->host_state.fs_sel);
 699         if (vmx->host_state.gs_ldt_reload_needed) {
 700                 kvm_load_ldt(vmx->host_state.ldt_sel);
 701                 /*
 702                  * If we have to reload gs, we must take care to
 703                  * preserve our gs base.
 704                  */
 705                 local_irq_save(flags);
 706                 kvm_load_gs(vmx->host_state.gs_sel);
 707 #ifdef CONFIG_X86_64
 708                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 709 #endif
 710                 local_irq_restore(flags);
 711         }
 712         reload_tss();
 713 #ifdef CONFIG_X86_64
 714         if (is_long_mode(&vmx->vcpu)) {
 715                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 716                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 717         }
 718 #endif
 719 }
 720
 721 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 722 {
 723         preempt_disable();
 724         __vmx_load_host_state(vmx);
 725         preempt_enable();
 726 }
 727
 728 /*
 729  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 730  * vcpu mutex is already taken.
 731  */
 732 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 733 {
 734         struct vcpu_vmx *vmx = to_vmx(vcpu);
 735         u64 phys_addr = __pa(vmx->vmcs);
 736         u64 tsc_this, delta, new_offset;
 737
 738         if (vcpu->cpu != cpu) {
 739                 vcpu_clear(vmx);
 740                 kvm_migrate_timers(vcpu);
 741                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 742                 local_irq_disable();
 743                 list_add(&vmx->local_vcpus_link,
 744                          &per_cpu(vcpus_on_cpu, cpu));
 745                 local_irq_enable();
 746         }
 747
 748         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 749                 u8 error;
 750
 751                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 752                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 753                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 754                               : "cc");
 755                 if (error)
 756                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 757                                vmx->vmcs, phys_addr);
 758         }
 759
 760         if (vcpu->cpu != cpu) {
 761                 struct descriptor_table dt;
 762                 unsigned long sysenter_esp;
 763
 764                 vcpu->cpu = cpu;
 765                 /*
 766                  * Linux uses per-cpu TSS and GDT, so set these when switching
 767                  * processors.
 768                  */
 769                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 770                 kvm_get_gdt(&dt);
 771                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 772
 773                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 774                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 775
 776                 /*
 777                  * Make sure the time stamp counter is monotonous.
 778                  */
 779                 rdtscll(tsc_this);
 780                 if (tsc_this < vcpu->arch.host_tsc) {
 781                         delta = vcpu->arch.host_tsc - tsc_this;
 782                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 783                         vmcs_write64(TSC_OFFSET, new_offset);
 784                 }
 785         }
 786 }
 787
 788 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 789 {
 790         __vmx_load_host_state(to_vmx(vcpu));
 791 }
 792
 793 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 794 {
 795         ulong cr0;
 796
 797         if (vcpu->fpu_active)
 798                 return;
 799         vcpu->fpu_active = 1;
 800         cr0 = vmcs_readl(GUEST_CR0);
 801         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 802         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 803         vmcs_writel(GUEST_CR0, cr0);
 804         update_exception_bitmap(vcpu);
 805         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 806         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 807 }
 808
 809 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 810
 811 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 812 {
 813         vmx_decache_cr0_guest_bits(vcpu);
 814         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 815         update_exception_bitmap(vcpu);
 816         vcpu->arch.cr0_guest_owned_bits = 0;
 817         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 818         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 819 }
 820
 821 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 822 {
 823         unsigned long rflags, save_rflags;
 824
 825         rflags = vmcs_readl(GUEST_RFLAGS);
 826         if (to_vmx(vcpu)->rmode.vm86_active) {
 827                 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
 828                 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
 829                 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
 830         }
 831         return rflags;
 832 }
 833
 834 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 835 {
 836         if (to_vmx(vcpu)->rmode.vm86_active) {
 837                 to_vmx(vcpu)->rmode.save_rflags = rflags;
 838                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 839         }
 840         vmcs_writel(GUEST_RFLAGS, rflags);
 841 }
 842
 843 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 844 {
 845         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 846         int ret = 0;
 847
 848         if (interruptibility & GUEST_INTR_STATE_STI)
 849                 ret |= X86_SHADOW_INT_STI;
 850         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 851                 ret |= X86_SHADOW_INT_MOV_SS;
 852
 853         return ret & mask;
 854 }
 855
 856 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 857 {
 858         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 859         u32 interruptibility = interruptibility_old;
 860
 861         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 862
 863         if (mask & X86_SHADOW_INT_MOV_SS)
 864                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 865         if (mask & X86_SHADOW_INT_STI)
 866                 interruptibility |= GUEST_INTR_STATE_STI;
 867
 868         if ((interruptibility != interruptibility_old))
 869                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 870 }
 871
 872 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 873 {
 874         unsigned long rip;
 875
 876         rip = kvm_rip_read(vcpu);
 877         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 878         kvm_rip_write(vcpu, rip);
 879
 880         /* skipping an emulated instruction also counts */
 881         vmx_set_interrupt_shadow(vcpu, 0);
 882 }
 883
 884 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 885                                 bool has_error_code, u32 error_code)
 886 {
 887         struct vcpu_vmx *vmx = to_vmx(vcpu);
 888         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 889
 890         if (has_error_code) {
 891                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 892                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 893         }
 894
 895         if (vmx->rmode.vm86_active) {
 896                 vmx->rmode.irq.pending = true;
 897                 vmx->rmode.irq.vector = nr;
 898                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 899                 if (kvm_exception_is_soft(nr))
 900                         vmx->rmode.irq.rip +=
 901                                 vmx->vcpu.arch.event_exit_inst_len;
 902                 intr_info |= INTR_TYPE_SOFT_INTR;
 903                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 904                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
 905                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
 906                 return;
 907         }
 908
 909         if (kvm_exception_is_soft(nr)) {
 910                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
 911                              vmx->vcpu.arch.event_exit_inst_len);
 912                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
 913         } else
 914                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
 915
 916         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
 917 }
 918
 919 static bool vmx_rdtscp_supported(void)
 920 {
 921         return cpu_has_vmx_rdtscp();
 922 }
 923
 924 /*
 925  * Swap MSR entry in host/guest MSR entry array.
 926  */
 927 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 928 {
 929         struct shared_msr_entry tmp;
 930
 931         tmp = vmx->guest_msrs[to];
 932         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 933         vmx->guest_msrs[from] = tmp;
 934 }
 935
 936 /*
 937  * Set up the vmcs to automatically save and restore system
 938  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 939  * mode, as fiddling with msrs is very expensive.
 940  */
 941 static void setup_msrs(struct vcpu_vmx *vmx)
 942 {
 943         int save_nmsrs, index;
 944         unsigned long *msr_bitmap;
 945
 946         vmx_load_host_state(vmx);
 947         save_nmsrs = 0;
 948 #ifdef CONFIG_X86_64
 949         if (is_long_mode(&vmx->vcpu)) {
 950                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 951                 if (index >= 0)
 952                         move_msr_up(vmx, index, save_nmsrs++);
 953                 index = __find_msr_index(vmx, MSR_LSTAR);
 954                 if (index >= 0)
 955                         move_msr_up(vmx, index, save_nmsrs++);
 956                 index = __find_msr_index(vmx, MSR_CSTAR);
 957                 if (index >= 0)
 958                         move_msr_up(vmx, index, save_nmsrs++);
 959                 index = __find_msr_index(vmx, MSR_TSC_AUX);
 960                 if (index >= 0 && vmx->rdtscp_enabled)
 961                         move_msr_up(vmx, index, save_nmsrs++);
 962                 /*
 963                  * MSR_K6_STAR is only needed on long mode guests, and only
 964                  * if efer.sce is enabled.
 965                  */
 966                 index = __find_msr_index(vmx, MSR_K6_STAR);
 967                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
 968                         move_msr_up(vmx, index, save_nmsrs++);
 969         }
 970 #endif
 971         index = __find_msr_index(vmx, MSR_EFER);
 972         if (index >= 0 && update_transition_efer(vmx, index))
 973                 move_msr_up(vmx, index, save_nmsrs++);
 974
 975         vmx->save_nmsrs = save_nmsrs;
 976
 977         if (cpu_has_vmx_msr_bitmap()) {
 978                 if (is_long_mode(&vmx->vcpu))
 979                         msr_bitmap = vmx_msr_bitmap_longmode;
 980                 else
 981                         msr_bitmap = vmx_msr_bitmap_legacy;
 982
 983                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
 984         }
 985 }
 986
 987 /*
 988  * reads and returns guest's timestamp counter "register"
 989  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 990  */
 991 static u64 guest_read_tsc(void)
 992 {
 993         u64 host_tsc, tsc_offset;
 994
 995         rdtscll(host_tsc);
 996         tsc_offset = vmcs_read64(TSC_OFFSET);
 997         return host_tsc + tsc_offset;
 998 }
 999
1000 /*
1001  * writes 'guest_tsc' into guest's timestamp counter "register"
1002  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1003  */
1004 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
1005 {
1006         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1007 }
1008
1009 /*
1010  * Reads an msr value (of 'msr_index') into 'pdata'.
1011  * Returns 0 on success, non-0 otherwise.
1012  * Assumes vcpu_load() was already called.
1013  */
1014 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1015 {
1016         u64 data;
1017         struct shared_msr_entry *msr;
1018
1019         if (!pdata) {
1020                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1021                 return -EINVAL;
1022         }
1023
1024         switch (msr_index) {
1025 #ifdef CONFIG_X86_64
1026         case MSR_FS_BASE:
1027                 data = vmcs_readl(GUEST_FS_BASE);
1028                 break;
1029         case MSR_GS_BASE:
1030                 data = vmcs_readl(GUEST_GS_BASE);
1031                 break;
1032         case MSR_KERNEL_GS_BASE:
1033                 vmx_load_host_state(to_vmx(vcpu));
1034                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1035                 break;
1036 #endif
1037         case MSR_EFER:
1038                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1039         case MSR_IA32_TSC:
1040                 data = guest_read_tsc();
1041                 break;
1042         case MSR_IA32_SYSENTER_CS:
1043                 data = vmcs_read32(GUEST_SYSENTER_CS);
1044                 break;
1045         case MSR_IA32_SYSENTER_EIP:
1046                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1047                 break;
1048         case MSR_IA32_SYSENTER_ESP:
1049                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1050                 break;
1051         case MSR_TSC_AUX:
1052                 if (!to_vmx(vcpu)->rdtscp_enabled)
1053                         return 1;
1054                 /* Otherwise falls through */
1055         default:
1056                 vmx_load_host_state(to_vmx(vcpu));
1057                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1058                 if (msr) {
1059                         vmx_load_host_state(to_vmx(vcpu));
1060                         data = msr->data;
1061                         break;
1062                 }
1063                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1064         }
1065
1066         *pdata = data;
1067         return 0;
1068 }
1069
1070 /*
1071  * Writes msr value into into the appropriate "register".
1072  * Returns 0 on success, non-0 otherwise.
1073  * Assumes vcpu_load() was already called.
1074  */
1075 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1076 {
1077         struct vcpu_vmx *vmx = to_vmx(vcpu);
1078         struct shared_msr_entry *msr;
1079         u64 host_tsc;
1080         int ret = 0;
1081
1082         switch (msr_index) {
1083         case MSR_EFER:
1084                 vmx_load_host_state(vmx);
1085                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1086                 break;
1087 #ifdef CONFIG_X86_64
1088         case MSR_FS_BASE:
1089                 vmcs_writel(GUEST_FS_BASE, data);
1090                 break;
1091         case MSR_GS_BASE:
1092                 vmcs_writel(GUEST_GS_BASE, data);
1093                 break;
1094         case MSR_KERNEL_GS_BASE:
1095                 vmx_load_host_state(vmx);
1096                 vmx->msr_guest_kernel_gs_base = data;
1097                 break;
1098 #endif
1099         case MSR_IA32_SYSENTER_CS:
1100                 vmcs_write32(GUEST_SYSENTER_CS, data);
1101                 break;
1102         case MSR_IA32_SYSENTER_EIP:
1103                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1104                 break;
1105         case MSR_IA32_SYSENTER_ESP:
1106                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1107                 break;
1108         case MSR_IA32_TSC:
1109                 rdtscll(host_tsc);
1110                 guest_write_tsc(data, host_tsc);
1111                 break;
1112         case MSR_IA32_CR_PAT:
1113                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1114                         vmcs_write64(GUEST_IA32_PAT, data);
1115                         vcpu->arch.pat = data;
1116                         break;
1117                 }
1118                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1119                 break;
1120         case MSR_TSC_AUX:
1121                 if (!vmx->rdtscp_enabled)
1122                         return 1;
1123                 /* Check reserved bit, higher 32 bits should be zero */
1124                 if ((data >> 32) != 0)
1125                         return 1;
1126                 /* Otherwise falls through */
1127         default:
1128                 msr = find_msr_entry(vmx, msr_index);
1129                 if (msr) {
1130                         vmx_load_host_state(vmx);
1131                         msr->data = data;
1132                         break;
1133                 }
1134                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1135         }
1136
1137         return ret;
1138 }
1139
1140 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1141 {
1142         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1143         switch (reg) {
1144         case VCPU_REGS_RSP:
1145                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1146                 break;
1147         case VCPU_REGS_RIP:
1148                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1149                 break;
1150         case VCPU_EXREG_PDPTR:
1151                 if (enable_ept)
1152                         ept_save_pdptrs(vcpu);
1153                 break;
1154         default:
1155                 break;
1156         }
1157 }
1158
1159 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1160 {
1161         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1162                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1163         else
1164                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1165
1166         update_exception_bitmap(vcpu);
1167 }
1168
1169 static __init int cpu_has_kvm_support(void)
1170 {
1171         return cpu_has_vmx();
1172 }
1173
1174 static __init int vmx_disabled_by_bios(void)
1175 {
1176         u64 msr;
1177
1178         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1179         return (msr & (FEATURE_CONTROL_LOCKED |
1180                        FEATURE_CONTROL_VMXON_ENABLED))
1181             == FEATURE_CONTROL_LOCKED;
1182         /* locked but not enabled */
1183 }
1184
1185 static int hardware_enable(void *garbage)
1186 {
1187         int cpu = raw_smp_processor_id();
1188         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1189         u64 old;
1190
1191         if (read_cr4() & X86_CR4_VMXE)
1192                 return -EBUSY;
1193
1194         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1195         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1196         if ((old & (FEATURE_CONTROL_LOCKED |
1197                     FEATURE_CONTROL_VMXON_ENABLED))
1198             != (FEATURE_CONTROL_LOCKED |
1199                 FEATURE_CONTROL_VMXON_ENABLED))
1200                 /* enable and lock */
1201                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1202                        FEATURE_CONTROL_LOCKED |
1203                        FEATURE_CONTROL_VMXON_ENABLED);
1204         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1205         asm volatile (ASM_VMX_VMXON_RAX
1206                       : : "a"(&phys_addr), "m"(phys_addr)
1207                       : "memory", "cc");
1208
1209         ept_sync_global();
1210
1211         return 0;
1212 }
1213
1214 static void vmclear_local_vcpus(void)
1215 {
1216         int cpu = raw_smp_processor_id();
1217         struct vcpu_vmx *vmx, *n;
1218
1219         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1220                                  local_vcpus_link)
1221                 __vcpu_clear(vmx);
1222 }
1223
1224
1225 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1226  * tricks.
1227  */
1228 static void kvm_cpu_vmxoff(void)
1229 {
1230         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1231         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1232 }
1233
1234 static void hardware_disable(void *garbage)
1235 {
1236         vmclear_local_vcpus();
1237         kvm_cpu_vmxoff();
1238 }
1239
1240 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1241                                       u32 msr, u32 *result)
1242 {
1243         u32 vmx_msr_low, vmx_msr_high;
1244         u32 ctl = ctl_min | ctl_opt;
1245
1246         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1247
1248         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1249         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1250
1251         /* Ensure minimum (required) set of control bits are supported. */
1252         if (ctl_min & ~ctl)
1253                 return -EIO;
1254
1255         *result = ctl;
1256         return 0;
1257 }
1258
1259 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1260 {
1261         u32 vmx_msr_low, vmx_msr_high;
1262         u32 min, opt, min2, opt2;
1263         u32 _pin_based_exec_control = 0;
1264         u32 _cpu_based_exec_control = 0;
1265         u32 _cpu_based_2nd_exec_control = 0;
1266         u32 _vmexit_control = 0;
1267         u32 _vmentry_control = 0;
1268
1269         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1270         opt = PIN_BASED_VIRTUAL_NMIS;
1271         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1272                                 &_pin_based_exec_control) < 0)
1273                 return -EIO;
1274
1275         min = CPU_BASED_HLT_EXITING |
1276 #ifdef CONFIG_X86_64
1277               CPU_BASED_CR8_LOAD_EXITING |
1278               CPU_BASED_CR8_STORE_EXITING |
1279 #endif
1280               CPU_BASED_CR3_LOAD_EXITING |
1281               CPU_BASED_CR3_STORE_EXITING |
1282               CPU_BASED_USE_IO_BITMAPS |
1283               CPU_BASED_MOV_DR_EXITING |
1284               CPU_BASED_USE_TSC_OFFSETING |
1285               CPU_BASED_MWAIT_EXITING |
1286               CPU_BASED_MONITOR_EXITING |
1287               CPU_BASED_INVLPG_EXITING;
1288         opt = CPU_BASED_TPR_SHADOW |
1289               CPU_BASED_USE_MSR_BITMAPS |
1290               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1291         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1292                                 &_cpu_based_exec_control) < 0)
1293                 return -EIO;
1294 #ifdef CONFIG_X86_64
1295         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1296                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1297                                            ~CPU_BASED_CR8_STORE_EXITING;
1298 #endif
1299         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1300                 min2 = 0;
1301                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1302                         SECONDARY_EXEC_WBINVD_EXITING |
1303                         SECONDARY_EXEC_ENABLE_VPID |
1304                         SECONDARY_EXEC_ENABLE_EPT |
1305                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1306                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1307                         SECONDARY_EXEC_RDTSCP;
1308                 if (adjust_vmx_controls(min2, opt2,
1309                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1310                                         &_cpu_based_2nd_exec_control) < 0)
1311                         return -EIO;
1312         }
1313 #ifndef CONFIG_X86_64
1314         if (!(_cpu_based_2nd_exec_control &
1315                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1316                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1317 #endif
1318         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1319                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1320                    enabled */
1321                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1322                                              CPU_BASED_CR3_STORE_EXITING |
1323                                              CPU_BASED_INVLPG_EXITING);
1324                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1325                       vmx_capability.ept, vmx_capability.vpid);
1326         }
1327
1328         min = 0;
1329 #ifdef CONFIG_X86_64
1330         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1331 #endif
1332         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1333         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1334                                 &_vmexit_control) < 0)
1335                 return -EIO;
1336
1337         min = 0;
1338         opt = VM_ENTRY_LOAD_IA32_PAT;
1339         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1340                                 &_vmentry_control) < 0)
1341                 return -EIO;
1342
1343         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1344
1345         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1346         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1347                 return -EIO;
1348
1349 #ifdef CONFIG_X86_64
1350         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1351         if (vmx_msr_high & (1u<<16))
1352                 return -EIO;
1353 #endif
1354
1355         /* Require Write-Back (WB) memory type for VMCS accesses. */
1356         if (((vmx_msr_high >> 18) & 15) != 6)
1357                 return -EIO;
1358
1359         vmcs_conf->size = vmx_msr_high & 0x1fff;
1360         vmcs_conf->order = get_order(vmcs_config.size);
1361         vmcs_conf->revision_id = vmx_msr_low;
1362
1363         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1364         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1365         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1366         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1367         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1368
1369         return 0;
1370 }
1371
1372 static struct vmcs *alloc_vmcs_cpu(int cpu)
1373 {
1374         int node = cpu_to_node(cpu);
1375         struct page *pages;
1376         struct vmcs *vmcs;
1377
1378         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1379         if (!pages)
1380                 return NULL;
1381         vmcs = page_address(pages);
1382         memset(vmcs, 0, vmcs_config.size);
1383         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1384         return vmcs;
1385 }
1386
1387 static struct vmcs *alloc_vmcs(void)
1388 {
1389         return alloc_vmcs_cpu(raw_smp_processor_id());
1390 }
1391
1392 static void free_vmcs(struct vmcs *vmcs)
1393 {
1394         free_pages((unsigned long)vmcs, vmcs_config.order);
1395 }
1396
1397 static void free_kvm_area(void)
1398 {
1399         int cpu;
1400
1401         for_each_possible_cpu(cpu) {
1402                 free_vmcs(per_cpu(vmxarea, cpu));
1403                 per_cpu(vmxarea, cpu) = NULL;
1404         }
1405 }
1406
1407 static __init int alloc_kvm_area(void)
1408 {
1409         int cpu;
1410
1411         for_each_possible_cpu(cpu) {
1412                 struct vmcs *vmcs;
1413
1414                 vmcs = alloc_vmcs_cpu(cpu);
1415                 if (!vmcs) {
1416                         free_kvm_area();
1417                         return -ENOMEM;
1418                 }
1419
1420                 per_cpu(vmxarea, cpu) = vmcs;
1421         }
1422         return 0;
1423 }
1424
1425 static __init int hardware_setup(void)
1426 {
1427         if (setup_vmcs_config(&vmcs_config) < 0)
1428                 return -EIO;
1429
1430         if (boot_cpu_has(X86_FEATURE_NX))
1431                 kvm_enable_efer_bits(EFER_NX);
1432
1433         if (!cpu_has_vmx_vpid())
1434                 enable_vpid = 0;
1435
1436         if (!cpu_has_vmx_ept()) {
1437                 enable_ept = 0;
1438                 enable_unrestricted_guest = 0;
1439         }
1440
1441         if (!cpu_has_vmx_unrestricted_guest())
1442                 enable_unrestricted_guest = 0;
1443
1444         if (!cpu_has_vmx_flexpriority())
1445                 flexpriority_enabled = 0;
1446
1447         if (!cpu_has_vmx_tpr_shadow())
1448                 kvm_x86_ops->update_cr8_intercept = NULL;
1449
1450         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1451                 kvm_disable_largepages();
1452
1453         if (!cpu_has_vmx_ple())
1454                 ple_gap = 0;
1455
1456         return alloc_kvm_area();
1457 }
1458
1459 static __exit void hardware_unsetup(void)
1460 {
1461         free_kvm_area();
1462 }
1463
1464 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1465 {
1466         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1467
1468         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1469                 vmcs_write16(sf->selector, save->selector);
1470                 vmcs_writel(sf->base, save->base);
1471                 vmcs_write32(sf->limit, save->limit);
1472                 vmcs_write32(sf->ar_bytes, save->ar);
1473         } else {
1474                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1475                         << AR_DPL_SHIFT;
1476                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1477         }
1478 }
1479
1480 static void enter_pmode(struct kvm_vcpu *vcpu)
1481 {
1482         unsigned long flags;
1483         struct vcpu_vmx *vmx = to_vmx(vcpu);
1484
1485         vmx->emulation_required = 1;
1486         vmx->rmode.vm86_active = 0;
1487
1488         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1489         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1490         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1491
1492         flags = vmcs_readl(GUEST_RFLAGS);
1493         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1494         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1495         vmcs_writel(GUEST_RFLAGS, flags);
1496
1497         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1498                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1499
1500         update_exception_bitmap(vcpu);
1501
1502         if (emulate_invalid_guest_state)
1503                 return;
1504
1505         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1506         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1507         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1508         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1509
1510         vmcs_write16(GUEST_SS_SELECTOR, 0);
1511         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1512
1513         vmcs_write16(GUEST_CS_SELECTOR,
1514                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1515         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1516 }
1517
1518 static gva_t rmode_tss_base(struct kvm *kvm)
1519 {
1520         if (!kvm->arch.tss_addr) {
1521                 struct kvm_memslots *slots;
1522                 gfn_t base_gfn;
1523
1524                 slots = rcu_dereference(kvm->memslots);
1525                 base_gfn = kvm->memslots->memslots[0].base_gfn +
1526                                  kvm->memslots->memslots[0].npages - 3;
1527                 return base_gfn << PAGE_SHIFT;
1528         }
1529         return kvm->arch.tss_addr;
1530 }
1531
1532 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1533 {
1534         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1535
1536         save->selector = vmcs_read16(sf->selector);
1537         save->base = vmcs_readl(sf->base);
1538         save->limit = vmcs_read32(sf->limit);
1539         save->ar = vmcs_read32(sf->ar_bytes);
1540         vmcs_write16(sf->selector, save->base >> 4);
1541         vmcs_write32(sf->base, save->base & 0xfffff);
1542         vmcs_write32(sf->limit, 0xffff);
1543         vmcs_write32(sf->ar_bytes, 0xf3);
1544 }
1545
1546 static void enter_rmode(struct kvm_vcpu *vcpu)
1547 {
1548         unsigned long flags;
1549         struct vcpu_vmx *vmx = to_vmx(vcpu);
1550
1551         if (enable_unrestricted_guest)
1552                 return;
1553
1554         vmx->emulation_required = 1;
1555         vmx->rmode.vm86_active = 1;
1556
1557         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1558         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1559
1560         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1561         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1562
1563         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1564         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1565
1566         flags = vmcs_readl(GUEST_RFLAGS);
1567         vmx->rmode.save_rflags = flags;
1568
1569         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1570
1571         vmcs_writel(GUEST_RFLAGS, flags);
1572         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1573         update_exception_bitmap(vcpu);
1574
1575         if (emulate_invalid_guest_state)
1576                 goto continue_rmode;
1577
1578         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1579         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1580         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1581
1582         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1583         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1584         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1585                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1586         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1587
1588         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1589         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1590         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1591         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1592
1593 continue_rmode:
1594         kvm_mmu_reset_context(vcpu);
1595         init_rmode(vcpu->kvm);
1596 }
1597
1598 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1599 {
1600         struct vcpu_vmx *vmx = to_vmx(vcpu);
1601         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1602
1603         if (!msr)
1604                 return;
1605
1606         /*
1607          * Force kernel_gs_base reloading before EFER changes, as control
1608          * of this msr depends on is_long_mode().
1609          */
1610         vmx_load_host_state(to_vmx(vcpu));
1611         vcpu->arch.efer = efer;
1612         if (efer & EFER_LMA) {
1613                 vmcs_write32(VM_ENTRY_CONTROLS,
1614                              vmcs_read32(VM_ENTRY_CONTROLS) |
1615                              VM_ENTRY_IA32E_MODE);
1616                 msr->data = efer;
1617         } else {
1618                 vmcs_write32(VM_ENTRY_CONTROLS,
1619                              vmcs_read32(VM_ENTRY_CONTROLS) &
1620                              ~VM_ENTRY_IA32E_MODE);
1621
1622                 msr->data = efer & ~EFER_LME;
1623         }
1624         setup_msrs(vmx);
1625 }
1626
1627 #ifdef CONFIG_X86_64
1628
1629 static void enter_lmode(struct kvm_vcpu *vcpu)
1630 {
1631         u32 guest_tr_ar;
1632
1633         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1634         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1635                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1636                        __func__);
1637                 vmcs_write32(GUEST_TR_AR_BYTES,
1638                              (guest_tr_ar & ~AR_TYPE_MASK)
1639                              | AR_TYPE_BUSY_64_TSS);
1640         }
1641         vcpu->arch.efer |= EFER_LMA;
1642         vmx_set_efer(vcpu, vcpu->arch.efer);
1643 }
1644
1645 static void exit_lmode(struct kvm_vcpu *vcpu)
1646 {
1647         vcpu->arch.efer &= ~EFER_LMA;
1648
1649         vmcs_write32(VM_ENTRY_CONTROLS,
1650                      vmcs_read32(VM_ENTRY_CONTROLS)
1651                      & ~VM_ENTRY_IA32E_MODE);
1652 }
1653
1654 #endif
1655
1656 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1657 {
1658         vpid_sync_vcpu_all(to_vmx(vcpu));
1659         if (enable_ept)
1660                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1661 }
1662
1663 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1664 {
1665         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1666
1667         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1668         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1669 }
1670
1671 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1672 {
1673         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1674
1675         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1676         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1677 }
1678
1679 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1680 {
1681         if (!test_bit(VCPU_EXREG_PDPTR,
1682                       (unsigned long *)&vcpu->arch.regs_dirty))
1683                 return;
1684
1685         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1686                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1687                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1688                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1689                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1690         }
1691 }
1692
1693 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1694 {
1695         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1696                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1697                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1698                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1699                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1700         }
1701
1702         __set_bit(VCPU_EXREG_PDPTR,
1703                   (unsigned long *)&vcpu->arch.regs_avail);
1704         __set_bit(VCPU_EXREG_PDPTR,
1705                   (unsigned long *)&vcpu->arch.regs_dirty);
1706 }
1707
1708 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1709
1710 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1711                                         unsigned long cr0,
1712                                         struct kvm_vcpu *vcpu)
1713 {
1714         if (!(cr0 & X86_CR0_PG)) {
1715                 /* From paging/starting to nonpaging */
1716                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1717                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1718                              (CPU_BASED_CR3_LOAD_EXITING |
1719                               CPU_BASED_CR3_STORE_EXITING));
1720                 vcpu->arch.cr0 = cr0;
1721                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1722         } else if (!is_paging(vcpu)) {
1723                 /* From nonpaging to paging */
1724                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1725                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1726                              ~(CPU_BASED_CR3_LOAD_EXITING |
1727                                CPU_BASED_CR3_STORE_EXITING));
1728                 vcpu->arch.cr0 = cr0;
1729                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1730         }
1731
1732         if (!(cr0 & X86_CR0_WP))
1733                 *hw_cr0 &= ~X86_CR0_WP;
1734 }
1735
1736 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1737 {
1738         struct vcpu_vmx *vmx = to_vmx(vcpu);
1739         unsigned long hw_cr0;
1740
1741         if (enable_unrestricted_guest)
1742                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1743                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1744         else
1745                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1746
1747         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1748                 enter_pmode(vcpu);
1749
1750         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1751                 enter_rmode(vcpu);
1752
1753 #ifdef CONFIG_X86_64
1754         if (vcpu->arch.efer & EFER_LME) {
1755                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1756                         enter_lmode(vcpu);
1757                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1758                         exit_lmode(vcpu);
1759         }
1760 #endif
1761
1762         if (enable_ept)
1763                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1764
1765         if (!vcpu->fpu_active)
1766                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1767
1768         vmcs_writel(CR0_READ_SHADOW, cr0);
1769         vmcs_writel(GUEST_CR0, hw_cr0);
1770         vcpu->arch.cr0 = cr0;
1771 }
1772
1773 static u64 construct_eptp(unsigned long root_hpa)
1774 {
1775         u64 eptp;
1776
1777         /* TODO write the value reading from MSR */
1778         eptp = VMX_EPT_DEFAULT_MT |
1779                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1780         eptp |= (root_hpa & PAGE_MASK);
1781
1782         return eptp;
1783 }
1784
1785 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1786 {
1787         unsigned long guest_cr3;
1788         u64 eptp;
1789
1790         guest_cr3 = cr3;
1791         if (enable_ept) {
1792                 eptp = construct_eptp(cr3);
1793                 vmcs_write64(EPT_POINTER, eptp);
1794                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1795                         vcpu->kvm->arch.ept_identity_map_addr;
1796                 ept_load_pdptrs(vcpu);
1797         }
1798
1799         vmx_flush_tlb(vcpu);
1800         vmcs_writel(GUEST_CR3, guest_cr3);
1801 }
1802
1803 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1804 {
1805         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1806                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1807
1808         vcpu->arch.cr4 = cr4;
1809         if (enable_ept) {
1810                 if (!is_paging(vcpu)) {
1811                         hw_cr4 &= ~X86_CR4_PAE;
1812                         hw_cr4 |= X86_CR4_PSE;
1813                 } else if (!(cr4 & X86_CR4_PAE)) {
1814                         hw_cr4 &= ~X86_CR4_PAE;
1815                 }
1816         }
1817
1818         vmcs_writel(CR4_READ_SHADOW, cr4);
1819         vmcs_writel(GUEST_CR4, hw_cr4);
1820 }
1821
1822 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1823 {
1824         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1825
1826         return vmcs_readl(sf->base);
1827 }
1828
1829 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1830                             struct kvm_segment *var, int seg)
1831 {
1832         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1833         u32 ar;
1834
1835         var->base = vmcs_readl(sf->base);
1836         var->limit = vmcs_read32(sf->limit);
1837         var->selector = vmcs_read16(sf->selector);
1838         ar = vmcs_read32(sf->ar_bytes);
1839         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1840                 ar = 0;
1841         var->type = ar & 15;
1842         var->s = (ar >> 4) & 1;
1843         var->dpl = (ar >> 5) & 3;
1844         var->present = (ar >> 7) & 1;
1845         var->avl = (ar >> 12) & 1;
1846         var->l = (ar >> 13) & 1;
1847         var->db = (ar >> 14) & 1;
1848         var->g = (ar >> 15) & 1;
1849         var->unusable = (ar >> 16) & 1;
1850 }
1851
1852 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1853 {
1854         if (!is_protmode(vcpu))
1855                 return 0;
1856
1857         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1858                 return 3;
1859
1860         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1861 }
1862
1863 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1864 {
1865         u32 ar;
1866
1867         if (var->unusable)
1868                 ar = 1 << 16;
1869         else {
1870                 ar = var->type & 15;
1871                 ar |= (var->s & 1) << 4;
1872                 ar |= (var->dpl & 3) << 5;
1873                 ar |= (var->present & 1) << 7;
1874                 ar |= (var->avl & 1) << 12;
1875                 ar |= (var->l & 1) << 13;
1876                 ar |= (var->db & 1) << 14;
1877                 ar |= (var->g & 1) << 15;
1878         }
1879         if (ar == 0) /* a 0 value means unusable */
1880                 ar = AR_UNUSABLE_MASK;
1881
1882         return ar;
1883 }
1884
1885 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1886                             struct kvm_segment *var, int seg)
1887 {
1888         struct vcpu_vmx *vmx = to_vmx(vcpu);
1889         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1890         u32 ar;
1891
1892         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1893                 vmx->rmode.tr.selector = var->selector;
1894                 vmx->rmode.tr.base = var->base;
1895                 vmx->rmode.tr.limit = var->limit;
1896                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1897                 return;
1898         }
1899         vmcs_writel(sf->base, var->base);
1900         vmcs_write32(sf->limit, var->limit);
1901         vmcs_write16(sf->selector, var->selector);
1902         if (vmx->rmode.vm86_active && var->s) {
1903                 /*
1904                  * Hack real-mode segments into vm86 compatibility.
1905                  */
1906                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1907                         vmcs_writel(sf->base, 0xf0000);
1908                 ar = 0xf3;
1909         } else
1910                 ar = vmx_segment_access_rights(var);
1911
1912         /*
1913          *   Fix the "Accessed" bit in AR field of segment registers for older
1914          * qemu binaries.
1915          *   IA32 arch specifies that at the time of processor reset the
1916          * "Accessed" bit in the AR field of segment registers is 1. And qemu
1917          * is setting it to 0 in the usedland code. This causes invalid guest
1918          * state vmexit when "unrestricted guest" mode is turned on.
1919          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
1920          * tree. Newer qemu binaries with that qemu fix would not need this
1921          * kvm hack.
1922          */
1923         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1924                 ar |= 0x1; /* Accessed */
1925
1926         vmcs_write32(sf->ar_bytes, ar);
1927 }
1928
1929 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1930 {
1931         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1932
1933         *db = (ar >> 14) & 1;
1934         *l = (ar >> 13) & 1;
1935 }
1936
1937 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1938 {
1939         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1940         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1941 }
1942
1943 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1944 {
1945         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1946         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1947 }
1948
1949 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1950 {
1951         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1952         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1953 }
1954
1955 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1956 {
1957         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1958         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1959 }
1960
1961 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1962 {
1963         struct kvm_segment var;
1964         u32 ar;
1965
1966         vmx_get_segment(vcpu, &var, seg);
1967         ar = vmx_segment_access_rights(&var);
1968
1969         if (var.base != (var.selector << 4))
1970                 return false;
1971         if (var.limit != 0xffff)
1972                 return false;
1973         if (ar != 0xf3)
1974                 return false;
1975
1976         return true;
1977 }
1978
1979 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1980 {
1981         struct kvm_segment cs;
1982         unsigned int cs_rpl;
1983
1984         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1985         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1986
1987         if (cs.unusable)
1988                 return false;
1989         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1990                 return false;
1991         if (!cs.s)
1992                 return false;
1993         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1994                 if (cs.dpl > cs_rpl)
1995                         return false;
1996         } else {
1997                 if (cs.dpl != cs_rpl)
1998                         return false;
1999         }
2000         if (!cs.present)
2001                 return false;
2002
2003         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2004         return true;
2005 }
2006
2007 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2008 {
2009         struct kvm_segment ss;
2010         unsigned int ss_rpl;
2011
2012         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2013         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2014
2015         if (ss.unusable)
2016                 return true;
2017         if (ss.type != 3 && ss.type != 7)
2018                 return false;
2019         if (!ss.s)
2020                 return false;
2021         if (ss.dpl != ss_rpl) /* DPL != RPL */
2022                 return false;
2023         if (!ss.present)
2024                 return false;
2025
2026         return true;
2027 }
2028
2029 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2030 {
2031         struct kvm_segment var;
2032         unsigned int rpl;
2033
2034         vmx_get_segment(vcpu, &var, seg);
2035         rpl = var.selector & SELECTOR_RPL_MASK;
2036
2037         if (var.unusable)
2038                 return true;
2039         if (!var.s)
2040                 return false;
2041         if (!var.present)
2042                 return false;
2043         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2044                 if (var.dpl < rpl) /* DPL < RPL */
2045                         return false;
2046         }
2047
2048         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2049          * rights flags
2050          */
2051         return true;
2052 }
2053
2054 static bool tr_valid(struct kvm_vcpu *vcpu)
2055 {
2056         struct kvm_segment tr;
2057
2058         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2059
2060         if (tr.unusable)
2061                 return false;
2062         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2063                 return false;
2064         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2065                 return false;
2066         if (!tr.present)
2067                 return false;
2068
2069         return true;
2070 }
2071
2072 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2073 {
2074         struct kvm_segment ldtr;
2075
2076         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2077
2078         if (ldtr.unusable)
2079                 return true;
2080         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2081                 return false;
2082         if (ldtr.type != 2)
2083                 return false;
2084         if (!ldtr.present)
2085                 return false;
2086
2087         return true;
2088 }
2089
2090 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2091 {
2092         struct kvm_segment cs, ss;
2093
2094         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2095         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2096
2097         return ((cs.selector & SELECTOR_RPL_MASK) ==
2098                  (ss.selector & SELECTOR_RPL_MASK));
2099 }
2100
2101 /*
2102  * Check if guest state is valid. Returns true if valid, false if
2103  * not.
2104  * We assume that registers are always usable
2105  */
2106 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2107 {
2108         /* real mode guest state checks */
2109         if (!is_protmode(vcpu)) {
2110                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2111                         return false;
2112                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2113                         return false;
2114                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2115                         return false;
2116                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2117                         return false;
2118                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2119                         return false;
2120                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2121                         return false;
2122         } else {
2123         /* protected mode guest state checks */
2124                 if (!cs_ss_rpl_check(vcpu))
2125                         return false;
2126                 if (!code_segment_valid(vcpu))
2127                         return false;
2128                 if (!stack_segment_valid(vcpu))
2129                         return false;
2130                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2131                         return false;
2132                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2133                         return false;
2134                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2135                         return false;
2136                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2137                         return false;
2138                 if (!tr_valid(vcpu))
2139                         return false;
2140                 if (!ldtr_valid(vcpu))
2141                         return false;
2142         }
2143         /* TODO:
2144          * - Add checks on RIP
2145          * - Add checks on RFLAGS
2146          */
2147
2148         return true;
2149 }
2150
2151 static int init_rmode_tss(struct kvm *kvm)
2152 {
2153         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2154         u16 data = 0;
2155         int ret = 0;
2156         int r;
2157
2158         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2159         if (r < 0)
2160                 goto out;
2161         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2162         r = kvm_write_guest_page(kvm, fn++, &data,
2163                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2164         if (r < 0)
2165                 goto out;
2166         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2167         if (r < 0)
2168                 goto out;
2169         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2170         if (r < 0)
2171                 goto out;
2172         data = ~0;
2173         r = kvm_write_guest_page(kvm, fn, &data,
2174                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2175                                  sizeof(u8));
2176         if (r < 0)
2177                 goto out;
2178
2179         ret = 1;
2180 out:
2181         return ret;
2182 }
2183
2184 static int init_rmode_identity_map(struct kvm *kvm)
2185 {
2186         int i, r, ret;
2187         pfn_t identity_map_pfn;
2188         u32 tmp;
2189
2190         if (!enable_ept)
2191                 return 1;
2192         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2193                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2194                         "haven't been allocated!\n");
2195                 return 0;
2196         }
2197         if (likely(kvm->arch.ept_identity_pagetable_done))
2198                 return 1;
2199         ret = 0;
2200         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2201         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2202         if (r < 0)
2203                 goto out;
2204         /* Set up identity-mapping pagetable for EPT in real mode */
2205         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2206                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2207                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2208                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2209                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2210                 if (r < 0)
2211                         goto out;
2212         }
2213         kvm->arch.ept_identity_pagetable_done = true;
2214         ret = 1;
2215 out:
2216         return ret;
2217 }
2218
2219 static void seg_setup(int seg)
2220 {
2221         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2222         unsigned int ar;
2223
2224         vmcs_write16(sf->selector, 0);
2225         vmcs_writel(sf->base, 0);
2226         vmcs_write32(sf->limit, 0xffff);
2227         if (enable_unrestricted_guest) {
2228                 ar = 0x93;
2229                 if (seg == VCPU_SREG_CS)
2230                         ar |= 0x08; /* code segment */
2231         } else
2232                 ar = 0xf3;
2233
2234         vmcs_write32(sf->ar_bytes, ar);
2235 }
2236
2237 static int alloc_apic_access_page(struct kvm *kvm)
2238 {
2239         struct kvm_userspace_memory_region kvm_userspace_mem;
2240         int r = 0;
2241
2242         mutex_lock(&kvm->slots_lock);
2243         if (kvm->arch.apic_access_page)
2244                 goto out;
2245         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2246         kvm_userspace_mem.flags = 0;
2247         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2248         kvm_userspace_mem.memory_size = PAGE_SIZE;
2249         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2250         if (r)
2251                 goto out;
2252
2253         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2254 out:
2255         mutex_unlock(&kvm->slots_lock);
2256         return r;
2257 }
2258
2259 static int alloc_identity_pagetable(struct kvm *kvm)
2260 {
2261         struct kvm_userspace_memory_region kvm_userspace_mem;
2262         int r = 0;
2263
2264         mutex_lock(&kvm->slots_lock);
2265         if (kvm->arch.ept_identity_pagetable)
2266                 goto out;
2267         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2268         kvm_userspace_mem.flags = 0;
2269         kvm_userspace_mem.guest_phys_addr =
2270                 kvm->arch.ept_identity_map_addr;
2271         kvm_userspace_mem.memory_size = PAGE_SIZE;
2272         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2273         if (r)
2274                 goto out;
2275
2276         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2277                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2278 out:
2279         mutex_unlock(&kvm->slots_lock);
2280         return r;
2281 }
2282
2283 static void allocate_vpid(struct vcpu_vmx *vmx)
2284 {
2285         int vpid;
2286
2287         vmx->vpid = 0;
2288         if (!enable_vpid)
2289                 return;
2290         spin_lock(&vmx_vpid_lock);
2291         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2292         if (vpid < VMX_NR_VPIDS) {
2293                 vmx->vpid = vpid;
2294                 __set_bit(vpid, vmx_vpid_bitmap);
2295         }
2296         spin_unlock(&vmx_vpid_lock);
2297 }
2298
2299 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2300 {
2301         int f = sizeof(unsigned long);
2302
2303         if (!cpu_has_vmx_msr_bitmap())
2304                 return;
2305
2306         /*
2307          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2308          * have the write-low and read-high bitmap offsets the wrong way round.
2309          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2310          */
2311         if (msr <= 0x1fff) {
2312                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2313                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2314         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2315                 msr &= 0x1fff;
2316                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2317                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2318         }
2319 }
2320
2321 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2322 {
2323         if (!longmode_only)
2324                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2325         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2326 }
2327
2328 /*
2329  * Sets up the vmcs for emulated real mode.
2330  */
2331 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2332 {
2333         u32 host_sysenter_cs, msr_low, msr_high;
2334         u32 junk;
2335         u64 host_pat, tsc_this, tsc_base;
2336         unsigned long a;
2337         struct descriptor_table dt;
2338         int i;
2339         unsigned long kvm_vmx_return;
2340         u32 exec_control;
2341
2342         /* I/O */
2343         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2344         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2345
2346         if (cpu_has_vmx_msr_bitmap())
2347                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2348
2349         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2350
2351         /* Control */
2352         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2353                 vmcs_config.pin_based_exec_ctrl);
2354
2355         exec_control = vmcs_config.cpu_based_exec_ctrl;
2356         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2357                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2358 #ifdef CONFIG_X86_64
2359                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2360                                 CPU_BASED_CR8_LOAD_EXITING;
2361 #endif
2362         }
2363         if (!enable_ept)
2364                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2365                                 CPU_BASED_CR3_LOAD_EXITING  |
2366                                 CPU_BASED_INVLPG_EXITING;
2367         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2368
2369         if (cpu_has_secondary_exec_ctrls()) {
2370                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2371                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2372                         exec_control &=
2373                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2374                 if (vmx->vpid == 0)
2375                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2376                 if (!enable_ept) {
2377                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2378                         enable_unrestricted_guest = 0;
2379                 }
2380                 if (!enable_unrestricted_guest)
2381                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2382                 if (!ple_gap)
2383                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2384                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2385         }
2386
2387         if (ple_gap) {
2388                 vmcs_write32(PLE_GAP, ple_gap);
2389                 vmcs_write32(PLE_WINDOW, ple_window);
2390         }
2391
2392         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2393         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2394         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2395
2396         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2397         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2398         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2399
2400         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2401         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2402         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2403         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2404         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2405         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2406 #ifdef CONFIG_X86_64
2407         rdmsrl(MSR_FS_BASE, a);
2408         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2409         rdmsrl(MSR_GS_BASE, a);
2410         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2411 #else
2412         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2413         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2414 #endif
2415
2416         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2417
2418         kvm_get_idt(&dt);
2419         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2420
2421         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2422         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2423         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2424         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2425         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2426
2427         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2428         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2429         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2430         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2431         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2432         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2433
2434         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2435                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2436                 host_pat = msr_low | ((u64) msr_high << 32);
2437                 vmcs_write64(HOST_IA32_PAT, host_pat);
2438         }
2439         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2440                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2441                 host_pat = msr_low | ((u64) msr_high << 32);
2442                 /* Write the default value follow host pat */
2443                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2444                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2445                 vmx->vcpu.arch.pat = host_pat;
2446         }
2447
2448         for (i = 0; i < NR_VMX_MSR; ++i) {
2449                 u32 index = vmx_msr_index[i];
2450                 u32 data_low, data_high;
2451                 int j = vmx->nmsrs;
2452
2453                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2454                         continue;
2455                 if (wrmsr_safe(index, data_low, data_high) < 0)
2456                         continue;
2457                 vmx->guest_msrs[j].index = i;
2458                 vmx->guest_msrs[j].data = 0;
2459                 vmx->guest_msrs[j].mask = -1ull;
2460                 ++vmx->nmsrs;
2461         }
2462
2463         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2464
2465         /* 22.2.1, 20.8.1 */
2466         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2467
2468         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2469         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2470         if (enable_ept)
2471                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2472         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2473
2474         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2475         rdtscll(tsc_this);
2476         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2477                 tsc_base = tsc_this;
2478
2479         guest_write_tsc(0, tsc_base);
2480
2481         return 0;
2482 }
2483
2484 static int init_rmode(struct kvm *kvm)
2485 {
2486         if (!init_rmode_tss(kvm))
2487                 return 0;
2488         if (!init_rmode_identity_map(kvm))
2489                 return 0;
2490         return 1;
2491 }
2492
2493 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2494 {
2495         struct vcpu_vmx *vmx = to_vmx(vcpu);
2496         u64 msr;
2497         int ret, idx;
2498
2499         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2500         idx = srcu_read_lock(&vcpu->kvm->srcu);
2501         if (!init_rmode(vmx->vcpu.kvm)) {
2502                 ret = -ENOMEM;
2503                 goto out;
2504         }
2505
2506         vmx->rmode.vm86_active = 0;
2507
2508         vmx->soft_vnmi_blocked = 0;
2509
2510         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2511         kvm_set_cr8(&vmx->vcpu, 0);
2512         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2513         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2514                 msr |= MSR_IA32_APICBASE_BSP;
2515         kvm_set_apic_base(&vmx->vcpu, msr);
2516
2517         fx_init(&vmx->vcpu);
2518
2519         seg_setup(VCPU_SREG_CS);
2520         /*
2521          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2522          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2523          */
2524         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2525                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2526                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2527         } else {
2528                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2529                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2530         }
2531
2532         seg_setup(VCPU_SREG_DS);
2533         seg_setup(VCPU_SREG_ES);
2534         seg_setup(VCPU_SREG_FS);
2535         seg_setup(VCPU_SREG_GS);
2536         seg_setup(VCPU_SREG_SS);
2537
2538         vmcs_write16(GUEST_TR_SELECTOR, 0);
2539         vmcs_writel(GUEST_TR_BASE, 0);
2540         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2541         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2542
2543         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2544         vmcs_writel(GUEST_LDTR_BASE, 0);
2545         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2546         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2547
2548         vmcs_write32(GUEST_SYSENTER_CS, 0);
2549         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2550         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2551
2552         vmcs_writel(GUEST_RFLAGS, 0x02);
2553         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2554                 kvm_rip_write(vcpu, 0xfff0);
2555         else
2556                 kvm_rip_write(vcpu, 0);
2557         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2558
2559         vmcs_writel(GUEST_DR7, 0x400);
2560
2561         vmcs_writel(GUEST_GDTR_BASE, 0);
2562         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2563
2564         vmcs_writel(GUEST_IDTR_BASE, 0);
2565         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2566
2567         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2568         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2569         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2570
2571         /* Special registers */
2572         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2573
2574         setup_msrs(vmx);
2575
2576         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2577
2578         if (cpu_has_vmx_tpr_shadow()) {
2579                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2580                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2581                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2582                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2583                 vmcs_write32(TPR_THRESHOLD, 0);
2584         }
2585
2586         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2587                 vmcs_write64(APIC_ACCESS_ADDR,
2588                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2589
2590         if (vmx->vpid != 0)
2591                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2592
2593         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2594         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2595         vmx_set_cr4(&vmx->vcpu, 0);
2596         vmx_set_efer(&vmx->vcpu, 0);
2597         vmx_fpu_activate(&vmx->vcpu);
2598         update_exception_bitmap(&vmx->vcpu);
2599
2600         vpid_sync_vcpu_all(vmx);
2601
2602         ret = 0;
2603
2604         /* HACK: Don't enable emulation on guest boot/reset */
2605         vmx->emulation_required = 0;
2606
2607 out:
2608         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2609         return ret;
2610 }
2611
2612 static void enable_irq_window(struct kvm_vcpu *vcpu)
2613 {
2614         u32 cpu_based_vm_exec_control;
2615
2616         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2617         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2618         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2619 }
2620
2621 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2622 {
2623         u32 cpu_based_vm_exec_control;
2624
2625         if (!cpu_has_virtual_nmis()) {
2626                 enable_irq_window(vcpu);
2627                 return;
2628         }
2629
2630         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2631         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2632         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2633 }
2634
2635 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2636 {
2637         struct vcpu_vmx *vmx = to_vmx(vcpu);
2638         uint32_t intr;
2639         int irq = vcpu->arch.interrupt.nr;
2640
2641         trace_kvm_inj_virq(irq);
2642
2643         ++vcpu->stat.irq_injections;
2644         if (vmx->rmode.vm86_active) {
2645                 vmx->rmode.irq.pending = true;
2646                 vmx->rmode.irq.vector = irq;
2647                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2648                 if (vcpu->arch.interrupt.soft)
2649                         vmx->rmode.irq.rip +=
2650                                 vmx->vcpu.arch.event_exit_inst_len;
2651                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2652                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2653                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2654                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2655                 return;
2656         }
2657         intr = irq | INTR_INFO_VALID_MASK;
2658         if (vcpu->arch.interrupt.soft) {
2659                 intr |= INTR_TYPE_SOFT_INTR;
2660                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2661                              vmx->vcpu.arch.event_exit_inst_len);
2662         } else
2663                 intr |= INTR_TYPE_EXT_INTR;
2664         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2665 }
2666
2667 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2668 {
2669         struct vcpu_vmx *vmx = to_vmx(vcpu);
2670
2671         if (!cpu_has_virtual_nmis()) {
2672                 /*
2673                  * Tracking the NMI-blocked state in software is built upon
2674                  * finding the next open IRQ window. This, in turn, depends on
2675                  * well-behaving guests: They have to keep IRQs disabled at
2676                  * least as long as the NMI handler runs. Otherwise we may
2677                  * cause NMI nesting, maybe breaking the guest. But as this is
2678                  * highly unlikely, we can live with the residual risk.
2679                  */
2680                 vmx->soft_vnmi_blocked = 1;
2681                 vmx->vnmi_blocked_time = 0;
2682         }
2683
2684         ++vcpu->stat.nmi_injections;
2685         if (vmx->rmode.vm86_active) {
2686                 vmx->rmode.irq.pending = true;
2687                 vmx->rmode.irq.vector = NMI_VECTOR;
2688                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2689                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2690                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2691                              INTR_INFO_VALID_MASK);
2692                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2693                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2694                 return;
2695         }
2696         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2697                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2698 }
2699
2700 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2701 {
2702         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2703                 return 0;
2704
2705         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2706                         (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2707 }
2708
2709 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2710 {
2711         if (!cpu_has_virtual_nmis())
2712                 return to_vmx(vcpu)->soft_vnmi_blocked;
2713         else
2714                 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2715                           GUEST_INTR_STATE_NMI);
2716 }
2717
2718 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2719 {
2720         struct vcpu_vmx *vmx = to_vmx(vcpu);
2721
2722         if (!cpu_has_virtual_nmis()) {
2723                 if (vmx->soft_vnmi_blocked != masked) {
2724                         vmx->soft_vnmi_blocked = masked;
2725                         vmx->vnmi_blocked_time = 0;
2726                 }
2727         } else {
2728                 if (masked)
2729                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2730                                       GUEST_INTR_STATE_NMI);
2731                 else
2732                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2733                                         GUEST_INTR_STATE_NMI);
2734         }
2735 }
2736
2737 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2738 {
2739         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2740                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2741                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2742 }
2743
2744 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2745 {
2746         int ret;
2747         struct kvm_userspace_memory_region tss_mem = {
2748                 .slot = TSS_PRIVATE_MEMSLOT,
2749                 .guest_phys_addr = addr,
2750                 .memory_size = PAGE_SIZE * 3,
2751                 .flags = 0,
2752         };
2753
2754         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2755         if (ret)
2756                 return ret;
2757         kvm->arch.tss_addr = addr;
2758         return 0;
2759 }
2760
2761 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2762                                   int vec, u32 err_code)
2763 {
2764         /*
2765          * Instruction with address size override prefix opcode 0x67
2766          * Cause the #SS fault with 0 error code in VM86 mode.
2767          */
2768         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2769                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2770                         return 1;
2771         /*
2772          * Forward all other exceptions that are valid in real mode.
2773          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2774          *        the required debugging infrastructure rework.
2775          */
2776         switch (vec) {
2777         case DB_VECTOR:
2778                 if (vcpu->guest_debug &
2779                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2780                         return 0;
2781                 kvm_queue_exception(vcpu, vec);
2782                 return 1;
2783         case BP_VECTOR:
2784                 /*
2785                  * Update instruction length as we may reinject the exception
2786                  * from user space while in guest debugging mode.
2787                  */
2788                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2789                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2790                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2791                         return 0;
2792                 /* fall through */
2793         case DE_VECTOR:
2794         case OF_VECTOR:
2795         case BR_VECTOR:
2796         case UD_VECTOR:
2797         case DF_VECTOR:
2798         case SS_VECTOR:
2799         case GP_VECTOR:
2800         case MF_VECTOR:
2801                 kvm_queue_exception(vcpu, vec);
2802                 return 1;
2803         }
2804         return 0;
2805 }
2806
2807 /*
2808  * Trigger machine check on the host. We assume all the MSRs are already set up
2809  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2810  * We pass a fake environment to the machine check handler because we want
2811  * the guest to be always treated like user space, no matter what context
2812  * it used internally.
2813  */
2814 static void kvm_machine_check(void)
2815 {
2816 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2817         struct pt_regs regs = {
2818                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2819                 .flags = X86_EFLAGS_IF,
2820         };
2821
2822         do_machine_check(&regs, 0);
2823 #endif
2824 }
2825
2826 static int handle_machine_check(struct kvm_vcpu *vcpu)
2827 {
2828         /* already handled by vcpu_run */
2829         return 1;
2830 }
2831
2832 static int handle_exception(struct kvm_vcpu *vcpu)
2833 {
2834         struct vcpu_vmx *vmx = to_vmx(vcpu);
2835         struct kvm_run *kvm_run = vcpu->run;
2836         u32 intr_info, ex_no, error_code;
2837         unsigned long cr2, rip, dr6;
2838         u32 vect_info;
2839         enum emulation_result er;
2840
2841         vect_info = vmx->idt_vectoring_info;
2842         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2843
2844         if (is_machine_check(intr_info))
2845                 return handle_machine_check(vcpu);
2846
2847         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2848             !is_page_fault(intr_info)) {
2849                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2850                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2851                 vcpu->run->internal.ndata = 2;
2852                 vcpu->run->internal.data[0] = vect_info;
2853                 vcpu->run->internal.data[1] = intr_info;
2854                 return 0;
2855         }
2856
2857         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2858                 return 1;  /* already handled by vmx_vcpu_run() */
2859
2860         if (is_no_device(intr_info)) {
2861                 vmx_fpu_activate(vcpu);
2862                 return 1;
2863         }
2864
2865         if (is_invalid_opcode(intr_info)) {
2866                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2867                 if (er != EMULATE_DONE)
2868                         kvm_queue_exception(vcpu, UD_VECTOR);
2869                 return 1;
2870         }
2871
2872         error_code = 0;
2873         rip = kvm_rip_read(vcpu);
2874         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2875                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2876         if (is_page_fault(intr_info)) {
2877                 /* EPT won't cause page fault directly */
2878                 if (enable_ept)
2879                         BUG();
2880                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2881                 trace_kvm_page_fault(cr2, error_code);
2882
2883                 if (kvm_event_needs_reinjection(vcpu))
2884                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2885                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2886         }
2887
2888         if (vmx->rmode.vm86_active &&
2889             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2890                                                                 error_code)) {
2891                 if (vcpu->arch.halt_request) {
2892                         vcpu->arch.halt_request = 0;
2893                         return kvm_emulate_halt(vcpu);
2894                 }
2895                 return 1;
2896         }
2897
2898         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2899         switch (ex_no) {
2900         case DB_VECTOR:
2901                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2902                 if (!(vcpu->guest_debug &
2903                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2904                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2905                         kvm_queue_exception(vcpu, DB_VECTOR);
2906                         return 1;
2907                 }
2908                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2909                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2910                 /* fall through */
2911         case BP_VECTOR:
2912                 /*
2913                  * Update instruction length as we may reinject #BP from
2914                  * user space while in guest debugging mode. Reading it for
2915                  * #DB as well causes no harm, it is not used in that case.
2916                  */
2917                 vmx->vcpu.arch.event_exit_inst_len =
2918                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2919                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2920                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2921                 kvm_run->debug.arch.exception = ex_no;
2922                 break;
2923         default:
2924                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2925                 kvm_run->ex.exception = ex_no;
2926                 kvm_run->ex.error_code = error_code;
2927                 break;
2928         }
2929         return 0;
2930 }
2931
2932 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2933 {
2934         ++vcpu->stat.irq_exits;
2935         return 1;
2936 }
2937
2938 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2939 {
2940         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2941         return 0;
2942 }
2943
2944 static int handle_io(struct kvm_vcpu *vcpu)
2945 {
2946         unsigned long exit_qualification;
2947         int size, in, string;
2948         unsigned port;
2949
2950         ++vcpu->stat.io_exits;
2951         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2952         string = (exit_qualification & 16) != 0;
2953
2954         if (string) {
2955                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2956                         return 0;
2957                 return 1;
2958         }
2959
2960         size = (exit_qualification & 7) + 1;
2961         in = (exit_qualification & 8) != 0;
2962         port = exit_qualification >> 16;
2963
2964         skip_emulated_instruction(vcpu);
2965         return kvm_emulate_pio(vcpu, in, size, port);
2966 }
2967
2968 static void
2969 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2970 {
2971         /*
2972          * Patch in the VMCALL instruction:
2973          */
2974         hypercall[0] = 0x0f;
2975         hypercall[1] = 0x01;
2976         hypercall[2] = 0xc1;
2977 }
2978
2979 static int handle_cr(struct kvm_vcpu *vcpu)
2980 {
2981         unsigned long exit_qualification, val;
2982         int cr;
2983         int reg;
2984
2985         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2986         cr = exit_qualification & 15;
2987         reg = (exit_qualification >> 8) & 15;
2988         switch ((exit_qualification >> 4) & 3) {
2989         case 0: /* mov to cr */
2990                 val = kvm_register_read(vcpu, reg);
2991                 trace_kvm_cr_write(cr, val);
2992                 switch (cr) {
2993                 case 0:
2994                         kvm_set_cr0(vcpu, val);
2995                         skip_emulated_instruction(vcpu);
2996                         return 1;
2997                 case 3:
2998                         kvm_set_cr3(vcpu, val);
2999                         skip_emulated_instruction(vcpu);
3000                         return 1;
3001                 case 4:
3002                         kvm_set_cr4(vcpu, val);
3003                         skip_emulated_instruction(vcpu);
3004                         return 1;
3005                 case 8: {
3006                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3007                                 u8 cr8 = kvm_register_read(vcpu, reg);
3008                                 kvm_set_cr8(vcpu, cr8);
3009                                 skip_emulated_instruction(vcpu);
3010                                 if (irqchip_in_kernel(vcpu->kvm))
3011                                         return 1;
3012                                 if (cr8_prev <= cr8)
3013                                         return 1;
3014                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3015                                 return 0;
3016                         }
3017                 };
3018                 break;
3019         case 2: /* clts */
3020                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3021                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3022                 skip_emulated_instruction(vcpu);
3023                 vmx_fpu_activate(vcpu);
3024                 return 1;
3025         case 1: /*mov from cr*/
3026                 switch (cr) {
3027                 case 3:
3028                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3029                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3030                         skip_emulated_instruction(vcpu);
3031                         return 1;
3032                 case 8:
3033                         val = kvm_get_cr8(vcpu);
3034                         kvm_register_write(vcpu, reg, val);
3035                         trace_kvm_cr_read(cr, val);
3036                         skip_emulated_instruction(vcpu);
3037                         return 1;
3038                 }
3039                 break;
3040         case 3: /* lmsw */
3041                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3042                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3043                 kvm_lmsw(vcpu, val);
3044
3045                 skip_emulated_instruction(vcpu);
3046                 return 1;
3047         default:
3048                 break;
3049         }
3050         vcpu->run->exit_reason = 0;
3051         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3052                (int)(exit_qualification >> 4) & 3, cr);
3053         return 0;
3054 }
3055
3056 static int check_dr_alias(struct kvm_vcpu *vcpu)
3057 {
3058         if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
3059                 kvm_queue_exception(vcpu, UD_VECTOR);
3060                 return -1;
3061         }
3062         return 0;
3063 }
3064
3065 static int handle_dr(struct kvm_vcpu *vcpu)
3066 {
3067         unsigned long exit_qualification;
3068         unsigned long val;
3069         int dr, reg;
3070
3071         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3072         if (!kvm_require_cpl(vcpu, 0))
3073                 return 1;
3074         dr = vmcs_readl(GUEST_DR7);
3075         if (dr & DR7_GD) {
3076                 /*
3077                  * As the vm-exit takes precedence over the debug trap, we
3078                  * need to emulate the latter, either for the host or the
3079                  * guest debugging itself.
3080                  */
3081                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3082                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3083                         vcpu->run->debug.arch.dr7 = dr;
3084                         vcpu->run->debug.arch.pc =
3085                                 vmcs_readl(GUEST_CS_BASE) +
3086                                 vmcs_readl(GUEST_RIP);
3087                         vcpu->run->debug.arch.exception = DB_VECTOR;
3088                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3089                         return 0;
3090                 } else {
3091                         vcpu->arch.dr7 &= ~DR7_GD;
3092                         vcpu->arch.dr6 |= DR6_BD;
3093                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3094                         kvm_queue_exception(vcpu, DB_VECTOR);
3095                         return 1;
3096                 }
3097         }
3098
3099         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3100         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3101         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3102         if (exit_qualification & TYPE_MOV_FROM_DR) {
3103                 switch (dr) {
3104                 case 0 ... 3:
3105                         val = vcpu->arch.db[dr];
3106                         break;
3107                 case 4:
3108                         if (check_dr_alias(vcpu) < 0)
3109                                 return 1;
3110                         /* fall through */
3111                 case 6:
3112                         val = vcpu->arch.dr6;
3113                         break;
3114                 case 5:
3115                         if (check_dr_alias(vcpu) < 0)
3116                                 return 1;
3117                         /* fall through */
3118                 default: /* 7 */
3119                         val = vcpu->arch.dr7;
3120                         break;
3121                 }
3122                 kvm_register_write(vcpu, reg, val);
3123         } else {
3124                 val = vcpu->arch.regs[reg];
3125                 switch (dr) {
3126                 case 0 ... 3:
3127                         vcpu->arch.db[dr] = val;
3128                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3129                                 vcpu->arch.eff_db[dr] = val;
3130                         break;
3131                 case 4:
3132                         if (check_dr_alias(vcpu) < 0)
3133                                 return 1;
3134                         /* fall through */
3135                 case 6:
3136                         if (val & 0xffffffff00000000ULL) {
3137                                 kvm_inject_gp(vcpu, 0);
3138                                 return 1;
3139                         }
3140                         vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3141                         break;
3142                 case 5:
3143                         if (check_dr_alias(vcpu) < 0)
3144                                 return 1;
3145                         /* fall through */
3146                 default: /* 7 */
3147                         if (val & 0xffffffff00000000ULL) {
3148                                 kvm_inject_gp(vcpu, 0);
3149                                 return 1;
3150                         }
3151                         vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3152                         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3153                                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3154                                 vcpu->arch.switch_db_regs =
3155                                         (val & DR7_BP_EN_MASK);
3156                         }
3157                         break;
3158                 }
3159         }
3160         skip_emulated_instruction(vcpu);
3161         return 1;
3162 }
3163
3164 static int handle_cpuid(struct kvm_vcpu *vcpu)
3165 {
3166         kvm_emulate_cpuid(vcpu);
3167         return 1;
3168 }
3169
3170 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3171 {
3172         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3173         u64 data;
3174
3175         if (vmx_get_msr(vcpu, ecx, &data)) {
3176                 trace_kvm_msr_read_ex(ecx);
3177                 kvm_inject_gp(vcpu, 0);
3178                 return 1;
3179         }
3180
3181         trace_kvm_msr_read(ecx, data);
3182
3183         /* FIXME: handling of bits 32:63 of rax, rdx */
3184         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3185         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3186         skip_emulated_instruction(vcpu);
3187         return 1;
3188 }
3189
3190 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3191 {
3192         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3193         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3194                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3195
3196         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3197                 trace_kvm_msr_write_ex(ecx, data);
3198                 kvm_inject_gp(vcpu, 0);
3199                 return 1;
3200         }
3201
3202         trace_kvm_msr_write(ecx, data);
3203         skip_emulated_instruction(vcpu);
3204         return 1;
3205 }
3206
3207 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3208 {
3209         return 1;
3210 }
3211
3212 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3213 {
3214         u32 cpu_based_vm_exec_control;
3215
3216         /* clear pending irq */
3217         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3218         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3219         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3220
3221         ++vcpu->stat.irq_window_exits;
3222
3223         /*
3224          * If the user space waits to inject interrupts, exit as soon as
3225          * possible
3226          */
3227         if (!irqchip_in_kernel(vcpu->kvm) &&
3228             vcpu->run->request_interrupt_window &&
3229             !kvm_cpu_has_interrupt(vcpu)) {
3230                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3231                 return 0;
3232         }
3233         return 1;
3234 }
3235
3236 static int handle_halt(struct kvm_vcpu *vcpu)
3237 {
3238         skip_emulated_instruction(vcpu);
3239         return kvm_emulate_halt(vcpu);
3240 }
3241
3242 static int handle_vmcall(struct kvm_vcpu *vcpu)
3243 {
3244         skip_emulated_instruction(vcpu);
3245         kvm_emulate_hypercall(vcpu);
3246         return 1;
3247 }
3248
3249 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3250 {
3251         kvm_queue_exception(vcpu, UD_VECTOR);
3252         return 1;
3253 }
3254
3255 static int handle_invlpg(struct kvm_vcpu *vcpu)
3256 {
3257         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3258
3259         kvm_mmu_invlpg(vcpu, exit_qualification);
3260         skip_emulated_instruction(vcpu);
3261         return 1;
3262 }
3263
3264 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3265 {
3266         skip_emulated_instruction(vcpu);
3267         /* TODO: Add support for VT-d/pass-through device */
3268         return 1;
3269 }
3270
3271 static int handle_apic_access(struct kvm_vcpu *vcpu)
3272 {
3273         unsigned long exit_qualification;
3274         enum emulation_result er;
3275         unsigned long offset;
3276
3277         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3278         offset = exit_qualification & 0xffful;
3279
3280         er = emulate_instruction(vcpu, 0, 0, 0);
3281
3282         if (er !=  EMULATE_DONE) {
3283                 printk(KERN_ERR
3284                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3285                        offset);
3286                 return -ENOEXEC;
3287         }
3288         return 1;
3289 }
3290
3291 static int handle_task_switch(struct kvm_vcpu *vcpu)
3292 {
3293         struct vcpu_vmx *vmx = to_vmx(vcpu);
3294         unsigned long exit_qualification;
3295         u16 tss_selector;
3296         int reason, type, idt_v;
3297
3298         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3299         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3300
3301         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3302
3303         reason = (u32)exit_qualification >> 30;
3304         if (reason == TASK_SWITCH_GATE && idt_v) {
3305                 switch (type) {
3306                 case INTR_TYPE_NMI_INTR:
3307                         vcpu->arch.nmi_injected = false;
3308                         if (cpu_has_virtual_nmis())
3309                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3310                                               GUEST_INTR_STATE_NMI);
3311                         break;
3312                 case INTR_TYPE_EXT_INTR:
3313                 case INTR_TYPE_SOFT_INTR:
3314                         kvm_clear_interrupt_queue(vcpu);
3315                         break;
3316                 case INTR_TYPE_HARD_EXCEPTION:
3317                 case INTR_TYPE_SOFT_EXCEPTION:
3318                         kvm_clear_exception_queue(vcpu);
3319                         break;
3320                 default:
3321                         break;
3322                 }
3323         }
3324         tss_selector = exit_qualification;
3325
3326         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3327                        type != INTR_TYPE_EXT_INTR &&
3328                        type != INTR_TYPE_NMI_INTR))
3329                 skip_emulated_instruction(vcpu);
3330
3331         if (!kvm_task_switch(vcpu, tss_selector, reason))
3332                 return 0;
3333
3334         /* clear all local breakpoint enable flags */
3335         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3336
3337         /*
3338          * TODO: What about debug traps on tss switch?
3339          *       Are we supposed to inject them and update dr6?
3340          */
3341
3342         return 1;
3343 }
3344
3345 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3346 {
3347         unsigned long exit_qualification;
3348         gpa_t gpa;
3349         int gla_validity;
3350
3351         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3352
3353         if (exit_qualification & (1 << 6)) {
3354                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3355                 return -EINVAL;
3356         }
3357
3358         gla_validity = (exit_qualification >> 7) & 0x3;
3359         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3360                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3361                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3362                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3363                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3364                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3365                         (long unsigned int)exit_qualification);
3366                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3367                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3368                 return 0;
3369         }
3370
3371         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3372         trace_kvm_page_fault(gpa, exit_qualification);
3373         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3374 }
3375
3376 static u64 ept_rsvd_mask(u64 spte, int level)
3377 {
3378         int i;
3379         u64 mask = 0;
3380
3381         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3382                 mask |= (1ULL << i);
3383
3384         if (level > 2)
3385                 /* bits 7:3 reserved */
3386                 mask |= 0xf8;
3387         else if (level == 2) {
3388                 if (spte & (1ULL << 7))
3389                         /* 2MB ref, bits 20:12 reserved */
3390                         mask |= 0x1ff000;
3391                 else
3392                         /* bits 6:3 reserved */
3393                         mask |= 0x78;
3394         }
3395
3396         return mask;
3397 }
3398
3399 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3400                                        int level)
3401 {
3402         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3403
3404         /* 010b (write-only) */
3405         WARN_ON((spte & 0x7) == 0x2);
3406
3407         /* 110b (write/execute) */
3408         WARN_ON((spte & 0x7) == 0x6);
3409
3410         /* 100b (execute-only) and value not supported by logical processor */
3411         if (!cpu_has_vmx_ept_execute_only())
3412                 WARN_ON((spte & 0x7) == 0x4);
3413
3414         /* not 000b */
3415         if ((spte & 0x7)) {
3416                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3417
3418                 if (rsvd_bits != 0) {
3419                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3420                                          __func__, rsvd_bits);
3421                         WARN_ON(1);
3422                 }
3423
3424                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3425                         u64 ept_mem_type = (spte & 0x38) >> 3;
3426
3427                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3428                             ept_mem_type == 7) {
3429                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3430                                                 __func__, ept_mem_type);
3431                                 WARN_ON(1);
3432                         }
3433                 }
3434         }
3435 }
3436
3437 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3438 {
3439         u64 sptes[4];
3440         int nr_sptes, i;
3441         gpa_t gpa;
3442
3443         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3444
3445         printk(KERN_ERR "EPT: Misconfiguration.\n");
3446         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3447
3448         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3449
3450         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3451                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3452
3453         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3454         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3455
3456         return 0;
3457 }
3458
3459 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3460 {
3461         u32 cpu_based_vm_exec_control;
3462
3463         /* clear pending NMI */
3464         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3465         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3466         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3467         ++vcpu->stat.nmi_window_exits;
3468
3469         return 1;
3470 }
3471
3472 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3473 {
3474         struct vcpu_vmx *vmx = to_vmx(vcpu);
3475         enum emulation_result err = EMULATE_DONE;
3476         int ret = 1;
3477
3478         while (!guest_state_valid(vcpu)) {
3479                 err = emulate_instruction(vcpu, 0, 0, 0);
3480
3481                 if (err == EMULATE_DO_MMIO) {
3482                         ret = 0;
3483                         goto out;
3484                 }
3485
3486                 if (err != EMULATE_DONE) {
3487                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3488                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3489                         vcpu->run->internal.ndata = 0;
3490                         ret = 0;
3491                         goto out;
3492                 }
3493
3494                 if (signal_pending(current))
3495                         goto out;
3496                 if (need_resched())
3497                         schedule();
3498         }
3499
3500         vmx->emulation_required = 0;
3501 out:
3502         return ret;
3503 }
3504
3505 /*
3506  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3507  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3508  */
3509 static int handle_pause(struct kvm_vcpu *vcpu)
3510 {
3511         skip_emulated_instruction(vcpu);
3512         kvm_vcpu_on_spin(vcpu);
3513
3514         return 1;
3515 }
3516
3517 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3518 {
3519         kvm_queue_exception(vcpu, UD_VECTOR);
3520         return 1;
3521 }
3522
3523 /*
3524  * The exit handlers return 1 if the exit was handled fully and guest execution
3525  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3526  * to be done to userspace and return 0.
3527  */
3528 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3529         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3530         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3531         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3532         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3533         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3534         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3535         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3536         [EXIT_REASON_CPUID]                   = handle_cpuid,
3537         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3538         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3539         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3540         [EXIT_REASON_HLT]                     = handle_halt,
3541         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3542         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3543         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3544         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3545         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3546         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3547         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3548         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3549         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3550         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3551         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3552         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3553         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3554         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3555         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3556         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3557         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3558         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3559         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3560         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3561         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3562 };
3563
3564 static const int kvm_vmx_max_exit_handlers =
3565         ARRAY_SIZE(kvm_vmx_exit_handlers);
3566
3567 /*
3568  * The guest has exited.  See if we can fix it or if we need userspace
3569  * assistance.
3570  */
3571 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3572 {
3573         struct vcpu_vmx *vmx = to_vmx(vcpu);
3574         u32 exit_reason = vmx->exit_reason;
3575         u32 vectoring_info = vmx->idt_vectoring_info;
3576
3577         trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3578
3579         /* If guest state is invalid, start emulating */
3580         if (vmx->emulation_required && emulate_invalid_guest_state)
3581                 return handle_invalid_guest_state(vcpu);
3582
3583         /* Access CR3 don't cause VMExit in paging mode, so we need
3584          * to sync with guest real CR3. */
3585         if (enable_ept && is_paging(vcpu))
3586                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3587
3588         if (unlikely(vmx->fail)) {
3589                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3590                 vcpu->run->fail_entry.hardware_entry_failure_reason
3591                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3592                 return 0;
3593         }
3594
3595         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3596                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3597                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3598                         exit_reason != EXIT_REASON_TASK_SWITCH))
3599                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3600                        "(0x%x) and exit reason is 0x%x\n",
3601                        __func__, vectoring_info, exit_reason);
3602
3603         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3604                 if (vmx_interrupt_allowed(vcpu)) {
3605                         vmx->soft_vnmi_blocked = 0;
3606                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3607                            vcpu->arch.nmi_pending) {
3608                         /*
3609                          * This CPU don't support us in finding the end of an
3610                          * NMI-blocked window if the guest runs with IRQs
3611                          * disabled. So we pull the trigger after 1 s of
3612                          * futile waiting, but inform the user about this.
3613                          */
3614                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3615                                "state on VCPU %d after 1 s timeout\n",
3616                                __func__, vcpu->vcpu_id);
3617                         vmx->soft_vnmi_blocked = 0;
3618                 }
3619         }
3620
3621         if (exit_reason < kvm_vmx_max_exit_handlers
3622             && kvm_vmx_exit_handlers[exit_reason])
3623                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3624         else {
3625                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3626                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3627         }
3628         return 0;
3629 }
3630
3631 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3632 {
3633         if (irr == -1 || tpr < irr) {
3634                 vmcs_write32(TPR_THRESHOLD, 0);
3635                 return;
3636         }
3637
3638         vmcs_write32(TPR_THRESHOLD, irr);
3639 }
3640
3641 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3642 {
3643         u32 exit_intr_info;
3644         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3645         bool unblock_nmi;
3646         u8 vector;
3647         int type;
3648         bool idtv_info_valid;
3649
3650         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3651
3652         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3653
3654         /* Handle machine checks before interrupts are enabled */
3655         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3656             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3657                 && is_machine_check(exit_intr_info)))
3658                 kvm_machine_check();
3659
3660         /* We need to handle NMIs before interrupts are enabled */
3661         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3662             (exit_intr_info & INTR_INFO_VALID_MASK)) {
3663                 kvm_before_handle_nmi(&vmx->vcpu);
3664                 asm("int $2");
3665                 kvm_after_handle_nmi(&vmx->vcpu);
3666         }
3667
3668         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3669
3670         if (cpu_has_virtual_nmis()) {
3671                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3672                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3673                 /*
3674                  * SDM 3: 27.7.1.2 (September 2008)
3675                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3676                  * a guest IRET fault.
3677                  * SDM 3: 23.2.2 (September 2008)
3678                  * Bit 12 is undefined in any of the following cases:
3679                  *  If the VM exit sets the valid bit in the IDT-vectoring
3680                  *   information field.
3681                  *  If the VM exit is due to a double fault.
3682                  */
3683                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3684                     vector != DF_VECTOR && !idtv_info_valid)
3685                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3686                                       GUEST_INTR_STATE_NMI);
3687         } else if (unlikely(vmx->soft_vnmi_blocked))
3688                 vmx->vnmi_blocked_time +=
3689                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3690
3691         vmx->vcpu.arch.nmi_injected = false;
3692         kvm_clear_exception_queue(&vmx->vcpu);
3693         kvm_clear_interrupt_queue(&vmx->vcpu);
3694
3695         if (!idtv_info_valid)
3696                 return;
3697
3698         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3699         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3700
3701         switch (type) {
3702         case INTR_TYPE_NMI_INTR:
3703                 vmx->vcpu.arch.nmi_injected = true;
3704                 /*
3705                  * SDM 3: 27.7.1.2 (September 2008)
3706                  * Clear bit "block by NMI" before VM entry if a NMI
3707                  * delivery faulted.
3708                  */
3709                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3710                                 GUEST_INTR_STATE_NMI);
3711                 break;
3712         case INTR_TYPE_SOFT_EXCEPTION:
3713                 vmx->vcpu.arch.event_exit_inst_len =
3714                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3715                 /* fall through */
3716         case INTR_TYPE_HARD_EXCEPTION:
3717                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3718                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3719                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3720                 } else
3721                         kvm_queue_exception(&vmx->vcpu, vector);
3722                 break;
3723         case INTR_TYPE_SOFT_INTR:
3724                 vmx->vcpu.arch.event_exit_inst_len =
3725                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3726                 /* fall through */
3727         case INTR_TYPE_EXT_INTR:
3728                 kvm_queue_interrupt(&vmx->vcpu, vector,
3729                         type == INTR_TYPE_SOFT_INTR);
3730                 break;
3731         default:
3732                 break;
3733         }
3734 }
3735
3736 /*
3737  * Failure to inject an interrupt should give us the information
3738  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3739  * when fetching the interrupt redirection bitmap in the real-mode
3740  * tss, this doesn't happen.  So we do it ourselves.
3741  */
3742 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3743 {
3744         vmx->rmode.irq.pending = 0;
3745         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3746                 return;
3747         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3748         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3749                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3750                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3751                 return;
3752         }
3753         vmx->idt_vectoring_info =
3754                 VECTORING_INFO_VALID_MASK
3755                 | INTR_TYPE_EXT_INTR
3756                 | vmx->rmode.irq.vector;
3757 }
3758
3759 #ifdef CONFIG_X86_64
3760 #define R "r"
3761 #define Q "q"
3762 #else
3763 #define R "e"
3764 #define Q "l"
3765 #endif
3766
3767 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3768 {
3769         struct vcpu_vmx *vmx = to_vmx(vcpu);
3770
3771         /* Record the guest's net vcpu time for enforced NMI injections. */
3772         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3773                 vmx->entry_time = ktime_get();
3774
3775         /* Don't enter VMX if guest state is invalid, let the exit handler
3776            start emulation until we arrive back to a valid state */
3777         if (vmx->emulation_required && emulate_invalid_guest_state)
3778                 return;
3779
3780         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3781                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3782         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3783                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3784
3785         /* When single-stepping over STI and MOV SS, we must clear the
3786          * corresponding interruptibility bits in the guest state. Otherwise
3787          * vmentry fails as it then expects bit 14 (BS) in pending debug
3788          * exceptions being set, but that's not correct for the guest debugging
3789          * case. */
3790         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3791                 vmx_set_interrupt_shadow(vcpu, 0);
3792
3793         /*
3794          * Loading guest fpu may have cleared host cr0.ts
3795          */
3796         vmcs_writel(HOST_CR0, read_cr0());
3797
3798         asm(
3799                 /* Store host registers */
3800                 "push %%"R"dx; push %%"R"bp;"
3801                 "push %%"R"cx \n\t"
3802                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3803                 "je 1f \n\t"
3804                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3805                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3806                 "1: \n\t"
3807                 /* Reload cr2 if changed */
3808                 "mov %c[cr2](%0), %%"R"ax \n\t"
3809                 "mov %%cr2, %%"R"dx \n\t"
3810                 "cmp %%"R"ax, %%"R"dx \n\t"
3811                 "je 2f \n\t"
3812                 "mov %%"R"ax, %%cr2 \n\t"
3813                 "2: \n\t"
3814                 /* Check if vmlaunch of vmresume is needed */
3815                 "cmpl $0, %c[launched](%0) \n\t"
3816                 /* Load guest registers.  Don't clobber flags. */
3817                 "mov %c[rax](%0), %%"R"ax \n\t"
3818                 "mov %c[rbx](%0), %%"R"bx \n\t"
3819                 "mov %c[rdx](%0), %%"R"dx \n\t"
3820                 "mov %c[rsi](%0), %%"R"si \n\t"
3821                 "mov %c[rdi](%0), %%"R"di \n\t"
3822                 "mov %c[rbp](%0), %%"R"bp \n\t"
3823 #ifdef CONFIG_X86_64
3824                 "mov %c[r8](%0),  %%r8  \n\t"
3825                 "mov %c[r9](%0),  %%r9  \n\t"
3826                 "mov %c[r10](%0), %%r10 \n\t"
3827                 "mov %c[r11](%0), %%r11 \n\t"
3828                 "mov %c[r12](%0), %%r12 \n\t"
3829                 "mov %c[r13](%0), %%r13 \n\t"
3830                 "mov %c[r14](%0), %%r14 \n\t"
3831                 "mov %c[r15](%0), %%r15 \n\t"
3832 #endif
3833                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3834
3835                 /* Enter guest mode */
3836                 "jne .Llaunched \n\t"
3837                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3838                 "jmp .Lkvm_vmx_return \n\t"
3839                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3840                 ".Lkvm_vmx_return: "
3841                 /* Save guest registers, load host registers, keep flags */
3842                 "xchg %0,     (%%"R"sp) \n\t"
3843                 "mov %%"R"ax, %c[rax](%0) \n\t"
3844                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3845                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3846                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3847                 "mov %%"R"si, %c[rsi](%0) \n\t"
3848                 "mov %%"R"di, %c[rdi](%0) \n\t"
3849                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3850 #ifdef CONFIG_X86_64
3851                 "mov %%r8,  %c[r8](%0) \n\t"
3852                 "mov %%r9,  %c[r9](%0) \n\t"
3853                 "mov %%r10, %c[r10](%0) \n\t"
3854                 "mov %%r11, %c[r11](%0) \n\t"
3855                 "mov %%r12, %c[r12](%0) \n\t"
3856                 "mov %%r13, %c[r13](%0) \n\t"
3857                 "mov %%r14, %c[r14](%0) \n\t"
3858                 "mov %%r15, %c[r15](%0) \n\t"
3859 #endif
3860                 "mov %%cr2, %%"R"ax   \n\t"
3861                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3862
3863                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3864                 "setbe %c[fail](%0) \n\t"
3865               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3866                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3867                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3868                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3869                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3870                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3871                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3872                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3873                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3874                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3875                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3876 #ifdef CONFIG_X86_64
3877                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3878                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3879                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3880                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3881                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3882                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3883                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3884                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3885 #endif
3886                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3887               : "cc", "memory"
3888                 , R"bx", R"di", R"si"
3889 #ifdef CONFIG_X86_64
3890                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3891 #endif
3892               );
3893
3894         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3895                                   | (1 << VCPU_EXREG_PDPTR));
3896         vcpu->arch.regs_dirty = 0;
3897
3898         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3899         if (vmx->rmode.irq.pending)
3900                 fixup_rmode_irq(vmx);
3901
3902         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3903         vmx->launched = 1;
3904
3905         vmx_complete_interrupts(vmx);
3906 }
3907
3908 #undef R
3909 #undef Q
3910
3911 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3912 {
3913         struct vcpu_vmx *vmx = to_vmx(vcpu);
3914
3915         if (vmx->vmcs) {
3916                 vcpu_clear(vmx);
3917                 free_vmcs(vmx->vmcs);
3918                 vmx->vmcs = NULL;
3919         }
3920 }
3921
3922 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3923 {
3924         struct vcpu_vmx *vmx = to_vmx(vcpu);
3925
3926         spin_lock(&vmx_vpid_lock);
3927         if (vmx->vpid != 0)
3928                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3929         spin_unlock(&vmx_vpid_lock);
3930         vmx_free_vmcs(vcpu);
3931         kfree(vmx->guest_msrs);
3932         kvm_vcpu_uninit(vcpu);
3933         kmem_cache_free(kvm_vcpu_cache, vmx);
3934 }
3935
3936 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3937 {
3938         int err;
3939         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3940         int cpu;
3941
3942         if (!vmx)
3943                 return ERR_PTR(-ENOMEM);
3944
3945         allocate_vpid(vmx);
3946
3947         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3948         if (err)
3949                 goto free_vcpu;
3950
3951         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3952         if (!vmx->guest_msrs) {
3953                 err = -ENOMEM;
3954                 goto uninit_vcpu;
3955         }
3956
3957         vmx->vmcs = alloc_vmcs();
3958         if (!vmx->vmcs)
3959                 goto free_msrs;
3960
3961         vmcs_clear(vmx->vmcs);
3962
3963         cpu = get_cpu();
3964         vmx_vcpu_load(&vmx->vcpu, cpu);
3965         err = vmx_vcpu_setup(vmx);
3966         vmx_vcpu_put(&vmx->vcpu);
3967         put_cpu();
3968         if (err)
3969                 goto free_vmcs;
3970         if (vm_need_virtualize_apic_accesses(kvm))
3971                 if (alloc_apic_access_page(kvm) != 0)
3972                         goto free_vmcs;
3973
3974         if (enable_ept) {
3975                 if (!kvm->arch.ept_identity_map_addr)
3976                         kvm->arch.ept_identity_map_addr =
3977                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3978                 if (alloc_identity_pagetable(kvm) != 0)
3979                         goto free_vmcs;
3980         }
3981
3982         return &vmx->vcpu;
3983
3984 free_vmcs:
3985         free_vmcs(vmx->vmcs);
3986 free_msrs:
3987         kfree(vmx->guest_msrs);
3988 uninit_vcpu:
3989         kvm_vcpu_uninit(&vmx->vcpu);
3990 free_vcpu:
3991         kmem_cache_free(kvm_vcpu_cache, vmx);
3992         return ERR_PTR(err);
3993 }
3994
3995 static void __init vmx_check_processor_compat(void *rtn)
3996 {
3997         struct vmcs_config vmcs_conf;
3998
3999         *(int *)rtn = 0;
4000         if (setup_vmcs_config(&vmcs_conf) < 0)
4001                 *(int *)rtn = -EIO;
4002         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4003                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4004                                 smp_processor_id());
4005                 *(int *)rtn = -EIO;
4006         }
4007 }
4008
4009 static int get_ept_level(void)
4010 {
4011         return VMX_EPT_DEFAULT_GAW + 1;
4012 }
4013
4014 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4015 {
4016         u64 ret;
4017
4018         /* For VT-d and EPT combination
4019          * 1. MMIO: always map as UC
4020          * 2. EPT with VT-d:
4021          *   a. VT-d without snooping control feature: can't guarantee the
4022          *      result, try to trust guest.
4023          *   b. VT-d with snooping control feature: snooping control feature of
4024          *      VT-d engine can guarantee the cache correctness. Just set it
4025          *      to WB to keep consistent with host. So the same as item 3.
4026          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4027          *    consistent with host MTRR
4028          */
4029         if (is_mmio)
4030                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4031         else if (vcpu->kvm->arch.iommu_domain &&
4032                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4033                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4034                       VMX_EPT_MT_EPTE_SHIFT;
4035         else
4036                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4037                         | VMX_EPT_IPAT_BIT;
4038
4039         return ret;
4040 }
4041
4042 #define _ER(x) { EXIT_REASON_##x, #x }
4043
4044 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4045         _ER(EXCEPTION_NMI),
4046         _ER(EXTERNAL_INTERRUPT),
4047         _ER(TRIPLE_FAULT),
4048         _ER(PENDING_INTERRUPT),
4049         _ER(NMI_WINDOW),
4050         _ER(TASK_SWITCH),
4051         _ER(CPUID),
4052         _ER(HLT),
4053         _ER(INVLPG),
4054         _ER(RDPMC),
4055         _ER(RDTSC),
4056         _ER(VMCALL),
4057         _ER(VMCLEAR),
4058         _ER(VMLAUNCH),
4059         _ER(VMPTRLD),
4060         _ER(VMPTRST),
4061         _ER(VMREAD),
4062         _ER(VMRESUME),
4063         _ER(VMWRITE),
4064         _ER(VMOFF),
4065         _ER(VMON),
4066         _ER(CR_ACCESS),
4067         _ER(DR_ACCESS),
4068         _ER(IO_INSTRUCTION),
4069         _ER(MSR_READ),
4070         _ER(MSR_WRITE),
4071         _ER(MWAIT_INSTRUCTION),
4072         _ER(MONITOR_INSTRUCTION),
4073         _ER(PAUSE_INSTRUCTION),
4074         _ER(MCE_DURING_VMENTRY),
4075         _ER(TPR_BELOW_THRESHOLD),
4076         _ER(APIC_ACCESS),
4077         _ER(EPT_VIOLATION),
4078         _ER(EPT_MISCONFIG),
4079         _ER(WBINVD),
4080         { -1, NULL }
4081 };
4082
4083 #undef _ER
4084
4085 static int vmx_get_lpage_level(void)
4086 {
4087         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4088                 return PT_DIRECTORY_LEVEL;
4089         else
4090                 /* For shadow and EPT supported 1GB page */
4091                 return PT_PDPE_LEVEL;
4092 }
4093
4094 static inline u32 bit(int bitno)
4095 {
4096         return 1 << (bitno & 31);
4097 }
4098
4099 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4100 {
4101         struct kvm_cpuid_entry2 *best;
4102         struct vcpu_vmx *vmx = to_vmx(vcpu);
4103         u32 exec_control;
4104
4105         vmx->rdtscp_enabled = false;
4106         if (vmx_rdtscp_supported()) {
4107                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4108                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4109                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4110                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4111                                 vmx->rdtscp_enabled = true;
4112                         else {
4113                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4114                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4115                                                 exec_control);
4116                         }
4117                 }
4118         }
4119 }
4120
4121 static struct kvm_x86_ops vmx_x86_ops = {
4122         .cpu_has_kvm_support = cpu_has_kvm_support,
4123         .disabled_by_bios = vmx_disabled_by_bios,
4124         .hardware_setup = hardware_setup,
4125         .hardware_unsetup = hardware_unsetup,
4126         .check_processor_compatibility = vmx_check_processor_compat,
4127         .hardware_enable = hardware_enable,
4128         .hardware_disable = hardware_disable,
4129         .cpu_has_accelerated_tpr = report_flexpriority,
4130
4131         .vcpu_create = vmx_create_vcpu,
4132         .vcpu_free = vmx_free_vcpu,
4133         .vcpu_reset = vmx_vcpu_reset,
4134
4135         .prepare_guest_switch = vmx_save_host_state,
4136         .vcpu_load = vmx_vcpu_load,
4137         .vcpu_put = vmx_vcpu_put,
4138
4139         .set_guest_debug = set_guest_debug,
4140         .get_msr = vmx_get_msr,
4141         .set_msr = vmx_set_msr,
4142         .get_segment_base = vmx_get_segment_base,
4143         .get_segment = vmx_get_segment,
4144         .set_segment = vmx_set_segment,
4145         .get_cpl = vmx_get_cpl,
4146         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4147         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4148         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4149         .set_cr0 = vmx_set_cr0,
4150         .set_cr3 = vmx_set_cr3,
4151         .set_cr4 = vmx_set_cr4,
4152         .set_efer = vmx_set_efer,
4153         .get_idt = vmx_get_idt,
4154         .set_idt = vmx_set_idt,
4155         .get_gdt = vmx_get_gdt,
4156         .set_gdt = vmx_set_gdt,
4157         .cache_reg = vmx_cache_reg,
4158         .get_rflags = vmx_get_rflags,
4159         .set_rflags = vmx_set_rflags,
4160         .fpu_activate = vmx_fpu_activate,
4161         .fpu_deactivate = vmx_fpu_deactivate,
4162
4163         .tlb_flush = vmx_flush_tlb,
4164
4165         .run = vmx_vcpu_run,
4166         .handle_exit = vmx_handle_exit,
4167         .skip_emulated_instruction = skip_emulated_instruction,
4168         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4169         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4170         .patch_hypercall = vmx_patch_hypercall,
4171         .set_irq = vmx_inject_irq,
4172         .set_nmi = vmx_inject_nmi,
4173         .queue_exception = vmx_queue_exception,
4174         .interrupt_allowed = vmx_interrupt_allowed,
4175         .nmi_allowed = vmx_nmi_allowed,
4176         .get_nmi_mask = vmx_get_nmi_mask,
4177         .set_nmi_mask = vmx_set_nmi_mask,
4178         .enable_nmi_window = enable_nmi_window,
4179         .enable_irq_window = enable_irq_window,
4180         .update_cr8_intercept = update_cr8_intercept,
4181
4182         .set_tss_addr = vmx_set_tss_addr,
4183         .get_tdp_level = get_ept_level,
4184         .get_mt_mask = vmx_get_mt_mask,
4185
4186         .exit_reasons_str = vmx_exit_reasons_str,
4187         .get_lpage_level = vmx_get_lpage_level,
4188
4189         .cpuid_update = vmx_cpuid_update,
4190
4191         .rdtscp_supported = vmx_rdtscp_supported,
4192 };
4193
4194 static int __init vmx_init(void)
4195 {
4196         int r, i;
4197
4198         rdmsrl_safe(MSR_EFER, &host_efer);
4199
4200         for (i = 0; i < NR_VMX_MSR; ++i)
4201                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4202
4203         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4204         if (!vmx_io_bitmap_a)
4205                 return -ENOMEM;
4206
4207         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4208         if (!vmx_io_bitmap_b) {
4209                 r = -ENOMEM;
4210                 goto out;
4211         }
4212
4213         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4214         if (!vmx_msr_bitmap_legacy) {
4215                 r = -ENOMEM;
4216                 goto out1;
4217         }
4218
4219         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4220         if (!vmx_msr_bitmap_longmode) {
4221                 r = -ENOMEM;
4222                 goto out2;
4223         }
4224
4225         /*
4226          * Allow direct access to the PC debug port (it is often used for I/O
4227          * delays, but the vmexits simply slow things down).
4228          */
4229         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4230         clear_bit(0x80, vmx_io_bitmap_a);
4231
4232         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4233
4234         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4235         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4236
4237         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4238
4239         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4240         if (r)
4241                 goto out3;
4242
4243         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4244         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4245         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4246         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4247         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4248         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4249
4250         if (enable_ept) {
4251                 bypass_guest_pf = 0;
4252                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4253                         VMX_EPT_WRITABLE_MASK);
4254                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4255                                 VMX_EPT_EXECUTABLE_MASK);
4256                 kvm_enable_tdp();
4257         } else
4258                 kvm_disable_tdp();
4259
4260         if (bypass_guest_pf)
4261                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4262
4263         return 0;
4264
4265 out3:
4266         free_page((unsigned long)vmx_msr_bitmap_longmode);
4267 out2:
4268         free_page((unsigned long)vmx_msr_bitmap_legacy);
4269 out1:
4270         free_page((unsigned long)vmx_io_bitmap_b);
4271 out:
4272         free_page((unsigned long)vmx_io_bitmap_a);
4273         return r;
4274 }
4275
4276 static void __exit vmx_exit(void)
4277 {
4278         free_page((unsigned long)vmx_msr_bitmap_legacy);
4279         free_page((unsigned long)vmx_msr_bitmap_longmode);
4280         free_page((unsigned long)vmx_io_bitmap_b);
4281         free_page((unsigned long)vmx_io_bitmap_a);
4282
4283         kvm_exit();
4284 }
4285
4286 module_init(vmx_init)
4287 module_exit(vmx_exit)