KVM: VMX: Allow single-stepping when uninterruptible
[sfrench/cifs-2.6.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  *
9  * Authors:
10  *   Avi Kivity   <avi@qumranet.com>
11  *   Yaniv Kamay  <yaniv@qumranet.com>
12  *
13  * This work is licensed under the terms of the GNU GPL, version 2.  See
14  * the COPYING file in the top-level directory.
15  *
16  */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
29 #include "x86.h"
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33 #include <asm/vmx.h>
34 #include <asm/virtext.h>
35
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
37
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
40
41 static int bypass_guest_pf = 1;
42 module_param(bypass_guest_pf, bool, 0);
43
44 static int enable_vpid = 1;
45 module_param(enable_vpid, bool, 0);
46
47 static int flexpriority_enabled = 1;
48 module_param(flexpriority_enabled, bool, 0);
49
50 static int enable_ept = 1;
51 module_param(enable_ept, bool, 0);
52
53 static int emulate_invalid_guest_state = 0;
54 module_param(emulate_invalid_guest_state, bool, 0);
55
56 struct vmcs {
57         u32 revision_id;
58         u32 abort;
59         char data[0];
60 };
61
62 struct vcpu_vmx {
63         struct kvm_vcpu       vcpu;
64         struct list_head      local_vcpus_link;
65         unsigned long         host_rsp;
66         int                   launched;
67         u8                    fail;
68         u32                   idt_vectoring_info;
69         struct kvm_msr_entry *guest_msrs;
70         struct kvm_msr_entry *host_msrs;
71         int                   nmsrs;
72         int                   save_nmsrs;
73         int                   msr_offset_efer;
74 #ifdef CONFIG_X86_64
75         int                   msr_offset_kernel_gs_base;
76 #endif
77         struct vmcs          *vmcs;
78         struct {
79                 int           loaded;
80                 u16           fs_sel, gs_sel, ldt_sel;
81                 int           gs_ldt_reload_needed;
82                 int           fs_reload_needed;
83                 int           guest_efer_loaded;
84         } host_state;
85         struct {
86                 struct {
87                         bool pending;
88                         u8 vector;
89                         unsigned rip;
90                 } irq;
91         } rmode;
92         int vpid;
93         bool emulation_required;
94
95         /* Support for vnmi-less CPUs */
96         int soft_vnmi_blocked;
97         ktime_t entry_time;
98         s64 vnmi_blocked_time;
99 };
100
101 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
102 {
103         return container_of(vcpu, struct vcpu_vmx, vcpu);
104 }
105
106 static int init_rmode(struct kvm *kvm);
107 static u64 construct_eptp(unsigned long root_hpa);
108
109 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
110 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
111 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
112
113 static struct page *vmx_io_bitmap_a;
114 static struct page *vmx_io_bitmap_b;
115 static struct page *vmx_msr_bitmap;
116
117 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
118 static DEFINE_SPINLOCK(vmx_vpid_lock);
119
120 static struct vmcs_config {
121         int size;
122         int order;
123         u32 revision_id;
124         u32 pin_based_exec_ctrl;
125         u32 cpu_based_exec_ctrl;
126         u32 cpu_based_2nd_exec_ctrl;
127         u32 vmexit_ctrl;
128         u32 vmentry_ctrl;
129 } vmcs_config;
130
131 static struct vmx_capability {
132         u32 ept;
133         u32 vpid;
134 } vmx_capability;
135
136 #define VMX_SEGMENT_FIELD(seg)                                  \
137         [VCPU_SREG_##seg] = {                                   \
138                 .selector = GUEST_##seg##_SELECTOR,             \
139                 .base = GUEST_##seg##_BASE,                     \
140                 .limit = GUEST_##seg##_LIMIT,                   \
141                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
142         }
143
144 static struct kvm_vmx_segment_field {
145         unsigned selector;
146         unsigned base;
147         unsigned limit;
148         unsigned ar_bytes;
149 } kvm_vmx_segment_fields[] = {
150         VMX_SEGMENT_FIELD(CS),
151         VMX_SEGMENT_FIELD(DS),
152         VMX_SEGMENT_FIELD(ES),
153         VMX_SEGMENT_FIELD(FS),
154         VMX_SEGMENT_FIELD(GS),
155         VMX_SEGMENT_FIELD(SS),
156         VMX_SEGMENT_FIELD(TR),
157         VMX_SEGMENT_FIELD(LDTR),
158 };
159
160 /*
161  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
162  * away by decrementing the array size.
163  */
164 static const u32 vmx_msr_index[] = {
165 #ifdef CONFIG_X86_64
166         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
167 #endif
168         MSR_EFER, MSR_K6_STAR,
169 };
170 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
171
172 static void load_msrs(struct kvm_msr_entry *e, int n)
173 {
174         int i;
175
176         for (i = 0; i < n; ++i)
177                 wrmsrl(e[i].index, e[i].data);
178 }
179
180 static void save_msrs(struct kvm_msr_entry *e, int n)
181 {
182         int i;
183
184         for (i = 0; i < n; ++i)
185                 rdmsrl(e[i].index, e[i].data);
186 }
187
188 static inline int is_page_fault(u32 intr_info)
189 {
190         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
191                              INTR_INFO_VALID_MASK)) ==
192                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
193 }
194
195 static inline int is_no_device(u32 intr_info)
196 {
197         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
198                              INTR_INFO_VALID_MASK)) ==
199                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
200 }
201
202 static inline int is_invalid_opcode(u32 intr_info)
203 {
204         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
205                              INTR_INFO_VALID_MASK)) ==
206                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
207 }
208
209 static inline int is_external_interrupt(u32 intr_info)
210 {
211         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
212                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
213 }
214
215 static inline int cpu_has_vmx_msr_bitmap(void)
216 {
217         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
218 }
219
220 static inline int cpu_has_vmx_tpr_shadow(void)
221 {
222         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
223 }
224
225 static inline int vm_need_tpr_shadow(struct kvm *kvm)
226 {
227         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
228 }
229
230 static inline int cpu_has_secondary_exec_ctrls(void)
231 {
232         return (vmcs_config.cpu_based_exec_ctrl &
233                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
234 }
235
236 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
237 {
238         return flexpriority_enabled
239                 && (vmcs_config.cpu_based_2nd_exec_ctrl &
240                     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
241 }
242
243 static inline int cpu_has_vmx_invept_individual_addr(void)
244 {
245         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
246 }
247
248 static inline int cpu_has_vmx_invept_context(void)
249 {
250         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
251 }
252
253 static inline int cpu_has_vmx_invept_global(void)
254 {
255         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
256 }
257
258 static inline int cpu_has_vmx_ept(void)
259 {
260         return (vmcs_config.cpu_based_2nd_exec_ctrl &
261                 SECONDARY_EXEC_ENABLE_EPT);
262 }
263
264 static inline int vm_need_ept(void)
265 {
266         return (cpu_has_vmx_ept() && enable_ept);
267 }
268
269 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
270 {
271         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
272                 (irqchip_in_kernel(kvm)));
273 }
274
275 static inline int cpu_has_vmx_vpid(void)
276 {
277         return (vmcs_config.cpu_based_2nd_exec_ctrl &
278                 SECONDARY_EXEC_ENABLE_VPID);
279 }
280
281 static inline int cpu_has_virtual_nmis(void)
282 {
283         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
284 }
285
286 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
287 {
288         int i;
289
290         for (i = 0; i < vmx->nmsrs; ++i)
291                 if (vmx->guest_msrs[i].index == msr)
292                         return i;
293         return -1;
294 }
295
296 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
297 {
298     struct {
299         u64 vpid : 16;
300         u64 rsvd : 48;
301         u64 gva;
302     } operand = { vpid, 0, gva };
303
304     asm volatile (__ex(ASM_VMX_INVVPID)
305                   /* CF==1 or ZF==1 --> rc = -1 */
306                   "; ja 1f ; ud2 ; 1:"
307                   : : "a"(&operand), "c"(ext) : "cc", "memory");
308 }
309
310 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
311 {
312         struct {
313                 u64 eptp, gpa;
314         } operand = {eptp, gpa};
315
316         asm volatile (__ex(ASM_VMX_INVEPT)
317                         /* CF==1 or ZF==1 --> rc = -1 */
318                         "; ja 1f ; ud2 ; 1:\n"
319                         : : "a" (&operand), "c" (ext) : "cc", "memory");
320 }
321
322 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
323 {
324         int i;
325
326         i = __find_msr_index(vmx, msr);
327         if (i >= 0)
328                 return &vmx->guest_msrs[i];
329         return NULL;
330 }
331
332 static void vmcs_clear(struct vmcs *vmcs)
333 {
334         u64 phys_addr = __pa(vmcs);
335         u8 error;
336
337         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
338                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
339                       : "cc", "memory");
340         if (error)
341                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
342                        vmcs, phys_addr);
343 }
344
345 static void __vcpu_clear(void *arg)
346 {
347         struct vcpu_vmx *vmx = arg;
348         int cpu = raw_smp_processor_id();
349
350         if (vmx->vcpu.cpu == cpu)
351                 vmcs_clear(vmx->vmcs);
352         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
353                 per_cpu(current_vmcs, cpu) = NULL;
354         rdtscll(vmx->vcpu.arch.host_tsc);
355         list_del(&vmx->local_vcpus_link);
356         vmx->vcpu.cpu = -1;
357         vmx->launched = 0;
358 }
359
360 static void vcpu_clear(struct vcpu_vmx *vmx)
361 {
362         if (vmx->vcpu.cpu == -1)
363                 return;
364         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
365 }
366
367 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
368 {
369         if (vmx->vpid == 0)
370                 return;
371
372         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
373 }
374
375 static inline void ept_sync_global(void)
376 {
377         if (cpu_has_vmx_invept_global())
378                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
379 }
380
381 static inline void ept_sync_context(u64 eptp)
382 {
383         if (vm_need_ept()) {
384                 if (cpu_has_vmx_invept_context())
385                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
386                 else
387                         ept_sync_global();
388         }
389 }
390
391 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
392 {
393         if (vm_need_ept()) {
394                 if (cpu_has_vmx_invept_individual_addr())
395                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
396                                         eptp, gpa);
397                 else
398                         ept_sync_context(eptp);
399         }
400 }
401
402 static unsigned long vmcs_readl(unsigned long field)
403 {
404         unsigned long value;
405
406         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
407                       : "=a"(value) : "d"(field) : "cc");
408         return value;
409 }
410
411 static u16 vmcs_read16(unsigned long field)
412 {
413         return vmcs_readl(field);
414 }
415
416 static u32 vmcs_read32(unsigned long field)
417 {
418         return vmcs_readl(field);
419 }
420
421 static u64 vmcs_read64(unsigned long field)
422 {
423 #ifdef CONFIG_X86_64
424         return vmcs_readl(field);
425 #else
426         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
427 #endif
428 }
429
430 static noinline void vmwrite_error(unsigned long field, unsigned long value)
431 {
432         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
433                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
434         dump_stack();
435 }
436
437 static void vmcs_writel(unsigned long field, unsigned long value)
438 {
439         u8 error;
440
441         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
442                        : "=q"(error) : "a"(value), "d"(field) : "cc");
443         if (unlikely(error))
444                 vmwrite_error(field, value);
445 }
446
447 static void vmcs_write16(unsigned long field, u16 value)
448 {
449         vmcs_writel(field, value);
450 }
451
452 static void vmcs_write32(unsigned long field, u32 value)
453 {
454         vmcs_writel(field, value);
455 }
456
457 static void vmcs_write64(unsigned long field, u64 value)
458 {
459         vmcs_writel(field, value);
460 #ifndef CONFIG_X86_64
461         asm volatile ("");
462         vmcs_writel(field+1, value >> 32);
463 #endif
464 }
465
466 static void vmcs_clear_bits(unsigned long field, u32 mask)
467 {
468         vmcs_writel(field, vmcs_readl(field) & ~mask);
469 }
470
471 static void vmcs_set_bits(unsigned long field, u32 mask)
472 {
473         vmcs_writel(field, vmcs_readl(field) | mask);
474 }
475
476 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
477 {
478         u32 eb;
479
480         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
481         if (!vcpu->fpu_active)
482                 eb |= 1u << NM_VECTOR;
483         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
484                 if (vcpu->guest_debug &
485                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
486                         eb |= 1u << DB_VECTOR;
487                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
488                         eb |= 1u << BP_VECTOR;
489         }
490         if (vcpu->arch.rmode.active)
491                 eb = ~0;
492         if (vm_need_ept())
493                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
494         vmcs_write32(EXCEPTION_BITMAP, eb);
495 }
496
497 static void reload_tss(void)
498 {
499         /*
500          * VT restores TR but not its size.  Useless.
501          */
502         struct descriptor_table gdt;
503         struct desc_struct *descs;
504
505         kvm_get_gdt(&gdt);
506         descs = (void *)gdt.base;
507         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
508         load_TR_desc();
509 }
510
511 static void load_transition_efer(struct vcpu_vmx *vmx)
512 {
513         int efer_offset = vmx->msr_offset_efer;
514         u64 host_efer = vmx->host_msrs[efer_offset].data;
515         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
516         u64 ignore_bits;
517
518         if (efer_offset < 0)
519                 return;
520         /*
521          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
522          * outside long mode
523          */
524         ignore_bits = EFER_NX | EFER_SCE;
525 #ifdef CONFIG_X86_64
526         ignore_bits |= EFER_LMA | EFER_LME;
527         /* SCE is meaningful only in long mode on Intel */
528         if (guest_efer & EFER_LMA)
529                 ignore_bits &= ~(u64)EFER_SCE;
530 #endif
531         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
532                 return;
533
534         vmx->host_state.guest_efer_loaded = 1;
535         guest_efer &= ~ignore_bits;
536         guest_efer |= host_efer & ignore_bits;
537         wrmsrl(MSR_EFER, guest_efer);
538         vmx->vcpu.stat.efer_reload++;
539 }
540
541 static void reload_host_efer(struct vcpu_vmx *vmx)
542 {
543         if (vmx->host_state.guest_efer_loaded) {
544                 vmx->host_state.guest_efer_loaded = 0;
545                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
546         }
547 }
548
549 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
550 {
551         struct vcpu_vmx *vmx = to_vmx(vcpu);
552
553         if (vmx->host_state.loaded)
554                 return;
555
556         vmx->host_state.loaded = 1;
557         /*
558          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
559          * allow segment selectors with cpl > 0 or ti == 1.
560          */
561         vmx->host_state.ldt_sel = kvm_read_ldt();
562         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
563         vmx->host_state.fs_sel = kvm_read_fs();
564         if (!(vmx->host_state.fs_sel & 7)) {
565                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
566                 vmx->host_state.fs_reload_needed = 0;
567         } else {
568                 vmcs_write16(HOST_FS_SELECTOR, 0);
569                 vmx->host_state.fs_reload_needed = 1;
570         }
571         vmx->host_state.gs_sel = kvm_read_gs();
572         if (!(vmx->host_state.gs_sel & 7))
573                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
574         else {
575                 vmcs_write16(HOST_GS_SELECTOR, 0);
576                 vmx->host_state.gs_ldt_reload_needed = 1;
577         }
578
579 #ifdef CONFIG_X86_64
580         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
581         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
582 #else
583         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
584         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
585 #endif
586
587 #ifdef CONFIG_X86_64
588         if (is_long_mode(&vmx->vcpu))
589                 save_msrs(vmx->host_msrs +
590                           vmx->msr_offset_kernel_gs_base, 1);
591
592 #endif
593         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
594         load_transition_efer(vmx);
595 }
596
597 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
598 {
599         unsigned long flags;
600
601         if (!vmx->host_state.loaded)
602                 return;
603
604         ++vmx->vcpu.stat.host_state_reload;
605         vmx->host_state.loaded = 0;
606         if (vmx->host_state.fs_reload_needed)
607                 kvm_load_fs(vmx->host_state.fs_sel);
608         if (vmx->host_state.gs_ldt_reload_needed) {
609                 kvm_load_ldt(vmx->host_state.ldt_sel);
610                 /*
611                  * If we have to reload gs, we must take care to
612                  * preserve our gs base.
613                  */
614                 local_irq_save(flags);
615                 kvm_load_gs(vmx->host_state.gs_sel);
616 #ifdef CONFIG_X86_64
617                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
618 #endif
619                 local_irq_restore(flags);
620         }
621         reload_tss();
622         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
623         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
624         reload_host_efer(vmx);
625 }
626
627 static void vmx_load_host_state(struct vcpu_vmx *vmx)
628 {
629         preempt_disable();
630         __vmx_load_host_state(vmx);
631         preempt_enable();
632 }
633
634 /*
635  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
636  * vcpu mutex is already taken.
637  */
638 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
639 {
640         struct vcpu_vmx *vmx = to_vmx(vcpu);
641         u64 phys_addr = __pa(vmx->vmcs);
642         u64 tsc_this, delta, new_offset;
643
644         if (vcpu->cpu != cpu) {
645                 vcpu_clear(vmx);
646                 kvm_migrate_timers(vcpu);
647                 vpid_sync_vcpu_all(vmx);
648                 local_irq_disable();
649                 list_add(&vmx->local_vcpus_link,
650                          &per_cpu(vcpus_on_cpu, cpu));
651                 local_irq_enable();
652         }
653
654         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
655                 u8 error;
656
657                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
658                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
659                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
660                               : "cc");
661                 if (error)
662                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
663                                vmx->vmcs, phys_addr);
664         }
665
666         if (vcpu->cpu != cpu) {
667                 struct descriptor_table dt;
668                 unsigned long sysenter_esp;
669
670                 vcpu->cpu = cpu;
671                 /*
672                  * Linux uses per-cpu TSS and GDT, so set these when switching
673                  * processors.
674                  */
675                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
676                 kvm_get_gdt(&dt);
677                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
678
679                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
680                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
681
682                 /*
683                  * Make sure the time stamp counter is monotonous.
684                  */
685                 rdtscll(tsc_this);
686                 if (tsc_this < vcpu->arch.host_tsc) {
687                         delta = vcpu->arch.host_tsc - tsc_this;
688                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
689                         vmcs_write64(TSC_OFFSET, new_offset);
690                 }
691         }
692 }
693
694 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
695 {
696         __vmx_load_host_state(to_vmx(vcpu));
697 }
698
699 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
700 {
701         if (vcpu->fpu_active)
702                 return;
703         vcpu->fpu_active = 1;
704         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
705         if (vcpu->arch.cr0 & X86_CR0_TS)
706                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
707         update_exception_bitmap(vcpu);
708 }
709
710 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
711 {
712         if (!vcpu->fpu_active)
713                 return;
714         vcpu->fpu_active = 0;
715         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
716         update_exception_bitmap(vcpu);
717 }
718
719 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
720 {
721         return vmcs_readl(GUEST_RFLAGS);
722 }
723
724 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
725 {
726         if (vcpu->arch.rmode.active)
727                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
728         vmcs_writel(GUEST_RFLAGS, rflags);
729 }
730
731 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
732 {
733         unsigned long rip;
734         u32 interruptibility;
735
736         rip = kvm_rip_read(vcpu);
737         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
738         kvm_rip_write(vcpu, rip);
739
740         /*
741          * We emulated an instruction, so temporary interrupt blocking
742          * should be removed, if set.
743          */
744         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
745         if (interruptibility & 3)
746                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
747                              interruptibility & ~3);
748         vcpu->arch.interrupt_window_open = 1;
749 }
750
751 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
752                                 bool has_error_code, u32 error_code)
753 {
754         struct vcpu_vmx *vmx = to_vmx(vcpu);
755         u32 intr_info = nr | INTR_INFO_VALID_MASK;
756
757         if (has_error_code) {
758                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
759                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
760         }
761
762         if (vcpu->arch.rmode.active) {
763                 vmx->rmode.irq.pending = true;
764                 vmx->rmode.irq.vector = nr;
765                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
766                 if (nr == BP_VECTOR || nr == OF_VECTOR)
767                         vmx->rmode.irq.rip++;
768                 intr_info |= INTR_TYPE_SOFT_INTR;
769                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
770                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
771                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
772                 return;
773         }
774
775         if (nr == BP_VECTOR || nr == OF_VECTOR) {
776                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
777                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
778         } else
779                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
780
781         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
782 }
783
784 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
785 {
786         return false;
787 }
788
789 /*
790  * Swap MSR entry in host/guest MSR entry array.
791  */
792 #ifdef CONFIG_X86_64
793 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
794 {
795         struct kvm_msr_entry tmp;
796
797         tmp = vmx->guest_msrs[to];
798         vmx->guest_msrs[to] = vmx->guest_msrs[from];
799         vmx->guest_msrs[from] = tmp;
800         tmp = vmx->host_msrs[to];
801         vmx->host_msrs[to] = vmx->host_msrs[from];
802         vmx->host_msrs[from] = tmp;
803 }
804 #endif
805
806 /*
807  * Set up the vmcs to automatically save and restore system
808  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
809  * mode, as fiddling with msrs is very expensive.
810  */
811 static void setup_msrs(struct vcpu_vmx *vmx)
812 {
813         int save_nmsrs;
814
815         vmx_load_host_state(vmx);
816         save_nmsrs = 0;
817 #ifdef CONFIG_X86_64
818         if (is_long_mode(&vmx->vcpu)) {
819                 int index;
820
821                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
822                 if (index >= 0)
823                         move_msr_up(vmx, index, save_nmsrs++);
824                 index = __find_msr_index(vmx, MSR_LSTAR);
825                 if (index >= 0)
826                         move_msr_up(vmx, index, save_nmsrs++);
827                 index = __find_msr_index(vmx, MSR_CSTAR);
828                 if (index >= 0)
829                         move_msr_up(vmx, index, save_nmsrs++);
830                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
831                 if (index >= 0)
832                         move_msr_up(vmx, index, save_nmsrs++);
833                 /*
834                  * MSR_K6_STAR is only needed on long mode guests, and only
835                  * if efer.sce is enabled.
836                  */
837                 index = __find_msr_index(vmx, MSR_K6_STAR);
838                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
839                         move_msr_up(vmx, index, save_nmsrs++);
840         }
841 #endif
842         vmx->save_nmsrs = save_nmsrs;
843
844 #ifdef CONFIG_X86_64
845         vmx->msr_offset_kernel_gs_base =
846                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
847 #endif
848         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
849 }
850
851 /*
852  * reads and returns guest's timestamp counter "register"
853  * guest_tsc = host_tsc + tsc_offset    -- 21.3
854  */
855 static u64 guest_read_tsc(void)
856 {
857         u64 host_tsc, tsc_offset;
858
859         rdtscll(host_tsc);
860         tsc_offset = vmcs_read64(TSC_OFFSET);
861         return host_tsc + tsc_offset;
862 }
863
864 /*
865  * writes 'guest_tsc' into guest's timestamp counter "register"
866  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
867  */
868 static void guest_write_tsc(u64 guest_tsc)
869 {
870         u64 host_tsc;
871
872         rdtscll(host_tsc);
873         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
874 }
875
876 /*
877  * Reads an msr value (of 'msr_index') into 'pdata'.
878  * Returns 0 on success, non-0 otherwise.
879  * Assumes vcpu_load() was already called.
880  */
881 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
882 {
883         u64 data;
884         struct kvm_msr_entry *msr;
885
886         if (!pdata) {
887                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
888                 return -EINVAL;
889         }
890
891         switch (msr_index) {
892 #ifdef CONFIG_X86_64
893         case MSR_FS_BASE:
894                 data = vmcs_readl(GUEST_FS_BASE);
895                 break;
896         case MSR_GS_BASE:
897                 data = vmcs_readl(GUEST_GS_BASE);
898                 break;
899         case MSR_EFER:
900                 return kvm_get_msr_common(vcpu, msr_index, pdata);
901 #endif
902         case MSR_IA32_TIME_STAMP_COUNTER:
903                 data = guest_read_tsc();
904                 break;
905         case MSR_IA32_SYSENTER_CS:
906                 data = vmcs_read32(GUEST_SYSENTER_CS);
907                 break;
908         case MSR_IA32_SYSENTER_EIP:
909                 data = vmcs_readl(GUEST_SYSENTER_EIP);
910                 break;
911         case MSR_IA32_SYSENTER_ESP:
912                 data = vmcs_readl(GUEST_SYSENTER_ESP);
913                 break;
914         default:
915                 vmx_load_host_state(to_vmx(vcpu));
916                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
917                 if (msr) {
918                         data = msr->data;
919                         break;
920                 }
921                 return kvm_get_msr_common(vcpu, msr_index, pdata);
922         }
923
924         *pdata = data;
925         return 0;
926 }
927
928 /*
929  * Writes msr value into into the appropriate "register".
930  * Returns 0 on success, non-0 otherwise.
931  * Assumes vcpu_load() was already called.
932  */
933 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
934 {
935         struct vcpu_vmx *vmx = to_vmx(vcpu);
936         struct kvm_msr_entry *msr;
937         int ret = 0;
938
939         switch (msr_index) {
940 #ifdef CONFIG_X86_64
941         case MSR_EFER:
942                 vmx_load_host_state(vmx);
943                 ret = kvm_set_msr_common(vcpu, msr_index, data);
944                 break;
945         case MSR_FS_BASE:
946                 vmcs_writel(GUEST_FS_BASE, data);
947                 break;
948         case MSR_GS_BASE:
949                 vmcs_writel(GUEST_GS_BASE, data);
950                 break;
951 #endif
952         case MSR_IA32_SYSENTER_CS:
953                 vmcs_write32(GUEST_SYSENTER_CS, data);
954                 break;
955         case MSR_IA32_SYSENTER_EIP:
956                 vmcs_writel(GUEST_SYSENTER_EIP, data);
957                 break;
958         case MSR_IA32_SYSENTER_ESP:
959                 vmcs_writel(GUEST_SYSENTER_ESP, data);
960                 break;
961         case MSR_IA32_TIME_STAMP_COUNTER:
962                 guest_write_tsc(data);
963                 break;
964         case MSR_P6_PERFCTR0:
965         case MSR_P6_PERFCTR1:
966         case MSR_P6_EVNTSEL0:
967         case MSR_P6_EVNTSEL1:
968                 /*
969                  * Just discard all writes to the performance counters; this
970                  * should keep both older linux and windows 64-bit guests
971                  * happy
972                  */
973                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
974
975                 break;
976         case MSR_IA32_CR_PAT:
977                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
978                         vmcs_write64(GUEST_IA32_PAT, data);
979                         vcpu->arch.pat = data;
980                         break;
981                 }
982                 /* Otherwise falls through to kvm_set_msr_common */
983         default:
984                 vmx_load_host_state(vmx);
985                 msr = find_msr_entry(vmx, msr_index);
986                 if (msr) {
987                         msr->data = data;
988                         break;
989                 }
990                 ret = kvm_set_msr_common(vcpu, msr_index, data);
991         }
992
993         return ret;
994 }
995
996 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
997 {
998         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
999         switch (reg) {
1000         case VCPU_REGS_RSP:
1001                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1002                 break;
1003         case VCPU_REGS_RIP:
1004                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1005                 break;
1006         default:
1007                 break;
1008         }
1009 }
1010
1011 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1012 {
1013         int old_debug = vcpu->guest_debug;
1014         unsigned long flags;
1015
1016         vcpu->guest_debug = dbg->control;
1017         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1018                 vcpu->guest_debug = 0;
1019
1020         flags = vmcs_readl(GUEST_RFLAGS);
1021         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1022                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1023         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1024                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1025         vmcs_writel(GUEST_RFLAGS, flags);
1026
1027         update_exception_bitmap(vcpu);
1028
1029         return 0;
1030 }
1031
1032 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1033 {
1034         if (!vcpu->arch.interrupt.pending)
1035                 return -1;
1036         return vcpu->arch.interrupt.nr;
1037 }
1038
1039 static __init int cpu_has_kvm_support(void)
1040 {
1041         return cpu_has_vmx();
1042 }
1043
1044 static __init int vmx_disabled_by_bios(void)
1045 {
1046         u64 msr;
1047
1048         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1049         return (msr & (FEATURE_CONTROL_LOCKED |
1050                        FEATURE_CONTROL_VMXON_ENABLED))
1051             == FEATURE_CONTROL_LOCKED;
1052         /* locked but not enabled */
1053 }
1054
1055 static void hardware_enable(void *garbage)
1056 {
1057         int cpu = raw_smp_processor_id();
1058         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1059         u64 old;
1060
1061         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1062         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1063         if ((old & (FEATURE_CONTROL_LOCKED |
1064                     FEATURE_CONTROL_VMXON_ENABLED))
1065             != (FEATURE_CONTROL_LOCKED |
1066                 FEATURE_CONTROL_VMXON_ENABLED))
1067                 /* enable and lock */
1068                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1069                        FEATURE_CONTROL_LOCKED |
1070                        FEATURE_CONTROL_VMXON_ENABLED);
1071         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1072         asm volatile (ASM_VMX_VMXON_RAX
1073                       : : "a"(&phys_addr), "m"(phys_addr)
1074                       : "memory", "cc");
1075 }
1076
1077 static void vmclear_local_vcpus(void)
1078 {
1079         int cpu = raw_smp_processor_id();
1080         struct vcpu_vmx *vmx, *n;
1081
1082         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1083                                  local_vcpus_link)
1084                 __vcpu_clear(vmx);
1085 }
1086
1087
1088 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1089  * tricks.
1090  */
1091 static void kvm_cpu_vmxoff(void)
1092 {
1093         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1094         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1095 }
1096
1097 static void hardware_disable(void *garbage)
1098 {
1099         vmclear_local_vcpus();
1100         kvm_cpu_vmxoff();
1101 }
1102
1103 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1104                                       u32 msr, u32 *result)
1105 {
1106         u32 vmx_msr_low, vmx_msr_high;
1107         u32 ctl = ctl_min | ctl_opt;
1108
1109         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1110
1111         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1112         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1113
1114         /* Ensure minimum (required) set of control bits are supported. */
1115         if (ctl_min & ~ctl)
1116                 return -EIO;
1117
1118         *result = ctl;
1119         return 0;
1120 }
1121
1122 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1123 {
1124         u32 vmx_msr_low, vmx_msr_high;
1125         u32 min, opt, min2, opt2;
1126         u32 _pin_based_exec_control = 0;
1127         u32 _cpu_based_exec_control = 0;
1128         u32 _cpu_based_2nd_exec_control = 0;
1129         u32 _vmexit_control = 0;
1130         u32 _vmentry_control = 0;
1131
1132         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1133         opt = PIN_BASED_VIRTUAL_NMIS;
1134         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1135                                 &_pin_based_exec_control) < 0)
1136                 return -EIO;
1137
1138         min = CPU_BASED_HLT_EXITING |
1139 #ifdef CONFIG_X86_64
1140               CPU_BASED_CR8_LOAD_EXITING |
1141               CPU_BASED_CR8_STORE_EXITING |
1142 #endif
1143               CPU_BASED_CR3_LOAD_EXITING |
1144               CPU_BASED_CR3_STORE_EXITING |
1145               CPU_BASED_USE_IO_BITMAPS |
1146               CPU_BASED_MOV_DR_EXITING |
1147               CPU_BASED_USE_TSC_OFFSETING |
1148               CPU_BASED_INVLPG_EXITING;
1149         opt = CPU_BASED_TPR_SHADOW |
1150               CPU_BASED_USE_MSR_BITMAPS |
1151               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1152         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1153                                 &_cpu_based_exec_control) < 0)
1154                 return -EIO;
1155 #ifdef CONFIG_X86_64
1156         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1157                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1158                                            ~CPU_BASED_CR8_STORE_EXITING;
1159 #endif
1160         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1161                 min2 = 0;
1162                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1163                         SECONDARY_EXEC_WBINVD_EXITING |
1164                         SECONDARY_EXEC_ENABLE_VPID |
1165                         SECONDARY_EXEC_ENABLE_EPT;
1166                 if (adjust_vmx_controls(min2, opt2,
1167                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1168                                         &_cpu_based_2nd_exec_control) < 0)
1169                         return -EIO;
1170         }
1171 #ifndef CONFIG_X86_64
1172         if (!(_cpu_based_2nd_exec_control &
1173                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1174                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1175 #endif
1176         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1177                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1178                    enabled */
1179                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1180                          CPU_BASED_CR3_STORE_EXITING |
1181                          CPU_BASED_INVLPG_EXITING);
1182                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1183                                         &_cpu_based_exec_control) < 0)
1184                         return -EIO;
1185                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1186                       vmx_capability.ept, vmx_capability.vpid);
1187         }
1188
1189         min = 0;
1190 #ifdef CONFIG_X86_64
1191         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1192 #endif
1193         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1194         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1195                                 &_vmexit_control) < 0)
1196                 return -EIO;
1197
1198         min = 0;
1199         opt = VM_ENTRY_LOAD_IA32_PAT;
1200         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1201                                 &_vmentry_control) < 0)
1202                 return -EIO;
1203
1204         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1205
1206         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1207         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1208                 return -EIO;
1209
1210 #ifdef CONFIG_X86_64
1211         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1212         if (vmx_msr_high & (1u<<16))
1213                 return -EIO;
1214 #endif
1215
1216         /* Require Write-Back (WB) memory type for VMCS accesses. */
1217         if (((vmx_msr_high >> 18) & 15) != 6)
1218                 return -EIO;
1219
1220         vmcs_conf->size = vmx_msr_high & 0x1fff;
1221         vmcs_conf->order = get_order(vmcs_config.size);
1222         vmcs_conf->revision_id = vmx_msr_low;
1223
1224         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1225         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1226         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1227         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1228         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1229
1230         return 0;
1231 }
1232
1233 static struct vmcs *alloc_vmcs_cpu(int cpu)
1234 {
1235         int node = cpu_to_node(cpu);
1236         struct page *pages;
1237         struct vmcs *vmcs;
1238
1239         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1240         if (!pages)
1241                 return NULL;
1242         vmcs = page_address(pages);
1243         memset(vmcs, 0, vmcs_config.size);
1244         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1245         return vmcs;
1246 }
1247
1248 static struct vmcs *alloc_vmcs(void)
1249 {
1250         return alloc_vmcs_cpu(raw_smp_processor_id());
1251 }
1252
1253 static void free_vmcs(struct vmcs *vmcs)
1254 {
1255         free_pages((unsigned long)vmcs, vmcs_config.order);
1256 }
1257
1258 static void free_kvm_area(void)
1259 {
1260         int cpu;
1261
1262         for_each_online_cpu(cpu)
1263                 free_vmcs(per_cpu(vmxarea, cpu));
1264 }
1265
1266 static __init int alloc_kvm_area(void)
1267 {
1268         int cpu;
1269
1270         for_each_online_cpu(cpu) {
1271                 struct vmcs *vmcs;
1272
1273                 vmcs = alloc_vmcs_cpu(cpu);
1274                 if (!vmcs) {
1275                         free_kvm_area();
1276                         return -ENOMEM;
1277                 }
1278
1279                 per_cpu(vmxarea, cpu) = vmcs;
1280         }
1281         return 0;
1282 }
1283
1284 static __init int hardware_setup(void)
1285 {
1286         if (setup_vmcs_config(&vmcs_config) < 0)
1287                 return -EIO;
1288
1289         if (boot_cpu_has(X86_FEATURE_NX))
1290                 kvm_enable_efer_bits(EFER_NX);
1291
1292         return alloc_kvm_area();
1293 }
1294
1295 static __exit void hardware_unsetup(void)
1296 {
1297         free_kvm_area();
1298 }
1299
1300 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1301 {
1302         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1303
1304         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1305                 vmcs_write16(sf->selector, save->selector);
1306                 vmcs_writel(sf->base, save->base);
1307                 vmcs_write32(sf->limit, save->limit);
1308                 vmcs_write32(sf->ar_bytes, save->ar);
1309         } else {
1310                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1311                         << AR_DPL_SHIFT;
1312                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1313         }
1314 }
1315
1316 static void enter_pmode(struct kvm_vcpu *vcpu)
1317 {
1318         unsigned long flags;
1319         struct vcpu_vmx *vmx = to_vmx(vcpu);
1320
1321         vmx->emulation_required = 1;
1322         vcpu->arch.rmode.active = 0;
1323
1324         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1325         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1326         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1327
1328         flags = vmcs_readl(GUEST_RFLAGS);
1329         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1330         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1331         vmcs_writel(GUEST_RFLAGS, flags);
1332
1333         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1334                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1335
1336         update_exception_bitmap(vcpu);
1337
1338         if (emulate_invalid_guest_state)
1339                 return;
1340
1341         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1342         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1343         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1344         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1345
1346         vmcs_write16(GUEST_SS_SELECTOR, 0);
1347         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1348
1349         vmcs_write16(GUEST_CS_SELECTOR,
1350                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1351         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1352 }
1353
1354 static gva_t rmode_tss_base(struct kvm *kvm)
1355 {
1356         if (!kvm->arch.tss_addr) {
1357                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1358                                  kvm->memslots[0].npages - 3;
1359                 return base_gfn << PAGE_SHIFT;
1360         }
1361         return kvm->arch.tss_addr;
1362 }
1363
1364 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1365 {
1366         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1367
1368         save->selector = vmcs_read16(sf->selector);
1369         save->base = vmcs_readl(sf->base);
1370         save->limit = vmcs_read32(sf->limit);
1371         save->ar = vmcs_read32(sf->ar_bytes);
1372         vmcs_write16(sf->selector, save->base >> 4);
1373         vmcs_write32(sf->base, save->base & 0xfffff);
1374         vmcs_write32(sf->limit, 0xffff);
1375         vmcs_write32(sf->ar_bytes, 0xf3);
1376 }
1377
1378 static void enter_rmode(struct kvm_vcpu *vcpu)
1379 {
1380         unsigned long flags;
1381         struct vcpu_vmx *vmx = to_vmx(vcpu);
1382
1383         vmx->emulation_required = 1;
1384         vcpu->arch.rmode.active = 1;
1385
1386         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1387         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1388
1389         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1390         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1391
1392         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1393         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1394
1395         flags = vmcs_readl(GUEST_RFLAGS);
1396         vcpu->arch.rmode.save_iopl
1397                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1398
1399         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1400
1401         vmcs_writel(GUEST_RFLAGS, flags);
1402         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1403         update_exception_bitmap(vcpu);
1404
1405         if (emulate_invalid_guest_state)
1406                 goto continue_rmode;
1407
1408         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1409         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1410         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1411
1412         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1413         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1414         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1415                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1416         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1417
1418         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1419         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1420         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1421         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1422
1423 continue_rmode:
1424         kvm_mmu_reset_context(vcpu);
1425         init_rmode(vcpu->kvm);
1426 }
1427
1428 #ifdef CONFIG_X86_64
1429
1430 static void enter_lmode(struct kvm_vcpu *vcpu)
1431 {
1432         u32 guest_tr_ar;
1433
1434         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1435         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1436                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1437                        __func__);
1438                 vmcs_write32(GUEST_TR_AR_BYTES,
1439                              (guest_tr_ar & ~AR_TYPE_MASK)
1440                              | AR_TYPE_BUSY_64_TSS);
1441         }
1442
1443         vcpu->arch.shadow_efer |= EFER_LMA;
1444
1445         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1446         vmcs_write32(VM_ENTRY_CONTROLS,
1447                      vmcs_read32(VM_ENTRY_CONTROLS)
1448                      | VM_ENTRY_IA32E_MODE);
1449 }
1450
1451 static void exit_lmode(struct kvm_vcpu *vcpu)
1452 {
1453         vcpu->arch.shadow_efer &= ~EFER_LMA;
1454
1455         vmcs_write32(VM_ENTRY_CONTROLS,
1456                      vmcs_read32(VM_ENTRY_CONTROLS)
1457                      & ~VM_ENTRY_IA32E_MODE);
1458 }
1459
1460 #endif
1461
1462 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1463 {
1464         vpid_sync_vcpu_all(to_vmx(vcpu));
1465         if (vm_need_ept())
1466                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1467 }
1468
1469 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1470 {
1471         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1472         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1473 }
1474
1475 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1476 {
1477         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1478                 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1479                         printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1480                         return;
1481                 }
1482                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1483                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1484                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1485                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1486         }
1487 }
1488
1489 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1490
1491 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1492                                         unsigned long cr0,
1493                                         struct kvm_vcpu *vcpu)
1494 {
1495         if (!(cr0 & X86_CR0_PG)) {
1496                 /* From paging/starting to nonpaging */
1497                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1498                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1499                              (CPU_BASED_CR3_LOAD_EXITING |
1500                               CPU_BASED_CR3_STORE_EXITING));
1501                 vcpu->arch.cr0 = cr0;
1502                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1503                 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1504                 *hw_cr0 &= ~X86_CR0_WP;
1505         } else if (!is_paging(vcpu)) {
1506                 /* From nonpaging to paging */
1507                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1508                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1509                              ~(CPU_BASED_CR3_LOAD_EXITING |
1510                                CPU_BASED_CR3_STORE_EXITING));
1511                 vcpu->arch.cr0 = cr0;
1512                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1513                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1514                         *hw_cr0 &= ~X86_CR0_WP;
1515         }
1516 }
1517
1518 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1519                                         struct kvm_vcpu *vcpu)
1520 {
1521         if (!is_paging(vcpu)) {
1522                 *hw_cr4 &= ~X86_CR4_PAE;
1523                 *hw_cr4 |= X86_CR4_PSE;
1524         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1525                 *hw_cr4 &= ~X86_CR4_PAE;
1526 }
1527
1528 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1529 {
1530         unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1531                                 KVM_VM_CR0_ALWAYS_ON;
1532
1533         vmx_fpu_deactivate(vcpu);
1534
1535         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1536                 enter_pmode(vcpu);
1537
1538         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1539                 enter_rmode(vcpu);
1540
1541 #ifdef CONFIG_X86_64
1542         if (vcpu->arch.shadow_efer & EFER_LME) {
1543                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1544                         enter_lmode(vcpu);
1545                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1546                         exit_lmode(vcpu);
1547         }
1548 #endif
1549
1550         if (vm_need_ept())
1551                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1552
1553         vmcs_writel(CR0_READ_SHADOW, cr0);
1554         vmcs_writel(GUEST_CR0, hw_cr0);
1555         vcpu->arch.cr0 = cr0;
1556
1557         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1558                 vmx_fpu_activate(vcpu);
1559 }
1560
1561 static u64 construct_eptp(unsigned long root_hpa)
1562 {
1563         u64 eptp;
1564
1565         /* TODO write the value reading from MSR */
1566         eptp = VMX_EPT_DEFAULT_MT |
1567                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1568         eptp |= (root_hpa & PAGE_MASK);
1569
1570         return eptp;
1571 }
1572
1573 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1574 {
1575         unsigned long guest_cr3;
1576         u64 eptp;
1577
1578         guest_cr3 = cr3;
1579         if (vm_need_ept()) {
1580                 eptp = construct_eptp(cr3);
1581                 vmcs_write64(EPT_POINTER, eptp);
1582                 ept_sync_context(eptp);
1583                 ept_load_pdptrs(vcpu);
1584                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1585                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1586         }
1587
1588         vmx_flush_tlb(vcpu);
1589         vmcs_writel(GUEST_CR3, guest_cr3);
1590         if (vcpu->arch.cr0 & X86_CR0_PE)
1591                 vmx_fpu_deactivate(vcpu);
1592 }
1593
1594 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1595 {
1596         unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1597                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1598
1599         vcpu->arch.cr4 = cr4;
1600         if (vm_need_ept())
1601                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1602
1603         vmcs_writel(CR4_READ_SHADOW, cr4);
1604         vmcs_writel(GUEST_CR4, hw_cr4);
1605 }
1606
1607 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1608 {
1609         struct vcpu_vmx *vmx = to_vmx(vcpu);
1610         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1611
1612         vcpu->arch.shadow_efer = efer;
1613         if (!msr)
1614                 return;
1615         if (efer & EFER_LMA) {
1616                 vmcs_write32(VM_ENTRY_CONTROLS,
1617                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1618                                      VM_ENTRY_IA32E_MODE);
1619                 msr->data = efer;
1620
1621         } else {
1622                 vmcs_write32(VM_ENTRY_CONTROLS,
1623                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1624                                      ~VM_ENTRY_IA32E_MODE);
1625
1626                 msr->data = efer & ~EFER_LME;
1627         }
1628         setup_msrs(vmx);
1629 }
1630
1631 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1632 {
1633         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1634
1635         return vmcs_readl(sf->base);
1636 }
1637
1638 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1639                             struct kvm_segment *var, int seg)
1640 {
1641         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1642         u32 ar;
1643
1644         var->base = vmcs_readl(sf->base);
1645         var->limit = vmcs_read32(sf->limit);
1646         var->selector = vmcs_read16(sf->selector);
1647         ar = vmcs_read32(sf->ar_bytes);
1648         if (ar & AR_UNUSABLE_MASK)
1649                 ar = 0;
1650         var->type = ar & 15;
1651         var->s = (ar >> 4) & 1;
1652         var->dpl = (ar >> 5) & 3;
1653         var->present = (ar >> 7) & 1;
1654         var->avl = (ar >> 12) & 1;
1655         var->l = (ar >> 13) & 1;
1656         var->db = (ar >> 14) & 1;
1657         var->g = (ar >> 15) & 1;
1658         var->unusable = (ar >> 16) & 1;
1659 }
1660
1661 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1662 {
1663         struct kvm_segment kvm_seg;
1664
1665         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1666                 return 0;
1667
1668         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1669                 return 3;
1670
1671         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1672         return kvm_seg.selector & 3;
1673 }
1674
1675 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1676 {
1677         u32 ar;
1678
1679         if (var->unusable)
1680                 ar = 1 << 16;
1681         else {
1682                 ar = var->type & 15;
1683                 ar |= (var->s & 1) << 4;
1684                 ar |= (var->dpl & 3) << 5;
1685                 ar |= (var->present & 1) << 7;
1686                 ar |= (var->avl & 1) << 12;
1687                 ar |= (var->l & 1) << 13;
1688                 ar |= (var->db & 1) << 14;
1689                 ar |= (var->g & 1) << 15;
1690         }
1691         if (ar == 0) /* a 0 value means unusable */
1692                 ar = AR_UNUSABLE_MASK;
1693
1694         return ar;
1695 }
1696
1697 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1698                             struct kvm_segment *var, int seg)
1699 {
1700         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1701         u32 ar;
1702
1703         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1704                 vcpu->arch.rmode.tr.selector = var->selector;
1705                 vcpu->arch.rmode.tr.base = var->base;
1706                 vcpu->arch.rmode.tr.limit = var->limit;
1707                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1708                 return;
1709         }
1710         vmcs_writel(sf->base, var->base);
1711         vmcs_write32(sf->limit, var->limit);
1712         vmcs_write16(sf->selector, var->selector);
1713         if (vcpu->arch.rmode.active && var->s) {
1714                 /*
1715                  * Hack real-mode segments into vm86 compatibility.
1716                  */
1717                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1718                         vmcs_writel(sf->base, 0xf0000);
1719                 ar = 0xf3;
1720         } else
1721                 ar = vmx_segment_access_rights(var);
1722         vmcs_write32(sf->ar_bytes, ar);
1723 }
1724
1725 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1726 {
1727         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1728
1729         *db = (ar >> 14) & 1;
1730         *l = (ar >> 13) & 1;
1731 }
1732
1733 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1734 {
1735         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1736         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1737 }
1738
1739 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1740 {
1741         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1742         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1743 }
1744
1745 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1746 {
1747         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1748         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1749 }
1750
1751 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1752 {
1753         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1754         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1755 }
1756
1757 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1758 {
1759         struct kvm_segment var;
1760         u32 ar;
1761
1762         vmx_get_segment(vcpu, &var, seg);
1763         ar = vmx_segment_access_rights(&var);
1764
1765         if (var.base != (var.selector << 4))
1766                 return false;
1767         if (var.limit != 0xffff)
1768                 return false;
1769         if (ar != 0xf3)
1770                 return false;
1771
1772         return true;
1773 }
1774
1775 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1776 {
1777         struct kvm_segment cs;
1778         unsigned int cs_rpl;
1779
1780         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1781         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1782
1783         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1784                 return false;
1785         if (!cs.s)
1786                 return false;
1787         if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) {
1788                 if (cs.dpl > cs_rpl)
1789                         return false;
1790         } else if (cs.type & AR_TYPE_CODE_MASK) {
1791                 if (cs.dpl != cs_rpl)
1792                         return false;
1793         }
1794         if (!cs.present)
1795                 return false;
1796
1797         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1798         return true;
1799 }
1800
1801 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1802 {
1803         struct kvm_segment ss;
1804         unsigned int ss_rpl;
1805
1806         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1807         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1808
1809         if ((ss.type != 3) || (ss.type != 7))
1810                 return false;
1811         if (!ss.s)
1812                 return false;
1813         if (ss.dpl != ss_rpl) /* DPL != RPL */
1814                 return false;
1815         if (!ss.present)
1816                 return false;
1817
1818         return true;
1819 }
1820
1821 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1822 {
1823         struct kvm_segment var;
1824         unsigned int rpl;
1825
1826         vmx_get_segment(vcpu, &var, seg);
1827         rpl = var.selector & SELECTOR_RPL_MASK;
1828
1829         if (!var.s)
1830                 return false;
1831         if (!var.present)
1832                 return false;
1833         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1834                 if (var.dpl < rpl) /* DPL < RPL */
1835                         return false;
1836         }
1837
1838         /* TODO: Add other members to kvm_segment_field to allow checking for other access
1839          * rights flags
1840          */
1841         return true;
1842 }
1843
1844 static bool tr_valid(struct kvm_vcpu *vcpu)
1845 {
1846         struct kvm_segment tr;
1847
1848         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1849
1850         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
1851                 return false;
1852         if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */
1853                 return false;
1854         if (!tr.present)
1855                 return false;
1856
1857         return true;
1858 }
1859
1860 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1861 {
1862         struct kvm_segment ldtr;
1863
1864         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1865
1866         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
1867                 return false;
1868         if (ldtr.type != 2)
1869                 return false;
1870         if (!ldtr.present)
1871                 return false;
1872
1873         return true;
1874 }
1875
1876 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1877 {
1878         struct kvm_segment cs, ss;
1879
1880         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1881         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1882
1883         return ((cs.selector & SELECTOR_RPL_MASK) ==
1884                  (ss.selector & SELECTOR_RPL_MASK));
1885 }
1886
1887 /*
1888  * Check if guest state is valid. Returns true if valid, false if
1889  * not.
1890  * We assume that registers are always usable
1891  */
1892 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1893 {
1894         /* real mode guest state checks */
1895         if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1896                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1897                         return false;
1898                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1899                         return false;
1900                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1901                         return false;
1902                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1903                         return false;
1904                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1905                         return false;
1906                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1907                         return false;
1908         } else {
1909         /* protected mode guest state checks */
1910                 if (!cs_ss_rpl_check(vcpu))
1911                         return false;
1912                 if (!code_segment_valid(vcpu))
1913                         return false;
1914                 if (!stack_segment_valid(vcpu))
1915                         return false;
1916                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1917                         return false;
1918                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1919                         return false;
1920                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1921                         return false;
1922                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1923                         return false;
1924                 if (!tr_valid(vcpu))
1925                         return false;
1926                 if (!ldtr_valid(vcpu))
1927                         return false;
1928         }
1929         /* TODO:
1930          * - Add checks on RIP
1931          * - Add checks on RFLAGS
1932          */
1933
1934         return true;
1935 }
1936
1937 static int init_rmode_tss(struct kvm *kvm)
1938 {
1939         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1940         u16 data = 0;
1941         int ret = 0;
1942         int r;
1943
1944         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1945         if (r < 0)
1946                 goto out;
1947         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1948         r = kvm_write_guest_page(kvm, fn++, &data,
1949                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
1950         if (r < 0)
1951                 goto out;
1952         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1953         if (r < 0)
1954                 goto out;
1955         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1956         if (r < 0)
1957                 goto out;
1958         data = ~0;
1959         r = kvm_write_guest_page(kvm, fn, &data,
1960                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1961                                  sizeof(u8));
1962         if (r < 0)
1963                 goto out;
1964
1965         ret = 1;
1966 out:
1967         return ret;
1968 }
1969
1970 static int init_rmode_identity_map(struct kvm *kvm)
1971 {
1972         int i, r, ret;
1973         pfn_t identity_map_pfn;
1974         u32 tmp;
1975
1976         if (!vm_need_ept())
1977                 return 1;
1978         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1979                 printk(KERN_ERR "EPT: identity-mapping pagetable "
1980                         "haven't been allocated!\n");
1981                 return 0;
1982         }
1983         if (likely(kvm->arch.ept_identity_pagetable_done))
1984                 return 1;
1985         ret = 0;
1986         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1987         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1988         if (r < 0)
1989                 goto out;
1990         /* Set up identity-mapping pagetable for EPT in real mode */
1991         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1992                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1993                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1994                 r = kvm_write_guest_page(kvm, identity_map_pfn,
1995                                 &tmp, i * sizeof(tmp), sizeof(tmp));
1996                 if (r < 0)
1997                         goto out;
1998         }
1999         kvm->arch.ept_identity_pagetable_done = true;
2000         ret = 1;
2001 out:
2002         return ret;
2003 }
2004
2005 static void seg_setup(int seg)
2006 {
2007         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2008
2009         vmcs_write16(sf->selector, 0);
2010         vmcs_writel(sf->base, 0);
2011         vmcs_write32(sf->limit, 0xffff);
2012         vmcs_write32(sf->ar_bytes, 0xf3);
2013 }
2014
2015 static int alloc_apic_access_page(struct kvm *kvm)
2016 {
2017         struct kvm_userspace_memory_region kvm_userspace_mem;
2018         int r = 0;
2019
2020         down_write(&kvm->slots_lock);
2021         if (kvm->arch.apic_access_page)
2022                 goto out;
2023         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2024         kvm_userspace_mem.flags = 0;
2025         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2026         kvm_userspace_mem.memory_size = PAGE_SIZE;
2027         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2028         if (r)
2029                 goto out;
2030
2031         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2032 out:
2033         up_write(&kvm->slots_lock);
2034         return r;
2035 }
2036
2037 static int alloc_identity_pagetable(struct kvm *kvm)
2038 {
2039         struct kvm_userspace_memory_region kvm_userspace_mem;
2040         int r = 0;
2041
2042         down_write(&kvm->slots_lock);
2043         if (kvm->arch.ept_identity_pagetable)
2044                 goto out;
2045         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2046         kvm_userspace_mem.flags = 0;
2047         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2048         kvm_userspace_mem.memory_size = PAGE_SIZE;
2049         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2050         if (r)
2051                 goto out;
2052
2053         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2054                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2055 out:
2056         up_write(&kvm->slots_lock);
2057         return r;
2058 }
2059
2060 static void allocate_vpid(struct vcpu_vmx *vmx)
2061 {
2062         int vpid;
2063
2064         vmx->vpid = 0;
2065         if (!enable_vpid || !cpu_has_vmx_vpid())
2066                 return;
2067         spin_lock(&vmx_vpid_lock);
2068         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2069         if (vpid < VMX_NR_VPIDS) {
2070                 vmx->vpid = vpid;
2071                 __set_bit(vpid, vmx_vpid_bitmap);
2072         }
2073         spin_unlock(&vmx_vpid_lock);
2074 }
2075
2076 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
2077 {
2078         void *va;
2079
2080         if (!cpu_has_vmx_msr_bitmap())
2081                 return;
2082
2083         /*
2084          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2085          * have the write-low and read-high bitmap offsets the wrong way round.
2086          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2087          */
2088         va = kmap(msr_bitmap);
2089         if (msr <= 0x1fff) {
2090                 __clear_bit(msr, va + 0x000); /* read-low */
2091                 __clear_bit(msr, va + 0x800); /* write-low */
2092         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2093                 msr &= 0x1fff;
2094                 __clear_bit(msr, va + 0x400); /* read-high */
2095                 __clear_bit(msr, va + 0xc00); /* write-high */
2096         }
2097         kunmap(msr_bitmap);
2098 }
2099
2100 /*
2101  * Sets up the vmcs for emulated real mode.
2102  */
2103 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2104 {
2105         u32 host_sysenter_cs, msr_low, msr_high;
2106         u32 junk;
2107         u64 host_pat;
2108         unsigned long a;
2109         struct descriptor_table dt;
2110         int i;
2111         unsigned long kvm_vmx_return;
2112         u32 exec_control;
2113
2114         /* I/O */
2115         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2116         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
2117
2118         if (cpu_has_vmx_msr_bitmap())
2119                 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2120
2121         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2122
2123         /* Control */
2124         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2125                 vmcs_config.pin_based_exec_ctrl);
2126
2127         exec_control = vmcs_config.cpu_based_exec_ctrl;
2128         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2129                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2130 #ifdef CONFIG_X86_64
2131                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2132                                 CPU_BASED_CR8_LOAD_EXITING;
2133 #endif
2134         }
2135         if (!vm_need_ept())
2136                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2137                                 CPU_BASED_CR3_LOAD_EXITING  |
2138                                 CPU_BASED_INVLPG_EXITING;
2139         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2140
2141         if (cpu_has_secondary_exec_ctrls()) {
2142                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2143                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2144                         exec_control &=
2145                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2146                 if (vmx->vpid == 0)
2147                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2148                 if (!vm_need_ept())
2149                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2150                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2151         }
2152
2153         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2154         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2155         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2156
2157         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2158         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2159         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2160
2161         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2162         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2163         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2164         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2165         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2166         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2167 #ifdef CONFIG_X86_64
2168         rdmsrl(MSR_FS_BASE, a);
2169         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2170         rdmsrl(MSR_GS_BASE, a);
2171         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2172 #else
2173         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2174         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2175 #endif
2176
2177         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2178
2179         kvm_get_idt(&dt);
2180         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
2181
2182         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2183         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2184         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2185         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2186         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2187
2188         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2189         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2190         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2191         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2192         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2193         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2194
2195         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2196                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2197                 host_pat = msr_low | ((u64) msr_high << 32);
2198                 vmcs_write64(HOST_IA32_PAT, host_pat);
2199         }
2200         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2201                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2202                 host_pat = msr_low | ((u64) msr_high << 32);
2203                 /* Write the default value follow host pat */
2204                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2205                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2206                 vmx->vcpu.arch.pat = host_pat;
2207         }
2208
2209         for (i = 0; i < NR_VMX_MSR; ++i) {
2210                 u32 index = vmx_msr_index[i];
2211                 u32 data_low, data_high;
2212                 u64 data;
2213                 int j = vmx->nmsrs;
2214
2215                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2216                         continue;
2217                 if (wrmsr_safe(index, data_low, data_high) < 0)
2218                         continue;
2219                 data = data_low | ((u64)data_high << 32);
2220                 vmx->host_msrs[j].index = index;
2221                 vmx->host_msrs[j].reserved = 0;
2222                 vmx->host_msrs[j].data = data;
2223                 vmx->guest_msrs[j] = vmx->host_msrs[j];
2224                 ++vmx->nmsrs;
2225         }
2226
2227         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2228
2229         /* 22.2.1, 20.8.1 */
2230         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2231
2232         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2233         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2234
2235
2236         return 0;
2237 }
2238
2239 static int init_rmode(struct kvm *kvm)
2240 {
2241         if (!init_rmode_tss(kvm))
2242                 return 0;
2243         if (!init_rmode_identity_map(kvm))
2244                 return 0;
2245         return 1;
2246 }
2247
2248 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2249 {
2250         struct vcpu_vmx *vmx = to_vmx(vcpu);
2251         u64 msr;
2252         int ret;
2253
2254         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2255         down_read(&vcpu->kvm->slots_lock);
2256         if (!init_rmode(vmx->vcpu.kvm)) {
2257                 ret = -ENOMEM;
2258                 goto out;
2259         }
2260
2261         vmx->vcpu.arch.rmode.active = 0;
2262
2263         vmx->soft_vnmi_blocked = 0;
2264
2265         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2266         kvm_set_cr8(&vmx->vcpu, 0);
2267         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2268         if (vmx->vcpu.vcpu_id == 0)
2269                 msr |= MSR_IA32_APICBASE_BSP;
2270         kvm_set_apic_base(&vmx->vcpu, msr);
2271
2272         fx_init(&vmx->vcpu);
2273
2274         seg_setup(VCPU_SREG_CS);
2275         /*
2276          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2277          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2278          */
2279         if (vmx->vcpu.vcpu_id == 0) {
2280                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2281                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2282         } else {
2283                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2284                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2285         }
2286
2287         seg_setup(VCPU_SREG_DS);
2288         seg_setup(VCPU_SREG_ES);
2289         seg_setup(VCPU_SREG_FS);
2290         seg_setup(VCPU_SREG_GS);
2291         seg_setup(VCPU_SREG_SS);
2292
2293         vmcs_write16(GUEST_TR_SELECTOR, 0);
2294         vmcs_writel(GUEST_TR_BASE, 0);
2295         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2296         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2297
2298         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2299         vmcs_writel(GUEST_LDTR_BASE, 0);
2300         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2301         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2302
2303         vmcs_write32(GUEST_SYSENTER_CS, 0);
2304         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2305         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2306
2307         vmcs_writel(GUEST_RFLAGS, 0x02);
2308         if (vmx->vcpu.vcpu_id == 0)
2309                 kvm_rip_write(vcpu, 0xfff0);
2310         else
2311                 kvm_rip_write(vcpu, 0);
2312         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2313
2314         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2315         vmcs_writel(GUEST_DR7, 0x400);
2316
2317         vmcs_writel(GUEST_GDTR_BASE, 0);
2318         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2319
2320         vmcs_writel(GUEST_IDTR_BASE, 0);
2321         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2322
2323         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2324         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2325         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2326
2327         guest_write_tsc(0);
2328
2329         /* Special registers */
2330         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2331
2332         setup_msrs(vmx);
2333
2334         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2335
2336         if (cpu_has_vmx_tpr_shadow()) {
2337                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2338                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2339                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2340                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2341                 vmcs_write32(TPR_THRESHOLD, 0);
2342         }
2343
2344         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2345                 vmcs_write64(APIC_ACCESS_ADDR,
2346                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2347
2348         if (vmx->vpid != 0)
2349                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2350
2351         vmx->vcpu.arch.cr0 = 0x60000010;
2352         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2353         vmx_set_cr4(&vmx->vcpu, 0);
2354         vmx_set_efer(&vmx->vcpu, 0);
2355         vmx_fpu_activate(&vmx->vcpu);
2356         update_exception_bitmap(&vmx->vcpu);
2357
2358         vpid_sync_vcpu_all(vmx);
2359
2360         ret = 0;
2361
2362         /* HACK: Don't enable emulation on guest boot/reset */
2363         vmx->emulation_required = 0;
2364
2365 out:
2366         up_read(&vcpu->kvm->slots_lock);
2367         return ret;
2368 }
2369
2370 static void enable_irq_window(struct kvm_vcpu *vcpu)
2371 {
2372         u32 cpu_based_vm_exec_control;
2373
2374         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2375         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2376         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2377 }
2378
2379 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2380 {
2381         u32 cpu_based_vm_exec_control;
2382
2383         if (!cpu_has_virtual_nmis()) {
2384                 enable_irq_window(vcpu);
2385                 return;
2386         }
2387
2388         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2389         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2390         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2391 }
2392
2393 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2394 {
2395         struct vcpu_vmx *vmx = to_vmx(vcpu);
2396
2397         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2398
2399         ++vcpu->stat.irq_injections;
2400         if (vcpu->arch.rmode.active) {
2401                 vmx->rmode.irq.pending = true;
2402                 vmx->rmode.irq.vector = irq;
2403                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2404                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2405                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2406                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2407                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2408                 return;
2409         }
2410         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2411                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2412 }
2413
2414 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2415 {
2416         struct vcpu_vmx *vmx = to_vmx(vcpu);
2417
2418         if (!cpu_has_virtual_nmis()) {
2419                 /*
2420                  * Tracking the NMI-blocked state in software is built upon
2421                  * finding the next open IRQ window. This, in turn, depends on
2422                  * well-behaving guests: They have to keep IRQs disabled at
2423                  * least as long as the NMI handler runs. Otherwise we may
2424                  * cause NMI nesting, maybe breaking the guest. But as this is
2425                  * highly unlikely, we can live with the residual risk.
2426                  */
2427                 vmx->soft_vnmi_blocked = 1;
2428                 vmx->vnmi_blocked_time = 0;
2429         }
2430
2431         ++vcpu->stat.nmi_injections;
2432         if (vcpu->arch.rmode.active) {
2433                 vmx->rmode.irq.pending = true;
2434                 vmx->rmode.irq.vector = NMI_VECTOR;
2435                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2436                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2437                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2438                              INTR_INFO_VALID_MASK);
2439                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2440                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2441                 return;
2442         }
2443         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2444                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2445 }
2446
2447 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2448 {
2449         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2450
2451         vcpu->arch.nmi_window_open =
2452                 !(guest_intr & (GUEST_INTR_STATE_STI |
2453                                 GUEST_INTR_STATE_MOV_SS |
2454                                 GUEST_INTR_STATE_NMI));
2455         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2456                 vcpu->arch.nmi_window_open = 0;
2457
2458         vcpu->arch.interrupt_window_open =
2459                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2460                  !(guest_intr & (GUEST_INTR_STATE_STI |
2461                                  GUEST_INTR_STATE_MOV_SS)));
2462 }
2463
2464 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2465 {
2466         int word_index = __ffs(vcpu->arch.irq_summary);
2467         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2468         int irq = word_index * BITS_PER_LONG + bit_index;
2469
2470         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2471         if (!vcpu->arch.irq_pending[word_index])
2472                 clear_bit(word_index, &vcpu->arch.irq_summary);
2473         kvm_queue_interrupt(vcpu, irq);
2474 }
2475
2476 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2477                                        struct kvm_run *kvm_run)
2478 {
2479         vmx_update_window_states(vcpu);
2480
2481         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2482                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2483                                 GUEST_INTR_STATE_STI |
2484                                 GUEST_INTR_STATE_MOV_SS);
2485
2486         if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2487                 if (vcpu->arch.interrupt.pending) {
2488                         enable_nmi_window(vcpu);
2489                 } else if (vcpu->arch.nmi_window_open) {
2490                         vcpu->arch.nmi_pending = false;
2491                         vcpu->arch.nmi_injected = true;
2492                 } else {
2493                         enable_nmi_window(vcpu);
2494                         return;
2495                 }
2496         }
2497         if (vcpu->arch.nmi_injected) {
2498                 vmx_inject_nmi(vcpu);
2499                 if (vcpu->arch.nmi_pending)
2500                         enable_nmi_window(vcpu);
2501                 else if (vcpu->arch.irq_summary
2502                          || kvm_run->request_interrupt_window)
2503                         enable_irq_window(vcpu);
2504                 return;
2505         }
2506
2507         if (vcpu->arch.interrupt_window_open) {
2508                 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2509                         kvm_do_inject_irq(vcpu);
2510
2511                 if (vcpu->arch.interrupt.pending)
2512                         vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2513         }
2514         if (!vcpu->arch.interrupt_window_open &&
2515             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2516                 enable_irq_window(vcpu);
2517 }
2518
2519 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2520 {
2521         int ret;
2522         struct kvm_userspace_memory_region tss_mem = {
2523                 .slot = TSS_PRIVATE_MEMSLOT,
2524                 .guest_phys_addr = addr,
2525                 .memory_size = PAGE_SIZE * 3,
2526                 .flags = 0,
2527         };
2528
2529         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2530         if (ret)
2531                 return ret;
2532         kvm->arch.tss_addr = addr;
2533         return 0;
2534 }
2535
2536 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2537                                   int vec, u32 err_code)
2538 {
2539         /*
2540          * Instruction with address size override prefix opcode 0x67
2541          * Cause the #SS fault with 0 error code in VM86 mode.
2542          */
2543         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2544                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2545                         return 1;
2546         /*
2547          * Forward all other exceptions that are valid in real mode.
2548          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2549          *        the required debugging infrastructure rework.
2550          */
2551         switch (vec) {
2552         case DB_VECTOR:
2553                 if (vcpu->guest_debug &
2554                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2555                         return 0;
2556                 kvm_queue_exception(vcpu, vec);
2557                 return 1;
2558         case BP_VECTOR:
2559                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2560                         return 0;
2561                 /* fall through */
2562         case DE_VECTOR:
2563         case OF_VECTOR:
2564         case BR_VECTOR:
2565         case UD_VECTOR:
2566         case DF_VECTOR:
2567         case SS_VECTOR:
2568         case GP_VECTOR:
2569         case MF_VECTOR:
2570                 kvm_queue_exception(vcpu, vec);
2571                 return 1;
2572         }
2573         return 0;
2574 }
2575
2576 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2577 {
2578         struct vcpu_vmx *vmx = to_vmx(vcpu);
2579         u32 intr_info, ex_no, error_code;
2580         unsigned long cr2, rip;
2581         u32 vect_info;
2582         enum emulation_result er;
2583
2584         vect_info = vmx->idt_vectoring_info;
2585         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2586
2587         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2588                                                 !is_page_fault(intr_info))
2589                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2590                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2591
2592         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2593                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2594                 set_bit(irq, vcpu->arch.irq_pending);
2595                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2596         }
2597
2598         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2599                 return 1;  /* already handled by vmx_vcpu_run() */
2600
2601         if (is_no_device(intr_info)) {
2602                 vmx_fpu_activate(vcpu);
2603                 return 1;
2604         }
2605
2606         if (is_invalid_opcode(intr_info)) {
2607                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2608                 if (er != EMULATE_DONE)
2609                         kvm_queue_exception(vcpu, UD_VECTOR);
2610                 return 1;
2611         }
2612
2613         error_code = 0;
2614         rip = kvm_rip_read(vcpu);
2615         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2616                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2617         if (is_page_fault(intr_info)) {
2618                 /* EPT won't cause page fault directly */
2619                 if (vm_need_ept())
2620                         BUG();
2621                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2622                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2623                             (u32)((u64)cr2 >> 32), handler);
2624                 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2625                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2626                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2627         }
2628
2629         if (vcpu->arch.rmode.active &&
2630             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2631                                                                 error_code)) {
2632                 if (vcpu->arch.halt_request) {
2633                         vcpu->arch.halt_request = 0;
2634                         return kvm_emulate_halt(vcpu);
2635                 }
2636                 return 1;
2637         }
2638
2639         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2640         if (ex_no == DB_VECTOR || ex_no == BP_VECTOR) {
2641                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2642                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2643                 kvm_run->debug.arch.exception = ex_no;
2644         } else {
2645                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2646                 kvm_run->ex.exception = ex_no;
2647                 kvm_run->ex.error_code = error_code;
2648         }
2649         return 0;
2650 }
2651
2652 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2653                                      struct kvm_run *kvm_run)
2654 {
2655         ++vcpu->stat.irq_exits;
2656         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2657         return 1;
2658 }
2659
2660 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2661 {
2662         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2663         return 0;
2664 }
2665
2666 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2667 {
2668         unsigned long exit_qualification;
2669         int size, down, in, string, rep;
2670         unsigned port;
2671
2672         ++vcpu->stat.io_exits;
2673         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2674         string = (exit_qualification & 16) != 0;
2675
2676         if (string) {
2677                 if (emulate_instruction(vcpu,
2678                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2679                         return 0;
2680                 return 1;
2681         }
2682
2683         size = (exit_qualification & 7) + 1;
2684         in = (exit_qualification & 8) != 0;
2685         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2686         rep = (exit_qualification & 32) != 0;
2687         port = exit_qualification >> 16;
2688
2689         skip_emulated_instruction(vcpu);
2690         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2691 }
2692
2693 static void
2694 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2695 {
2696         /*
2697          * Patch in the VMCALL instruction:
2698          */
2699         hypercall[0] = 0x0f;
2700         hypercall[1] = 0x01;
2701         hypercall[2] = 0xc1;
2702 }
2703
2704 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2705 {
2706         unsigned long exit_qualification;
2707         int cr;
2708         int reg;
2709
2710         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2711         cr = exit_qualification & 15;
2712         reg = (exit_qualification >> 8) & 15;
2713         switch ((exit_qualification >> 4) & 3) {
2714         case 0: /* mov to cr */
2715                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2716                             (u32)kvm_register_read(vcpu, reg),
2717                             (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2718                             handler);
2719                 switch (cr) {
2720                 case 0:
2721                         kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2722                         skip_emulated_instruction(vcpu);
2723                         return 1;
2724                 case 3:
2725                         kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2726                         skip_emulated_instruction(vcpu);
2727                         return 1;
2728                 case 4:
2729                         kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2730                         skip_emulated_instruction(vcpu);
2731                         return 1;
2732                 case 8:
2733                         kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2734                         skip_emulated_instruction(vcpu);
2735                         if (irqchip_in_kernel(vcpu->kvm))
2736                                 return 1;
2737                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2738                         return 0;
2739                 };
2740                 break;
2741         case 2: /* clts */
2742                 vmx_fpu_deactivate(vcpu);
2743                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2744                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2745                 vmx_fpu_activate(vcpu);
2746                 KVMTRACE_0D(CLTS, vcpu, handler);
2747                 skip_emulated_instruction(vcpu);
2748                 return 1;
2749         case 1: /*mov from cr*/
2750                 switch (cr) {
2751                 case 3:
2752                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2753                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2754                                     (u32)kvm_register_read(vcpu, reg),
2755                                     (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2756                                     handler);
2757                         skip_emulated_instruction(vcpu);
2758                         return 1;
2759                 case 8:
2760                         kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2761                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2762                                     (u32)kvm_register_read(vcpu, reg), handler);
2763                         skip_emulated_instruction(vcpu);
2764                         return 1;
2765                 }
2766                 break;
2767         case 3: /* lmsw */
2768                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2769
2770                 skip_emulated_instruction(vcpu);
2771                 return 1;
2772         default:
2773                 break;
2774         }
2775         kvm_run->exit_reason = 0;
2776         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2777                (int)(exit_qualification >> 4) & 3, cr);
2778         return 0;
2779 }
2780
2781 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2782 {
2783         unsigned long exit_qualification;
2784         unsigned long val;
2785         int dr, reg;
2786
2787         /*
2788          * FIXME: this code assumes the host is debugging the guest.
2789          *        need to deal with guest debugging itself too.
2790          */
2791         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2792         dr = exit_qualification & 7;
2793         reg = (exit_qualification >> 8) & 15;
2794         if (exit_qualification & 16) {
2795                 /* mov from dr */
2796                 switch (dr) {
2797                 case 6:
2798                         val = 0xffff0ff0;
2799                         break;
2800                 case 7:
2801                         val = 0x400;
2802                         break;
2803                 default:
2804                         val = 0;
2805                 }
2806                 kvm_register_write(vcpu, reg, val);
2807                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2808         } else {
2809                 /* mov to dr */
2810         }
2811         skip_emulated_instruction(vcpu);
2812         return 1;
2813 }
2814
2815 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2816 {
2817         kvm_emulate_cpuid(vcpu);
2818         return 1;
2819 }
2820
2821 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2822 {
2823         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2824         u64 data;
2825
2826         if (vmx_get_msr(vcpu, ecx, &data)) {
2827                 kvm_inject_gp(vcpu, 0);
2828                 return 1;
2829         }
2830
2831         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2832                     handler);
2833
2834         /* FIXME: handling of bits 32:63 of rax, rdx */
2835         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2836         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2837         skip_emulated_instruction(vcpu);
2838         return 1;
2839 }
2840
2841 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2842 {
2843         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2844         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2845                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2846
2847         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2848                     handler);
2849
2850         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2851                 kvm_inject_gp(vcpu, 0);
2852                 return 1;
2853         }
2854
2855         skip_emulated_instruction(vcpu);
2856         return 1;
2857 }
2858
2859 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2860                                       struct kvm_run *kvm_run)
2861 {
2862         return 1;
2863 }
2864
2865 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2866                                    struct kvm_run *kvm_run)
2867 {
2868         u32 cpu_based_vm_exec_control;
2869
2870         /* clear pending irq */
2871         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2872         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2873         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2874
2875         KVMTRACE_0D(PEND_INTR, vcpu, handler);
2876         ++vcpu->stat.irq_window_exits;
2877
2878         /*
2879          * If the user space waits to inject interrupts, exit as soon as
2880          * possible
2881          */
2882         if (kvm_run->request_interrupt_window &&
2883             !vcpu->arch.irq_summary) {
2884                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2885                 return 0;
2886         }
2887         return 1;
2888 }
2889
2890 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2891 {
2892         skip_emulated_instruction(vcpu);
2893         return kvm_emulate_halt(vcpu);
2894 }
2895
2896 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2897 {
2898         skip_emulated_instruction(vcpu);
2899         kvm_emulate_hypercall(vcpu);
2900         return 1;
2901 }
2902
2903 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2904 {
2905         u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2906
2907         kvm_mmu_invlpg(vcpu, exit_qualification);
2908         skip_emulated_instruction(vcpu);
2909         return 1;
2910 }
2911
2912 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2913 {
2914         skip_emulated_instruction(vcpu);
2915         /* TODO: Add support for VT-d/pass-through device */
2916         return 1;
2917 }
2918
2919 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2920 {
2921         u64 exit_qualification;
2922         enum emulation_result er;
2923         unsigned long offset;
2924
2925         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2926         offset = exit_qualification & 0xffful;
2927
2928         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2929
2930         if (er !=  EMULATE_DONE) {
2931                 printk(KERN_ERR
2932                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2933                        offset);
2934                 return -ENOTSUPP;
2935         }
2936         return 1;
2937 }
2938
2939 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2940 {
2941         struct vcpu_vmx *vmx = to_vmx(vcpu);
2942         unsigned long exit_qualification;
2943         u16 tss_selector;
2944         int reason;
2945
2946         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2947
2948         reason = (u32)exit_qualification >> 30;
2949         if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
2950             (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
2951             (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
2952             == INTR_TYPE_NMI_INTR) {
2953                 vcpu->arch.nmi_injected = false;
2954                 if (cpu_has_virtual_nmis())
2955                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2956                                       GUEST_INTR_STATE_NMI);
2957         }
2958         tss_selector = exit_qualification;
2959
2960         return kvm_task_switch(vcpu, tss_selector, reason);
2961 }
2962
2963 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2964 {
2965         u64 exit_qualification;
2966         enum emulation_result er;
2967         gpa_t gpa;
2968         unsigned long hva;
2969         int gla_validity;
2970         int r;
2971
2972         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2973
2974         if (exit_qualification & (1 << 6)) {
2975                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2976                 return -ENOTSUPP;
2977         }
2978
2979         gla_validity = (exit_qualification >> 7) & 0x3;
2980         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2981                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2982                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2983                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2984                         (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2985                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2986                         (long unsigned int)exit_qualification);
2987                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2988                 kvm_run->hw.hardware_exit_reason = 0;
2989                 return -ENOTSUPP;
2990         }
2991
2992         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2993         hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2994         if (!kvm_is_error_hva(hva)) {
2995                 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2996                 if (r < 0) {
2997                         printk(KERN_ERR "EPT: Not enough memory!\n");
2998                         return -ENOMEM;
2999                 }
3000                 return 1;
3001         } else {
3002                 /* must be MMIO */
3003                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3004
3005                 if (er == EMULATE_FAIL) {
3006                         printk(KERN_ERR
3007                          "EPT: Fail to handle EPT violation vmexit!er is %d\n",
3008                          er);
3009                         printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3010                          (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3011                          (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3012                         printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3013                                 (long unsigned int)exit_qualification);
3014                         return -ENOTSUPP;
3015                 } else if (er == EMULATE_DO_MMIO)
3016                         return 0;
3017         }
3018         return 1;
3019 }
3020
3021 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3022 {
3023         u32 cpu_based_vm_exec_control;
3024
3025         /* clear pending NMI */
3026         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3027         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3028         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3029         ++vcpu->stat.nmi_window_exits;
3030
3031         return 1;
3032 }
3033
3034 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3035                                 struct kvm_run *kvm_run)
3036 {
3037         struct vcpu_vmx *vmx = to_vmx(vcpu);
3038         int err;
3039
3040         preempt_enable();
3041         local_irq_enable();
3042
3043         while (!guest_state_valid(vcpu)) {
3044                 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3045
3046                 if (err == EMULATE_DO_MMIO)
3047                         break;
3048
3049                 if (err != EMULATE_DONE) {
3050                         kvm_report_emulation_failure(vcpu, "emulation failure");
3051                         return;
3052                 }
3053
3054                 if (signal_pending(current))
3055                         break;
3056                 if (need_resched())
3057                         schedule();
3058         }
3059
3060         local_irq_disable();
3061         preempt_disable();
3062
3063         /* Guest state should be valid now except if we need to
3064          * emulate an MMIO */
3065         if (guest_state_valid(vcpu))
3066                 vmx->emulation_required = 0;
3067 }
3068
3069 /*
3070  * The exit handlers return 1 if the exit was handled fully and guest execution
3071  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3072  * to be done to userspace and return 0.
3073  */
3074 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3075                                       struct kvm_run *kvm_run) = {
3076         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3077         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3078         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3079         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3080         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3081         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3082         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3083         [EXIT_REASON_CPUID]                   = handle_cpuid,
3084         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3085         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3086         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3087         [EXIT_REASON_HLT]                     = handle_halt,
3088         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3089         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3090         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3091         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3092         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3093         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3094         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3095 };
3096
3097 static const int kvm_vmx_max_exit_handlers =
3098         ARRAY_SIZE(kvm_vmx_exit_handlers);
3099
3100 /*
3101  * The guest has exited.  See if we can fix it or if we need userspace
3102  * assistance.
3103  */
3104 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3105 {
3106         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
3107         struct vcpu_vmx *vmx = to_vmx(vcpu);
3108         u32 vectoring_info = vmx->idt_vectoring_info;
3109
3110         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3111                     (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3112
3113         /* If we need to emulate an MMIO from handle_invalid_guest_state
3114          * we just return 0 */
3115         if (vmx->emulation_required && emulate_invalid_guest_state)
3116                 return 0;
3117
3118         /* Access CR3 don't cause VMExit in paging mode, so we need
3119          * to sync with guest real CR3. */
3120         if (vm_need_ept() && is_paging(vcpu)) {
3121                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3122                 ept_load_pdptrs(vcpu);
3123         }
3124
3125         if (unlikely(vmx->fail)) {
3126                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3127                 kvm_run->fail_entry.hardware_entry_failure_reason
3128                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3129                 return 0;
3130         }
3131
3132         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3133                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3134                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3135                         exit_reason != EXIT_REASON_TASK_SWITCH))
3136                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3137                        "(0x%x) and exit reason is 0x%x\n",
3138                        __func__, vectoring_info, exit_reason);
3139
3140         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3141                 if (vcpu->arch.interrupt_window_open) {
3142                         vmx->soft_vnmi_blocked = 0;
3143                         vcpu->arch.nmi_window_open = 1;
3144                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3145                            vcpu->arch.nmi_pending) {
3146                         /*
3147                          * This CPU don't support us in finding the end of an
3148                          * NMI-blocked window if the guest runs with IRQs
3149                          * disabled. So we pull the trigger after 1 s of
3150                          * futile waiting, but inform the user about this.
3151                          */
3152                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3153                                "state on VCPU %d after 1 s timeout\n",
3154                                __func__, vcpu->vcpu_id);
3155                         vmx->soft_vnmi_blocked = 0;
3156                         vmx->vcpu.arch.nmi_window_open = 1;
3157                 }
3158         }
3159
3160         if (exit_reason < kvm_vmx_max_exit_handlers
3161             && kvm_vmx_exit_handlers[exit_reason])
3162                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3163         else {
3164                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3165                 kvm_run->hw.hardware_exit_reason = exit_reason;
3166         }
3167         return 0;
3168 }
3169
3170 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3171 {
3172         int max_irr, tpr;
3173
3174         if (!vm_need_tpr_shadow(vcpu->kvm))
3175                 return;
3176
3177         if (!kvm_lapic_enabled(vcpu) ||
3178             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3179                 vmcs_write32(TPR_THRESHOLD, 0);
3180                 return;
3181         }
3182
3183         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3184         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3185 }
3186
3187 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3188 {
3189         u32 exit_intr_info;
3190         u32 idt_vectoring_info;
3191         bool unblock_nmi;
3192         u8 vector;
3193         int type;
3194         bool idtv_info_valid;
3195         u32 error;
3196
3197         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3198         if (cpu_has_virtual_nmis()) {
3199                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3200                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3201                 /*
3202                  * SDM 3: 25.7.1.2
3203                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3204                  * a guest IRET fault.
3205                  */
3206                 if (unblock_nmi && vector != DF_VECTOR)
3207                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3208                                       GUEST_INTR_STATE_NMI);
3209         } else if (unlikely(vmx->soft_vnmi_blocked))
3210                 vmx->vnmi_blocked_time +=
3211                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3212
3213         idt_vectoring_info = vmx->idt_vectoring_info;
3214         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3215         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3216         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3217         if (vmx->vcpu.arch.nmi_injected) {
3218                 /*
3219                  * SDM 3: 25.7.1.2
3220                  * Clear bit "block by NMI" before VM entry if a NMI delivery
3221                  * faulted.
3222                  */
3223                 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3224                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3225                                         GUEST_INTR_STATE_NMI);
3226                 else
3227                         vmx->vcpu.arch.nmi_injected = false;
3228         }
3229         kvm_clear_exception_queue(&vmx->vcpu);
3230         if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3231                                 type == INTR_TYPE_SOFT_EXCEPTION)) {
3232                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3233                         error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3234                         kvm_queue_exception_e(&vmx->vcpu, vector, error);
3235                 } else
3236                         kvm_queue_exception(&vmx->vcpu, vector);
3237                 vmx->idt_vectoring_info = 0;
3238         }
3239         kvm_clear_interrupt_queue(&vmx->vcpu);
3240         if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3241                 kvm_queue_interrupt(&vmx->vcpu, vector);
3242                 vmx->idt_vectoring_info = 0;
3243         }
3244 }
3245
3246 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3247 {
3248         update_tpr_threshold(vcpu);
3249
3250         vmx_update_window_states(vcpu);
3251
3252         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3253                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3254                                 GUEST_INTR_STATE_STI |
3255                                 GUEST_INTR_STATE_MOV_SS);
3256
3257         if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3258                 if (vcpu->arch.interrupt.pending) {
3259                         enable_nmi_window(vcpu);
3260                 } else if (vcpu->arch.nmi_window_open) {
3261                         vcpu->arch.nmi_pending = false;
3262                         vcpu->arch.nmi_injected = true;
3263                 } else {
3264                         enable_nmi_window(vcpu);
3265                         return;
3266                 }
3267         }
3268         if (vcpu->arch.nmi_injected) {
3269                 vmx_inject_nmi(vcpu);
3270                 if (vcpu->arch.nmi_pending)
3271                         enable_nmi_window(vcpu);
3272                 else if (kvm_cpu_has_interrupt(vcpu))
3273                         enable_irq_window(vcpu);
3274                 return;
3275         }
3276         if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3277                 if (vcpu->arch.interrupt_window_open)
3278                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3279                 else
3280                         enable_irq_window(vcpu);
3281         }
3282         if (vcpu->arch.interrupt.pending) {
3283                 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3284                 if (kvm_cpu_has_interrupt(vcpu))
3285                         enable_irq_window(vcpu);
3286         }
3287 }
3288
3289 /*
3290  * Failure to inject an interrupt should give us the information
3291  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3292  * when fetching the interrupt redirection bitmap in the real-mode
3293  * tss, this doesn't happen.  So we do it ourselves.
3294  */
3295 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3296 {
3297         vmx->rmode.irq.pending = 0;
3298         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3299                 return;
3300         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3301         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3302                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3303                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3304                 return;
3305         }
3306         vmx->idt_vectoring_info =
3307                 VECTORING_INFO_VALID_MASK
3308                 | INTR_TYPE_EXT_INTR
3309                 | vmx->rmode.irq.vector;
3310 }
3311
3312 #ifdef CONFIG_X86_64
3313 #define R "r"
3314 #define Q "q"
3315 #else
3316 #define R "e"
3317 #define Q "l"
3318 #endif
3319
3320 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3321 {
3322         struct vcpu_vmx *vmx = to_vmx(vcpu);
3323         u32 intr_info;
3324
3325         /* Record the guest's net vcpu time for enforced NMI injections. */
3326         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3327                 vmx->entry_time = ktime_get();
3328
3329         /* Handle invalid guest state instead of entering VMX */
3330         if (vmx->emulation_required && emulate_invalid_guest_state) {
3331                 handle_invalid_guest_state(vcpu, kvm_run);
3332                 return;
3333         }
3334
3335         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3336                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3337         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3338                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3339
3340         /*
3341          * Loading guest fpu may have cleared host cr0.ts
3342          */
3343         vmcs_writel(HOST_CR0, read_cr0());
3344
3345         asm(
3346                 /* Store host registers */
3347                 "push %%"R"dx; push %%"R"bp;"
3348                 "push %%"R"cx \n\t"
3349                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3350                 "je 1f \n\t"
3351                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3352                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3353                 "1: \n\t"
3354                 /* Check if vmlaunch of vmresume is needed */
3355                 "cmpl $0, %c[launched](%0) \n\t"
3356                 /* Load guest registers.  Don't clobber flags. */
3357                 "mov %c[cr2](%0), %%"R"ax \n\t"
3358                 "mov %%"R"ax, %%cr2 \n\t"
3359                 "mov %c[rax](%0), %%"R"ax \n\t"
3360                 "mov %c[rbx](%0), %%"R"bx \n\t"
3361                 "mov %c[rdx](%0), %%"R"dx \n\t"
3362                 "mov %c[rsi](%0), %%"R"si \n\t"
3363                 "mov %c[rdi](%0), %%"R"di \n\t"
3364                 "mov %c[rbp](%0), %%"R"bp \n\t"