2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
53 #include <asm/nospec-branch.h>
58 #define __ex(x) __kvm_handle_fault_on_reboot(x)
59 #define __ex_clear(x, reg) \
60 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
62 MODULE_AUTHOR("Qumranet");
63 MODULE_LICENSE("GPL");
65 static const struct x86_cpu_id vmx_cpu_id[] = {
66 X86_FEATURE_MATCH(X86_FEATURE_VMX),
69 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
71 static bool __read_mostly enable_vpid = 1;
72 module_param_named(vpid, enable_vpid, bool, 0444);
74 static bool __read_mostly enable_vnmi = 1;
75 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
77 static bool __read_mostly flexpriority_enabled = 1;
78 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
80 static bool __read_mostly enable_ept = 1;
81 module_param_named(ept, enable_ept, bool, S_IRUGO);
83 static bool __read_mostly enable_unrestricted_guest = 1;
84 module_param_named(unrestricted_guest,
85 enable_unrestricted_guest, bool, S_IRUGO);
87 static bool __read_mostly enable_ept_ad_bits = 1;
88 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
90 static bool __read_mostly emulate_invalid_guest_state = true;
91 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
93 static bool __read_mostly fasteoi = 1;
94 module_param(fasteoi, bool, S_IRUGO);
96 static bool __read_mostly enable_apicv = 1;
97 module_param(enable_apicv, bool, S_IRUGO);
99 static bool __read_mostly enable_shadow_vmcs = 1;
100 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
106 static bool __read_mostly nested = 0;
107 module_param(nested, bool, S_IRUGO);
109 static u64 __read_mostly host_xss;
111 static bool __read_mostly enable_pml = 1;
112 module_param_named(pml, enable_pml, bool, S_IRUGO);
116 #define MSR_TYPE_RW 3
118 #define MSR_BITMAP_MODE_X2APIC 1
119 #define MSR_BITMAP_MODE_X2APIC_APICV 2
120 #define MSR_BITMAP_MODE_LM 4
122 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
124 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
125 static int __read_mostly cpu_preemption_timer_multi;
126 static bool __read_mostly enable_preemption_timer = 1;
128 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
131 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
132 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
133 #define KVM_VM_CR0_ALWAYS_ON \
134 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
135 #define KVM_CR4_GUEST_OWNED_BITS \
136 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
137 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
139 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
140 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
142 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
144 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
147 * Hyper-V requires all of these, so mark them as supported even though
148 * they are just treated the same as all-context.
150 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
151 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
152 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
153 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
154 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
157 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
158 * ple_gap: upper bound on the amount of time between two successive
159 * executions of PAUSE in a loop. Also indicate if ple enabled.
160 * According to test, this time is usually smaller than 128 cycles.
161 * ple_window: upper bound on the amount of time a guest is allowed to execute
162 * in a PAUSE loop. Tests indicate that most spinlocks are held for
163 * less than 2^12 cycles
164 * Time is measured based on a counter that runs at the same rate as the TSC,
165 * refer SDM volume 3b section 21.6.13 & 22.1.3.
167 #define KVM_VMX_DEFAULT_PLE_GAP 128
168 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
169 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
170 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
171 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
172 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
174 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
175 module_param(ple_gap, int, S_IRUGO);
177 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
178 module_param(ple_window, int, S_IRUGO);
180 /* Default doubles per-vcpu window every exit. */
181 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
182 module_param(ple_window_grow, int, S_IRUGO);
184 /* Default resets per-vcpu window every exit to ple_window. */
185 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
186 module_param(ple_window_shrink, int, S_IRUGO);
188 /* Default is to compute the maximum so we can never overflow. */
189 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
190 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
191 module_param(ple_window_max, int, S_IRUGO);
193 extern const ulong vmx_return;
195 #define NR_AUTOLOAD_MSRS 8
204 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
205 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
206 * loaded on this CPU (so we can clear them if the CPU goes down).
210 struct vmcs *shadow_vmcs;
213 bool nmi_known_unmasked;
214 unsigned long vmcs_host_cr3; /* May not match real cr3 */
215 unsigned long vmcs_host_cr4; /* May not match real cr4 */
216 /* Support for vnmi-less CPUs */
217 int soft_vnmi_blocked;
219 s64 vnmi_blocked_time;
220 unsigned long *msr_bitmap;
221 struct list_head loaded_vmcss_on_cpu_link;
224 struct shared_msr_entry {
231 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
232 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
233 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
234 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
235 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
236 * More than one of these structures may exist, if L1 runs multiple L2 guests.
237 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
238 * underlying hardware which will be used to run L2.
239 * This structure is packed to ensure that its layout is identical across
240 * machines (necessary for live migration).
241 * If there are changes in this struct, VMCS12_REVISION must be changed.
243 typedef u64 natural_width;
244 struct __packed vmcs12 {
245 /* According to the Intel spec, a VMCS region must start with the
246 * following two fields. Then follow implementation-specific data.
251 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
252 u32 padding[7]; /* room for future expansion */
257 u64 vm_exit_msr_store_addr;
258 u64 vm_exit_msr_load_addr;
259 u64 vm_entry_msr_load_addr;
261 u64 virtual_apic_page_addr;
262 u64 apic_access_addr;
263 u64 posted_intr_desc_addr;
264 u64 vm_function_control;
266 u64 eoi_exit_bitmap0;
267 u64 eoi_exit_bitmap1;
268 u64 eoi_exit_bitmap2;
269 u64 eoi_exit_bitmap3;
270 u64 eptp_list_address;
272 u64 guest_physical_address;
273 u64 vmcs_link_pointer;
275 u64 guest_ia32_debugctl;
278 u64 guest_ia32_perf_global_ctrl;
286 u64 host_ia32_perf_global_ctrl;
287 u64 padding64[8]; /* room for future expansion */
289 * To allow migration of L1 (complete with its L2 guests) between
290 * machines of different natural widths (32 or 64 bit), we cannot have
291 * unsigned long fields with no explict size. We use u64 (aliased
292 * natural_width) instead. Luckily, x86 is little-endian.
294 natural_width cr0_guest_host_mask;
295 natural_width cr4_guest_host_mask;
296 natural_width cr0_read_shadow;
297 natural_width cr4_read_shadow;
298 natural_width cr3_target_value0;
299 natural_width cr3_target_value1;
300 natural_width cr3_target_value2;
301 natural_width cr3_target_value3;
302 natural_width exit_qualification;
303 natural_width guest_linear_address;
304 natural_width guest_cr0;
305 natural_width guest_cr3;
306 natural_width guest_cr4;
307 natural_width guest_es_base;
308 natural_width guest_cs_base;
309 natural_width guest_ss_base;
310 natural_width guest_ds_base;
311 natural_width guest_fs_base;
312 natural_width guest_gs_base;
313 natural_width guest_ldtr_base;
314 natural_width guest_tr_base;
315 natural_width guest_gdtr_base;
316 natural_width guest_idtr_base;
317 natural_width guest_dr7;
318 natural_width guest_rsp;
319 natural_width guest_rip;
320 natural_width guest_rflags;
321 natural_width guest_pending_dbg_exceptions;
322 natural_width guest_sysenter_esp;
323 natural_width guest_sysenter_eip;
324 natural_width host_cr0;
325 natural_width host_cr3;
326 natural_width host_cr4;
327 natural_width host_fs_base;
328 natural_width host_gs_base;
329 natural_width host_tr_base;
330 natural_width host_gdtr_base;
331 natural_width host_idtr_base;
332 natural_width host_ia32_sysenter_esp;
333 natural_width host_ia32_sysenter_eip;
334 natural_width host_rsp;
335 natural_width host_rip;
336 natural_width paddingl[8]; /* room for future expansion */
337 u32 pin_based_vm_exec_control;
338 u32 cpu_based_vm_exec_control;
339 u32 exception_bitmap;
340 u32 page_fault_error_code_mask;
341 u32 page_fault_error_code_match;
342 u32 cr3_target_count;
343 u32 vm_exit_controls;
344 u32 vm_exit_msr_store_count;
345 u32 vm_exit_msr_load_count;
346 u32 vm_entry_controls;
347 u32 vm_entry_msr_load_count;
348 u32 vm_entry_intr_info_field;
349 u32 vm_entry_exception_error_code;
350 u32 vm_entry_instruction_len;
352 u32 secondary_vm_exec_control;
353 u32 vm_instruction_error;
355 u32 vm_exit_intr_info;
356 u32 vm_exit_intr_error_code;
357 u32 idt_vectoring_info_field;
358 u32 idt_vectoring_error_code;
359 u32 vm_exit_instruction_len;
360 u32 vmx_instruction_info;
367 u32 guest_ldtr_limit;
369 u32 guest_gdtr_limit;
370 u32 guest_idtr_limit;
371 u32 guest_es_ar_bytes;
372 u32 guest_cs_ar_bytes;
373 u32 guest_ss_ar_bytes;
374 u32 guest_ds_ar_bytes;
375 u32 guest_fs_ar_bytes;
376 u32 guest_gs_ar_bytes;
377 u32 guest_ldtr_ar_bytes;
378 u32 guest_tr_ar_bytes;
379 u32 guest_interruptibility_info;
380 u32 guest_activity_state;
381 u32 guest_sysenter_cs;
382 u32 host_ia32_sysenter_cs;
383 u32 vmx_preemption_timer_value;
384 u32 padding32[7]; /* room for future expansion */
385 u16 virtual_processor_id;
387 u16 guest_es_selector;
388 u16 guest_cs_selector;
389 u16 guest_ss_selector;
390 u16 guest_ds_selector;
391 u16 guest_fs_selector;
392 u16 guest_gs_selector;
393 u16 guest_ldtr_selector;
394 u16 guest_tr_selector;
395 u16 guest_intr_status;
397 u16 host_es_selector;
398 u16 host_cs_selector;
399 u16 host_ss_selector;
400 u16 host_ds_selector;
401 u16 host_fs_selector;
402 u16 host_gs_selector;
403 u16 host_tr_selector;
407 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
408 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
409 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
411 #define VMCS12_REVISION 0x11e57ed0
414 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
415 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
416 * current implementation, 4K are reserved to avoid future complications.
418 #define VMCS12_SIZE 0x1000
421 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
422 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
425 /* Has the level1 guest done vmxon? */
430 /* The guest-physical address of the current VMCS L1 keeps for L2 */
433 * Cache of the guest's VMCS, existing outside of guest memory.
434 * Loaded from guest memory during VMPTRLD. Flushed to guest
435 * memory during VMCLEAR and VMPTRLD.
437 struct vmcs12 *cached_vmcs12;
439 * Indicates if the shadow vmcs must be updated with the
440 * data hold by vmcs12
442 bool sync_shadow_vmcs;
444 bool change_vmcs01_virtual_x2apic_mode;
445 /* L2 must run next, and mustn't decide to exit to L1. */
446 bool nested_run_pending;
448 struct loaded_vmcs vmcs02;
451 * Guest pages referred to in the vmcs02 with host-physical
452 * pointers, so we must keep them pinned while L2 runs.
454 struct page *apic_access_page;
455 struct page *virtual_apic_page;
456 struct page *pi_desc_page;
457 struct pi_desc *pi_desc;
461 struct hrtimer preemption_timer;
462 bool preemption_timer_expired;
464 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
471 * We only store the "true" versions of the VMX capability MSRs. We
472 * generate the "non-true" versions by setting the must-be-1 bits
473 * according to the SDM.
475 u32 nested_vmx_procbased_ctls_low;
476 u32 nested_vmx_procbased_ctls_high;
477 u32 nested_vmx_secondary_ctls_low;
478 u32 nested_vmx_secondary_ctls_high;
479 u32 nested_vmx_pinbased_ctls_low;
480 u32 nested_vmx_pinbased_ctls_high;
481 u32 nested_vmx_exit_ctls_low;
482 u32 nested_vmx_exit_ctls_high;
483 u32 nested_vmx_entry_ctls_low;
484 u32 nested_vmx_entry_ctls_high;
485 u32 nested_vmx_misc_low;
486 u32 nested_vmx_misc_high;
487 u32 nested_vmx_ept_caps;
488 u32 nested_vmx_vpid_caps;
489 u64 nested_vmx_basic;
490 u64 nested_vmx_cr0_fixed0;
491 u64 nested_vmx_cr0_fixed1;
492 u64 nested_vmx_cr4_fixed0;
493 u64 nested_vmx_cr4_fixed1;
494 u64 nested_vmx_vmcs_enum;
495 u64 nested_vmx_vmfunc_controls;
497 /* SMM related state */
499 /* in VMX operation on SMM entry? */
501 /* in guest mode on SMM entry? */
506 #define POSTED_INTR_ON 0
507 #define POSTED_INTR_SN 1
509 /* Posted-Interrupt Descriptor */
511 u32 pir[8]; /* Posted interrupt requested */
514 /* bit 256 - Outstanding Notification */
516 /* bit 257 - Suppress Notification */
518 /* bit 271:258 - Reserved */
520 /* bit 279:272 - Notification Vector */
522 /* bit 287:280 - Reserved */
524 /* bit 319:288 - Notification Destination */
532 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
534 return test_and_set_bit(POSTED_INTR_ON,
535 (unsigned long *)&pi_desc->control);
538 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
540 return test_and_clear_bit(POSTED_INTR_ON,
541 (unsigned long *)&pi_desc->control);
544 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
546 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
549 static inline void pi_clear_sn(struct pi_desc *pi_desc)
551 return clear_bit(POSTED_INTR_SN,
552 (unsigned long *)&pi_desc->control);
555 static inline void pi_set_sn(struct pi_desc *pi_desc)
557 return set_bit(POSTED_INTR_SN,
558 (unsigned long *)&pi_desc->control);
561 static inline void pi_clear_on(struct pi_desc *pi_desc)
563 clear_bit(POSTED_INTR_ON,
564 (unsigned long *)&pi_desc->control);
567 static inline int pi_test_on(struct pi_desc *pi_desc)
569 return test_bit(POSTED_INTR_ON,
570 (unsigned long *)&pi_desc->control);
573 static inline int pi_test_sn(struct pi_desc *pi_desc)
575 return test_bit(POSTED_INTR_SN,
576 (unsigned long *)&pi_desc->control);
580 struct kvm_vcpu vcpu;
581 unsigned long host_rsp;
585 u32 idt_vectoring_info;
587 struct shared_msr_entry *guest_msrs;
590 unsigned long host_idt_base;
592 u64 msr_host_kernel_gs_base;
593 u64 msr_guest_kernel_gs_base;
595 u32 vm_entry_controls_shadow;
596 u32 vm_exit_controls_shadow;
597 u32 secondary_exec_control;
600 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
601 * non-nested (L1) guest, it always points to vmcs01. For a nested
602 * guest (L2), it points to a different VMCS.
604 struct loaded_vmcs vmcs01;
605 struct loaded_vmcs *loaded_vmcs;
606 bool __launched; /* temporary, used in vmx_vcpu_run */
607 struct msr_autoload {
609 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
610 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
614 u16 fs_sel, gs_sel, ldt_sel;
618 int gs_ldt_reload_needed;
619 int fs_reload_needed;
620 u64 msr_host_bndcfgs;
625 struct kvm_segment segs[8];
628 u32 bitmask; /* 4 bits per segment (1 bit per field) */
629 struct kvm_save_segment {
637 bool emulation_required;
641 /* Posted interrupt descriptor */
642 struct pi_desc pi_desc;
644 /* Support for a guest hypervisor (nested VMX) */
645 struct nested_vmx nested;
647 /* Dynamic PLE window. */
649 bool ple_window_dirty;
651 /* Support for PML */
652 #define PML_ENTITY_NUM 512
655 /* apic deadline value in host tsc */
658 u64 current_tsc_ratio;
663 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
664 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
665 * in msr_ia32_feature_control_valid_bits.
667 u64 msr_ia32_feature_control;
668 u64 msr_ia32_feature_control_valid_bits;
671 enum segment_cache_field {
680 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
682 return container_of(vcpu, struct vcpu_vmx, vcpu);
685 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
687 return &(to_vmx(vcpu)->pi_desc);
690 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
691 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
692 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
693 [number##_HIGH] = VMCS12_OFFSET(name)+4
696 static unsigned long shadow_read_only_fields[] = {
698 * We do NOT shadow fields that are modified when L0
699 * traps and emulates any vmx instruction (e.g. VMPTRLD,
700 * VMXON...) executed by L1.
701 * For example, VM_INSTRUCTION_ERROR is read
702 * by L1 if a vmx instruction fails (part of the error path).
703 * Note the code assumes this logic. If for some reason
704 * we start shadowing these fields then we need to
705 * force a shadow sync when L0 emulates vmx instructions
706 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
707 * by nested_vmx_failValid)
711 VM_EXIT_INSTRUCTION_LEN,
712 IDT_VECTORING_INFO_FIELD,
713 IDT_VECTORING_ERROR_CODE,
714 VM_EXIT_INTR_ERROR_CODE,
716 GUEST_LINEAR_ADDRESS,
717 GUEST_PHYSICAL_ADDRESS
719 static int max_shadow_read_only_fields =
720 ARRAY_SIZE(shadow_read_only_fields);
722 static unsigned long shadow_read_write_fields[] = {
729 GUEST_INTERRUPTIBILITY_INFO,
742 CPU_BASED_VM_EXEC_CONTROL,
743 VM_ENTRY_EXCEPTION_ERROR_CODE,
744 VM_ENTRY_INTR_INFO_FIELD,
745 VM_ENTRY_INSTRUCTION_LEN,
746 VM_ENTRY_EXCEPTION_ERROR_CODE,
752 static int max_shadow_read_write_fields =
753 ARRAY_SIZE(shadow_read_write_fields);
755 static const unsigned short vmcs_field_to_offset_table[] = {
756 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
757 FIELD(POSTED_INTR_NV, posted_intr_nv),
758 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
759 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
760 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
761 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
762 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
763 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
764 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
765 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
766 FIELD(GUEST_INTR_STATUS, guest_intr_status),
767 FIELD(GUEST_PML_INDEX, guest_pml_index),
768 FIELD(HOST_ES_SELECTOR, host_es_selector),
769 FIELD(HOST_CS_SELECTOR, host_cs_selector),
770 FIELD(HOST_SS_SELECTOR, host_ss_selector),
771 FIELD(HOST_DS_SELECTOR, host_ds_selector),
772 FIELD(HOST_FS_SELECTOR, host_fs_selector),
773 FIELD(HOST_GS_SELECTOR, host_gs_selector),
774 FIELD(HOST_TR_SELECTOR, host_tr_selector),
775 FIELD64(IO_BITMAP_A, io_bitmap_a),
776 FIELD64(IO_BITMAP_B, io_bitmap_b),
777 FIELD64(MSR_BITMAP, msr_bitmap),
778 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
779 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
780 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
781 FIELD64(TSC_OFFSET, tsc_offset),
782 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
783 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
784 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
785 FIELD64(VM_FUNCTION_CONTROL, vm_function_control),
786 FIELD64(EPT_POINTER, ept_pointer),
787 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
788 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
789 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
790 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
791 FIELD64(EPTP_LIST_ADDRESS, eptp_list_address),
792 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
793 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
794 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
795 FIELD64(PML_ADDRESS, pml_address),
796 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
797 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
798 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
799 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
800 FIELD64(GUEST_PDPTR0, guest_pdptr0),
801 FIELD64(GUEST_PDPTR1, guest_pdptr1),
802 FIELD64(GUEST_PDPTR2, guest_pdptr2),
803 FIELD64(GUEST_PDPTR3, guest_pdptr3),
804 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
805 FIELD64(HOST_IA32_PAT, host_ia32_pat),
806 FIELD64(HOST_IA32_EFER, host_ia32_efer),
807 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
808 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
809 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
810 FIELD(EXCEPTION_BITMAP, exception_bitmap),
811 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
812 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
813 FIELD(CR3_TARGET_COUNT, cr3_target_count),
814 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
815 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
816 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
817 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
818 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
819 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
820 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
821 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
822 FIELD(TPR_THRESHOLD, tpr_threshold),
823 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
824 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
825 FIELD(VM_EXIT_REASON, vm_exit_reason),
826 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
827 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
828 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
829 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
830 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
831 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
832 FIELD(GUEST_ES_LIMIT, guest_es_limit),
833 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
834 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
835 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
836 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
837 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
838 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
839 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
840 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
841 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
842 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
843 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
844 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
845 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
846 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
847 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
848 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
849 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
850 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
851 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
852 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
853 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
854 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
855 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
856 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
857 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
858 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
859 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
860 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
861 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
862 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
863 FIELD(EXIT_QUALIFICATION, exit_qualification),
864 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
865 FIELD(GUEST_CR0, guest_cr0),
866 FIELD(GUEST_CR3, guest_cr3),
867 FIELD(GUEST_CR4, guest_cr4),
868 FIELD(GUEST_ES_BASE, guest_es_base),
869 FIELD(GUEST_CS_BASE, guest_cs_base),
870 FIELD(GUEST_SS_BASE, guest_ss_base),
871 FIELD(GUEST_DS_BASE, guest_ds_base),
872 FIELD(GUEST_FS_BASE, guest_fs_base),
873 FIELD(GUEST_GS_BASE, guest_gs_base),
874 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
875 FIELD(GUEST_TR_BASE, guest_tr_base),
876 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
877 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
878 FIELD(GUEST_DR7, guest_dr7),
879 FIELD(GUEST_RSP, guest_rsp),
880 FIELD(GUEST_RIP, guest_rip),
881 FIELD(GUEST_RFLAGS, guest_rflags),
882 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
883 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
884 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
885 FIELD(HOST_CR0, host_cr0),
886 FIELD(HOST_CR3, host_cr3),
887 FIELD(HOST_CR4, host_cr4),
888 FIELD(HOST_FS_BASE, host_fs_base),
889 FIELD(HOST_GS_BASE, host_gs_base),
890 FIELD(HOST_TR_BASE, host_tr_base),
891 FIELD(HOST_GDTR_BASE, host_gdtr_base),
892 FIELD(HOST_IDTR_BASE, host_idtr_base),
893 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
894 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
895 FIELD(HOST_RSP, host_rsp),
896 FIELD(HOST_RIP, host_rip),
899 static inline short vmcs_field_to_offset(unsigned long field)
901 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
903 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table))
907 * FIXME: Mitigation for CVE-2017-5753. To be replaced with a
912 if (vmcs_field_to_offset_table[field] == 0)
915 return vmcs_field_to_offset_table[field];
918 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
920 return to_vmx(vcpu)->nested.cached_vmcs12;
923 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
924 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
925 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
926 static bool vmx_xsaves_supported(void);
927 static void vmx_set_segment(struct kvm_vcpu *vcpu,
928 struct kvm_segment *var, int seg);
929 static void vmx_get_segment(struct kvm_vcpu *vcpu,
930 struct kvm_segment *var, int seg);
931 static bool guest_state_valid(struct kvm_vcpu *vcpu);
932 static u32 vmx_segment_access_rights(struct kvm_segment *var);
933 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
934 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
935 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
936 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
938 static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
940 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
941 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
943 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
944 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
946 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
949 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
950 * can find which vCPU should be waken up.
952 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
953 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
963 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
965 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
966 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
967 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
968 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
970 static bool cpu_has_load_ia32_efer;
971 static bool cpu_has_load_perf_global_ctrl;
973 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
974 static DEFINE_SPINLOCK(vmx_vpid_lock);
976 static struct vmcs_config {
981 u32 pin_based_exec_ctrl;
982 u32 cpu_based_exec_ctrl;
983 u32 cpu_based_2nd_exec_ctrl;
988 static struct vmx_capability {
993 #define VMX_SEGMENT_FIELD(seg) \
994 [VCPU_SREG_##seg] = { \
995 .selector = GUEST_##seg##_SELECTOR, \
996 .base = GUEST_##seg##_BASE, \
997 .limit = GUEST_##seg##_LIMIT, \
998 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1001 static const struct kvm_vmx_segment_field {
1006 } kvm_vmx_segment_fields[] = {
1007 VMX_SEGMENT_FIELD(CS),
1008 VMX_SEGMENT_FIELD(DS),
1009 VMX_SEGMENT_FIELD(ES),
1010 VMX_SEGMENT_FIELD(FS),
1011 VMX_SEGMENT_FIELD(GS),
1012 VMX_SEGMENT_FIELD(SS),
1013 VMX_SEGMENT_FIELD(TR),
1014 VMX_SEGMENT_FIELD(LDTR),
1017 static u64 host_efer;
1019 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1022 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1023 * away by decrementing the array size.
1025 static const u32 vmx_msr_index[] = {
1026 #ifdef CONFIG_X86_64
1027 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1029 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1032 static inline bool is_exception_n(u32 intr_info, u8 vector)
1034 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1035 INTR_INFO_VALID_MASK)) ==
1036 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1039 static inline bool is_debug(u32 intr_info)
1041 return is_exception_n(intr_info, DB_VECTOR);
1044 static inline bool is_breakpoint(u32 intr_info)
1046 return is_exception_n(intr_info, BP_VECTOR);
1049 static inline bool is_page_fault(u32 intr_info)
1051 return is_exception_n(intr_info, PF_VECTOR);
1054 static inline bool is_no_device(u32 intr_info)
1056 return is_exception_n(intr_info, NM_VECTOR);
1059 static inline bool is_invalid_opcode(u32 intr_info)
1061 return is_exception_n(intr_info, UD_VECTOR);
1064 static inline bool is_external_interrupt(u32 intr_info)
1066 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1067 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1070 static inline bool is_machine_check(u32 intr_info)
1072 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1073 INTR_INFO_VALID_MASK)) ==
1074 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1077 static inline bool cpu_has_vmx_msr_bitmap(void)
1079 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1082 static inline bool cpu_has_vmx_tpr_shadow(void)
1084 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1087 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1089 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1092 static inline bool cpu_has_secondary_exec_ctrls(void)
1094 return vmcs_config.cpu_based_exec_ctrl &
1095 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1098 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1100 return vmcs_config.cpu_based_2nd_exec_ctrl &
1101 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1104 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1106 return vmcs_config.cpu_based_2nd_exec_ctrl &
1107 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1110 static inline bool cpu_has_vmx_apic_register_virt(void)
1112 return vmcs_config.cpu_based_2nd_exec_ctrl &
1113 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1116 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1118 return vmcs_config.cpu_based_2nd_exec_ctrl &
1119 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1123 * Comment's format: document - errata name - stepping - processor name.
1125 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1127 static u32 vmx_preemption_cpu_tfms[] = {
1128 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1130 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1131 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1132 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1134 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1136 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1137 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1139 * 320767.pdf - AAP86 - B1 -
1140 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1143 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1145 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1147 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1149 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1150 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1151 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1155 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1157 u32 eax = cpuid_eax(0x00000001), i;
1159 /* Clear the reserved bits */
1160 eax &= ~(0x3U << 14 | 0xfU << 28);
1161 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1162 if (eax == vmx_preemption_cpu_tfms[i])
1168 static inline bool cpu_has_vmx_preemption_timer(void)
1170 return vmcs_config.pin_based_exec_ctrl &
1171 PIN_BASED_VMX_PREEMPTION_TIMER;
1174 static inline bool cpu_has_vmx_posted_intr(void)
1176 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1177 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1180 static inline bool cpu_has_vmx_apicv(void)
1182 return cpu_has_vmx_apic_register_virt() &&
1183 cpu_has_vmx_virtual_intr_delivery() &&
1184 cpu_has_vmx_posted_intr();
1187 static inline bool cpu_has_vmx_flexpriority(void)
1189 return cpu_has_vmx_tpr_shadow() &&
1190 cpu_has_vmx_virtualize_apic_accesses();
1193 static inline bool cpu_has_vmx_ept_execute_only(void)
1195 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1198 static inline bool cpu_has_vmx_ept_2m_page(void)
1200 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1203 static inline bool cpu_has_vmx_ept_1g_page(void)
1205 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1208 static inline bool cpu_has_vmx_ept_4levels(void)
1210 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1213 static inline bool cpu_has_vmx_ept_mt_wb(void)
1215 return vmx_capability.ept & VMX_EPTP_WB_BIT;
1218 static inline bool cpu_has_vmx_ept_5levels(void)
1220 return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
1223 static inline bool cpu_has_vmx_ept_ad_bits(void)
1225 return vmx_capability.ept & VMX_EPT_AD_BIT;
1228 static inline bool cpu_has_vmx_invept_context(void)
1230 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1233 static inline bool cpu_has_vmx_invept_global(void)
1235 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1238 static inline bool cpu_has_vmx_invvpid_single(void)
1240 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1243 static inline bool cpu_has_vmx_invvpid_global(void)
1245 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1248 static inline bool cpu_has_vmx_invvpid(void)
1250 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1253 static inline bool cpu_has_vmx_ept(void)
1255 return vmcs_config.cpu_based_2nd_exec_ctrl &
1256 SECONDARY_EXEC_ENABLE_EPT;
1259 static inline bool cpu_has_vmx_unrestricted_guest(void)
1261 return vmcs_config.cpu_based_2nd_exec_ctrl &
1262 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1265 static inline bool cpu_has_vmx_ple(void)
1267 return vmcs_config.cpu_based_2nd_exec_ctrl &
1268 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1271 static inline bool cpu_has_vmx_basic_inout(void)
1273 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1276 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1278 return flexpriority_enabled && lapic_in_kernel(vcpu);
1281 static inline bool cpu_has_vmx_vpid(void)
1283 return vmcs_config.cpu_based_2nd_exec_ctrl &
1284 SECONDARY_EXEC_ENABLE_VPID;
1287 static inline bool cpu_has_vmx_rdtscp(void)
1289 return vmcs_config.cpu_based_2nd_exec_ctrl &
1290 SECONDARY_EXEC_RDTSCP;
1293 static inline bool cpu_has_vmx_invpcid(void)
1295 return vmcs_config.cpu_based_2nd_exec_ctrl &
1296 SECONDARY_EXEC_ENABLE_INVPCID;
1299 static inline bool cpu_has_virtual_nmis(void)
1301 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1304 static inline bool cpu_has_vmx_wbinvd_exit(void)
1306 return vmcs_config.cpu_based_2nd_exec_ctrl &
1307 SECONDARY_EXEC_WBINVD_EXITING;
1310 static inline bool cpu_has_vmx_shadow_vmcs(void)
1313 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1314 /* check if the cpu supports writing r/o exit information fields */
1315 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1318 return vmcs_config.cpu_based_2nd_exec_ctrl &
1319 SECONDARY_EXEC_SHADOW_VMCS;
1322 static inline bool cpu_has_vmx_pml(void)
1324 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1327 static inline bool cpu_has_vmx_tsc_scaling(void)
1329 return vmcs_config.cpu_based_2nd_exec_ctrl &
1330 SECONDARY_EXEC_TSC_SCALING;
1333 static inline bool cpu_has_vmx_vmfunc(void)
1335 return vmcs_config.cpu_based_2nd_exec_ctrl &
1336 SECONDARY_EXEC_ENABLE_VMFUNC;
1339 static inline bool report_flexpriority(void)
1341 return flexpriority_enabled;
1344 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1346 return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1349 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1351 return vmcs12->cpu_based_vm_exec_control & bit;
1354 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1356 return (vmcs12->cpu_based_vm_exec_control &
1357 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1358 (vmcs12->secondary_vm_exec_control & bit);
1361 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1363 return vmcs12->pin_based_vm_exec_control &
1364 PIN_BASED_VMX_PREEMPTION_TIMER;
1367 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1369 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1372 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1374 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
1377 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1379 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1382 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1384 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1387 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1389 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1392 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1394 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1397 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1399 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1402 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1404 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1407 static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
1409 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
1412 static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
1414 return nested_cpu_has_vmfunc(vmcs12) &&
1415 (vmcs12->vm_function_control &
1416 VMX_VMFUNC_EPTP_SWITCHING);
1419 static inline bool is_nmi(u32 intr_info)
1421 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1422 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1425 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1427 unsigned long exit_qualification);
1428 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1429 struct vmcs12 *vmcs12,
1430 u32 reason, unsigned long qualification);
1432 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1436 for (i = 0; i < vmx->nmsrs; ++i)
1437 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1442 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1448 } operand = { vpid, 0, gva };
1450 asm volatile (__ex(ASM_VMX_INVVPID)
1451 /* CF==1 or ZF==1 --> rc = -1 */
1452 "; ja 1f ; ud2 ; 1:"
1453 : : "a"(&operand), "c"(ext) : "cc", "memory");
1456 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1460 } operand = {eptp, gpa};
1462 asm volatile (__ex(ASM_VMX_INVEPT)
1463 /* CF==1 or ZF==1 --> rc = -1 */
1464 "; ja 1f ; ud2 ; 1:\n"
1465 : : "a" (&operand), "c" (ext) : "cc", "memory");
1468 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1472 i = __find_msr_index(vmx, msr);
1474 return &vmx->guest_msrs[i];
1478 static void vmcs_clear(struct vmcs *vmcs)
1480 u64 phys_addr = __pa(vmcs);
1483 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1484 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1487 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1491 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1493 vmcs_clear(loaded_vmcs->vmcs);
1494 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1495 vmcs_clear(loaded_vmcs->shadow_vmcs);
1496 loaded_vmcs->cpu = -1;
1497 loaded_vmcs->launched = 0;
1500 static void vmcs_load(struct vmcs *vmcs)
1502 u64 phys_addr = __pa(vmcs);
1505 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1506 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1509 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1513 #ifdef CONFIG_KEXEC_CORE
1515 * This bitmap is used to indicate whether the vmclear
1516 * operation is enabled on all cpus. All disabled by
1519 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1521 static inline void crash_enable_local_vmclear(int cpu)
1523 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1526 static inline void crash_disable_local_vmclear(int cpu)
1528 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1531 static inline int crash_local_vmclear_enabled(int cpu)
1533 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1536 static void crash_vmclear_local_loaded_vmcss(void)
1538 int cpu = raw_smp_processor_id();
1539 struct loaded_vmcs *v;
1541 if (!crash_local_vmclear_enabled(cpu))
1544 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1545 loaded_vmcss_on_cpu_link)
1546 vmcs_clear(v->vmcs);
1549 static inline void crash_enable_local_vmclear(int cpu) { }
1550 static inline void crash_disable_local_vmclear(int cpu) { }
1551 #endif /* CONFIG_KEXEC_CORE */
1553 static void __loaded_vmcs_clear(void *arg)
1555 struct loaded_vmcs *loaded_vmcs = arg;
1556 int cpu = raw_smp_processor_id();
1558 if (loaded_vmcs->cpu != cpu)
1559 return; /* vcpu migration can race with cpu offline */
1560 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1561 per_cpu(current_vmcs, cpu) = NULL;
1562 crash_disable_local_vmclear(cpu);
1563 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1566 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1567 * is before setting loaded_vmcs->vcpu to -1 which is done in
1568 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1569 * then adds the vmcs into percpu list before it is deleted.
1573 loaded_vmcs_init(loaded_vmcs);
1574 crash_enable_local_vmclear(cpu);
1577 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1579 int cpu = loaded_vmcs->cpu;
1582 smp_call_function_single(cpu,
1583 __loaded_vmcs_clear, loaded_vmcs, 1);
1586 static inline void vpid_sync_vcpu_single(int vpid)
1591 if (cpu_has_vmx_invvpid_single())
1592 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1595 static inline void vpid_sync_vcpu_global(void)
1597 if (cpu_has_vmx_invvpid_global())
1598 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1601 static inline void vpid_sync_context(int vpid)
1603 if (cpu_has_vmx_invvpid_single())
1604 vpid_sync_vcpu_single(vpid);
1606 vpid_sync_vcpu_global();
1609 static inline void ept_sync_global(void)
1611 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1614 static inline void ept_sync_context(u64 eptp)
1616 if (cpu_has_vmx_invept_context())
1617 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1622 static __always_inline void vmcs_check16(unsigned long field)
1624 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1625 "16-bit accessor invalid for 64-bit field");
1626 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1627 "16-bit accessor invalid for 64-bit high field");
1628 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1629 "16-bit accessor invalid for 32-bit high field");
1630 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1631 "16-bit accessor invalid for natural width field");
1634 static __always_inline void vmcs_check32(unsigned long field)
1636 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1637 "32-bit accessor invalid for 16-bit field");
1638 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1639 "32-bit accessor invalid for natural width field");
1642 static __always_inline void vmcs_check64(unsigned long field)
1644 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1645 "64-bit accessor invalid for 16-bit field");
1646 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1647 "64-bit accessor invalid for 64-bit high field");
1648 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1649 "64-bit accessor invalid for 32-bit field");
1650 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1651 "64-bit accessor invalid for natural width field");
1654 static __always_inline void vmcs_checkl(unsigned long field)
1656 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1657 "Natural width accessor invalid for 16-bit field");
1658 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1659 "Natural width accessor invalid for 64-bit field");
1660 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1661 "Natural width accessor invalid for 64-bit high field");
1662 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1663 "Natural width accessor invalid for 32-bit field");
1666 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1668 unsigned long value;
1670 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1671 : "=a"(value) : "d"(field) : "cc");
1675 static __always_inline u16 vmcs_read16(unsigned long field)
1677 vmcs_check16(field);
1678 return __vmcs_readl(field);
1681 static __always_inline u32 vmcs_read32(unsigned long field)
1683 vmcs_check32(field);
1684 return __vmcs_readl(field);
1687 static __always_inline u64 vmcs_read64(unsigned long field)
1689 vmcs_check64(field);
1690 #ifdef CONFIG_X86_64
1691 return __vmcs_readl(field);
1693 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1697 static __always_inline unsigned long vmcs_readl(unsigned long field)
1700 return __vmcs_readl(field);
1703 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1705 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1706 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1710 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1714 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1715 : "=q"(error) : "a"(value), "d"(field) : "cc");
1716 if (unlikely(error))
1717 vmwrite_error(field, value);
1720 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1722 vmcs_check16(field);
1723 __vmcs_writel(field, value);
1726 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1728 vmcs_check32(field);
1729 __vmcs_writel(field, value);
1732 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1734 vmcs_check64(field);
1735 __vmcs_writel(field, value);
1736 #ifndef CONFIG_X86_64
1738 __vmcs_writel(field+1, value >> 32);
1742 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1745 __vmcs_writel(field, value);
1748 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1750 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1751 "vmcs_clear_bits does not support 64-bit fields");
1752 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1755 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1757 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1758 "vmcs_set_bits does not support 64-bit fields");
1759 __vmcs_writel(field, __vmcs_readl(field) | mask);
1762 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1764 vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1767 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1769 vmcs_write32(VM_ENTRY_CONTROLS, val);
1770 vmx->vm_entry_controls_shadow = val;
1773 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1775 if (vmx->vm_entry_controls_shadow != val)
1776 vm_entry_controls_init(vmx, val);
1779 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1781 return vmx->vm_entry_controls_shadow;
1785 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1787 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1790 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1792 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1795 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1797 vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1800 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1802 vmcs_write32(VM_EXIT_CONTROLS, val);
1803 vmx->vm_exit_controls_shadow = val;
1806 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1808 if (vmx->vm_exit_controls_shadow != val)
1809 vm_exit_controls_init(vmx, val);
1812 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1814 return vmx->vm_exit_controls_shadow;
1818 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1820 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1823 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1825 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1828 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1830 vmx->segment_cache.bitmask = 0;
1833 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1837 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1839 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1840 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1841 vmx->segment_cache.bitmask = 0;
1843 ret = vmx->segment_cache.bitmask & mask;
1844 vmx->segment_cache.bitmask |= mask;
1848 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1850 u16 *p = &vmx->segment_cache.seg[seg].selector;
1852 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1853 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1857 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1859 ulong *p = &vmx->segment_cache.seg[seg].base;
1861 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1862 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1866 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1868 u32 *p = &vmx->segment_cache.seg[seg].limit;
1870 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1871 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1875 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1877 u32 *p = &vmx->segment_cache.seg[seg].ar;
1879 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1880 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1884 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1888 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1889 (1u << DB_VECTOR) | (1u << AC_VECTOR);
1890 if ((vcpu->guest_debug &
1891 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1892 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1893 eb |= 1u << BP_VECTOR;
1894 if (to_vmx(vcpu)->rmode.vm86_active)
1897 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1899 /* When we are running a nested L2 guest and L1 specified for it a
1900 * certain exception bitmap, we must trap the same exceptions and pass
1901 * them to L1. When running L2, we will only handle the exceptions
1902 * specified above if L1 did not want them.
1904 if (is_guest_mode(vcpu))
1905 eb |= get_vmcs12(vcpu)->exception_bitmap;
1907 vmcs_write32(EXCEPTION_BITMAP, eb);
1910 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1911 unsigned long entry, unsigned long exit)
1913 vm_entry_controls_clearbit(vmx, entry);
1914 vm_exit_controls_clearbit(vmx, exit);
1917 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1920 struct msr_autoload *m = &vmx->msr_autoload;
1924 if (cpu_has_load_ia32_efer) {
1925 clear_atomic_switch_msr_special(vmx,
1926 VM_ENTRY_LOAD_IA32_EFER,
1927 VM_EXIT_LOAD_IA32_EFER);
1931 case MSR_CORE_PERF_GLOBAL_CTRL:
1932 if (cpu_has_load_perf_global_ctrl) {
1933 clear_atomic_switch_msr_special(vmx,
1934 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1935 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1941 for (i = 0; i < m->nr; ++i)
1942 if (m->guest[i].index == msr)
1948 m->guest[i] = m->guest[m->nr];
1949 m->host[i] = m->host[m->nr];
1950 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1951 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1954 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1955 unsigned long entry, unsigned long exit,
1956 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1957 u64 guest_val, u64 host_val)
1959 vmcs_write64(guest_val_vmcs, guest_val);
1960 vmcs_write64(host_val_vmcs, host_val);
1961 vm_entry_controls_setbit(vmx, entry);
1962 vm_exit_controls_setbit(vmx, exit);
1965 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1966 u64 guest_val, u64 host_val)
1969 struct msr_autoload *m = &vmx->msr_autoload;
1973 if (cpu_has_load_ia32_efer) {
1974 add_atomic_switch_msr_special(vmx,
1975 VM_ENTRY_LOAD_IA32_EFER,
1976 VM_EXIT_LOAD_IA32_EFER,
1979 guest_val, host_val);
1983 case MSR_CORE_PERF_GLOBAL_CTRL:
1984 if (cpu_has_load_perf_global_ctrl) {
1985 add_atomic_switch_msr_special(vmx,
1986 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1987 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1988 GUEST_IA32_PERF_GLOBAL_CTRL,
1989 HOST_IA32_PERF_GLOBAL_CTRL,
1990 guest_val, host_val);
1994 case MSR_IA32_PEBS_ENABLE:
1995 /* PEBS needs a quiescent period after being disabled (to write
1996 * a record). Disabling PEBS through VMX MSR swapping doesn't
1997 * provide that period, so a CPU could write host's record into
2000 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
2003 for (i = 0; i < m->nr; ++i)
2004 if (m->guest[i].index == msr)
2007 if (i == NR_AUTOLOAD_MSRS) {
2008 printk_once(KERN_WARNING "Not enough msr switch entries. "
2009 "Can't add msr %x\n", msr);
2011 } else if (i == m->nr) {
2013 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
2014 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
2017 m->guest[i].index = msr;
2018 m->guest[i].value = guest_val;
2019 m->host[i].index = msr;
2020 m->host[i].value = host_val;
2023 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2025 u64 guest_efer = vmx->vcpu.arch.efer;
2026 u64 ignore_bits = 0;
2030 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2031 * host CPUID is more efficient than testing guest CPUID
2032 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2034 if (boot_cpu_has(X86_FEATURE_SMEP))
2035 guest_efer |= EFER_NX;
2036 else if (!(guest_efer & EFER_NX))
2037 ignore_bits |= EFER_NX;
2041 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2043 ignore_bits |= EFER_SCE;
2044 #ifdef CONFIG_X86_64
2045 ignore_bits |= EFER_LMA | EFER_LME;
2046 /* SCE is meaningful only in long mode on Intel */
2047 if (guest_efer & EFER_LMA)
2048 ignore_bits &= ~(u64)EFER_SCE;
2051 clear_atomic_switch_msr(vmx, MSR_EFER);
2054 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2055 * On CPUs that support "load IA32_EFER", always switch EFER
2056 * atomically, since it's faster than switching it manually.
2058 if (cpu_has_load_ia32_efer ||
2059 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2060 if (!(guest_efer & EFER_LMA))
2061 guest_efer &= ~EFER_LME;
2062 if (guest_efer != host_efer)
2063 add_atomic_switch_msr(vmx, MSR_EFER,
2064 guest_efer, host_efer);
2067 guest_efer &= ~ignore_bits;
2068 guest_efer |= host_efer & ignore_bits;
2070 vmx->guest_msrs[efer_offset].data = guest_efer;
2071 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2077 #ifdef CONFIG_X86_32
2079 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2080 * VMCS rather than the segment table. KVM uses this helper to figure
2081 * out the current bases to poke them into the VMCS before entry.
2083 static unsigned long segment_base(u16 selector)
2085 struct desc_struct *table;
2088 if (!(selector & ~SEGMENT_RPL_MASK))
2091 table = get_current_gdt_ro();
2093 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2094 u16 ldt_selector = kvm_read_ldt();
2096 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2099 table = (struct desc_struct *)segment_base(ldt_selector);
2101 v = get_desc_base(&table[selector >> 3]);
2106 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2108 struct vcpu_vmx *vmx = to_vmx(vcpu);
2111 if (vmx->host_state.loaded)
2114 vmx->host_state.loaded = 1;
2116 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2117 * allow segment selectors with cpl > 0 or ti == 1.
2119 vmx->host_state.ldt_sel = kvm_read_ldt();
2120 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2121 savesegment(fs, vmx->host_state.fs_sel);
2122 if (!(vmx->host_state.fs_sel & 7)) {
2123 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2124 vmx->host_state.fs_reload_needed = 0;
2126 vmcs_write16(HOST_FS_SELECTOR, 0);
2127 vmx->host_state.fs_reload_needed = 1;
2129 savesegment(gs, vmx->host_state.gs_sel);
2130 if (!(vmx->host_state.gs_sel & 7))
2131 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2133 vmcs_write16(HOST_GS_SELECTOR, 0);
2134 vmx->host_state.gs_ldt_reload_needed = 1;
2137 #ifdef CONFIG_X86_64
2138 savesegment(ds, vmx->host_state.ds_sel);
2139 savesegment(es, vmx->host_state.es_sel);
2142 #ifdef CONFIG_X86_64
2143 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2144 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2146 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2147 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2150 #ifdef CONFIG_X86_64
2151 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2152 if (is_long_mode(&vmx->vcpu))
2153 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2155 if (boot_cpu_has(X86_FEATURE_MPX))
2156 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2157 for (i = 0; i < vmx->save_nmsrs; ++i)
2158 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2159 vmx->guest_msrs[i].data,
2160 vmx->guest_msrs[i].mask);
2163 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2165 if (!vmx->host_state.loaded)
2168 ++vmx->vcpu.stat.host_state_reload;
2169 vmx->host_state.loaded = 0;
2170 #ifdef CONFIG_X86_64
2171 if (is_long_mode(&vmx->vcpu))
2172 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2174 if (vmx->host_state.gs_ldt_reload_needed) {
2175 kvm_load_ldt(vmx->host_state.ldt_sel);
2176 #ifdef CONFIG_X86_64
2177 load_gs_index(vmx->host_state.gs_sel);
2179 loadsegment(gs, vmx->host_state.gs_sel);
2182 if (vmx->host_state.fs_reload_needed)
2183 loadsegment(fs, vmx->host_state.fs_sel);
2184 #ifdef CONFIG_X86_64
2185 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2186 loadsegment(ds, vmx->host_state.ds_sel);
2187 loadsegment(es, vmx->host_state.es_sel);
2190 invalidate_tss_limit();
2191 #ifdef CONFIG_X86_64
2192 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2194 if (vmx->host_state.msr_host_bndcfgs)
2195 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2196 load_fixmap_gdt(raw_smp_processor_id());
2199 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2202 __vmx_load_host_state(vmx);
2206 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2208 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2209 struct pi_desc old, new;
2213 * In case of hot-plug or hot-unplug, we may have to undo
2214 * vmx_vcpu_pi_put even if there is no assigned device. And we
2215 * always keep PI.NDST up to date for simplicity: it makes the
2216 * code easier, and CPU migration is not a fast path.
2218 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
2222 * First handle the simple case where no cmpxchg is necessary; just
2223 * allow posting non-urgent interrupts.
2225 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2226 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2227 * expects the VCPU to be on the blocked_vcpu_list that matches
2230 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
2232 pi_clear_sn(pi_desc);
2236 /* The full case. */
2238 old.control = new.control = pi_desc->control;
2240 dest = cpu_physical_id(cpu);
2242 if (x2apic_enabled())
2245 new.ndst = (dest << 8) & 0xFF00;
2248 } while (cmpxchg64(&pi_desc->control, old.control,
2249 new.control) != old.control);
2252 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2254 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2255 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2259 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2260 * vcpu mutex is already taken.
2262 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2264 struct vcpu_vmx *vmx = to_vmx(vcpu);
2265 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2267 if (!already_loaded) {
2268 loaded_vmcs_clear(vmx->loaded_vmcs);
2269 local_irq_disable();
2270 crash_disable_local_vmclear(cpu);
2273 * Read loaded_vmcs->cpu should be before fetching
2274 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2275 * See the comments in __loaded_vmcs_clear().
2279 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2280 &per_cpu(loaded_vmcss_on_cpu, cpu));
2281 crash_enable_local_vmclear(cpu);
2285 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2286 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2287 vmcs_load(vmx->loaded_vmcs->vmcs);
2290 if (!already_loaded) {
2291 void *gdt = get_current_gdt_ro();
2292 unsigned long sysenter_esp;
2294 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2297 * Linux uses per-cpu TSS and GDT, so set these when switching
2298 * processors. See 22.2.4.
2300 vmcs_writel(HOST_TR_BASE,
2301 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
2302 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
2305 * VM exits change the host TR limit to 0x67 after a VM
2306 * exit. This is okay, since 0x67 covers everything except
2307 * the IO bitmap and have have code to handle the IO bitmap
2308 * being lost after a VM exit.
2310 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2312 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2313 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2315 vmx->loaded_vmcs->cpu = cpu;
2318 /* Setup TSC multiplier */
2319 if (kvm_has_tsc_control &&
2320 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2321 decache_tsc_multiplier(vmx);
2323 vmx_vcpu_pi_load(vcpu, cpu);
2324 vmx->host_pkru = read_pkru();
2327 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2329 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2331 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2332 !irq_remapping_cap(IRQ_POSTING_CAP) ||
2333 !kvm_vcpu_apicv_active(vcpu))
2336 /* Set SN when the vCPU is preempted */
2337 if (vcpu->preempted)
2341 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2343 vmx_vcpu_pi_put(vcpu);
2345 __vmx_load_host_state(to_vmx(vcpu));
2348 static bool emulation_required(struct kvm_vcpu *vcpu)
2350 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2353 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2356 * Return the cr0 value that a nested guest would read. This is a combination
2357 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2358 * its hypervisor (cr0_read_shadow).
2360 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2362 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2363 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2365 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2367 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2368 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2371 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2373 unsigned long rflags, save_rflags;
2375 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2376 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2377 rflags = vmcs_readl(GUEST_RFLAGS);
2378 if (to_vmx(vcpu)->rmode.vm86_active) {
2379 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2380 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2381 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2383 to_vmx(vcpu)->rflags = rflags;
2385 return to_vmx(vcpu)->rflags;
2388 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2390 unsigned long old_rflags = vmx_get_rflags(vcpu);
2392 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2393 to_vmx(vcpu)->rflags = rflags;
2394 if (to_vmx(vcpu)->rmode.vm86_active) {
2395 to_vmx(vcpu)->rmode.save_rflags = rflags;
2396 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2398 vmcs_writel(GUEST_RFLAGS, rflags);
2400 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
2401 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
2404 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2406 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2409 if (interruptibility & GUEST_INTR_STATE_STI)
2410 ret |= KVM_X86_SHADOW_INT_STI;
2411 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2412 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2417 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2419 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2420 u32 interruptibility = interruptibility_old;
2422 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2424 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2425 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2426 else if (mask & KVM_X86_SHADOW_INT_STI)
2427 interruptibility |= GUEST_INTR_STATE_STI;
2429 if ((interruptibility != interruptibility_old))
2430 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2433 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2437 rip = kvm_rip_read(vcpu);
2438 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2439 kvm_rip_write(vcpu, rip);
2441 /* skipping an emulated instruction also counts */
2442 vmx_set_interrupt_shadow(vcpu, 0);
2445 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu,
2446 unsigned long exit_qual)
2448 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2449 unsigned int nr = vcpu->arch.exception.nr;
2450 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2452 if (vcpu->arch.exception.has_error_code) {
2453 vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code;
2454 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2457 if (kvm_exception_is_soft(nr))
2458 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2460 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2462 if (!(vmcs12->idt_vectoring_info_field & VECTORING_INFO_VALID_MASK) &&
2463 vmx_get_nmi_mask(vcpu))
2464 intr_info |= INTR_INFO_UNBLOCK_NMI;
2466 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, intr_info, exit_qual);
2470 * KVM wants to inject page-faults which it got to the guest. This function
2471 * checks whether in a nested guest, we need to inject them to L1 or L2.
2473 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned long *exit_qual)
2475 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2476 unsigned int nr = vcpu->arch.exception.nr;
2478 if (nr == PF_VECTOR) {
2479 if (vcpu->arch.exception.nested_apf) {
2480 *exit_qual = vcpu->arch.apf.nested_apf_token;
2484 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2485 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2486 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2487 * can be written only when inject_pending_event runs. This should be
2488 * conditional on a new capability---if the capability is disabled,
2489 * kvm_multiple_exception would write the ancillary information to
2490 * CR2 or DR6, for backwards ABI-compatibility.
2492 if (nested_vmx_is_page_fault_vmexit(vmcs12,
2493 vcpu->arch.exception.error_code)) {
2494 *exit_qual = vcpu->arch.cr2;
2498 if (vmcs12->exception_bitmap & (1u << nr)) {
2499 if (nr == DB_VECTOR)
2500 *exit_qual = vcpu->arch.dr6;
2510 static void vmx_queue_exception(struct kvm_vcpu *vcpu)
2512 struct vcpu_vmx *vmx = to_vmx(vcpu);
2513 unsigned nr = vcpu->arch.exception.nr;
2514 bool has_error_code = vcpu->arch.exception.has_error_code;
2515 u32 error_code = vcpu->arch.exception.error_code;
2516 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2518 if (has_error_code) {
2519 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2520 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2523 if (vmx->rmode.vm86_active) {
2525 if (kvm_exception_is_soft(nr))
2526 inc_eip = vcpu->arch.event_exit_inst_len;
2527 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2528 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2532 if (kvm_exception_is_soft(nr)) {
2533 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2534 vmx->vcpu.arch.event_exit_inst_len);
2535 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2537 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2539 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2542 static bool vmx_rdtscp_supported(void)
2544 return cpu_has_vmx_rdtscp();
2547 static bool vmx_invpcid_supported(void)
2549 return cpu_has_vmx_invpcid() && enable_ept;
2553 * Swap MSR entry in host/guest MSR entry array.
2555 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2557 struct shared_msr_entry tmp;
2559 tmp = vmx->guest_msrs[to];
2560 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2561 vmx->guest_msrs[from] = tmp;
2565 * Set up the vmcs to automatically save and restore system
2566 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2567 * mode, as fiddling with msrs is very expensive.
2569 static void setup_msrs(struct vcpu_vmx *vmx)
2571 int save_nmsrs, index;
2574 #ifdef CONFIG_X86_64
2575 if (is_long_mode(&vmx->vcpu)) {
2576 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2578 move_msr_up(vmx, index, save_nmsrs++);
2579 index = __find_msr_index(vmx, MSR_LSTAR);
2581 move_msr_up(vmx, index, save_nmsrs++);
2582 index = __find_msr_index(vmx, MSR_CSTAR);
2584 move_msr_up(vmx, index, save_nmsrs++);
2585 index = __find_msr_index(vmx, MSR_TSC_AUX);
2586 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
2587 move_msr_up(vmx, index, save_nmsrs++);
2589 * MSR_STAR is only needed on long mode guests, and only
2590 * if efer.sce is enabled.
2592 index = __find_msr_index(vmx, MSR_STAR);
2593 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2594 move_msr_up(vmx, index, save_nmsrs++);
2597 index = __find_msr_index(vmx, MSR_EFER);
2598 if (index >= 0 && update_transition_efer(vmx, index))
2599 move_msr_up(vmx, index, save_nmsrs++);
2601 vmx->save_nmsrs = save_nmsrs;
2603 if (cpu_has_vmx_msr_bitmap())
2604 vmx_update_msr_bitmap(&vmx->vcpu);
2608 * reads and returns guest's timestamp counter "register"
2609 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2610 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2612 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2614 u64 host_tsc, tsc_offset;
2617 tsc_offset = vmcs_read64(TSC_OFFSET);
2618 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2622 * writes 'offset' into guest's timestamp counter offset register
2624 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2626 if (is_guest_mode(vcpu)) {
2628 * We're here if L1 chose not to trap WRMSR to TSC. According
2629 * to the spec, this should set L1's TSC; The offset that L1
2630 * set for L2 remains unchanged, and still needs to be added
2631 * to the newly set TSC to get L2's TSC.
2633 struct vmcs12 *vmcs12;
2634 /* recalculate vmcs02.TSC_OFFSET: */
2635 vmcs12 = get_vmcs12(vcpu);
2636 vmcs_write64(TSC_OFFSET, offset +
2637 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2638 vmcs12->tsc_offset : 0));
2640 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2641 vmcs_read64(TSC_OFFSET), offset);
2642 vmcs_write64(TSC_OFFSET, offset);
2647 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2648 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2649 * all guests if the "nested" module option is off, and can also be disabled
2650 * for a single guest by disabling its VMX cpuid bit.
2652 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2654 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
2658 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2659 * returned for the various VMX controls MSRs when nested VMX is enabled.
2660 * The same values should also be used to verify that vmcs12 control fields are
2661 * valid during nested entry from L1 to L2.
2662 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2663 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2664 * bit in the high half is on if the corresponding bit in the control field
2665 * may be on. See also vmx_control_verify().
2667 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2670 * Note that as a general rule, the high half of the MSRs (bits in
2671 * the control fields which may be 1) should be initialized by the
2672 * intersection of the underlying hardware's MSR (i.e., features which
2673 * can be supported) and the list of features we want to expose -
2674 * because they are known to be properly supported in our code.
2675 * Also, usually, the low half of the MSRs (bits which must be 1) can
2676 * be set to 0, meaning that L1 may turn off any of these bits. The
2677 * reason is that if one of these bits is necessary, it will appear
2678 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2679 * fields of vmcs01 and vmcs02, will turn these bits off - and
2680 * nested_vmx_exit_reflected() will not pass related exits to L1.
2681 * These rules have exceptions below.
2684 /* pin-based controls */
2685 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2686 vmx->nested.nested_vmx_pinbased_ctls_low,
2687 vmx->nested.nested_vmx_pinbased_ctls_high);
2688 vmx->nested.nested_vmx_pinbased_ctls_low |=
2689 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2690 vmx->nested.nested_vmx_pinbased_ctls_high &=
2691 PIN_BASED_EXT_INTR_MASK |
2692 PIN_BASED_NMI_EXITING |
2693 PIN_BASED_VIRTUAL_NMIS;
2694 vmx->nested.nested_vmx_pinbased_ctls_high |=
2695 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2696 PIN_BASED_VMX_PREEMPTION_TIMER;
2697 if (kvm_vcpu_apicv_active(&vmx->vcpu))
2698 vmx->nested.nested_vmx_pinbased_ctls_high |=
2699 PIN_BASED_POSTED_INTR;
2702 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2703 vmx->nested.nested_vmx_exit_ctls_low,
2704 vmx->nested.nested_vmx_exit_ctls_high);
2705 vmx->nested.nested_vmx_exit_ctls_low =
2706 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2708 vmx->nested.nested_vmx_exit_ctls_high &=
2709 #ifdef CONFIG_X86_64
2710 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2712 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2713 vmx->nested.nested_vmx_exit_ctls_high |=
2714 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2715 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2716 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2718 if (kvm_mpx_supported())
2719 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2721 /* We support free control of debug control saving. */
2722 vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2724 /* entry controls */
2725 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2726 vmx->nested.nested_vmx_entry_ctls_low,
2727 vmx->nested.nested_vmx_entry_ctls_high);
2728 vmx->nested.nested_vmx_entry_ctls_low =
2729 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2730 vmx->nested.nested_vmx_entry_ctls_high &=
2731 #ifdef CONFIG_X86_64
2732 VM_ENTRY_IA32E_MODE |
2734 VM_ENTRY_LOAD_IA32_PAT;
2735 vmx->nested.nested_vmx_entry_ctls_high |=
2736 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2737 if (kvm_mpx_supported())
2738 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2740 /* We support free control of debug control loading. */
2741 vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2743 /* cpu-based controls */
2744 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2745 vmx->nested.nested_vmx_procbased_ctls_low,
2746 vmx->nested.nested_vmx_procbased_ctls_high);
2747 vmx->nested.nested_vmx_procbased_ctls_low =
2748 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2749 vmx->nested.nested_vmx_procbased_ctls_high &=
2750 CPU_BASED_VIRTUAL_INTR_PENDING |
2751 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2752 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2753 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2754 CPU_BASED_CR3_STORE_EXITING |
2755 #ifdef CONFIG_X86_64
2756 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2758 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2759 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2760 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2761 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2762 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2764 * We can allow some features even when not supported by the
2765 * hardware. For example, L1 can specify an MSR bitmap - and we
2766 * can use it to avoid exits to L1 - even when L0 runs L2
2767 * without MSR bitmaps.
2769 vmx->nested.nested_vmx_procbased_ctls_high |=
2770 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2771 CPU_BASED_USE_MSR_BITMAPS;
2773 /* We support free control of CR3 access interception. */
2774 vmx->nested.nested_vmx_procbased_ctls_low &=
2775 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2778 * secondary cpu-based controls. Do not include those that
2779 * depend on CPUID bits, they are added later by vmx_cpuid_update.
2781 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2782 vmx->nested.nested_vmx_secondary_ctls_low,
2783 vmx->nested.nested_vmx_secondary_ctls_high);
2784 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2785 vmx->nested.nested_vmx_secondary_ctls_high &=
2786 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2787 SECONDARY_EXEC_DESC |
2788 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2789 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2790 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2791 SECONDARY_EXEC_WBINVD_EXITING;
2794 /* nested EPT: emulate EPT also to L1 */
2795 vmx->nested.nested_vmx_secondary_ctls_high |=
2796 SECONDARY_EXEC_ENABLE_EPT;
2797 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2798 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2799 if (cpu_has_vmx_ept_execute_only())
2800 vmx->nested.nested_vmx_ept_caps |=
2801 VMX_EPT_EXECUTE_ONLY_BIT;
2802 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2803 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2804 VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2805 VMX_EPT_1GB_PAGE_BIT;
2806 if (enable_ept_ad_bits) {
2807 vmx->nested.nested_vmx_secondary_ctls_high |=
2808 SECONDARY_EXEC_ENABLE_PML;
2809 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2813 if (cpu_has_vmx_vmfunc()) {
2814 vmx->nested.nested_vmx_secondary_ctls_high |=
2815 SECONDARY_EXEC_ENABLE_VMFUNC;
2817 * Advertise EPTP switching unconditionally
2818 * since we emulate it
2821 vmx->nested.nested_vmx_vmfunc_controls =
2822 VMX_VMFUNC_EPTP_SWITCHING;
2826 * Old versions of KVM use the single-context version without
2827 * checking for support, so declare that it is supported even
2828 * though it is treated as global context. The alternative is
2829 * not failing the single-context invvpid, and it is worse.
2832 vmx->nested.nested_vmx_secondary_ctls_high |=
2833 SECONDARY_EXEC_ENABLE_VPID;
2834 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2835 VMX_VPID_EXTENT_SUPPORTED_MASK;
2838 if (enable_unrestricted_guest)
2839 vmx->nested.nested_vmx_secondary_ctls_high |=
2840 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2842 /* miscellaneous data */
2843 rdmsr(MSR_IA32_VMX_MISC,
2844 vmx->nested.nested_vmx_misc_low,
2845 vmx->nested.nested_vmx_misc_high);
2846 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2847 vmx->nested.nested_vmx_misc_low |=
2848 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2849 VMX_MISC_ACTIVITY_HLT;
2850 vmx->nested.nested_vmx_misc_high = 0;
2853 * This MSR reports some information about VMX support. We
2854 * should return information about the VMX we emulate for the
2855 * guest, and the VMCS structure we give it - not about the
2856 * VMX support of the underlying hardware.
2858 vmx->nested.nested_vmx_basic =
2860 VMX_BASIC_TRUE_CTLS |
2861 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2862 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2864 if (cpu_has_vmx_basic_inout())
2865 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2868 * These MSRs specify bits which the guest must keep fixed on
2869 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2870 * We picked the standard core2 setting.
2872 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2873 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2874 vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2875 vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2877 /* These MSRs specify bits which the guest must keep fixed off. */
2878 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2879 rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2881 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2882 vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2886 * if fixed0[i] == 1: val[i] must be 1
2887 * if fixed1[i] == 0: val[i] must be 0
2889 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2891 return ((val & fixed1) | fixed0) == val;
2894 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2896 return fixed_bits_valid(control, low, high);
2899 static inline u64 vmx_control_msr(u32 low, u32 high)
2901 return low | ((u64)high << 32);
2904 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2909 return (superset | subset) == superset;
2912 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2914 const u64 feature_and_reserved =
2915 /* feature (except bit 48; see below) */
2916 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2918 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2919 u64 vmx_basic = vmx->nested.nested_vmx_basic;
2921 if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2925 * KVM does not emulate a version of VMX that constrains physical
2926 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2928 if (data & BIT_ULL(48))
2931 if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2932 vmx_basic_vmcs_revision_id(data))
2935 if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2938 vmx->nested.nested_vmx_basic = data;
2943 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2948 switch (msr_index) {
2949 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2950 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2951 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2953 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2954 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2955 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2957 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2958 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2959 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2961 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2962 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2963 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2965 case MSR_IA32_VMX_PROCBASED_CTLS2:
2966 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2967 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2973 supported = vmx_control_msr(*lowp, *highp);
2975 /* Check must-be-1 bits are still 1. */
2976 if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2979 /* Check must-be-0 bits are still 0. */
2980 if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2984 *highp = data >> 32;
2988 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2990 const u64 feature_and_reserved_bits =
2992 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2993 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2995 GENMASK_ULL(13, 9) | BIT_ULL(31);
2998 vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2999 vmx->nested.nested_vmx_misc_high);
3001 if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
3004 if ((vmx->nested.nested_vmx_pinbased_ctls_high &
3005 PIN_BASED_VMX_PREEMPTION_TIMER) &&
3006 vmx_misc_preemption_timer_rate(data) !=
3007 vmx_misc_preemption_timer_rate(vmx_misc))
3010 if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
3013 if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
3016 if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
3019 vmx->nested.nested_vmx_misc_low = data;
3020 vmx->nested.nested_vmx_misc_high = data >> 32;
3024 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
3026 u64 vmx_ept_vpid_cap;
3028 vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
3029 vmx->nested.nested_vmx_vpid_caps);
3031 /* Every bit is either reserved or a feature bit. */
3032 if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
3035 vmx->nested.nested_vmx_ept_caps = data;
3036 vmx->nested.nested_vmx_vpid_caps = data >> 32;
3040 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
3044 switch (msr_index) {
3045 case MSR_IA32_VMX_CR0_FIXED0:
3046 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3048 case MSR_IA32_VMX_CR4_FIXED0:
3049 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3056 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3057 * must be 1 in the restored value.
3059 if (!is_bitwise_subset(data, *msr, -1ULL))
3067 * Called when userspace is restoring VMX MSRs.
3069 * Returns 0 on success, non-0 otherwise.
3071 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3073 struct vcpu_vmx *vmx = to_vmx(vcpu);
3075 switch (msr_index) {
3076 case MSR_IA32_VMX_BASIC:
3077 return vmx_restore_vmx_basic(vmx, data);
3078 case MSR_IA32_VMX_PINBASED_CTLS:
3079 case MSR_IA32_VMX_PROCBASED_CTLS:
3080 case MSR_IA32_VMX_EXIT_CTLS:
3081 case MSR_IA32_VMX_ENTRY_CTLS:
3083 * The "non-true" VMX capability MSRs are generated from the
3084 * "true" MSRs, so we do not support restoring them directly.
3086 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3087 * should restore the "true" MSRs with the must-be-1 bits
3088 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3089 * DEFAULT SETTINGS".
3092 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3093 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3094 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3095 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3096 case MSR_IA32_VMX_PROCBASED_CTLS2:
3097 return vmx_restore_control_msr(vmx, msr_index, data);
3098 case MSR_IA32_VMX_MISC:
3099 return vmx_restore_vmx_misc(vmx, data);
3100 case MSR_IA32_VMX_CR0_FIXED0:
3101 case MSR_IA32_VMX_CR4_FIXED0:
3102 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3103 case MSR_IA32_VMX_CR0_FIXED1:
3104 case MSR_IA32_VMX_CR4_FIXED1:
3106 * These MSRs are generated based on the vCPU's CPUID, so we
3107 * do not support restoring them directly.
3110 case MSR_IA32_VMX_EPT_VPID_CAP:
3111 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3112 case MSR_IA32_VMX_VMCS_ENUM:
3113 vmx->nested.nested_vmx_vmcs_enum = data;
3117 * The rest of the VMX capability MSRs do not support restore.
3123 /* Returns 0 on success, non-0 otherwise. */
3124 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3126 struct vcpu_vmx *vmx = to_vmx(vcpu);
3128 switch (msr_index) {
3129 case MSR_IA32_VMX_BASIC:
3130 *pdata = vmx->nested.nested_vmx_basic;
3132 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3133 case MSR_IA32_VMX_PINBASED_CTLS:
3134 *pdata = vmx_control_msr(
3135 vmx->nested.nested_vmx_pinbased_ctls_low,
3136 vmx->nested.nested_vmx_pinbased_ctls_high);
3137 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3138 *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3140 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3141 case MSR_IA32_VMX_PROCBASED_CTLS:
3142 *pdata = vmx_control_msr(
3143 vmx->nested.nested_vmx_procbased_ctls_low,
3144 vmx->nested.nested_vmx_procbased_ctls_high);
3145 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3146 *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3148 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3149 case MSR_IA32_VMX_EXIT_CTLS:
3150 *pdata = vmx_control_msr(
3151 vmx->nested.nested_vmx_exit_ctls_low,
3152 vmx->nested.nested_vmx_exit_ctls_high);
3153 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3154 *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3156 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3157 case MSR_IA32_VMX_ENTRY_CTLS:
3158 *pdata = vmx_control_msr(
3159 vmx->nested.nested_vmx_entry_ctls_low,
3160 vmx->nested.nested_vmx_entry_ctls_high);
3161 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3162 *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3164 case MSR_IA32_VMX_MISC:
3165 *pdata = vmx_control_msr(
3166 vmx->nested.nested_vmx_misc_low,
3167 vmx->nested.nested_vmx_misc_high);
3169 case MSR_IA32_VMX_CR0_FIXED0:
3170 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3172 case MSR_IA32_VMX_CR0_FIXED1:
3173 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3175 case MSR_IA32_VMX_CR4_FIXED0:
3176 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3178 case MSR_IA32_VMX_CR4_FIXED1:
3179 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3181 case MSR_IA32_VMX_VMCS_ENUM:
3182 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3184 case MSR_IA32_VMX_PROCBASED_CTLS2:
3185 *pdata = vmx_control_msr(
3186 vmx->nested.nested_vmx_secondary_ctls_low,
3187 vmx->nested.nested_vmx_secondary_ctls_high);
3189 case MSR_IA32_VMX_EPT_VPID_CAP:
3190 *pdata = vmx->nested.nested_vmx_ept_caps |
3191 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3193 case MSR_IA32_VMX_VMFUNC:
3194 *pdata = vmx->nested.nested_vmx_vmfunc_controls;
3203 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3206 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3208 return !(val & ~valid_bits);
3212 * Reads an msr value (of 'msr_index') into 'pdata'.
3213 * Returns 0 on success, non-0 otherwise.
3214 * Assumes vcpu_load() was already called.
3216 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3218 struct shared_msr_entry *msr;
3220 switch (msr_info->index) {
3221 #ifdef CONFIG_X86_64
3223 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3226 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3228 case MSR_KERNEL_GS_BASE:
3229 vmx_load_host_state(to_vmx(vcpu));
3230 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3234 return kvm_get_msr_common(vcpu, msr_info);
3236 msr_info->data = guest_read_tsc(vcpu);
3238 case MSR_IA32_SYSENTER_CS:
3239 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3241 case MSR_IA32_SYSENTER_EIP:
3242 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3244 case MSR_IA32_SYSENTER_ESP:
3245 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3247 case MSR_IA32_BNDCFGS:
3248 if (!kvm_mpx_supported() ||
3249 (!msr_info->host_initiated &&
3250 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3252 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3254 case MSR_IA32_MCG_EXT_CTL:
3255 if (!msr_info->host_initiated &&
3256 !(to_vmx(vcpu)->msr_ia32_feature_control &
3257 FEATURE_CONTROL_LMCE))
3259 msr_info->data = vcpu->arch.mcg_ext_ctl;
3261 case MSR_IA32_FEATURE_CONTROL:
3262 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3264 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3265 if (!nested_vmx_allowed(vcpu))
3267 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3269 if (!vmx_xsaves_supported())
3271 msr_info->data = vcpu->arch.ia32_xss;
3274 if (!msr_info->host_initiated &&
3275 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
3277 /* Otherwise falls through */
3279 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3281 msr_info->data = msr->data;
3284 return kvm_get_msr_common(vcpu, msr_info);
3290 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3293 * Writes msr value into into the appropriate "register".
3294 * Returns 0 on success, non-0 otherwise.
3295 * Assumes vcpu_load() was already called.
3297 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3299 struct vcpu_vmx *vmx = to_vmx(vcpu);
3300 struct shared_msr_entry *msr;
3302 u32 msr_index = msr_info->index;
3303 u64 data = msr_info->data;
3305 switch (msr_index) {
3307 ret = kvm_set_msr_common(vcpu, msr_info);
3309 #ifdef CONFIG_X86_64
3311 vmx_segment_cache_clear(vmx);
3312 vmcs_writel(GUEST_FS_BASE, data);
3315 vmx_segment_cache_clear(vmx);
3316 vmcs_writel(GUEST_GS_BASE, data);
3318 case MSR_KERNEL_GS_BASE:
3319 vmx_load_host_state(vmx);
3320 vmx->msr_guest_kernel_gs_base = data;
3323 case MSR_IA32_SYSENTER_CS:
3324 vmcs_write32(GUEST_SYSENTER_CS, data);
3326 case MSR_IA32_SYSENTER_EIP:
3327 vmcs_writel(GUEST_SYSENTER_EIP, data);
3329 case MSR_IA32_SYSENTER_ESP:
3330 vmcs_writel(GUEST_SYSENTER_ESP, data);
3332 case MSR_IA32_BNDCFGS:
3333 if (!kvm_mpx_supported() ||
3334 (!msr_info->host_initiated &&
3335 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
3337 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
3338 (data & MSR_IA32_BNDCFGS_RSVD))
3340 vmcs_write64(GUEST_BNDCFGS, data);
3343 kvm_write_tsc(vcpu, msr_info);
3345 case MSR_IA32_CR_PAT:
3346 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3347 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3349 vmcs_write64(GUEST_IA32_PAT, data);
3350 vcpu->arch.pat = data;
3353 ret = kvm_set_msr_common(vcpu, msr_info);
3355 case MSR_IA32_TSC_ADJUST:
3356 ret = kvm_set_msr_common(vcpu, msr_info);
3358 case MSR_IA32_MCG_EXT_CTL:
3359 if ((!msr_info->host_initiated &&
3360 !(to_vmx(vcpu)->msr_ia32_feature_control &
3361 FEATURE_CONTROL_LMCE)) ||
3362 (data & ~MCG_EXT_CTL_LMCE_EN))
3364 vcpu->arch.mcg_ext_ctl = data;
3366 case MSR_IA32_FEATURE_CONTROL:
3367 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3368 (to_vmx(vcpu)->msr_ia32_feature_control &
3369 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3371 vmx->msr_ia32_feature_control = data;
3372 if (msr_info->host_initiated && data == 0)
3373 vmx_leave_nested(vcpu);
3375 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3376 if (!msr_info->host_initiated)
3377 return 1; /* they are read-only */
3378 if (!nested_vmx_allowed(vcpu))
3380 return vmx_set_vmx_msr(vcpu, msr_index, data);
3382 if (!vmx_xsaves_supported())
3385 * The only supported bit as of Skylake is bit 8, but
3386 * it is not supported on KVM.
3390 vcpu->arch.ia32_xss = data;
3391 if (vcpu->arch.ia32_xss != host_xss)
3392 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3393 vcpu->arch.ia32_xss, host_xss);
3395 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3398 if (!msr_info->host_initiated &&
3399 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))