arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly fasteoi = 1;
  88 module_param(fasteoi, bool, S_IRUGO);
  89
  90 static bool __read_mostly enable_apicv = 1;
  91 module_param(enable_apicv, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_shadow_vmcs = 1;
  94 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  95 /*
  96  * If nested=1, nested virtualization is supported, i.e., guests may use
  97  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  98  * use VMX instructions.
  99  */
 100 static bool __read_mostly nested = 0;
 101 module_param(nested, bool, S_IRUGO);
 102
 103 static u64 __read_mostly host_xss;
 104
 105 static bool __read_mostly enable_pml = 1;
 106 module_param_named(pml, enable_pml, bool, S_IRUGO);
 107
 108 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 109
 110 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 111 static int __read_mostly cpu_preemption_timer_multi;
 112 static bool __read_mostly enable_preemption_timer = 1;
 113 #ifdef CONFIG_X86_64
 114 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 115 #endif
 116
 117 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 118 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 119 #define KVM_VM_CR0_ALWAYS_ON                                            \
 120         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 121 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 122         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 123          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 124
 125 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 126 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 127
 128 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 129
 130 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 131
 132 /*
 133  * Hyper-V requires all of these, so mark them as supported even though
 134  * they are just treated the same as all-context.
 135  */
 136 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 137         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 138         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 139         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 140         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 141
 142 /*
 143  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 144  * ple_gap:    upper bound on the amount of time between two successive
 145  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 146  *             According to test, this time is usually smaller than 128 cycles.
 147  * ple_window: upper bound on the amount of time a guest is allowed to execute
 148  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 149  *             less than 2^12 cycles
 150  * Time is measured based on a counter that runs at the same rate as the TSC,
 151  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 152  */
 153 #define KVM_VMX_DEFAULT_PLE_GAP           128
 154 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 155 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 156 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 158                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 159
 160 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 161 module_param(ple_gap, int, S_IRUGO);
 162
 163 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 164 module_param(ple_window, int, S_IRUGO);
 165
 166 /* Default doubles per-vcpu window every exit. */
 167 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 168 module_param(ple_window_grow, int, S_IRUGO);
 169
 170 /* Default resets per-vcpu window every exit to ple_window. */
 171 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 172 module_param(ple_window_shrink, int, S_IRUGO);
 173
 174 /* Default is to compute the maximum so we can never overflow. */
 175 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 176 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 177 module_param(ple_window_max, int, S_IRUGO);
 178
 179 extern const ulong vmx_return;
 180
 181 #define NR_AUTOLOAD_MSRS 8
 182 #define VMCS02_POOL_SIZE 1
 183
 184 struct vmcs {
 185         u32 revision_id;
 186         u32 abort;
 187         char data[0];
 188 };
 189
 190 /*
 191  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 192  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 193  * loaded on this CPU (so we can clear them if the CPU goes down).
 194  */
 195 struct loaded_vmcs {
 196         struct vmcs *vmcs;
 197         struct vmcs *shadow_vmcs;
 198         int cpu;
 199         int launched;
 200         struct list_head loaded_vmcss_on_cpu_link;
 201 };
 202
 203 struct shared_msr_entry {
 204         unsigned index;
 205         u64 data;
 206         u64 mask;
 207 };
 208
 209 /*
 210  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 211  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 212  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 213  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 214  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 215  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 216  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 217  * underlying hardware which will be used to run L2.
 218  * This structure is packed to ensure that its layout is identical across
 219  * machines (necessary for live migration).
 220  * If there are changes in this struct, VMCS12_REVISION must be changed.
 221  */
 222 typedef u64 natural_width;
 223 struct __packed vmcs12 {
 224         /* According to the Intel spec, a VMCS region must start with the
 225          * following two fields. Then follow implementation-specific data.
 226          */
 227         u32 revision_id;
 228         u32 abort;
 229
 230         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 231         u32 padding[7]; /* room for future expansion */
 232
 233         u64 io_bitmap_a;
 234         u64 io_bitmap_b;
 235         u64 msr_bitmap;
 236         u64 vm_exit_msr_store_addr;
 237         u64 vm_exit_msr_load_addr;
 238         u64 vm_entry_msr_load_addr;
 239         u64 tsc_offset;
 240         u64 virtual_apic_page_addr;
 241         u64 apic_access_addr;
 242         u64 posted_intr_desc_addr;
 243         u64 ept_pointer;
 244         u64 eoi_exit_bitmap0;
 245         u64 eoi_exit_bitmap1;
 246         u64 eoi_exit_bitmap2;
 247         u64 eoi_exit_bitmap3;
 248         u64 xss_exit_bitmap;
 249         u64 guest_physical_address;
 250         u64 vmcs_link_pointer;
 251         u64 pml_address;
 252         u64 guest_ia32_debugctl;
 253         u64 guest_ia32_pat;
 254         u64 guest_ia32_efer;
 255         u64 guest_ia32_perf_global_ctrl;
 256         u64 guest_pdptr0;
 257         u64 guest_pdptr1;
 258         u64 guest_pdptr2;
 259         u64 guest_pdptr3;
 260         u64 guest_bndcfgs;
 261         u64 host_ia32_pat;
 262         u64 host_ia32_efer;
 263         u64 host_ia32_perf_global_ctrl;
 264         u64 padding64[8]; /* room for future expansion */
 265         /*
 266          * To allow migration of L1 (complete with its L2 guests) between
 267          * machines of different natural widths (32 or 64 bit), we cannot have
 268          * unsigned long fields with no explict size. We use u64 (aliased
 269          * natural_width) instead. Luckily, x86 is little-endian.
 270          */
 271         natural_width cr0_guest_host_mask;
 272         natural_width cr4_guest_host_mask;
 273         natural_width cr0_read_shadow;
 274         natural_width cr4_read_shadow;
 275         natural_width cr3_target_value0;
 276         natural_width cr3_target_value1;
 277         natural_width cr3_target_value2;
 278         natural_width cr3_target_value3;
 279         natural_width exit_qualification;
 280         natural_width guest_linear_address;
 281         natural_width guest_cr0;
 282         natural_width guest_cr3;
 283         natural_width guest_cr4;
 284         natural_width guest_es_base;
 285         natural_width guest_cs_base;
 286         natural_width guest_ss_base;
 287         natural_width guest_ds_base;
 288         natural_width guest_fs_base;
 289         natural_width guest_gs_base;
 290         natural_width guest_ldtr_base;
 291         natural_width guest_tr_base;
 292         natural_width guest_gdtr_base;
 293         natural_width guest_idtr_base;
 294         natural_width guest_dr7;
 295         natural_width guest_rsp;
 296         natural_width guest_rip;
 297         natural_width guest_rflags;
 298         natural_width guest_pending_dbg_exceptions;
 299         natural_width guest_sysenter_esp;
 300         natural_width guest_sysenter_eip;
 301         natural_width host_cr0;
 302         natural_width host_cr3;
 303         natural_width host_cr4;
 304         natural_width host_fs_base;
 305         natural_width host_gs_base;
 306         natural_width host_tr_base;
 307         natural_width host_gdtr_base;
 308         natural_width host_idtr_base;
 309         natural_width host_ia32_sysenter_esp;
 310         natural_width host_ia32_sysenter_eip;
 311         natural_width host_rsp;
 312         natural_width host_rip;
 313         natural_width paddingl[8]; /* room for future expansion */
 314         u32 pin_based_vm_exec_control;
 315         u32 cpu_based_vm_exec_control;
 316         u32 exception_bitmap;
 317         u32 page_fault_error_code_mask;
 318         u32 page_fault_error_code_match;
 319         u32 cr3_target_count;
 320         u32 vm_exit_controls;
 321         u32 vm_exit_msr_store_count;
 322         u32 vm_exit_msr_load_count;
 323         u32 vm_entry_controls;
 324         u32 vm_entry_msr_load_count;
 325         u32 vm_entry_intr_info_field;
 326         u32 vm_entry_exception_error_code;
 327         u32 vm_entry_instruction_len;
 328         u32 tpr_threshold;
 329         u32 secondary_vm_exec_control;
 330         u32 vm_instruction_error;
 331         u32 vm_exit_reason;
 332         u32 vm_exit_intr_info;
 333         u32 vm_exit_intr_error_code;
 334         u32 idt_vectoring_info_field;
 335         u32 idt_vectoring_error_code;
 336         u32 vm_exit_instruction_len;
 337         u32 vmx_instruction_info;
 338         u32 guest_es_limit;
 339         u32 guest_cs_limit;
 340         u32 guest_ss_limit;
 341         u32 guest_ds_limit;
 342         u32 guest_fs_limit;
 343         u32 guest_gs_limit;
 344         u32 guest_ldtr_limit;
 345         u32 guest_tr_limit;
 346         u32 guest_gdtr_limit;
 347         u32 guest_idtr_limit;
 348         u32 guest_es_ar_bytes;
 349         u32 guest_cs_ar_bytes;
 350         u32 guest_ss_ar_bytes;
 351         u32 guest_ds_ar_bytes;
 352         u32 guest_fs_ar_bytes;
 353         u32 guest_gs_ar_bytes;
 354         u32 guest_ldtr_ar_bytes;
 355         u32 guest_tr_ar_bytes;
 356         u32 guest_interruptibility_info;
 357         u32 guest_activity_state;
 358         u32 guest_sysenter_cs;
 359         u32 host_ia32_sysenter_cs;
 360         u32 vmx_preemption_timer_value;
 361         u32 padding32[7]; /* room for future expansion */
 362         u16 virtual_processor_id;
 363         u16 posted_intr_nv;
 364         u16 guest_es_selector;
 365         u16 guest_cs_selector;
 366         u16 guest_ss_selector;
 367         u16 guest_ds_selector;
 368         u16 guest_fs_selector;
 369         u16 guest_gs_selector;
 370         u16 guest_ldtr_selector;
 371         u16 guest_tr_selector;
 372         u16 guest_intr_status;
 373         u16 guest_pml_index;
 374         u16 host_es_selector;
 375         u16 host_cs_selector;
 376         u16 host_ss_selector;
 377         u16 host_ds_selector;
 378         u16 host_fs_selector;
 379         u16 host_gs_selector;
 380         u16 host_tr_selector;
 381 };
 382
 383 /*
 384  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 385  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 386  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 387  */
 388 #define VMCS12_REVISION 0x11e57ed0
 389
 390 /*
 391  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 392  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 393  * current implementation, 4K are reserved to avoid future complications.
 394  */
 395 #define VMCS12_SIZE 0x1000
 396
 397 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 398 struct vmcs02_list {
 399         struct list_head list;
 400         gpa_t vmptr;
 401         struct loaded_vmcs vmcs02;
 402 };
 403
 404 /*
 405  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 406  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 407  */
 408 struct nested_vmx {
 409         /* Has the level1 guest done vmxon? */
 410         bool vmxon;
 411         gpa_t vmxon_ptr;
 412         bool pml_full;
 413
 414         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 415         gpa_t current_vmptr;
 416         /* The host-usable pointer to the above */
 417         struct page *current_vmcs12_page;
 418         struct vmcs12 *current_vmcs12;
 419         /*
 420          * Cache of the guest's VMCS, existing outside of guest memory.
 421          * Loaded from guest memory during VMPTRLD. Flushed to guest
 422          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 423          */
 424         struct vmcs12 *cached_vmcs12;
 425         /*
 426          * Indicates if the shadow vmcs must be updated with the
 427          * data hold by vmcs12
 428          */
 429         bool sync_shadow_vmcs;
 430
 431         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 432         struct list_head vmcs02_pool;
 433         int vmcs02_num;
 434         bool change_vmcs01_virtual_x2apic_mode;
 435         /* L2 must run next, and mustn't decide to exit to L1. */
 436         bool nested_run_pending;
 437         /*
 438          * Guest pages referred to in vmcs02 with host-physical pointers, so
 439          * we must keep them pinned while L2 runs.
 440          */
 441         struct page *apic_access_page;
 442         struct page *virtual_apic_page;
 443         struct page *pi_desc_page;
 444         struct pi_desc *pi_desc;
 445         bool pi_pending;
 446         u16 posted_intr_nv;
 447
 448         unsigned long *msr_bitmap;
 449
 450         struct hrtimer preemption_timer;
 451         bool preemption_timer_expired;
 452
 453         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 454         u64 vmcs01_debugctl;
 455
 456         u16 vpid02;
 457         u16 last_vpid;
 458
 459         /*
 460          * We only store the "true" versions of the VMX capability MSRs. We
 461          * generate the "non-true" versions by setting the must-be-1 bits
 462          * according to the SDM.
 463          */
 464         u32 nested_vmx_procbased_ctls_low;
 465         u32 nested_vmx_procbased_ctls_high;
 466         u32 nested_vmx_secondary_ctls_low;
 467         u32 nested_vmx_secondary_ctls_high;
 468         u32 nested_vmx_pinbased_ctls_low;
 469         u32 nested_vmx_pinbased_ctls_high;
 470         u32 nested_vmx_exit_ctls_low;
 471         u32 nested_vmx_exit_ctls_high;
 472         u32 nested_vmx_entry_ctls_low;
 473         u32 nested_vmx_entry_ctls_high;
 474         u32 nested_vmx_misc_low;
 475         u32 nested_vmx_misc_high;
 476         u32 nested_vmx_ept_caps;
 477         u32 nested_vmx_vpid_caps;
 478         u64 nested_vmx_basic;
 479         u64 nested_vmx_cr0_fixed0;
 480         u64 nested_vmx_cr0_fixed1;
 481         u64 nested_vmx_cr4_fixed0;
 482         u64 nested_vmx_cr4_fixed1;
 483         u64 nested_vmx_vmcs_enum;
 484 };
 485
 486 #define POSTED_INTR_ON  0
 487 #define POSTED_INTR_SN  1
 488
 489 /* Posted-Interrupt Descriptor */
 490 struct pi_desc {
 491         u32 pir[8];     /* Posted interrupt requested */
 492         union {
 493                 struct {
 494                                 /* bit 256 - Outstanding Notification */
 495                         u16     on      : 1,
 496                                 /* bit 257 - Suppress Notification */
 497                                 sn      : 1,
 498                                 /* bit 271:258 - Reserved */
 499                                 rsvd_1  : 14;
 500                                 /* bit 279:272 - Notification Vector */
 501                         u8      nv;
 502                                 /* bit 287:280 - Reserved */
 503                         u8      rsvd_2;
 504                                 /* bit 319:288 - Notification Destination */
 505                         u32     ndst;
 506                 };
 507                 u64 control;
 508         };
 509         u32 rsvd[6];
 510 } __aligned(64);
 511
 512 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 513 {
 514         return test_and_set_bit(POSTED_INTR_ON,
 515                         (unsigned long *)&pi_desc->control);
 516 }
 517
 518 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 519 {
 520         return test_and_clear_bit(POSTED_INTR_ON,
 521                         (unsigned long *)&pi_desc->control);
 522 }
 523
 524 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 525 {
 526         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 527 }
 528
 529 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 530 {
 531         return clear_bit(POSTED_INTR_SN,
 532                         (unsigned long *)&pi_desc->control);
 533 }
 534
 535 static inline void pi_set_sn(struct pi_desc *pi_desc)
 536 {
 537         return set_bit(POSTED_INTR_SN,
 538                         (unsigned long *)&pi_desc->control);
 539 }
 540
 541 static inline void pi_clear_on(struct pi_desc *pi_desc)
 542 {
 543         clear_bit(POSTED_INTR_ON,
 544                   (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static inline int pi_test_on(struct pi_desc *pi_desc)
 548 {
 549         return test_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static inline int pi_test_sn(struct pi_desc *pi_desc)
 554 {
 555         return test_bit(POSTED_INTR_SN,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 struct vcpu_vmx {
 560         struct kvm_vcpu       vcpu;
 561         unsigned long         host_rsp;
 562         u8                    fail;
 563         bool                  nmi_known_unmasked;
 564         u32                   exit_intr_info;
 565         u32                   idt_vectoring_info;
 566         ulong                 rflags;
 567         struct shared_msr_entry *guest_msrs;
 568         int                   nmsrs;
 569         int                   save_nmsrs;
 570         unsigned long         host_idt_base;
 571 #ifdef CONFIG_X86_64
 572         u64                   msr_host_kernel_gs_base;
 573         u64                   msr_guest_kernel_gs_base;
 574 #endif
 575         u32 vm_entry_controls_shadow;
 576         u32 vm_exit_controls_shadow;
 577         /*
 578          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 579          * non-nested (L1) guest, it always points to vmcs01. For a nested
 580          * guest (L2), it points to a different VMCS.
 581          */
 582         struct loaded_vmcs    vmcs01;
 583         struct loaded_vmcs   *loaded_vmcs;
 584         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 585         struct msr_autoload {
 586                 unsigned nr;
 587                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 588                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 589         } msr_autoload;
 590         struct {
 591                 int           loaded;
 592                 u16           fs_sel, gs_sel, ldt_sel;
 593 #ifdef CONFIG_X86_64
 594                 u16           ds_sel, es_sel;
 595 #endif
 596                 int           gs_ldt_reload_needed;
 597                 int           fs_reload_needed;
 598                 u64           msr_host_bndcfgs;
 599                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 600         } host_state;
 601         struct {
 602                 int vm86_active;
 603                 ulong save_rflags;
 604                 struct kvm_segment segs[8];
 605         } rmode;
 606         struct {
 607                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 608                 struct kvm_save_segment {
 609                         u16 selector;
 610                         unsigned long base;
 611                         u32 limit;
 612                         u32 ar;
 613                 } seg[8];
 614         } segment_cache;
 615         int vpid;
 616         bool emulation_required;
 617
 618         u32 exit_reason;
 619
 620         /* Posted interrupt descriptor */
 621         struct pi_desc pi_desc;
 622
 623         /* Support for a guest hypervisor (nested VMX) */
 624         struct nested_vmx nested;
 625
 626         /* Dynamic PLE window. */
 627         int ple_window;
 628         bool ple_window_dirty;
 629
 630         /* Support for PML */
 631 #define PML_ENTITY_NUM          512
 632         struct page *pml_pg;
 633
 634         /* apic deadline value in host tsc */
 635         u64 hv_deadline_tsc;
 636
 637         u64 current_tsc_ratio;
 638
 639         bool guest_pkru_valid;
 640         u32 guest_pkru;
 641         u32 host_pkru;
 642
 643         /*
 644          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 645          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 646          * in msr_ia32_feature_control_valid_bits.
 647          */
 648         u64 msr_ia32_feature_control;
 649         u64 msr_ia32_feature_control_valid_bits;
 650 };
 651
 652 enum segment_cache_field {
 653         SEG_FIELD_SEL = 0,
 654         SEG_FIELD_BASE = 1,
 655         SEG_FIELD_LIMIT = 2,
 656         SEG_FIELD_AR = 3,
 657
 658         SEG_FIELD_NR = 4
 659 };
 660
 661 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 662 {
 663         return container_of(vcpu, struct vcpu_vmx, vcpu);
 664 }
 665
 666 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 667 {
 668         return &(to_vmx(vcpu)->pi_desc);
 669 }
 670
 671 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 672 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 673 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 674                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 675
 676
 677 static unsigned long shadow_read_only_fields[] = {
 678         /*
 679          * We do NOT shadow fields that are modified when L0
 680          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 681          * VMXON...) executed by L1.
 682          * For example, VM_INSTRUCTION_ERROR is read
 683          * by L1 if a vmx instruction fails (part of the error path).
 684          * Note the code assumes this logic. If for some reason
 685          * we start shadowing these fields then we need to
 686          * force a shadow sync when L0 emulates vmx instructions
 687          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 688          * by nested_vmx_failValid)
 689          */
 690         VM_EXIT_REASON,
 691         VM_EXIT_INTR_INFO,
 692         VM_EXIT_INSTRUCTION_LEN,
 693         IDT_VECTORING_INFO_FIELD,
 694         IDT_VECTORING_ERROR_CODE,
 695         VM_EXIT_INTR_ERROR_CODE,
 696         EXIT_QUALIFICATION,
 697         GUEST_LINEAR_ADDRESS,
 698         GUEST_PHYSICAL_ADDRESS
 699 };
 700 static int max_shadow_read_only_fields =
 701         ARRAY_SIZE(shadow_read_only_fields);
 702
 703 static unsigned long shadow_read_write_fields[] = {
 704         TPR_THRESHOLD,
 705         GUEST_RIP,
 706         GUEST_RSP,
 707         GUEST_CR0,
 708         GUEST_CR3,
 709         GUEST_CR4,
 710         GUEST_INTERRUPTIBILITY_INFO,
 711         GUEST_RFLAGS,
 712         GUEST_CS_SELECTOR,
 713         GUEST_CS_AR_BYTES,
 714         GUEST_CS_LIMIT,
 715         GUEST_CS_BASE,
 716         GUEST_ES_BASE,
 717         GUEST_BNDCFGS,
 718         CR0_GUEST_HOST_MASK,
 719         CR0_READ_SHADOW,
 720         CR4_READ_SHADOW,
 721         TSC_OFFSET,
 722         EXCEPTION_BITMAP,
 723         CPU_BASED_VM_EXEC_CONTROL,
 724         VM_ENTRY_EXCEPTION_ERROR_CODE,
 725         VM_ENTRY_INTR_INFO_FIELD,
 726         VM_ENTRY_INSTRUCTION_LEN,
 727         VM_ENTRY_EXCEPTION_ERROR_CODE,
 728         HOST_FS_BASE,
 729         HOST_GS_BASE,
 730         HOST_FS_SELECTOR,
 731         HOST_GS_SELECTOR
 732 };
 733 static int max_shadow_read_write_fields =
 734         ARRAY_SIZE(shadow_read_write_fields);
 735
 736 static const unsigned short vmcs_field_to_offset_table[] = {
 737         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 738         FIELD(POSTED_INTR_NV, posted_intr_nv),
 739         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 740         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 741         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 742         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 743         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 744         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 745         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 746         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 747         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 748         FIELD(GUEST_PML_INDEX, guest_pml_index),
 749         FIELD(HOST_ES_SELECTOR, host_es_selector),
 750         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 751         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 752         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 753         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 754         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 755         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 756         FIELD64(IO_BITMAP_A, io_bitmap_a),
 757         FIELD64(IO_BITMAP_B, io_bitmap_b),
 758         FIELD64(MSR_BITMAP, msr_bitmap),
 759         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 760         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 761         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 762         FIELD64(TSC_OFFSET, tsc_offset),
 763         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 764         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 765         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 766         FIELD64(EPT_POINTER, ept_pointer),
 767         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 768         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 769         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 770         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 771         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 772         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 773         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 774         FIELD64(PML_ADDRESS, pml_address),
 775         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 776         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 777         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 778         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 779         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 780         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 781         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 782         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 783         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 784         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 785         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 786         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 787         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 788         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 789         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 790         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 791         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 792         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 793         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 794         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 795         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 796         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 797         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 798         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 799         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 800         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 801         FIELD(TPR_THRESHOLD, tpr_threshold),
 802         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 803         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 804         FIELD(VM_EXIT_REASON, vm_exit_reason),
 805         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 806         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 807         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 808         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 809         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 810         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 811         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 812         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 813         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 814         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 815         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 816         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 817         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 818         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 819         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 820         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 821         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 822         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 823         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 824         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 825         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 826         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 827         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 828         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 829         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 830         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 831         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 832         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 833         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 834         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 835         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 836         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 837         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 838         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 839         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 840         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 841         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 842         FIELD(EXIT_QUALIFICATION, exit_qualification),
 843         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 844         FIELD(GUEST_CR0, guest_cr0),
 845         FIELD(GUEST_CR3, guest_cr3),
 846         FIELD(GUEST_CR4, guest_cr4),
 847         FIELD(GUEST_ES_BASE, guest_es_base),
 848         FIELD(GUEST_CS_BASE, guest_cs_base),
 849         FIELD(GUEST_SS_BASE, guest_ss_base),
 850         FIELD(GUEST_DS_BASE, guest_ds_base),
 851         FIELD(GUEST_FS_BASE, guest_fs_base),
 852         FIELD(GUEST_GS_BASE, guest_gs_base),
 853         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 854         FIELD(GUEST_TR_BASE, guest_tr_base),
 855         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 856         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 857         FIELD(GUEST_DR7, guest_dr7),
 858         FIELD(GUEST_RSP, guest_rsp),
 859         FIELD(GUEST_RIP, guest_rip),
 860         FIELD(GUEST_RFLAGS, guest_rflags),
 861         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 862         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 863         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 864         FIELD(HOST_CR0, host_cr0),
 865         FIELD(HOST_CR3, host_cr3),
 866         FIELD(HOST_CR4, host_cr4),
 867         FIELD(HOST_FS_BASE, host_fs_base),
 868         FIELD(HOST_GS_BASE, host_gs_base),
 869         FIELD(HOST_TR_BASE, host_tr_base),
 870         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 871         FIELD(HOST_IDTR_BASE, host_idtr_base),
 872         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 873         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 874         FIELD(HOST_RSP, host_rsp),
 875         FIELD(HOST_RIP, host_rip),
 876 };
 877
 878 static inline short vmcs_field_to_offset(unsigned long field)
 879 {
 880         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 881
 882         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 883             vmcs_field_to_offset_table[field] == 0)
 884                 return -ENOENT;
 885
 886         return vmcs_field_to_offset_table[field];
 887 }
 888
 889 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 890 {
 891         return to_vmx(vcpu)->nested.cached_vmcs12;
 892 }
 893
 894 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 895 {
 896         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 897         if (is_error_page(page))
 898                 return NULL;
 899
 900         return page;
 901 }
 902
 903 static void nested_release_page(struct page *page)
 904 {
 905         kvm_release_page_dirty(page);
 906 }
 907
 908 static void nested_release_page_clean(struct page *page)
 909 {
 910         kvm_release_page_clean(page);
 911 }
 912
 913 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 914 static u64 construct_eptp(unsigned long root_hpa);
 915 static bool vmx_xsaves_supported(void);
 916 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 917 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 918                             struct kvm_segment *var, int seg);
 919 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 920                             struct kvm_segment *var, int seg);
 921 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 922 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 923 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 924 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 925 static int alloc_identity_pagetable(struct kvm *kvm);
 926
 927 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 928 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 929 /*
 930  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 931  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 932  */
 933 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 934
 935 /*
 936  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 937  * can find which vCPU should be waken up.
 938  */
 939 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 940 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 941
 942 enum {
 943         VMX_IO_BITMAP_A,
 944         VMX_IO_BITMAP_B,
 945         VMX_MSR_BITMAP_LEGACY,
 946         VMX_MSR_BITMAP_LONGMODE,
 947         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 948         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 949         VMX_MSR_BITMAP_LEGACY_X2APIC,
 950         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 951         VMX_VMREAD_BITMAP,
 952         VMX_VMWRITE_BITMAP,
 953         VMX_BITMAP_NR
 954 };
 955
 956 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 957
 958 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 959 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 960 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 961 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 962 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 963 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 964 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 965 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 966 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 967 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 968
 969 static bool cpu_has_load_ia32_efer;
 970 static bool cpu_has_load_perf_global_ctrl;
 971
 972 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 973 static DEFINE_SPINLOCK(vmx_vpid_lock);
 974
 975 static struct vmcs_config {
 976         int size;
 977         int order;
 978         u32 basic_cap;
 979         u32 revision_id;
 980         u32 pin_based_exec_ctrl;
 981         u32 cpu_based_exec_ctrl;
 982         u32 cpu_based_2nd_exec_ctrl;
 983         u32 vmexit_ctrl;
 984         u32 vmentry_ctrl;
 985 } vmcs_config;
 986
 987 static struct vmx_capability {
 988         u32 ept;
 989         u32 vpid;
 990 } vmx_capability;
 991
 992 #define VMX_SEGMENT_FIELD(seg)                                  \
 993         [VCPU_SREG_##seg] = {                                   \
 994                 .selector = GUEST_##seg##_SELECTOR,             \
 995                 .base = GUEST_##seg##_BASE,                     \
 996                 .limit = GUEST_##seg##_LIMIT,                   \
 997                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 998         }
 999
1000 static const struct kvm_vmx_segment_field {
1001         unsigned selector;
1002         unsigned base;
1003         unsigned limit;
1004         unsigned ar_bytes;
1005 } kvm_vmx_segment_fields[] = {
1006         VMX_SEGMENT_FIELD(CS),
1007         VMX_SEGMENT_FIELD(DS),
1008         VMX_SEGMENT_FIELD(ES),
1009         VMX_SEGMENT_FIELD(FS),
1010         VMX_SEGMENT_FIELD(GS),
1011         VMX_SEGMENT_FIELD(SS),
1012         VMX_SEGMENT_FIELD(TR),
1013         VMX_SEGMENT_FIELD(LDTR),
1014 };
1015
1016 static u64 host_efer;
1017
1018 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1019
1020 /*
1021  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1022  * away by decrementing the array size.
1023  */
1024 static const u32 vmx_msr_index[] = {
1025 #ifdef CONFIG_X86_64
1026         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1027 #endif
1028         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1029 };
1030
1031 static inline bool is_exception_n(u32 intr_info, u8 vector)
1032 {
1033         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1034                              INTR_INFO_VALID_MASK)) ==
1035                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1036 }
1037
1038 static inline bool is_debug(u32 intr_info)
1039 {
1040         return is_exception_n(intr_info, DB_VECTOR);
1041 }
1042
1043 static inline bool is_breakpoint(u32 intr_info)
1044 {
1045         return is_exception_n(intr_info, BP_VECTOR);
1046 }
1047
1048 static inline bool is_page_fault(u32 intr_info)
1049 {
1050         return is_exception_n(intr_info, PF_VECTOR);
1051 }
1052
1053 static inline bool is_no_device(u32 intr_info)
1054 {
1055         return is_exception_n(intr_info, NM_VECTOR);
1056 }
1057
1058 static inline bool is_invalid_opcode(u32 intr_info)
1059 {
1060         return is_exception_n(intr_info, UD_VECTOR);
1061 }
1062
1063 static inline bool is_external_interrupt(u32 intr_info)
1064 {
1065         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1066                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1067 }
1068
1069 static inline bool is_machine_check(u32 intr_info)
1070 {
1071         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1072                              INTR_INFO_VALID_MASK)) ==
1073                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1074 }
1075
1076 static inline bool cpu_has_vmx_msr_bitmap(void)
1077 {
1078         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1079 }
1080
1081 static inline bool cpu_has_vmx_tpr_shadow(void)
1082 {
1083         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1084 }
1085
1086 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1087 {
1088         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1089 }
1090
1091 static inline bool cpu_has_secondary_exec_ctrls(void)
1092 {
1093         return vmcs_config.cpu_based_exec_ctrl &
1094                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1095 }
1096
1097 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1098 {
1099         return vmcs_config.cpu_based_2nd_exec_ctrl &
1100                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1101 }
1102
1103 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1104 {
1105         return vmcs_config.cpu_based_2nd_exec_ctrl &
1106                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1107 }
1108
1109 static inline bool cpu_has_vmx_apic_register_virt(void)
1110 {
1111         return vmcs_config.cpu_based_2nd_exec_ctrl &
1112                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1113 }
1114
1115 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1116 {
1117         return vmcs_config.cpu_based_2nd_exec_ctrl &
1118                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1119 }
1120
1121 /*
1122  * Comment's format: document - errata name - stepping - processor name.
1123  * Refer from
1124  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1125  */
1126 static u32 vmx_preemption_cpu_tfms[] = {
1127 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1128 0x000206E6,
1129 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1130 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1131 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1132 0x00020652,
1133 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1134 0x00020655,
1135 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1136 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1137 /*
1138  * 320767.pdf - AAP86  - B1 -
1139  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1140  */
1141 0x000106E5,
1142 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1143 0x000106A0,
1144 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1145 0x000106A1,
1146 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1147 0x000106A4,
1148  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1149  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1150  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1151 0x000106A5,
1152 };
1153
1154 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1155 {
1156         u32 eax = cpuid_eax(0x00000001), i;
1157
1158         /* Clear the reserved bits */
1159         eax &= ~(0x3U << 14 | 0xfU << 28);
1160         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1161                 if (eax == vmx_preemption_cpu_tfms[i])
1162                         return true;
1163
1164         return false;
1165 }
1166
1167 static inline bool cpu_has_vmx_preemption_timer(void)
1168 {
1169         return vmcs_config.pin_based_exec_ctrl &
1170                 PIN_BASED_VMX_PREEMPTION_TIMER;
1171 }
1172
1173 static inline bool cpu_has_vmx_posted_intr(void)
1174 {
1175         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1176                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1177 }
1178
1179 static inline bool cpu_has_vmx_apicv(void)
1180 {
1181         return cpu_has_vmx_apic_register_virt() &&
1182                 cpu_has_vmx_virtual_intr_delivery() &&
1183                 cpu_has_vmx_posted_intr();
1184 }
1185
1186 static inline bool cpu_has_vmx_flexpriority(void)
1187 {
1188         return cpu_has_vmx_tpr_shadow() &&
1189                 cpu_has_vmx_virtualize_apic_accesses();
1190 }
1191
1192 static inline bool cpu_has_vmx_ept_execute_only(void)
1193 {
1194         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1195 }
1196
1197 static inline bool cpu_has_vmx_ept_2m_page(void)
1198 {
1199         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1200 }
1201
1202 static inline bool cpu_has_vmx_ept_1g_page(void)
1203 {
1204         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1205 }
1206
1207 static inline bool cpu_has_vmx_ept_4levels(void)
1208 {
1209         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1210 }
1211
1212 static inline bool cpu_has_vmx_ept_ad_bits(void)
1213 {
1214         return vmx_capability.ept & VMX_EPT_AD_BIT;
1215 }
1216
1217 static inline bool cpu_has_vmx_invept_context(void)
1218 {
1219         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1220 }
1221
1222 static inline bool cpu_has_vmx_invept_global(void)
1223 {
1224         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1225 }
1226
1227 static inline bool cpu_has_vmx_invvpid_single(void)
1228 {
1229         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1230 }
1231
1232 static inline bool cpu_has_vmx_invvpid_global(void)
1233 {
1234         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1235 }
1236
1237 static inline bool cpu_has_vmx_invvpid(void)
1238 {
1239         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1240 }
1241
1242 static inline bool cpu_has_vmx_ept(void)
1243 {
1244         return vmcs_config.cpu_based_2nd_exec_ctrl &
1245                 SECONDARY_EXEC_ENABLE_EPT;
1246 }
1247
1248 static inline bool cpu_has_vmx_unrestricted_guest(void)
1249 {
1250         return vmcs_config.cpu_based_2nd_exec_ctrl &
1251                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1252 }
1253
1254 static inline bool cpu_has_vmx_ple(void)
1255 {
1256         return vmcs_config.cpu_based_2nd_exec_ctrl &
1257                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1258 }
1259
1260 static inline bool cpu_has_vmx_basic_inout(void)
1261 {
1262         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1263 }
1264
1265 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1266 {
1267         return flexpriority_enabled && lapic_in_kernel(vcpu);
1268 }
1269
1270 static inline bool cpu_has_vmx_vpid(void)
1271 {
1272         return vmcs_config.cpu_based_2nd_exec_ctrl &
1273                 SECONDARY_EXEC_ENABLE_VPID;
1274 }
1275
1276 static inline bool cpu_has_vmx_rdtscp(void)
1277 {
1278         return vmcs_config.cpu_based_2nd_exec_ctrl &
1279                 SECONDARY_EXEC_RDTSCP;
1280 }
1281
1282 static inline bool cpu_has_vmx_invpcid(void)
1283 {
1284         return vmcs_config.cpu_based_2nd_exec_ctrl &
1285                 SECONDARY_EXEC_ENABLE_INVPCID;
1286 }
1287
1288 static inline bool cpu_has_vmx_wbinvd_exit(void)
1289 {
1290         return vmcs_config.cpu_based_2nd_exec_ctrl &
1291                 SECONDARY_EXEC_WBINVD_EXITING;
1292 }
1293
1294 static inline bool cpu_has_vmx_shadow_vmcs(void)
1295 {
1296         u64 vmx_msr;
1297         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1298         /* check if the cpu supports writing r/o exit information fields */
1299         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1300                 return false;
1301
1302         return vmcs_config.cpu_based_2nd_exec_ctrl &
1303                 SECONDARY_EXEC_SHADOW_VMCS;
1304 }
1305
1306 static inline bool cpu_has_vmx_pml(void)
1307 {
1308         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1309 }
1310
1311 static inline bool cpu_has_vmx_tsc_scaling(void)
1312 {
1313         return vmcs_config.cpu_based_2nd_exec_ctrl &
1314                 SECONDARY_EXEC_TSC_SCALING;
1315 }
1316
1317 static inline bool report_flexpriority(void)
1318 {
1319         return flexpriority_enabled;
1320 }
1321
1322 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1323 {
1324         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1325 }
1326
1327 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1328 {
1329         return vmcs12->cpu_based_vm_exec_control & bit;
1330 }
1331
1332 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1333 {
1334         return (vmcs12->cpu_based_vm_exec_control &
1335                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1336                 (vmcs12->secondary_vm_exec_control & bit);
1337 }
1338
1339 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1340 {
1341         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1342 }
1343
1344 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1345 {
1346         return vmcs12->pin_based_vm_exec_control &
1347                 PIN_BASED_VMX_PREEMPTION_TIMER;
1348 }
1349
1350 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1351 {
1352         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1353 }
1354
1355 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1356 {
1357         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1358                 vmx_xsaves_supported();
1359 }
1360
1361 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1362 {
1363         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1364 }
1365
1366 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1367 {
1368         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1369 }
1370
1371 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1372 {
1373         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1374 }
1375
1376 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1377 {
1378         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1379 }
1380
1381 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1382 {
1383         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1384 }
1385
1386 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1387 {
1388         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1389 }
1390
1391 static inline bool is_nmi(u32 intr_info)
1392 {
1393         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1394                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1395 }
1396
1397 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1398                               u32 exit_intr_info,
1399                               unsigned long exit_qualification);
1400 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1401                         struct vmcs12 *vmcs12,
1402                         u32 reason, unsigned long qualification);
1403
1404 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1405 {
1406         int i;
1407
1408         for (i = 0; i < vmx->nmsrs; ++i)
1409                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1410                         return i;
1411         return -1;
1412 }
1413
1414 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1415 {
1416     struct {
1417         u64 vpid : 16;
1418         u64 rsvd : 48;
1419         u64 gva;
1420     } operand = { vpid, 0, gva };
1421
1422     asm volatile (__ex(ASM_VMX_INVVPID)
1423                   /* CF==1 or ZF==1 --> rc = -1 */
1424                   "; ja 1f ; ud2 ; 1:"
1425                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1426 }
1427
1428 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1429 {
1430         struct {
1431                 u64 eptp, gpa;
1432         } operand = {eptp, gpa};
1433
1434         asm volatile (__ex(ASM_VMX_INVEPT)
1435                         /* CF==1 or ZF==1 --> rc = -1 */
1436                         "; ja 1f ; ud2 ; 1:\n"
1437                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1438 }
1439
1440 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1441 {
1442         int i;
1443
1444         i = __find_msr_index(vmx, msr);
1445         if (i >= 0)
1446                 return &vmx->guest_msrs[i];
1447         return NULL;
1448 }
1449
1450 static void vmcs_clear(struct vmcs *vmcs)
1451 {
1452         u64 phys_addr = __pa(vmcs);
1453         u8 error;
1454
1455         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1456                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1457                       : "cc", "memory");
1458         if (error)
1459                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1460                        vmcs, phys_addr);
1461 }
1462
1463 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1464 {
1465         vmcs_clear(loaded_vmcs->vmcs);
1466         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1467                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1468         loaded_vmcs->cpu = -1;
1469         loaded_vmcs->launched = 0;
1470 }
1471
1472 static void vmcs_load(struct vmcs *vmcs)
1473 {
1474         u64 phys_addr = __pa(vmcs);
1475         u8 error;
1476
1477         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1478                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1479                         : "cc", "memory");
1480         if (error)
1481                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1482                        vmcs, phys_addr);
1483 }
1484
1485 #ifdef CONFIG_KEXEC_CORE
1486 /*
1487  * This bitmap is used to indicate whether the vmclear
1488  * operation is enabled on all cpus. All disabled by
1489  * default.
1490  */
1491 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1492
1493 static inline void crash_enable_local_vmclear(int cpu)
1494 {
1495         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1496 }
1497
1498 static inline void crash_disable_local_vmclear(int cpu)
1499 {
1500         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1501 }
1502
1503 static inline int crash_local_vmclear_enabled(int cpu)
1504 {
1505         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1506 }
1507
1508 static void crash_vmclear_local_loaded_vmcss(void)
1509 {
1510         int cpu = raw_smp_processor_id();
1511         struct loaded_vmcs *v;
1512
1513         if (!crash_local_vmclear_enabled(cpu))
1514                 return;
1515
1516         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1517                             loaded_vmcss_on_cpu_link)
1518                 vmcs_clear(v->vmcs);
1519 }
1520 #else
1521 static inline void crash_enable_local_vmclear(int cpu) { }
1522 static inline void crash_disable_local_vmclear(int cpu) { }
1523 #endif /* CONFIG_KEXEC_CORE */
1524
1525 static void __loaded_vmcs_clear(void *arg)
1526 {
1527         struct loaded_vmcs *loaded_vmcs = arg;
1528         int cpu = raw_smp_processor_id();
1529
1530         if (loaded_vmcs->cpu != cpu)
1531                 return; /* vcpu migration can race with cpu offline */
1532         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1533                 per_cpu(current_vmcs, cpu) = NULL;
1534         crash_disable_local_vmclear(cpu);
1535         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1536
1537         /*
1538          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1539          * is before setting loaded_vmcs->vcpu to -1 which is done in
1540          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1541          * then adds the vmcs into percpu list before it is deleted.
1542          */
1543         smp_wmb();
1544
1545         loaded_vmcs_init(loaded_vmcs);
1546         crash_enable_local_vmclear(cpu);
1547 }
1548
1549 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1550 {
1551         int cpu = loaded_vmcs->cpu;
1552
1553         if (cpu != -1)
1554                 smp_call_function_single(cpu,
1555                          __loaded_vmcs_clear, loaded_vmcs, 1);
1556 }
1557
1558 static inline void vpid_sync_vcpu_single(int vpid)
1559 {
1560         if (vpid == 0)
1561                 return;
1562
1563         if (cpu_has_vmx_invvpid_single())
1564                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1565 }
1566
1567 static inline void vpid_sync_vcpu_global(void)
1568 {
1569         if (cpu_has_vmx_invvpid_global())
1570                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1571 }
1572
1573 static inline void vpid_sync_context(int vpid)
1574 {
1575         if (cpu_has_vmx_invvpid_single())
1576                 vpid_sync_vcpu_single(vpid);
1577         else
1578                 vpid_sync_vcpu_global();
1579 }
1580
1581 static inline void ept_sync_global(void)
1582 {
1583         if (cpu_has_vmx_invept_global())
1584                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1585 }
1586
1587 static inline void ept_sync_context(u64 eptp)
1588 {
1589         if (enable_ept) {
1590                 if (cpu_has_vmx_invept_context())
1591                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1592                 else
1593                         ept_sync_global();
1594         }
1595 }
1596
1597 static __always_inline void vmcs_check16(unsigned long field)
1598 {
1599         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1600                          "16-bit accessor invalid for 64-bit field");
1601         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1602                          "16-bit accessor invalid for 64-bit high field");
1603         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1604                          "16-bit accessor invalid for 32-bit high field");
1605         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1606                          "16-bit accessor invalid for natural width field");
1607 }
1608
1609 static __always_inline void vmcs_check32(unsigned long field)
1610 {
1611         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1612                          "32-bit accessor invalid for 16-bit field");
1613         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1614                          "32-bit accessor invalid for natural width field");
1615 }
1616
1617 static __always_inline void vmcs_check64(unsigned long field)
1618 {
1619         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1620                          "64-bit accessor invalid for 16-bit field");
1621         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1622                          "64-bit accessor invalid for 64-bit high field");
1623         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1624                          "64-bit accessor invalid for 32-bit field");
1625         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1626                          "64-bit accessor invalid for natural width field");
1627 }
1628
1629 static __always_inline void vmcs_checkl(unsigned long field)
1630 {
1631         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1632                          "Natural width accessor invalid for 16-bit field");
1633         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1634                          "Natural width accessor invalid for 64-bit field");
1635         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1636                          "Natural width accessor invalid for 64-bit high field");
1637         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1638                          "Natural width accessor invalid for 32-bit field");
1639 }
1640
1641 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1642 {
1643         unsigned long value;
1644
1645         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1646                       : "=a"(value) : "d"(field) : "cc");
1647         return value;
1648 }
1649
1650 static __always_inline u16 vmcs_read16(unsigned long field)
1651 {
1652         vmcs_check16(field);
1653         return __vmcs_readl(field);
1654 }
1655
1656 static __always_inline u32 vmcs_read32(unsigned long field)
1657 {
1658         vmcs_check32(field);
1659         return __vmcs_readl(field);
1660 }
1661
1662 static __always_inline u64 vmcs_read64(unsigned long field)
1663 {
1664         vmcs_check64(field);
1665 #ifdef CONFIG_X86_64
1666         return __vmcs_readl(field);
1667 #else
1668         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1669 #endif
1670 }
1671
1672 static __always_inline unsigned long vmcs_readl(unsigned long field)
1673 {
1674         vmcs_checkl(field);
1675         return __vmcs_readl(field);
1676 }
1677
1678 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1679 {
1680         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1681                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1682         dump_stack();
1683 }
1684
1685 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1686 {
1687         u8 error;
1688
1689         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1690                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1691         if (unlikely(error))
1692                 vmwrite_error(field, value);
1693 }
1694
1695 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1696 {
1697         vmcs_check16(field);
1698         __vmcs_writel(field, value);
1699 }
1700
1701 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1702 {
1703         vmcs_check32(field);
1704         __vmcs_writel(field, value);
1705 }
1706
1707 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1708 {
1709         vmcs_check64(field);
1710         __vmcs_writel(field, value);
1711 #ifndef CONFIG_X86_64
1712         asm volatile ("");
1713         __vmcs_writel(field+1, value >> 32);
1714 #endif
1715 }
1716
1717 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1718 {
1719         vmcs_checkl(field);
1720         __vmcs_writel(field, value);
1721 }
1722
1723 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1724 {
1725         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1726                          "vmcs_clear_bits does not support 64-bit fields");
1727         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1728 }
1729
1730 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1731 {
1732         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1733                          "vmcs_set_bits does not support 64-bit fields");
1734         __vmcs_writel(field, __vmcs_readl(field) | mask);
1735 }
1736
1737 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1738 {
1739         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1740 }
1741
1742 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1743 {
1744         vmcs_write32(VM_ENTRY_CONTROLS, val);
1745         vmx->vm_entry_controls_shadow = val;
1746 }
1747
1748 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1749 {
1750         if (vmx->vm_entry_controls_shadow != val)
1751                 vm_entry_controls_init(vmx, val);
1752 }
1753
1754 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1755 {
1756         return vmx->vm_entry_controls_shadow;
1757 }
1758
1759
1760 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1761 {
1762         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1763 }
1764
1765 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1766 {
1767         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1768 }
1769
1770 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1771 {
1772         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1773 }
1774
1775 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1776 {
1777         vmcs_write32(VM_EXIT_CONTROLS, val);
1778         vmx->vm_exit_controls_shadow = val;
1779 }
1780
1781 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1782 {
1783         if (vmx->vm_exit_controls_shadow != val)
1784                 vm_exit_controls_init(vmx, val);
1785 }
1786
1787 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1788 {
1789         return vmx->vm_exit_controls_shadow;
1790 }
1791
1792
1793 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1794 {
1795         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1796 }
1797
1798 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1799 {
1800         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1801 }
1802
1803 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1804 {
1805         vmx->segment_cache.bitmask = 0;
1806 }
1807
1808 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1809                                        unsigned field)
1810 {
1811         bool ret;
1812         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1813
1814         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1815                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1816                 vmx->segment_cache.bitmask = 0;
1817         }
1818         ret = vmx->segment_cache.bitmask & mask;
1819         vmx->segment_cache.bitmask |= mask;
1820         return ret;
1821 }
1822
1823 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1824 {
1825         u16 *p = &vmx->segment_cache.seg[seg].selector;
1826
1827         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1828                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1829         return *p;
1830 }
1831
1832 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1833 {
1834         ulong *p = &vmx->segment_cache.seg[seg].base;
1835
1836         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1837                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1838         return *p;
1839 }
1840
1841 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1842 {
1843         u32 *p = &vmx->segment_cache.seg[seg].limit;
1844
1845         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1846                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1847         return *p;
1848 }
1849
1850 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1851 {
1852         u32 *p = &vmx->segment_cache.seg[seg].ar;
1853
1854         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1855                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1856         return *p;
1857 }
1858
1859 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1860 {
1861         u32 eb;
1862
1863         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1864              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1865         if ((vcpu->guest_debug &
1866              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1867             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1868                 eb |= 1u << BP_VECTOR;
1869         if (to_vmx(vcpu)->rmode.vm86_active)
1870                 eb = ~0;
1871         if (enable_ept)
1872                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1873
1874         /* When we are running a nested L2 guest and L1 specified for it a
1875          * certain exception bitmap, we must trap the same exceptions and pass
1876          * them to L1. When running L2, we will only handle the exceptions
1877          * specified above if L1 did not want them.
1878          */
1879         if (is_guest_mode(vcpu))
1880                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1881
1882         vmcs_write32(EXCEPTION_BITMAP, eb);
1883 }
1884
1885 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1886                 unsigned long entry, unsigned long exit)
1887 {
1888         vm_entry_controls_clearbit(vmx, entry);
1889         vm_exit_controls_clearbit(vmx, exit);
1890 }
1891
1892 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1893 {
1894         unsigned i;
1895         struct msr_autoload *m = &vmx->msr_autoload;
1896
1897         switch (msr) {
1898         case MSR_EFER:
1899                 if (cpu_has_load_ia32_efer) {
1900                         clear_atomic_switch_msr_special(vmx,
1901                                         VM_ENTRY_LOAD_IA32_EFER,
1902                                         VM_EXIT_LOAD_IA32_EFER);
1903                         return;
1904                 }
1905                 break;
1906         case MSR_CORE_PERF_GLOBAL_CTRL:
1907                 if (cpu_has_load_perf_global_ctrl) {
1908                         clear_atomic_switch_msr_special(vmx,
1909                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1910                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1911                         return;
1912                 }
1913                 break;
1914         }
1915
1916         for (i = 0; i < m->nr; ++i)
1917                 if (m->guest[i].index == msr)
1918                         break;
1919
1920         if (i == m->nr)
1921                 return;
1922         --m->nr;
1923         m->guest[i] = m->guest[m->nr];
1924         m->host[i] = m->host[m->nr];
1925         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1926         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1927 }
1928
1929 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1930                 unsigned long entry, unsigned long exit,
1931                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1932                 u64 guest_val, u64 host_val)
1933 {
1934         vmcs_write64(guest_val_vmcs, guest_val);
1935         vmcs_write64(host_val_vmcs, host_val);
1936         vm_entry_controls_setbit(vmx, entry);
1937         vm_exit_controls_setbit(vmx, exit);
1938 }
1939
1940 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1941                                   u64 guest_val, u64 host_val)
1942 {
1943         unsigned i;
1944         struct msr_autoload *m = &vmx->msr_autoload;
1945
1946         switch (msr) {
1947         case MSR_EFER:
1948                 if (cpu_has_load_ia32_efer) {
1949                         add_atomic_switch_msr_special(vmx,
1950                                         VM_ENTRY_LOAD_IA32_EFER,
1951                                         VM_EXIT_LOAD_IA32_EFER,
1952                                         GUEST_IA32_EFER,
1953                                         HOST_IA32_EFER,
1954                                         guest_val, host_val);
1955                         return;
1956                 }
1957                 break;
1958         case MSR_CORE_PERF_GLOBAL_CTRL:
1959                 if (cpu_has_load_perf_global_ctrl) {
1960                         add_atomic_switch_msr_special(vmx,
1961                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1962                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1963                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1964                                         HOST_IA32_PERF_GLOBAL_CTRL,
1965                                         guest_val, host_val);
1966                         return;
1967                 }
1968                 break;
1969         case MSR_IA32_PEBS_ENABLE:
1970                 /* PEBS needs a quiescent period after being disabled (to write
1971                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1972                  * provide that period, so a CPU could write host's record into
1973                  * guest's memory.
1974                  */
1975                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1976         }
1977
1978         for (i = 0; i < m->nr; ++i)
1979                 if (m->guest[i].index == msr)
1980                         break;
1981
1982         if (i == NR_AUTOLOAD_MSRS) {
1983                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1984                                 "Can't add msr %x\n", msr);
1985                 return;
1986         } else if (i == m->nr) {
1987                 ++m->nr;
1988                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1989                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1990         }
1991
1992         m->guest[i].index = msr;
1993         m->guest[i].value = guest_val;
1994         m->host[i].index = msr;
1995         m->host[i].value = host_val;
1996 }
1997
1998 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1999 {
2000         u64 guest_efer = vmx->vcpu.arch.efer;
2001         u64 ignore_bits = 0;
2002
2003         if (!enable_ept) {
2004                 /*
2005                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2006                  * host CPUID is more efficient than testing guest CPUID
2007                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2008                  */
2009                 if (boot_cpu_has(X86_FEATURE_SMEP))
2010                         guest_efer |= EFER_NX;
2011                 else if (!(guest_efer & EFER_NX))
2012                         ignore_bits |= EFER_NX;
2013         }
2014
2015         /*
2016          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2017          */
2018         ignore_bits |= EFER_SCE;
2019 #ifdef CONFIG_X86_64
2020         ignore_bits |= EFER_LMA | EFER_LME;
2021         /* SCE is meaningful only in long mode on Intel */
2022         if (guest_efer & EFER_LMA)
2023                 ignore_bits &= ~(u64)EFER_SCE;
2024 #endif
2025
2026         clear_atomic_switch_msr(vmx, MSR_EFER);
2027
2028         /*
2029          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2030          * On CPUs that support "load IA32_EFER", always switch EFER
2031          * atomically, since it's faster than switching it manually.
2032          */
2033         if (cpu_has_load_ia32_efer ||
2034             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2035                 if (!(guest_efer & EFER_LMA))
2036                         guest_efer &= ~EFER_LME;
2037                 if (guest_efer != host_efer)
2038                         add_atomic_switch_msr(vmx, MSR_EFER,
2039                                               guest_efer, host_efer);
2040                 return false;
2041         } else {
2042                 guest_efer &= ~ignore_bits;
2043                 guest_efer |= host_efer & ignore_bits;
2044
2045                 vmx->guest_msrs[efer_offset].data = guest_efer;
2046                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2047
2048                 return true;
2049         }
2050 }
2051
2052 #ifdef CONFIG_X86_32
2053 /*
2054  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2055  * VMCS rather than the segment table.  KVM uses this helper to figure
2056  * out the current bases to poke them into the VMCS before entry.
2057  */
2058 static unsigned long segment_base(u16 selector)
2059 {
2060         struct desc_struct *table;
2061         unsigned long v;
2062
2063         if (!(selector & ~SEGMENT_RPL_MASK))
2064                 return 0;
2065
2066         table = get_current_gdt_ro();
2067
2068         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2069                 u16 ldt_selector = kvm_read_ldt();
2070
2071                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2072                         return 0;
2073
2074                 table = (struct desc_struct *)segment_base(ldt_selector);
2075         }
2076         v = get_desc_base(&table[selector >> 3]);
2077         return v;
2078 }
2079 #endif
2080
2081 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2082 {
2083         struct vcpu_vmx *vmx = to_vmx(vcpu);
2084         int i;
2085
2086         if (vmx->host_state.loaded)
2087                 return;
2088
2089         vmx->host_state.loaded = 1;
2090         /*
2091          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2092          * allow segment selectors with cpl > 0 or ti == 1.
2093          */
2094         vmx->host_state.ldt_sel = kvm_read_ldt();
2095         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2096         savesegment(fs, vmx->host_state.fs_sel);
2097         if (!(vmx->host_state.fs_sel & 7)) {
2098                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2099                 vmx->host_state.fs_reload_needed = 0;
2100         } else {
2101                 vmcs_write16(HOST_FS_SELECTOR, 0);
2102                 vmx->host_state.fs_reload_needed = 1;
2103         }
2104         savesegment(gs, vmx->host_state.gs_sel);
2105         if (!(vmx->host_state.gs_sel & 7))
2106                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2107         else {
2108                 vmcs_write16(HOST_GS_SELECTOR, 0);
2109                 vmx->host_state.gs_ldt_reload_needed = 1;
2110         }
2111
2112 #ifdef CONFIG_X86_64
2113         savesegment(ds, vmx->host_state.ds_sel);
2114         savesegment(es, vmx->host_state.es_sel);
2115 #endif
2116
2117 #ifdef CONFIG_X86_64
2118         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2119         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2120 #else
2121         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2122         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2123 #endif
2124
2125 #ifdef CONFIG_X86_64
2126         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2127         if (is_long_mode(&vmx->vcpu))
2128                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2129 #endif
2130         if (boot_cpu_has(X86_FEATURE_MPX))
2131                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2132         for (i = 0; i < vmx->save_nmsrs; ++i)
2133                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2134                                    vmx->guest_msrs[i].data,
2135                                    vmx->guest_msrs[i].mask);
2136 }
2137
2138 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2139 {
2140         if (!vmx->host_state.loaded)
2141                 return;
2142
2143         ++vmx->vcpu.stat.host_state_reload;
2144         vmx->host_state.loaded = 0;
2145 #ifdef CONFIG_X86_64
2146         if (is_long_mode(&vmx->vcpu))
2147                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2148 #endif
2149         if (vmx->host_state.gs_ldt_reload_needed) {
2150                 kvm_load_ldt(vmx->host_state.ldt_sel);
2151 #ifdef CONFIG_X86_64
2152                 load_gs_index(vmx->host_state.gs_sel);
2153 #else
2154                 loadsegment(gs, vmx->host_state.gs_sel);
2155 #endif
2156         }
2157         if (vmx->host_state.fs_reload_needed)
2158                 loadsegment(fs, vmx->host_state.fs_sel);
2159 #ifdef CONFIG_X86_64
2160         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2161                 loadsegment(ds, vmx->host_state.ds_sel);
2162                 loadsegment(es, vmx->host_state.es_sel);
2163         }
2164 #endif
2165         invalidate_tss_limit();
2166 #ifdef CONFIG_X86_64
2167         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2168 #endif
2169         if (vmx->host_state.msr_host_bndcfgs)
2170                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2171         load_fixmap_gdt(raw_smp_processor_id());
2172 }
2173
2174 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2175 {
2176         preempt_disable();
2177         __vmx_load_host_state(vmx);
2178         preempt_enable();
2179 }
2180
2181 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2182 {
2183         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2184         struct pi_desc old, new;
2185         unsigned int dest;
2186
2187         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2188                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2189                 !kvm_vcpu_apicv_active(vcpu))
2190                 return;
2191
2192         do {
2193                 old.control = new.control = pi_desc->control;
2194
2195                 /*
2196                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2197                  * are two possible cases:
2198                  * 1. After running 'pre_block', context switch
2199                  *    happened. For this case, 'sn' was set in
2200                  *    vmx_vcpu_put(), so we need to clear it here.
2201                  * 2. After running 'pre_block', we were blocked,
2202                  *    and woken up by some other guy. For this case,
2203                  *    we don't need to do anything, 'pi_post_block'
2204                  *    will do everything for us. However, we cannot
2205                  *    check whether it is case #1 or case #2 here
2206                  *    (maybe, not needed), so we also clear sn here,
2207                  *    I think it is not a big deal.
2208                  */
2209                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2210                         if (vcpu->cpu != cpu) {
2211                                 dest = cpu_physical_id(cpu);
2212
2213                                 if (x2apic_enabled())
2214                                         new.ndst = dest;
2215                                 else
2216                                         new.ndst = (dest << 8) & 0xFF00;
2217                         }
2218
2219                         /* set 'NV' to 'notification vector' */
2220                         new.nv = POSTED_INTR_VECTOR;
2221                 }
2222
2223                 /* Allow posting non-urgent interrupts */
2224                 new.sn = 0;
2225         } while (cmpxchg(&pi_desc->control, old.control,
2226                         new.control) != old.control);
2227 }
2228
2229 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2230 {
2231         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2232         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2233 }
2234
2235 /*
2236  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2237  * vcpu mutex is already taken.
2238  */
2239 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2240 {
2241         struct vcpu_vmx *vmx = to_vmx(vcpu);
2242         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2243
2244         if (!already_loaded) {
2245                 loaded_vmcs_clear(vmx->loaded_vmcs);
2246                 local_irq_disable();
2247                 crash_disable_local_vmclear(cpu);
2248
2249                 /*
2250                  * Read loaded_vmcs->cpu should be before fetching
2251                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2252                  * See the comments in __loaded_vmcs_clear().
2253                  */
2254                 smp_rmb();
2255
2256                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2257                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2258                 crash_enable_local_vmclear(cpu);
2259                 local_irq_enable();
2260         }
2261
2262         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2263                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2264                 vmcs_load(vmx->loaded_vmcs->vmcs);
2265         }
2266
2267         if (!already_loaded) {
2268                 void *gdt = get_current_gdt_ro();
2269                 unsigned long sysenter_esp;
2270
2271                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2272
2273                 /*
2274                  * Linux uses per-cpu TSS and GDT, so set these when switching
2275                  * processors.  See 22.2.4.
2276                  */
2277                 vmcs_writel(HOST_TR_BASE,
2278                             (unsigned long)this_cpu_ptr(&cpu_tss));
2279                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2280
2281                 /*
2282                  * VM exits change the host TR limit to 0x67 after a VM
2283                  * exit.  This is okay, since 0x67 covers everything except
2284                  * the IO bitmap and have have code to handle the IO bitmap
2285                  * being lost after a VM exit.
2286                  */
2287                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2288
2289                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2290                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2291
2292                 vmx->loaded_vmcs->cpu = cpu;
2293         }
2294
2295         /* Setup TSC multiplier */
2296         if (kvm_has_tsc_control &&
2297             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2298                 decache_tsc_multiplier(vmx);
2299
2300         vmx_vcpu_pi_load(vcpu, cpu);
2301         vmx->host_pkru = read_pkru();
2302 }
2303
2304 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2305 {
2306         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2307
2308         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2309                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2310                 !kvm_vcpu_apicv_active(vcpu))
2311                 return;
2312
2313         /* Set SN when the vCPU is preempted */
2314         if (vcpu->preempted)
2315                 pi_set_sn(pi_desc);
2316 }
2317
2318 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2319 {
2320         vmx_vcpu_pi_put(vcpu);
2321
2322         __vmx_load_host_state(to_vmx(vcpu));
2323 }
2324
2325 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2326
2327 /*
2328  * Return the cr0 value that a nested guest would read. This is a combination
2329  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2330  * its hypervisor (cr0_read_shadow).
2331  */
2332 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2333 {
2334         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2335                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2336 }
2337 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2338 {
2339         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2340                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2341 }
2342
2343 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2344 {
2345         unsigned long rflags, save_rflags;
2346
2347         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2348                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2349                 rflags = vmcs_readl(GUEST_RFLAGS);
2350                 if (to_vmx(vcpu)->rmode.vm86_active) {
2351                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2352                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2353                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2354                 }
2355                 to_vmx(vcpu)->rflags = rflags;
2356         }
2357         return to_vmx(vcpu)->rflags;
2358 }
2359
2360 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2361 {
2362         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2363         to_vmx(vcpu)->rflags = rflags;
2364         if (to_vmx(vcpu)->rmode.vm86_active) {
2365                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2366                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2367         }
2368         vmcs_writel(GUEST_RFLAGS, rflags);
2369 }
2370
2371 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2372 {
2373         return to_vmx(vcpu)->guest_pkru;
2374 }
2375
2376 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2377 {
2378         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2379         int ret = 0;
2380
2381         if (interruptibility & GUEST_INTR_STATE_STI)
2382                 ret |= KVM_X86_SHADOW_INT_STI;
2383         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2384                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2385
2386         return ret;
2387 }
2388
2389 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2390 {
2391         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2392         u32 interruptibility = interruptibility_old;
2393
2394         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2395
2396         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2397                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2398         else if (mask & KVM_X86_SHADOW_INT_STI)
2399                 interruptibility |= GUEST_INTR_STATE_STI;
2400
2401         if ((interruptibility != interruptibility_old))
2402                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2403 }
2404
2405 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2406 {
2407         unsigned long rip;
2408
2409         rip = kvm_rip_read(vcpu);
2410         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2411         kvm_rip_write(vcpu, rip);
2412
2413         /* skipping an emulated instruction also counts */
2414         vmx_set_interrupt_shadow(vcpu, 0);
2415 }
2416
2417 /*
2418  * KVM wants to inject page-faults which it got to the guest. This function
2419  * checks whether in a nested guest, we need to inject them to L1 or L2.
2420  */
2421 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2422 {
2423         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2424
2425         if (!(vmcs12->exception_bitmap & (1u << nr)))
2426                 return 0;
2427
2428         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2429                           vmcs_read32(VM_EXIT_INTR_INFO),
2430                           vmcs_readl(EXIT_QUALIFICATION));
2431         return 1;
2432 }
2433
2434 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2435                                 bool has_error_code, u32 error_code,
2436                                 bool reinject)
2437 {
2438         struct vcpu_vmx *vmx = to_vmx(vcpu);
2439         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2440
2441         if (!reinject && is_guest_mode(vcpu) &&
2442             nested_vmx_check_exception(vcpu, nr))
2443                 return;
2444
2445         if (has_error_code) {
2446                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2447                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2448         }
2449
2450         if (vmx->rmode.vm86_active) {
2451                 int inc_eip = 0;
2452                 if (kvm_exception_is_soft(nr))
2453                         inc_eip = vcpu->arch.event_exit_inst_len;
2454                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2455                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2456                 return;
2457         }
2458
2459         if (kvm_exception_is_soft(nr)) {
2460                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2461                              vmx->vcpu.arch.event_exit_inst_len);
2462                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2463         } else
2464                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2465
2466         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2467 }
2468
2469 static bool vmx_rdtscp_supported(void)
2470 {
2471         return cpu_has_vmx_rdtscp();
2472 }
2473
2474 static bool vmx_invpcid_supported(void)
2475 {
2476         return cpu_has_vmx_invpcid() && enable_ept;
2477 }
2478
2479 /*
2480  * Swap MSR entry in host/guest MSR entry array.
2481  */
2482 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2483 {
2484         struct shared_msr_entry tmp;
2485
2486         tmp = vmx->guest_msrs[to];
2487         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2488         vmx->guest_msrs[from] = tmp;
2489 }
2490
2491 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2492 {
2493         unsigned long *msr_bitmap;
2494
2495         if (is_guest_mode(vcpu))
2496                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2497         else if (cpu_has_secondary_exec_ctrls() &&
2498                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2499                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2500                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2501                         if (is_long_mode(vcpu))
2502                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2503                         else
2504                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2505                 } else {
2506                         if (is_long_mode(vcpu))
2507                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2508                         else
2509                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2510                 }
2511         } else {
2512                 if (is_long_mode(vcpu))
2513                         msr_bitmap = vmx_msr_bitmap_longmode;
2514                 else
2515                         msr_bitmap = vmx_msr_bitmap_legacy;
2516         }
2517
2518         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2519 }
2520
2521 /*
2522  * Set up the vmcs to automatically save and restore system
2523  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2524  * mode, as fiddling with msrs is very expensive.
2525  */
2526 static void setup_msrs(struct vcpu_vmx *vmx)
2527 {
2528         int save_nmsrs, index;
2529
2530         save_nmsrs = 0;
2531 #ifdef CONFIG_X86_64
2532         if (is_long_mode(&vmx->vcpu)) {
2533                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2534                 if (index >= 0)
2535                         move_msr_up(vmx, index, save_nmsrs++);
2536                 index = __find_msr_index(vmx, MSR_LSTAR);
2537                 if (index >= 0)
2538                         move_msr_up(vmx, index, save_nmsrs++);
2539                 index = __find_msr_index(vmx, MSR_CSTAR);
2540                 if (index >= 0)
2541                         move_msr_up(vmx, index, save_nmsrs++);
2542                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2543                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2544                         move_msr_up(vmx, index, save_nmsrs++);
2545                 /*
2546                  * MSR_STAR is only needed on long mode guests, and only
2547                  * if efer.sce is enabled.
2548                  */
2549                 index = __find_msr_index(vmx, MSR_STAR);
2550                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2551                         move_msr_up(vmx, index, save_nmsrs++);
2552         }
2553 #endif
2554         index = __find_msr_index(vmx, MSR_EFER);
2555         if (index >= 0 && update_transition_efer(vmx, index))
2556                 move_msr_up(vmx, index, save_nmsrs++);
2557
2558         vmx->save_nmsrs = save_nmsrs;
2559
2560         if (cpu_has_vmx_msr_bitmap())
2561                 vmx_set_msr_bitmap(&vmx->vcpu);
2562 }
2563
2564 /*
2565  * reads and returns guest's timestamp counter "register"
2566  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2567  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2568  */
2569 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2570 {
2571         u64 host_tsc, tsc_offset;
2572
2573         host_tsc = rdtsc();
2574         tsc_offset = vmcs_read64(TSC_OFFSET);
2575         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2576 }
2577
2578 /*
2579  * writes 'offset' into guest's timestamp counter offset register
2580  */
2581 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2582 {
2583         if (is_guest_mode(vcpu)) {
2584                 /*
2585                  * We're here if L1 chose not to trap WRMSR to TSC. According
2586                  * to the spec, this should set L1's TSC; The offset that L1
2587                  * set for L2 remains unchanged, and still needs to be added
2588                  * to the newly set TSC to get L2's TSC.
2589                  */
2590                 struct vmcs12 *vmcs12;
2591                 /* recalculate vmcs02.TSC_OFFSET: */
2592                 vmcs12 = get_vmcs12(vcpu);
2593                 vmcs_write64(TSC_OFFSET, offset +
2594                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2595                          vmcs12->tsc_offset : 0));
2596         } else {
2597                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2598                                            vmcs_read64(TSC_OFFSET), offset);
2599                 vmcs_write64(TSC_OFFSET, offset);
2600         }
2601 }
2602
2603 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2604 {
2605         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2606         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2607 }
2608
2609 /*
2610  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2611  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2612  * all guests if the "nested" module option is off, and can also be disabled
2613  * for a single guest by disabling its VMX cpuid bit.
2614  */
2615 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2616 {
2617         return nested && guest_cpuid_has_vmx(vcpu);
2618 }
2619
2620 /*
2621  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2622  * returned for the various VMX controls MSRs when nested VMX is enabled.
2623  * The same values should also be used to verify that vmcs12 control fields are
2624  * valid during nested entry from L1 to L2.
2625  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2626  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2627  * bit in the high half is on if the corresponding bit in the control field
2628  * may be on. See also vmx_control_verify().
2629  */
2630 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2631 {
2632         /*
2633          * Note that as a general rule, the high half of the MSRs (bits in
2634          * the control fields which may be 1) should be initialized by the
2635          * intersection of the underlying hardware's MSR (i.e., features which
2636          * can be supported) and the list of features we want to expose -
2637          * because they are known to be properly supported in our code.
2638          * Also, usually, the low half of the MSRs (bits which must be 1) can
2639          * be set to 0, meaning that L1 may turn off any of these bits. The
2640          * reason is that if one of these bits is necessary, it will appear
2641          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2642          * fields of vmcs01 and vmcs02, will turn these bits off - and
2643          * nested_vmx_exit_handled() will not pass related exits to L1.
2644          * These rules have exceptions below.
2645          */
2646
2647         /* pin-based controls */
2648         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2649                 vmx->nested.nested_vmx_pinbased_ctls_low,
2650                 vmx->nested.nested_vmx_pinbased_ctls_high);
2651         vmx->nested.nested_vmx_pinbased_ctls_low |=
2652                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2653         vmx->nested.nested_vmx_pinbased_ctls_high &=
2654                 PIN_BASED_EXT_INTR_MASK |
2655                 PIN_BASED_NMI_EXITING |
2656                 PIN_BASED_VIRTUAL_NMIS;
2657         vmx->nested.nested_vmx_pinbased_ctls_high |=
2658                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2659                 PIN_BASED_VMX_PREEMPTION_TIMER;
2660         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2661                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2662                         PIN_BASED_POSTED_INTR;
2663
2664         /* exit controls */
2665         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2666                 vmx->nested.nested_vmx_exit_ctls_low,
2667                 vmx->nested.nested_vmx_exit_ctls_high);
2668         vmx->nested.nested_vmx_exit_ctls_low =
2669                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2670
2671         vmx->nested.nested_vmx_exit_ctls_high &=
2672 #ifdef CONFIG_X86_64
2673                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2674 #endif
2675                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2676         vmx->nested.nested_vmx_exit_ctls_high |=
2677                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2678                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2679                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2680
2681         if (kvm_mpx_supported())
2682                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2683
2684         /* We support free control of debug control saving. */
2685         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2686
2687         /* entry controls */
2688         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2689                 vmx->nested.nested_vmx_entry_ctls_low,
2690                 vmx->nested.nested_vmx_entry_ctls_high);
2691         vmx->nested.nested_vmx_entry_ctls_low =
2692                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2693         vmx->nested.nested_vmx_entry_ctls_high &=
2694 #ifdef CONFIG_X86_64
2695                 VM_ENTRY_IA32E_MODE |
2696 #endif
2697                 VM_ENTRY_LOAD_IA32_PAT;
2698         vmx->nested.nested_vmx_entry_ctls_high |=
2699                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2700         if (kvm_mpx_supported())
2701                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2702
2703         /* We support free control of debug control loading. */
2704         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2705
2706         /* cpu-based controls */
2707         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2708                 vmx->nested.nested_vmx_procbased_ctls_low,
2709                 vmx->nested.nested_vmx_procbased_ctls_high);
2710         vmx->nested.nested_vmx_procbased_ctls_low =
2711                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2712         vmx->nested.nested_vmx_procbased_ctls_high &=
2713                 CPU_BASED_VIRTUAL_INTR_PENDING |
2714                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2715                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2716                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2717                 CPU_BASED_CR3_STORE_EXITING |
2718 #ifdef CONFIG_X86_64
2719                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2720 #endif
2721                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2722                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2723                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2724                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2725                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2726         /*
2727          * We can allow some features even when not supported by the
2728          * hardware. For example, L1 can specify an MSR bitmap - and we
2729          * can use it to avoid exits to L1 - even when L0 runs L2
2730          * without MSR bitmaps.
2731          */
2732         vmx->nested.nested_vmx_procbased_ctls_high |=
2733                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2734                 CPU_BASED_USE_MSR_BITMAPS;
2735
2736         /* We support free control of CR3 access interception. */
2737         vmx->nested.nested_vmx_procbased_ctls_low &=
2738                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2739
2740         /* secondary cpu-based controls */
2741         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2742                 vmx->nested.nested_vmx_secondary_ctls_low,
2743                 vmx->nested.nested_vmx_secondary_ctls_high);
2744         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2745         vmx->nested.nested_vmx_secondary_ctls_high &=
2746                 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
2747                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2748                 SECONDARY_EXEC_RDTSCP |
2749                 SECONDARY_EXEC_DESC |
2750                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2751                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2752                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2753                 SECONDARY_EXEC_WBINVD_EXITING |
2754                 SECONDARY_EXEC_XSAVES;
2755
2756         if (enable_ept) {
2757                 /* nested EPT: emulate EPT also to L1 */
2758                 vmx->nested.nested_vmx_secondary_ctls_high |=
2759                         SECONDARY_EXEC_ENABLE_EPT;
2760                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2761                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2762                 if (cpu_has_vmx_ept_execute_only())
2763                         vmx->nested.nested_vmx_ept_caps |=
2764                                 VMX_EPT_EXECUTE_ONLY_BIT;
2765                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2766                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2767                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2768                         VMX_EPT_1GB_PAGE_BIT;
2769                 if (enable_ept_ad_bits) {
2770                         vmx->nested.nested_vmx_secondary_ctls_high |=
2771                                 SECONDARY_EXEC_ENABLE_PML;
2772                        vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2773                 }
2774         } else
2775                 vmx->nested.nested_vmx_ept_caps = 0;
2776
2777         /*
2778          * Old versions of KVM use the single-context version without
2779          * checking for support, so declare that it is supported even
2780          * though it is treated as global context.  The alternative is
2781          * not failing the single-context invvpid, and it is worse.
2782          */
2783         if (enable_vpid) {
2784                 vmx->nested.nested_vmx_secondary_ctls_high |=
2785                         SECONDARY_EXEC_ENABLE_VPID;
2786                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2787                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2788         } else
2789                 vmx->nested.nested_vmx_vpid_caps = 0;
2790
2791         if (enable_unrestricted_guest)
2792                 vmx->nested.nested_vmx_secondary_ctls_high |=
2793                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2794
2795         /* miscellaneous data */
2796         rdmsr(MSR_IA32_VMX_MISC,
2797                 vmx->nested.nested_vmx_misc_low,
2798                 vmx->nested.nested_vmx_misc_high);
2799         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2800         vmx->nested.nested_vmx_misc_low |=
2801                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2802                 VMX_MISC_ACTIVITY_HLT;
2803         vmx->nested.nested_vmx_misc_high = 0;
2804
2805         /*
2806          * This MSR reports some information about VMX support. We
2807          * should return information about the VMX we emulate for the
2808          * guest, and the VMCS structure we give it - not about the
2809          * VMX support of the underlying hardware.
2810          */
2811         vmx->nested.nested_vmx_basic =
2812                 VMCS12_REVISION |
2813                 VMX_BASIC_TRUE_CTLS |
2814                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2815                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2816
2817         if (cpu_has_vmx_basic_inout())
2818                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2819
2820         /*
2821          * These MSRs specify bits which the guest must keep fixed on
2822          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2823          * We picked the standard core2 setting.
2824          */
2825 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2826 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2827         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2828         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2829
2830         /* These MSRs specify bits which the guest must keep fixed off. */
2831         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2832         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2833
2834         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2835         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2836 }
2837
2838 /*
2839  * if fixed0[i] == 1: val[i] must be 1
2840  * if fixed1[i] == 0: val[i] must be 0
2841  */
2842 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2843 {
2844         return ((val & fixed1) | fixed0) == val;
2845 }
2846
2847 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2848 {
2849         return fixed_bits_valid(control, low, high);
2850 }
2851
2852 static inline u64 vmx_control_msr(u32 low, u32 high)
2853 {
2854         return low | ((u64)high << 32);
2855 }
2856
2857 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2858 {
2859         superset &= mask;
2860         subset &= mask;
2861
2862         return (superset | subset) == superset;
2863 }
2864
2865 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2866 {
2867         const u64 feature_and_reserved =
2868                 /* feature (except bit 48; see below) */
2869                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2870                 /* reserved */
2871                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2872         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2873
2874         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2875                 return -EINVAL;
2876
2877         /*
2878          * KVM does not emulate a version of VMX that constrains physical
2879          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2880          */
2881         if (data & BIT_ULL(48))
2882                 return -EINVAL;
2883
2884         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2885             vmx_basic_vmcs_revision_id(data))
2886                 return -EINVAL;
2887
2888         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2889                 return -EINVAL;
2890
2891         vmx->nested.nested_vmx_basic = data;
2892         return 0;
2893 }
2894
2895 static int
2896 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2897 {
2898         u64 supported;
2899         u32 *lowp, *highp;
2900
2901         switch (msr_index) {
2902         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2903                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2904                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2905                 break;
2906         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2907                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2908                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2909                 break;
2910         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2911                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2912                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2913                 break;
2914         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2915                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2916                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2917                 break;
2918         case MSR_IA32_VMX_PROCBASED_CTLS2:
2919                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2920                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2921                 break;
2922         default:
2923                 BUG();
2924         }
2925
2926         supported = vmx_control_msr(*lowp, *highp);
2927
2928         /* Check must-be-1 bits are still 1. */
2929         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2930                 return -EINVAL;
2931
2932         /* Check must-be-0 bits are still 0. */
2933         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2934                 return -EINVAL;
2935
2936         *lowp = data;
2937         *highp = data >> 32;
2938         return 0;
2939 }
2940
2941 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2942 {
2943         const u64 feature_and_reserved_bits =
2944                 /* feature */
2945                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2946                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2947                 /* reserved */
2948                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2949         u64 vmx_misc;
2950
2951         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2952                                    vmx->nested.nested_vmx_misc_high);
2953
2954         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2955                 return -EINVAL;
2956
2957         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2958              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2959             vmx_misc_preemption_timer_rate(data) !=
2960             vmx_misc_preemption_timer_rate(vmx_misc))
2961                 return -EINVAL;
2962
2963         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2964                 return -EINVAL;
2965
2966         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2967                 return -EINVAL;
2968
2969         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2970                 return -EINVAL;
2971
2972         vmx->nested.nested_vmx_misc_low = data;
2973         vmx->nested.nested_vmx_misc_high = data >> 32;
2974         return 0;
2975 }
2976
2977 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2978 {
2979         u64 vmx_ept_vpid_cap;
2980
2981         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2982                                            vmx->nested.nested_vmx_vpid_caps);
2983
2984         /* Every bit is either reserved or a feature bit. */
2985         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2986                 return -EINVAL;
2987
2988         vmx->nested.nested_vmx_ept_caps = data;
2989         vmx->nested.nested_vmx_vpid_caps = data >> 32;
2990         return 0;
2991 }
2992
2993 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2994 {
2995         u64 *msr;
2996
2997         switch (msr_index) {
2998         case MSR_IA32_VMX_CR0_FIXED0:
2999                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3000                 break;
3001         case MSR_IA32_VMX_CR4_FIXED0:
3002                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3003                 break;
3004         default:
3005                 BUG();
3006         }
3007
3008         /*
3009          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3010          * must be 1 in the restored value.
3011          */
3012         if (!is_bitwise_subset(data, *msr, -1ULL))
3013                 return -EINVAL;
3014
3015         *msr = data;
3016         return 0;
3017 }
3018
3019 /*
3020  * Called when userspace is restoring VMX MSRs.
3021  *
3022  * Returns 0 on success, non-0 otherwise.
3023  */
3024 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3025 {
3026         struct vcpu_vmx *vmx = to_vmx(vcpu);
3027
3028         switch (msr_index) {
3029         case MSR_IA32_VMX_BASIC:
3030                 return vmx_restore_vmx_basic(vmx, data);
3031         case MSR_IA32_VMX_PINBASED_CTLS:
3032         case MSR_IA32_VMX_PROCBASED_CTLS:
3033         case MSR_IA32_VMX_EXIT_CTLS:
3034         case MSR_IA32_VMX_ENTRY_CTLS:
3035                 /*
3036                  * The "non-true" VMX capability MSRs are generated from the
3037                  * "true" MSRs, so we do not support restoring them directly.
3038                  *
3039                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3040                  * should restore the "true" MSRs with the must-be-1 bits
3041                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3042                  * DEFAULT SETTINGS".
3043                  */
3044                 return -EINVAL;
3045         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3046         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3047         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3048         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3049         case MSR_IA32_VMX_PROCBASED_CTLS2:
3050                 return vmx_restore_control_msr(vmx, msr_index, data);
3051         case MSR_IA32_VMX_MISC:
3052                 return vmx_restore_vmx_misc(vmx, data);
3053         case MSR_IA32_VMX_CR0_FIXED0:
3054         case MSR_IA32_VMX_CR4_FIXED0:
3055                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3056         case MSR_IA32_VMX_CR0_FIXED1:
3057         case MSR_IA32_VMX_CR4_FIXED1:
3058                 /*
3059                  * These MSRs are generated based on the vCPU's CPUID, so we
3060                  * do not support restoring them directly.
3061                  */
3062                 return -EINVAL;
3063         case MSR_IA32_VMX_EPT_VPID_CAP:
3064                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3065         case MSR_IA32_VMX_VMCS_ENUM:
3066                 vmx->nested.nested_vmx_vmcs_enum = data;
3067                 return 0;
3068         default:
3069                 /*
3070                  * The rest of the VMX capability MSRs do not support restore.
3071                  */
3072                 return -EINVAL;
3073         }
3074 }
3075
3076 /* Returns 0 on success, non-0 otherwise. */
3077 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3078 {
3079         struct vcpu_vmx *vmx = to_vmx(vcpu);
3080
3081         switch (msr_index) {
3082         case MSR_IA32_VMX_BASIC:
3083                 *pdata = vmx->nested.nested_vmx_basic;
3084                 break;
3085         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3086         case MSR_IA32_VMX_PINBASED_CTLS:
3087                 *pdata = vmx_control_msr(
3088                         vmx->nested.nested_vmx_pinbased_ctls_low,
3089                         vmx->nested.nested_vmx_pinbased_ctls_high);
3090                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3091                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3092                 break;
3093         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3094         case MSR_IA32_VMX_PROCBASED_CTLS:
3095                 *pdata = vmx_control_msr(
3096                         vmx->nested.nested_vmx_procbased_ctls_low,
3097                         vmx->nested.nested_vmx_procbased_ctls_high);
3098                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3099                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3100                 break;
3101         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3102         case MSR_IA32_VMX_EXIT_CTLS:
3103                 *pdata = vmx_control_msr(
3104                         vmx->nested.nested_vmx_exit_ctls_low,
3105                         vmx->nested.nested_vmx_exit_ctls_high);
3106                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3107                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3108                 break;
3109         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3110         case MSR_IA32_VMX_ENTRY_CTLS:
3111                 *pdata = vmx_control_msr(
3112                         vmx->nested.nested_vmx_entry_ctls_low,
3113                         vmx->nested.nested_vmx_entry_ctls_high);
3114                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3115                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3116                 break;
3117         case MSR_IA32_VMX_MISC:
3118                 *pdata = vmx_control_msr(
3119                         vmx->nested.nested_vmx_misc_low,
3120                         vmx->nested.nested_vmx_misc_high);
3121                 break;
3122         case MSR_IA32_VMX_CR0_FIXED0:
3123                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3124                 break;
3125         case MSR_IA32_VMX_CR0_FIXED1:
3126                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3127                 break;
3128         case MSR_IA32_VMX_CR4_FIXED0:
3129                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3130                 break;
3131         case MSR_IA32_VMX_CR4_FIXED1:
3132                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3133                 break;
3134         case MSR_IA32_VMX_VMCS_ENUM:
3135                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3136                 break;
3137         case MSR_IA32_VMX_PROCBASED_CTLS2:
3138                 *pdata = vmx_control_msr(
3139                         vmx->nested.nested_vmx_secondary_ctls_low,
3140                         vmx->nested.nested_vmx_secondary_ctls_high);
3141                 break;
3142         case MSR_IA32_VMX_EPT_VPID_CAP:
3143                 *pdata = vmx->nested.nested_vmx_ept_caps |
3144                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3145                 break;
3146         default:
3147                 return 1;
3148         }
3149
3150         return 0;
3151 }
3152
3153 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3154                                                  uint64_t val)
3155 {
3156         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3157
3158         return !(val & ~valid_bits);
3159 }
3160
3161 /*
3162  * Reads an msr value (of 'msr_index') into 'pdata'.
3163  * Returns 0 on success, non-0 otherwise.
3164  * Assumes vcpu_load() was already called.
3165  */
3166 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3167 {
3168         struct shared_msr_entry *msr;
3169
3170         switch (msr_info->index) {
3171 #ifdef CONFIG_X86_64
3172         case MSR_FS_BASE:
3173                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3174                 break;
3175         case MSR_GS_BASE:
3176                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3177                 break;
3178         case MSR_KERNEL_GS_BASE:
3179                 vmx_load_host_state(to_vmx(vcpu));
3180                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3181                 break;
3182 #endif
3183         case MSR_EFER:
3184                 return kvm_get_msr_common(vcpu, msr_info);
3185         case MSR_IA32_TSC:
3186                 msr_info->data = guest_read_tsc(vcpu);
3187                 break;
3188         case MSR_IA32_SYSENTER_CS:
3189                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3190                 break;
3191         case MSR_IA32_SYSENTER_EIP:
3192                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3193                 break;
3194         case MSR_IA32_SYSENTER_ESP:
3195                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3196                 break;
3197         case MSR_IA32_BNDCFGS:
3198                 if (!kvm_mpx_supported())
3199                         return 1;
3200                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3201                 break;
3202         case MSR_IA32_MCG_EXT_CTL:
3203                 if (!msr_info->host_initiated &&
3204                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3205                       FEATURE_CONTROL_LMCE))
3206                         return 1;
3207                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3208                 break;
3209         case MSR_IA32_FEATURE_CONTROL:
3210                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3211                 break;
3212         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3213                 if (!nested_vmx_allowed(vcpu))
3214                         return 1;
3215                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3216         case MSR_IA32_XSS:
3217                 if (!vmx_xsaves_supported())
3218                         return 1;
3219                 msr_info->data = vcpu->arch.ia32_xss;
3220                 break;
3221         case MSR_TSC_AUX:
3222                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3223                         return 1;
3224                 /* Otherwise falls through */
3225         default:
3226                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3227                 if (msr) {
3228                         msr_info->data = msr->data;
3229                         break;
3230                 }
3231                 return kvm_get_msr_common(vcpu, msr_info);
3232         }
3233
3234         return 0;
3235 }
3236
3237 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3238
3239 /*
3240  * Writes msr value into into the appropriate "register".
3241  * Returns 0 on success, non-0 otherwise.
3242  * Assumes vcpu_load() was already called.
3243  */
3244 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3245 {
3246         struct vcpu_vmx *vmx = to_vmx(vcpu);
3247         struct shared_msr_entry *msr;
3248         int ret = 0;
3249         u32 msr_index = msr_info->index;
3250         u64 data = msr_info->data;
3251
3252         switch (msr_index) {
3253         case MSR_EFER:
3254                 ret = kvm_set_msr_common(vcpu, msr_info);
3255                 break;
3256 #ifdef CONFIG_X86_64
3257         case MSR_FS_BASE:
3258                 vmx_segment_cache_clear(vmx);
3259                 vmcs_writel(GUEST_FS_BASE, data);
3260                 break;
3261         case MSR_GS_BASE:
3262                 vmx_segment_cache_clear(vmx);
3263                 vmcs_writel(GUEST_GS_BASE, data);
3264                 break;
3265         case MSR_KERNEL_GS_BASE:
3266                 vmx_load_host_state(vmx);
3267                 vmx->msr_guest_kernel_gs_base = data;
3268                 break;
3269 #endif
3270         case MSR_IA32_SYSENTER_CS:
3271                 vmcs_write32(GUEST_SYSENTER_CS, data);
3272                 break;
3273         case MSR_IA32_SYSENTER_EIP:
3274                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3275                 break;
3276         case MSR_IA32_SYSENTER_ESP:
3277                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3278                 break;
3279         case MSR_IA32_BNDCFGS:
3280                 if (!kvm_mpx_supported())
3281                         return 1;
3282                 vmcs_write64(GUEST_BNDCFGS, data);
3283                 break;
3284         case MSR_IA32_TSC:
3285                 kvm_write_tsc(vcpu, msr_info);
3286                 break;
3287         case MSR_IA32_CR_PAT:
3288                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3289                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3290                                 return 1;
3291                         vmcs_write64(GUEST_IA32_PAT, data);
3292                         vcpu->arch.pat = data;
3293                         break;
3294                 }
3295                 ret = kvm_set_msr_common(vcpu, msr_info);
3296                 break;
3297         case MSR_IA32_TSC_ADJUST:
3298                 ret = kvm_set_msr_common(vcpu, msr_info);
3299                 break;
3300         case MSR_IA32_MCG_EXT_CTL:
3301                 if ((!msr_info->host_initiated &&
3302                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3303                        FEATURE_CONTROL_LMCE)) ||
3304                     (data & ~MCG_EXT_CTL_LMCE_EN))
3305                         return 1;
3306                 vcpu->arch.mcg_ext_ctl = data;
3307                 break;
3308         case MSR_IA32_FEATURE_CONTROL:
3309                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3310                     (to_vmx(vcpu)->msr_ia32_feature_control &
3311                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3312                         return 1;
3313                 vmx->msr_ia32_feature_control = data;
3314                 if (msr_info->host_initiated && data == 0)
3315                         vmx_leave_nested(vcpu);
3316                 break;
3317         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3318                 if (!msr_info->host_initiated)
3319                         return 1; /* they are read-only */
3320                 if (!nested_vmx_allowed(vcpu))
3321                         return 1;
3322                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3323         case MSR_IA32_XSS:
3324                 if (!vmx_xsaves_supported())
3325                         return 1;
3326                 /*
3327                  * The only supported bit as of Skylake is bit 8, but
3328                  * it is not supported on KVM.
3329                  */
3330                 if (data != 0)
3331                         return 1;
3332                 vcpu->arch.ia32_xss = data;
3333                 if (vcpu->arch.ia32_xss != host_xss)
3334                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3335                                 vcpu->arch.ia32_xss, host_xss);
3336                 else
3337                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3338                 break;
3339         case MSR_TSC_AUX:
3340                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3341                         return 1;
3342                 /* Check reserved bit, higher 32 bits should be zero */
3343                 if ((data >> 32) != 0)
3344                         return 1;
3345                 /* Otherwise falls through */
3346         default:
3347                 msr = find_msr_entry(vmx, msr_index);
3348                 if (msr) {
3349                         u64 old_msr_data = msr->data;
3350                         msr->data = data;
3351                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3352                                 preempt_disable();
3353                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3354                                                          msr->mask);
3355                                 preempt_enable();
3356                                 if (ret)
3357                                         msr->data = old_msr_data;
3358                         }
3359                         break;
3360                 }
3361                 ret = kvm_set_msr_common(vcpu, msr_info);
3362         }
3363
3364         return ret;
3365 }
3366
3367 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3368 {
3369         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3370         switch (reg) {
3371         case VCPU_REGS_RSP:
3372                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3373                 break;
3374         case VCPU_REGS_RIP:
3375                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3376                 break;
3377         case VCPU_EXREG_PDPTR:
3378                 if (enable_ept)
3379                         ept_save_pdptrs(vcpu);
3380                 break;
3381         default:
3382                 break;
3383         }
3384 }
3385
3386 static __init int cpu_has_kvm_support(void)
3387 {
3388         return cpu_has_vmx();
3389 }
3390
3391 static __init int vmx_disabled_by_bios(void)
3392 {
3393         u64 msr;
3394
3395         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3396         if (msr & FEATURE_CONTROL_LOCKED) {
3397                 /* launched w/ TXT and VMX disabled */
3398                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3399                         && tboot_enabled())
3400                         return 1;
3401                 /* launched w/o TXT and VMX only enabled w/ TXT */
3402                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3403                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3404                         && !tboot_enabled()) {
3405                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3406                                 "activate TXT before enabling KVM\n");
3407                         return 1;
3408                 }
3409                 /* launched w/o TXT and VMX disabled */
3410                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3411                         && !tboot_enabled())
3412                         return 1;
3413         }
3414
3415         return 0;
3416 }
3417
3418 static void kvm_cpu_vmxon(u64 addr)
3419 {
3420         cr4_set_bits(X86_CR4_VMXE);
3421         intel_pt_handle_vmx(1);
3422
3423         asm volatile (ASM_VMX_VMXON_RAX
3424                         : : "a"(&addr), "m"(addr)
3425                         : "memory", "cc");
3426 }
3427
3428 static int hardware_enable(void)
3429 {
3430         int cpu = raw_smp_processor_id();
3431         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3432         u64 old, test_bits;
3433
3434         if (cr4_read_shadow() & X86_CR4_VMXE)
3435                 return -EBUSY;
3436
3437         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3438         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3439         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3440
3441         /*
3442          * Now we can enable the vmclear operation in kdump
3443          * since the loaded_vmcss_on_cpu list on this cpu
3444          * has been initialized.
3445          *
3446          * Though the cpu is not in VMX operation now, there
3447          * is no problem to enable the vmclear operation
3448          * for the loaded_vmcss_on_cpu list is empty!
3449          */
3450         crash_enable_local_vmclear(cpu);
3451
3452         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3453
3454         test_bits = FEATURE_CONTROL_LOCKED;
3455         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3456         if (tboot_enabled())
3457                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3458
3459         if ((old & test_bits) != test_bits) {
3460                 /* enable and lock */
3461                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3462         }
3463         kvm_cpu_vmxon(phys_addr);
3464         ept_sync_global();
3465
3466         return 0;
3467 }
3468
3469 static void vmclear_local_loaded_vmcss(void)
3470 {
3471         int cpu = raw_smp_processor_id();
3472         struct loaded_vmcs *v, *n;
3473
3474         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3475                                  loaded_vmcss_on_cpu_link)
3476                 __loaded_vmcs_clear(v);
3477 }
3478
3479
3480 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3481  * tricks.
3482  */
3483 static void kvm_cpu_vmxoff(void)
3484 {
3485         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3486
3487         intel_pt_handle_vmx(0);
3488         cr4_clear_bits(X86_CR4_VMXE);
3489 }
3490
3491 static void hardware_disable(void)
3492 {
3493         vmclear_local_loaded_vmcss();
3494         kvm_cpu_vmxoff();
3495 }
3496
3497 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3498                                       u32 msr, u32 *result)
3499 {
3500         u32 vmx_msr_low, vmx_msr_high;
3501         u32 ctl = ctl_min | ctl_opt;
3502
3503         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3504
3505         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3506         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3507
3508         /* Ensure minimum (required) set of control bits are supported. */
3509         if (ctl_min & ~ctl)
3510                 return -EIO;
3511
3512         *result = ctl;
3513         return 0;
3514 }
3515
3516 static __init bool allow_1_setting(u32 msr, u32 ctl)
3517 {
3518         u32 vmx_msr_low, vmx_msr_high;
3519
3520         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3521         return vmx_msr_high & ctl;
3522 }
3523
3524 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3525 {
3526         u32 vmx_msr_low, vmx_msr_high;
3527         u32 min, opt, min2, opt2;
3528         u32 _pin_based_exec_control = 0;
3529         u32 _cpu_based_exec_control = 0;
3530         u32 _cpu_based_2nd_exec_control = 0;
3531         u32 _vmexit_control = 0;
3532         u32 _vmentry_control = 0;
3533
3534         min = CPU_BASED_HLT_EXITING |
3535 #ifdef CONFIG_X86_64
3536               CPU_BASED_CR8_LOAD_EXITING |
3537               CPU_BASED_CR8_STORE_EXITING |
3538 #endif
3539               CPU_BASED_CR3_LOAD_EXITING |
3540               CPU_BASED_CR3_STORE_EXITING |
3541               CPU_BASED_USE_IO_BITMAPS |
3542               CPU_BASED_MOV_DR_EXITING |
3543               CPU_BASED_USE_TSC_OFFSETING |
3544               CPU_BASED_INVLPG_EXITING |
3545               CPU_BASED_RDPMC_EXITING;
3546
3547         if (!kvm_mwait_in_guest())
3548                 min |= CPU_BASED_MWAIT_EXITING |
3549                         CPU_BASED_MONITOR_EXITING;
3550
3551         opt = CPU_BASED_TPR_SHADOW |
3552               CPU_BASED_USE_MSR_BITMAPS |
3553               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3554         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3555                                 &_cpu_based_exec_control) < 0)
3556                 return -EIO;
3557 #ifdef CONFIG_X86_64
3558         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3559                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3560                                            ~CPU_BASED_CR8_STORE_EXITING;
3561 #endif
3562         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3563                 min2 = 0;
3564                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3565                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3566                         SECONDARY_EXEC_WBINVD_EXITING |
3567                         SECONDARY_EXEC_ENABLE_VPID |
3568                         SECONDARY_EXEC_ENABLE_EPT |
3569                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3570                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3571                         SECONDARY_EXEC_RDTSCP |
3572                         SECONDARY_EXEC_ENABLE_INVPCID |
3573                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3574                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3575                         SECONDARY_EXEC_SHADOW_VMCS |
3576                         SECONDARY_EXEC_XSAVES |
3577                         SECONDARY_EXEC_ENABLE_PML |
3578                         SECONDARY_EXEC_TSC_SCALING;
3579                 if (adjust_vmx_controls(min2, opt2,
3580                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3581                                         &_cpu_based_2nd_exec_control) < 0)
3582                         return -EIO;
3583         }
3584 #ifndef CONFIG_X86_64
3585         if (!(_cpu_based_2nd_exec_control &
3586                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3587                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3588 #endif
3589
3590         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3591                 _cpu_based_2nd_exec_control &= ~(
3592                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3593                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3594                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3595
3596         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3597                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3598                    enabled */
3599                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3600                                              CPU_BASED_CR3_STORE_EXITING |
3601                                              CPU_BASED_INVLPG_EXITING);
3602                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3603                       vmx_capability.ept, vmx_capability.vpid);
3604         }
3605
3606         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3607 #ifdef CONFIG_X86_64
3608         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3609 #endif
3610         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3611                 VM_EXIT_CLEAR_BNDCFGS;
3612         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3613                                 &_vmexit_control) < 0)
3614                 return -EIO;
3615
3616         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3617                 PIN_BASED_VIRTUAL_NMIS;
3618         opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3619         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3620                                 &_pin_based_exec_control) < 0)
3621                 return -EIO;
3622
3623         if (cpu_has_broken_vmx_preemption_timer())
3624                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3625         if (!(_cpu_based_2nd_exec_control &
3626                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3627                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3628
3629         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3630         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3631         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3632                                 &_vmentry_control) < 0)
3633                 return -EIO;
3634
3635         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3636
3637         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3638         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3639                 return -EIO;
3640
3641 #ifdef CONFIG_X86_64
3642         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3643         if (vmx_msr_high & (1u<<16))
3644                 return -EIO;
3645 #endif
3646
3647         /* Require Write-Back (WB) memory type for VMCS accesses. */
3648         if (((vmx_msr_high >> 18) & 15) != 6)
3649                 return -EIO;
3650
3651         vmcs_conf->size = vmx_msr_high & 0x1fff;
3652         vmcs_conf->order = get_order(vmcs_conf->size);
3653         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3654         vmcs_conf->revision_id = vmx_msr_low;
3655
3656         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3657         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3658         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3659         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3660         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3661
3662         cpu_has_load_ia32_efer =
3663                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3664                                 VM_ENTRY_LOAD_IA32_EFER)
3665                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3666                                    VM_EXIT_LOAD_IA32_EFER);
3667
3668         cpu_has_load_perf_global_ctrl =
3669                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3670                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3671                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3672                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3673
3674         /*
3675          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3676          * but due to errata below it can't be used. Workaround is to use
3677          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3678          *
3679          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3680          *
3681          * AAK155             (model 26)
3682          * AAP115             (model 30)
3683          * AAT100             (model 37)
3684          * BC86,AAY89,BD102   (model 44)
3685          * BA97               (model 46)
3686          *
3687          */
3688         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3689                 switch (boot_cpu_data.x86_model) {
3690                 case 26:
3691                 case 30:
3692                 case 37:
3693                 case 44:
3694                 case 46:
3695                         cpu_has_load_perf_global_ctrl = false;
3696                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3697                                         "does not work properly. Using workaround\n");
3698                         break;
3699                 default:
3700                         break;
3701                 }
3702         }
3703
3704         if (boot_cpu_has(X86_FEATURE_XSAVES))
3705                 rdmsrl(MSR_IA32_XSS, host_xss);
3706
3707         return 0;
3708 }
3709
3710 static struct vmcs *alloc_vmcs_cpu(int cpu)
3711 {
3712         int node = cpu_to_node(cpu);
3713         struct page *pages;
3714         struct vmcs *vmcs;
3715
3716         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3717         if (!pages)
3718                 return NULL;
3719         vmcs = page_address(pages);
3720         memset(vmcs, 0, vmcs_config.size);
3721         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3722         return vmcs;
3723 }
3724
3725 static struct vmcs *alloc_vmcs(void)
3726 {
3727         return alloc_vmcs_cpu(raw_smp_processor_id());
3728 }
3729
3730 static void free_vmcs(struct vmcs *vmcs)
3731 {
3732         free_pages((unsigned long)vmcs, vmcs_config.order);
3733 }
3734
3735 /*
3736  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3737  */
3738 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3739 {
3740         if (!loaded_vmcs->vmcs)
3741                 return;
3742         loaded_vmcs_clear(loaded_vmcs);
3743         free_vmcs(loaded_vmcs->vmcs);
3744         loaded_vmcs->vmcs = NULL;
3745         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3746 }
3747
3748 static void free_kvm_area(void)
3749 {
3750         int cpu;
3751
3752         for_each_possible_cpu(cpu) {
3753                 free_vmcs(per_cpu(vmxarea, cpu));
3754                 per_cpu(vmxarea, cpu) = NULL;
3755         }
3756 }
3757
3758 static void init_vmcs_shadow_fields(void)
3759 {
3760         int i, j;
3761
3762         /* No checks for read only fields yet */
3763
3764         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3765                 switch (shadow_read_write_fields[i]) {
3766                 case GUEST_BNDCFGS:
3767                         if (!kvm_mpx_supported())
3768                                 continue;
3769                         break;
3770                 default:
3771                         break;
3772                 }
3773
3774                 if (j < i)
3775                         shadow_read_write_fields[j] =
3776                                 shadow_read_write_fields[i];
3777                 j++;
3778         }
3779         max_shadow_read_write_fields = j;
3780
3781         /* shadowed fields guest access without vmexit */
3782         for (i = 0; i < max_shadow_read_write_fields; i++) {
3783                 clear_bit(shadow_read_write_fields[i],
3784                           vmx_vmwrite_bitmap);
3785                 clear_bit(shadow_read_write_fields[i],
3786                           vmx_vmread_bitmap);
3787         }
3788         for (i = 0; i < max_shadow_read_only_fields; i++)
3789                 clear_bit(shadow_read_only_fields[i],
3790                           vmx_vmread_bitmap);
3791 }
3792
3793 static __init int alloc_kvm_area(void)
3794 {
3795         int cpu;
3796
3797         for_each_possible_cpu(cpu) {
3798                 struct vmcs *vmcs;
3799
3800                 vmcs = alloc_vmcs_cpu(cpu);
3801                 if (!vmcs) {
3802                         free_kvm_area();
3803                         return -ENOMEM;
3804                 }
3805
3806                 per_cpu(vmxarea, cpu) = vmcs;
3807         }
3808         return 0;
3809 }
3810
3811 static bool emulation_required(struct kvm_vcpu *vcpu)
3812 {
3813         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3814 }
3815
3816 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3817                 struct kvm_segment *save)
3818 {
3819         if (!emulate_invalid_guest_state) {
3820                 /*
3821                  * CS and SS RPL should be equal during guest entry according
3822                  * to VMX spec, but in reality it is not always so. Since vcpu
3823                  * is in the middle of the transition from real mode to
3824                  * protected mode it is safe to assume that RPL 0 is a good
3825                  * default value.
3826                  */
3827                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3828                         save->selector &= ~SEGMENT_RPL_MASK;
3829                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3830                 save->s = 1;
3831         }
3832         vmx_set_segment(vcpu, save, seg);
3833 }
3834
3835 static void enter_pmode(struct kvm_vcpu *vcpu)
3836 {
3837         unsigned long flags;
3838         struct vcpu_vmx *vmx = to_vmx(vcpu);
3839
3840         /*
3841          * Update real mode segment cache. It may be not up-to-date if sement
3842          * register was written while vcpu was in a guest mode.
3843          */
3844         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3845         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3846         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3847         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3848         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3849         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3850
3851         vmx->rmode.vm86_active = 0;
3852
3853         vmx_segment_cache_clear(vmx);
3854
3855         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3856
3857         flags = vmcs_readl(GUEST_RFLAGS);
3858         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3859         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3860         vmcs_writel(GUEST_RFLAGS, flags);
3861
3862         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3863                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3864
3865         update_exception_bitmap(vcpu);
3866
3867         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3868         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3869         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3870         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3871         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3872         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3873 }
3874
3875 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3876 {
3877         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3878         struct kvm_segment var = *save;
3879
3880         var.dpl = 0x3;
3881         if (seg == VCPU_SREG_CS)
3882                 var.type = 0x3;
3883
3884         if (!emulate_invalid_guest_state) {
3885                 var.selector = var.base >> 4;
3886                 var.base = var.base & 0xffff0;
3887                 var.limit = 0xffff;
3888                 var.g = 0;
3889                 var.db = 0;
3890                 var.present = 1;
3891                 var.s = 1;
3892                 var.l = 0;
3893                 var.unusable = 0;
3894                 var.type = 0x3;
3895                 var.avl = 0;
3896                 if (save->base & 0xf)
3897                         printk_once(KERN_WARNING "kvm: segment base is not "
3898                                         "paragraph aligned when entering "
3899                                         "protected mode (seg=%d)", seg);
3900         }
3901
3902         vmcs_write16(sf->selector, var.selector);
3903         vmcs_writel(sf->base, var.base);
3904         vmcs_write32(sf->limit, var.limit);
3905         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3906 }
3907
3908 static void enter_rmode(struct kvm_vcpu *vcpu)
3909 {
3910         unsigned long flags;
3911         struct vcpu_vmx *vmx = to_vmx(vcpu);
3912
3913         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3914         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3915         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3916         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3917         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3918         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3919         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3920
3921         vmx->rmode.vm86_active = 1;
3922
3923         /*
3924          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3925          * vcpu. Warn the user that an update is overdue.
3926          */
3927         if (!vcpu->kvm->arch.tss_addr)
3928                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3929                              "called before entering vcpu\n");
3930
3931         vmx_segment_cache_clear(vmx);
3932
3933         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3934         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3935         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3936
3937         flags = vmcs_readl(GUEST_RFLAGS);
3938         vmx->rmode.save_rflags = flags;
3939
3940         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3941
3942         vmcs_writel(GUEST_RFLAGS, flags);
3943         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3944         update_exception_bitmap(vcpu);
3945
3946         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3947         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3948         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3949         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3950         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3951         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3952
3953         kvm_mmu_reset_context(vcpu);
3954 }
3955
3956 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3957 {
3958         struct vcpu_vmx *vmx = to_vmx(vcpu);
3959         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3960
3961         if (!msr)
3962                 return;
3963
3964         /*
3965          * Force kernel_gs_base reloading before EFER changes, as control
3966          * of this msr depends on is_long_mode().
3967          */
3968         vmx_load_host_state(to_vmx(vcpu));
3969         vcpu->arch.efer = efer;
3970         if (efer & EFER_LMA) {
3971                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3972                 msr->data = efer;
3973         } else {
3974                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3975
3976                 msr->data = efer & ~EFER_LME;
3977         }
3978         setup_msrs(vmx);
3979 }
3980
3981 #ifdef CONFIG_X86_64
3982
3983 static void enter_lmode(struct kvm_vcpu *vcpu)
3984 {
3985         u32 guest_tr_ar;
3986
3987         vmx_segment_cache_clear(to_vmx(vcpu));
3988
3989         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3990         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3991                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3992                                      __func__);
3993                 vmcs_write32(GUEST_TR_AR_BYTES,
3994                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3995                              | VMX_AR_TYPE_BUSY_64_TSS);
3996         }
3997         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3998 }
3999
4000 static void exit_lmode(struct kvm_vcpu *vcpu)
4001 {
4002         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4003         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4004 }
4005
4006 #endif
4007
4008 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4009 {
4010         if (enable_ept) {
4011                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4012                         return;
4013                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
4014         } else {
4015                 vpid_sync_context(vpid);
4016         }
4017 }
4018
4019 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4020 {
4021         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4022 }
4023
4024 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4025 {
4026         if (enable_ept)
4027                 vmx_flush_tlb(vcpu);
4028 }
4029
4030 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4031 {
4032         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4033
4034         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4035         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4036 }
4037
4038 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4039 {
4040         if (enable_ept && is_paging(vcpu))
4041                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4042         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4043 }
4044
4045 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4046 {
4047         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4048
4049         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4050         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4051 }
4052
4053 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4054 {
4055         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4056
4057         if (!test_bit(VCPU_EXREG_PDPTR,
4058                       (unsigned long *)&vcpu->arch.regs_dirty))
4059                 return;
4060
4061         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4062                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4063                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4064                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4065                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4066         }
4067 }
4068
4069 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4070 {
4071         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4072
4073         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4074                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4075                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4076                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4077                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4078         }
4079
4080         __set_bit(VCPU_EXREG_PDPTR,
4081                   (unsigned long *)&vcpu->arch.regs_avail);
4082         __set_bit(VCPU_EXREG_PDPTR,
4083                   (unsigned long *)&vcpu->arch.regs_dirty);
4084 }
4085
4086 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4087 {
4088         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4089         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4090         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4091
4092         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4093                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4094             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4095                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4096
4097         return fixed_bits_valid(val, fixed0, fixed1);
4098 }
4099
4100 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4101 {
4102         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4103         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4104
4105         return fixed_bits_valid(val, fixed0, fixed1);
4106 }
4107
4108 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4109 {
4110         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4111         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4112
4113         return fixed_bits_valid(val, fixed0, fixed1);
4114 }
4115
4116 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4117 #define nested_guest_cr4_valid  nested_cr4_valid
4118 #define nested_host_cr4_valid   nested_cr4_valid
4119
4120 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4121
4122 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4123                                         unsigned long cr0,
4124                                         struct kvm_vcpu *vcpu)
4125 {
4126         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4127                 vmx_decache_cr3(vcpu);
4128         if (!(cr0 & X86_CR0_PG)) {
4129                 /* From paging/starting to nonpaging */
4130                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4131                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4132                              (CPU_BASED_CR3_LOAD_EXITING |
4133                               CPU_BASED_CR3_STORE_EXITING));
4134                 vcpu->arch.cr0 = cr0;
4135                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4136         } else if (!is_paging(vcpu)) {
4137                 /* From nonpaging to paging */
4138                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4139                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4140                              ~(CPU_BASED_CR3_LOAD_EXITING |
4141                                CPU_BASED_CR3_STORE_EXITING));
4142                 vcpu->arch.cr0 = cr0;
4143                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4144         }
4145
4146         if (!(cr0 & X86_CR0_WP))
4147                 *hw_cr0 &= ~X86_CR0_WP;
4148 }
4149
4150 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4151 {
4152         struct vcpu_vmx *vmx = to_vmx(vcpu);
4153         unsigned long hw_cr0;
4154
4155         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4156         if (enable_unrestricted_guest)
4157                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4158         else {
4159                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4160
4161                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4162                         enter_pmode(vcpu);
4163
4164                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4165                         enter_rmode(vcpu);
4166         }
4167
4168 #ifdef CONFIG_X86_64
4169         if (vcpu->arch.efer & EFER_LME) {
4170                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4171                         enter_lmode(vcpu);
4172                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4173                         exit_lmode(vcpu);
4174         }
4175 #endif
4176
4177         if (enable_ept)
4178                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4179
4180         vmcs_writel(CR0_READ_SHADOW, cr0);
4181         vmcs_writel(GUEST_CR0, hw_cr0);
4182         vcpu->arch.cr0 = cr0;
4183
4184         /* depends on vcpu->arch.cr0 to be set to a new value */
4185         vmx->emulation_required = emulation_required(vcpu);
4186 }
4187
4188 static u64 construct_eptp(unsigned long root_hpa)
4189 {
4190         u64 eptp;
4191
4192         /* TODO write the value reading from MSR */
4193         eptp = VMX_EPT_DEFAULT_MT |
4194                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4195         if (enable_ept_ad_bits)
4196                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4197         eptp |= (root_hpa & PAGE_MASK);
4198
4199         return eptp;
4200 }
4201
4202 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4203 {
4204         unsigned long guest_cr3;
4205         u64 eptp;
4206
4207         guest_cr3 = cr3;
4208         if (enable_ept) {
4209                 eptp = construct_eptp(cr3);
4210                 vmcs_write64(EPT_POINTER, eptp);
4211                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4212                         guest_cr3 = kvm_read_cr3(vcpu);
4213                 else
4214                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4215                 ept_load_pdptrs(vcpu);
4216         }
4217
4218         vmx_flush_tlb(vcpu);
4219         vmcs_writel(GUEST_CR3, guest_cr3);
4220 }
4221
4222 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4223 {
4224         /*
4225          * Pass through host's Machine Check Enable value to hw_cr4, which
4226          * is in force while we are in guest mode.  Do not let guests control
4227          * this bit, even if host CR4.MCE == 0.
4228          */
4229         unsigned long hw_cr4 =
4230                 (cr4_read_shadow() & X86_CR4_MCE) |
4231                 (cr4 & ~X86_CR4_MCE) |
4232                 (to_vmx(vcpu)->rmode.vm86_active ?
4233                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4234
4235         if (cr4 & X86_CR4_VMXE) {
4236                 /*
4237                  * To use VMXON (and later other VMX instructions), a guest
4238                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4239                  * So basically the check on whether to allow nested VMX
4240                  * is here.
4241                  */
4242                 if (!nested_vmx_allowed(vcpu))
4243                         return 1;
4244         }
4245
4246         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4247                 return 1;
4248
4249         vcpu->arch.cr4 = cr4;
4250         if (enable_ept) {
4251                 if (!is_paging(vcpu)) {
4252                         hw_cr4 &= ~X86_CR4_PAE;
4253                         hw_cr4 |= X86_CR4_PSE;
4254                 } else if (!(cr4 & X86_CR4_PAE)) {
4255                         hw_cr4 &= ~X86_CR4_PAE;
4256                 }
4257         }
4258
4259         if (!enable_unrestricted_guest && !is_paging(vcpu))
4260                 /*
4261                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4262                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4263                  * to be manually disabled when guest switches to non-paging
4264                  * mode.
4265                  *
4266                  * If !enable_unrestricted_guest, the CPU is always running
4267                  * with CR0.PG=1 and CR4 needs to be modified.
4268                  * If enable_unrestricted_guest, the CPU automatically
4269                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4270                  */
4271                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4272
4273         vmcs_writel(CR4_READ_SHADOW, cr4);
4274         vmcs_writel(GUEST_CR4, hw_cr4);
4275         return 0;
4276 }
4277
4278 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4279                             struct kvm_segment *var, int seg)
4280 {
4281         struct vcpu_vmx *vmx = to_vmx(vcpu);
4282         u32 ar;
4283
4284         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4285                 *var = vmx->rmode.segs[seg];
4286                 if (seg == VCPU_SREG_TR
4287                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4288                         return;
4289                 var->base = vmx_read_guest_seg_base(vmx, seg);
4290                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4291                 return;
4292         }
4293         var->base = vmx_read_guest_seg_base(vmx, seg);
4294         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4295         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4296         ar = vmx_read_guest_seg_ar(vmx, seg);
4297         var->unusable = (ar >> 16) & 1;
4298         var->type = ar & 15;
4299         var->s = (ar >> 4) & 1;
4300         var->dpl = (ar >> 5) & 3;
4301         /*
4302          * Some userspaces do not preserve unusable property. Since usable
4303          * segment has to be present according to VMX spec we can use present
4304          * property to amend userspace bug by making unusable segment always
4305          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4306          * segment as unusable.
4307          */
4308         var->present = !var->unusable;
4309         var->avl = (ar >> 12) & 1;
4310         var->l = (ar >> 13) & 1;
4311         var->db = (ar >> 14) & 1;
4312         var->g = (ar >> 15) & 1;
4313 }
4314
4315 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4316 {
4317         struct kvm_segment s;
4318
4319         if (to_vmx(vcpu)->rmode.vm86_active) {
4320                 vmx_get_segment(vcpu, &s, seg);
4321                 return s.base;
4322         }
4323         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4324 }
4325
4326 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4327 {
4328         struct vcpu_vmx *vmx = to_vmx(vcpu);
4329
4330         if (unlikely(vmx->rmode.vm86_active))
4331                 return 0;
4332         else {
4333                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4334                 return VMX_AR_DPL(ar);
4335         }
4336 }
4337
4338 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4339 {
4340         u32 ar;
4341
4342         if (var->unusable || !var->present)
4343                 ar = 1 << 16;
4344         else {
4345                 ar = var->type & 15;
4346                 ar |= (var->s & 1) << 4;
4347                 ar |= (var->dpl & 3) << 5;
4348                 ar |= (var->present & 1) << 7;
4349                 ar |= (var->avl & 1) << 12;
4350                 ar |= (var->l & 1) << 13;
4351                 ar |= (var->db & 1) << 14;
4352                 ar |= (var->g & 1) << 15;
4353         }
4354
4355         return ar;
4356 }
4357
4358 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4359                             struct kvm_segment *var, int seg)
4360 {
4361         struct vcpu_vmx *vmx = to_vmx(vcpu);
4362         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4363
4364         vmx_segment_cache_clear(vmx);
4365
4366         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4367                 vmx->rmode.segs[seg] = *var;
4368                 if (seg == VCPU_SREG_TR)
4369                         vmcs_write16(sf->selector, var->selector);
4370                 else if (var->s)
4371                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4372                 goto out;
4373         }
4374
4375         vmcs_writel(sf->base, var->base);
4376         vmcs_write32(sf->limit, var->limit);
4377         vmcs_write16(sf->selector, var->selector);
4378
4379         /*
4380          *   Fix the "Accessed" bit in AR field of segment registers for older
4381          * qemu binaries.
4382          *   IA32 arch specifies that at the time of processor reset the
4383          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4384          * is setting it to 0 in the userland code. This causes invalid guest
4385          * state vmexit when "unrestricted guest" mode is turned on.
4386          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4387          * tree. Newer qemu binaries with that qemu fix would not need this
4388          * kvm hack.
4389          */
4390         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4391                 var->type |= 0x1; /* Accessed */
4392
4393         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4394
4395 out:
4396         vmx->emulation_required = emulation_required(vcpu);
4397 }
4398
4399 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4400 {
4401         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4402
4403         *db = (ar >> 14) & 1;
4404         *l = (ar >> 13) & 1;
4405 }
4406
4407 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4408 {
4409         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4410         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4411 }
4412
4413 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4414 {
4415         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4416         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4417 }
4418
4419 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4420 {
4421         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4422         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4423 }
4424
4425 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4426 {
4427         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4428         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4429 }
4430
4431 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4432 {
4433         struct kvm_segment var;
4434         u32 ar;
4435
4436         vmx_get_segment(vcpu, &var, seg);
4437         var.dpl = 0x3;
4438         if (seg == VCPU_SREG_CS)
4439                 var.type = 0x3;
4440         ar = vmx_segment_access_rights(&var);
4441
4442         if (var.base != (var.selector << 4))
4443                 return false;
4444         if (var.limit != 0xffff)
4445                 return false;
4446         if (ar != 0xf3)
4447                 return false;
4448
4449         return true;
4450 }
4451
4452 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4453 {
4454         struct kvm_segment cs;
4455         unsigned int cs_rpl;
4456
4457         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4458         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4459
4460         if (cs.unusable)
4461                 return false;
4462         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4463                 return false;
4464         if (!cs.s)
4465                 return false;
4466         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4467                 if (cs.dpl > cs_rpl)
4468                         return false;
4469         } else {
4470                 if (cs.dpl != cs_rpl)
4471                         return false;
4472         }
4473         if (!cs.present)
4474                 return false;
4475
4476         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4477         return true;
4478 }
4479
4480 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4481 {
4482         struct kvm_segment ss;
4483         unsigned int ss_rpl;
4484
4485         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4486         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4487
4488         if (ss.unusable)
4489                 return true;
4490         if (ss.type != 3 && ss.type != 7)
4491                 return false;
4492         if (!ss.s)
4493                 return false;
4494         if (ss.dpl != ss_rpl) /* DPL != RPL */
4495                 return false;
4496         if (!ss.present)
4497                 return false;
4498
4499         return true;
4500 }
4501
4502 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4503 {
4504         struct kvm_segment var;
4505         unsigned int rpl;
4506
4507         vmx_get_segment(vcpu, &var, seg);
4508         rpl = var.selector & SEGMENT_RPL_MASK;
4509
4510         if (var.unusable)
4511                 return true;
4512         if (!var.s)
4513                 return false;
4514         if (!var.present)
4515                 return false;
4516         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4517                 if (var.dpl < rpl) /* DPL < RPL */
4518                         return false;
4519         }
4520
4521         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4522          * rights flags
4523          */
4524         return true;
4525 }
4526
4527 static bool tr_valid(struct kvm_vcpu *vcpu)
4528 {
4529         struct kvm_segment tr;
4530
4531         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4532
4533         if (tr.unusable)
4534                 return false;
4535         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4536                 return false;
4537         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4538                 return false;
4539         if (!tr.present)
4540                 return false;
4541
4542         return true;
4543 }
4544
4545 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4546 {
4547         struct kvm_segment ldtr;
4548
4549         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4550
4551         if (ldtr.unusable)
4552                 return true;
4553         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4554                 return false;
4555         if (ldtr.type != 2)
4556                 return false;
4557         if (!ldtr.present)
4558                 return false;
4559
4560         return true;
4561 }
4562
4563 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4564 {
4565         struct kvm_segment cs, ss;
4566
4567         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4568         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4569
4570         return ((cs.selector & SEGMENT_RPL_MASK) ==
4571                  (ss.selector & SEGMENT_RPL_MASK));
4572 }
4573
4574 /*
4575  * Check if guest state is valid. Returns true if valid, false if
4576  * not.
4577  * We assume that registers are always usable
4578  */
4579 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4580 {
4581         if (enable_unrestricted_guest)
4582                 return true;
4583
4584         /* real mode guest state checks */
4585         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4586                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4587                         return false;
4588                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4589                         return false;
4590                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4591                         return false;
4592                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4593                         return false;
4594                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4595                         return false;
4596                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4597                         return false;
4598         } else {
4599         /* protected mode guest state checks */
4600                 if (!cs_ss_rpl_check(vcpu))
4601                         return false;
4602                 if (!code_segment_valid(vcpu))
4603                         return false;
4604                 if (!stack_segment_valid(vcpu))
4605                         return false;
4606                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4607                         return false;
4608                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4609                         return false;
4610                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4611                         return false;
4612                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4613                         return false;
4614                 if (!tr_valid(vcpu))
4615                         return false;
4616                 if (!ldtr_valid(vcpu))
4617                         return false;
4618         }
4619         /* TODO:
4620          * - Add checks on RIP
4621          * - Add checks on RFLAGS
4622          */
4623
4624         return true;
4625 }
4626
4627 static int init_rmode_tss(struct kvm *kvm)
4628 {
4629         gfn_t fn;
4630         u16 data = 0;
4631         int idx, r;
4632
4633         idx = srcu_read_lock(&kvm->srcu);
4634         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4635         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4636         if (r < 0)
4637                 goto out;
4638         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4639         r = kvm_write_guest_page(kvm, fn++, &data,
4640                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4641         if (r < 0)
4642                 goto out;
4643         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4644         if (r < 0)
4645                 goto out;
4646         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4647         if (r < 0)
4648                 goto out;
4649         data = ~0;
4650         r = kvm_write_guest_page(kvm, fn, &data,
4651                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4652                                  sizeof(u8));
4653 out:
4654         srcu_read_unlock(&kvm->srcu, idx);
4655         return r;
4656 }
4657
4658 static int init_rmode_identity_map(struct kvm *kvm)
4659 {
4660         int i, idx, r = 0;
4661         kvm_pfn_t identity_map_pfn;
4662         u32 tmp;
4663
4664         if (!enable_ept)
4665                 return 0;
4666
4667         /* Protect kvm->arch.ept_identity_pagetable_done. */
4668         mutex_lock(&kvm->slots_lock);
4669
4670         if (likely(kvm->arch.ept_identity_pagetable_done))
4671                 goto out2;
4672
4673         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4674
4675         r = alloc_identity_pagetable(kvm);
4676         if (r < 0)
4677                 goto out2;
4678
4679         idx = srcu_read_lock(&kvm->srcu);
4680         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4681         if (r < 0)
4682                 goto out;
4683         /* Set up identity-mapping pagetable for EPT in real mode */
4684         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4685                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4686                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4687                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4688                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4689                 if (r < 0)
4690                         goto out;
4691         }
4692         kvm->arch.ept_identity_pagetable_done = true;
4693
4694 out:
4695         srcu_read_unlock(&kvm->srcu, idx);
4696
4697 out2:
4698         mutex_unlock(&kvm->slots_lock);
4699         return r;
4700 }
4701
4702 static void seg_setup(int seg)
4703 {
4704         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4705         unsigned int ar;
4706
4707         vmcs_write16(sf->selector, 0);
4708         vmcs_writel(sf->base, 0);
4709         vmcs_write32(sf->limit, 0xffff);
4710         ar = 0x93;
4711         if (seg == VCPU_SREG_CS)
4712                 ar |= 0x08; /* code segment */
4713
4714         vmcs_write32(sf->ar_bytes, ar);
4715 }
4716
4717 static int alloc_apic_access_page(struct kvm *kvm)
4718 {
4719         struct page *page;
4720         int r = 0;
4721
4722         mutex_lock(&kvm->slots_lock);
4723         if (kvm->arch.apic_access_page_done)
4724                 goto out;
4725         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4726                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4727         if (r)
4728                 goto out;
4729
4730         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4731         if (is_error_page(page)) {
4732                 r = -EFAULT;
4733                 goto out;
4734         }
4735
4736         /*
4737          * Do not pin the page in memory, so that memory hot-unplug
4738          * is able to migrate it.
4739          */
4740         put_page(page);
4741         kvm->arch.apic_access_page_done = true;
4742 out:
4743         mutex_unlock(&kvm->slots_lock);
4744         return r;
4745 }
4746
4747 static int alloc_identity_pagetable(struct kvm *kvm)
4748 {
4749         /* Called with kvm->slots_lock held. */
4750
4751         int r = 0;
4752
4753         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4754
4755         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4756                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4757
4758         return r;
4759 }
4760
4761 static int allocate_vpid(void)
4762 {
4763         int vpid;
4764
4765         if (!enable_vpid)
4766                 return 0;
4767         spin_lock(&vmx_vpid_lock);
4768         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4769         if (vpid < VMX_NR_VPIDS)
4770                 __set_bit(vpid, vmx_vpid_bitmap);
4771         else
4772                 vpid = 0;
4773         spin_unlock(&vmx_vpid_lock);
4774         return vpid;
4775 }
4776
4777 static void free_vpid(int vpid)
4778 {
4779         if (!enable_vpid || vpid == 0)
4780                 return;
4781         spin_lock(&vmx_vpid_lock);
4782         __clear_bit(vpid, vmx_vpid_bitmap);
4783         spin_unlock(&vmx_vpid_lock);
4784 }
4785
4786 #define MSR_TYPE_R      1
4787 #define MSR_TYPE_W      2
4788 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4789                                                 u32 msr, int type)
4790 {
4791         int f = sizeof(unsigned long);
4792
4793         if (!cpu_has_vmx_msr_bitmap())
4794                 return;
4795
4796         /*
4797          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4798          * have the write-low and read-high bitmap offsets the wrong way round.
4799          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4800          */
4801         if (msr <= 0x1fff) {
4802                 if (type & MSR_TYPE_R)
4803                         /* read-low */
4804                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4805
4806                 if (type & MSR_TYPE_W)
4807                         /* write-low */
4808                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4809
4810         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4811                 msr &= 0x1fff;
4812                 if (type & MSR_TYPE_R)
4813                         /* read-high */
4814                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4815
4816                 if (type & MSR_TYPE_W)
4817                         /* write-high */
4818                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4819
4820         }
4821 }
4822
4823 /*
4824  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4825  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4826  */
4827 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4828                                                unsigned long *msr_bitmap_nested,
4829                                                u32 msr, int type)
4830 {
4831         int f = sizeof(unsigned long);
4832
4833         if (!cpu_has_vmx_msr_bitmap()) {
4834                 WARN_ON(1);
4835                 return;
4836         }
4837
4838         /*
4839          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4840          * have the write-low and read-high bitmap offsets the wrong way round.
4841          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4842          */
4843         if (msr <= 0x1fff) {
4844                 if (type & MSR_TYPE_R &&
4845                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4846                         /* read-low */
4847                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4848
4849                 if (type & MSR_TYPE_W &&
4850                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4851                         /* write-low */
4852                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4853
4854         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4855                 msr &= 0x1fff;
4856                 if (type & MSR_TYPE_R &&
4857                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4858                         /* read-high */
4859                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4860
4861                 if (type & MSR_TYPE_W &&
4862                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4863                         /* write-high */
4864                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4865
4866         }
4867 }
4868
4869 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4870 {
4871         if (!longmode_only)
4872                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4873                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4874         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4875                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4876 }
4877
4878 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4879 {
4880         if (apicv_active) {
4881                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4882                                 msr, type);
4883                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4884                                 msr, type);
4885         } else {
4886                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4887                                 msr, type);
4888                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4889                                 msr, type);
4890         }
4891 }
4892
4893 static bool vmx_get_enable_apicv(void)
4894 {
4895         return enable_apicv;
4896 }
4897
4898 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4899 {
4900         struct vcpu_vmx *vmx = to_vmx(vcpu);
4901         int max_irr;
4902         void *vapic_page;
4903         u16 status;
4904
4905         if (vmx->nested.pi_desc &&
4906             vmx->nested.pi_pending) {
4907                 vmx->nested.pi_pending = false;
4908                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4909                         return;
4910
4911                 max_irr = find_last_bit(
4912                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4913
4914                 if (max_irr == 256)
4915                         return;
4916
4917                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4918                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4919                 kunmap(vmx->nested.virtual_apic_page);
4920
4921                 status = vmcs_read16(GUEST_INTR_STATUS);
4922                 if ((u8)max_irr > ((u8)status & 0xff)) {
4923                         status &= ~0xff;
4924                         status |= (u8)max_irr;
4925                         vmcs_write16(GUEST_INTR_STATUS, status);
4926                 }
4927         }
4928 }
4929
4930 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4931 {
4932 #ifdef CONFIG_SMP
4933         if (vcpu->mode == IN_GUEST_MODE) {
4934                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4935
4936                 /*
4937                  * Currently, we don't support urgent interrupt,
4938                  * all interrupts are recognized as non-urgent
4939                  * interrupt, so we cannot post interrupts when
4940                  * 'SN' is set.
4941                  *
4942                  * If the vcpu is in guest mode, it means it is
4943                  * running instead of being scheduled out and
4944                  * waiting in the run queue, and that's the only
4945                  * case when 'SN' is set currently, warning if
4946                  * 'SN' is set.
4947                  */
4948                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4949
4950                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4951                                 POSTED_INTR_VECTOR);
4952                 return true;
4953         }
4954 #endif
4955         return false;
4956 }
4957
4958 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4959                                                 int vector)
4960 {
4961         struct vcpu_vmx *vmx = to_vmx(vcpu);
4962
4963         if (is_guest_mode(vcpu) &&
4964             vector == vmx->nested.posted_intr_nv) {
4965                 /* the PIR and ON have been set by L1. */
4966                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4967                 /*
4968                  * If a posted intr is not recognized by hardware,
4969                  * we will accomplish it in the next vmentry.
4970                  */
4971                 vmx->nested.pi_pending = true;
4972                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4973                 return 0;
4974         }
4975         return -1;
4976 }
4977 /*
4978  * Send interrupt to vcpu via posted interrupt way.
4979  * 1. If target vcpu is running(non-root mode), send posted interrupt
4980  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4981  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4982  * interrupt from PIR in next vmentry.
4983  */
4984 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4985 {
4986         struct vcpu_vmx *vmx = to_vmx(vcpu);
4987         int r;
4988
4989         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4990         if (!r)
4991                 return;
4992
4993         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4994                 return;
4995
4996         /* If a previous notification has sent the IPI, nothing to do.  */
4997         if (pi_test_and_set_on(&vmx->pi_desc))
4998                 return;
4999
5000         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5001                 kvm_vcpu_kick(vcpu);
5002 }
5003
5004 /*
5005  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5006  * will not change in the lifetime of the guest.
5007  * Note that host-state that does change is set elsewhere. E.g., host-state
5008  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5009  */
5010 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5011 {
5012         u32 low32, high32;
5013         unsigned long tmpl;
5014         struct desc_ptr dt;
5015         unsigned long cr0, cr4;
5016
5017         cr0 = read_cr0();
5018         WARN_ON(cr0 & X86_CR0_TS);
5019         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5020         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
5021
5022         /* Save the most likely value for this task's CR4 in the VMCS. */
5023         cr4 = cr4_read_shadow();
5024         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5025         vmx->host_state.vmcs_host_cr4 = cr4;
5026
5027         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5028 #ifdef CONFIG_X86_64
5029         /*
5030          * Load null selectors, so we can avoid reloading them in
5031          * __vmx_load_host_state(), in case userspace uses the null selectors
5032          * too (the expected case).
5033          */
5034         vmcs_write16(HOST_DS_SELECTOR, 0);
5035         vmcs_write16(HOST_ES_SELECTOR, 0);
5036 #else
5037         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5038         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5039 #endif
5040         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5041         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5042
5043         native_store_idt(&dt);
5044         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5045         vmx->host_idt_base = dt.address;
5046
5047         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5048
5049         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5050         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5051         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5052         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5053
5054         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5055                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5056                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5057         }
5058 }
5059
5060 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5061 {
5062         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5063         if (enable_ept)
5064                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5065         if (is_guest_mode(&vmx->vcpu))
5066                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5067                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5068         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5069 }
5070
5071 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5072 {
5073         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5074
5075         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5076                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5077         /* Enable the preemption timer dynamically */
5078         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5079         return pin_based_exec_ctrl;
5080 }
5081
5082 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5083 {
5084         struct vcpu_vmx *vmx = to_vmx(vcpu);
5085
5086         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5087         if (cpu_has_secondary_exec_ctrls()) {
5088                 if (kvm_vcpu_apicv_active(vcpu))
5089                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5090                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5091                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5092                 else
5093                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5094                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5095                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5096         }
5097
5098         if (cpu_has_vmx_msr_bitmap())
5099                 vmx_set_msr_bitmap(vcpu);
5100 }
5101
5102 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5103 {
5104         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5105
5106         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5107                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5108
5109         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5110                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5111 #ifdef CONFIG_X86_64
5112                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5113                                 CPU_BASED_CR8_LOAD_EXITING;
5114 #endif
5115         }
5116         if (!enable_ept)
5117                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5118                                 CPU_BASED_CR3_LOAD_EXITING  |
5119                                 CPU_BASED_INVLPG_EXITING;
5120         return exec_control;
5121 }
5122
5123 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5124 {
5125         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5126         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5127                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5128         if (vmx->vpid == 0)
5129                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5130         if (!enable_ept) {
5131                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5132                 enable_unrestricted_guest = 0;
5133                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5134                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5135         }
5136         if (!enable_unrestricted_guest)
5137                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5138         if (!ple_gap)
5139                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5140         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5141                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5142                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5143         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5144         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5145            (handle_vmptrld).
5146            We can NOT enable shadow_vmcs here because we don't have yet
5147            a current VMCS12
5148         */
5149         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5150
5151         if (!enable_pml)
5152                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5153
5154         return exec_control;
5155 }
5156
5157 static void ept_set_mmio_spte_mask(void)
5158 {
5159         /*
5160          * EPT Misconfigurations can be generated if the value of bits 2:0
5161          * of an EPT paging-structure entry is 110b (write/execute).
5162          */
5163         kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5164 }
5165
5166 #define VMX_XSS_EXIT_BITMAP 0
5167 /*
5168  * Sets up the vmcs for emulated real mode.
5169  */
5170 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5171 {
5172 #ifdef CONFIG_X86_64
5173         unsigned long a;
5174 #endif
5175         int i;
5176
5177         /* I/O */
5178         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5179         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5180
5181         if (enable_shadow_vmcs) {
5182                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5183                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5184         }
5185         if (cpu_has_vmx_msr_bitmap())
5186                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5187
5188         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5189
5190         /* Control */
5191         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5192         vmx->hv_deadline_tsc = -1;
5193
5194         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5195
5196         if (cpu_has_secondary_exec_ctrls()) {
5197                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5198                                 vmx_secondary_exec_control(vmx));
5199         }
5200
5201         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5202                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5203                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5204                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5205                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5206
5207                 vmcs_write16(GUEST_INTR_STATUS, 0);
5208
5209                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5210                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5211         }
5212
5213         if (ple_gap) {
5214                 vmcs_write32(PLE_GAP, ple_gap);
5215                 vmx->ple_window = ple_window;
5216                 vmx->ple_window_dirty = true;
5217         }
5218
5219         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5220         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5221         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5222
5223         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5224         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5225         vmx_set_constant_host_state(vmx);
5226 #ifdef CONFIG_X86_64
5227         rdmsrl(MSR_FS_BASE, a);
5228         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5229         rdmsrl(MSR_GS_BASE, a);
5230         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5231 #else
5232         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5233         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5234 #endif
5235
5236         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5237         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5238         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5239         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5240         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5241
5242         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5243                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5244
5245         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5246                 u32 index = vmx_msr_index[i];
5247                 u32 data_low, data_high;
5248                 int j = vmx->nmsrs;
5249
5250                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5251                         continue;
5252                 if (wrmsr_safe(index, data_low, data_high) < 0)
5253                         continue;
5254                 vmx->guest_msrs[j].index = i;
5255                 vmx->guest_msrs[j].data = 0;
5256                 vmx->guest_msrs[j].mask = -1ull;
5257                 ++vmx->nmsrs;
5258         }
5259
5260
5261         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5262
5263         /* 22.2.1, 20.8.1 */
5264         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5265
5266         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5267         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5268
5269         set_cr4_guest_host_mask(vmx);
5270
5271         if (vmx_xsaves_supported())
5272                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5273
5274         if (enable_pml) {
5275                 ASSERT(vmx->pml_pg);
5276                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5277                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5278         }
5279
5280         return 0;
5281 }
5282
5283 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5284 {
5285         struct vcpu_vmx *vmx = to_vmx(vcpu);
5286         struct msr_data apic_base_msr;
5287         u64 cr0;
5288
5289         vmx->rmode.vm86_active = 0;
5290
5291         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5292         kvm_set_cr8(vcpu, 0);
5293
5294         if (!init_event) {
5295                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5296                                      MSR_IA32_APICBASE_ENABLE;
5297                 if (kvm_vcpu_is_reset_bsp(vcpu))
5298                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5299                 apic_base_msr.host_initiated = true;
5300                 kvm_set_apic_base(vcpu, &apic_base_msr);
5301         }
5302
5303         vmx_segment_cache_clear(vmx);
5304
5305         seg_setup(VCPU_SREG_CS);
5306         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5307         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5308
5309         seg_setup(VCPU_SREG_DS);
5310         seg_setup(VCPU_SREG_ES);
5311         seg_setup(VCPU_SREG_FS);
5312         seg_setup(VCPU_SREG_GS);
5313         seg_setup(VCPU_SREG_SS);
5314
5315         vmcs_write16(GUEST_TR_SELECTOR, 0);
5316         vmcs_writel(GUEST_TR_BASE, 0);
5317         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5318         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5319
5320         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5321         vmcs_writel(GUEST_LDTR_BASE, 0);
5322         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5323         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5324
5325         if (!init_event) {
5326                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5327                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5328                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5329                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5330         }
5331
5332         vmcs_writel(GUEST_RFLAGS, 0x02);
5333         kvm_rip_write(vcpu, 0xfff0);
5334
5335         vmcs_writel(GUEST_GDTR_BASE, 0);
5336         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5337
5338         vmcs_writel(GUEST_IDTR_BASE, 0);
5339         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5340
5341         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5342         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5343         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5344
5345         setup_msrs(vmx);
5346
5347         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5348
5349         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5350                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5351                 if (cpu_need_tpr_shadow(vcpu))
5352                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5353                                      __pa(vcpu->arch.apic->regs));
5354                 vmcs_write32(TPR_THRESHOLD, 0);
5355         }
5356
5357         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5358
5359         if (kvm_vcpu_apicv_active(vcpu))
5360                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5361
5362         if (vmx->vpid != 0)
5363                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5364
5365         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5366         vmx->vcpu.arch.cr0 = cr0;
5367         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5368         vmx_set_cr4(vcpu, 0);
5369         vmx_set_efer(vcpu, 0);
5370
5371         update_exception_bitmap(vcpu);
5372
5373         vpid_sync_context(vmx->vpid);
5374 }
5375
5376 /*
5377  * In nested virtualization, check if L1 asked to exit on external interrupts.
5378  * For most existing hypervisors, this will always return true.
5379  */
5380 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5381 {
5382         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5383                 PIN_BASED_EXT_INTR_MASK;
5384 }
5385
5386 /*
5387  * In nested virtualization, check if L1 has set
5388  * VM_EXIT_ACK_INTR_ON_EXIT
5389  */
5390 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5391 {
5392         return get_vmcs12(vcpu)->vm_exit_controls &
5393                 VM_EXIT_ACK_INTR_ON_EXIT;
5394 }
5395
5396 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5397 {
5398         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5399                 PIN_BASED_NMI_EXITING;
5400 }
5401
5402 static void enable_irq_window(struct kvm_vcpu *vcpu)
5403 {
5404         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5405                       CPU_BASED_VIRTUAL_INTR_PENDING);
5406 }
5407
5408 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5409 {
5410         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5411                 enable_irq_window(vcpu);
5412                 return;
5413         }
5414
5415         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5416                       CPU_BASED_VIRTUAL_NMI_PENDING);
5417 }
5418
5419 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5420 {
5421         struct vcpu_vmx *vmx = to_vmx(vcpu);
5422         uint32_t intr;
5423         int irq = vcpu->arch.interrupt.nr;
5424
5425         trace_kvm_inj_virq(irq);
5426
5427         ++vcpu->stat.irq_injections;
5428         if (vmx->rmode.vm86_active) {
5429                 int inc_eip = 0;
5430                 if (vcpu->arch.interrupt.soft)
5431                         inc_eip = vcpu->arch.event_exit_inst_len;
5432                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5433                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5434                 return;
5435         }
5436         intr = irq | INTR_INFO_VALID_MASK;
5437         if (vcpu->arch.interrupt.soft) {
5438                 intr |= INTR_TYPE_SOFT_INTR;
5439                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5440                              vmx->vcpu.arch.event_exit_inst_len);
5441         } else
5442                 intr |= INTR_TYPE_EXT_INTR;
5443         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5444 }
5445
5446 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5447 {
5448         struct vcpu_vmx *vmx = to_vmx(vcpu);
5449
5450         if (!is_guest_mode(vcpu)) {
5451                 ++vcpu->stat.nmi_injections;
5452                 vmx->nmi_known_unmasked = false;
5453         }
5454
5455         if (vmx->rmode.vm86_active) {
5456                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5457                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5458                 return;
5459         }
5460
5461         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5462                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5463 }
5464
5465 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5466 {
5467         if (to_vmx(vcpu)->nmi_known_unmasked)
5468                 return false;
5469         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5470 }
5471
5472 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5473 {
5474         struct vcpu_vmx *vmx = to_vmx(vcpu);
5475
5476         vmx->nmi_known_unmasked = !masked;
5477         if (masked)
5478                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5479                               GUEST_INTR_STATE_NMI);
5480         else
5481                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5482                                 GUEST_INTR_STATE_NMI);
5483 }
5484
5485 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5486 {
5487         if (to_vmx(vcpu)->nested.nested_run_pending)
5488                 return 0;
5489
5490         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5491                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5492                    | GUEST_INTR_STATE_NMI));
5493 }
5494
5495 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5496 {
5497         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5498                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5499                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5500                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5501 }
5502
5503 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5504 {
5505         int ret;
5506
5507         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5508                                     PAGE_SIZE * 3);
5509         if (ret)
5510                 return ret;
5511         kvm->arch.tss_addr = addr;
5512         return init_rmode_tss(kvm);
5513 }
5514
5515 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5516 {
5517         switch (vec) {
5518         case BP_VECTOR:
5519                 /*
5520                  * Update instruction length as we may reinject the exception
5521                  * from user space while in guest debugging mode.
5522                  */
5523                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5524                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5525                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5526                         return false;
5527                 /* fall through */
5528         case DB_VECTOR:
5529                 if (vcpu->guest_debug &
5530                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5531                         return false;
5532                 /* fall through */
5533         case DE_VECTOR:
5534         case OF_VECTOR:
5535         case BR_VECTOR:
5536         case UD_VECTOR:
5537         case DF_VECTOR:
5538         case SS_VECTOR:
5539         case GP_VECTOR:
5540         case MF_VECTOR:
5541                 return true;
5542         break;
5543         }
5544         return false;
5545 }
5546
5547 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5548                                   int vec, u32 err_code)
5549 {
5550         /*
5551          * Instruction with address size override prefix opcode 0x67
5552          * Cause the #SS fault with 0 error code in VM86 mode.
5553          */
5554         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5555                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5556                         if (vcpu->arch.halt_request) {
5557                                 vcpu->arch.halt_request = 0;
5558                                 return kvm_vcpu_halt(vcpu);
5559                         }
5560                         return 1;
5561                 }
5562                 return 0;
5563         }
5564
5565         /*
5566          * Forward all other exceptions that are valid in real mode.
5567          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5568          *        the required debugging infrastructure rework.
5569          */
5570         kvm_queue_exception(vcpu, vec);
5571         return 1;
5572 }
5573
5574 /*
5575  * Trigger machine check on the host. We assume all the MSRs are already set up
5576  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5577  * We pass a fake environment to the machine check handler because we want
5578  * the guest to be always treated like user space, no matter what context
5579  * it used internally.
5580  */
5581 static void kvm_machine_check(void)
5582 {
5583 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5584         struct pt_regs regs = {
5585                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5586                 .flags = X86_EFLAGS_IF,
5587         };
5588
5589         do_machine_check(&regs, 0);
5590 #endif
5591 }
5592
5593 static int handle_machine_check(struct kvm_vcpu *vcpu)
5594 {
5595         /* already handled by vcpu_run */
5596         return 1;
5597 }
5598
5599 static int handle_exception(struct kvm_vcpu *vcpu)
5600 {
5601         struct vcpu_vmx *vmx = to_vmx(vcpu);
5602         struct kvm_run *kvm_run = vcpu->run;
5603         u32 intr_info, ex_no, error_code;
5604         unsigned long cr2, rip, dr6;
5605         u32 vect_info;
5606         enum emulation_result er;
5607
5608         vect_info = vmx->idt_vectoring_info;
5609         intr_info = vmx->exit_intr_info;
5610
5611         if (is_machine_check(intr_info))
5612                 return handle_machine_check(vcpu);
5613
5614         if (is_nmi(intr_info))
5615                 return 1;  /* already handled by vmx_vcpu_run() */
5616
5617         if (is_invalid_opcode(intr_info)) {
5618                 if (is_guest_mode(vcpu)) {
5619                         kvm_queue_exception(vcpu, UD_VECTOR);
5620                         return 1;
5621                 }
5622                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5623                 if (er != EMULATE_DONE)
5624                         kvm_queue_exception(vcpu, UD_VECTOR);
5625                 return 1;
5626         }
5627
5628         error_code = 0;
5629         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5630                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5631
5632         /*
5633          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5634          * MMIO, it is better to report an internal error.
5635          * See the comments in vmx_handle_exit.
5636          */
5637         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5638             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5639                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5640                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5641                 vcpu->run->internal.ndata = 3;
5642                 vcpu->run->internal.data[0] = vect_info;
5643                 vcpu->run->internal.data[1] = intr_info;
5644                 vcpu->run->internal.data[2] = error_code;
5645                 return 0;
5646         }
5647
5648         if (is_page_fault(intr_info)) {
5649                 /* EPT won't cause page fault directly */
5650                 BUG_ON(enable_ept);
5651                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5652                 trace_kvm_page_fault(cr2, error_code);
5653
5654                 if (kvm_event_needs_reinjection(vcpu))
5655                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5656                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5657         }
5658
5659         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5660
5661         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5662                 return handle_rmode_exception(vcpu, ex_no, error_code);
5663
5664         switch (ex_no) {
5665         case AC_VECTOR:
5666                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5667                 return 1;
5668         case DB_VECTOR:
5669                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5670                 if (!(vcpu->guest_debug &
5671                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5672                         vcpu->arch.dr6 &= ~15;
5673                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5674                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5675                                 skip_emulated_instruction(vcpu);
5676
5677                         kvm_queue_exception(vcpu, DB_VECTOR);
5678                         return 1;
5679                 }
5680                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5681                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5682                 /* fall through */
5683         case BP_VECTOR:
5684                 /*
5685                  * Update instruction length as we may reinject #BP from
5686                  * user space while in guest debugging mode. Reading it for
5687                  * #DB as well causes no harm, it is not used in that case.
5688                  */
5689                 vmx->vcpu.arch.event_exit_inst_len =
5690                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5691                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5692                 rip = kvm_rip_read(vcpu);
5693                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5694                 kvm_run->debug.arch.exception = ex_no;
5695                 break;
5696         default:
5697                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5698                 kvm_run->ex.exception = ex_no;
5699                 kvm_run->ex.error_code = error_code;
5700                 break;
5701         }
5702         return 0;
5703 }
5704
5705 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5706 {
5707         ++vcpu->stat.irq_exits;
5708         return 1;
5709 }
5710
5711 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5712 {
5713         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5714         return 0;
5715 }
5716
5717 static int handle_io(struct kvm_vcpu *vcpu)
5718 {
5719         unsigned long exit_qualification;
5720         int size, in, string, ret;
5721         unsigned port;
5722
5723         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5724         string = (exit_qualification & 16) != 0;
5725         in = (exit_qualification & 8) != 0;
5726
5727         ++vcpu->stat.io_exits;
5728
5729         if (string || in)
5730                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5731
5732         port = exit_qualification >> 16;
5733         size = (exit_qualification & 7) + 1;
5734
5735         ret = kvm_skip_emulated_instruction(vcpu);
5736
5737         /*
5738          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5739          * KVM_EXIT_DEBUG here.
5740          */
5741         return kvm_fast_pio_out(vcpu, size, port) && ret;
5742 }
5743
5744 static void
5745 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5746 {
5747         /*
5748          * Patch in the VMCALL instruction:
5749          */
5750         hypercall[0] = 0x0f;
5751         hypercall[1] = 0x01;
5752         hypercall[2] = 0xc1;
5753 }
5754
5755 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5756 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5757 {
5758         if (is_guest_mode(vcpu)) {
5759                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5760                 unsigned long orig_val = val;
5761
5762                 /*
5763                  * We get here when L2 changed cr0 in a way that did not change
5764                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5765                  * but did change L0 shadowed bits. So we first calculate the
5766                  * effective cr0 value that L1 would like to write into the
5767                  * hardware. It consists of the L2-owned bits from the new
5768                  * value combined with the L1-owned bits from L1's guest_cr0.
5769                  */
5770                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5771                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5772
5773                 if (!nested_guest_cr0_valid(vcpu, val))
5774                         return 1;
5775
5776                 if (kvm_set_cr0(vcpu, val))
5777                         return 1;
5778                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5779                 return 0;
5780         } else {
5781                 if (to_vmx(vcpu)->nested.vmxon &&
5782                     !nested_host_cr0_valid(vcpu, val))
5783                         return 1;
5784
5785                 return kvm_set_cr0(vcpu, val);
5786         }
5787 }
5788
5789 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5790 {
5791         if (is_guest_mode(vcpu)) {
5792                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5793                 unsigned long orig_val = val;
5794
5795                 /* analogously to handle_set_cr0 */
5796                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5797                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5798                 if (kvm_set_cr4(vcpu, val))
5799                         return 1;
5800                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5801                 return 0;
5802         } else
5803                 return kvm_set_cr4(vcpu, val);
5804 }
5805
5806 static int handle_cr(struct kvm_vcpu *vcpu)
5807 {
5808         unsigned long exit_qualification, val;
5809         int cr;
5810         int reg;
5811         int err;
5812         int ret;
5813
5814         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5815         cr = exit_qualification & 15;
5816         reg = (exit_qualification >> 8) & 15;
5817         switch ((exit_qualification >> 4) & 3) {
5818         case 0: /* mov to cr */
5819                 val = kvm_register_readl(vcpu, reg);
5820                 trace_kvm_cr_write(cr, val);
5821                 switch (cr) {
5822                 case 0:
5823                         err = handle_set_cr0(vcpu, val);
5824                         return kvm_complete_insn_gp(vcpu, err);
5825                 case 3:
5826                         err = kvm_set_cr3(vcpu, val);
5827                         return kvm_complete_insn_gp(vcpu, err);
5828                 case 4:
5829                         err = handle_set_cr4(vcpu, val);
5830                         return kvm_complete_insn_gp(vcpu, err);
5831                 case 8: {
5832                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5833                                 u8 cr8 = (u8)val;
5834                                 err = kvm_set_cr8(vcpu, cr8);
5835                                 ret = kvm_complete_insn_gp(vcpu, err);
5836                                 if (lapic_in_kernel(vcpu))
5837                                         return ret;
5838                                 if (cr8_prev <= cr8)
5839                                         return ret;
5840                                 /*
5841                                  * TODO: we might be squashing a
5842                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5843                                  * KVM_EXIT_DEBUG here.
5844                                  */
5845                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5846                                 return 0;
5847                         }
5848                 }
5849                 break;
5850         case 2: /* clts */
5851                 WARN_ONCE(1, "Guest should always own CR0.TS");
5852                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5853                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5854                 return kvm_skip_emulated_instruction(vcpu);
5855         case 1: /*mov from cr*/
5856                 switch (cr) {
5857                 case 3:
5858                         val = kvm_read_cr3(vcpu);
5859                         kvm_register_write(vcpu, reg, val);
5860                         trace_kvm_cr_read(cr, val);
5861                         return kvm_skip_emulated_instruction(vcpu);
5862                 case 8:
5863                         val = kvm_get_cr8(vcpu);
5864                         kvm_register_write(vcpu, reg, val);
5865                         trace_kvm_cr_read(cr, val);
5866                         return kvm_skip_emulated_instruction(vcpu);
5867                 }
5868                 break;
5869         case 3: /* lmsw */
5870                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5871                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5872                 kvm_lmsw(vcpu, val);
5873
5874                 return kvm_skip_emulated_instruction(vcpu);
5875         default:
5876                 break;
5877         }
5878         vcpu->run->exit_reason = 0;
5879         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5880                (int)(exit_qualification >> 4) & 3, cr);
5881         return 0;
5882 }
5883
5884 static int handle_dr(struct kvm_vcpu *vcpu)
5885 {
5886         unsigned long exit_qualification;
5887         int dr, dr7, reg;
5888
5889         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5890         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5891
5892         /* First, if DR does not exist, trigger UD */
5893         if (!kvm_require_dr(vcpu, dr))
5894                 return 1;
5895
5896         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5897         if (!kvm_require_cpl(vcpu, 0))
5898                 return 1;
5899         dr7 = vmcs_readl(GUEST_DR7);
5900         if (dr7 & DR7_GD) {
5901                 /*
5902                  * As the vm-exit takes precedence over the debug trap, we
5903                  * need to emulate the latter, either for the host or the
5904                  * guest debugging itself.
5905                  */
5906                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5907                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5908                         vcpu->run->debug.arch.dr7 = dr7;
5909                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5910                         vcpu->run->debug.arch.exception = DB_VECTOR;
5911                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5912                         return 0;
5913                 } else {
5914                         vcpu->arch.dr6 &= ~15;
5915                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5916                         kvm_queue_exception(vcpu, DB_VECTOR);
5917                         return 1;
5918                 }
5919         }
5920
5921         if (vcpu->guest_debug == 0) {
5922                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5923                                 CPU_BASED_MOV_DR_EXITING);
5924
5925                 /*
5926                  * No more DR vmexits; force a reload of the debug registers
5927                  * and reenter on this instruction.  The next vmexit will
5928                  * retrieve the full state of the debug registers.
5929                  */
5930                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5931                 return 1;
5932         }
5933
5934         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5935         if (exit_qualification & TYPE_MOV_FROM_DR) {
5936                 unsigned long val;
5937
5938                 if (kvm_get_dr(vcpu, dr, &val))
5939                         return 1;
5940                 kvm_register_write(vcpu, reg, val);
5941         } else
5942                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5943                         return 1;
5944
5945         return kvm_skip_emulated_instruction(vcpu);
5946 }
5947
5948 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5949 {
5950         return vcpu->arch.dr6;
5951 }
5952
5953 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5954 {
5955 }
5956
5957 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5958 {
5959         get_debugreg(vcpu->arch.db[0], 0);
5960         get_debugreg(vcpu->arch.db[1], 1);
5961         get_debugreg(vcpu->arch.db[2], 2);
5962         get_debugreg(vcpu->arch.db[3], 3);
5963         get_debugreg(vcpu->arch.dr6, 6);
5964         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5965
5966         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5967         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5968 }
5969
5970 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5971 {
5972         vmcs_writel(GUEST_DR7, val);
5973 }
5974
5975 static int handle_cpuid(struct kvm_vcpu *vcpu)
5976 {
5977         return kvm_emulate_cpuid(vcpu);
5978 }
5979
5980 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5981 {
5982         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5983         struct msr_data msr_info;
5984
5985         msr_info.index = ecx;
5986         msr_info.host_initiated = false;
5987         if (vmx_get_msr(vcpu, &msr_info)) {
5988                 trace_kvm_msr_read_ex(ecx);
5989                 kvm_inject_gp(vcpu, 0);
5990                 return 1;
5991         }
5992
5993         trace_kvm_msr_read(ecx, msr_info.data);
5994
5995         /* FIXME: handling of bits 32:63 of rax, rdx */
5996         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5997         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5998         return kvm_skip_emulated_instruction(vcpu);
5999 }
6000
6001 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6002 {
6003         struct msr_data msr;
6004         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6005         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6006                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6007
6008         msr.data = data;
6009         msr.index = ecx;
6010         msr.host_initiated = false;
6011         if (kvm_set_msr(vcpu, &msr) != 0) {
6012                 trace_kvm_msr_write_ex(ecx, data);
6013                 kvm_inject_gp(vcpu, 0);
6014                 return 1;
6015         }
6016
6017         trace_kvm_msr_write(ecx, data);
6018         return kvm_skip_emulated_instruction(vcpu);
6019 }
6020
6021 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6022 {
6023         kvm_apic_update_ppr(vcpu);
6024         return 1;
6025 }
6026
6027 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6028 {
6029         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6030                         CPU_BASED_VIRTUAL_INTR_PENDING);
6031
6032         kvm_make_request(KVM_REQ_EVENT, vcpu);
6033
6034         ++vcpu->stat.irq_window_exits;
6035         return 1;
6036 }
6037
6038 static int handle_halt(struct kvm_vcpu *vcpu)
6039 {
6040         return kvm_emulate_halt(vcpu);
6041 }
6042
6043 static int handle_vmcall(struct kvm_vcpu *vcpu)
6044 {
6045         return kvm_emulate_hypercall(vcpu);
6046 }
6047
6048 static int handle_invd(struct kvm_vcpu *vcpu)
6049 {
6050         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6051 }
6052
6053 static int handle_invlpg(struct kvm_vcpu *vcpu)
6054 {
6055         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6056
6057         kvm_mmu_invlpg(vcpu, exit_qualification);
6058         return kvm_skip_emulated_instruction(vcpu);
6059 }
6060
6061 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6062 {
6063         int err;
6064
6065         err = kvm_rdpmc(vcpu);
6066         return kvm_complete_insn_gp(vcpu, err);
6067 }
6068
6069 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6070 {
6071         return kvm_emulate_wbinvd(vcpu);
6072 }
6073
6074 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6075 {
6076         u64 new_bv = kvm_read_edx_eax(vcpu);
6077         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6078
6079         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6080                 return kvm_skip_emulated_instruction(vcpu);
6081         return 1;
6082 }
6083
6084 static int handle_xsaves(struct kvm_vcpu *vcpu)
6085 {
6086         kvm_skip_emulated_instruction(vcpu);
6087         WARN(1, "this should never happen\n");
6088         return 1;
6089 }
6090
6091 static int handle_xrstors(struct kvm_vcpu *vcpu)
6092 {
6093         kvm_skip_emulated_instruction(vcpu);
6094         WARN(1, "this should never happen\n");
6095         return 1;
6096 }
6097
6098 static int handle_apic_access(struct kvm_vcpu *vcpu)
6099 {
6100         if (likely(fasteoi)) {
6101                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6102                 int access_type, offset;
6103
6104                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6105                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6106                 /*
6107                  * Sane guest uses MOV to write EOI, with written value
6108                  * not cared. So make a short-circuit here by avoiding
6109                  * heavy instruction emulation.
6110                  */
6111                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6112                     (offset == APIC_EOI)) {
6113                         kvm_lapic_set_eoi(vcpu);
6114                         return kvm_skip_emulated_instruction(vcpu);
6115                 }
6116         }
6117         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6118 }
6119
6120 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6121 {
6122         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6123         int vector = exit_qualification & 0xff;
6124
6125         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6126         kvm_apic_set_eoi_accelerated(vcpu, vector);
6127         return 1;
6128 }
6129
6130 static int handle_apic_write(struct kvm_vcpu *vcpu)
6131 {
6132         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6133         u32 offset = exit_qualification & 0xfff;
6134
6135         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6136         kvm_apic_write_nodecode(vcpu, offset);
6137         return 1;
6138 }
6139
6140 static int handle_task_switch(struct kvm_vcpu *vcpu)
6141 {
6142         struct vcpu_vmx *vmx = to_vmx(vcpu);
6143         unsigned long exit_qualification;
6144         bool has_error_code = false;
6145         u32 error_code = 0;
6146         u16 tss_selector;
6147         int reason, type, idt_v, idt_index;
6148
6149         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6150         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6151         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6152
6153         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6154
6155         reason = (u32)exit_qualification >> 30;
6156         if (reason == TASK_SWITCH_GATE && idt_v) {
6157                 switch (type) {
6158                 case INTR_TYPE_NMI_INTR:
6159                         vcpu->arch.nmi_injected = false;
6160                         vmx_set_nmi_mask(vcpu, true);
6161                         break;
6162                 case INTR_TYPE_EXT_INTR:
6163                 case INTR_TYPE_SOFT_INTR:
6164                         kvm_clear_interrupt_queue(vcpu);
6165                         break;
6166                 case INTR_TYPE_HARD_EXCEPTION:
6167                         if (vmx->idt_vectoring_info &
6168                             VECTORING_INFO_DELIVER_CODE_MASK) {
6169                                 has_error_code = true;
6170                                 error_code =
6171                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6172                         }
6173                         /* fall through */
6174                 case INTR_TYPE_SOFT_EXCEPTION:
6175                         kvm_clear_exception_queue(vcpu);
6176                         break;
6177                 default:
6178                         break;
6179                 }
6180         }
6181         tss_selector = exit_qualification;
6182
6183         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6184                        type != INTR_TYPE_EXT_INTR &&
6185                        type != INTR_TYPE_NMI_INTR))
6186                 skip_emulated_instruction(vcpu);
6187
6188         if (kvm_task_switch(vcpu, tss_selector,
6189                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6190                             has_error_code, error_code) == EMULATE_FAIL) {
6191                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6192                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6193                 vcpu->run->internal.ndata = 0;
6194                 return 0;
6195         }
6196
6197         /*
6198          * TODO: What about debug traps on tss switch?
6199          *       Are we supposed to inject them and update dr6?
6200          */
6201
6202         return 1;
6203 }
6204
6205 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6206 {
6207         unsigned long exit_qualification;
6208         gpa_t gpa;
6209         u32 error_code;
6210
6211         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6212
6213         if (is_guest_mode(vcpu)
6214             && !(exit_qualification & EPT_VIOLATION_GVA_TRANSLATED)) {
6215                 /*
6216                  * Fix up exit_qualification according to whether guest
6217                  * page table accesses are reads or writes.
6218                  */
6219                 u64 eptp = nested_ept_get_cr3(vcpu);
6220                 if (!(eptp & VMX_EPT_AD_ENABLE_BIT))
6221                         exit_qualification &= ~EPT_VIOLATION_ACC_WRITE;
6222         }
6223
6224         /*
6225          * EPT violation happened while executing iret from NMI,
6226          * "blocked by NMI" bit has to be set before next VM entry.
6227          * There are errata that may cause this bit to not be set:
6228          * AAK134, BY25.
6229          */
6230         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6231                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6232                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6233
6234         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6235         trace_kvm_page_fault(gpa, exit_qualification);
6236
6237         /* Is it a read fault? */
6238         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6239                      ? PFERR_USER_MASK : 0;
6240         /* Is it a write fault? */
6241         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6242                       ? PFERR_WRITE_MASK : 0;
6243         /* Is it a fetch fault? */
6244         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6245                       ? PFERR_FETCH_MASK : 0;
6246         /* ept page table entry is present? */
6247         error_code |= (exit_qualification &
6248                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6249                         EPT_VIOLATION_EXECUTABLE))
6250                       ? PFERR_PRESENT_MASK : 0;
6251
6252         vcpu->arch.gpa_available = true;
6253         vcpu->arch.exit_qualification = exit_qualification;
6254
6255         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6256 }
6257
6258 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6259 {
6260         int ret;
6261         gpa_t gpa;
6262
6263         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6264         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6265                 trace_kvm_fast_mmio(gpa);
6266                 return kvm_skip_emulated_instruction(vcpu);
6267         }
6268
6269         ret = handle_mmio_page_fault(vcpu, gpa, true);
6270         vcpu->arch.gpa_available = true;
6271         if (likely(ret == RET_MMIO_PF_EMULATE))
6272                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6273                                               EMULATE_DONE;
6274
6275         if (unlikely(ret == RET_MMIO_PF_INVALID))
6276                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6277
6278         if (unlikely(ret == RET_MMIO_PF_RETRY))
6279                 return 1;
6280
6281         /* It is the real ept misconfig */
6282         WARN_ON(1);
6283
6284         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6285         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6286
6287         return 0;
6288 }
6289
6290 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6291 {
6292         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6293                         CPU_BASED_VIRTUAL_NMI_PENDING);
6294         ++vcpu->stat.nmi_window_exits;
6295         kvm_make_request(KVM_REQ_EVENT, vcpu);
6296
6297         return 1;
6298 }
6299
6300 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6301 {
6302         struct vcpu_vmx *vmx = to_vmx(vcpu);
6303         enum emulation_result err = EMULATE_DONE;
6304         int ret = 1;
6305         u32 cpu_exec_ctrl;
6306         bool intr_window_requested;
6307         unsigned count = 130;
6308
6309         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6310         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6311
6312         while (vmx->emulation_required && count-- != 0) {
6313                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6314                         return handle_interrupt_window(&vmx->vcpu);
6315
6316                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6317                         return 1;
6318
6319                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6320
6321                 if (err == EMULATE_USER_EXIT) {
6322                         ++vcpu->stat.mmio_exits;
6323                         ret = 0;
6324                         goto out;
6325                 }
6326
6327                 if (err != EMULATE_DONE) {
6328                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6329                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6330                         vcpu->run->internal.ndata = 0;
6331                         return 0;
6332                 }
6333
6334                 if (vcpu->arch.halt_request) {
6335                         vcpu->arch.halt_request = 0;
6336                         ret = kvm_vcpu_halt(vcpu);
6337                         goto out;
6338                 }
6339
6340                 if (signal_pending(current))
6341                         goto out;
6342                 if (need_resched())
6343                         schedule();
6344         }
6345
6346 out:
6347         return ret;
6348 }
6349
6350 static int __grow_ple_window(int val)
6351 {
6352         if (ple_window_grow < 1)
6353                 return ple_window;
6354
6355         val = min(val, ple_window_actual_max);
6356
6357         if (ple_window_grow < ple_window)
6358                 val *= ple_window_grow;
6359         else
6360                 val += ple_window_grow;
6361
6362         return val;
6363 }
6364
6365 static int __shrink_ple_window(int val, int modifier, int minimum)
6366 {
6367         if (modifier < 1)
6368                 return ple_window;
6369
6370         if (modifier < ple_window)
6371                 val /= modifier;
6372         else
6373                 val -= modifier;
6374
6375         return max(val, minimum);
6376 }
6377
6378 static void grow_ple_window(struct kvm_vcpu *vcpu)
6379 {
6380         struct vcpu_vmx *vmx = to_vmx(vcpu);
6381         int old = vmx->ple_window;
6382
6383         vmx->ple_window = __grow_ple_window(old);
6384
6385         if (vmx->ple_window != old)
6386                 vmx->ple_window_dirty = true;
6387
6388         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6389 }
6390
6391 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6392 {
6393         struct vcpu_vmx *vmx = to_vmx(vcpu);
6394         int old = vmx->ple_window;
6395
6396         vmx->ple_window = __shrink_ple_window(old,
6397                                               ple_window_shrink, ple_window);
6398
6399         if (vmx->ple_window != old)
6400                 vmx->ple_window_dirty = true;
6401
6402         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6403 }
6404
6405 /*
6406  * ple_window_actual_max is computed to be one grow_ple_window() below
6407  * ple_window_max. (See __grow_ple_window for the reason.)
6408  * This prevents overflows, because ple_window_max is int.
6409  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6410  * this process.
6411  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6412  */
6413 static void update_ple_window_actual_max(void)
6414 {
6415         ple_window_actual_max =
6416                         __shrink_ple_window(max(ple_window_max, ple_window),
6417                                             ple_window_grow, INT_MIN);
6418 }
6419
6420 /*
6421  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6422  */
6423 static void wakeup_handler(void)
6424 {
6425         struct kvm_vcpu *vcpu;
6426         int cpu = smp_processor_id();
6427
6428         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6429         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6430                         blocked_vcpu_list) {
6431                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6432
6433                 if (pi_test_on(pi_desc) == 1)
6434                         kvm_vcpu_kick(vcpu);
6435         }
6436         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6437 }
6438
6439 void vmx_enable_tdp(void)
6440 {
6441         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6442                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6443                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6444                 0ull, VMX_EPT_EXECUTABLE_MASK,
6445                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6446                 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6447
6448         ept_set_mmio_spte_mask();
6449         kvm_enable_tdp();
6450 }
6451
6452 static __init int hardware_setup(void)
6453 {
6454         int r = -ENOMEM, i, msr;
6455
6456         rdmsrl_safe(MSR_EFER, &host_efer);
6457
6458         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6459                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6460
6461         for (i = 0; i < VMX_BITMAP_NR; i++) {
6462                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6463                 if (!vmx_bitmap[i])
6464                         goto out;
6465         }
6466
6467         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6468         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6469         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6470
6471         /*
6472          * Allow direct access to the PC debug port (it is often used for I/O
6473          * delays, but the vmexits simply slow things down).
6474          */
6475         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6476         clear_bit(0x80, vmx_io_bitmap_a);
6477
6478         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6479
6480         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6481         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6482
6483         if (setup_vmcs_config(&vmcs_config) < 0) {
6484                 r = -EIO;
6485                 goto out;
6486         }
6487
6488         if (boot_cpu_has(X86_FEATURE_NX))
6489                 kvm_enable_efer_bits(EFER_NX);
6490
6491         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6492                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6493                 enable_vpid = 0;
6494
6495         if (!cpu_has_vmx_shadow_vmcs())
6496                 enable_shadow_vmcs = 0;
6497         if (enable_shadow_vmcs)
6498                 init_vmcs_shadow_fields();
6499
6500         if (!cpu_has_vmx_ept() ||
6501             !cpu_has_vmx_ept_4levels()) {
6502                 enable_ept = 0;
6503                 enable_unrestricted_guest = 0;
6504                 enable_ept_ad_bits = 0;
6505         }
6506
6507         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6508                 enable_ept_ad_bits = 0;
6509
6510         if (!cpu_has_vmx_unrestricted_guest())
6511                 enable_unrestricted_guest = 0;
6512
6513         if (!cpu_has_vmx_flexpriority())
6514                 flexpriority_enabled = 0;
6515
6516         /*
6517          * set_apic_access_page_addr() is used to reload apic access
6518          * page upon invalidation.  No need to do anything if not
6519          * using the APIC_ACCESS_ADDR VMCS field.
6520          */
6521         if (!flexpriority_enabled)
6522                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6523
6524         if (!cpu_has_vmx_tpr_shadow())
6525                 kvm_x86_ops->update_cr8_intercept = NULL;
6526
6527         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6528                 kvm_disable_largepages();
6529
6530         if (!cpu_has_vmx_ple())
6531                 ple_gap = 0;
6532
6533         if (!cpu_has_vmx_apicv()) {
6534                 enable_apicv = 0;
6535                 kvm_x86_ops->sync_pir_to_irr = NULL;
6536         }
6537
6538         if (cpu_has_vmx_tsc_scaling()) {
6539                 kvm_has_tsc_control = true;
6540                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6541                 kvm_tsc_scaling_ratio_frac_bits = 48;
6542         }
6543
6544         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6545         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6546         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6547         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6548         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6549         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6550         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6551
6552         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6553                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6554         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6555                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6556         memcpy(vmx_msr_bitmap_legacy_x2apic,
6557                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6558         memcpy(vmx_msr_bitmap_longmode_x2apic,
6559                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6560
6561         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6562
6563         for (msr = 0x800; msr <= 0x8ff; msr++) {
6564                 if (msr == 0x839 /* TMCCT */)
6565                         continue;
6566                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6567         }
6568
6569         /*
6570          * TPR reads and writes can be virtualized even if virtual interrupt
6571          * delivery is not in use.
6572          */
6573         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6574         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6575
6576         /* EOI */
6577         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6578         /* SELF-IPI */
6579         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6580
6581         if (enable_ept)
6582                 vmx_enable_tdp();
6583         else
6584                 kvm_disable_tdp();
6585
6586         update_ple_window_actual_max();
6587
6588         /*
6589          * Only enable PML when hardware supports PML feature, and both EPT
6590          * and EPT A/D bit features are enabled -- PML depends on them to work.
6591          */
6592         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6593                 enable_pml = 0;
6594
6595         if (!enable_pml) {
6596                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6597                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6598                 kvm_x86_ops->flush_log_dirty = NULL;
6599                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6600         }
6601
6602         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6603                 u64 vmx_msr;
6604
6605                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6606                 cpu_preemption_timer_multi =
6607                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6608         } else {
6609                 kvm_x86_ops->set_hv_timer = NULL;
6610                 kvm_x86_ops->cancel_hv_timer = NULL;
6611         }
6612
6613         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6614
6615         kvm_mce_cap_supported |= MCG_LMCE_P;
6616
6617         return alloc_kvm_area();
6618
6619 out:
6620         for (i = 0; i < VMX_BITMAP_NR; i++)
6621                 free_page((unsigned long)vmx_bitmap[i]);
6622
6623     return r;
6624 }
6625
6626 static __exit void hardware_unsetup(void)
6627 {
6628         int i;
6629
6630         for (i = 0; i < VMX_BITMAP_NR; i++)
6631                 free_page((unsigned long)vmx_bitmap[i]);
6632
6633         free_kvm_area();
6634 }
6635
6636 /*
6637  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6638  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6639  */
6640 static int handle_pause(struct kvm_vcpu *vcpu)
6641 {
6642         if (ple_gap)
6643                 grow_ple_window(vcpu);
6644
6645         kvm_vcpu_on_spin(vcpu);
6646         return kvm_skip_emulated_instruction(vcpu);
6647 }
6648
6649 static int handle_nop(struct kvm_vcpu *vcpu)
6650 {
6651         return kvm_skip_emulated_instruction(vcpu);
6652 }
6653
6654 static int handle_mwait(struct kvm_vcpu *vcpu)
6655 {
6656         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6657         return handle_nop(vcpu);
6658 }
6659
6660 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6661 {
6662         return 1;
6663 }
6664
6665 static int handle_monitor(struct kvm_vcpu *vcpu)
6666 {
6667         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6668         return handle_nop(vcpu);
6669 }
6670
6671 /*
6672  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6673  * We could reuse a single VMCS for all the L2 guests, but we also want the
6674  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6675  * allows keeping them loaded on the processor, and in the future will allow
6676  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6677  * every entry if they never change.
6678  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6679  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6680  *
6681  * The following functions allocate and free a vmcs02 in this pool.
6682  */
6683
6684 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6685 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6686 {
6687         struct vmcs02_list *item;
6688         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6689                 if (item->vmptr == vmx->nested.current_vmptr) {
6690                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6691                         return &item->vmcs02;
6692                 }
6693
6694         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6695                 /* Recycle the least recently used VMCS. */
6696                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6697                                        struct vmcs02_list, list);
6698                 item->vmptr = vmx->nested.current_vmptr;
6699                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6700                 return &item->vmcs02;
6701         }
6702
6703         /* Create a new VMCS */
6704         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6705         if (!item)
6706                 return NULL;
6707         item->vmcs02.vmcs = alloc_vmcs();
6708         item->vmcs02.shadow_vmcs = NULL;
6709         if (!item->vmcs02.vmcs) {
6710                 kfree(item);
6711                 return NULL;
6712         }
6713         loaded_vmcs_init(&item->vmcs02);
6714         item->vmptr = vmx->nested.current_vmptr;
6715         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6716         vmx->nested.vmcs02_num++;
6717         return &item->vmcs02;
6718 }
6719
6720 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6721 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6722 {
6723         struct vmcs02_list *item;
6724         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6725                 if (item->vmptr == vmptr) {
6726                         free_loaded_vmcs(&item->vmcs02);
6727                         list_del(&item->list);
6728                         kfree(item);
6729                         vmx->nested.vmcs02_num--;
6730                         return;
6731                 }
6732 }
6733
6734 /*
6735  * Free all VMCSs saved for this vcpu, except the one pointed by
6736  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6737  * must be &vmx->vmcs01.
6738  */
6739 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6740 {
6741         struct vmcs02_list *item, *n;
6742
6743         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6744         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6745                 /*
6746                  * Something will leak if the above WARN triggers.  Better than
6747                  * a use-after-free.
6748                  */
6749                 if (vmx->loaded_vmcs == &item->vmcs02)
6750                         continue;
6751
6752                 free_loaded_vmcs(&item->vmcs02);
6753                 list_del(&item->list);
6754                 kfree(item);
6755                 vmx->nested.vmcs02_num--;
6756         }
6757 }
6758
6759 /*
6760  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6761  * set the success or error code of an emulated VMX instruction, as specified
6762  * by Vol 2B, VMX Instruction Reference, "Conventions".
6763  */
6764 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6765 {
6766         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6767                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6768                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6769 }
6770
6771 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6772 {
6773         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6774                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6775                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6776                         | X86_EFLAGS_CF);
6777 }
6778
6779 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6780                                         u32 vm_instruction_error)
6781 {
6782         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6783                 /*
6784                  * failValid writes the error number to the current VMCS, which
6785                  * can't be done there isn't a current VMCS.
6786                  */
6787                 nested_vmx_failInvalid(vcpu);
6788                 return;
6789         }
6790         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6791                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6792                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6793                         | X86_EFLAGS_ZF);
6794         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6795         /*
6796          * We don't need to force a shadow sync because
6797          * VM_INSTRUCTION_ERROR is not shadowed
6798          */
6799 }
6800
6801 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6802 {
6803         /* TODO: not to reset guest simply here. */
6804         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6805         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6806 }
6807
6808 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6809 {
6810         struct vcpu_vmx *vmx =
6811                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6812
6813         vmx->nested.preemption_timer_expired = true;
6814         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6815         kvm_vcpu_kick(&vmx->vcpu);
6816
6817         return HRTIMER_NORESTART;
6818 }
6819
6820 /*
6821  * Decode the memory-address operand of a vmx instruction, as recorded on an
6822  * exit caused by such an instruction (run by a guest hypervisor).
6823  * On success, returns 0. When the operand is invalid, returns 1 and throws
6824  * #UD or #GP.
6825  */
6826 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6827                                  unsigned long exit_qualification,
6828                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6829 {
6830         gva_t off;
6831         bool exn;
6832         struct kvm_segment s;
6833
6834         /*
6835          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6836          * Execution", on an exit, vmx_instruction_info holds most of the
6837          * addressing components of the operand. Only the displacement part
6838          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6839          * For how an actual address is calculated from all these components,
6840          * refer to Vol. 1, "Operand Addressing".
6841          */
6842         int  scaling = vmx_instruction_info & 3;
6843         int  addr_size = (vmx_instruction_info >> 7) & 7;
6844         bool is_reg = vmx_instruction_info & (1u << 10);
6845         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6846         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6847         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6848         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6849         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6850
6851         if (is_reg) {
6852                 kvm_queue_exception(vcpu, UD_VECTOR);
6853                 return 1;
6854         }
6855
6856         /* Addr = segment_base + offset */
6857         /* offset = base + [index * scale] + displacement */
6858         off = exit_qualification; /* holds the displacement */
6859         if (base_is_valid)
6860                 off += kvm_register_read(vcpu, base_reg);
6861         if (index_is_valid)
6862                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6863         vmx_get_segment(vcpu, &s, seg_reg);
6864         *ret = s.base + off;
6865
6866         if (addr_size == 1) /* 32 bit */
6867                 *ret &= 0xffffffff;
6868
6869         /* Checks for #GP/#SS exceptions. */
6870         exn = false;
6871         if (is_long_mode(vcpu)) {
6872                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6873                  * non-canonical form. This is the only check on the memory
6874                  * destination for long mode!
6875                  */
6876                 exn = is_noncanonical_address(*ret);
6877         } else if (is_protmode(vcpu)) {
6878                 /* Protected mode: apply checks for segment validity in the
6879                  * following order:
6880                  * - segment type check (#GP(0) may be thrown)
6881                  * - usability check (#GP(0)/#SS(0))
6882                  * - limit check (#GP(0)/#SS(0))
6883                  */
6884                 if (wr)
6885                         /* #GP(0) if the destination operand is located in a
6886                          * read-only data segment or any code segment.
6887                          */
6888                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6889                 else
6890                         /* #GP(0) if the source operand is located in an
6891                          * execute-only code segment
6892                          */
6893                         exn = ((s.type & 0xa) == 8);
6894                 if (exn) {
6895                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6896                         return 1;
6897                 }
6898                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6899                  */
6900                 exn = (s.unusable != 0);
6901                 /* Protected mode: #GP(0)/#SS(0) if the memory
6902                  * operand is outside the segment limit.
6903                  */
6904                 exn = exn || (off + sizeof(u64) > s.limit);
6905         }
6906         if (exn) {
6907                 kvm_queue_exception_e(vcpu,
6908                                       seg_reg == VCPU_SREG_SS ?
6909                                                 SS_VECTOR : GP_VECTOR,
6910                                       0);
6911                 return 1;
6912         }
6913
6914         return 0;
6915 }
6916
6917 /*
6918  * This function performs the various checks including
6919  * - if it's 4KB aligned
6920  * - No bits beyond the physical address width are set
6921  * - Returns 0 on success or else 1
6922  * (Intel SDM Section 30.3)
6923  */
6924 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6925                                   gpa_t *vmpointer)
6926 {
6927         gva_t gva;
6928         gpa_t vmptr;
6929         struct x86_exception e;
6930         struct page *page;
6931         struct vcpu_vmx *vmx = to_vmx(vcpu);
6932         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6933
6934         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6935                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6936                 return 1;
6937
6938         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6939                                 sizeof(vmptr), &e)) {
6940                 kvm_inject_page_fault(vcpu, &e);
6941                 return 1;
6942         }
6943
6944         switch (exit_reason) {
6945         case EXIT_REASON_VMON:
6946                 /*
6947                  * SDM 3: 24.11.5
6948                  * The first 4 bytes of VMXON region contain the supported
6949                  * VMCS revision identifier
6950                  *
6951                  * Note - IA32_VMX_BASIC[48] will never be 1
6952                  * for the nested case;
6953                  * which replaces physical address width with 32
6954                  *
6955                  */
6956                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6957                         nested_vmx_failInvalid(vcpu);
6958                         return kvm_skip_emulated_instruction(vcpu);
6959                 }
6960
6961                 page = nested_get_page(vcpu, vmptr);
6962                 if (page == NULL) {
6963                         nested_vmx_failInvalid(vcpu);
6964                         return kvm_skip_emulated_instruction(vcpu);
6965                 }
6966                 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
6967                         kunmap(page);
6968                         nested_release_page_clean(page);
6969                         nested_vmx_failInvalid(vcpu);
6970                         return kvm_skip_emulated_instruction(vcpu);
6971                 }
6972                 kunmap(page);
6973                 nested_release_page_clean(page);
6974                 vmx->nested.vmxon_ptr = vmptr;
6975                 break;
6976         case EXIT_REASON_VMCLEAR:
6977                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6978                         nested_vmx_failValid(vcpu,
6979                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6980                         return kvm_skip_emulated_instruction(vcpu);
6981                 }
6982
6983                 if (vmptr == vmx->nested.vmxon_ptr) {
6984                         nested_vmx_failValid(vcpu,
6985                                              VMXERR_VMCLEAR_VMXON_POINTER);
6986                         return kvm_skip_emulated_instruction(vcpu);
6987                 }
6988                 break;
6989         case EXIT_REASON_VMPTRLD:
6990                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6991                         nested_vmx_failValid(vcpu,
6992                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6993                         return kvm_skip_emulated_instruction(vcpu);
6994                 }
6995
6996                 if (vmptr == vmx->nested.vmxon_ptr) {
6997                         nested_vmx_failValid(vcpu,
6998                                              VMXERR_VMPTRLD_VMXON_POINTER);
6999                         return kvm_skip_emulated_instruction(vcpu);
7000                 }
7001                 break;
7002         default:
7003                 return 1; /* shouldn't happen */
7004         }
7005
7006         if (vmpointer)
7007                 *vmpointer = vmptr;
7008         return 0;
7009 }
7010
7011 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7012 {
7013         struct vcpu_vmx *vmx = to_vmx(vcpu);
7014         struct vmcs *shadow_vmcs;
7015
7016         if (cpu_has_vmx_msr_bitmap()) {
7017                 vmx->nested.msr_bitmap =
7018                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7019                 if (!vmx->nested.msr_bitmap)
7020                         goto out_msr_bitmap;
7021         }
7022
7023         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7024         if (!vmx->nested.cached_vmcs12)
7025                 goto out_cached_vmcs12;
7026
7027         if (enable_shadow_vmcs) {
7028                 shadow_vmcs = alloc_vmcs();
7029                 if (!shadow_vmcs)
7030                         goto out_shadow_vmcs;
7031                 /* mark vmcs as shadow */
7032                 shadow_vmcs->revision_id |= (1u << 31);
7033                 /* init shadow vmcs */
7034                 vmcs_clear(shadow_vmcs);
7035                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7036         }
7037
7038         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7039         vmx->nested.vmcs02_num = 0;
7040
7041         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7042                      HRTIMER_MODE_REL_PINNED);
7043         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7044
7045         vmx->nested.vmxon = true;
7046         return 0;
7047
7048 out_shadow_vmcs:
7049         kfree(vmx->nested.cached_vmcs12);
7050
7051 out_cached_vmcs12:
7052         free_page((unsigned long)vmx->nested.msr_bitmap);
7053
7054 out_msr_bitmap:
7055         return -ENOMEM;
7056 }
7057
7058 /*
7059  * Emulate the VMXON instruction.
7060  * Currently, we just remember that VMX is active, and do not save or even
7061  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7062  * do not currently need to store anything in that guest-allocated memory
7063  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7064  * argument is different from the VMXON pointer (which the spec says they do).
7065  */
7066 static int handle_vmon(struct kvm_vcpu *vcpu)
7067 {
7068         int ret;
7069         struct vcpu_vmx *vmx = to_vmx(vcpu);
7070         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7071                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7072
7073         /*
7074          * The Intel VMX Instruction Reference lists a bunch of bits that are
7075          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7076          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7077          * Otherwise, we should fail with #UD.  But most faulting conditions
7078          * have already been checked by hardware, prior to the VM-exit for
7079          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7080          * that bit set to 1 in non-root mode.
7081          */
7082         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7083                 kvm_queue_exception(vcpu, UD_VECTOR);
7084                 return 1;
7085         }
7086
7087         if (vmx->nested.vmxon) {
7088                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7089                 return kvm_skip_emulated_instruction(vcpu);
7090         }
7091
7092         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7093                         != VMXON_NEEDED_FEATURES) {
7094                 kvm_inject_gp(vcpu, 0);
7095                 return 1;
7096         }
7097
7098         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7099                 return 1;
7100
7101         ret = enter_vmx_operation(vcpu);
7102         if (ret)
7103                 return ret;
7104
7105         nested_vmx_succeed(vcpu);
7106         return kvm_skip_emulated_instruction(vcpu);
7107 }
7108
7109 /*
7110  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7111  * for running VMX instructions (except VMXON, whose prerequisites are
7112  * slightly different). It also specifies what exception to inject otherwise.
7113  * Note that many of these exceptions have priority over VM exits, so they
7114  * don't have to be checked again here.
7115  */
7116 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7117 {
7118         if (!to_vmx(vcpu)->nested.vmxon) {
7119                 kvm_queue_exception(vcpu, UD_VECTOR);
7120                 return 0;
7121         }
7122         return 1;
7123 }
7124
7125 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7126 {
7127         if (vmx->nested.current_vmptr == -1ull)
7128                 return;
7129
7130         /* current_vmptr and current_vmcs12 are always set/reset together */
7131         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7132                 return;
7133
7134         if (enable_shadow_vmcs) {
7135                 /* copy to memory all shadowed fields in case
7136                    they were modified */
7137                 copy_shadow_to_vmcs12(vmx);
7138                 vmx->nested.sync_shadow_vmcs = false;
7139                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7140                                 SECONDARY_EXEC_SHADOW_VMCS);
7141                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7142         }
7143         vmx->nested.posted_intr_nv = -1;
7144
7145         /* Flush VMCS12 to guest memory */
7146         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7147                VMCS12_SIZE);
7148
7149         kunmap(vmx->nested.current_vmcs12_page);
7150         nested_release_page(vmx->nested.current_vmcs12_page);
7151         vmx->nested.current_vmptr = -1ull;
7152         vmx->nested.current_vmcs12 = NULL;
7153 }
7154
7155 /*
7156  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7157  * just stops using VMX.
7158  */
7159 static void free_nested(struct vcpu_vmx *vmx)
7160 {
7161         if (!vmx->nested.vmxon)
7162                 return;
7163
7164         vmx->nested.vmxon = false;
7165         free_vpid(vmx->nested.vpid02);
7166         nested_release_vmcs12(vmx);
7167         if (vmx->nested.msr_bitmap) {
7168                 free_page((unsigned long)vmx->nested.msr_bitmap);
7169                 vmx->nested.msr_bitmap = NULL;
7170         }
7171         if (enable_shadow_vmcs) {
7172                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7173                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7174                 vmx->vmcs01.shadow_vmcs = NULL;
7175         }
7176         kfree(vmx->nested.cached_vmcs12);
7177         /* Unpin physical memory we referred to in current vmcs02 */
7178         if (vmx->nested.apic_access_page) {
7179                 nested_release_page(vmx->nested.apic_access_page);
7180                 vmx->nested.apic_access_page = NULL;
7181         }
7182         if (vmx->nested.virtual_apic_page) {
7183                 nested_release_page(vmx->nested.virtual_apic_page);
7184                 vmx->nested.virtual_apic_page = NULL;
7185         }
7186         if (vmx->nested.pi_desc_page) {
7187                 kunmap(vmx->nested.pi_desc_page);
7188                 nested_release_page(vmx->nested.pi_desc_page);
7189                 vmx->nested.pi_desc_page = NULL;
7190                 vmx->nested.pi_desc = NULL;
7191         }
7192
7193         nested_free_all_saved_vmcss(vmx);
7194 }
7195
7196 /* Emulate the VMXOFF instruction */
7197 static int handle_vmoff(struct kvm_vcpu *vcpu)
7198 {
7199         if (!nested_vmx_check_permission(vcpu))
7200                 return 1;
7201         free_nested(to_vmx(vcpu));
7202         nested_vmx_succeed(vcpu);
7203         return kvm_skip_emulated_instruction(vcpu);
7204 }
7205
7206 /* Emulate the VMCLEAR instruction */
7207 static int handle_vmclear(struct kvm_vcpu *vcpu)
7208 {
7209         struct vcpu_vmx *vmx = to_vmx(vcpu);
7210         u32 zero = 0;
7211         gpa_t vmptr;
7212
7213         if (!nested_vmx_check_permission(vcpu))
7214                 return 1;
7215
7216         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7217                 return 1;
7218
7219         if (vmptr == vmx->nested.current_vmptr)
7220                 nested_release_vmcs12(vmx);
7221
7222         kvm_vcpu_write_guest(vcpu,
7223                         vmptr + offsetof(struct vmcs12, launch_state),
7224                         &zero, sizeof(zero));
7225
7226         nested_free_vmcs02(vmx, vmptr);
7227
7228         nested_vmx_succeed(vcpu);
7229         return kvm_skip_emulated_instruction(vcpu);
7230 }
7231
7232 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7233
7234 /* Emulate the VMLAUNCH instruction */
7235 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7236 {
7237         return nested_vmx_run(vcpu, true);
7238 }
7239
7240 /* Emulate the VMRESUME instruction */
7241 static int handle_vmresume(struct kvm_vcpu *vcpu)
7242 {
7243
7244         return nested_vmx_run(vcpu, false);
7245 }
7246
7247 enum vmcs_field_type {
7248         VMCS_FIELD_TYPE_U16 = 0,
7249         VMCS_FIELD_TYPE_U64 = 1,
7250         VMCS_FIELD_TYPE_U32 = 2,
7251         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7252 };
7253
7254 static inline int vmcs_field_type(unsigned long field)
7255 {
7256         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7257                 return VMCS_FIELD_TYPE_U32;
7258         return (field >> 13) & 0x3 ;
7259 }
7260
7261 static inline int vmcs_field_readonly(unsigned long field)
7262 {
7263         return (((field >> 10) & 0x3) == 1);
7264 }
7265
7266 /*
7267  * Read a vmcs12 field. Since these can have varying lengths and we return
7268  * one type, we chose the biggest type (u64) and zero-extend the return value
7269  * to that size. Note that the caller, handle_vmread, might need to use only
7270  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7271  * 64-bit fields are to be returned).
7272  */
7273 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7274                                   unsigned long field, u64 *ret)
7275 {
7276         short offset = vmcs_field_to_offset(field);
7277         char *p;
7278
7279         if (offset < 0)
7280                 return offset;
7281
7282         p = ((char *)(get_vmcs12(vcpu))) + offset;
7283
7284         switch (vmcs_field_type(field)) {
7285         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7286                 *ret = *((natural_width *)p);
7287                 return 0;
7288         case VMCS_FIELD_TYPE_U16:
7289                 *ret = *((u16 *)p);
7290                 return 0;
7291         case VMCS_FIELD_TYPE_U32:
7292                 *ret = *((u32 *)p);
7293                 return 0;
7294         case VMCS_FIELD_TYPE_U64:
7295                 *ret = *((u64 *)p);
7296                 return 0;
7297         default:
7298                 WARN_ON(1);
7299                 return -ENOENT;
7300         }
7301 }
7302
7303
7304 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7305                                    unsigned long field, u64 field_value){
7306         short offset = vmcs_field_to_offset(field);
7307         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7308         if (offset < 0)
7309                 return offset;
7310
7311         switch (vmcs_field_type(field)) {
7312         case VMCS_FIELD_TYPE_U16:
7313                 *(u16 *)p = field_value;
7314                 return 0;
7315         case VMCS_FIELD_TYPE_U32:
7316                 *(u32 *)p = field_value;
7317                 return 0;
7318         case VMCS_FIELD_TYPE_U64:
7319                 *(u64 *)p = field_value;
7320                 return 0;
7321         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7322                 *(natural_width *)p = field_value;
7323                 return 0;
7324         default:
7325                 WARN_ON(1);
7326                 return -ENOENT;
7327         }
7328
7329 }
7330
7331 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7332 {
7333         int i;
7334         unsigned long field;
7335         u64 field_value;
7336         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7337         const unsigned long *fields = shadow_read_write_fields;
7338         const int num_fields = max_shadow_read_write_fields;
7339
7340         preempt_disable();
7341
7342         vmcs_load(shadow_vmcs);
7343
7344         for (i = 0; i < num_fields; i++) {
7345                 field = fields[i];
7346                 switch (vmcs_field_type(field)) {
7347                 case VMCS_FIELD_TYPE_U16:
7348                         field_value = vmcs_read16(field);
7349                         break;
7350                 case VMCS_FIELD_TYPE_U32:
7351                         field_value = vmcs_read32(field);
7352                         break;
7353                 case VMCS_FIELD_TYPE_U64:
7354                         field_value = vmcs_read64(field);
7355                         break;
7356                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7357                         field_value = vmcs_readl(field);
7358                         break;
7359                 default:
7360                         WARN_ON(1);
7361                         continue;
7362                 }
7363                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7364         }
7365
7366         vmcs_clear(shadow_vmcs);
7367         vmcs_load(vmx->loaded_vmcs->vmcs);
7368
7369         preempt_enable();
7370 }
7371
7372 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7373 {
7374         const unsigned long *fields[] = {
7375                 shadow_read_write_fields,
7376                 shadow_read_only_fields
7377         };
7378         const int max_fields[] = {
7379                 max_shadow_read_write_fields,
7380                 max_shadow_read_only_fields
7381         };
7382         int i, q;
7383         unsigned long field;
7384         u64 field_value = 0;
7385         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7386
7387         vmcs_load(shadow_vmcs);
7388
7389         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7390                 for (i = 0; i < max_fields[q]; i++) {
7391                         field = fields[q][i];
7392                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7393
7394                         switch (vmcs_field_type(field)) {
7395                         case VMCS_FIELD_TYPE_U16:
7396                                 vmcs_write16(field, (u16)field_value);
7397                                 break;
7398                         case VMCS_FIELD_TYPE_U32:
7399                                 vmcs_write32(field, (u32)field_value);
7400                                 break;
7401                         case VMCS_FIELD_TYPE_U64:
7402                                 vmcs_write64(field, (u64)field_value);
7403                                 break;
7404                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7405                                 vmcs_writel(field, (long)field_value);
7406                                 break;
7407                         default:
7408                                 WARN_ON(1);
7409                                 break;
7410                         }
7411                 }
7412         }
7413
7414         vmcs_clear(shadow_vmcs);
7415         vmcs_load(vmx->loaded_vmcs->vmcs);
7416 }
7417
7418 /*
7419  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7420  * used before) all generate the same failure when it is missing.
7421  */
7422 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7423 {
7424         struct vcpu_vmx *vmx = to_vmx(vcpu);
7425         if (vmx->nested.current_vmptr == -1ull) {
7426                 nested_vmx_failInvalid(vcpu);
7427                 return 0;
7428         }
7429         return 1;
7430 }
7431
7432 static int handle_vmread(struct kvm_vcpu *vcpu)
7433 {
7434         unsigned long field;
7435         u64 field_value;
7436         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7437         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7438         gva_t gva = 0;
7439
7440         if (!nested_vmx_check_permission(vcpu))
7441                 return 1;
7442
7443         if (!nested_vmx_check_vmcs12(vcpu))
7444                 return kvm_skip_emulated_instruction(vcpu);
7445
7446         /* Decode instruction info and find the field to read */
7447         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7448         /* Read the field, zero-extended to a u64 field_value */
7449         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7450                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7451                 return kvm_skip_emulated_instruction(vcpu);
7452         }
7453         /*
7454          * Now copy part of this value to register or memory, as requested.
7455          * Note that the number of bits actually copied is 32 or 64 depending
7456          * on the guest's mode (32 or 64 bit), not on the given field's length.
7457          */
7458         if (vmx_instruction_info & (1u << 10)) {
7459                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7460                         field_value);
7461         } else {
7462                 if (get_vmx_mem_address(vcpu, exit_qualification,
7463                                 vmx_instruction_info, true, &gva))
7464                         return 1;
7465                 /* _system ok, as hardware has verified cpl=0 */
7466                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7467                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7468         }
7469
7470         nested_vmx_succeed(vcpu);
7471         return kvm_skip_emulated_instruction(vcpu);
7472 }
7473
7474
7475 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7476 {
7477         unsigned long field;
7478         gva_t gva;
7479         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7480         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7481         /* The value to write might be 32 or 64 bits, depending on L1's long
7482          * mode, and eventually we need to write that into a field of several
7483          * possible lengths. The code below first zero-extends the value to 64
7484          * bit (field_value), and then copies only the appropriate number of
7485          * bits into the vmcs12 field.
7486          */
7487         u64 field_value = 0;
7488         struct x86_exception e;
7489
7490         if (!nested_vmx_check_permission(vcpu))
7491                 return 1;
7492
7493         if (!nested_vmx_check_vmcs12(vcpu))
7494                 return kvm_skip_emulated_instruction(vcpu);
7495
7496         if (vmx_instruction_info & (1u << 10))
7497                 field_value = kvm_register_readl(vcpu,
7498                         (((vmx_instruction_info) >> 3) & 0xf));
7499         else {
7500                 if (get_vmx_mem_address(vcpu, exit_qualification,
7501                                 vmx_instruction_info, false, &gva))
7502                         return 1;
7503                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7504                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7505                         kvm_inject_page_fault(vcpu, &e);
7506                         return 1;
7507                 }
7508         }
7509
7510
7511         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7512         if (vmcs_field_readonly(field)) {
7513                 nested_vmx_failValid(vcpu,
7514                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7515                 return kvm_skip_emulated_instruction(vcpu);
7516         }
7517
7518         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7519                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7520                 return kvm_skip_emulated_instruction(vcpu);
7521         }
7522
7523         nested_vmx_succeed(vcpu);
7524         return kvm_skip_emulated_instruction(vcpu);
7525 }
7526
7527 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7528 {
7529         vmx->nested.current_vmptr = vmptr;
7530         if (enable_shadow_vmcs) {
7531                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7532                               SECONDARY_EXEC_SHADOW_VMCS);
7533                 vmcs_write64(VMCS_LINK_POINTER,
7534                              __pa(vmx->vmcs01.shadow_vmcs));
7535                 vmx->nested.sync_shadow_vmcs = true;
7536         }
7537 }
7538
7539 /* Emulate the VMPTRLD instruction */
7540 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7541 {
7542         struct vcpu_vmx *vmx = to_vmx(vcpu);
7543         gpa_t vmptr;
7544
7545         if (!nested_vmx_check_permission(vcpu))
7546                 return 1;
7547
7548         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7549                 return 1;
7550
7551         if (vmx->nested.current_vmptr != vmptr) {
7552                 struct vmcs12 *new_vmcs12;
7553                 struct page *page;
7554                 page = nested_get_page(vcpu, vmptr);
7555                 if (page == NULL) {
7556                         nested_vmx_failInvalid(vcpu);
7557                         return kvm_skip_emulated_instruction(vcpu);
7558                 }
7559                 new_vmcs12 = kmap(page);
7560                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7561                         kunmap(page);
7562                         nested_release_page_clean(page);
7563                         nested_vmx_failValid(vcpu,
7564                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7565                         return kvm_skip_emulated_instruction(vcpu);
7566                 }
7567
7568                 nested_release_vmcs12(vmx);
7569                 vmx->nested.current_vmcs12 = new_vmcs12;
7570                 vmx->nested.current_vmcs12_page = page;
7571                 /*
7572                  * Load VMCS12 from guest memory since it is not already
7573                  * cached.
7574                  */
7575                 memcpy(vmx->nested.cached_vmcs12,
7576                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7577                 set_current_vmptr(vmx, vmptr);
7578         }
7579
7580         nested_vmx_succeed(vcpu);
7581         return kvm_skip_emulated_instruction(vcpu);
7582 }
7583
7584 /* Emulate the VMPTRST instruction */
7585 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7586 {
7587         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7588         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7589         gva_t vmcs_gva;
7590         struct x86_exception e;
7591
7592         if (!nested_vmx_check_permission(vcpu))
7593                 return 1;
7594
7595         if (get_vmx_mem_address(vcpu, exit_qualification,
7596                         vmx_instruction_info, true, &vmcs_gva))
7597                 return 1;
7598         /* ok to use *_system, as hardware has verified cpl=0 */
7599         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7600                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7601                                  sizeof(u64), &e)) {
7602                 kvm_inject_page_fault(vcpu, &e);
7603                 return 1;
7604         }
7605         nested_vmx_succeed(vcpu);
7606         return kvm_skip_emulated_instruction(vcpu);
7607 }
7608
7609 /* Emulate the INVEPT instruction */
7610 static int handle_invept(struct kvm_vcpu *vcpu)
7611 {
7612         struct vcpu_vmx *vmx = to_vmx(vcpu);
7613         u32 vmx_instruction_info, types;
7614         unsigned long type;
7615         gva_t gva;
7616         struct x86_exception e;
7617         struct {
7618                 u64 eptp, gpa;
7619         } operand;
7620
7621         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7622               SECONDARY_EXEC_ENABLE_EPT) ||
7623             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7624                 kvm_queue_exception(vcpu, UD_VECTOR);
7625                 return 1;
7626         }
7627
7628         if (!nested_vmx_check_permission(vcpu))
7629                 return 1;
7630
7631         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7632         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7633
7634         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7635
7636         if (type >= 32 || !(types & (1 << type))) {
7637                 nested_vmx_failValid(vcpu,
7638                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7639                 return kvm_skip_emulated_instruction(vcpu);
7640         }
7641
7642         /* According to the Intel VMX instruction reference, the memory
7643          * operand is read even if it isn't needed (e.g., for type==global)
7644          */
7645         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7646                         vmx_instruction_info, false, &gva))
7647                 return 1;
7648         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7649                                 sizeof(operand), &e)) {
7650                 kvm_inject_page_fault(vcpu, &e);
7651                 return 1;
7652         }
7653
7654         switch (type) {
7655         case VMX_EPT_EXTENT_GLOBAL:
7656         /*
7657          * TODO: track mappings and invalidate
7658          * single context requests appropriately
7659          */
7660         case VMX_EPT_EXTENT_CONTEXT:
7661                 kvm_mmu_sync_roots(vcpu);
7662                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7663                 nested_vmx_succeed(vcpu);
7664                 break;
7665         default:
7666                 BUG_ON(1);
7667                 break;
7668         }
7669
7670         return kvm_skip_emulated_instruction(vcpu);
7671 }
7672
7673 static int handle_invvpid(struct kvm_vcpu *vcpu)
7674 {
7675         struct vcpu_vmx *vmx = to_vmx(vcpu);
7676         u32 vmx_instruction_info;
7677         unsigned long type, types;
7678         gva_t gva;
7679         struct x86_exception e;
7680         int vpid;
7681
7682         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7683               SECONDARY_EXEC_ENABLE_VPID) ||
7684                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7685                 kvm_queue_exception(vcpu, UD_VECTOR);
7686                 return 1;
7687         }
7688
7689         if (!nested_vmx_check_permission(vcpu))
7690                 return 1;
7691
7692         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7693         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7694
7695         types = (vmx->nested.nested_vmx_vpid_caps &
7696                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7697
7698         if (type >= 32 || !(types & (1 << type))) {
7699                 nested_vmx_failValid(vcpu,
7700                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7701                 return kvm_skip_emulated_instruction(vcpu);
7702         }
7703
7704         /* according to the intel vmx instruction reference, the memory
7705          * operand is read even if it isn't needed (e.g., for type==global)
7706          */
7707         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7708                         vmx_instruction_info, false, &gva))
7709                 return 1;
7710         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7711                                 sizeof(u32), &e)) {
7712                 kvm_inject_page_fault(vcpu, &e);
7713                 return 1;
7714         }
7715
7716         switch (type) {
7717         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7718         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7719         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7720                 if (!vpid) {
7721                         nested_vmx_failValid(vcpu,
7722                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7723                         return kvm_skip_emulated_instruction(vcpu);
7724                 }
7725                 break;
7726         case VMX_VPID_EXTENT_ALL_CONTEXT:
7727                 break;
7728         default:
7729                 WARN_ON_ONCE(1);
7730                 return kvm_skip_emulated_instruction(vcpu);
7731         }
7732
7733         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7734         nested_vmx_succeed(vcpu);
7735
7736         return kvm_skip_emulated_instruction(vcpu);
7737 }
7738
7739 static int handle_pml_full(struct kvm_vcpu *vcpu)
7740 {
7741         unsigned long exit_qualification;
7742
7743         trace_kvm_pml_full(vcpu->vcpu_id);
7744
7745         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7746
7747         /*
7748          * PML buffer FULL happened while executing iret from NMI,
7749          * "blocked by NMI" bit has to be set before next VM entry.
7750          */
7751         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7752                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7753                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7754                                 GUEST_INTR_STATE_NMI);
7755
7756         /*
7757          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7758          * here.., and there's no userspace involvement needed for PML.
7759          */
7760         return 1;
7761 }
7762
7763 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7764 {
7765         kvm_lapic_expired_hv_timer(vcpu);
7766         return 1;
7767 }
7768
7769 /*
7770  * The exit handlers return 1 if the exit was handled fully and guest execution
7771  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7772  * to be done to userspace and return 0.
7773  */
7774 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7775         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7776         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7777         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7778         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7779         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7780         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7781         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7782         [EXIT_REASON_CPUID]                   = handle_cpuid,
7783         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7784         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7785         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7786         [EXIT_REASON_HLT]                     = handle_halt,
7787         [EXIT_REASON_INVD]                    = handle_invd,
7788         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7789         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7790         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7791         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7792         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7793         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7794         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7795         [EXIT_REASON_VMREAD]                  = handle_vmread,
7796         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7797         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7798         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7799         [EXIT_REASON_VMON]                    = handle_vmon,
7800         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7801         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7802         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7803         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7804         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7805         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7806         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7807         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7808         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7809         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7810         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7811         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7812         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7813         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7814         [EXIT_REASON_INVEPT]                  = handle_invept,
7815         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7816         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7817         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7818         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7819         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7820 };
7821
7822 static const int kvm_vmx_max_exit_handlers =
7823         ARRAY_SIZE(kvm_vmx_exit_handlers);
7824
7825 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7826                                        struct vmcs12 *vmcs12)
7827 {
7828         unsigned long exit_qualification;
7829         gpa_t bitmap, last_bitmap;
7830         unsigned int port;
7831         int size;
7832         u8 b;
7833
7834         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7835                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7836
7837         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7838
7839         port = exit_qualification >> 16;
7840         size = (exit_qualification & 7) + 1;
7841
7842         last_bitmap = (gpa_t)-1;
7843         b = -1;
7844
7845         while (size > 0) {
7846                 if (port < 0x8000)
7847                         bitmap = vmcs12->io_bitmap_a;
7848                 else if (port < 0x10000)
7849                         bitmap = vmcs12->io_bitmap_b;
7850                 else
7851                         return true;
7852                 bitmap += (port & 0x7fff) / 8;
7853
7854                 if (last_bitmap != bitmap)
7855                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7856                                 return true;
7857                 if (b & (1 << (port & 7)))
7858                         return true;
7859
7860                 port++;
7861                 size--;
7862                 last_bitmap = bitmap;
7863         }
7864
7865         return false;
7866 }
7867
7868 /*
7869  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7870  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7871  * disinterest in the current event (read or write a specific MSR) by using an
7872  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7873  */
7874 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7875         struct vmcs12 *vmcs12, u32 exit_reason)
7876 {
7877         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7878         gpa_t bitmap;
7879
7880         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7881                 return true;
7882
7883         /*
7884          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7885          * for the four combinations of read/write and low/high MSR numbers.
7886          * First we need to figure out which of the four to use:
7887          */
7888         bitmap = vmcs12->msr_bitmap;
7889         if (exit_reason == EXIT_REASON_MSR_WRITE)
7890                 bitmap += 2048;
7891         if (msr_index >= 0xc0000000) {
7892                 msr_index -= 0xc0000000;
7893                 bitmap += 1024;
7894         }
7895
7896         /* Then read the msr_index'th bit from this bitmap: */
7897         if (msr_index < 1024*8) {
7898                 unsigned char b;
7899                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7900                         return true;
7901                 return 1 & (b >> (msr_index & 7));
7902         } else
7903                 return true; /* let L1 handle the wrong parameter */
7904 }
7905
7906 /*
7907  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7908  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7909  * intercept (via guest_host_mask etc.) the current event.
7910  */
7911 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7912         struct vmcs12 *vmcs12)
7913 {
7914         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7915         int cr = exit_qualification & 15;
7916         int reg = (exit_qualification >> 8) & 15;
7917         unsigned long val = kvm_register_readl(vcpu, reg);
7918
7919         switch ((exit_qualification >> 4) & 3) {
7920         case 0: /* mov to cr */
7921                 switch (cr) {
7922                 case 0:
7923                         if (vmcs12->cr0_guest_host_mask &
7924                             (val ^ vmcs12->cr0_read_shadow))
7925                                 return true;
7926                         break;
7927                 case 3:
7928                         if ((vmcs12->cr3_target_count >= 1 &&
7929                                         vmcs12->cr3_target_value0 == val) ||
7930                                 (vmcs12->cr3_target_count >= 2 &&
7931                                         vmcs12->cr3_target_value1 == val) ||
7932                                 (vmcs12->cr3_target_count >= 3 &&
7933                                         vmcs12->cr3_target_value2 == val) ||
7934                                 (vmcs12->cr3_target_count >= 4 &&
7935                                         vmcs12->cr3_target_value3 == val))
7936                                 return false;
7937                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7938                                 return true;
7939                         break;
7940                 case 4:
7941                         if (vmcs12->cr4_guest_host_mask &
7942                             (vmcs12->cr4_read_shadow ^ val))
7943                                 return true;
7944                         break;
7945                 case 8:
7946                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7947                                 return true;
7948                         break;
7949                 }
7950                 break;
7951         case 2: /* clts */
7952                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7953                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7954                         return true;
7955                 break;
7956         case 1: /* mov from cr */
7957                 switch (cr) {
7958                 case 3:
7959                         if (vmcs12->cpu_based_vm_exec_control &
7960                             CPU_BASED_CR3_STORE_EXITING)
7961                                 return true;
7962                         break;
7963                 case 8:
7964                         if (vmcs12->cpu_based_vm_exec_control &
7965                             CPU_BASED_CR8_STORE_EXITING)
7966                                 return true;
7967                         break;
7968                 }
7969                 break;
7970         case 3: /* lmsw */
7971                 /*
7972                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7973                  * cr0. Other attempted changes are ignored, with no exit.
7974                  */
7975                 if (vmcs12->cr0_guest_host_mask & 0xe &
7976                     (val ^ vmcs12->cr0_read_shadow))
7977                         return true;
7978                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7979                     !(vmcs12->cr0_read_shadow & 0x1) &&
7980                     (val & 0x1))
7981                         return true;
7982                 break;
7983         }
7984         return false;
7985 }
7986
7987 /*
7988  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7989  * should handle it ourselves in L0 (and then continue L2). Only call this
7990  * when in is_guest_mode (L2).
7991  */
7992 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7993 {
7994         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7995         struct vcpu_vmx *vmx = to_vmx(vcpu);
7996         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7997         u32 exit_reason = vmx->exit_reason;
7998
7999         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8000                                 vmcs_readl(EXIT_QUALIFICATION),
8001                                 vmx->idt_vectoring_info,
8002                                 intr_info,
8003                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8004                                 KVM_ISA_VMX);
8005
8006         if (vmx->nested.nested_run_pending)
8007                 return false;
8008
8009         if (unlikely(vmx->fail)) {
8010                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8011                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8012                 return true;
8013         }
8014
8015         switch (exit_reason) {
8016         case EXIT_REASON_EXCEPTION_NMI:
8017                 if (is_nmi(intr_info))
8018                         return false;
8019                 else if (is_page_fault(intr_info))
8020                         return enable_ept;
8021                 else if (is_no_device(intr_info) &&
8022                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8023                         return false;
8024                 else if (is_debug(intr_info) &&
8025                          vcpu->guest_debug &
8026                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8027                         return false;
8028                 else if (is_breakpoint(intr_info) &&
8029                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8030                         return false;
8031                 return vmcs12->exception_bitmap &
8032                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8033         case EXIT_REASON_EXTERNAL_INTERRUPT:
8034                 return false;
8035         case EXIT_REASON_TRIPLE_FAULT:
8036                 return true;
8037         case EXIT_REASON_PENDING_INTERRUPT:
8038                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8039         case EXIT_REASON_NMI_WINDOW:
8040                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8041         case EXIT_REASON_TASK_SWITCH:
8042                 return true;
8043         case EXIT_REASON_CPUID:
8044                 return true;
8045         case EXIT_REASON_HLT:
8046                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8047         case EXIT_REASON_INVD:
8048                 return true;
8049         case EXIT_REASON_INVLPG:
8050                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8051         case EXIT_REASON_RDPMC:
8052                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8053         case EXIT_REASON_RDRAND:
8054                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8055         case EXIT_REASON_RDSEED:
8056                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8057         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8058                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8059         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8060         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8061         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8062         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8063         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8064         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8065                 /*
8066                  * VMX instructions trap unconditionally. This allows L1 to
8067                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8068                  */
8069                 return true;
8070         case EXIT_REASON_CR_ACCESS:
8071                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8072         case EXIT_REASON_DR_ACCESS:
8073                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8074         case EXIT_REASON_IO_INSTRUCTION:
8075                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8076         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8077                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8078         case EXIT_REASON_MSR_READ:
8079         case EXIT_REASON_MSR_WRITE:
8080                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8081         case EXIT_REASON_INVALID_STATE:
8082                 return true;
8083         case EXIT_REASON_MWAIT_INSTRUCTION:
8084                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8085         case EXIT_REASON_MONITOR_TRAP_FLAG:
8086                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8087         case EXIT_REASON_MONITOR_INSTRUCTION:
8088                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8089         case EXIT_REASON_PAUSE_INSTRUCTION:
8090                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8091                         nested_cpu_has2(vmcs12,
8092                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8093         case EXIT_REASON_MCE_DURING_VMENTRY:
8094                 return false;
8095         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8096                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8097         case EXIT_REASON_APIC_ACCESS:
8098                 return nested_cpu_has2(vmcs12,
8099                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8100         case EXIT_REASON_APIC_WRITE:
8101         case EXIT_REASON_EOI_INDUCED:
8102                 /* apic_write and eoi_induced should exit unconditionally. */
8103                 return true;
8104         case EXIT_REASON_EPT_VIOLATION:
8105                 /*
8106                  * L0 always deals with the EPT violation. If nested EPT is
8107                  * used, and the nested mmu code discovers that the address is
8108                  * missing in the guest EPT table (EPT12), the EPT violation
8109                  * will be injected with nested_ept_inject_page_fault()
8110                  */
8111                 return false;
8112         case EXIT_REASON_EPT_MISCONFIG:
8113                 /*
8114                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8115                  * table (shadow on EPT) or a merged EPT table that L0 built
8116                  * (EPT on EPT). So any problems with the structure of the
8117                  * table is L0's fault.
8118                  */
8119                 return false;
8120         case EXIT_REASON_WBINVD:
8121                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8122         case EXIT_REASON_XSETBV:
8123                 return true;
8124         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8125                 /*
8126                  * This should never happen, since it is not possible to
8127                  * set XSS to a non-zero value---neither in L1 nor in L2.
8128                  * If if it were, XSS would have to be checked against
8129                  * the XSS exit bitmap in vmcs12.
8130                  */
8131                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8132         case EXIT_REASON_PREEMPTION_TIMER:
8133                 return false;
8134         case EXIT_REASON_PML_FULL:
8135                 /* We emulate PML support to L1. */
8136                 return false;
8137         default:
8138                 return true;
8139         }
8140 }
8141
8142 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8143 {
8144         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8145         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8146 }
8147
8148 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8149 {
8150         if (vmx->pml_pg) {
8151                 __free_page(vmx->pml_pg);
8152                 vmx->pml_pg = NULL;
8153         }
8154 }
8155
8156 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8157 {
8158         struct vcpu_vmx *vmx = to_vmx(vcpu);
8159         u64 *pml_buf;
8160         u16 pml_idx;
8161
8162         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8163
8164         /* Do nothing if PML buffer is empty */
8165         if (pml_idx == (PML_ENTITY_NUM - 1))
8166                 return;
8167
8168         /* PML index always points to next available PML buffer entity */
8169         if (pml_idx >= PML_ENTITY_NUM)
8170                 pml_idx = 0;
8171         else
8172                 pml_idx++;
8173
8174         pml_buf = page_address(vmx->pml_pg);
8175         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8176                 u64 gpa;
8177
8178                 gpa = pml_buf[pml_idx];
8179                 WARN_ON(gpa & (PAGE_SIZE - 1));
8180                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8181         }
8182
8183         /* reset PML index */
8184         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8185 }
8186
8187 /*
8188  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8189  * Called before reporting dirty_bitmap to userspace.
8190  */
8191 static void kvm_flush_pml_buffers(struct kvm *kvm)
8192 {
8193         int i;
8194         struct kvm_vcpu *vcpu;
8195         /*
8196          * We only need to kick vcpu out of guest mode here, as PML buffer
8197          * is flushed at beginning of all VMEXITs, and it's obvious that only
8198          * vcpus running in guest are possible to have unflushed GPAs in PML
8199          * buffer.
8200          */
8201         kvm_for_each_vcpu(i, vcpu, kvm)
8202                 kvm_vcpu_kick(vcpu);
8203 }
8204
8205 static void vmx_dump_sel(char *name, uint32_t sel)
8206 {
8207         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8208                name, vmcs_read16(sel),
8209                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8210                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8211                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8212 }
8213
8214 static void vmx_dump_dtsel(char *name, uint32_t limit)
8215 {
8216         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8217                name, vmcs_read32(limit),
8218                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8219 }
8220
8221 static void dump_vmcs(void)
8222 {
8223         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8224         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8225         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8226         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8227         u32 secondary_exec_control = 0;
8228         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8229         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8230         int i, n;
8231
8232         if (cpu_has_secondary_exec_ctrls())
8233                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8234
8235         pr_err("*** Guest State ***\n");
8236         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8237                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8238                vmcs_readl(CR0_GUEST_HOST_MASK));
8239         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8240                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8241         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8242         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8243             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8244         {
8245                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8246                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8247                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8248                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8249         }
8250         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8251                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8252         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8253                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8254         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8255                vmcs_readl(GUEST_SYSENTER_ESP),
8256                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8257         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8258         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8259         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8260         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8261         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8262         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8263         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8264         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8265         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8266         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8267         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8268             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8269                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8270                        efer, vmcs_read64(GUEST_IA32_PAT));
8271         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8272                vmcs_read64(GUEST_IA32_DEBUGCTL),
8273                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8274         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8275                 pr_err("PerfGlobCtl = 0x%016llx\n",
8276                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8277         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8278                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8279         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8280                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8281                vmcs_read32(GUEST_ACTIVITY_STATE));
8282         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8283                 pr_err("InterruptStatus = %04x\n",
8284                        vmcs_read16(GUEST_INTR_STATUS));
8285
8286         pr_err("*** Host State ***\n");
8287         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8288                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8289         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8290                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8291                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8292                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8293                vmcs_read16(HOST_TR_SELECTOR));
8294         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8295                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8296                vmcs_readl(HOST_TR_BASE));
8297         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8298                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8299         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8300                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8301                vmcs_readl(HOST_CR4));
8302         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8303                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8304                vmcs_read32(HOST_IA32_SYSENTER_CS),
8305                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8306         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8307                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8308                        vmcs_read64(HOST_IA32_EFER),
8309                        vmcs_read64(HOST_IA32_PAT));
8310         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8311                 pr_err("PerfGlobCtl = 0x%016llx\n",
8312                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8313
8314         pr_err("*** Control State ***\n");
8315         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8316                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8317         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8318         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8319                vmcs_read32(EXCEPTION_BITMAP),
8320                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8321                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8322         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8323                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8324                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8325                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8326         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8327                vmcs_read32(VM_EXIT_INTR_INFO),
8328                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8329                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8330         pr_err("        reason=%08x qualification=%016lx\n",
8331                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8332         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8333                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8334                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8335         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8336         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8337                 pr_err("TSC Multiplier = 0x%016llx\n",
8338                        vmcs_read64(TSC_MULTIPLIER));
8339         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8340                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8341         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8342                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8343         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8344                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8345         n = vmcs_read32(CR3_TARGET_COUNT);
8346         for (i = 0; i + 1 < n; i += 4)
8347                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8348                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8349                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8350         if (i < n)
8351                 pr_err("CR3 target%u=%016lx\n",
8352                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8353         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8354                 pr_err("PLE Gap=%08x Window=%08x\n",
8355                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8356         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8357                 pr_err("Virtual processor ID = 0x%04x\n",
8358                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8359 }
8360
8361 /*
8362  * The guest has exited.  See if we can fix it or if we need userspace
8363  * assistance.
8364  */
8365 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8366 {
8367         struct vcpu_vmx *vmx = to_vmx(vcpu);
8368         u32 exit_reason = vmx->exit_reason;
8369         u32 vectoring_info = vmx->idt_vectoring_info;
8370
8371         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8372         vcpu->arch.gpa_available = false;
8373
8374         /*
8375          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8376          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8377          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8378          * mode as if vcpus is in root mode, the PML buffer must has been
8379          * flushed already.
8380          */
8381         if (enable_pml)
8382                 vmx_flush_pml_buffer(vcpu);
8383
8384         /* If guest state is invalid, start emulating */
8385         if (vmx->emulation_required)
8386                 return handle_invalid_guest_state(vcpu);
8387
8388         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8389                 nested_vmx_vmexit(vcpu, exit_reason,
8390                                   vmcs_read32(VM_EXIT_INTR_INFO),
8391                                   vmcs_readl(EXIT_QUALIFICATION));
8392                 return 1;
8393         }
8394
8395         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8396                 dump_vmcs();
8397                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8398                 vcpu->run->fail_entry.hardware_entry_failure_reason
8399                         = exit_reason;
8400                 return 0;
8401         }
8402
8403         if (unlikely(vmx->fail)) {
8404                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8405                 vcpu->run->fail_entry.hardware_entry_failure_reason
8406                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8407                 return 0;
8408         }
8409
8410         /*
8411          * Note:
8412          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8413          * delivery event since it indicates guest is accessing MMIO.
8414          * The vm-exit can be triggered again after return to guest that
8415          * will cause infinite loop.
8416          */
8417         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8418                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8419                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8420                         exit_reason != EXIT_REASON_PML_FULL &&
8421                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8422                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8423                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8424                 vcpu->run->internal.ndata = 2;
8425                 vcpu->run->internal.data[0] = vectoring_info;
8426                 vcpu->run->internal.data[1] = exit_reason;
8427                 return 0;
8428         }
8429
8430         if (exit_reason < kvm_vmx_max_exit_handlers
8431             && kvm_vmx_exit_handlers[exit_reason])
8432                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8433         else {
8434                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8435                                 exit_reason);
8436                 kvm_queue_exception(vcpu, UD_VECTOR);
8437                 return 1;
8438         }
8439 }
8440
8441 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8442 {
8443         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8444
8445         if (is_guest_mode(vcpu) &&
8446                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8447                 return;
8448
8449         if (irr == -1 || tpr < irr) {
8450                 vmcs_write32(TPR_THRESHOLD, 0);
8451                 return;
8452         }
8453
8454         vmcs_write32(TPR_THRESHOLD, irr);
8455 }
8456
8457 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8458 {
8459         u32 sec_exec_control;
8460
8461         /* Postpone execution until vmcs01 is the current VMCS. */
8462         if (is_guest_mode(vcpu)) {
8463                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8464                 return;
8465         }
8466
8467         if (!cpu_has_vmx_virtualize_x2apic_mode())
8468                 return;
8469
8470         if (!cpu_need_tpr_shadow(vcpu))
8471                 return;
8472
8473         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8474
8475         if (set) {
8476                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8477                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8478         } else {
8479                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8480                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8481                 vmx_flush_tlb_ept_only(vcpu);
8482         }
8483         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8484
8485         vmx_set_msr_bitmap(vcpu);
8486 }
8487
8488 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8489 {
8490         struct vcpu_vmx *vmx = to_vmx(vcpu);
8491
8492         /*
8493          * Currently we do not handle the nested case where L2 has an
8494          * APIC access page of its own; that page is still pinned.
8495          * Hence, we skip the case where the VCPU is in guest mode _and_
8496          * L1 prepared an APIC access page for L2.
8497          *
8498          * For the case where L1 and L2 share the same APIC access page
8499          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8500          * in the vmcs12), this function will only update either the vmcs01
8501          * or the vmcs02.  If the former, the vmcs02 will be updated by
8502          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8503          * the next L2->L1 exit.
8504          */
8505         if (!is_guest_mode(vcpu) ||
8506             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8507                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8508                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8509                 vmx_flush_tlb_ept_only(vcpu);
8510         }
8511 }
8512
8513 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8514 {
8515         u16 status;
8516         u8 old;
8517
8518         if (max_isr == -1)
8519                 max_isr = 0;
8520
8521         status = vmcs_read16(GUEST_INTR_STATUS);
8522         old = status >> 8;
8523         if (max_isr != old) {
8524                 status &= 0xff;
8525                 status |= max_isr << 8;
8526                 vmcs_write16(GUEST_INTR_STATUS, status);
8527         }
8528 }
8529
8530 static void vmx_set_rvi(int vector)
8531 {
8532         u16 status;
8533         u8 old;
8534
8535         if (vector == -1)
8536                 vector = 0;
8537
8538         status = vmcs_read16(GUEST_INTR_STATUS);
8539         old = (u8)status & 0xff;
8540         if ((u8)vector != old) {
8541                 status &= ~0xff;
8542                 status |= (u8)vector;
8543                 vmcs_write16(GUEST_INTR_STATUS, status);
8544         }
8545 }
8546
8547 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8548 {
8549         if (!is_guest_mode(vcpu)) {
8550                 vmx_set_rvi(max_irr);
8551                 return;
8552         }
8553
8554         if (max_irr == -1)
8555                 return;
8556
8557         /*
8558          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8559          * handles it.
8560          */
8561         if (nested_exit_on_intr(vcpu))
8562                 return;
8563
8564         /*
8565          * Else, fall back to pre-APICv interrupt injection since L2
8566          * is run without virtual interrupt delivery.
8567          */
8568         if (!kvm_event_needs_reinjection(vcpu) &&
8569             vmx_interrupt_allowed(vcpu)) {
8570                 kvm_queue_interrupt(vcpu, max_irr, false);
8571                 vmx_inject_irq(vcpu);
8572         }
8573 }
8574
8575 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8576 {
8577         struct vcpu_vmx *vmx = to_vmx(vcpu);
8578         int max_irr;
8579
8580         WARN_ON(!vcpu->arch.apicv_active);
8581         if (pi_test_on(&vmx->pi_desc)) {
8582                 pi_clear_on(&vmx->pi_desc);
8583                 /*
8584                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8585                  * But on x86 this is just a compiler barrier anyway.
8586                  */
8587                 smp_mb__after_atomic();
8588                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8589         } else {
8590                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8591         }
8592         vmx_hwapic_irr_update(vcpu, max_irr);
8593         return max_irr;
8594 }
8595
8596 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8597 {
8598         if (!kvm_vcpu_apicv_active(vcpu))
8599                 return;
8600
8601         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8602         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8603         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8604         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8605 }
8606
8607 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8608 {
8609         struct vcpu_vmx *vmx = to_vmx(vcpu);
8610
8611         pi_clear_on(&vmx->pi_desc);
8612         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8613 }
8614
8615 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8616 {
8617         u32 exit_intr_info;
8618
8619         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8620               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8621                 return;
8622
8623         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8624         exit_intr_info = vmx->exit_intr_info;
8625
8626         /* Handle machine checks before interrupts are enabled */
8627         if (is_machine_check(exit_intr_info))
8628                 kvm_machine_check();
8629
8630         /* We need to handle NMIs before interrupts are enabled */
8631         if (is_nmi(exit_intr_info)) {
8632                 kvm_before_handle_nmi(&vmx->vcpu);
8633                 asm("int $2");
8634                 kvm_after_handle_nmi(&vmx->vcpu);
8635         }
8636 }
8637
8638 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8639 {
8640         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8641         register void *__sp asm(_ASM_SP);
8642
8643         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8644                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8645                 unsigned int vector;
8646                 unsigned long entry;
8647                 gate_desc *desc;
8648                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8649 #ifdef CONFIG_X86_64
8650                 unsigned long tmp;
8651 #endif
8652
8653                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8654                 desc = (gate_desc *)vmx->host_idt_base + vector;
8655                 entry = gate_offset(*desc);
8656                 asm volatile(
8657 #ifdef CONFIG_X86_64
8658                         "mov %%" _ASM_SP ", %[sp]\n\t"
8659                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8660                         "push $%c[ss]\n\t"
8661                         "push %[sp]\n\t"
8662 #endif
8663                         "pushf\n\t"
8664                         __ASM_SIZE(push) " $%c[cs]\n\t"
8665                         "call *%[entry]\n\t"
8666                         :
8667 #ifdef CONFIG_X86_64
8668                         [sp]"=&r"(tmp),
8669 #endif
8670                         "+r"(__sp)
8671                         :
8672                         [entry]"r"(entry),
8673                         [ss]"i"(__KERNEL_DS),
8674                         [cs]"i"(__KERNEL_CS)
8675                         );
8676         }
8677 }
8678
8679 static bool vmx_has_high_real_mode_segbase(void)
8680 {
8681         return enable_unrestricted_guest || emulate_invalid_guest_state;
8682 }
8683
8684 static bool vmx_mpx_supported(void)
8685 {
8686         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8687                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8688 }
8689
8690 static bool vmx_xsaves_supported(void)
8691 {
8692         return vmcs_config.cpu_based_2nd_exec_ctrl &
8693                 SECONDARY_EXEC_XSAVES;
8694 }
8695
8696 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8697 {
8698         u32 exit_intr_info;
8699         bool unblock_nmi;
8700         u8 vector;
8701         bool idtv_info_valid;
8702
8703         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8704
8705         if (vmx->nmi_known_unmasked)
8706                 return;
8707         /*
8708          * Can't use vmx->exit_intr_info since we're not sure what
8709          * the exit reason is.
8710          */
8711         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8712         unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8713         vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8714         /*
8715          * SDM 3: 27.7.1.2 (September 2008)
8716          * Re-set bit "block by NMI" before VM entry if vmexit caused by
8717          * a guest IRET fault.
8718          * SDM 3: 23.2.2 (September 2008)
8719          * Bit 12 is undefined in any of the following cases:
8720          *  If the VM exit sets the valid bit in the IDT-vectoring
8721          *   information field.
8722          *  If the VM exit is due to a double fault.
8723          */
8724         if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8725             vector != DF_VECTOR && !idtv_info_valid)
8726                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8727                               GUEST_INTR_STATE_NMI);
8728         else
8729                 vmx->nmi_known_unmasked =
8730                         !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8731                           & GUEST_INTR_STATE_NMI);
8732 }
8733
8734 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8735                                       u32 idt_vectoring_info,
8736                                       int instr_len_field,
8737                                       int error_code_field)
8738 {
8739         u8 vector;
8740         int type;
8741         bool idtv_info_valid;
8742
8743         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8744
8745         vcpu->arch.nmi_injected = false;
8746         kvm_clear_exception_queue(vcpu);
8747         kvm_clear_interrupt_queue(vcpu);
8748
8749         if (!idtv_info_valid)
8750                 return;
8751
8752         kvm_make_request(KVM_REQ_EVENT, vcpu);
8753
8754         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8755         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8756
8757         switch (type) {
8758         case INTR_TYPE_NMI_INTR:
8759                 vcpu->arch.nmi_injected = true;
8760                 /*
8761                  * SDM 3: 27.7.1.2 (September 2008)
8762                  * Clear bit "block by NMI" before VM entry if a NMI
8763                  * delivery faulted.
8764                  */
8765                 vmx_set_nmi_mask(vcpu, false);
8766                 break;
8767         case INTR_TYPE_SOFT_EXCEPTION:
8768                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8769                 /* fall through */
8770         case INTR_TYPE_HARD_EXCEPTION:
8771                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8772                         u32 err = vmcs_read32(error_code_field);
8773                         kvm_requeue_exception_e(vcpu, vector, err);
8774                 } else
8775                         kvm_requeue_exception(vcpu, vector);
8776                 break;
8777         case INTR_TYPE_SOFT_INTR:
8778                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8779                 /* fall through */
8780         case INTR_TYPE_EXT_INTR:
8781                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8782                 break;
8783         default:
8784                 break;
8785         }
8786 }
8787
8788 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8789 {
8790         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8791                                   VM_EXIT_INSTRUCTION_LEN,
8792                                   IDT_VECTORING_ERROR_CODE);
8793 }
8794
8795 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8796 {
8797         __vmx_complete_interrupts(vcpu,
8798                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8799                                   VM_ENTRY_INSTRUCTION_LEN,
8800                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8801
8802         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8803 }
8804
8805 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8806 {
8807         int i, nr_msrs;
8808         struct perf_guest_switch_msr *msrs;
8809
8810         msrs = perf_guest_get_msrs(&nr_msrs);
8811
8812         if (!msrs)
8813                 return;
8814
8815         for (i = 0; i < nr_msrs; i++)
8816                 if (msrs[i].host == msrs[i].guest)
8817                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8818                 else
8819                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8820                                         msrs[i].host);
8821 }
8822
8823 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8824 {
8825         struct vcpu_vmx *vmx = to_vmx(vcpu);
8826         u64 tscl;
8827         u32 delta_tsc;
8828
8829         if (vmx->hv_deadline_tsc == -1)
8830                 return;
8831
8832         tscl = rdtsc();
8833         if (vmx->hv_deadline_tsc > tscl)
8834                 /* sure to be 32 bit only because checked on set_hv_timer */
8835                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8836                         cpu_preemption_timer_multi);
8837         else
8838                 delta_tsc = 0;
8839
8840         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8841 }
8842
8843 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8844 {
8845         struct vcpu_vmx *vmx = to_vmx(vcpu);
8846         unsigned long debugctlmsr, cr4;
8847
8848         /* Don't enter VMX if guest state is invalid, let the exit handler
8849            start emulation until we arrive back to a valid state */
8850         if (vmx->emulation_required)
8851                 return;
8852
8853         if (vmx->ple_window_dirty) {
8854                 vmx->ple_window_dirty = false;
8855                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8856         }
8857
8858         if (vmx->nested.sync_shadow_vmcs) {
8859                 copy_vmcs12_to_shadow(vmx);
8860                 vmx->nested.sync_shadow_vmcs = false;
8861         }
8862
8863         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8864                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8865         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8866                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8867
8868         cr4 = cr4_read_shadow();
8869         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8870                 vmcs_writel(HOST_CR4, cr4);
8871                 vmx->host_state.vmcs_host_cr4 = cr4;
8872         }
8873
8874         /* When single-stepping over STI and MOV SS, we must clear the
8875          * corresponding interruptibility bits in the guest state. Otherwise
8876          * vmentry fails as it then expects bit 14 (BS) in pending debug
8877          * exceptions being set, but that's not correct for the guest debugging
8878          * case. */
8879         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8880                 vmx_set_interrupt_shadow(vcpu, 0);
8881
8882         if (vmx->guest_pkru_valid)
8883                 __write_pkru(vmx->guest_pkru);
8884
8885         atomic_switch_perf_msrs(vmx);
8886         debugctlmsr = get_debugctlmsr();
8887
8888         vmx_arm_hv_timer(vcpu);
8889
8890         vmx->__launched = vmx->loaded_vmcs->launched;
8891         asm(
8892                 /* Store host registers */
8893                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8894                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8895                 "push %%" _ASM_CX " \n\t"
8896                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8897                 "je 1f \n\t"
8898                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8899                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8900                 "1: \n\t"
8901                 /* Reload cr2 if changed */
8902                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8903                 "mov %%cr2, %%" _ASM_DX " \n\t"
8904                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8905                 "je 2f \n\t"
8906                 "mov %%" _ASM_AX", %%cr2 \n\t"
8907                 "2: \n\t"
8908                 /* Check if vmlaunch of vmresume is needed */
8909                 "cmpl $0, %c[launched](%0) \n\t"
8910                 /* Load guest registers.  Don't clobber flags. */
8911                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8912                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8913                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8914                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8915                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8916                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8917 #ifdef CONFIG_X86_64
8918                 "mov %c[r8](%0),  %%r8  \n\t"
8919                 "mov %c[r9](%0),  %%r9  \n\t"
8920                 "mov %c[r10](%0), %%r10 \n\t"
8921                 "mov %c[r11](%0), %%r11 \n\t"
8922                 "mov %c[r12](%0), %%r12 \n\t"
8923                 "mov %c[r13](%0), %%r13 \n\t"
8924                 "mov %c[r14](%0), %%r14 \n\t"
8925                 "mov %c[r15](%0), %%r15 \n\t"
8926 #endif
8927                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8928
8929                 /* Enter guest mode */
8930                 "jne 1f \n\t"
8931                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8932                 "jmp 2f \n\t"
8933                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8934                 "2: "
8935                 /* Save guest registers, load host registers, keep flags */
8936                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8937                 "pop %0 \n\t"
8938                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8939                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8940                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8941                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8942                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8943                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8944                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8945 #ifdef CONFIG_X86_64
8946                 "mov %%r8,  %c[r8](%0) \n\t"
8947                 "mov %%r9,  %c[r9](%0) \n\t"
8948                 "mov %%r10, %c[r10](%0) \n\t"
8949                 "mov %%r11, %c[r11](%0) \n\t"
8950                 "mov %%r12, %c[r12](%0) \n\t"
8951                 "mov %%r13, %c[r13](%0) \n\t"
8952                 "mov %%r14, %c[r14](%0) \n\t"
8953                 "mov %%r15, %c[r15](%0) \n\t"
8954 #endif
8955                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8956                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8957
8958                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8959                 "setbe %c[fail](%0) \n\t"
8960                 ".pushsection .rodata \n\t"
8961                 ".global vmx_return \n\t"
8962                 "vmx_return: " _ASM_PTR " 2b \n\t"
8963                 ".popsection"
8964               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8965                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8966                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8967                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8968                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8969                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8970                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8971                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8972                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8973                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8974                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8975 #ifdef CONFIG_X86_64
8976                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8977                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8978                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8979                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8980                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8981                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8982                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8983                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8984 #endif
8985                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8986                 [wordsize]"i"(sizeof(ulong))
8987               : "cc", "memory"
8988 #ifdef CONFIG_X86_64
8989                 , "rax", "rbx", "rdi", "rsi"
8990                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8991 #else
8992                 , "eax", "ebx", "edi", "esi"
8993 #endif
8994               );
8995
8996         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8997         if (debugctlmsr)
8998                 update_debugctlmsr(debugctlmsr);
8999
9000 #ifndef CONFIG_X86_64
9001         /*
9002          * The sysexit path does not restore ds/es, so we must set them to
9003          * a reasonable value ourselves.
9004          *
9005          * We can't defer this to vmx_load_host_state() since that function
9006          * may be executed in interrupt context, which saves and restore segments
9007          * around it, nullifying its effect.
9008          */
9009         loadsegment(ds, __USER_DS);
9010         loadsegment(es, __USER_DS);
9011 #endif
9012
9013         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9014                                   | (1 << VCPU_EXREG_RFLAGS)
9015                                   | (1 << VCPU_EXREG_PDPTR)
9016                                   | (1 << VCPU_EXREG_SEGMENTS)
9017                                   | (1 << VCPU_EXREG_CR3));
9018         vcpu->arch.regs_dirty = 0;
9019
9020         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9021
9022         vmx->loaded_vmcs->launched = 1;
9023
9024         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9025
9026         /*
9027          * eager fpu is enabled if PKEY is supported and CR4 is switched
9028          * back on host, so it is safe to read guest PKRU from current
9029          * XSAVE.
9030          */
9031         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9032                 vmx->guest_pkru = __read_pkru();
9033                 if (vmx->guest_pkru != vmx->host_pkru) {
9034                         vmx->guest_pkru_valid = true;
9035                         __write_pkru(vmx->host_pkru);
9036                 } else
9037                         vmx->guest_pkru_valid = false;
9038         }
9039
9040         /*
9041          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9042          * we did not inject a still-pending event to L1 now because of
9043          * nested_run_pending, we need to re-enable this bit.
9044          */
9045         if (vmx->nested.nested_run_pending)
9046                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9047
9048         vmx->nested.nested_run_pending = 0;
9049
9050         vmx_complete_atomic_exit(vmx);
9051         vmx_recover_nmi_blocking(vmx);
9052         vmx_complete_interrupts(vmx);
9053 }
9054
9055 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9056 {
9057         struct vcpu_vmx *vmx = to_vmx(vcpu);
9058         int cpu;
9059
9060         if (vmx->loaded_vmcs == vmcs)
9061                 return;
9062
9063         cpu = get_cpu();
9064         vmx->loaded_vmcs = vmcs;
9065         vmx_vcpu_put(vcpu);
9066         vmx_vcpu_load(vcpu, cpu);
9067         vcpu->cpu = cpu;
9068         put_cpu();
9069 }
9070
9071 /*
9072  * Ensure that the current vmcs of the logical processor is the
9073  * vmcs01 of the vcpu before calling free_nested().
9074  */
9075 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9076 {
9077        struct vcpu_vmx *vmx = to_vmx(vcpu);
9078        int r;
9079
9080        r = vcpu_load(vcpu);
9081        BUG_ON(r);
9082        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9083        free_nested(vmx);
9084        vcpu_put(vcpu);
9085 }
9086
9087 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9088 {
9089         struct vcpu_vmx *vmx = to_vmx(vcpu);
9090
9091         if (enable_pml)
9092                 vmx_destroy_pml_buffer(vmx);
9093         free_vpid(vmx->vpid);
9094         leave_guest_mode(vcpu);
9095         vmx_free_vcpu_nested(vcpu);
9096         free_loaded_vmcs(vmx->loaded_vmcs);
9097         kfree(vmx->guest_msrs);
9098         kvm_vcpu_uninit(vcpu);
9099         kmem_cache_free(kvm_vcpu_cache, vmx);
9100 }
9101
9102 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9103 {
9104         int err;
9105         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9106         int cpu;
9107
9108         if (!vmx)
9109                 return ERR_PTR(-ENOMEM);
9110
9111         vmx->vpid = allocate_vpid();
9112
9113         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9114         if (err)
9115                 goto free_vcpu;
9116
9117         err = -ENOMEM;
9118
9119         /*
9120          * If PML is turned on, failure on enabling PML just results in failure
9121          * of creating the vcpu, therefore we can simplify PML logic (by
9122          * avoiding dealing with cases, such as enabling PML partially on vcpus
9123          * for the guest, etc.
9124          */
9125         if (enable_pml) {
9126                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9127                 if (!vmx->pml_pg)
9128                         goto uninit_vcpu;
9129         }
9130
9131         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9132         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9133                      > PAGE_SIZE);
9134
9135         if (!vmx->guest_msrs)
9136                 goto free_pml;
9137
9138         vmx->loaded_vmcs = &vmx->vmcs01;
9139         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9140         vmx->loaded_vmcs->shadow_vmcs = NULL;
9141         if (!vmx->loaded_vmcs->vmcs)
9142                 goto free_msrs;
9143         loaded_vmcs_init(vmx->loaded_vmcs);
9144
9145         cpu = get_cpu();
9146         vmx_vcpu_load(&vmx->vcpu, cpu);
9147         vmx->vcpu.cpu = cpu;
9148         err = vmx_vcpu_setup(vmx);
9149         vmx_vcpu_put(&vmx->vcpu);
9150         put_cpu();
9151         if (err)
9152                 goto free_vmcs;
9153         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9154                 err = alloc_apic_access_page(kvm);
9155                 if (err)
9156                         goto free_vmcs;
9157         }
9158
9159         if (enable_ept) {
9160                 if (!kvm->arch.ept_identity_map_addr)
9161                         kvm->arch.ept_identity_map_addr =
9162                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9163                 err = init_rmode_identity_map(kvm);
9164                 if (err)
9165                         goto free_vmcs;
9166         }
9167
9168         if (nested) {
9169                 nested_vmx_setup_ctls_msrs(vmx);
9170                 vmx->nested.vpid02 = allocate_vpid();
9171         }
9172
9173         vmx->nested.posted_intr_nv = -1;
9174         vmx->nested.current_vmptr = -1ull;
9175         vmx->nested.current_vmcs12 = NULL;
9176
9177         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9178
9179         return &vmx->vcpu;
9180
9181 free_vmcs:
9182         free_vpid(vmx->nested.vpid02);
9183         free_loaded_vmcs(vmx->loaded_vmcs);
9184 free_msrs:
9185         kfree(vmx->guest_msrs);
9186 free_pml:
9187         vmx_destroy_pml_buffer(vmx);
9188 uninit_vcpu:
9189         kvm_vcpu_uninit(&vmx->vcpu);
9190 free_vcpu:
9191         free_vpid(vmx->vpid);
9192         kmem_cache_free(kvm_vcpu_cache, vmx);
9193         return ERR_PTR(err);
9194 }
9195
9196 static void __init vmx_check_processor_compat(void *rtn)
9197 {
9198         struct vmcs_config vmcs_conf;
9199
9200         *(int *)rtn = 0;
9201         if (setup_vmcs_config(&vmcs_conf) < 0)
9202                 *(int *)rtn = -EIO;
9203         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9204                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9205                                 smp_processor_id());
9206                 *(int *)rtn = -EIO;
9207         }
9208 }
9209
9210 static int get_ept_level(void)
9211 {
9212         return VMX_EPT_DEFAULT_GAW + 1;
9213 }
9214
9215 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9216 {
9217         u8 cache;
9218         u64 ipat = 0;
9219
9220         /* For VT-d and EPT combination
9221          * 1. MMIO: always map as UC
9222          * 2. EPT with VT-d:
9223          *   a. VT-d without snooping control feature: can't guarantee the
9224          *      result, try to trust guest.
9225          *   b. VT-d with snooping control feature: snooping control feature of
9226          *      VT-d engine can guarantee the cache correctness. Just set it
9227          *      to WB to keep consistent with host. So the same as item 3.
9228          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9229          *    consistent with host MTRR
9230          */
9231         if (is_mmio) {
9232                 cache = MTRR_TYPE_UNCACHABLE;
9233                 goto exit;
9234         }
9235
9236         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9237                 ipat = VMX_EPT_IPAT_BIT;
9238                 cache = MTRR_TYPE_WRBACK;
9239                 goto exit;
9240         }
9241
9242         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9243                 ipat = VMX_EPT_IPAT_BIT;
9244                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9245                         cache = MTRR_TYPE_WRBACK;
9246                 else
9247                         cache = MTRR_TYPE_UNCACHABLE;
9248                 goto exit;
9249         }
9250
9251         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9252
9253 exit:
9254         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9255 }
9256
9257 static int vmx_get_lpage_level(void)
9258 {
9259         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9260                 return PT_DIRECTORY_LEVEL;
9261         else
9262                 /* For shadow and EPT supported 1GB page */
9263                 return PT_PDPE_LEVEL;
9264 }
9265
9266 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9267 {
9268         /*
9269          * These bits in the secondary execution controls field
9270          * are dynamic, the others are mostly based on the hypervisor
9271          * architecture and the guest's CPUID.  Do not touch the
9272          * dynamic bits.
9273          */
9274         u32 mask =
9275                 SECONDARY_EXEC_SHADOW_VMCS |
9276                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9277                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9278
9279         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9280
9281         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9282                      (new_ctl & ~mask) | (cur_ctl & mask));
9283 }
9284
9285 /*
9286  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9287  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9288  */
9289 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9290 {
9291         struct vcpu_vmx *vmx = to_vmx(vcpu);
9292         struct kvm_cpuid_entry2 *entry;
9293
9294         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9295         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9296
9297 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9298         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9299                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9300 } while (0)
9301
9302         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9303         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9304         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9305         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9306         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9307         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9308         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9309         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9310         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9311         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9312         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9313         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9314         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9315         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9316         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9317
9318         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9319         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9320         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9321         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9322         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9323         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9324         cr4_fixed1_update(bit(11),            ecx, bit(2));
9325
9326 #undef cr4_fixed1_update
9327 }
9328
9329 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9330 {
9331         struct kvm_cpuid_entry2 *best;
9332         struct vcpu_vmx *vmx = to_vmx(vcpu);
9333         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9334
9335         if (vmx_rdtscp_supported()) {
9336                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9337                 if (!rdtscp_enabled)
9338                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9339
9340                 if (nested) {
9341                         if (rdtscp_enabled)
9342                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9343                                         SECONDARY_EXEC_RDTSCP;
9344                         else
9345                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9346                                         ~SECONDARY_EXEC_RDTSCP;
9347                 }
9348         }
9349
9350         /* Exposing INVPCID only when PCID is exposed */
9351         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9352         if (vmx_invpcid_supported() &&
9353             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9354             !guest_cpuid_has_pcid(vcpu))) {
9355                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9356
9357                 if (best)
9358                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9359         }
9360
9361         if (cpu_has_secondary_exec_ctrls())
9362                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9363
9364         if (nested_vmx_allowed(vcpu))
9365                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9366                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9367         else
9368                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9369                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9370
9371         if (nested_vmx_allowed(vcpu))
9372                 nested_vmx_cr_fixed1_bits_update(vcpu);
9373 }
9374
9375 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9376 {
9377         if (func == 1 && nested)
9378                 entry->ecx |= bit(X86_FEATURE_VMX);
9379 }
9380
9381 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9382                 struct x86_exception *fault)
9383 {
9384         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9385         struct vcpu_vmx *vmx = to_vmx(vcpu);
9386         u32 exit_reason;
9387         unsigned long exit_qualification = vcpu->arch.exit_qualification;
9388
9389         if (vmx->nested.pml_full) {
9390                 exit_reason = EXIT_REASON_PML_FULL;
9391                 vmx->nested.pml_full = false;
9392                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9393         } else if (fault->error_code & PFERR_RSVD_MASK)
9394                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9395         else
9396                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9397
9398         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9399         vmcs12->guest_physical_address = fault->address;
9400 }
9401
9402 /* Callbacks for nested_ept_init_mmu_context: */
9403
9404 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9405 {
9406         /* return the page table to be shadowed - in our case, EPT12 */
9407         return get_vmcs12(vcpu)->ept_pointer;
9408 }
9409
9410 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9411 {
9412         u64 eptp;
9413
9414         WARN_ON(mmu_is_nested(vcpu));
9415         eptp = nested_ept_get_cr3(vcpu);
9416         if ((eptp & VMX_EPT_AD_ENABLE_BIT) && !enable_ept_ad_bits)
9417                 return 1;
9418
9419         kvm_mmu_unload(vcpu);
9420         kvm_init_shadow_ept_mmu(vcpu,
9421                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9422                         VMX_EPT_EXECUTE_ONLY_BIT,
9423                         eptp & VMX_EPT_AD_ENABLE_BIT);
9424         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9425         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9426         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9427
9428         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9429         return 0;
9430 }
9431
9432 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9433 {
9434         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9435 }
9436
9437 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9438                                             u16 error_code)
9439 {
9440         bool inequality, bit;
9441
9442         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9443         inequality =
9444                 (error_code & vmcs12->page_fault_error_code_mask) !=
9445                  vmcs12->page_fault_error_code_match;
9446         return inequality ^ bit;
9447 }
9448
9449 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9450                 struct x86_exception *fault)
9451 {
9452         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9453
9454         WARN_ON(!is_guest_mode(vcpu));
9455
9456         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9457                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9458                                   vmcs_read32(VM_EXIT_INTR_INFO),
9459                                   vmcs_readl(EXIT_QUALIFICATION));
9460         else
9461                 kvm_inject_page_fault(vcpu, fault);
9462 }
9463
9464 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9465                                                struct vmcs12 *vmcs12);
9466
9467 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9468                                         struct vmcs12 *vmcs12)
9469 {
9470         struct vcpu_vmx *vmx = to_vmx(vcpu);
9471         u64 hpa;
9472
9473         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9474                 /*
9475                  * Translate L1 physical address to host physical
9476                  * address for vmcs02. Keep the page pinned, so this
9477                  * physical address remains valid. We keep a reference
9478                  * to it so we can release it later.
9479                  */
9480                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9481                         nested_release_page(vmx->nested.apic_access_page);
9482                 vmx->nested.apic_access_page =
9483                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9484                 /*
9485                  * If translation failed, no matter: This feature asks
9486                  * to exit when accessing the given address, and if it
9487                  * can never be accessed, this feature won't do
9488                  * anything anyway.
9489                  */
9490                 if (vmx->nested.apic_access_page) {
9491                         hpa = page_to_phys(vmx->nested.apic_access_page);
9492                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9493                 } else {
9494                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9495                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9496                 }
9497         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9498                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9499                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9500                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9501                 kvm_vcpu_reload_apic_access_page(vcpu);
9502         }
9503
9504         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9505                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9506                         nested_release_page(vmx->nested.virtual_apic_page);
9507                 vmx->nested.virtual_apic_page =
9508                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9509
9510                 /*
9511                  * If translation failed, VM entry will fail because
9512                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9513                  * Failing the vm entry is _not_ what the processor
9514                  * does but it's basically the only possibility we
9515                  * have.  We could still enter the guest if CR8 load
9516                  * exits are enabled, CR8 store exits are enabled, and
9517                  * virtualize APIC access is disabled; in this case
9518                  * the processor would never use the TPR shadow and we
9519                  * could simply clear the bit from the execution
9520                  * control.  But such a configuration is useless, so
9521                  * let's keep the code simple.
9522                  */
9523                 if (vmx->nested.virtual_apic_page) {
9524                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9525                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9526                 }
9527         }
9528
9529         if (nested_cpu_has_posted_intr(vmcs12)) {
9530                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9531                         kunmap(vmx->nested.pi_desc_page);
9532                         nested_release_page(vmx->nested.pi_desc_page);
9533                 }
9534                 vmx->nested.pi_desc_page =
9535                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9536                 vmx->nested.pi_desc =
9537                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9538                 if (!vmx->nested.pi_desc) {
9539                         nested_release_page_clean(vmx->nested.pi_desc_page);
9540                         return;
9541                 }
9542                 vmx->nested.pi_desc =
9543                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9544                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9545                         (PAGE_SIZE - 1)));
9546                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9547                         page_to_phys(vmx->nested.pi_desc_page) +
9548                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9549                         (PAGE_SIZE - 1)));
9550         }
9551         if (cpu_has_vmx_msr_bitmap() &&
9552             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9553             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9554                 ;
9555         else
9556                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9557                                 CPU_BASED_USE_MSR_BITMAPS);
9558 }
9559
9560 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9561 {
9562         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9563         struct vcpu_vmx *vmx = to_vmx(vcpu);
9564
9565         if (vcpu->arch.virtual_tsc_khz == 0)
9566                 return;
9567
9568         /* Make sure short timeouts reliably trigger an immediate vmexit.
9569          * hrtimer_start does not guarantee this. */
9570         if (preemption_timeout <= 1) {
9571                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9572                 return;
9573         }
9574
9575         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9576         preemption_timeout *= 1000000;
9577         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9578         hrtimer_start(&vmx->nested.preemption_timer,
9579                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9580 }
9581
9582 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9583                                                 struct vmcs12 *vmcs12)
9584 {
9585         int maxphyaddr;
9586         u64 addr;
9587
9588         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9589                 return 0;
9590
9591         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9592                 WARN_ON(1);
9593                 return -EINVAL;
9594         }
9595         maxphyaddr = cpuid_maxphyaddr(vcpu);
9596
9597         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9598            ((addr + PAGE_SIZE) >> maxphyaddr))
9599                 return -EINVAL;
9600
9601         return 0;
9602 }
9603
9604 /*
9605  * Merge L0's and L1's MSR bitmap, return false to indicate that
9606  * we do not use the hardware.
9607  */
9608 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9609                                                struct vmcs12 *vmcs12)
9610 {
9611         int msr;
9612         struct page *page;
9613         unsigned long *msr_bitmap_l1;
9614         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9615
9616         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9617         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9618                 return false;
9619
9620         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9621         if (!page)
9622                 return false;
9623         msr_bitmap_l1 = (unsigned long *)kmap(page);
9624
9625         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9626
9627         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9628                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9629                         for (msr = 0x800; msr <= 0x8ff; msr++)
9630                                 nested_vmx_disable_intercept_for_msr(
9631                                         msr_bitmap_l1, msr_bitmap_l0,
9632                                         msr, MSR_TYPE_R);
9633
9634                 nested_vmx_disable_intercept_for_msr(
9635                                 msr_bitmap_l1, msr_bitmap_l0,
9636                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9637                                 MSR_TYPE_R | MSR_TYPE_W);
9638
9639                 if (nested_cpu_has_vid(vmcs12)) {
9640                         nested_vmx_disable_intercept_for_msr(
9641                                 msr_bitmap_l1, msr_bitmap_l0,
9642                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9643                                 MSR_TYPE_W);
9644                         nested_vmx_disable_intercept_for_msr(
9645                                 msr_bitmap_l1, msr_bitmap_l0,
9646                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9647                                 MSR_TYPE_W);
9648                 }
9649         }
9650         kunmap(page);
9651         nested_release_page_clean(page);
9652
9653         return true;
9654 }
9655
9656 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9657                                            struct vmcs12 *vmcs12)
9658 {
9659         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9660             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9661             !nested_cpu_has_vid(vmcs12) &&
9662             !nested_cpu_has_posted_intr(vmcs12))
9663                 return 0;
9664
9665         /*
9666          * If virtualize x2apic mode is enabled,
9667          * virtualize apic access must be disabled.
9668          */
9669         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9670             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9671                 return -EINVAL;
9672
9673         /*
9674          * If virtual interrupt delivery is enabled,
9675          * we must exit on external interrupts.
9676          */
9677         if (nested_cpu_has_vid(vmcs12) &&
9678            !nested_exit_on_intr(vcpu))
9679                 return -EINVAL;
9680
9681         /*
9682          * bits 15:8 should be zero in posted_intr_nv,
9683          * the descriptor address has been already checked
9684          * in nested_get_vmcs12_pages.
9685          */
9686         if (nested_cpu_has_posted_intr(vmcs12) &&
9687            (!nested_cpu_has_vid(vmcs12) ||
9688             !nested_exit_intr_ack_set(vcpu) ||
9689             vmcs12->posted_intr_nv & 0xff00))
9690                 return -EINVAL;
9691
9692         /* tpr shadow is needed by all apicv features. */
9693         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9694                 return -EINVAL;
9695
9696         return 0;
9697 }
9698
9699 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9700                                        unsigned long count_field,
9701                                        unsigned long addr_field)
9702 {
9703         int maxphyaddr;
9704         u64 count, addr;
9705
9706         if (vmcs12_read_any(vcpu, count_field, &count) ||
9707             vmcs12_read_any(vcpu, addr_field, &addr)) {
9708                 WARN_ON(1);
9709                 return -EINVAL;
9710         }
9711         if (count == 0)
9712                 return 0;
9713         maxphyaddr = cpuid_maxphyaddr(vcpu);
9714         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9715             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9716                 pr_debug_ratelimited(
9717                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9718                         addr_field, maxphyaddr, count, addr);
9719                 return -EINVAL;
9720         }
9721         return 0;
9722 }
9723
9724 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9725                                                 struct vmcs12 *vmcs12)
9726 {
9727         if (vmcs12->vm_exit_msr_load_count == 0 &&
9728             vmcs12->vm_exit_msr_store_count == 0 &&
9729             vmcs12->vm_entry_msr_load_count == 0)
9730                 return 0; /* Fast path */
9731         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9732                                         VM_EXIT_MSR_LOAD_ADDR) ||
9733             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9734                                         VM_EXIT_MSR_STORE_ADDR) ||
9735             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9736                                         VM_ENTRY_MSR_LOAD_ADDR))
9737                 return -EINVAL;
9738         return 0;
9739 }
9740
9741 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9742                                          struct vmcs12 *vmcs12)
9743 {
9744         u64 address = vmcs12->pml_address;
9745         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9746
9747         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9748                 if (!nested_cpu_has_ept(vmcs12) ||
9749                     !IS_ALIGNED(address, 4096)  ||
9750                     address >> maxphyaddr)
9751                         return -EINVAL;
9752         }
9753
9754         return 0;
9755 }
9756
9757 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9758                                        struct vmx_msr_entry *e)
9759 {
9760         /* x2APIC MSR accesses are not allowed */
9761         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9762                 return -EINVAL;
9763         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9764             e->index == MSR_IA32_UCODE_REV)
9765                 return -EINVAL;
9766         if (e->reserved != 0)
9767                 return -EINVAL;
9768         return 0;
9769 }
9770
9771 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9772                                      struct vmx_msr_entry *e)
9773 {
9774         if (e->index == MSR_FS_BASE ||
9775             e->index == MSR_GS_BASE ||
9776             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9777             nested_vmx_msr_check_common(vcpu, e))
9778                 return -EINVAL;
9779         return 0;
9780 }
9781
9782 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9783                                       struct vmx_msr_entry *e)
9784 {
9785         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9786             nested_vmx_msr_check_common(vcpu, e))
9787                 return -EINVAL;
9788         return 0;
9789 }
9790
9791 /*
9792  * Load guest's/host's msr at nested entry/exit.
9793  * return 0 for success, entry index for failure.
9794  */
9795 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9796 {
9797         u32 i;
9798         struct vmx_msr_entry e;
9799         struct msr_data msr;
9800
9801         msr.host_initiated = false;
9802         for (i = 0; i < count; i++) {
9803                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9804                                         &e, sizeof(e))) {
9805                         pr_debug_ratelimited(
9806                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9807                                 __func__, i, gpa + i * sizeof(e));
9808                         goto fail;
9809                 }
9810                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9811                         pr_debug_ratelimited(
9812                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9813                                 __func__, i, e.index, e.reserved);
9814                         goto fail;
9815                 }
9816                 msr.index = e.index;
9817                 msr.data = e.value;
9818                 if (kvm_set_msr(vcpu, &msr)) {
9819                         pr_debug_ratelimited(
9820                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9821                                 __func__, i, e.index, e.value);
9822                         goto fail;
9823                 }
9824         }
9825         return 0;
9826 fail:
9827         return i + 1;
9828 }
9829
9830 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9831 {
9832         u32 i;
9833         struct vmx_msr_entry e;
9834
9835         for (i = 0; i < count; i++) {
9836                 struct msr_data msr_info;
9837                 if (kvm_vcpu_read_guest(vcpu,
9838                                         gpa + i * sizeof(e),
9839                                         &e, 2 * sizeof(u32))) {
9840                         pr_debug_ratelimited(
9841                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9842                                 __func__, i, gpa + i * sizeof(e));
9843                         return -EINVAL;
9844                 }
9845                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9846                         pr_debug_ratelimited(
9847                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9848                                 __func__, i, e.index, e.reserved);
9849                         return -EINVAL;
9850                 }
9851                 msr_info.host_initiated = false;
9852                 msr_info.index = e.index;
9853                 if (kvm_get_msr(vcpu, &msr_info)) {
9854                         pr_debug_ratelimited(
9855                                 "%s cannot read MSR (%u, 0x%x)\n",
9856                                 __func__, i, e.index);
9857                         return -EINVAL;
9858                 }
9859                 if (kvm_vcpu_write_guest(vcpu,
9860                                          gpa + i * sizeof(e) +
9861                                              offsetof(struct vmx_msr_entry, value),
9862                                          &msr_info.data, sizeof(msr_info.data))) {
9863                         pr_debug_ratelimited(
9864                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9865                                 __func__, i, e.index, msr_info.data);
9866                         return -EINVAL;
9867                 }
9868         }
9869         return 0;
9870 }
9871
9872 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9873 {
9874         unsigned long invalid_mask;
9875
9876         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9877         return (val & invalid_mask) == 0;
9878 }
9879
9880 /*
9881  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9882  * emulating VM entry into a guest with EPT enabled.
9883  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9884  * is assigned to entry_failure_code on failure.
9885  */
9886 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9887                                u32 *entry_failure_code)
9888 {
9889         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9890                 if (!nested_cr3_valid(vcpu, cr3)) {
9891                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9892                         return 1;
9893                 }
9894
9895                 /*
9896                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9897                  * must not be dereferenced.
9898                  */
9899                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9900                     !nested_ept) {
9901                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9902                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9903                                 return 1;
9904                         }
9905                 }
9906
9907                 vcpu->arch.cr3 = cr3;
9908                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9909         }
9910
9911         kvm_mmu_reset_context(vcpu);
9912         return 0;
9913 }
9914
9915 /*
9916  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9917  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9918  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9919  * guest in a way that will both be appropriate to L1's requests, and our
9920  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9921  * function also has additional necessary side-effects, like setting various
9922  * vcpu->arch fields.
9923  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9924  * is assigned to entry_failure_code on failure.
9925  */
9926 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9927                           bool from_vmentry, u32 *entry_failure_code)
9928 {
9929         struct vcpu_vmx *vmx = to_vmx(vcpu);
9930         u32 exec_control, vmcs12_exec_ctrl;
9931
9932         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9933         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9934         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9935         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9936         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9937         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9938         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9939         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9940         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9941         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9942         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9943         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9944         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9945         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9946         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9947         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9948         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9949         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9950         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9951         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9952         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9953         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9954         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9955         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9956         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9957         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9958         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9959         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9960         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9961         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9962         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9963         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9964         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9965         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9966         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9967         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9968
9969         if (from_vmentry &&
9970             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
9971                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9972                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9973         } else {
9974                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9975                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9976         }
9977         if (from_vmentry) {
9978                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9979                              vmcs12->vm_entry_intr_info_field);
9980                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9981                              vmcs12->vm_entry_exception_error_code);
9982                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9983                              vmcs12->vm_entry_instruction_len);
9984                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9985                              vmcs12->guest_interruptibility_info);
9986         } else {
9987                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9988         }
9989         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9990         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9991         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9992                 vmcs12->guest_pending_dbg_exceptions);
9993         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9994         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9995
9996         if (nested_cpu_has_xsaves(vmcs12))
9997                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9998         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9999
10000         exec_control = vmcs12->pin_based_vm_exec_control;
10001
10002         /* Preemption timer setting is only taken from vmcs01.  */
10003         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10004         exec_control |= vmcs_config.pin_based_exec_ctrl;
10005         if (vmx->hv_deadline_tsc == -1)
10006                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10007
10008         /* Posted interrupts setting is only taken from vmcs12.  */
10009         if (nested_cpu_has_posted_intr(vmcs12)) {
10010                 /*
10011                  * Note that we use L0's vector here and in
10012                  * vmx_deliver_nested_posted_interrupt.
10013                  */
10014                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10015                 vmx->nested.pi_pending = false;
10016                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10017         } else {
10018                 exec_control &= ~PIN_BASED_POSTED_INTR;
10019         }
10020
10021         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10022
10023         vmx->nested.preemption_timer_expired = false;
10024         if (nested_cpu_has_preemption_timer(vmcs12))
10025                 vmx_start_preemption_timer(vcpu);
10026
10027         /*
10028          * Whether page-faults are trapped is determined by a combination of
10029          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10030          * If enable_ept, L0 doesn't care about page faults and we should
10031          * set all of these to L1's desires. However, if !enable_ept, L0 does
10032          * care about (at least some) page faults, and because it is not easy
10033          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10034          * to exit on each and every L2 page fault. This is done by setting
10035          * MASK=MATCH=0 and (see below) EB.PF=1.
10036          * Note that below we don't need special code to set EB.PF beyond the
10037          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10038          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10039          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10040          *
10041          * A problem with this approach (when !enable_ept) is that L1 may be
10042          * injected with more page faults than it asked for. This could have
10043          * caused problems, but in practice existing hypervisors don't care.
10044          * To fix this, we will need to emulate the PFEC checking (on the L1
10045          * page tables), using walk_addr(), when injecting PFs to L1.
10046          */
10047         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10048                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10049         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10050                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10051
10052         if (cpu_has_secondary_exec_ctrls()) {
10053                 exec_control = vmx_secondary_exec_control(vmx);
10054
10055                 /* Take the following fields only from vmcs12 */
10056                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10057                                   SECONDARY_EXEC_RDTSCP |
10058                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10059                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10060                 if (nested_cpu_has(vmcs12,
10061                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10062                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10063                                 ~SECONDARY_EXEC_ENABLE_PML;
10064                         exec_control |= vmcs12_exec_ctrl;
10065                 }
10066
10067                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10068                         vmcs_write64(EOI_EXIT_BITMAP0,
10069                                 vmcs12->eoi_exit_bitmap0);
10070                         vmcs_write64(EOI_EXIT_BITMAP1,
10071                                 vmcs12->eoi_exit_bitmap1);
10072                         vmcs_write64(EOI_EXIT_BITMAP2,
10073                                 vmcs12->eoi_exit_bitmap2);
10074                         vmcs_write64(EOI_EXIT_BITMAP3,
10075                                 vmcs12->eoi_exit_bitmap3);
10076                         vmcs_write16(GUEST_INTR_STATUS,
10077                                 vmcs12->guest_intr_status);
10078                 }
10079
10080                 /*
10081                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10082                  * nested_get_vmcs12_pages will either fix it up or
10083                  * remove the VM execution control.
10084                  */
10085                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10086                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10087
10088                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10089         }
10090
10091
10092         /*
10093          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10094          * Some constant fields are set here by vmx_set_constant_host_state().
10095          * Other fields are different per CPU, and will be set later when
10096          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10097          */
10098         vmx_set_constant_host_state(vmx);
10099
10100         /*
10101          * Set the MSR load/store lists to match L0's settings.
10102          */
10103         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10104         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10105         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10106         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10107         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10108
10109         /*
10110          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10111          * entry, but only if the current (host) sp changed from the value
10112          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10113          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10114          * here we just force the write to happen on entry.
10115          */
10116         vmx->host_rsp = 0;
10117
10118         exec_control = vmx_exec_control(vmx); /* L0's desires */
10119         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10120         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10121         exec_control &= ~CPU_BASED_TPR_SHADOW;
10122         exec_control |= vmcs12->cpu_based_vm_exec_control;
10123
10124         /*
10125          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10126          * nested_get_vmcs12_pages can't fix it up, the illegal value
10127          * will result in a VM entry failure.
10128          */
10129         if (exec_control & CPU_BASED_TPR_SHADOW) {
10130                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10131                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10132         }
10133
10134         /*
10135          * Merging of IO bitmap not currently supported.
10136          * Rather, exit every time.
10137          */
10138         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10139         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10140
10141         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10142
10143         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10144          * bitwise-or of what L1 wants to trap for L2, and what we want to
10145          * trap. Note that CR0.TS also needs updating - we do this later.
10146          */
10147         update_exception_bitmap(vcpu);
10148         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10149         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10150
10151         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10152          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10153          * bits are further modified by vmx_set_efer() below.
10154          */
10155         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10156
10157         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10158          * emulated by vmx_set_efer(), below.
10159          */
10160         vm_entry_controls_init(vmx,
10161                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10162                         ~VM_ENTRY_IA32E_MODE) |
10163                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10164
10165         if (from_vmentry &&
10166             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10167                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10168                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10169         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10170                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10171         }
10172
10173         set_cr4_guest_host_mask(vmx);
10174
10175         if (from_vmentry &&
10176             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10177                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10178
10179         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10180                 vmcs_write64(TSC_OFFSET,
10181                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10182         else
10183                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10184         if (kvm_has_tsc_control)
10185                 decache_tsc_multiplier(vmx);
10186
10187         if (enable_vpid) {
10188                 /*
10189                  * There is no direct mapping between vpid02 and vpid12, the
10190                  * vpid02 is per-vCPU for L0 and reused while the value of
10191                  * vpid12 is changed w/ one invvpid during nested vmentry.
10192                  * The vpid12 is allocated by L1 for L2, so it will not
10193                  * influence global bitmap(for vpid01 and vpid02 allocation)
10194                  * even if spawn a lot of nested vCPUs.
10195                  */
10196                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10197                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10198                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10199                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10200                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10201                         }
10202                 } else {
10203                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10204                         vmx_flush_tlb(vcpu);
10205                 }
10206
10207         }
10208
10209         if (enable_pml) {
10210                 /*
10211                  * Conceptually we want to copy the PML address and index from
10212                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10213                  * since we always flush the log on each vmexit, this happens
10214                  * to be equivalent to simply resetting the fields in vmcs02.
10215                  */
10216                 ASSERT(vmx->pml_pg);
10217                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10218                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10219         }
10220
10221         if (nested_cpu_has_ept(vmcs12)) {
10222                 if (nested_ept_init_mmu_context(vcpu)) {
10223                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10224                         return 1;
10225                 }
10226         } else if (nested_cpu_has2(vmcs12,
10227                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10228                 vmx_flush_tlb_ept_only(vcpu);
10229         }
10230
10231         /*
10232          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10233          * bits which we consider mandatory enabled.
10234          * The CR0_READ_SHADOW is what L2 should have expected to read given
10235          * the specifications by L1; It's not enough to take
10236          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10237          * have more bits than L1 expected.
10238          */
10239         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10240         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10241
10242         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10243         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10244
10245         if (from_vmentry &&
10246             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10247                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10248         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10249                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10250         else
10251                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10252         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10253         vmx_set_efer(vcpu, vcpu->arch.efer);
10254
10255         /* Shadow page tables on either EPT or shadow page tables. */
10256         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10257                                 entry_failure_code))
10258                 return 1;
10259
10260         if (!enable_ept)
10261                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10262
10263         /*
10264          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10265          */
10266         if (enable_ept) {
10267                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10268                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10269                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10270                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10271         }
10272
10273         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10274         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10275         return 0;
10276 }
10277
10278 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10279 {
10280         struct vcpu_vmx *vmx = to_vmx(vcpu);
10281
10282         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10283             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10284                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10285
10286         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10287                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10288
10289         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10290                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10291
10292         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10293                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10294
10295         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10296                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10297
10298         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10299                                 vmx->nested.nested_vmx_procbased_ctls_low,
10300                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10301             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10302              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10303                                  vmx->nested.nested_vmx_secondary_ctls_low,
10304                                  vmx->nested.nested_vmx_secondary_ctls_high)) ||
10305             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10306                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10307                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10308             !vmx_control_verify(vmcs12->vm_exit_controls,
10309                                 vmx->nested.nested_vmx_exit_ctls_low,
10310                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10311             !vmx_control_verify(vmcs12->vm_entry_controls,
10312                                 vmx->nested.nested_vmx_entry_ctls_low,
10313                                 vmx->nested.nested_vmx_entry_ctls_high))
10314                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10315
10316         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10317                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10318
10319         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10320             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10321             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10322                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10323
10324         return 0;
10325 }
10326
10327 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10328                                   u32 *exit_qual)
10329 {
10330         bool ia32e;
10331
10332         *exit_qual = ENTRY_FAIL_DEFAULT;
10333
10334         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10335             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10336                 return 1;
10337
10338         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10339             vmcs12->vmcs_link_pointer != -1ull) {
10340                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10341                 return 1;
10342         }
10343
10344         /*
10345          * If the load IA32_EFER VM-entry control is 1, the following checks
10346          * are performed on the field for the IA32_EFER MSR:
10347          * - Bits reserved in the IA32_EFER MSR must be 0.
10348          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10349          *   the IA-32e mode guest VM-exit control. It must also be identical
10350          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10351          *   CR0.PG) is 1.
10352          */
10353         if (to_vmx(vcpu)->nested.nested_run_pending &&
10354             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10355                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10356                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10357                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10358                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10359                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10360                         return 1;
10361         }
10362
10363         /*
10364          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10365          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10366          * the values of the LMA and LME bits in the field must each be that of
10367          * the host address-space size VM-exit control.
10368          */
10369         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10370                 ia32e = (vmcs12->vm_exit_controls &
10371                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10372                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10373                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10374                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10375                         return 1;
10376         }
10377
10378         return 0;
10379 }
10380
10381 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10382 {
10383         struct vcpu_vmx *vmx = to_vmx(vcpu);
10384         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10385         struct loaded_vmcs *vmcs02;
10386         u32 msr_entry_idx;
10387         u32 exit_qual;
10388
10389         vmcs02 = nested_get_current_vmcs02(vmx);
10390         if (!vmcs02)
10391                 return -ENOMEM;
10392
10393         enter_guest_mode(vcpu);
10394
10395         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10396                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10397
10398         vmx_switch_vmcs(vcpu, vmcs02);
10399         vmx_segment_cache_clear(vmx);
10400
10401         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10402                 leave_guest_mode(vcpu);
10403                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10404                 nested_vmx_entry_failure(vcpu, vmcs12,
10405                                          EXIT_REASON_INVALID_STATE, exit_qual);
10406                 return 1;
10407         }
10408
10409         nested_get_vmcs12_pages(vcpu, vmcs12);
10410
10411         msr_entry_idx = nested_vmx_load_msr(vcpu,
10412                                             vmcs12->vm_entry_msr_load_addr,
10413                                             vmcs12->vm_entry_msr_load_count);
10414         if (msr_entry_idx) {
10415                 leave_guest_mode(vcpu);
10416                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10417                 nested_vmx_entry_failure(vcpu, vmcs12,
10418                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10419                 return 1;
10420         }
10421
10422         vmcs12->launch_state = 1;
10423
10424         /*
10425          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10426          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10427          * returned as far as L1 is concerned. It will only return (and set
10428          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10429          */
10430         return 0;
10431 }
10432
10433 /*
10434  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10435  * for running an L2 nested guest.
10436  */
10437 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10438 {
10439         struct vmcs12 *vmcs12;
10440         struct vcpu_vmx *vmx = to_vmx(vcpu);
10441         u32 exit_qual;
10442         int ret;
10443
10444         if (!nested_vmx_check_permission(vcpu))
10445                 return 1;
10446
10447         if (!nested_vmx_check_vmcs12(vcpu))
10448                 goto out;
10449
10450         vmcs12 = get_vmcs12(vcpu);
10451
10452         if (enable_shadow_vmcs)
10453                 copy_shadow_to_vmcs12(vmx);
10454
10455         /*
10456          * The nested entry process starts with enforcing various prerequisites
10457          * on vmcs12 as required by the Intel SDM, and act appropriately when
10458          * they fail: As the SDM explains, some conditions should cause the
10459          * instruction to fail, while others will cause the instruction to seem
10460          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10461          * To speed up the normal (success) code path, we should avoid checking
10462          * for misconfigurations which will anyway be caught by the processor
10463          * when using the merged vmcs02.
10464          */
10465         if (vmcs12->launch_state == launch) {
10466                 nested_vmx_failValid(vcpu,
10467                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10468                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10469                 goto out;
10470         }
10471
10472         ret = check_vmentry_prereqs(vcpu, vmcs12);
10473         if (ret) {
10474                 nested_vmx_failValid(vcpu, ret);
10475                 goto out;
10476         }
10477
10478         /*
10479          * After this point, the trap flag no longer triggers a singlestep trap
10480          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10481          * This is not 100% correct; for performance reasons, we delegate most
10482          * of the checks on host state to the processor.  If those fail,
10483          * the singlestep trap is missed.
10484          */
10485         skip_emulated_instruction(vcpu);
10486
10487         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10488         if (ret) {
10489                 nested_vmx_entry_failure(vcpu, vmcs12,
10490                                          EXIT_REASON_INVALID_STATE, exit_qual);
10491                 return 1;
10492         }
10493
10494         /*
10495          * We're finally done with prerequisite checking, and can start with
10496          * the nested entry.
10497          */
10498
10499         ret = enter_vmx_non_root_mode(vcpu, true);
10500         if (ret)
10501                 return ret;
10502
10503         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10504                 return kvm_vcpu_halt(vcpu);
10505
10506         vmx->nested.nested_run_pending = 1;
10507
10508         return 1;
10509
10510 out:
10511         return kvm_skip_emulated_instruction(vcpu);
10512 }
10513
10514 /*
10515  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10516  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10517  * This function returns the new value we should put in vmcs12.guest_cr0.
10518  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10519  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10520  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10521  *     didn't trap the bit, because if L1 did, so would L0).
10522  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10523  *     been modified by L2, and L1 knows it. So just leave the old value of
10524  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10525  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10526  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10527  *     changed these bits, and therefore they need to be updated, but L0
10528  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10529  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10530  */
10531 static inline unsigned long
10532 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10533 {
10534         return
10535         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10536         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10537         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10538                         vcpu->arch.cr0_guest_owned_bits));
10539 }
10540
10541 static inline unsigned long
10542 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10543 {
10544         return
10545         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10546         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10547         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10548                         vcpu->arch.cr4_guest_owned_bits));
10549 }
10550
10551 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10552                                        struct vmcs12 *vmcs12)
10553 {
10554         u32 idt_vectoring;
10555         unsigned int nr;
10556
10557         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10558                 nr = vcpu->arch.exception.nr;
10559                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10560
10561                 if (kvm_exception_is_soft(nr)) {
10562                         vmcs12->vm_exit_instruction_len =
10563                                 vcpu->arch.event_exit_inst_len;
10564                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10565                 } else
10566                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10567
10568                 if (vcpu->arch.exception.has_error_code) {
10569                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10570                         vmcs12->idt_vectoring_error_code =
10571                                 vcpu->arch.exception.error_code;
10572                 }
10573
10574                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10575         } else if (vcpu->arch.nmi_injected) {
10576                 vmcs12->idt_vectoring_info_field =
10577                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10578         } else if (vcpu->arch.interrupt.pending) {
10579                 nr = vcpu->arch.interrupt.nr;
10580                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10581
10582                 if (vcpu->arch.interrupt.soft) {
10583                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10584                         vmcs12->vm_entry_instruction_len =
10585                                 vcpu->arch.event_exit_inst_len;
10586                 } else
10587                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10588
10589                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10590         }
10591 }
10592
10593 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10594 {
10595         struct vcpu_vmx *vmx = to_vmx(vcpu);
10596
10597         if (vcpu->arch.exception.pending ||
10598                 vcpu->arch.nmi_injected ||
10599                 vcpu->arch.interrupt.pending)
10600                 return -EBUSY;
10601
10602         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10603             vmx->nested.preemption_timer_expired) {
10604                 if (vmx->nested.nested_run_pending)
10605                         return -EBUSY;
10606                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10607                 return 0;
10608         }
10609
10610         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10611                 if (vmx->nested.nested_run_pending)
10612                         return -EBUSY;
10613                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10614                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10615                                   INTR_INFO_VALID_MASK, 0);
10616                 /*
10617                  * The NMI-triggered VM exit counts as injection:
10618                  * clear this one and block further NMIs.
10619                  */
10620                 vcpu->arch.nmi_pending = 0;
10621                 vmx_set_nmi_mask(vcpu, true);
10622                 return 0;
10623         }
10624
10625         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10626             nested_exit_on_intr(vcpu)) {
10627                 if (vmx->nested.nested_run_pending)
10628                         return -EBUSY;
10629                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10630                 return 0;
10631         }
10632
10633         vmx_complete_nested_posted_interrupt(vcpu);
10634         return 0;
10635 }
10636
10637 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10638 {
10639         ktime_t remaining =
10640                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10641         u64 value;
10642
10643         if (ktime_to_ns(remaining) <= 0)
10644                 return 0;
10645
10646         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10647         do_div(value, 1000000);
10648         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10649 }
10650
10651 /*
10652  * Update the guest state fields of vmcs12 to reflect changes that
10653  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10654  * VM-entry controls is also updated, since this is really a guest
10655  * state bit.)
10656  */
10657 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10658 {
10659         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10660         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10661
10662         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10663         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10664         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10665
10666         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10667         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10668         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10669         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10670         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10671         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10672         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10673         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10674         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10675         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10676         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10677         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10678         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10679         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10680         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10681         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10682         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10683         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10684         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10685         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10686         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10687         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10688         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10689         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10690         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10691         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10692         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10693         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10694         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10695         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10696         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10697         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10698         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10699         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10700         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10701         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10702
10703         vmcs12->guest_interruptibility_info =
10704                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10705         vmcs12->guest_pending_dbg_exceptions =
10706                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10707         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10708                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10709         else
10710                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10711
10712         if (nested_cpu_has_preemption_timer(vmcs12)) {
10713                 if (vmcs12->vm_exit_controls &
10714                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10715                         vmcs12->vmx_preemption_timer_value =
10716                                 vmx_get_preemption_timer_value(vcpu);
10717                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10718         }
10719
10720         /*
10721          * In some cases (usually, nested EPT), L2 is allowed to change its
10722          * own CR3 without exiting. If it has changed it, we must keep it.
10723          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10724          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10725          *
10726          * Additionally, restore L2's PDPTR to vmcs12.
10727          */
10728         if (enable_ept) {
10729                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10730                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10731                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10732                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10733                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10734         }
10735
10736         if (nested_cpu_has_ept(vmcs12))
10737                 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10738
10739         if (nested_cpu_has_vid(vmcs12))
10740                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10741
10742         vmcs12->vm_entry_controls =
10743                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10744                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10745
10746         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10747                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10748                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10749         }
10750
10751         /* TODO: These cannot have changed unless we have MSR bitmaps and
10752          * the relevant bit asks not to trap the change */
10753         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10754                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10755         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10756                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10757         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10758         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10759         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10760         if (kvm_mpx_supported())
10761                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10762         if (nested_cpu_has_xsaves(vmcs12))
10763                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10764 }
10765
10766 /*
10767  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10768  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10769  * and this function updates it to reflect the changes to the guest state while
10770  * L2 was running (and perhaps made some exits which were handled directly by L0
10771  * without going back to L1), and to reflect the exit reason.
10772  * Note that we do not have to copy here all VMCS fields, just those that
10773  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10774  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10775  * which already writes to vmcs12 directly.
10776  */
10777 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10778                            u32 exit_reason, u32 exit_intr_info,
10779                            unsigned long exit_qualification)
10780 {
10781         /* update guest state fields: */
10782         sync_vmcs12(vcpu, vmcs12);
10783
10784         /* update exit information fields: */
10785
10786         vmcs12->vm_exit_reason = exit_reason;
10787         vmcs12->exit_qualification = exit_qualification;
10788
10789         vmcs12->vm_exit_intr_info = exit_intr_info;
10790         if ((vmcs12->vm_exit_intr_info &
10791              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10792             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10793                 vmcs12->vm_exit_intr_error_code =
10794                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10795         vmcs12->idt_vectoring_info_field = 0;
10796         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10797         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10798
10799         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10800                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10801                  * instead of reading the real value. */
10802                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10803
10804                 /*
10805                  * Transfer the event that L0 or L1 may wanted to inject into
10806                  * L2 to IDT_VECTORING_INFO_FIELD.
10807                  */
10808                 vmcs12_save_pending_event(vcpu, vmcs12);
10809         }
10810
10811         /*
10812          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10813          * preserved above and would only end up incorrectly in L1.
10814          */
10815         vcpu->arch.nmi_injected = false;
10816         kvm_clear_exception_queue(vcpu);
10817         kvm_clear_interrupt_queue(vcpu);
10818 }
10819
10820 /*
10821  * A part of what we need to when the nested L2 guest exits and we want to
10822  * run its L1 parent, is to reset L1's guest state to the host state specified
10823  * in vmcs12.
10824  * This function is to be called not only on normal nested exit, but also on
10825  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10826  * Failures During or After Loading Guest State").
10827  * This function should be called when the active VMCS is L1's (vmcs01).
10828  */
10829 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10830                                    struct vmcs12 *vmcs12)
10831 {
10832         struct kvm_segment seg;
10833         u32 entry_failure_code;
10834
10835         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10836                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10837         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10838                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10839         else
10840                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10841         vmx_set_efer(vcpu, vcpu->arch.efer);
10842
10843         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10844         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10845         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10846         /*
10847          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10848          * actually changed, because vmx_set_cr0 refers to efer set above.
10849          *
10850          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10851          * (KVM doesn't change it);
10852          */
10853         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10854         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10855
10856         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10857         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10858         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10859
10860         nested_ept_uninit_mmu_context(vcpu);
10861
10862         /*
10863          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10864          * couldn't have changed.
10865          */
10866         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10867                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10868
10869         if (!enable_ept)
10870                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10871
10872         if (enable_vpid) {
10873                 /*
10874                  * Trivially support vpid by letting L2s share their parent
10875                  * L1's vpid. TODO: move to a more elaborate solution, giving
10876                  * each L2 its own vpid and exposing the vpid feature to L1.
10877                  */
10878                 vmx_flush_tlb(vcpu);
10879         }
10880
10881
10882         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10883         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10884         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10885         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10886         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10887
10888         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10889         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10890                 vmcs_write64(GUEST_BNDCFGS, 0);
10891
10892         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10893                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10894                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10895         }
10896         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10897                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10898                         vmcs12->host_ia32_perf_global_ctrl);
10899
10900         /* Set L1 segment info according to Intel SDM
10901             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10902         seg = (struct kvm_segment) {
10903                 .base = 0,
10904                 .limit = 0xFFFFFFFF,
10905                 .selector = vmcs12->host_cs_selector,
10906                 .type = 11,
10907                 .present = 1,
10908                 .s = 1,
10909                 .g = 1
10910         };
10911         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10912                 seg.l = 1;
10913         else
10914                 seg.db = 1;
10915         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10916         seg = (struct kvm_segment) {
10917                 .base = 0,
10918                 .limit = 0xFFFFFFFF,
10919                 .type = 3,
10920                 .present = 1,
10921                 .s = 1,
10922                 .db = 1,
10923                 .g = 1
10924         };
10925         seg.selector = vmcs12->host_ds_selector;
10926         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10927         seg.selector = vmcs12->host_es_selector;
10928         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10929         seg.selector = vmcs12->host_ss_selector;
10930         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10931         seg.selector = vmcs12->host_fs_selector;
10932         seg.base = vmcs12->host_fs_base;
10933         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10934         seg.selector = vmcs12->host_gs_selector;
10935         seg.base = vmcs12->host_gs_base;
10936         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10937         seg = (struct kvm_segment) {
10938                 .base = vmcs12->host_tr_base,
10939                 .limit = 0x67,
10940                 .selector = vmcs12->host_tr_selector,
10941                 .type = 11,
10942                 .present = 1
10943         };
10944         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10945
10946         kvm_set_dr(vcpu, 7, 0x400);
10947         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10948
10949         if (cpu_has_vmx_msr_bitmap())
10950                 vmx_set_msr_bitmap(vcpu);
10951
10952         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10953                                 vmcs12->vm_exit_msr_load_count))
10954                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10955 }
10956
10957 /*
10958  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10959  * and modify vmcs12 to make it see what it would expect to see there if
10960  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10961  */
10962 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10963                               u32 exit_intr_info,
10964                               unsigned long exit_qualification)
10965 {
10966         struct vcpu_vmx *vmx = to_vmx(vcpu);
10967         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10968         u32 vm_inst_error = 0;
10969
10970         /* trying to cancel vmlaunch/vmresume is a bug */
10971         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10972
10973         leave_guest_mode(vcpu);
10974         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10975                        exit_qualification);
10976
10977         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10978                                  vmcs12->vm_exit_msr_store_count))
10979                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10980
10981         if (unlikely(vmx->fail))
10982                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
10983
10984         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10985
10986         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10987             && nested_exit_intr_ack_set(vcpu)) {
10988                 int irq = kvm_cpu_get_interrupt(vcpu);
10989                 WARN_ON(irq < 0);
10990                 vmcs12->vm_exit_intr_info = irq |
10991                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10992         }
10993
10994         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10995                                        vmcs12->exit_qualification,
10996                                        vmcs12->idt_vectoring_info_field,
10997                                        vmcs12->vm_exit_intr_info,
10998                                        vmcs12->vm_exit_intr_error_code,
10999                                        KVM_ISA_VMX);
11000
11001         vm_entry_controls_reset_shadow(vmx);
11002         vm_exit_controls_reset_shadow(vmx);
11003         vmx_segment_cache_clear(vmx);
11004
11005         /* if no vmcs02 cache requested, remove the one we used */
11006         if (VMCS02_POOL_SIZE == 0)
11007                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11008
11009         load_vmcs12_host_state(vcpu, vmcs12);
11010
11011         /* Update any VMCS fields that might have changed while L2 ran */
11012         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11013         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11014         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11015         if (vmx->hv_deadline_tsc == -1)
11016                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11017                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11018         else
11019                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11020                               PIN_BASED_VMX_PREEMPTION_TIMER);
11021         if (kvm_has_tsc_control)
11022                 decache_tsc_multiplier(vmx);
11023
11024         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11025                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11026                 vmx_set_virtual_x2apic_mode(vcpu,
11027                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11028         } else if (!nested_cpu_has_ept(vmcs12) &&
11029                    nested_cpu_has2(vmcs12,
11030                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11031                 vmx_flush_tlb_ept_only(vcpu);
11032         }
11033
11034         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11035         vmx->host_rsp = 0;
11036
11037         /* Unpin physical memory we referred to in vmcs02 */
11038         if (vmx->nested.apic_access_page) {
11039                 nested_release_page(vmx->nested.apic_access_page);
11040                 vmx->nested.apic_access_page = NULL;
11041         }
11042         if (vmx->nested.virtual_apic_page) {
11043                 nested_release_page(vmx->nested.virtual_apic_page);
11044                 vmx->nested.virtual_apic_page = NULL;
11045         }
11046         if (vmx->nested.pi_desc_page) {
11047                 kunmap(vmx->nested.pi_desc_page);
11048                 nested_release_page(vmx->nested.pi_desc_page);
11049                 vmx->nested.pi_desc_page = NULL;
11050                 vmx->nested.pi_desc = NULL;
11051         }
11052
11053         /*
11054          * We are now running in L2, mmu_notifier will force to reload the
11055          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11056          */
11057         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11058
11059         /*
11060          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11061          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11062          * success or failure flag accordingly.
11063          */
11064         if (unlikely(vmx->fail)) {
11065                 vmx->fail = 0;
11066                 nested_vmx_failValid(vcpu, vm_inst_error);
11067         } else
11068                 nested_vmx_succeed(vcpu);
11069         if (enable_shadow_vmcs)
11070                 vmx->nested.sync_shadow_vmcs = true;
11071
11072         /* in case we halted in L2 */
11073         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11074 }
11075
11076 /*
11077  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11078  */
11079 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11080 {
11081         if (is_guest_mode(vcpu)) {
11082                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11083                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11084         }
11085         free_nested(to_vmx(vcpu));
11086 }
11087
11088 /*
11089  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11090  * 23.7 "VM-entry failures during or after loading guest state" (this also
11091  * lists the acceptable exit-reason and exit-qualification parameters).
11092  * It should only be called before L2 actually succeeded to run, and when
11093  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11094  */
11095 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11096                         struct vmcs12 *vmcs12,
11097                         u32 reason, unsigned long qualification)
11098 {
11099         load_vmcs12_host_state(vcpu, vmcs12);
11100         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11101         vmcs12->exit_qualification = qualification;
11102         nested_vmx_succeed(vcpu);
11103         if (enable_shadow_vmcs)
11104                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11105 }
11106
11107 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11108                                struct x86_instruction_info *info,
11109                                enum x86_intercept_stage stage)
11110 {
11111         return X86EMUL_CONTINUE;
11112 }
11113
11114 #ifdef CONFIG_X86_64
11115 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11116 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11117                                   u64 divisor, u64 *result)
11118 {
11119         u64 low = a << shift, high = a >> (64 - shift);
11120
11121         /* To avoid the overflow on divq */
11122         if (high >= divisor)
11123                 return 1;
11124
11125         /* Low hold the result, high hold rem which is discarded */
11126         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11127             "rm" (divisor), "0" (low), "1" (high));
11128         *result = low;
11129
11130         return 0;
11131 }
11132
11133 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11134 {
11135         struct vcpu_vmx *vmx = to_vmx(vcpu);
11136         u64 tscl = rdtsc();
11137         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11138         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11139
11140         /* Convert to host delta tsc if tsc scaling is enabled */
11141         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11142                         u64_shl_div_u64(delta_tsc,
11143                                 kvm_tsc_scaling_ratio_frac_bits,
11144                                 vcpu->arch.tsc_scaling_ratio,
11145                                 &delta_tsc))
11146                 return -ERANGE;
11147
11148         /*
11149          * If the delta tsc can't fit in the 32 bit after the multi shift,
11150          * we can't use the preemption timer.
11151          * It's possible that it fits on later vmentries, but checking
11152          * on every vmentry is costly so we just use an hrtimer.
11153          */
11154         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11155                 return -ERANGE;
11156
11157         vmx->hv_deadline_tsc = tscl + delta_tsc;
11158         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11159                         PIN_BASED_VMX_PREEMPTION_TIMER);
11160         return 0;
11161 }
11162
11163 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11164 {
11165         struct vcpu_vmx *vmx = to_vmx(vcpu);
11166         vmx->hv_deadline_tsc = -1;
11167         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11168                         PIN_BASED_VMX_PREEMPTION_TIMER);
11169 }
11170 #endif
11171
11172 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11173 {
11174         if (ple_gap)
11175                 shrink_ple_window(vcpu);
11176 }
11177
11178 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11179                                      struct kvm_memory_slot *slot)
11180 {
11181         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11182         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11183 }
11184
11185 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11186                                        struct kvm_memory_slot *slot)
11187 {
11188         kvm_mmu_slot_set_dirty(kvm, slot);
11189 }
11190
11191 static void vmx_flush_log_dirty(struct kvm *kvm)
11192 {
11193         kvm_flush_pml_buffers(kvm);
11194 }
11195
11196 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11197 {
11198         struct vmcs12 *vmcs12;
11199         struct vcpu_vmx *vmx = to_vmx(vcpu);
11200         gpa_t gpa;
11201         struct page *page = NULL;
11202         u64 *pml_address;
11203
11204         if (is_guest_mode(vcpu)) {
11205                 WARN_ON_ONCE(vmx->nested.pml_full);
11206
11207                 /*
11208                  * Check if PML is enabled for the nested guest.
11209                  * Whether eptp bit 6 is set is already checked
11210                  * as part of A/D emulation.
11211                  */
11212                 vmcs12 = get_vmcs12(vcpu);
11213                 if (!nested_cpu_has_pml(vmcs12))
11214                         return 0;
11215
11216                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11217                         vmx->nested.pml_full = true;
11218                         return 1;
11219                 }
11220
11221                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11222
11223                 page = nested_get_page(vcpu, vmcs12->pml_address);
11224                 if (!page)
11225                         return 0;
11226
11227                 pml_address = kmap(page);
11228                 pml_address[vmcs12->guest_pml_index--] = gpa;
11229                 kunmap(page);
11230                 nested_release_page_clean(page);
11231         }
11232
11233         return 0;
11234 }
11235
11236 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11237                                            struct kvm_memory_slot *memslot,
11238                                            gfn_t offset, unsigned long mask)
11239 {
11240         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11241 }
11242
11243 /*
11244  * This routine does the following things for vCPU which is going
11245  * to be blocked if VT-d PI is enabled.
11246  * - Store the vCPU to the wakeup list, so when interrupts happen
11247  *   we can find the right vCPU to wake up.
11248  * - Change the Posted-interrupt descriptor as below:
11249  *      'NDST' <-- vcpu->pre_pcpu
11250  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11251  * - If 'ON' is set during this process, which means at least one
11252  *   interrupt is posted for this vCPU, we cannot block it, in
11253  *   this case, return 1, otherwise, return 0.
11254  *
11255  */
11256 static int pi_pre_block(struct kvm_vcpu *vcpu)
11257 {
11258         unsigned long flags;
11259         unsigned int dest;
11260         struct pi_desc old, new;
11261         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11262
11263         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11264                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11265                 !kvm_vcpu_apicv_active(vcpu))
11266                 return 0;
11267
11268         vcpu->pre_pcpu = vcpu->cpu;
11269         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11270                           vcpu->pre_pcpu), flags);
11271         list_add_tail(&vcpu->blocked_vcpu_list,
11272                       &per_cpu(blocked_vcpu_on_cpu,
11273                       vcpu->pre_pcpu));
11274         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11275                                vcpu->pre_pcpu), flags);
11276
11277         do {
11278                 old.control = new.control = pi_desc->control;
11279
11280                 /*
11281                  * We should not block the vCPU if
11282                  * an interrupt is posted for it.
11283                  */
11284                 if (pi_test_on(pi_desc) == 1) {
11285                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11286                                           vcpu->pre_pcpu), flags);
11287                         list_del(&vcpu->blocked_vcpu_list);
11288                         spin_unlock_irqrestore(
11289                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11290                                         vcpu->pre_pcpu), flags);
11291                         vcpu->pre_pcpu = -1;
11292
11293                         return 1;
11294                 }
11295
11296                 WARN((pi_desc->sn == 1),
11297                      "Warning: SN field of posted-interrupts "
11298                      "is set before blocking\n");
11299
11300                 /*
11301                  * Since vCPU can be preempted during this process,
11302                  * vcpu->cpu could be different with pre_pcpu, we
11303                  * need to set pre_pcpu as the destination of wakeup
11304                  * notification event, then we can find the right vCPU
11305                  * to wakeup in wakeup handler if interrupts happen
11306                  * when the vCPU is in blocked state.
11307                  */
11308                 dest = cpu_physical_id(vcpu->pre_pcpu);
11309
11310                 if (x2apic_enabled())
11311                         new.ndst = dest;
11312                 else
11313                         new.ndst = (dest << 8) & 0xFF00;
11314
11315                 /* set 'NV' to 'wakeup vector' */
11316                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11317         } while (cmpxchg(&pi_desc->control, old.control,
11318                         new.control) != old.control);
11319
11320         return 0;
11321 }
11322
11323 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11324 {
11325         if (pi_pre_block(vcpu))
11326                 return 1;
11327
11328         if (kvm_lapic_hv_timer_in_use(vcpu))
11329                 kvm_lapic_switch_to_sw_timer(vcpu);
11330
11331         return 0;
11332 }
11333
11334 static void pi_post_block(struct kvm_vcpu *vcpu)
11335 {
11336         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11337         struct pi_desc old, new;
11338         unsigned int dest;
11339         unsigned long flags;
11340
11341         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11342                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11343                 !kvm_vcpu_apicv_active(vcpu))
11344                 return;
11345
11346         do {
11347                 old.control = new.control = pi_desc->control;
11348
11349                 dest = cpu_physical_id(vcpu->cpu);
11350
11351                 if (x2apic_enabled())
11352                         new.ndst = dest;
11353                 else
11354                         new.ndst = (dest << 8) & 0xFF00;
11355
11356                 /* Allow posting non-urgent interrupts */
11357                 new.sn = 0;
11358
11359                 /* set 'NV' to 'notification vector' */
11360                 new.nv = POSTED_INTR_VECTOR;
11361         } while (cmpxchg(&pi_desc->control, old.control,
11362                         new.control) != old.control);
11363
11364         if(vcpu->pre_pcpu != -1) {
11365                 spin_lock_irqsave(
11366                         &per_cpu(blocked_vcpu_on_cpu_lock,
11367                         vcpu->pre_pcpu), flags);
11368                 list_del(&vcpu->blocked_vcpu_list);
11369                 spin_unlock_irqrestore(
11370                         &per_cpu(blocked_vcpu_on_cpu_lock,
11371                         vcpu->pre_pcpu), flags);
11372                 vcpu->pre_pcpu = -1;
11373         }
11374 }
11375
11376 static void vmx_post_block(struct kvm_vcpu *vcpu)
11377 {
11378         if (kvm_x86_ops->set_hv_timer)
11379                 kvm_lapic_switch_to_hv_timer(vcpu);
11380
11381         pi_post_block(vcpu);
11382 }
11383
11384 /*
11385  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11386  *
11387  * @kvm: kvm
11388  * @host_irq: host irq of the interrupt
11389  * @guest_irq: gsi of the interrupt
11390  * @set: set or unset PI
11391  * returns 0 on success, < 0 on failure
11392  */
11393 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11394                               uint32_t guest_irq, bool set)
11395 {
11396         struct kvm_kernel_irq_routing_entry *e;
11397         struct kvm_irq_routing_table *irq_rt;
11398         struct kvm_lapic_irq irq;
11399         struct kvm_vcpu *vcpu;
11400         struct vcpu_data vcpu_info;
11401         int idx, ret = -EINVAL;
11402
11403         if (!kvm_arch_has_assigned_device(kvm) ||
11404                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11405                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11406                 return 0;
11407
11408         idx = srcu_read_lock(&kvm->irq_srcu);
11409         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11410         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11411
11412         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11413                 if (e->type != KVM_IRQ_ROUTING_MSI)
11414                         continue;
11415                 /*
11416                  * VT-d PI cannot support posting multicast/broadcast
11417                  * interrupts to a vCPU, we still use interrupt remapping
11418                  * for these kind of interrupts.
11419                  *
11420                  * For lowest-priority interrupts, we only support
11421                  * those with single CPU as the destination, e.g. user
11422                  * configures the interrupts via /proc/irq or uses
11423                  * irqbalance to make the interrupts single-CPU.
11424                  *
11425                  * We will support full lowest-priority interrupt later.
11426                  */
11427
11428                 kvm_set_msi_irq(kvm, e, &irq);
11429                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11430                         /*
11431                          * Make sure the IRTE is in remapped mode if
11432                          * we don't handle it in posted mode.
11433                          */
11434                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11435                         if (ret < 0) {
11436                                 printk(KERN_INFO
11437                                    "failed to back to remapped mode, irq: %u\n",
11438                                    host_irq);
11439                                 goto out;
11440                         }
11441
11442                         continue;
11443                 }
11444
11445                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11446                 vcpu_info.vector = irq.vector;
11447
11448                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11449                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11450
11451                 if (set)
11452                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11453                 else {
11454                         /* suppress notification event before unposting */
11455                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11456                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11457                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11458                 }
11459
11460                 if (ret < 0) {
11461                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11462                                         __func__);
11463                         goto out;
11464                 }
11465         }
11466
11467         ret = 0;
11468 out:
11469         srcu_read_unlock(&kvm->irq_srcu, idx);
11470         return ret;
11471 }
11472
11473 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11474 {
11475         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11476                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11477                         FEATURE_CONTROL_LMCE;
11478         else
11479                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11480                         ~FEATURE_CONTROL_LMCE;
11481 }
11482
11483 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11484         .cpu_has_kvm_support = cpu_has_kvm_support,
11485         .disabled_by_bios = vmx_disabled_by_bios,
11486         .hardware_setup = hardware_setup,
11487         .hardware_unsetup = hardware_unsetup,
11488         .check_processor_compatibility = vmx_check_processor_compat,
11489         .hardware_enable = hardware_enable,
11490         .hardware_disable = hardware_disable,
11491         .cpu_has_accelerated_tpr = report_flexpriority,
11492         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11493
11494         .vcpu_create = vmx_create_vcpu,
11495         .vcpu_free = vmx_free_vcpu,
11496         .vcpu_reset = vmx_vcpu_reset,
11497
11498         .prepare_guest_switch = vmx_save_host_state,
11499         .vcpu_load = vmx_vcpu_load,
11500         .vcpu_put = vmx_vcpu_put,
11501
11502         .update_bp_intercept = update_exception_bitmap,
11503         .get_msr = vmx_get_msr,
11504         .set_msr = vmx_set_msr,
11505         .get_segment_base = vmx_get_segment_base,
11506         .get_segment = vmx_get_segment,
11507         .set_segment = vmx_set_segment,
11508         .get_cpl = vmx_get_cpl,
11509         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11510         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11511         .decache_cr3 = vmx_decache_cr3,
11512         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11513         .set_cr0 = vmx_set_cr0,
11514         .set_cr3 = vmx_set_cr3,
11515         .set_cr4 = vmx_set_cr4,
11516         .set_efer = vmx_set_efer,
11517         .get_idt = vmx_get_idt,
11518         .set_idt = vmx_set_idt,
11519         .get_gdt = vmx_get_gdt,
11520         .set_gdt = vmx_set_gdt,
11521         .get_dr6 = vmx_get_dr6,
11522         .set_dr6 = vmx_set_dr6,
11523         .set_dr7 = vmx_set_dr7,
11524         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11525         .cache_reg = vmx_cache_reg,
11526         .get_rflags = vmx_get_rflags,
11527         .set_rflags = vmx_set_rflags,
11528
11529         .get_pkru = vmx_get_pkru,
11530
11531         .tlb_flush = vmx_flush_tlb,
11532
11533         .run = vmx_vcpu_run,
11534         .handle_exit = vmx_handle_exit,
11535         .skip_emulated_instruction = skip_emulated_instruction,
11536         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11537         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11538         .patch_hypercall = vmx_patch_hypercall,
11539         .set_irq = vmx_inject_irq,
11540         .set_nmi = vmx_inject_nmi,
11541         .queue_exception = vmx_queue_exception,
11542         .cancel_injection = vmx_cancel_injection,
11543         .interrupt_allowed = vmx_interrupt_allowed,
11544         .nmi_allowed = vmx_nmi_allowed,
11545         .get_nmi_mask = vmx_get_nmi_mask,
11546         .set_nmi_mask = vmx_set_nmi_mask,
11547         .enable_nmi_window = enable_nmi_window,
11548         .enable_irq_window = enable_irq_window,
11549         .update_cr8_intercept = update_cr8_intercept,
11550         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11551         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11552         .get_enable_apicv = vmx_get_enable_apicv,
11553         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11554         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11555         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11556         .hwapic_irr_update = vmx_hwapic_irr_update,
11557         .hwapic_isr_update = vmx_hwapic_isr_update,
11558         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11559         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11560
11561         .set_tss_addr = vmx_set_tss_addr,
11562         .get_tdp_level = get_ept_level,
11563         .get_mt_mask = vmx_get_mt_mask,
11564
11565         .get_exit_info = vmx_get_exit_info,
11566
11567         .get_lpage_level = vmx_get_lpage_level,
11568
11569         .cpuid_update = vmx_cpuid_update,
11570
11571         .rdtscp_supported = vmx_rdtscp_supported,
11572         .invpcid_supported = vmx_invpcid_supported,
11573
11574         .set_supported_cpuid = vmx_set_supported_cpuid,
11575
11576         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11577
11578         .write_tsc_offset = vmx_write_tsc_offset,
11579
11580         .set_tdp_cr3 = vmx_set_cr3,
11581
11582         .check_intercept = vmx_check_intercept,
11583         .handle_external_intr = vmx_handle_external_intr,
11584         .mpx_supported = vmx_mpx_supported,
11585         .xsaves_supported = vmx_xsaves_supported,
11586
11587         .check_nested_events = vmx_check_nested_events,
11588
11589         .sched_in = vmx_sched_in,
11590
11591         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11592         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11593         .flush_log_dirty = vmx_flush_log_dirty,
11594         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11595         .write_log_dirty = vmx_write_pml_buffer,
11596
11597         .pre_block = vmx_pre_block,
11598         .post_block = vmx_post_block,
11599
11600         .pmu_ops = &intel_pmu_ops,
11601
11602         .update_pi_irte = vmx_update_pi_irte,
11603
11604 #ifdef CONFIG_X86_64
11605         .set_hv_timer = vmx_set_hv_timer,
11606         .cancel_hv_timer = vmx_cancel_hv_timer,
11607 #endif
11608
11609         .setup_mce = vmx_setup_mce,
11610 };
11611
11612 static int __init vmx_init(void)
11613 {
11614         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11615                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11616         if (r)
11617                 return r;
11618
11619 #ifdef CONFIG_KEXEC_CORE
11620         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11621                            crash_vmclear_local_loaded_vmcss);
11622 #endif
11623
11624         return 0;
11625 }
11626
11627 static void __exit vmx_exit(void)
11628 {
11629 #ifdef CONFIG_KEXEC_CORE
11630         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11631         synchronize_rcu();
11632 #endif
11633
11634         kvm_exit();
11635 }
11636
11637 module_init(vmx_init)
11638 module_exit(vmx_exit)