Merge branches 'arm/rockchip', 'arm/exynos', 'arm/smmu', 'x86/vt-d', 'x86/amd', ...
[sfrench/cifs-2.6.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9  *
10  * Authors:
11  *   Avi Kivity   <avi@qumranet.com>
12  *   Yaniv Kamay  <yaniv@qumranet.com>
13  *
14  * This work is licensed under the terms of the GNU GPL, version 2.  See
15  * the COPYING file in the top-level directory.
16  *
17  */
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "cpuid.h"
22
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
36 #include "x86.h"
37
38 #include <asm/io.h>
39 #include <asm/desc.h>
40 #include <asm/vmx.h>
41 #include <asm/virtext.h>
42 #include <asm/mce.h>
43 #include <asm/i387.h>
44 #include <asm/xcr.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
48 #include <asm/apic.h>
49
50 #include "trace.h"
51
52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
53 #define __ex_clear(x, reg) \
54         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
55
56 MODULE_AUTHOR("Qumranet");
57 MODULE_LICENSE("GPL");
58
59 static const struct x86_cpu_id vmx_cpu_id[] = {
60         X86_FEATURE_MATCH(X86_FEATURE_VMX),
61         {}
62 };
63 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
64
65 static bool __read_mostly enable_vpid = 1;
66 module_param_named(vpid, enable_vpid, bool, 0444);
67
68 static bool __read_mostly flexpriority_enabled = 1;
69 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
70
71 static bool __read_mostly enable_ept = 1;
72 module_param_named(ept, enable_ept, bool, S_IRUGO);
73
74 static bool __read_mostly enable_unrestricted_guest = 1;
75 module_param_named(unrestricted_guest,
76                         enable_unrestricted_guest, bool, S_IRUGO);
77
78 static bool __read_mostly enable_ept_ad_bits = 1;
79 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
80
81 static bool __read_mostly emulate_invalid_guest_state = true;
82 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
83
84 static bool __read_mostly vmm_exclusive = 1;
85 module_param(vmm_exclusive, bool, S_IRUGO);
86
87 static bool __read_mostly fasteoi = 1;
88 module_param(fasteoi, bool, S_IRUGO);
89
90 static bool __read_mostly enable_apicv = 1;
91 module_param(enable_apicv, bool, S_IRUGO);
92
93 static bool __read_mostly enable_shadow_vmcs = 1;
94 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
95 /*
96  * If nested=1, nested virtualization is supported, i.e., guests may use
97  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98  * use VMX instructions.
99  */
100 static bool __read_mostly nested = 0;
101 module_param(nested, bool, S_IRUGO);
102
103 static u64 __read_mostly host_xss;
104
105 static bool __read_mostly enable_pml = 1;
106 module_param_named(pml, enable_pml, bool, S_IRUGO);
107
108 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
110 #define KVM_VM_CR0_ALWAYS_ON                                            \
111         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
112 #define KVM_CR4_GUEST_OWNED_BITS                                      \
113         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
114          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
115
116 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118
119 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120
121 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
122
123 /*
124  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125  * ple_gap:    upper bound on the amount of time between two successive
126  *             executions of PAUSE in a loop. Also indicate if ple enabled.
127  *             According to test, this time is usually smaller than 128 cycles.
128  * ple_window: upper bound on the amount of time a guest is allowed to execute
129  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
130  *             less than 2^12 cycles
131  * Time is measured based on a counter that runs at the same rate as the TSC,
132  * refer SDM volume 3b section 21.6.13 & 22.1.3.
133  */
134 #define KVM_VMX_DEFAULT_PLE_GAP           128
135 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
136 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
137 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
139                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140
141 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142 module_param(ple_gap, int, S_IRUGO);
143
144 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145 module_param(ple_window, int, S_IRUGO);
146
147 /* Default doubles per-vcpu window every exit. */
148 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149 module_param(ple_window_grow, int, S_IRUGO);
150
151 /* Default resets per-vcpu window every exit to ple_window. */
152 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153 module_param(ple_window_shrink, int, S_IRUGO);
154
155 /* Default is to compute the maximum so we can never overflow. */
156 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158 module_param(ple_window_max, int, S_IRUGO);
159
160 extern const ulong vmx_return;
161
162 #define NR_AUTOLOAD_MSRS 8
163 #define VMCS02_POOL_SIZE 1
164
165 struct vmcs {
166         u32 revision_id;
167         u32 abort;
168         char data[0];
169 };
170
171 /*
172  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174  * loaded on this CPU (so we can clear them if the CPU goes down).
175  */
176 struct loaded_vmcs {
177         struct vmcs *vmcs;
178         int cpu;
179         int launched;
180         struct list_head loaded_vmcss_on_cpu_link;
181 };
182
183 struct shared_msr_entry {
184         unsigned index;
185         u64 data;
186         u64 mask;
187 };
188
189 /*
190  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195  * More than one of these structures may exist, if L1 runs multiple L2 guests.
196  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197  * underlying hardware which will be used to run L2.
198  * This structure is packed to ensure that its layout is identical across
199  * machines (necessary for live migration).
200  * If there are changes in this struct, VMCS12_REVISION must be changed.
201  */
202 typedef u64 natural_width;
203 struct __packed vmcs12 {
204         /* According to the Intel spec, a VMCS region must start with the
205          * following two fields. Then follow implementation-specific data.
206          */
207         u32 revision_id;
208         u32 abort;
209
210         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211         u32 padding[7]; /* room for future expansion */
212
213         u64 io_bitmap_a;
214         u64 io_bitmap_b;
215         u64 msr_bitmap;
216         u64 vm_exit_msr_store_addr;
217         u64 vm_exit_msr_load_addr;
218         u64 vm_entry_msr_load_addr;
219         u64 tsc_offset;
220         u64 virtual_apic_page_addr;
221         u64 apic_access_addr;
222         u64 posted_intr_desc_addr;
223         u64 ept_pointer;
224         u64 eoi_exit_bitmap0;
225         u64 eoi_exit_bitmap1;
226         u64 eoi_exit_bitmap2;
227         u64 eoi_exit_bitmap3;
228         u64 xss_exit_bitmap;
229         u64 guest_physical_address;
230         u64 vmcs_link_pointer;
231         u64 guest_ia32_debugctl;
232         u64 guest_ia32_pat;
233         u64 guest_ia32_efer;
234         u64 guest_ia32_perf_global_ctrl;
235         u64 guest_pdptr0;
236         u64 guest_pdptr1;
237         u64 guest_pdptr2;
238         u64 guest_pdptr3;
239         u64 guest_bndcfgs;
240         u64 host_ia32_pat;
241         u64 host_ia32_efer;
242         u64 host_ia32_perf_global_ctrl;
243         u64 padding64[8]; /* room for future expansion */
244         /*
245          * To allow migration of L1 (complete with its L2 guests) between
246          * machines of different natural widths (32 or 64 bit), we cannot have
247          * unsigned long fields with no explict size. We use u64 (aliased
248          * natural_width) instead. Luckily, x86 is little-endian.
249          */
250         natural_width cr0_guest_host_mask;
251         natural_width cr4_guest_host_mask;
252         natural_width cr0_read_shadow;
253         natural_width cr4_read_shadow;
254         natural_width cr3_target_value0;
255         natural_width cr3_target_value1;
256         natural_width cr3_target_value2;
257         natural_width cr3_target_value3;
258         natural_width exit_qualification;
259         natural_width guest_linear_address;
260         natural_width guest_cr0;
261         natural_width guest_cr3;
262         natural_width guest_cr4;
263         natural_width guest_es_base;
264         natural_width guest_cs_base;
265         natural_width guest_ss_base;
266         natural_width guest_ds_base;
267         natural_width guest_fs_base;
268         natural_width guest_gs_base;
269         natural_width guest_ldtr_base;
270         natural_width guest_tr_base;
271         natural_width guest_gdtr_base;
272         natural_width guest_idtr_base;
273         natural_width guest_dr7;
274         natural_width guest_rsp;
275         natural_width guest_rip;
276         natural_width guest_rflags;
277         natural_width guest_pending_dbg_exceptions;
278         natural_width guest_sysenter_esp;
279         natural_width guest_sysenter_eip;
280         natural_width host_cr0;
281         natural_width host_cr3;
282         natural_width host_cr4;
283         natural_width host_fs_base;
284         natural_width host_gs_base;
285         natural_width host_tr_base;
286         natural_width host_gdtr_base;
287         natural_width host_idtr_base;
288         natural_width host_ia32_sysenter_esp;
289         natural_width host_ia32_sysenter_eip;
290         natural_width host_rsp;
291         natural_width host_rip;
292         natural_width paddingl[8]; /* room for future expansion */
293         u32 pin_based_vm_exec_control;
294         u32 cpu_based_vm_exec_control;
295         u32 exception_bitmap;
296         u32 page_fault_error_code_mask;
297         u32 page_fault_error_code_match;
298         u32 cr3_target_count;
299         u32 vm_exit_controls;
300         u32 vm_exit_msr_store_count;
301         u32 vm_exit_msr_load_count;
302         u32 vm_entry_controls;
303         u32 vm_entry_msr_load_count;
304         u32 vm_entry_intr_info_field;
305         u32 vm_entry_exception_error_code;
306         u32 vm_entry_instruction_len;
307         u32 tpr_threshold;
308         u32 secondary_vm_exec_control;
309         u32 vm_instruction_error;
310         u32 vm_exit_reason;
311         u32 vm_exit_intr_info;
312         u32 vm_exit_intr_error_code;
313         u32 idt_vectoring_info_field;
314         u32 idt_vectoring_error_code;
315         u32 vm_exit_instruction_len;
316         u32 vmx_instruction_info;
317         u32 guest_es_limit;
318         u32 guest_cs_limit;
319         u32 guest_ss_limit;
320         u32 guest_ds_limit;
321         u32 guest_fs_limit;
322         u32 guest_gs_limit;
323         u32 guest_ldtr_limit;
324         u32 guest_tr_limit;
325         u32 guest_gdtr_limit;
326         u32 guest_idtr_limit;
327         u32 guest_es_ar_bytes;
328         u32 guest_cs_ar_bytes;
329         u32 guest_ss_ar_bytes;
330         u32 guest_ds_ar_bytes;
331         u32 guest_fs_ar_bytes;
332         u32 guest_gs_ar_bytes;
333         u32 guest_ldtr_ar_bytes;
334         u32 guest_tr_ar_bytes;
335         u32 guest_interruptibility_info;
336         u32 guest_activity_state;
337         u32 guest_sysenter_cs;
338         u32 host_ia32_sysenter_cs;
339         u32 vmx_preemption_timer_value;
340         u32 padding32[7]; /* room for future expansion */
341         u16 virtual_processor_id;
342         u16 posted_intr_nv;
343         u16 guest_es_selector;
344         u16 guest_cs_selector;
345         u16 guest_ss_selector;
346         u16 guest_ds_selector;
347         u16 guest_fs_selector;
348         u16 guest_gs_selector;
349         u16 guest_ldtr_selector;
350         u16 guest_tr_selector;
351         u16 guest_intr_status;
352         u16 host_es_selector;
353         u16 host_cs_selector;
354         u16 host_ss_selector;
355         u16 host_ds_selector;
356         u16 host_fs_selector;
357         u16 host_gs_selector;
358         u16 host_tr_selector;
359 };
360
361 /*
362  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
365  */
366 #define VMCS12_REVISION 0x11e57ed0
367
368 /*
369  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371  * current implementation, 4K are reserved to avoid future complications.
372  */
373 #define VMCS12_SIZE 0x1000
374
375 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
376 struct vmcs02_list {
377         struct list_head list;
378         gpa_t vmptr;
379         struct loaded_vmcs vmcs02;
380 };
381
382 /*
383  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
385  */
386 struct nested_vmx {
387         /* Has the level1 guest done vmxon? */
388         bool vmxon;
389         gpa_t vmxon_ptr;
390
391         /* The guest-physical address of the current VMCS L1 keeps for L2 */
392         gpa_t current_vmptr;
393         /* The host-usable pointer to the above */
394         struct page *current_vmcs12_page;
395         struct vmcs12 *current_vmcs12;
396         struct vmcs *current_shadow_vmcs;
397         /*
398          * Indicates if the shadow vmcs must be updated with the
399          * data hold by vmcs12
400          */
401         bool sync_shadow_vmcs;
402
403         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404         struct list_head vmcs02_pool;
405         int vmcs02_num;
406         u64 vmcs01_tsc_offset;
407         /* L2 must run next, and mustn't decide to exit to L1. */
408         bool nested_run_pending;
409         /*
410          * Guest pages referred to in vmcs02 with host-physical pointers, so
411          * we must keep them pinned while L2 runs.
412          */
413         struct page *apic_access_page;
414         struct page *virtual_apic_page;
415         struct page *pi_desc_page;
416         struct pi_desc *pi_desc;
417         bool pi_pending;
418         u16 posted_intr_nv;
419         u64 msr_ia32_feature_control;
420
421         struct hrtimer preemption_timer;
422         bool preemption_timer_expired;
423
424         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
425         u64 vmcs01_debugctl;
426
427         u32 nested_vmx_procbased_ctls_low;
428         u32 nested_vmx_procbased_ctls_high;
429         u32 nested_vmx_true_procbased_ctls_low;
430         u32 nested_vmx_secondary_ctls_low;
431         u32 nested_vmx_secondary_ctls_high;
432         u32 nested_vmx_pinbased_ctls_low;
433         u32 nested_vmx_pinbased_ctls_high;
434         u32 nested_vmx_exit_ctls_low;
435         u32 nested_vmx_exit_ctls_high;
436         u32 nested_vmx_true_exit_ctls_low;
437         u32 nested_vmx_entry_ctls_low;
438         u32 nested_vmx_entry_ctls_high;
439         u32 nested_vmx_true_entry_ctls_low;
440         u32 nested_vmx_misc_low;
441         u32 nested_vmx_misc_high;
442         u32 nested_vmx_ept_caps;
443 };
444
445 #define POSTED_INTR_ON  0
446 /* Posted-Interrupt Descriptor */
447 struct pi_desc {
448         u32 pir[8];     /* Posted interrupt requested */
449         u32 control;    /* bit 0 of control is outstanding notification bit */
450         u32 rsvd[7];
451 } __aligned(64);
452
453 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
454 {
455         return test_and_set_bit(POSTED_INTR_ON,
456                         (unsigned long *)&pi_desc->control);
457 }
458
459 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
460 {
461         return test_and_clear_bit(POSTED_INTR_ON,
462                         (unsigned long *)&pi_desc->control);
463 }
464
465 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
466 {
467         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
468 }
469
470 struct vcpu_vmx {
471         struct kvm_vcpu       vcpu;
472         unsigned long         host_rsp;
473         u8                    fail;
474         bool                  nmi_known_unmasked;
475         u32                   exit_intr_info;
476         u32                   idt_vectoring_info;
477         ulong                 rflags;
478         struct shared_msr_entry *guest_msrs;
479         int                   nmsrs;
480         int                   save_nmsrs;
481         unsigned long         host_idt_base;
482 #ifdef CONFIG_X86_64
483         u64                   msr_host_kernel_gs_base;
484         u64                   msr_guest_kernel_gs_base;
485 #endif
486         u32 vm_entry_controls_shadow;
487         u32 vm_exit_controls_shadow;
488         /*
489          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490          * non-nested (L1) guest, it always points to vmcs01. For a nested
491          * guest (L2), it points to a different VMCS.
492          */
493         struct loaded_vmcs    vmcs01;
494         struct loaded_vmcs   *loaded_vmcs;
495         bool                  __launched; /* temporary, used in vmx_vcpu_run */
496         struct msr_autoload {
497                 unsigned nr;
498                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
499                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
500         } msr_autoload;
501         struct {
502                 int           loaded;
503                 u16           fs_sel, gs_sel, ldt_sel;
504 #ifdef CONFIG_X86_64
505                 u16           ds_sel, es_sel;
506 #endif
507                 int           gs_ldt_reload_needed;
508                 int           fs_reload_needed;
509                 u64           msr_host_bndcfgs;
510                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
511         } host_state;
512         struct {
513                 int vm86_active;
514                 ulong save_rflags;
515                 struct kvm_segment segs[8];
516         } rmode;
517         struct {
518                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
519                 struct kvm_save_segment {
520                         u16 selector;
521                         unsigned long base;
522                         u32 limit;
523                         u32 ar;
524                 } seg[8];
525         } segment_cache;
526         int vpid;
527         bool emulation_required;
528
529         /* Support for vnmi-less CPUs */
530         int soft_vnmi_blocked;
531         ktime_t entry_time;
532         s64 vnmi_blocked_time;
533         u32 exit_reason;
534
535         bool rdtscp_enabled;
536
537         /* Posted interrupt descriptor */
538         struct pi_desc pi_desc;
539
540         /* Support for a guest hypervisor (nested VMX) */
541         struct nested_vmx nested;
542
543         /* Dynamic PLE window. */
544         int ple_window;
545         bool ple_window_dirty;
546
547         /* Support for PML */
548 #define PML_ENTITY_NUM          512
549         struct page *pml_pg;
550 };
551
552 enum segment_cache_field {
553         SEG_FIELD_SEL = 0,
554         SEG_FIELD_BASE = 1,
555         SEG_FIELD_LIMIT = 2,
556         SEG_FIELD_AR = 3,
557
558         SEG_FIELD_NR = 4
559 };
560
561 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
562 {
563         return container_of(vcpu, struct vcpu_vmx, vcpu);
564 }
565
566 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
567 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
568 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
569                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
570
571
572 static unsigned long shadow_read_only_fields[] = {
573         /*
574          * We do NOT shadow fields that are modified when L0
575          * traps and emulates any vmx instruction (e.g. VMPTRLD,
576          * VMXON...) executed by L1.
577          * For example, VM_INSTRUCTION_ERROR is read
578          * by L1 if a vmx instruction fails (part of the error path).
579          * Note the code assumes this logic. If for some reason
580          * we start shadowing these fields then we need to
581          * force a shadow sync when L0 emulates vmx instructions
582          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
583          * by nested_vmx_failValid)
584          */
585         VM_EXIT_REASON,
586         VM_EXIT_INTR_INFO,
587         VM_EXIT_INSTRUCTION_LEN,
588         IDT_VECTORING_INFO_FIELD,
589         IDT_VECTORING_ERROR_CODE,
590         VM_EXIT_INTR_ERROR_CODE,
591         EXIT_QUALIFICATION,
592         GUEST_LINEAR_ADDRESS,
593         GUEST_PHYSICAL_ADDRESS
594 };
595 static int max_shadow_read_only_fields =
596         ARRAY_SIZE(shadow_read_only_fields);
597
598 static unsigned long shadow_read_write_fields[] = {
599         TPR_THRESHOLD,
600         GUEST_RIP,
601         GUEST_RSP,
602         GUEST_CR0,
603         GUEST_CR3,
604         GUEST_CR4,
605         GUEST_INTERRUPTIBILITY_INFO,
606         GUEST_RFLAGS,
607         GUEST_CS_SELECTOR,
608         GUEST_CS_AR_BYTES,
609         GUEST_CS_LIMIT,
610         GUEST_CS_BASE,
611         GUEST_ES_BASE,
612         GUEST_BNDCFGS,
613         CR0_GUEST_HOST_MASK,
614         CR0_READ_SHADOW,
615         CR4_READ_SHADOW,
616         TSC_OFFSET,
617         EXCEPTION_BITMAP,
618         CPU_BASED_VM_EXEC_CONTROL,
619         VM_ENTRY_EXCEPTION_ERROR_CODE,
620         VM_ENTRY_INTR_INFO_FIELD,
621         VM_ENTRY_INSTRUCTION_LEN,
622         VM_ENTRY_EXCEPTION_ERROR_CODE,
623         HOST_FS_BASE,
624         HOST_GS_BASE,
625         HOST_FS_SELECTOR,
626         HOST_GS_SELECTOR
627 };
628 static int max_shadow_read_write_fields =
629         ARRAY_SIZE(shadow_read_write_fields);
630
631 static const unsigned short vmcs_field_to_offset_table[] = {
632         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
633         FIELD(POSTED_INTR_NV, posted_intr_nv),
634         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
635         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
636         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
637         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
638         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
639         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
640         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
641         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
642         FIELD(GUEST_INTR_STATUS, guest_intr_status),
643         FIELD(HOST_ES_SELECTOR, host_es_selector),
644         FIELD(HOST_CS_SELECTOR, host_cs_selector),
645         FIELD(HOST_SS_SELECTOR, host_ss_selector),
646         FIELD(HOST_DS_SELECTOR, host_ds_selector),
647         FIELD(HOST_FS_SELECTOR, host_fs_selector),
648         FIELD(HOST_GS_SELECTOR, host_gs_selector),
649         FIELD(HOST_TR_SELECTOR, host_tr_selector),
650         FIELD64(IO_BITMAP_A, io_bitmap_a),
651         FIELD64(IO_BITMAP_B, io_bitmap_b),
652         FIELD64(MSR_BITMAP, msr_bitmap),
653         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
654         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
655         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
656         FIELD64(TSC_OFFSET, tsc_offset),
657         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
658         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
659         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
660         FIELD64(EPT_POINTER, ept_pointer),
661         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
662         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
663         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
664         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
665         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
666         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
667         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
668         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
669         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
670         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
671         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
672         FIELD64(GUEST_PDPTR0, guest_pdptr0),
673         FIELD64(GUEST_PDPTR1, guest_pdptr1),
674         FIELD64(GUEST_PDPTR2, guest_pdptr2),
675         FIELD64(GUEST_PDPTR3, guest_pdptr3),
676         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
677         FIELD64(HOST_IA32_PAT, host_ia32_pat),
678         FIELD64(HOST_IA32_EFER, host_ia32_efer),
679         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
680         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
681         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
682         FIELD(EXCEPTION_BITMAP, exception_bitmap),
683         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
684         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
685         FIELD(CR3_TARGET_COUNT, cr3_target_count),
686         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
687         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
688         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
689         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
690         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
691         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
692         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
693         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
694         FIELD(TPR_THRESHOLD, tpr_threshold),
695         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
696         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
697         FIELD(VM_EXIT_REASON, vm_exit_reason),
698         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
699         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
700         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
701         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
702         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
703         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
704         FIELD(GUEST_ES_LIMIT, guest_es_limit),
705         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
706         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
707         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
708         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
709         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
710         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
711         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
712         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
713         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
714         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
715         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
716         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
717         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
718         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
719         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
720         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
721         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
722         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
723         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
724         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
725         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
726         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
727         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
728         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
729         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
730         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
731         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
732         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
733         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
734         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
735         FIELD(EXIT_QUALIFICATION, exit_qualification),
736         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
737         FIELD(GUEST_CR0, guest_cr0),
738         FIELD(GUEST_CR3, guest_cr3),
739         FIELD(GUEST_CR4, guest_cr4),
740         FIELD(GUEST_ES_BASE, guest_es_base),
741         FIELD(GUEST_CS_BASE, guest_cs_base),
742         FIELD(GUEST_SS_BASE, guest_ss_base),
743         FIELD(GUEST_DS_BASE, guest_ds_base),
744         FIELD(GUEST_FS_BASE, guest_fs_base),
745         FIELD(GUEST_GS_BASE, guest_gs_base),
746         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
747         FIELD(GUEST_TR_BASE, guest_tr_base),
748         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
749         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
750         FIELD(GUEST_DR7, guest_dr7),
751         FIELD(GUEST_RSP, guest_rsp),
752         FIELD(GUEST_RIP, guest_rip),
753         FIELD(GUEST_RFLAGS, guest_rflags),
754         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
755         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
756         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
757         FIELD(HOST_CR0, host_cr0),
758         FIELD(HOST_CR3, host_cr3),
759         FIELD(HOST_CR4, host_cr4),
760         FIELD(HOST_FS_BASE, host_fs_base),
761         FIELD(HOST_GS_BASE, host_gs_base),
762         FIELD(HOST_TR_BASE, host_tr_base),
763         FIELD(HOST_GDTR_BASE, host_gdtr_base),
764         FIELD(HOST_IDTR_BASE, host_idtr_base),
765         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
766         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
767         FIELD(HOST_RSP, host_rsp),
768         FIELD(HOST_RIP, host_rip),
769 };
770
771 static inline short vmcs_field_to_offset(unsigned long field)
772 {
773         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
774
775         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
776             vmcs_field_to_offset_table[field] == 0)
777                 return -ENOENT;
778
779         return vmcs_field_to_offset_table[field];
780 }
781
782 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
783 {
784         return to_vmx(vcpu)->nested.current_vmcs12;
785 }
786
787 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
788 {
789         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
790         if (is_error_page(page))
791                 return NULL;
792
793         return page;
794 }
795
796 static void nested_release_page(struct page *page)
797 {
798         kvm_release_page_dirty(page);
799 }
800
801 static void nested_release_page_clean(struct page *page)
802 {
803         kvm_release_page_clean(page);
804 }
805
806 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
807 static u64 construct_eptp(unsigned long root_hpa);
808 static void kvm_cpu_vmxon(u64 addr);
809 static void kvm_cpu_vmxoff(void);
810 static bool vmx_mpx_supported(void);
811 static bool vmx_xsaves_supported(void);
812 static int vmx_vm_has_apicv(struct kvm *kvm);
813 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
814 static void vmx_set_segment(struct kvm_vcpu *vcpu,
815                             struct kvm_segment *var, int seg);
816 static void vmx_get_segment(struct kvm_vcpu *vcpu,
817                             struct kvm_segment *var, int seg);
818 static bool guest_state_valid(struct kvm_vcpu *vcpu);
819 static u32 vmx_segment_access_rights(struct kvm_segment *var);
820 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
821 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
822 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
823 static int alloc_identity_pagetable(struct kvm *kvm);
824
825 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
826 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
827 /*
828  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
829  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
830  */
831 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
832 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
833
834 static unsigned long *vmx_io_bitmap_a;
835 static unsigned long *vmx_io_bitmap_b;
836 static unsigned long *vmx_msr_bitmap_legacy;
837 static unsigned long *vmx_msr_bitmap_longmode;
838 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
839 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
840 static unsigned long *vmx_msr_bitmap_nested;
841 static unsigned long *vmx_vmread_bitmap;
842 static unsigned long *vmx_vmwrite_bitmap;
843
844 static bool cpu_has_load_ia32_efer;
845 static bool cpu_has_load_perf_global_ctrl;
846
847 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
848 static DEFINE_SPINLOCK(vmx_vpid_lock);
849
850 static struct vmcs_config {
851         int size;
852         int order;
853         u32 revision_id;
854         u32 pin_based_exec_ctrl;
855         u32 cpu_based_exec_ctrl;
856         u32 cpu_based_2nd_exec_ctrl;
857         u32 vmexit_ctrl;
858         u32 vmentry_ctrl;
859 } vmcs_config;
860
861 static struct vmx_capability {
862         u32 ept;
863         u32 vpid;
864 } vmx_capability;
865
866 #define VMX_SEGMENT_FIELD(seg)                                  \
867         [VCPU_SREG_##seg] = {                                   \
868                 .selector = GUEST_##seg##_SELECTOR,             \
869                 .base = GUEST_##seg##_BASE,                     \
870                 .limit = GUEST_##seg##_LIMIT,                   \
871                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
872         }
873
874 static const struct kvm_vmx_segment_field {
875         unsigned selector;
876         unsigned base;
877         unsigned limit;
878         unsigned ar_bytes;
879 } kvm_vmx_segment_fields[] = {
880         VMX_SEGMENT_FIELD(CS),
881         VMX_SEGMENT_FIELD(DS),
882         VMX_SEGMENT_FIELD(ES),
883         VMX_SEGMENT_FIELD(FS),
884         VMX_SEGMENT_FIELD(GS),
885         VMX_SEGMENT_FIELD(SS),
886         VMX_SEGMENT_FIELD(TR),
887         VMX_SEGMENT_FIELD(LDTR),
888 };
889
890 static u64 host_efer;
891
892 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
893
894 /*
895  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
896  * away by decrementing the array size.
897  */
898 static const u32 vmx_msr_index[] = {
899 #ifdef CONFIG_X86_64
900         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
901 #endif
902         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
903 };
904
905 static inline bool is_page_fault(u32 intr_info)
906 {
907         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
908                              INTR_INFO_VALID_MASK)) ==
909                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
910 }
911
912 static inline bool is_no_device(u32 intr_info)
913 {
914         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
915                              INTR_INFO_VALID_MASK)) ==
916                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
917 }
918
919 static inline bool is_invalid_opcode(u32 intr_info)
920 {
921         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
922                              INTR_INFO_VALID_MASK)) ==
923                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
924 }
925
926 static inline bool is_external_interrupt(u32 intr_info)
927 {
928         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
929                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
930 }
931
932 static inline bool is_machine_check(u32 intr_info)
933 {
934         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
935                              INTR_INFO_VALID_MASK)) ==
936                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
937 }
938
939 static inline bool cpu_has_vmx_msr_bitmap(void)
940 {
941         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
942 }
943
944 static inline bool cpu_has_vmx_tpr_shadow(void)
945 {
946         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
947 }
948
949 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
950 {
951         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
952 }
953
954 static inline bool cpu_has_secondary_exec_ctrls(void)
955 {
956         return vmcs_config.cpu_based_exec_ctrl &
957                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
958 }
959
960 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
961 {
962         return vmcs_config.cpu_based_2nd_exec_ctrl &
963                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
964 }
965
966 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
967 {
968         return vmcs_config.cpu_based_2nd_exec_ctrl &
969                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
970 }
971
972 static inline bool cpu_has_vmx_apic_register_virt(void)
973 {
974         return vmcs_config.cpu_based_2nd_exec_ctrl &
975                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
976 }
977
978 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
979 {
980         return vmcs_config.cpu_based_2nd_exec_ctrl &
981                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
982 }
983
984 static inline bool cpu_has_vmx_posted_intr(void)
985 {
986         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
987 }
988
989 static inline bool cpu_has_vmx_apicv(void)
990 {
991         return cpu_has_vmx_apic_register_virt() &&
992                 cpu_has_vmx_virtual_intr_delivery() &&
993                 cpu_has_vmx_posted_intr();
994 }
995
996 static inline bool cpu_has_vmx_flexpriority(void)
997 {
998         return cpu_has_vmx_tpr_shadow() &&
999                 cpu_has_vmx_virtualize_apic_accesses();
1000 }
1001
1002 static inline bool cpu_has_vmx_ept_execute_only(void)
1003 {
1004         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1005 }
1006
1007 static inline bool cpu_has_vmx_ept_2m_page(void)
1008 {
1009         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1010 }
1011
1012 static inline bool cpu_has_vmx_ept_1g_page(void)
1013 {
1014         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1015 }
1016
1017 static inline bool cpu_has_vmx_ept_4levels(void)
1018 {
1019         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1020 }
1021
1022 static inline bool cpu_has_vmx_ept_ad_bits(void)
1023 {
1024         return vmx_capability.ept & VMX_EPT_AD_BIT;
1025 }
1026
1027 static inline bool cpu_has_vmx_invept_context(void)
1028 {
1029         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1030 }
1031
1032 static inline bool cpu_has_vmx_invept_global(void)
1033 {
1034         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1035 }
1036
1037 static inline bool cpu_has_vmx_invvpid_single(void)
1038 {
1039         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1040 }
1041
1042 static inline bool cpu_has_vmx_invvpid_global(void)
1043 {
1044         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1045 }
1046
1047 static inline bool cpu_has_vmx_ept(void)
1048 {
1049         return vmcs_config.cpu_based_2nd_exec_ctrl &
1050                 SECONDARY_EXEC_ENABLE_EPT;
1051 }
1052
1053 static inline bool cpu_has_vmx_unrestricted_guest(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1057 }
1058
1059 static inline bool cpu_has_vmx_ple(void)
1060 {
1061         return vmcs_config.cpu_based_2nd_exec_ctrl &
1062                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1063 }
1064
1065 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1066 {
1067         return flexpriority_enabled && irqchip_in_kernel(kvm);
1068 }
1069
1070 static inline bool cpu_has_vmx_vpid(void)
1071 {
1072         return vmcs_config.cpu_based_2nd_exec_ctrl &
1073                 SECONDARY_EXEC_ENABLE_VPID;
1074 }
1075
1076 static inline bool cpu_has_vmx_rdtscp(void)
1077 {
1078         return vmcs_config.cpu_based_2nd_exec_ctrl &
1079                 SECONDARY_EXEC_RDTSCP;
1080 }
1081
1082 static inline bool cpu_has_vmx_invpcid(void)
1083 {
1084         return vmcs_config.cpu_based_2nd_exec_ctrl &
1085                 SECONDARY_EXEC_ENABLE_INVPCID;
1086 }
1087
1088 static inline bool cpu_has_virtual_nmis(void)
1089 {
1090         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1091 }
1092
1093 static inline bool cpu_has_vmx_wbinvd_exit(void)
1094 {
1095         return vmcs_config.cpu_based_2nd_exec_ctrl &
1096                 SECONDARY_EXEC_WBINVD_EXITING;
1097 }
1098
1099 static inline bool cpu_has_vmx_shadow_vmcs(void)
1100 {
1101         u64 vmx_msr;
1102         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103         /* check if the cpu supports writing r/o exit information fields */
1104         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1105                 return false;
1106
1107         return vmcs_config.cpu_based_2nd_exec_ctrl &
1108                 SECONDARY_EXEC_SHADOW_VMCS;
1109 }
1110
1111 static inline bool cpu_has_vmx_pml(void)
1112 {
1113         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1114 }
1115
1116 static inline bool report_flexpriority(void)
1117 {
1118         return flexpriority_enabled;
1119 }
1120
1121 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1122 {
1123         return vmcs12->cpu_based_vm_exec_control & bit;
1124 }
1125
1126 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1127 {
1128         return (vmcs12->cpu_based_vm_exec_control &
1129                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130                 (vmcs12->secondary_vm_exec_control & bit);
1131 }
1132
1133 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1134 {
1135         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1136 }
1137
1138 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1139 {
1140         return vmcs12->pin_based_vm_exec_control &
1141                 PIN_BASED_VMX_PREEMPTION_TIMER;
1142 }
1143
1144 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1145 {
1146         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1147 }
1148
1149 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1150 {
1151         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152                 vmx_xsaves_supported();
1153 }
1154
1155 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1156 {
1157         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1158 }
1159
1160 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1161 {
1162         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1163 }
1164
1165 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1166 {
1167         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1168 }
1169
1170 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1171 {
1172         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1173 }
1174
1175 static inline bool is_exception(u32 intr_info)
1176 {
1177         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1179 }
1180
1181 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1182                               u32 exit_intr_info,
1183                               unsigned long exit_qualification);
1184 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185                         struct vmcs12 *vmcs12,
1186                         u32 reason, unsigned long qualification);
1187
1188 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1189 {
1190         int i;
1191
1192         for (i = 0; i < vmx->nmsrs; ++i)
1193                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1194                         return i;
1195         return -1;
1196 }
1197
1198 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1199 {
1200     struct {
1201         u64 vpid : 16;
1202         u64 rsvd : 48;
1203         u64 gva;
1204     } operand = { vpid, 0, gva };
1205
1206     asm volatile (__ex(ASM_VMX_INVVPID)
1207                   /* CF==1 or ZF==1 --> rc = -1 */
1208                   "; ja 1f ; ud2 ; 1:"
1209                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1210 }
1211
1212 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1213 {
1214         struct {
1215                 u64 eptp, gpa;
1216         } operand = {eptp, gpa};
1217
1218         asm volatile (__ex(ASM_VMX_INVEPT)
1219                         /* CF==1 or ZF==1 --> rc = -1 */
1220                         "; ja 1f ; ud2 ; 1:\n"
1221                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1222 }
1223
1224 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1225 {
1226         int i;
1227
1228         i = __find_msr_index(vmx, msr);
1229         if (i >= 0)
1230                 return &vmx->guest_msrs[i];
1231         return NULL;
1232 }
1233
1234 static void vmcs_clear(struct vmcs *vmcs)
1235 {
1236         u64 phys_addr = __pa(vmcs);
1237         u8 error;
1238
1239         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1240                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1241                       : "cc", "memory");
1242         if (error)
1243                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1244                        vmcs, phys_addr);
1245 }
1246
1247 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1248 {
1249         vmcs_clear(loaded_vmcs->vmcs);
1250         loaded_vmcs->cpu = -1;
1251         loaded_vmcs->launched = 0;
1252 }
1253
1254 static void vmcs_load(struct vmcs *vmcs)
1255 {
1256         u64 phys_addr = __pa(vmcs);
1257         u8 error;
1258
1259         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1260                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1261                         : "cc", "memory");
1262         if (error)
1263                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1264                        vmcs, phys_addr);
1265 }
1266
1267 #ifdef CONFIG_KEXEC
1268 /*
1269  * This bitmap is used to indicate whether the vmclear
1270  * operation is enabled on all cpus. All disabled by
1271  * default.
1272  */
1273 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1274
1275 static inline void crash_enable_local_vmclear(int cpu)
1276 {
1277         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1278 }
1279
1280 static inline void crash_disable_local_vmclear(int cpu)
1281 {
1282         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1283 }
1284
1285 static inline int crash_local_vmclear_enabled(int cpu)
1286 {
1287         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1288 }
1289
1290 static void crash_vmclear_local_loaded_vmcss(void)
1291 {
1292         int cpu = raw_smp_processor_id();
1293         struct loaded_vmcs *v;
1294
1295         if (!crash_local_vmclear_enabled(cpu))
1296                 return;
1297
1298         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299                             loaded_vmcss_on_cpu_link)
1300                 vmcs_clear(v->vmcs);
1301 }
1302 #else
1303 static inline void crash_enable_local_vmclear(int cpu) { }
1304 static inline void crash_disable_local_vmclear(int cpu) { }
1305 #endif /* CONFIG_KEXEC */
1306
1307 static void __loaded_vmcs_clear(void *arg)
1308 {
1309         struct loaded_vmcs *loaded_vmcs = arg;
1310         int cpu = raw_smp_processor_id();
1311
1312         if (loaded_vmcs->cpu != cpu)
1313                 return; /* vcpu migration can race with cpu offline */
1314         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1315                 per_cpu(current_vmcs, cpu) = NULL;
1316         crash_disable_local_vmclear(cpu);
1317         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1318
1319         /*
1320          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321          * is before setting loaded_vmcs->vcpu to -1 which is done in
1322          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323          * then adds the vmcs into percpu list before it is deleted.
1324          */
1325         smp_wmb();
1326
1327         loaded_vmcs_init(loaded_vmcs);
1328         crash_enable_local_vmclear(cpu);
1329 }
1330
1331 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1332 {
1333         int cpu = loaded_vmcs->cpu;
1334
1335         if (cpu != -1)
1336                 smp_call_function_single(cpu,
1337                          __loaded_vmcs_clear, loaded_vmcs, 1);
1338 }
1339
1340 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1341 {
1342         if (vmx->vpid == 0)
1343                 return;
1344
1345         if (cpu_has_vmx_invvpid_single())
1346                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1347 }
1348
1349 static inline void vpid_sync_vcpu_global(void)
1350 {
1351         if (cpu_has_vmx_invvpid_global())
1352                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1353 }
1354
1355 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1356 {
1357         if (cpu_has_vmx_invvpid_single())
1358                 vpid_sync_vcpu_single(vmx);
1359         else
1360                 vpid_sync_vcpu_global();
1361 }
1362
1363 static inline void ept_sync_global(void)
1364 {
1365         if (cpu_has_vmx_invept_global())
1366                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1367 }
1368
1369 static inline void ept_sync_context(u64 eptp)
1370 {
1371         if (enable_ept) {
1372                 if (cpu_has_vmx_invept_context())
1373                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1374                 else
1375                         ept_sync_global();
1376         }
1377 }
1378
1379 static __always_inline unsigned long vmcs_readl(unsigned long field)
1380 {
1381         unsigned long value;
1382
1383         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384                       : "=a"(value) : "d"(field) : "cc");
1385         return value;
1386 }
1387
1388 static __always_inline u16 vmcs_read16(unsigned long field)
1389 {
1390         return vmcs_readl(field);
1391 }
1392
1393 static __always_inline u32 vmcs_read32(unsigned long field)
1394 {
1395         return vmcs_readl(field);
1396 }
1397
1398 static __always_inline u64 vmcs_read64(unsigned long field)
1399 {
1400 #ifdef CONFIG_X86_64
1401         return vmcs_readl(field);
1402 #else
1403         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1404 #endif
1405 }
1406
1407 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1408 {
1409         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1411         dump_stack();
1412 }
1413
1414 static void vmcs_writel(unsigned long field, unsigned long value)
1415 {
1416         u8 error;
1417
1418         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1419                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1420         if (unlikely(error))
1421                 vmwrite_error(field, value);
1422 }
1423
1424 static void vmcs_write16(unsigned long field, u16 value)
1425 {
1426         vmcs_writel(field, value);
1427 }
1428
1429 static void vmcs_write32(unsigned long field, u32 value)
1430 {
1431         vmcs_writel(field, value);
1432 }
1433
1434 static void vmcs_write64(unsigned long field, u64 value)
1435 {
1436         vmcs_writel(field, value);
1437 #ifndef CONFIG_X86_64
1438         asm volatile ("");
1439         vmcs_writel(field+1, value >> 32);
1440 #endif
1441 }
1442
1443 static void vmcs_clear_bits(unsigned long field, u32 mask)
1444 {
1445         vmcs_writel(field, vmcs_readl(field) & ~mask);
1446 }
1447
1448 static void vmcs_set_bits(unsigned long field, u32 mask)
1449 {
1450         vmcs_writel(field, vmcs_readl(field) | mask);
1451 }
1452
1453 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1454 {
1455         vmcs_write32(VM_ENTRY_CONTROLS, val);
1456         vmx->vm_entry_controls_shadow = val;
1457 }
1458
1459 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1460 {
1461         if (vmx->vm_entry_controls_shadow != val)
1462                 vm_entry_controls_init(vmx, val);
1463 }
1464
1465 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1466 {
1467         return vmx->vm_entry_controls_shadow;
1468 }
1469
1470
1471 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1472 {
1473         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1474 }
1475
1476 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1477 {
1478         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1479 }
1480
1481 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1482 {
1483         vmcs_write32(VM_EXIT_CONTROLS, val);
1484         vmx->vm_exit_controls_shadow = val;
1485 }
1486
1487 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1488 {
1489         if (vmx->vm_exit_controls_shadow != val)
1490                 vm_exit_controls_init(vmx, val);
1491 }
1492
1493 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1494 {
1495         return vmx->vm_exit_controls_shadow;
1496 }
1497
1498
1499 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1500 {
1501         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1502 }
1503
1504 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1505 {
1506         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1507 }
1508
1509 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1510 {
1511         vmx->segment_cache.bitmask = 0;
1512 }
1513
1514 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1515                                        unsigned field)
1516 {
1517         bool ret;
1518         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1519
1520         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522                 vmx->segment_cache.bitmask = 0;
1523         }
1524         ret = vmx->segment_cache.bitmask & mask;
1525         vmx->segment_cache.bitmask |= mask;
1526         return ret;
1527 }
1528
1529 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1530 {
1531         u16 *p = &vmx->segment_cache.seg[seg].selector;
1532
1533         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1535         return *p;
1536 }
1537
1538 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1539 {
1540         ulong *p = &vmx->segment_cache.seg[seg].base;
1541
1542         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1544         return *p;
1545 }
1546
1547 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1548 {
1549         u32 *p = &vmx->segment_cache.seg[seg].limit;
1550
1551         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1553         return *p;
1554 }
1555
1556 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1557 {
1558         u32 *p = &vmx->segment_cache.seg[seg].ar;
1559
1560         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1562         return *p;
1563 }
1564
1565 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1566 {
1567         u32 eb;
1568
1569         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571         if ((vcpu->guest_debug &
1572              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574                 eb |= 1u << BP_VECTOR;
1575         if (to_vmx(vcpu)->rmode.vm86_active)
1576                 eb = ~0;
1577         if (enable_ept)
1578                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1579         if (vcpu->fpu_active)
1580                 eb &= ~(1u << NM_VECTOR);
1581
1582         /* When we are running a nested L2 guest and L1 specified for it a
1583          * certain exception bitmap, we must trap the same exceptions and pass
1584          * them to L1. When running L2, we will only handle the exceptions
1585          * specified above if L1 did not want them.
1586          */
1587         if (is_guest_mode(vcpu))
1588                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1589
1590         vmcs_write32(EXCEPTION_BITMAP, eb);
1591 }
1592
1593 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594                 unsigned long entry, unsigned long exit)
1595 {
1596         vm_entry_controls_clearbit(vmx, entry);
1597         vm_exit_controls_clearbit(vmx, exit);
1598 }
1599
1600 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1601 {
1602         unsigned i;
1603         struct msr_autoload *m = &vmx->msr_autoload;
1604
1605         switch (msr) {
1606         case MSR_EFER:
1607                 if (cpu_has_load_ia32_efer) {
1608                         clear_atomic_switch_msr_special(vmx,
1609                                         VM_ENTRY_LOAD_IA32_EFER,
1610                                         VM_EXIT_LOAD_IA32_EFER);
1611                         return;
1612                 }
1613                 break;
1614         case MSR_CORE_PERF_GLOBAL_CTRL:
1615                 if (cpu_has_load_perf_global_ctrl) {
1616                         clear_atomic_switch_msr_special(vmx,
1617                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1619                         return;
1620                 }
1621                 break;
1622         }
1623
1624         for (i = 0; i < m->nr; ++i)
1625                 if (m->guest[i].index == msr)
1626                         break;
1627
1628         if (i == m->nr)
1629                 return;
1630         --m->nr;
1631         m->guest[i] = m->guest[m->nr];
1632         m->host[i] = m->host[m->nr];
1633         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1635 }
1636
1637 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638                 unsigned long entry, unsigned long exit,
1639                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640                 u64 guest_val, u64 host_val)
1641 {
1642         vmcs_write64(guest_val_vmcs, guest_val);
1643         vmcs_write64(host_val_vmcs, host_val);
1644         vm_entry_controls_setbit(vmx, entry);
1645         vm_exit_controls_setbit(vmx, exit);
1646 }
1647
1648 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649                                   u64 guest_val, u64 host_val)
1650 {
1651         unsigned i;
1652         struct msr_autoload *m = &vmx->msr_autoload;
1653
1654         switch (msr) {
1655         case MSR_EFER:
1656                 if (cpu_has_load_ia32_efer) {
1657                         add_atomic_switch_msr_special(vmx,
1658                                         VM_ENTRY_LOAD_IA32_EFER,
1659                                         VM_EXIT_LOAD_IA32_EFER,
1660                                         GUEST_IA32_EFER,
1661                                         HOST_IA32_EFER,
1662                                         guest_val, host_val);
1663                         return;
1664                 }
1665                 break;
1666         case MSR_CORE_PERF_GLOBAL_CTRL:
1667                 if (cpu_has_load_perf_global_ctrl) {
1668                         add_atomic_switch_msr_special(vmx,
1669                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1672                                         HOST_IA32_PERF_GLOBAL_CTRL,
1673                                         guest_val, host_val);
1674                         return;
1675                 }
1676                 break;
1677         }
1678
1679         for (i = 0; i < m->nr; ++i)
1680                 if (m->guest[i].index == msr)
1681                         break;
1682
1683         if (i == NR_AUTOLOAD_MSRS) {
1684                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1685                                 "Can't add msr %x\n", msr);
1686                 return;
1687         } else if (i == m->nr) {
1688                 ++m->nr;
1689                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1691         }
1692
1693         m->guest[i].index = msr;
1694         m->guest[i].value = guest_val;
1695         m->host[i].index = msr;
1696         m->host[i].value = host_val;
1697 }
1698
1699 static void reload_tss(void)
1700 {
1701         /*
1702          * VT restores TR but not its size.  Useless.
1703          */
1704         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1705         struct desc_struct *descs;
1706
1707         descs = (void *)gdt->address;
1708         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1709         load_TR_desc();
1710 }
1711
1712 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1713 {
1714         u64 guest_efer;
1715         u64 ignore_bits;
1716
1717         guest_efer = vmx->vcpu.arch.efer;
1718
1719         /*
1720          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1721          * outside long mode
1722          */
1723         ignore_bits = EFER_NX | EFER_SCE;
1724 #ifdef CONFIG_X86_64
1725         ignore_bits |= EFER_LMA | EFER_LME;
1726         /* SCE is meaningful only in long mode on Intel */
1727         if (guest_efer & EFER_LMA)
1728                 ignore_bits &= ~(u64)EFER_SCE;
1729 #endif
1730         guest_efer &= ~ignore_bits;
1731         guest_efer |= host_efer & ignore_bits;
1732         vmx->guest_msrs[efer_offset].data = guest_efer;
1733         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1734
1735         clear_atomic_switch_msr(vmx, MSR_EFER);
1736
1737         /*
1738          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739          * On CPUs that support "load IA32_EFER", always switch EFER
1740          * atomically, since it's faster than switching it manually.
1741          */
1742         if (cpu_has_load_ia32_efer ||
1743             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1744                 guest_efer = vmx->vcpu.arch.efer;
1745                 if (!(guest_efer & EFER_LMA))
1746                         guest_efer &= ~EFER_LME;
1747                 if (guest_efer != host_efer)
1748                         add_atomic_switch_msr(vmx, MSR_EFER,
1749                                               guest_efer, host_efer);
1750                 return false;
1751         }
1752
1753         return true;
1754 }
1755
1756 static unsigned long segment_base(u16 selector)
1757 {
1758         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1759         struct desc_struct *d;
1760         unsigned long table_base;
1761         unsigned long v;
1762
1763         if (!(selector & ~3))
1764                 return 0;
1765
1766         table_base = gdt->address;
1767
1768         if (selector & 4) {           /* from ldt */
1769                 u16 ldt_selector = kvm_read_ldt();
1770
1771                 if (!(ldt_selector & ~3))
1772                         return 0;
1773
1774                 table_base = segment_base(ldt_selector);
1775         }
1776         d = (struct desc_struct *)(table_base + (selector & ~7));
1777         v = get_desc_base(d);
1778 #ifdef CONFIG_X86_64
1779        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1781 #endif
1782         return v;
1783 }
1784
1785 static inline unsigned long kvm_read_tr_base(void)
1786 {
1787         u16 tr;
1788         asm("str %0" : "=g"(tr));
1789         return segment_base(tr);
1790 }
1791
1792 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1793 {
1794         struct vcpu_vmx *vmx = to_vmx(vcpu);
1795         int i;
1796
1797         if (vmx->host_state.loaded)
1798                 return;
1799
1800         vmx->host_state.loaded = 1;
1801         /*
1802          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1803          * allow segment selectors with cpl > 0 or ti == 1.
1804          */
1805         vmx->host_state.ldt_sel = kvm_read_ldt();
1806         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1807         savesegment(fs, vmx->host_state.fs_sel);
1808         if (!(vmx->host_state.fs_sel & 7)) {
1809                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1810                 vmx->host_state.fs_reload_needed = 0;
1811         } else {
1812                 vmcs_write16(HOST_FS_SELECTOR, 0);
1813                 vmx->host_state.fs_reload_needed = 1;
1814         }
1815         savesegment(gs, vmx->host_state.gs_sel);
1816         if (!(vmx->host_state.gs_sel & 7))
1817                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1818         else {
1819                 vmcs_write16(HOST_GS_SELECTOR, 0);
1820                 vmx->host_state.gs_ldt_reload_needed = 1;
1821         }
1822
1823 #ifdef CONFIG_X86_64
1824         savesegment(ds, vmx->host_state.ds_sel);
1825         savesegment(es, vmx->host_state.es_sel);
1826 #endif
1827
1828 #ifdef CONFIG_X86_64
1829         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1831 #else
1832         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1834 #endif
1835
1836 #ifdef CONFIG_X86_64
1837         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838         if (is_long_mode(&vmx->vcpu))
1839                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1840 #endif
1841         if (boot_cpu_has(X86_FEATURE_MPX))
1842                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1843         for (i = 0; i < vmx->save_nmsrs; ++i)
1844                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1845                                    vmx->guest_msrs[i].data,
1846                                    vmx->guest_msrs[i].mask);
1847 }
1848
1849 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1850 {
1851         if (!vmx->host_state.loaded)
1852                 return;
1853
1854         ++vmx->vcpu.stat.host_state_reload;
1855         vmx->host_state.loaded = 0;
1856 #ifdef CONFIG_X86_64
1857         if (is_long_mode(&vmx->vcpu))
1858                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1859 #endif
1860         if (vmx->host_state.gs_ldt_reload_needed) {
1861                 kvm_load_ldt(vmx->host_state.ldt_sel);
1862 #ifdef CONFIG_X86_64
1863                 load_gs_index(vmx->host_state.gs_sel);
1864 #else
1865                 loadsegment(gs, vmx->host_state.gs_sel);
1866 #endif
1867         }
1868         if (vmx->host_state.fs_reload_needed)
1869                 loadsegment(fs, vmx->host_state.fs_sel);
1870 #ifdef CONFIG_X86_64
1871         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872                 loadsegment(ds, vmx->host_state.ds_sel);
1873                 loadsegment(es, vmx->host_state.es_sel);
1874         }
1875 #endif
1876         reload_tss();
1877 #ifdef CONFIG_X86_64
1878         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1879 #endif
1880         if (vmx->host_state.msr_host_bndcfgs)
1881                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1882         /*
1883          * If the FPU is not active (through the host task or
1884          * the guest vcpu), then restore the cr0.TS bit.
1885          */
1886         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1887                 stts();
1888         load_gdt(this_cpu_ptr(&host_gdt));
1889 }
1890
1891 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1892 {
1893         preempt_disable();
1894         __vmx_load_host_state(vmx);
1895         preempt_enable();
1896 }
1897
1898 /*
1899  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900  * vcpu mutex is already taken.
1901  */
1902 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1903 {
1904         struct vcpu_vmx *vmx = to_vmx(vcpu);
1905         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1906
1907         if (!vmm_exclusive)
1908                 kvm_cpu_vmxon(phys_addr);
1909         else if (vmx->loaded_vmcs->cpu != cpu)
1910                 loaded_vmcs_clear(vmx->loaded_vmcs);
1911
1912         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914                 vmcs_load(vmx->loaded_vmcs->vmcs);
1915         }
1916
1917         if (vmx->loaded_vmcs->cpu != cpu) {
1918                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1919                 unsigned long sysenter_esp;
1920
1921                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1922                 local_irq_disable();
1923                 crash_disable_local_vmclear(cpu);
1924
1925                 /*
1926                  * Read loaded_vmcs->cpu should be before fetching
1927                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928                  * See the comments in __loaded_vmcs_clear().
1929                  */
1930                 smp_rmb();
1931
1932                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1934                 crash_enable_local_vmclear(cpu);
1935                 local_irq_enable();
1936
1937                 /*
1938                  * Linux uses per-cpu TSS and GDT, so set these when switching
1939                  * processors.
1940                  */
1941                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1942                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1943
1944                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1946                 vmx->loaded_vmcs->cpu = cpu;
1947         }
1948 }
1949
1950 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1951 {
1952         __vmx_load_host_state(to_vmx(vcpu));
1953         if (!vmm_exclusive) {
1954                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1955                 vcpu->cpu = -1;
1956                 kvm_cpu_vmxoff();
1957         }
1958 }
1959
1960 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1961 {
1962         ulong cr0;
1963
1964         if (vcpu->fpu_active)
1965                 return;
1966         vcpu->fpu_active = 1;
1967         cr0 = vmcs_readl(GUEST_CR0);
1968         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970         vmcs_writel(GUEST_CR0, cr0);
1971         update_exception_bitmap(vcpu);
1972         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1973         if (is_guest_mode(vcpu))
1974                 vcpu->arch.cr0_guest_owned_bits &=
1975                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1976         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1977 }
1978
1979 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1980
1981 /*
1982  * Return the cr0 value that a nested guest would read. This is a combination
1983  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984  * its hypervisor (cr0_read_shadow).
1985  */
1986 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1987 {
1988         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1990 }
1991 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1992 {
1993         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1995 }
1996
1997 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1998 {
1999         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000          * set this *before* calling this function.
2001          */
2002         vmx_decache_cr0_guest_bits(vcpu);
2003         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2004         update_exception_bitmap(vcpu);
2005         vcpu->arch.cr0_guest_owned_bits = 0;
2006         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2007         if (is_guest_mode(vcpu)) {
2008                 /*
2009                  * L1's specified read shadow might not contain the TS bit,
2010                  * so now that we turned on shadowing of this bit, we need to
2011                  * set this bit of the shadow. Like in nested_vmx_run we need
2012                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013                  * up-to-date here because we just decached cr0.TS (and we'll
2014                  * only update vmcs12->guest_cr0 on nested exit).
2015                  */
2016                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018                         (vcpu->arch.cr0 & X86_CR0_TS);
2019                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2020         } else
2021                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2022 }
2023
2024 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2025 {
2026         unsigned long rflags, save_rflags;
2027
2028         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030                 rflags = vmcs_readl(GUEST_RFLAGS);
2031                 if (to_vmx(vcpu)->rmode.vm86_active) {
2032                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2035                 }
2036                 to_vmx(vcpu)->rflags = rflags;
2037         }
2038         return to_vmx(vcpu)->rflags;
2039 }
2040
2041 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2042 {
2043         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044         to_vmx(vcpu)->rflags = rflags;
2045         if (to_vmx(vcpu)->rmode.vm86_active) {
2046                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2047                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2048         }
2049         vmcs_writel(GUEST_RFLAGS, rflags);
2050 }
2051
2052 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2053 {
2054         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2055         int ret = 0;
2056
2057         if (interruptibility & GUEST_INTR_STATE_STI)
2058                 ret |= KVM_X86_SHADOW_INT_STI;
2059         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2060                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2061
2062         return ret;
2063 }
2064
2065 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2066 {
2067         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068         u32 interruptibility = interruptibility_old;
2069
2070         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2071
2072         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2073                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2074         else if (mask & KVM_X86_SHADOW_INT_STI)
2075                 interruptibility |= GUEST_INTR_STATE_STI;
2076
2077         if ((interruptibility != interruptibility_old))
2078                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2079 }
2080
2081 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2082 {
2083         unsigned long rip;
2084
2085         rip = kvm_rip_read(vcpu);
2086         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2087         kvm_rip_write(vcpu, rip);
2088
2089         /* skipping an emulated instruction also counts */
2090         vmx_set_interrupt_shadow(vcpu, 0);
2091 }
2092
2093 /*
2094  * KVM wants to inject page-faults which it got to the guest. This function
2095  * checks whether in a nested guest, we need to inject them to L1 or L2.
2096  */
2097 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2098 {
2099         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100
2101         if (!(vmcs12->exception_bitmap & (1u << nr)))
2102                 return 0;
2103
2104         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105                           vmcs_read32(VM_EXIT_INTR_INFO),
2106                           vmcs_readl(EXIT_QUALIFICATION));
2107         return 1;
2108 }
2109
2110 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2111                                 bool has_error_code, u32 error_code,
2112                                 bool reinject)
2113 {
2114         struct vcpu_vmx *vmx = to_vmx(vcpu);
2115         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2116
2117         if (!reinject && is_guest_mode(vcpu) &&
2118             nested_vmx_check_exception(vcpu, nr))
2119                 return;
2120
2121         if (has_error_code) {
2122                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2123                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2124         }
2125
2126         if (vmx->rmode.vm86_active) {
2127                 int inc_eip = 0;
2128                 if (kvm_exception_is_soft(nr))
2129                         inc_eip = vcpu->arch.event_exit_inst_len;
2130                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2131                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2132                 return;
2133         }
2134
2135         if (kvm_exception_is_soft(nr)) {
2136                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137                              vmx->vcpu.arch.event_exit_inst_len);
2138                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2139         } else
2140                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2141
2142         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2143 }
2144
2145 static bool vmx_rdtscp_supported(void)
2146 {
2147         return cpu_has_vmx_rdtscp();
2148 }
2149
2150 static bool vmx_invpcid_supported(void)
2151 {
2152         return cpu_has_vmx_invpcid() && enable_ept;
2153 }
2154
2155 /*
2156  * Swap MSR entry in host/guest MSR entry array.
2157  */
2158 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2159 {
2160         struct shared_msr_entry tmp;
2161
2162         tmp = vmx->guest_msrs[to];
2163         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164         vmx->guest_msrs[from] = tmp;
2165 }
2166
2167 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2168 {
2169         unsigned long *msr_bitmap;
2170
2171         if (is_guest_mode(vcpu))
2172                 msr_bitmap = vmx_msr_bitmap_nested;
2173         else if (irqchip_in_kernel(vcpu->kvm) &&
2174                 apic_x2apic_mode(vcpu->arch.apic)) {
2175                 if (is_long_mode(vcpu))
2176                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2177                 else
2178                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2179         } else {
2180                 if (is_long_mode(vcpu))
2181                         msr_bitmap = vmx_msr_bitmap_longmode;
2182                 else
2183                         msr_bitmap = vmx_msr_bitmap_legacy;
2184         }
2185
2186         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2187 }
2188
2189 /*
2190  * Set up the vmcs to automatically save and restore system
2191  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2192  * mode, as fiddling with msrs is very expensive.
2193  */
2194 static void setup_msrs(struct vcpu_vmx *vmx)
2195 {
2196         int save_nmsrs, index;
2197
2198         save_nmsrs = 0;
2199 #ifdef CONFIG_X86_64
2200         if (is_long_mode(&vmx->vcpu)) {
2201                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2202                 if (index >= 0)
2203                         move_msr_up(vmx, index, save_nmsrs++);
2204                 index = __find_msr_index(vmx, MSR_LSTAR);
2205                 if (index >= 0)
2206                         move_msr_up(vmx, index, save_nmsrs++);
2207                 index = __find_msr_index(vmx, MSR_CSTAR);
2208                 if (index >= 0)
2209                         move_msr_up(vmx, index, save_nmsrs++);
2210                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2211                 if (index >= 0 && vmx->rdtscp_enabled)
2212                         move_msr_up(vmx, index, save_nmsrs++);
2213                 /*
2214                  * MSR_STAR is only needed on long mode guests, and only
2215                  * if efer.sce is enabled.
2216                  */
2217                 index = __find_msr_index(vmx, MSR_STAR);
2218                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2219                         move_msr_up(vmx, index, save_nmsrs++);
2220         }
2221 #endif
2222         index = __find_msr_index(vmx, MSR_EFER);
2223         if (index >= 0 && update_transition_efer(vmx, index))
2224                 move_msr_up(vmx, index, save_nmsrs++);
2225
2226         vmx->save_nmsrs = save_nmsrs;
2227
2228         if (cpu_has_vmx_msr_bitmap())
2229                 vmx_set_msr_bitmap(&vmx->vcpu);
2230 }
2231
2232 /*
2233  * reads and returns guest's timestamp counter "register"
2234  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2235  */
2236 static u64 guest_read_tsc(void)
2237 {
2238         u64 host_tsc, tsc_offset;
2239
2240         rdtscll(host_tsc);
2241         tsc_offset = vmcs_read64(TSC_OFFSET);
2242         return host_tsc + tsc_offset;
2243 }
2244
2245 /*
2246  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2247  * counter, even if a nested guest (L2) is currently running.
2248  */
2249 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2250 {
2251         u64 tsc_offset;
2252
2253         tsc_offset = is_guest_mode(vcpu) ?
2254                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2255                 vmcs_read64(TSC_OFFSET);
2256         return host_tsc + tsc_offset;
2257 }
2258
2259 /*
2260  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2261  * software catchup for faster rates on slower CPUs.
2262  */
2263 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2264 {
2265         if (!scale)
2266                 return;
2267
2268         if (user_tsc_khz > tsc_khz) {
2269                 vcpu->arch.tsc_catchup = 1;
2270                 vcpu->arch.tsc_always_catchup = 1;
2271         } else
2272                 WARN(1, "user requested TSC rate below hardware speed\n");
2273 }
2274
2275 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2276 {
2277         return vmcs_read64(TSC_OFFSET);
2278 }
2279
2280 /*
2281  * writes 'offset' into guest's timestamp counter offset register
2282  */
2283 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2284 {
2285         if (is_guest_mode(vcpu)) {
2286                 /*
2287                  * We're here if L1 chose not to trap WRMSR to TSC. According
2288                  * to the spec, this should set L1's TSC; The offset that L1
2289                  * set for L2 remains unchanged, and still needs to be added
2290                  * to the newly set TSC to get L2's TSC.
2291                  */
2292                 struct vmcs12 *vmcs12;
2293                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2294                 /* recalculate vmcs02.TSC_OFFSET: */
2295                 vmcs12 = get_vmcs12(vcpu);
2296                 vmcs_write64(TSC_OFFSET, offset +
2297                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2298                          vmcs12->tsc_offset : 0));
2299         } else {
2300                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2301                                            vmcs_read64(TSC_OFFSET), offset);
2302                 vmcs_write64(TSC_OFFSET, offset);
2303         }
2304 }
2305
2306 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2307 {
2308         u64 offset = vmcs_read64(TSC_OFFSET);
2309
2310         vmcs_write64(TSC_OFFSET, offset + adjustment);
2311         if (is_guest_mode(vcpu)) {
2312                 /* Even when running L2, the adjustment needs to apply to L1 */
2313                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2314         } else
2315                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2316                                            offset + adjustment);
2317 }
2318
2319 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2320 {
2321         return target_tsc - native_read_tsc();
2322 }
2323
2324 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2325 {
2326         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2327         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2328 }
2329
2330 /*
2331  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2332  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2333  * all guests if the "nested" module option is off, and can also be disabled
2334  * for a single guest by disabling its VMX cpuid bit.
2335  */
2336 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2337 {
2338         return nested && guest_cpuid_has_vmx(vcpu);
2339 }
2340
2341 /*
2342  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2343  * returned for the various VMX controls MSRs when nested VMX is enabled.
2344  * The same values should also be used to verify that vmcs12 control fields are
2345  * valid during nested entry from L1 to L2.
2346  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2347  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2348  * bit in the high half is on if the corresponding bit in the control field
2349  * may be on. See also vmx_control_verify().
2350  */
2351 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2352 {
2353         /*
2354          * Note that as a general rule, the high half of the MSRs (bits in
2355          * the control fields which may be 1) should be initialized by the
2356          * intersection of the underlying hardware's MSR (i.e., features which
2357          * can be supported) and the list of features we want to expose -
2358          * because they are known to be properly supported in our code.
2359          * Also, usually, the low half of the MSRs (bits which must be 1) can
2360          * be set to 0, meaning that L1 may turn off any of these bits. The
2361          * reason is that if one of these bits is necessary, it will appear
2362          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2363          * fields of vmcs01 and vmcs02, will turn these bits off - and
2364          * nested_vmx_exit_handled() will not pass related exits to L1.
2365          * These rules have exceptions below.
2366          */
2367
2368         /* pin-based controls */
2369         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2370                 vmx->nested.nested_vmx_pinbased_ctls_low,
2371                 vmx->nested.nested_vmx_pinbased_ctls_high);
2372         vmx->nested.nested_vmx_pinbased_ctls_low |=
2373                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2374         vmx->nested.nested_vmx_pinbased_ctls_high &=
2375                 PIN_BASED_EXT_INTR_MASK |
2376                 PIN_BASED_NMI_EXITING |
2377                 PIN_BASED_VIRTUAL_NMIS;
2378         vmx->nested.nested_vmx_pinbased_ctls_high |=
2379                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2380                 PIN_BASED_VMX_PREEMPTION_TIMER;
2381         if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2382                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2383                         PIN_BASED_POSTED_INTR;
2384
2385         /* exit controls */
2386         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2387                 vmx->nested.nested_vmx_exit_ctls_low,
2388                 vmx->nested.nested_vmx_exit_ctls_high);
2389         vmx->nested.nested_vmx_exit_ctls_low =
2390                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2391
2392         vmx->nested.nested_vmx_exit_ctls_high &=
2393 #ifdef CONFIG_X86_64
2394                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2395 #endif
2396                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2397         vmx->nested.nested_vmx_exit_ctls_high |=
2398                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2399                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2400                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2401
2402         if (vmx_mpx_supported())
2403                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2404
2405         /* We support free control of debug control saving. */
2406         vmx->nested.nested_vmx_true_exit_ctls_low =
2407                 vmx->nested.nested_vmx_exit_ctls_low &
2408                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2409
2410         /* entry controls */
2411         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2412                 vmx->nested.nested_vmx_entry_ctls_low,
2413                 vmx->nested.nested_vmx_entry_ctls_high);
2414         vmx->nested.nested_vmx_entry_ctls_low =
2415                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2416         vmx->nested.nested_vmx_entry_ctls_high &=
2417 #ifdef CONFIG_X86_64
2418                 VM_ENTRY_IA32E_MODE |
2419 #endif
2420                 VM_ENTRY_LOAD_IA32_PAT;
2421         vmx->nested.nested_vmx_entry_ctls_high |=
2422                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2423         if (vmx_mpx_supported())
2424                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2425
2426         /* We support free control of debug control loading. */
2427         vmx->nested.nested_vmx_true_entry_ctls_low =
2428                 vmx->nested.nested_vmx_entry_ctls_low &
2429                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2430
2431         /* cpu-based controls */
2432         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2433                 vmx->nested.nested_vmx_procbased_ctls_low,
2434                 vmx->nested.nested_vmx_procbased_ctls_high);
2435         vmx->nested.nested_vmx_procbased_ctls_low =
2436                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2437         vmx->nested.nested_vmx_procbased_ctls_high &=
2438                 CPU_BASED_VIRTUAL_INTR_PENDING |
2439                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2440                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2441                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2442                 CPU_BASED_CR3_STORE_EXITING |
2443 #ifdef CONFIG_X86_64
2444                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2445 #endif
2446                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2447                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2448                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2449                 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
2450                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2451         /*
2452          * We can allow some features even when not supported by the
2453          * hardware. For example, L1 can specify an MSR bitmap - and we
2454          * can use it to avoid exits to L1 - even when L0 runs L2
2455          * without MSR bitmaps.
2456          */
2457         vmx->nested.nested_vmx_procbased_ctls_high |=
2458                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2459                 CPU_BASED_USE_MSR_BITMAPS;
2460
2461         /* We support free control of CR3 access interception. */
2462         vmx->nested.nested_vmx_true_procbased_ctls_low =
2463                 vmx->nested.nested_vmx_procbased_ctls_low &
2464                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2465
2466         /* secondary cpu-based controls */
2467         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2468                 vmx->nested.nested_vmx_secondary_ctls_low,
2469                 vmx->nested.nested_vmx_secondary_ctls_high);
2470         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2471         vmx->nested.nested_vmx_secondary_ctls_high &=
2472                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2473                 SECONDARY_EXEC_RDTSCP |
2474                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2475                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2476                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2477                 SECONDARY_EXEC_WBINVD_EXITING |
2478                 SECONDARY_EXEC_XSAVES;
2479
2480         if (enable_ept) {
2481                 /* nested EPT: emulate EPT also to L1 */
2482                 vmx->nested.nested_vmx_secondary_ctls_high |=
2483                         SECONDARY_EXEC_ENABLE_EPT;
2484                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2485                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2486                          VMX_EPT_INVEPT_BIT;
2487                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2488                 /*
2489                  * For nested guests, we don't do anything specific
2490                  * for single context invalidation. Hence, only advertise
2491                  * support for global context invalidation.
2492                  */
2493                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2494         } else
2495                 vmx->nested.nested_vmx_ept_caps = 0;
2496
2497         if (enable_unrestricted_guest)
2498                 vmx->nested.nested_vmx_secondary_ctls_high |=
2499                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2500
2501         /* miscellaneous data */
2502         rdmsr(MSR_IA32_VMX_MISC,
2503                 vmx->nested.nested_vmx_misc_low,
2504                 vmx->nested.nested_vmx_misc_high);
2505         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2506         vmx->nested.nested_vmx_misc_low |=
2507                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2508                 VMX_MISC_ACTIVITY_HLT;
2509         vmx->nested.nested_vmx_misc_high = 0;
2510 }
2511
2512 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2513 {
2514         /*
2515          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2516          */
2517         return ((control & high) | low) == control;
2518 }
2519
2520 static inline u64 vmx_control_msr(u32 low, u32 high)
2521 {
2522         return low | ((u64)high << 32);
2523 }
2524
2525 /* Returns 0 on success, non-0 otherwise. */
2526 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2527 {
2528         struct vcpu_vmx *vmx = to_vmx(vcpu);
2529
2530         switch (msr_index) {
2531         case MSR_IA32_VMX_BASIC:
2532                 /*
2533                  * This MSR reports some information about VMX support. We
2534                  * should return information about the VMX we emulate for the
2535                  * guest, and the VMCS structure we give it - not about the
2536                  * VMX support of the underlying hardware.
2537                  */
2538                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2539                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2540                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2541                 break;
2542         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2543         case MSR_IA32_VMX_PINBASED_CTLS:
2544                 *pdata = vmx_control_msr(
2545                         vmx->nested.nested_vmx_pinbased_ctls_low,
2546                         vmx->nested.nested_vmx_pinbased_ctls_high);
2547                 break;
2548         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2549                 *pdata = vmx_control_msr(
2550                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2551                         vmx->nested.nested_vmx_procbased_ctls_high);
2552                 break;
2553         case MSR_IA32_VMX_PROCBASED_CTLS:
2554                 *pdata = vmx_control_msr(
2555                         vmx->nested.nested_vmx_procbased_ctls_low,
2556                         vmx->nested.nested_vmx_procbased_ctls_high);
2557                 break;
2558         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2559                 *pdata = vmx_control_msr(
2560                         vmx->nested.nested_vmx_true_exit_ctls_low,
2561                         vmx->nested.nested_vmx_exit_ctls_high);
2562                 break;
2563         case MSR_IA32_VMX_EXIT_CTLS:
2564                 *pdata = vmx_control_msr(
2565                         vmx->nested.nested_vmx_exit_ctls_low,
2566                         vmx->nested.nested_vmx_exit_ctls_high);
2567                 break;
2568         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2569                 *pdata = vmx_control_msr(
2570                         vmx->nested.nested_vmx_true_entry_ctls_low,
2571                         vmx->nested.nested_vmx_entry_ctls_high);
2572                 break;
2573         case MSR_IA32_VMX_ENTRY_CTLS:
2574                 *pdata = vmx_control_msr(
2575                         vmx->nested.nested_vmx_entry_ctls_low,
2576                         vmx->nested.nested_vmx_entry_ctls_high);
2577                 break;
2578         case MSR_IA32_VMX_MISC:
2579                 *pdata = vmx_control_msr(
2580                         vmx->nested.nested_vmx_misc_low,
2581                         vmx->nested.nested_vmx_misc_high);
2582                 break;
2583         /*
2584          * These MSRs specify bits which the guest must keep fixed (on or off)
2585          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2586          * We picked the standard core2 setting.
2587          */
2588 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2589 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2590         case MSR_IA32_VMX_CR0_FIXED0:
2591                 *pdata = VMXON_CR0_ALWAYSON;
2592                 break;
2593         case MSR_IA32_VMX_CR0_FIXED1:
2594                 *pdata = -1ULL;
2595                 break;
2596         case MSR_IA32_VMX_CR4_FIXED0:
2597                 *pdata = VMXON_CR4_ALWAYSON;
2598                 break;
2599         case MSR_IA32_VMX_CR4_FIXED1:
2600                 *pdata = -1ULL;
2601                 break;
2602         case MSR_IA32_VMX_VMCS_ENUM:
2603                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2604                 break;
2605         case MSR_IA32_VMX_PROCBASED_CTLS2:
2606                 *pdata = vmx_control_msr(
2607                         vmx->nested.nested_vmx_secondary_ctls_low,
2608                         vmx->nested.nested_vmx_secondary_ctls_high);
2609                 break;
2610         case MSR_IA32_VMX_EPT_VPID_CAP:
2611                 /* Currently, no nested vpid support */
2612                 *pdata = vmx->nested.nested_vmx_ept_caps;
2613                 break;
2614         default:
2615                 return 1;
2616         }
2617
2618         return 0;
2619 }
2620
2621 /*
2622  * Reads an msr value (of 'msr_index') into 'pdata'.
2623  * Returns 0 on success, non-0 otherwise.
2624  * Assumes vcpu_load() was already called.
2625  */
2626 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2627 {
2628         u64 data;
2629         struct shared_msr_entry *msr;
2630
2631         if (!pdata) {
2632                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2633                 return -EINVAL;
2634         }
2635
2636         switch (msr_index) {
2637 #ifdef CONFIG_X86_64
2638         case MSR_FS_BASE:
2639                 data = vmcs_readl(GUEST_FS_BASE);
2640                 break;
2641         case MSR_GS_BASE:
2642                 data = vmcs_readl(GUEST_GS_BASE);
2643                 break;
2644         case MSR_KERNEL_GS_BASE:
2645                 vmx_load_host_state(to_vmx(vcpu));
2646                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2647                 break;
2648 #endif
2649         case MSR_EFER:
2650                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2651         case MSR_IA32_TSC:
2652                 data = guest_read_tsc();
2653                 break;
2654         case MSR_IA32_SYSENTER_CS:
2655                 data = vmcs_read32(GUEST_SYSENTER_CS);
2656                 break;
2657         case MSR_IA32_SYSENTER_EIP:
2658                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2659                 break;
2660         case MSR_IA32_SYSENTER_ESP:
2661                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2662                 break;
2663         case MSR_IA32_BNDCFGS:
2664                 if (!vmx_mpx_supported())
2665                         return 1;
2666                 data = vmcs_read64(GUEST_BNDCFGS);
2667                 break;
2668         case MSR_IA32_FEATURE_CONTROL:
2669                 if (!nested_vmx_allowed(vcpu))
2670                         return 1;
2671                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2672                 break;
2673         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2674                 if (!nested_vmx_allowed(vcpu))
2675                         return 1;
2676                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2677         case MSR_IA32_XSS:
2678                 if (!vmx_xsaves_supported())
2679                         return 1;
2680                 data = vcpu->arch.ia32_xss;
2681                 break;
2682         case MSR_TSC_AUX:
2683                 if (!to_vmx(vcpu)->rdtscp_enabled)
2684                         return 1;
2685                 /* Otherwise falls through */
2686         default:
2687                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2688                 if (msr) {
2689                         data = msr->data;
2690                         break;
2691                 }
2692                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2693         }
2694
2695         *pdata = data;
2696         return 0;
2697 }
2698
2699 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2700
2701 /*
2702  * Writes msr value into into the appropriate "register".
2703  * Returns 0 on success, non-0 otherwise.
2704  * Assumes vcpu_load() was already called.
2705  */
2706 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2707 {
2708         struct vcpu_vmx *vmx = to_vmx(vcpu);
2709         struct shared_msr_entry *msr;
2710         int ret = 0;
2711         u32 msr_index = msr_info->index;
2712         u64 data = msr_info->data;
2713
2714         switch (msr_index) {
2715         case MSR_EFER:
2716                 ret = kvm_set_msr_common(vcpu, msr_info);
2717                 break;
2718 #ifdef CONFIG_X86_64
2719         case MSR_FS_BASE:
2720                 vmx_segment_cache_clear(vmx);
2721                 vmcs_writel(GUEST_FS_BASE, data);
2722                 break;
2723         case MSR_GS_BASE:
2724                 vmx_segment_cache_clear(vmx);
2725                 vmcs_writel(GUEST_GS_BASE, data);
2726                 break;
2727         case MSR_KERNEL_GS_BASE:
2728                 vmx_load_host_state(vmx);
2729                 vmx->msr_guest_kernel_gs_base = data;
2730                 break;
2731 #endif
2732         case MSR_IA32_SYSENTER_CS:
2733                 vmcs_write32(GUEST_SYSENTER_CS, data);
2734                 break;
2735         case MSR_IA32_SYSENTER_EIP:
2736                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2737                 break;
2738         case MSR_IA32_SYSENTER_ESP:
2739                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2740                 break;
2741         case MSR_IA32_BNDCFGS:
2742                 if (!vmx_mpx_supported())
2743                         return 1;
2744                 vmcs_write64(GUEST_BNDCFGS, data);
2745                 break;
2746         case MSR_IA32_TSC:
2747                 kvm_write_tsc(vcpu, msr_info);
2748                 break;
2749         case MSR_IA32_CR_PAT:
2750                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2751                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2752                                 return 1;
2753                         vmcs_write64(GUEST_IA32_PAT, data);
2754                         vcpu->arch.pat = data;
2755                         break;
2756                 }
2757                 ret = kvm_set_msr_common(vcpu, msr_info);
2758                 break;
2759         case MSR_IA32_TSC_ADJUST:
2760                 ret = kvm_set_msr_common(vcpu, msr_info);
2761                 break;
2762         case MSR_IA32_FEATURE_CONTROL:
2763                 if (!nested_vmx_allowed(vcpu) ||
2764                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2765                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2766                         return 1;
2767                 vmx->nested.msr_ia32_feature_control = data;
2768                 if (msr_info->host_initiated && data == 0)
2769                         vmx_leave_nested(vcpu);
2770                 break;
2771         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2772                 return 1; /* they are read-only */
2773         case MSR_IA32_XSS:
2774                 if (!vmx_xsaves_supported())
2775                         return 1;
2776                 /*
2777                  * The only supported bit as of Skylake is bit 8, but
2778                  * it is not supported on KVM.
2779                  */
2780                 if (data != 0)
2781                         return 1;
2782                 vcpu->arch.ia32_xss = data;
2783                 if (vcpu->arch.ia32_xss != host_xss)
2784                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2785                                 vcpu->arch.ia32_xss, host_xss);
2786                 else
2787                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2788                 break;
2789         case MSR_TSC_AUX:
2790                 if (!vmx->rdtscp_enabled)
2791                         return 1;
2792                 /* Check reserved bit, higher 32 bits should be zero */
2793                 if ((data >> 32) != 0)
2794                         return 1;
2795                 /* Otherwise falls through */
2796         default:
2797                 msr = find_msr_entry(vmx, msr_index);
2798                 if (msr) {
2799                         u64 old_msr_data = msr->data;
2800                         msr->data = data;
2801                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2802                                 preempt_disable();
2803                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2804                                                          msr->mask);
2805                                 preempt_enable();
2806                                 if (ret)
2807                                         msr->data = old_msr_data;
2808                         }
2809                         break;
2810                 }
2811                 ret = kvm_set_msr_common(vcpu, msr_info);
2812         }
2813
2814         return ret;
2815 }
2816
2817 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2818 {
2819         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2820         switch (reg) {
2821         case VCPU_REGS_RSP:
2822                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2823                 break;
2824         case VCPU_REGS_RIP:
2825                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2826                 break;
2827         case VCPU_EXREG_PDPTR:
2828                 if (enable_ept)
2829                         ept_save_pdptrs(vcpu);
2830                 break;
2831         default:
2832                 break;
2833         }
2834 }
2835
2836 static __init int cpu_has_kvm_support(void)
2837 {
2838         return cpu_has_vmx();
2839 }
2840
2841 static __init int vmx_disabled_by_bios(void)
2842 {
2843         u64 msr;
2844
2845         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2846         if (msr & FEATURE_CONTROL_LOCKED) {
2847                 /* launched w/ TXT and VMX disabled */
2848                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2849                         && tboot_enabled())
2850                         return 1;
2851                 /* launched w/o TXT and VMX only enabled w/ TXT */
2852                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2853                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2854                         && !tboot_enabled()) {
2855                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2856                                 "activate TXT before enabling KVM\n");
2857                         return 1;
2858                 }
2859                 /* launched w/o TXT and VMX disabled */
2860                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2861                         && !tboot_enabled())
2862                         return 1;
2863         }
2864
2865         return 0;
2866 }
2867
2868 static void kvm_cpu_vmxon(u64 addr)
2869 {
2870         asm volatile (ASM_VMX_VMXON_RAX
2871                         : : "a"(&addr), "m"(addr)
2872                         : "memory", "cc");
2873 }
2874
2875 static int hardware_enable(void)
2876 {
2877         int cpu = raw_smp_processor_id();
2878         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2879         u64 old, test_bits;
2880
2881         if (cr4_read_shadow() & X86_CR4_VMXE)
2882                 return -EBUSY;
2883
2884         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2885
2886         /*
2887          * Now we can enable the vmclear operation in kdump
2888          * since the loaded_vmcss_on_cpu list on this cpu
2889          * has been initialized.
2890          *
2891          * Though the cpu is not in VMX operation now, there
2892          * is no problem to enable the vmclear operation
2893          * for the loaded_vmcss_on_cpu list is empty!
2894          */
2895         crash_enable_local_vmclear(cpu);
2896
2897         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2898
2899         test_bits = FEATURE_CONTROL_LOCKED;
2900         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2901         if (tboot_enabled())
2902                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2903
2904         if ((old & test_bits) != test_bits) {
2905                 /* enable and lock */
2906                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2907         }
2908         cr4_set_bits(X86_CR4_VMXE);
2909
2910         if (vmm_exclusive) {
2911                 kvm_cpu_vmxon(phys_addr);
2912                 ept_sync_global();
2913         }
2914
2915         native_store_gdt(this_cpu_ptr(&host_gdt));
2916
2917         return 0;
2918 }
2919
2920 static void vmclear_local_loaded_vmcss(void)
2921 {
2922         int cpu = raw_smp_processor_id();
2923         struct loaded_vmcs *v, *n;
2924
2925         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2926                                  loaded_vmcss_on_cpu_link)
2927                 __loaded_vmcs_clear(v);
2928 }
2929
2930
2931 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2932  * tricks.
2933  */
2934 static void kvm_cpu_vmxoff(void)
2935 {
2936         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2937 }
2938
2939 static void hardware_disable(void)
2940 {
2941         if (vmm_exclusive) {
2942                 vmclear_local_loaded_vmcss();
2943                 kvm_cpu_vmxoff();
2944         }
2945         cr4_clear_bits(X86_CR4_VMXE);
2946 }
2947
2948 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2949                                       u32 msr, u32 *result)
2950 {
2951         u32 vmx_msr_low, vmx_msr_high;
2952         u32 ctl = ctl_min | ctl_opt;
2953
2954         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2955
2956         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2957         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2958
2959         /* Ensure minimum (required) set of control bits are supported. */
2960         if (ctl_min & ~ctl)
2961                 return -EIO;
2962
2963         *result = ctl;
2964         return 0;
2965 }
2966
2967 static __init bool allow_1_setting(u32 msr, u32 ctl)
2968 {
2969         u32 vmx_msr_low, vmx_msr_high;
2970
2971         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2972         return vmx_msr_high & ctl;
2973 }
2974
2975 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2976 {
2977         u32 vmx_msr_low, vmx_msr_high;
2978         u32 min, opt, min2, opt2;
2979         u32 _pin_based_exec_control = 0;
2980         u32 _cpu_based_exec_control = 0;
2981         u32 _cpu_based_2nd_exec_control = 0;
2982         u32 _vmexit_control = 0;
2983         u32 _vmentry_control = 0;
2984
2985         min = CPU_BASED_HLT_EXITING |
2986 #ifdef CONFIG_X86_64
2987               CPU_BASED_CR8_LOAD_EXITING |
2988               CPU_BASED_CR8_STORE_EXITING |
2989 #endif
2990               CPU_BASED_CR3_LOAD_EXITING |
2991               CPU_BASED_CR3_STORE_EXITING |
2992               CPU_BASED_USE_IO_BITMAPS |
2993               CPU_BASED_MOV_DR_EXITING |
2994               CPU_BASED_USE_TSC_OFFSETING |
2995               CPU_BASED_MWAIT_EXITING |
2996               CPU_BASED_MONITOR_EXITING |
2997               CPU_BASED_INVLPG_EXITING |
2998               CPU_BASED_RDPMC_EXITING;
2999
3000         opt = CPU_BASED_TPR_SHADOW |
3001               CPU_BASED_USE_MSR_BITMAPS |
3002               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3003         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3004                                 &_cpu_based_exec_control) < 0)
3005                 return -EIO;
3006 #ifdef CONFIG_X86_64
3007         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3008                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3009                                            ~CPU_BASED_CR8_STORE_EXITING;
3010 #endif
3011         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3012                 min2 = 0;
3013                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3014                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3015                         SECONDARY_EXEC_WBINVD_EXITING |
3016                         SECONDARY_EXEC_ENABLE_VPID |
3017                         SECONDARY_EXEC_ENABLE_EPT |
3018                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3019                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3020                         SECONDARY_EXEC_RDTSCP |
3021                         SECONDARY_EXEC_ENABLE_INVPCID |
3022                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3023                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3024                         SECONDARY_EXEC_SHADOW_VMCS |
3025                         SECONDARY_EXEC_XSAVES |
3026                         SECONDARY_EXEC_ENABLE_PML;
3027                 if (adjust_vmx_controls(min2, opt2,
3028                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3029                                         &_cpu_based_2nd_exec_control) < 0)
3030                         return -EIO;
3031         }
3032 #ifndef CONFIG_X86_64
3033         if (!(_cpu_based_2nd_exec_control &
3034                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3035                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3036 #endif
3037
3038         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3039                 _cpu_based_2nd_exec_control &= ~(
3040                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3041                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3042                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3043
3044         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3045                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3046                    enabled */
3047                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3048                                              CPU_BASED_CR3_STORE_EXITING |
3049                                              CPU_BASED_INVLPG_EXITING);
3050                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3051                       vmx_capability.ept, vmx_capability.vpid);
3052         }
3053
3054         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3055 #ifdef CONFIG_X86_64
3056         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3057 #endif
3058         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3059                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3060         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3061                                 &_vmexit_control) < 0)
3062                 return -EIO;
3063
3064         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3065         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3066         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3067                                 &_pin_based_exec_control) < 0)
3068                 return -EIO;
3069
3070         if (!(_cpu_based_2nd_exec_control &
3071                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3072                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3073                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3074
3075         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3076         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3077         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3078                                 &_vmentry_control) < 0)
3079                 return -EIO;
3080
3081         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3082
3083         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3084         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3085                 return -EIO;
3086
3087 #ifdef CONFIG_X86_64
3088         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3089         if (vmx_msr_high & (1u<<16))
3090                 return -EIO;
3091 #endif
3092
3093         /* Require Write-Back (WB) memory type for VMCS accesses. */
3094         if (((vmx_msr_high >> 18) & 15) != 6)
3095                 return -EIO;
3096
3097         vmcs_conf->size = vmx_msr_high & 0x1fff;
3098         vmcs_conf->order = get_order(vmcs_config.size);
3099         vmcs_conf->revision_id = vmx_msr_low;
3100
3101         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3102         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3103         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3104         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3105         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3106
3107         cpu_has_load_ia32_efer =
3108                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3109                                 VM_ENTRY_LOAD_IA32_EFER)
3110                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3111                                    VM_EXIT_LOAD_IA32_EFER);
3112
3113         cpu_has_load_perf_global_ctrl =
3114                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3115                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3116                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3117                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3118
3119         /*
3120          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3121          * but due to arrata below it can't be used. Workaround is to use
3122          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3123          *
3124          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3125          *
3126          * AAK155             (model 26)
3127          * AAP115             (model 30)
3128          * AAT100             (model 37)
3129          * BC86,AAY89,BD102   (model 44)
3130          * BA97               (model 46)
3131          *
3132          */
3133         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3134                 switch (boot_cpu_data.x86_model) {
3135                 case 26:
3136                 case 30:
3137                 case 37:
3138                 case 44:
3139                 case 46:
3140                         cpu_has_load_perf_global_ctrl = false;
3141                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3142                                         "does not work properly. Using workaround\n");
3143                         break;
3144                 default:
3145                         break;
3146                 }
3147         }
3148
3149         if (cpu_has_xsaves)
3150                 rdmsrl(MSR_IA32_XSS, host_xss);
3151
3152         return 0;
3153 }
3154
3155 static struct vmcs *alloc_vmcs_cpu(int cpu)
3156 {
3157         int node = cpu_to_node(cpu);
3158         struct page *pages;
3159         struct vmcs *vmcs;
3160
3161         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3162         if (!pages)
3163                 return NULL;
3164         vmcs = page_address(pages);
3165         memset(vmcs, 0, vmcs_config.size);
3166         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3167         return vmcs;
3168 }
3169
3170 static struct vmcs *alloc_vmcs(void)
3171 {
3172         return alloc_vmcs_cpu(raw_smp_processor_id());
3173 }
3174
3175 static void free_vmcs(struct vmcs *vmcs)
3176 {
3177         free_pages((unsigned long)vmcs, vmcs_config.order);
3178 }
3179
3180 /*
3181  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3182  */
3183 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3184 {
3185         if (!loaded_vmcs->vmcs)
3186                 return;
3187         loaded_vmcs_clear(loaded_vmcs);
3188         free_vmcs(loaded_vmcs->vmcs);
3189         loaded_vmcs->vmcs = NULL;
3190 }
3191
3192 static void free_kvm_area(void)
3193 {
3194         int cpu;
3195
3196         for_each_possible_cpu(cpu) {
3197                 free_vmcs(per_cpu(vmxarea, cpu));
3198                 per_cpu(vmxarea, cpu) = NULL;
3199         }
3200 }
3201
3202 static void init_vmcs_shadow_fields(void)
3203 {
3204         int i, j;
3205
3206         /* No checks for read only fields yet */
3207
3208         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3209                 switch (shadow_read_write_fields[i]) {
3210                 case GUEST_BNDCFGS:
3211                         if (!vmx_mpx_supported())
3212                                 continue;
3213                         break;
3214                 default:
3215                         break;
3216                 }
3217
3218                 if (j < i)
3219                         shadow_read_write_fields[j] =
3220                                 shadow_read_write_fields[i];
3221                 j++;
3222         }
3223         max_shadow_read_write_fields = j;
3224
3225         /* shadowed fields guest access without vmexit */
3226         for (i = 0; i < max_shadow_read_write_fields; i++) {
3227                 clear_bit(shadow_read_write_fields[i],
3228                           vmx_vmwrite_bitmap);
3229                 clear_bit(shadow_read_write_fields[i],
3230                           vmx_vmread_bitmap);
3231         }
3232         for (i = 0; i < max_shadow_read_only_fields; i++)
3233                 clear_bit(shadow_read_only_fields[i],
3234                           vmx_vmread_bitmap);
3235 }
3236
3237 static __init int alloc_kvm_area(void)
3238 {
3239         int cpu;
3240
3241         for_each_possible_cpu(cpu) {
3242                 struct vmcs *vmcs;
3243
3244                 vmcs = alloc_vmcs_cpu(cpu);
3245                 if (!vmcs) {
3246                         free_kvm_area();
3247                         return -ENOMEM;
3248                 }
3249
3250                 per_cpu(vmxarea, cpu) = vmcs;
3251         }
3252         return 0;
3253 }
3254
3255 static bool emulation_required(struct kvm_vcpu *vcpu)
3256 {
3257         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3258 }
3259
3260 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3261                 struct kvm_segment *save)
3262 {
3263         if (!emulate_invalid_guest_state) {
3264                 /*
3265                  * CS and SS RPL should be equal during guest entry according
3266                  * to VMX spec, but in reality it is not always so. Since vcpu
3267                  * is in the middle of the transition from real mode to
3268                  * protected mode it is safe to assume that RPL 0 is a good
3269                  * default value.
3270                  */
3271                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3272                         save->selector &= ~SEGMENT_RPL_MASK;
3273                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3274                 save->s = 1;
3275         }
3276         vmx_set_segment(vcpu, save, seg);
3277 }
3278
3279 static void enter_pmode(struct kvm_vcpu *vcpu)
3280 {
3281         unsigned long flags;
3282         struct vcpu_vmx *vmx = to_vmx(vcpu);
3283
3284         /*
3285          * Update real mode segment cache. It may be not up-to-date if sement
3286          * register was written while vcpu was in a guest mode.
3287          */
3288         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3289         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3290         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3291         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3292         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3293         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3294
3295         vmx->rmode.vm86_active = 0;
3296
3297         vmx_segment_cache_clear(vmx);
3298
3299         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3300
3301         flags = vmcs_readl(GUEST_RFLAGS);
3302         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3303         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3304         vmcs_writel(GUEST_RFLAGS, flags);
3305
3306         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3307                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3308
3309         update_exception_bitmap(vcpu);
3310
3311         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3312         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3313         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3314         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3315         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3316         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3317 }
3318
3319 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3320 {
3321         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3322         struct kvm_segment var = *save;
3323
3324         var.dpl = 0x3;
3325         if (seg == VCPU_SREG_CS)
3326                 var.type = 0x3;
3327
3328         if (!emulate_invalid_guest_state) {
3329                 var.selector = var.base >> 4;
3330                 var.base = var.base & 0xffff0;
3331                 var.limit = 0xffff;
3332                 var.g = 0;
3333                 var.db = 0;
3334                 var.present = 1;
3335                 var.s = 1;
3336                 var.l = 0;
3337                 var.unusable = 0;
3338                 var.type = 0x3;
3339                 var.avl = 0;
3340                 if (save->base & 0xf)
3341                         printk_once(KERN_WARNING "kvm: segment base is not "
3342                                         "paragraph aligned when entering "
3343                                         "protected mode (seg=%d)", seg);
3344         }
3345
3346         vmcs_write16(sf->selector, var.selector);
3347         vmcs_write32(sf->base, var.base);
3348         vmcs_write32(sf->limit, var.limit);
3349         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3350 }
3351
3352 static void enter_rmode(struct kvm_vcpu *vcpu)
3353 {
3354         unsigned long flags;
3355         struct vcpu_vmx *vmx = to_vmx(vcpu);
3356
3357         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3358         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3359         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3360         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3361         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3362         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3363         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3364
3365         vmx->rmode.vm86_active = 1;
3366
3367         /*
3368          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3369          * vcpu. Warn the user that an update is overdue.
3370          */
3371         if (!vcpu->kvm->arch.tss_addr)
3372                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3373                              "called before entering vcpu\n");
3374
3375         vmx_segment_cache_clear(vmx);
3376
3377         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3378         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3379         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3380
3381         flags = vmcs_readl(GUEST_RFLAGS);
3382         vmx->rmode.save_rflags = flags;
3383
3384         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3385
3386         vmcs_writel(GUEST_RFLAGS, flags);
3387         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3388         update_exception_bitmap(vcpu);