arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * Hyper-V requires all of these, so mark them as supported even though
 137  * they are just treated the same as all-context.
 138  */
 139 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 140         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 141         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 143         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 144
 145 /*
 146  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 147  * ple_gap:    upper bound on the amount of time between two successive
 148  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 149  *             According to test, this time is usually smaller than 128 cycles.
 150  * ple_window: upper bound on the amount of time a guest is allowed to execute
 151  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 152  *             less than 2^12 cycles
 153  * Time is measured based on a counter that runs at the same rate as the TSC,
 154  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 155  */
 156 #define KVM_VMX_DEFAULT_PLE_GAP           128
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 161                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 162
 163 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 164 module_param(ple_gap, int, S_IRUGO);
 165
 166 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 167 module_param(ple_window, int, S_IRUGO);
 168
 169 /* Default doubles per-vcpu window every exit. */
 170 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 171 module_param(ple_window_grow, int, S_IRUGO);
 172
 173 /* Default resets per-vcpu window every exit to ple_window. */
 174 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 175 module_param(ple_window_shrink, int, S_IRUGO);
 176
 177 /* Default is to compute the maximum so we can never overflow. */
 178 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 180 module_param(ple_window_max, int, S_IRUGO);
 181
 182 extern const ulong vmx_return;
 183
 184 #define NR_AUTOLOAD_MSRS 8
 185 #define VMCS02_POOL_SIZE 1
 186
 187 struct vmcs {
 188         u32 revision_id;
 189         u32 abort;
 190         char data[0];
 191 };
 192
 193 /*
 194  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 195  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 196  * loaded on this CPU (so we can clear them if the CPU goes down).
 197  */
 198 struct loaded_vmcs {
 199         struct vmcs *vmcs;
 200         struct vmcs *shadow_vmcs;
 201         int cpu;
 202         int launched;
 203         struct list_head loaded_vmcss_on_cpu_link;
 204 };
 205
 206 struct shared_msr_entry {
 207         unsigned index;
 208         u64 data;
 209         u64 mask;
 210 };
 211
 212 /*
 213  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 214  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 215  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 216  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 217  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 218  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 219  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 220  * underlying hardware which will be used to run L2.
 221  * This structure is packed to ensure that its layout is identical across
 222  * machines (necessary for live migration).
 223  * If there are changes in this struct, VMCS12_REVISION must be changed.
 224  */
 225 typedef u64 natural_width;
 226 struct __packed vmcs12 {
 227         /* According to the Intel spec, a VMCS region must start with the
 228          * following two fields. Then follow implementation-specific data.
 229          */
 230         u32 revision_id;
 231         u32 abort;
 232
 233         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 234         u32 padding[7]; /* room for future expansion */
 235
 236         u64 io_bitmap_a;
 237         u64 io_bitmap_b;
 238         u64 msr_bitmap;
 239         u64 vm_exit_msr_store_addr;
 240         u64 vm_exit_msr_load_addr;
 241         u64 vm_entry_msr_load_addr;
 242         u64 tsc_offset;
 243         u64 virtual_apic_page_addr;
 244         u64 apic_access_addr;
 245         u64 posted_intr_desc_addr;
 246         u64 ept_pointer;
 247         u64 eoi_exit_bitmap0;
 248         u64 eoi_exit_bitmap1;
 249         u64 eoi_exit_bitmap2;
 250         u64 eoi_exit_bitmap3;
 251         u64 xss_exit_bitmap;
 252         u64 guest_physical_address;
 253         u64 vmcs_link_pointer;
 254         u64 guest_ia32_debugctl;
 255         u64 guest_ia32_pat;
 256         u64 guest_ia32_efer;
 257         u64 guest_ia32_perf_global_ctrl;
 258         u64 guest_pdptr0;
 259         u64 guest_pdptr1;
 260         u64 guest_pdptr2;
 261         u64 guest_pdptr3;
 262         u64 guest_bndcfgs;
 263         u64 host_ia32_pat;
 264         u64 host_ia32_efer;
 265         u64 host_ia32_perf_global_ctrl;
 266         u64 padding64[8]; /* room for future expansion */
 267         /*
 268          * To allow migration of L1 (complete with its L2 guests) between
 269          * machines of different natural widths (32 or 64 bit), we cannot have
 270          * unsigned long fields with no explict size. We use u64 (aliased
 271          * natural_width) instead. Luckily, x86 is little-endian.
 272          */
 273         natural_width cr0_guest_host_mask;
 274         natural_width cr4_guest_host_mask;
 275         natural_width cr0_read_shadow;
 276         natural_width cr4_read_shadow;
 277         natural_width cr3_target_value0;
 278         natural_width cr3_target_value1;
 279         natural_width cr3_target_value2;
 280         natural_width cr3_target_value3;
 281         natural_width exit_qualification;
 282         natural_width guest_linear_address;
 283         natural_width guest_cr0;
 284         natural_width guest_cr3;
 285         natural_width guest_cr4;
 286         natural_width guest_es_base;
 287         natural_width guest_cs_base;
 288         natural_width guest_ss_base;
 289         natural_width guest_ds_base;
 290         natural_width guest_fs_base;
 291         natural_width guest_gs_base;
 292         natural_width guest_ldtr_base;
 293         natural_width guest_tr_base;
 294         natural_width guest_gdtr_base;
 295         natural_width guest_idtr_base;
 296         natural_width guest_dr7;
 297         natural_width guest_rsp;
 298         natural_width guest_rip;
 299         natural_width guest_rflags;
 300         natural_width guest_pending_dbg_exceptions;
 301         natural_width guest_sysenter_esp;
 302         natural_width guest_sysenter_eip;
 303         natural_width host_cr0;
 304         natural_width host_cr3;
 305         natural_width host_cr4;
 306         natural_width host_fs_base;
 307         natural_width host_gs_base;
 308         natural_width host_tr_base;
 309         natural_width host_gdtr_base;
 310         natural_width host_idtr_base;
 311         natural_width host_ia32_sysenter_esp;
 312         natural_width host_ia32_sysenter_eip;
 313         natural_width host_rsp;
 314         natural_width host_rip;
 315         natural_width paddingl[8]; /* room for future expansion */
 316         u32 pin_based_vm_exec_control;
 317         u32 cpu_based_vm_exec_control;
 318         u32 exception_bitmap;
 319         u32 page_fault_error_code_mask;
 320         u32 page_fault_error_code_match;
 321         u32 cr3_target_count;
 322         u32 vm_exit_controls;
 323         u32 vm_exit_msr_store_count;
 324         u32 vm_exit_msr_load_count;
 325         u32 vm_entry_controls;
 326         u32 vm_entry_msr_load_count;
 327         u32 vm_entry_intr_info_field;
 328         u32 vm_entry_exception_error_code;
 329         u32 vm_entry_instruction_len;
 330         u32 tpr_threshold;
 331         u32 secondary_vm_exec_control;
 332         u32 vm_instruction_error;
 333         u32 vm_exit_reason;
 334         u32 vm_exit_intr_info;
 335         u32 vm_exit_intr_error_code;
 336         u32 idt_vectoring_info_field;
 337         u32 idt_vectoring_error_code;
 338         u32 vm_exit_instruction_len;
 339         u32 vmx_instruction_info;
 340         u32 guest_es_limit;
 341         u32 guest_cs_limit;
 342         u32 guest_ss_limit;
 343         u32 guest_ds_limit;
 344         u32 guest_fs_limit;
 345         u32 guest_gs_limit;
 346         u32 guest_ldtr_limit;
 347         u32 guest_tr_limit;
 348         u32 guest_gdtr_limit;
 349         u32 guest_idtr_limit;
 350         u32 guest_es_ar_bytes;
 351         u32 guest_cs_ar_bytes;
 352         u32 guest_ss_ar_bytes;
 353         u32 guest_ds_ar_bytes;
 354         u32 guest_fs_ar_bytes;
 355         u32 guest_gs_ar_bytes;
 356         u32 guest_ldtr_ar_bytes;
 357         u32 guest_tr_ar_bytes;
 358         u32 guest_interruptibility_info;
 359         u32 guest_activity_state;
 360         u32 guest_sysenter_cs;
 361         u32 host_ia32_sysenter_cs;
 362         u32 vmx_preemption_timer_value;
 363         u32 padding32[7]; /* room for future expansion */
 364         u16 virtual_processor_id;
 365         u16 posted_intr_nv;
 366         u16 guest_es_selector;
 367         u16 guest_cs_selector;
 368         u16 guest_ss_selector;
 369         u16 guest_ds_selector;
 370         u16 guest_fs_selector;
 371         u16 guest_gs_selector;
 372         u16 guest_ldtr_selector;
 373         u16 guest_tr_selector;
 374         u16 guest_intr_status;
 375         u16 host_es_selector;
 376         u16 host_cs_selector;
 377         u16 host_ss_selector;
 378         u16 host_ds_selector;
 379         u16 host_fs_selector;
 380         u16 host_gs_selector;
 381         u16 host_tr_selector;
 382 };
 383
 384 /*
 385  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 386  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 387  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 388  */
 389 #define VMCS12_REVISION 0x11e57ed0
 390
 391 /*
 392  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 393  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 394  * current implementation, 4K are reserved to avoid future complications.
 395  */
 396 #define VMCS12_SIZE 0x1000
 397
 398 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 399 struct vmcs02_list {
 400         struct list_head list;
 401         gpa_t vmptr;
 402         struct loaded_vmcs vmcs02;
 403 };
 404
 405 /*
 406  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 407  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 408  */
 409 struct nested_vmx {
 410         /* Has the level1 guest done vmxon? */
 411         bool vmxon;
 412         gpa_t vmxon_ptr;
 413
 414         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 415         gpa_t current_vmptr;
 416         /* The host-usable pointer to the above */
 417         struct page *current_vmcs12_page;
 418         struct vmcs12 *current_vmcs12;
 419         /*
 420          * Cache of the guest's VMCS, existing outside of guest memory.
 421          * Loaded from guest memory during VMPTRLD. Flushed to guest
 422          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 423          */
 424         struct vmcs12 *cached_vmcs12;
 425         /*
 426          * Indicates if the shadow vmcs must be updated with the
 427          * data hold by vmcs12
 428          */
 429         bool sync_shadow_vmcs;
 430
 431         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 432         struct list_head vmcs02_pool;
 433         int vmcs02_num;
 434         bool change_vmcs01_virtual_x2apic_mode;
 435         /* L2 must run next, and mustn't decide to exit to L1. */
 436         bool nested_run_pending;
 437         /*
 438          * Guest pages referred to in vmcs02 with host-physical pointers, so
 439          * we must keep them pinned while L2 runs.
 440          */
 441         struct page *apic_access_page;
 442         struct page *virtual_apic_page;
 443         struct page *pi_desc_page;
 444         struct pi_desc *pi_desc;
 445         bool pi_pending;
 446         u16 posted_intr_nv;
 447
 448         unsigned long *msr_bitmap;
 449
 450         struct hrtimer preemption_timer;
 451         bool preemption_timer_expired;
 452
 453         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 454         u64 vmcs01_debugctl;
 455
 456         u16 vpid02;
 457         u16 last_vpid;
 458
 459         /*
 460          * We only store the "true" versions of the VMX capability MSRs. We
 461          * generate the "non-true" versions by setting the must-be-1 bits
 462          * according to the SDM.
 463          */
 464         u32 nested_vmx_procbased_ctls_low;
 465         u32 nested_vmx_procbased_ctls_high;
 466         u32 nested_vmx_secondary_ctls_low;
 467         u32 nested_vmx_secondary_ctls_high;
 468         u32 nested_vmx_pinbased_ctls_low;
 469         u32 nested_vmx_pinbased_ctls_high;
 470         u32 nested_vmx_exit_ctls_low;
 471         u32 nested_vmx_exit_ctls_high;
 472         u32 nested_vmx_entry_ctls_low;
 473         u32 nested_vmx_entry_ctls_high;
 474         u32 nested_vmx_misc_low;
 475         u32 nested_vmx_misc_high;
 476         u32 nested_vmx_ept_caps;
 477         u32 nested_vmx_vpid_caps;
 478         u64 nested_vmx_basic;
 479         u64 nested_vmx_cr0_fixed0;
 480         u64 nested_vmx_cr0_fixed1;
 481         u64 nested_vmx_cr4_fixed0;
 482         u64 nested_vmx_cr4_fixed1;
 483         u64 nested_vmx_vmcs_enum;
 484 };
 485
 486 #define POSTED_INTR_ON  0
 487 #define POSTED_INTR_SN  1
 488
 489 /* Posted-Interrupt Descriptor */
 490 struct pi_desc {
 491         u32 pir[8];     /* Posted interrupt requested */
 492         union {
 493                 struct {
 494                                 /* bit 256 - Outstanding Notification */
 495                         u16     on      : 1,
 496                                 /* bit 257 - Suppress Notification */
 497                                 sn      : 1,
 498                                 /* bit 271:258 - Reserved */
 499                                 rsvd_1  : 14;
 500                                 /* bit 279:272 - Notification Vector */
 501                         u8      nv;
 502                                 /* bit 287:280 - Reserved */
 503                         u8      rsvd_2;
 504                                 /* bit 319:288 - Notification Destination */
 505                         u32     ndst;
 506                 };
 507                 u64 control;
 508         };
 509         u32 rsvd[6];
 510 } __aligned(64);
 511
 512 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 513 {
 514         return test_and_set_bit(POSTED_INTR_ON,
 515                         (unsigned long *)&pi_desc->control);
 516 }
 517
 518 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 519 {
 520         return test_and_clear_bit(POSTED_INTR_ON,
 521                         (unsigned long *)&pi_desc->control);
 522 }
 523
 524 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 525 {
 526         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 527 }
 528
 529 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 530 {
 531         return clear_bit(POSTED_INTR_SN,
 532                         (unsigned long *)&pi_desc->control);
 533 }
 534
 535 static inline void pi_set_sn(struct pi_desc *pi_desc)
 536 {
 537         return set_bit(POSTED_INTR_SN,
 538                         (unsigned long *)&pi_desc->control);
 539 }
 540
 541 static inline void pi_clear_on(struct pi_desc *pi_desc)
 542 {
 543         clear_bit(POSTED_INTR_ON,
 544                   (unsigned long *)&pi_desc->control);
 545 }
 546
 547 static inline int pi_test_on(struct pi_desc *pi_desc)
 548 {
 549         return test_bit(POSTED_INTR_ON,
 550                         (unsigned long *)&pi_desc->control);
 551 }
 552
 553 static inline int pi_test_sn(struct pi_desc *pi_desc)
 554 {
 555         return test_bit(POSTED_INTR_SN,
 556                         (unsigned long *)&pi_desc->control);
 557 }
 558
 559 struct vcpu_vmx {
 560         struct kvm_vcpu       vcpu;
 561         unsigned long         host_rsp;
 562         u8                    fail;
 563         bool                  nmi_known_unmasked;
 564         u32                   exit_intr_info;
 565         u32                   idt_vectoring_info;
 566         ulong                 rflags;
 567         struct shared_msr_entry *guest_msrs;
 568         int                   nmsrs;
 569         int                   save_nmsrs;
 570         unsigned long         host_idt_base;
 571 #ifdef CONFIG_X86_64
 572         u64                   msr_host_kernel_gs_base;
 573         u64                   msr_guest_kernel_gs_base;
 574 #endif
 575         u32 vm_entry_controls_shadow;
 576         u32 vm_exit_controls_shadow;
 577         /*
 578          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 579          * non-nested (L1) guest, it always points to vmcs01. For a nested
 580          * guest (L2), it points to a different VMCS.
 581          */
 582         struct loaded_vmcs    vmcs01;
 583         struct loaded_vmcs   *loaded_vmcs;
 584         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 585         struct msr_autoload {
 586                 unsigned nr;
 587                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 588                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 589         } msr_autoload;
 590         struct {
 591                 int           loaded;
 592                 u16           fs_sel, gs_sel, ldt_sel;
 593 #ifdef CONFIG_X86_64
 594                 u16           ds_sel, es_sel;
 595 #endif
 596                 int           gs_ldt_reload_needed;
 597                 int           fs_reload_needed;
 598                 u64           msr_host_bndcfgs;
 599                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 600         } host_state;
 601         struct {
 602                 int vm86_active;
 603                 ulong save_rflags;
 604                 struct kvm_segment segs[8];
 605         } rmode;
 606         struct {
 607                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 608                 struct kvm_save_segment {
 609                         u16 selector;
 610                         unsigned long base;
 611                         u32 limit;
 612                         u32 ar;
 613                 } seg[8];
 614         } segment_cache;
 615         int vpid;
 616         bool emulation_required;
 617
 618         /* Support for vnmi-less CPUs */
 619         int soft_vnmi_blocked;
 620         ktime_t entry_time;
 621         s64 vnmi_blocked_time;
 622         u32 exit_reason;
 623
 624         /* Posted interrupt descriptor */
 625         struct pi_desc pi_desc;
 626
 627         /* Support for a guest hypervisor (nested VMX) */
 628         struct nested_vmx nested;
 629
 630         /* Dynamic PLE window. */
 631         int ple_window;
 632         bool ple_window_dirty;
 633
 634         /* Support for PML */
 635 #define PML_ENTITY_NUM          512
 636         struct page *pml_pg;
 637
 638         /* apic deadline value in host tsc */
 639         u64 hv_deadline_tsc;
 640
 641         u64 current_tsc_ratio;
 642
 643         bool guest_pkru_valid;
 644         u32 guest_pkru;
 645         u32 host_pkru;
 646
 647         /*
 648          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 649          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 650          * in msr_ia32_feature_control_valid_bits.
 651          */
 652         u64 msr_ia32_feature_control;
 653         u64 msr_ia32_feature_control_valid_bits;
 654 };
 655
 656 enum segment_cache_field {
 657         SEG_FIELD_SEL = 0,
 658         SEG_FIELD_BASE = 1,
 659         SEG_FIELD_LIMIT = 2,
 660         SEG_FIELD_AR = 3,
 661
 662         SEG_FIELD_NR = 4
 663 };
 664
 665 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 666 {
 667         return container_of(vcpu, struct vcpu_vmx, vcpu);
 668 }
 669
 670 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 671 {
 672         return &(to_vmx(vcpu)->pi_desc);
 673 }
 674
 675 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 676 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 677 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 678                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 679
 680
 681 static unsigned long shadow_read_only_fields[] = {
 682         /*
 683          * We do NOT shadow fields that are modified when L0
 684          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 685          * VMXON...) executed by L1.
 686          * For example, VM_INSTRUCTION_ERROR is read
 687          * by L1 if a vmx instruction fails (part of the error path).
 688          * Note the code assumes this logic. If for some reason
 689          * we start shadowing these fields then we need to
 690          * force a shadow sync when L0 emulates vmx instructions
 691          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 692          * by nested_vmx_failValid)
 693          */
 694         VM_EXIT_REASON,
 695         VM_EXIT_INTR_INFO,
 696         VM_EXIT_INSTRUCTION_LEN,
 697         IDT_VECTORING_INFO_FIELD,
 698         IDT_VECTORING_ERROR_CODE,
 699         VM_EXIT_INTR_ERROR_CODE,
 700         EXIT_QUALIFICATION,
 701         GUEST_LINEAR_ADDRESS,
 702         GUEST_PHYSICAL_ADDRESS
 703 };
 704 static int max_shadow_read_only_fields =
 705         ARRAY_SIZE(shadow_read_only_fields);
 706
 707 static unsigned long shadow_read_write_fields[] = {
 708         TPR_THRESHOLD,
 709         GUEST_RIP,
 710         GUEST_RSP,
 711         GUEST_CR0,
 712         GUEST_CR3,
 713         GUEST_CR4,
 714         GUEST_INTERRUPTIBILITY_INFO,
 715         GUEST_RFLAGS,
 716         GUEST_CS_SELECTOR,
 717         GUEST_CS_AR_BYTES,
 718         GUEST_CS_LIMIT,
 719         GUEST_CS_BASE,
 720         GUEST_ES_BASE,
 721         GUEST_BNDCFGS,
 722         CR0_GUEST_HOST_MASK,
 723         CR0_READ_SHADOW,
 724         CR4_READ_SHADOW,
 725         TSC_OFFSET,
 726         EXCEPTION_BITMAP,
 727         CPU_BASED_VM_EXEC_CONTROL,
 728         VM_ENTRY_EXCEPTION_ERROR_CODE,
 729         VM_ENTRY_INTR_INFO_FIELD,
 730         VM_ENTRY_INSTRUCTION_LEN,
 731         VM_ENTRY_EXCEPTION_ERROR_CODE,
 732         HOST_FS_BASE,
 733         HOST_GS_BASE,
 734         HOST_FS_SELECTOR,
 735         HOST_GS_SELECTOR
 736 };
 737 static int max_shadow_read_write_fields =
 738         ARRAY_SIZE(shadow_read_write_fields);
 739
 740 static const unsigned short vmcs_field_to_offset_table[] = {
 741         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 742         FIELD(POSTED_INTR_NV, posted_intr_nv),
 743         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 744         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 745         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 746         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 747         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 748         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 749         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 750         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 751         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(EPT_POINTER, ept_pointer),
 770         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 771         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 772         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 773         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 774         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 775         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 776         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 777         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 778         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 779         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 780         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 781         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 782         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 783         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 784         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 785         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 786         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 787         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 788         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 789         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 790         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 791         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 792         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 793         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 794         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 795         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 796         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 797         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 798         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 799         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 800         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 801         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 802         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 803         FIELD(TPR_THRESHOLD, tpr_threshold),
 804         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 805         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 806         FIELD(VM_EXIT_REASON, vm_exit_reason),
 807         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 808         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 809         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 810         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 811         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 812         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 813         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 814         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 815         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 816         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 817         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 818         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 819         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 820         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 821         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 822         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 823         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 824         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 825         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 826         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 827         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 828         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 829         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 830         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 831         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 832         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 833         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 834         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 835         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 836         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 837         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 838         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 839         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 840         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 841         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 842         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 843         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 844         FIELD(EXIT_QUALIFICATION, exit_qualification),
 845         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 846         FIELD(GUEST_CR0, guest_cr0),
 847         FIELD(GUEST_CR3, guest_cr3),
 848         FIELD(GUEST_CR4, guest_cr4),
 849         FIELD(GUEST_ES_BASE, guest_es_base),
 850         FIELD(GUEST_CS_BASE, guest_cs_base),
 851         FIELD(GUEST_SS_BASE, guest_ss_base),
 852         FIELD(GUEST_DS_BASE, guest_ds_base),
 853         FIELD(GUEST_FS_BASE, guest_fs_base),
 854         FIELD(GUEST_GS_BASE, guest_gs_base),
 855         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 856         FIELD(GUEST_TR_BASE, guest_tr_base),
 857         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 858         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 859         FIELD(GUEST_DR7, guest_dr7),
 860         FIELD(GUEST_RSP, guest_rsp),
 861         FIELD(GUEST_RIP, guest_rip),
 862         FIELD(GUEST_RFLAGS, guest_rflags),
 863         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 864         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 865         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 866         FIELD(HOST_CR0, host_cr0),
 867         FIELD(HOST_CR3, host_cr3),
 868         FIELD(HOST_CR4, host_cr4),
 869         FIELD(HOST_FS_BASE, host_fs_base),
 870         FIELD(HOST_GS_BASE, host_gs_base),
 871         FIELD(HOST_TR_BASE, host_tr_base),
 872         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 873         FIELD(HOST_IDTR_BASE, host_idtr_base),
 874         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 875         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 876         FIELD(HOST_RSP, host_rsp),
 877         FIELD(HOST_RIP, host_rip),
 878 };
 879
 880 static inline short vmcs_field_to_offset(unsigned long field)
 881 {
 882         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 883
 884         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 885             vmcs_field_to_offset_table[field] == 0)
 886                 return -ENOENT;
 887
 888         return vmcs_field_to_offset_table[field];
 889 }
 890
 891 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 892 {
 893         return to_vmx(vcpu)->nested.cached_vmcs12;
 894 }
 895
 896 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 897 {
 898         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 899         if (is_error_page(page))
 900                 return NULL;
 901
 902         return page;
 903 }
 904
 905 static void nested_release_page(struct page *page)
 906 {
 907         kvm_release_page_dirty(page);
 908 }
 909
 910 static void nested_release_page_clean(struct page *page)
 911 {
 912         kvm_release_page_clean(page);
 913 }
 914
 915 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 916 static u64 construct_eptp(unsigned long root_hpa);
 917 static void kvm_cpu_vmxon(u64 addr);
 918 static void kvm_cpu_vmxoff(void);
 919 static bool vmx_xsaves_supported(void);
 920 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 921 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 922                             struct kvm_segment *var, int seg);
 923 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 924                             struct kvm_segment *var, int seg);
 925 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 926 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 927 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 928 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 929 static int alloc_identity_pagetable(struct kvm *kvm);
 930
 931 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 932 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 933 /*
 934  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 935  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 936  */
 937 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 938 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 939
 940 /*
 941  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 942  * can find which vCPU should be waken up.
 943  */
 944 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 945 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 946
 947 enum {
 948         VMX_IO_BITMAP_A,
 949         VMX_IO_BITMAP_B,
 950         VMX_MSR_BITMAP_LEGACY,
 951         VMX_MSR_BITMAP_LONGMODE,
 952         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 953         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 954         VMX_MSR_BITMAP_LEGACY_X2APIC,
 955         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 956         VMX_VMREAD_BITMAP,
 957         VMX_VMWRITE_BITMAP,
 958         VMX_BITMAP_NR
 959 };
 960
 961 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 962
 963 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 964 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 965 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 966 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 967 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 968 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 969 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 970 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 971 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 972 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 973
 974 static bool cpu_has_load_ia32_efer;
 975 static bool cpu_has_load_perf_global_ctrl;
 976
 977 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 978 static DEFINE_SPINLOCK(vmx_vpid_lock);
 979
 980 static struct vmcs_config {
 981         int size;
 982         int order;
 983         u32 basic_cap;
 984         u32 revision_id;
 985         u32 pin_based_exec_ctrl;
 986         u32 cpu_based_exec_ctrl;
 987         u32 cpu_based_2nd_exec_ctrl;
 988         u32 vmexit_ctrl;
 989         u32 vmentry_ctrl;
 990 } vmcs_config;
 991
 992 static struct vmx_capability {
 993         u32 ept;
 994         u32 vpid;
 995 } vmx_capability;
 996
 997 #define VMX_SEGMENT_FIELD(seg)                                  \
 998         [VCPU_SREG_##seg] = {                                   \
 999                 .selector = GUEST_##seg##_SELECTOR,             \
1000                 .base = GUEST_##seg##_BASE,                     \
1001                 .limit = GUEST_##seg##_LIMIT,                   \
1002                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1003         }
1004
1005 static const struct kvm_vmx_segment_field {
1006         unsigned selector;
1007         unsigned base;
1008         unsigned limit;
1009         unsigned ar_bytes;
1010 } kvm_vmx_segment_fields[] = {
1011         VMX_SEGMENT_FIELD(CS),
1012         VMX_SEGMENT_FIELD(DS),
1013         VMX_SEGMENT_FIELD(ES),
1014         VMX_SEGMENT_FIELD(FS),
1015         VMX_SEGMENT_FIELD(GS),
1016         VMX_SEGMENT_FIELD(SS),
1017         VMX_SEGMENT_FIELD(TR),
1018         VMX_SEGMENT_FIELD(LDTR),
1019 };
1020
1021 static u64 host_efer;
1022
1023 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1024
1025 /*
1026  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1027  * away by decrementing the array size.
1028  */
1029 static const u32 vmx_msr_index[] = {
1030 #ifdef CONFIG_X86_64
1031         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1032 #endif
1033         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1034 };
1035
1036 static inline bool is_exception_n(u32 intr_info, u8 vector)
1037 {
1038         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1039                              INTR_INFO_VALID_MASK)) ==
1040                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1041 }
1042
1043 static inline bool is_debug(u32 intr_info)
1044 {
1045         return is_exception_n(intr_info, DB_VECTOR);
1046 }
1047
1048 static inline bool is_breakpoint(u32 intr_info)
1049 {
1050         return is_exception_n(intr_info, BP_VECTOR);
1051 }
1052
1053 static inline bool is_page_fault(u32 intr_info)
1054 {
1055         return is_exception_n(intr_info, PF_VECTOR);
1056 }
1057
1058 static inline bool is_no_device(u32 intr_info)
1059 {
1060         return is_exception_n(intr_info, NM_VECTOR);
1061 }
1062
1063 static inline bool is_invalid_opcode(u32 intr_info)
1064 {
1065         return is_exception_n(intr_info, UD_VECTOR);
1066 }
1067
1068 static inline bool is_external_interrupt(u32 intr_info)
1069 {
1070         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1071                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1072 }
1073
1074 static inline bool is_machine_check(u32 intr_info)
1075 {
1076         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1077                              INTR_INFO_VALID_MASK)) ==
1078                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1079 }
1080
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1082 {
1083         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1084 }
1085
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1087 {
1088         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1089 }
1090
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1092 {
1093         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1094 }
1095
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1097 {
1098         return vmcs_config.cpu_based_exec_ctrl &
1099                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1100 }
1101
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1103 {
1104         return vmcs_config.cpu_based_2nd_exec_ctrl &
1105                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1106 }
1107
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1109 {
1110         return vmcs_config.cpu_based_2nd_exec_ctrl &
1111                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1112 }
1113
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1115 {
1116         return vmcs_config.cpu_based_2nd_exec_ctrl &
1117                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1118 }
1119
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1121 {
1122         return vmcs_config.cpu_based_2nd_exec_ctrl &
1123                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1124 }
1125
1126 /*
1127  * Comment's format: document - errata name - stepping - processor name.
1128  * Refer from
1129  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1130  */
1131 static u32 vmx_preemption_cpu_tfms[] = {
1132 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1133 0x000206E6,
1134 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 0x00020652,
1138 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1139 0x00020655,
1140 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1142 /*
1143  * 320767.pdf - AAP86  - B1 -
1144  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1145  */
1146 0x000106E5,
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1148 0x000106A0,
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1150 0x000106A1,
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1152 0x000106A4,
1153  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1156 0x000106A5,
1157 };
1158
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1160 {
1161         u32 eax = cpuid_eax(0x00000001), i;
1162
1163         /* Clear the reserved bits */
1164         eax &= ~(0x3U << 14 | 0xfU << 28);
1165         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1166                 if (eax == vmx_preemption_cpu_tfms[i])
1167                         return true;
1168
1169         return false;
1170 }
1171
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1173 {
1174         return vmcs_config.pin_based_exec_ctrl &
1175                 PIN_BASED_VMX_PREEMPTION_TIMER;
1176 }
1177
1178 static inline bool cpu_has_vmx_posted_intr(void)
1179 {
1180         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1181                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1182 }
1183
1184 static inline bool cpu_has_vmx_apicv(void)
1185 {
1186         return cpu_has_vmx_apic_register_virt() &&
1187                 cpu_has_vmx_virtual_intr_delivery() &&
1188                 cpu_has_vmx_posted_intr();
1189 }
1190
1191 static inline bool cpu_has_vmx_flexpriority(void)
1192 {
1193         return cpu_has_vmx_tpr_shadow() &&
1194                 cpu_has_vmx_virtualize_apic_accesses();
1195 }
1196
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1198 {
1199         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1200 }
1201
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1203 {
1204         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1205 }
1206
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1208 {
1209         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1210 }
1211
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1213 {
1214         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1215 }
1216
1217 static inline bool cpu_has_vmx_ept_ad_bits(void)
1218 {
1219         return vmx_capability.ept & VMX_EPT_AD_BIT;
1220 }
1221
1222 static inline bool cpu_has_vmx_invept_context(void)
1223 {
1224         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1225 }
1226
1227 static inline bool cpu_has_vmx_invept_global(void)
1228 {
1229         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1230 }
1231
1232 static inline bool cpu_has_vmx_invvpid_single(void)
1233 {
1234         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1235 }
1236
1237 static inline bool cpu_has_vmx_invvpid_global(void)
1238 {
1239         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1240 }
1241
1242 static inline bool cpu_has_vmx_invvpid(void)
1243 {
1244         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1245 }
1246
1247 static inline bool cpu_has_vmx_ept(void)
1248 {
1249         return vmcs_config.cpu_based_2nd_exec_ctrl &
1250                 SECONDARY_EXEC_ENABLE_EPT;
1251 }
1252
1253 static inline bool cpu_has_vmx_unrestricted_guest(void)
1254 {
1255         return vmcs_config.cpu_based_2nd_exec_ctrl &
1256                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1257 }
1258
1259 static inline bool cpu_has_vmx_ple(void)
1260 {
1261         return vmcs_config.cpu_based_2nd_exec_ctrl &
1262                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1263 }
1264
1265 static inline bool cpu_has_vmx_basic_inout(void)
1266 {
1267         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1268 }
1269
1270 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1271 {
1272         return flexpriority_enabled && lapic_in_kernel(vcpu);
1273 }
1274
1275 static inline bool cpu_has_vmx_vpid(void)
1276 {
1277         return vmcs_config.cpu_based_2nd_exec_ctrl &
1278                 SECONDARY_EXEC_ENABLE_VPID;
1279 }
1280
1281 static inline bool cpu_has_vmx_rdtscp(void)
1282 {
1283         return vmcs_config.cpu_based_2nd_exec_ctrl &
1284                 SECONDARY_EXEC_RDTSCP;
1285 }
1286
1287 static inline bool cpu_has_vmx_invpcid(void)
1288 {
1289         return vmcs_config.cpu_based_2nd_exec_ctrl &
1290                 SECONDARY_EXEC_ENABLE_INVPCID;
1291 }
1292
1293 static inline bool cpu_has_virtual_nmis(void)
1294 {
1295         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1296 }
1297
1298 static inline bool cpu_has_vmx_wbinvd_exit(void)
1299 {
1300         return vmcs_config.cpu_based_2nd_exec_ctrl &
1301                 SECONDARY_EXEC_WBINVD_EXITING;
1302 }
1303
1304 static inline bool cpu_has_vmx_shadow_vmcs(void)
1305 {
1306         u64 vmx_msr;
1307         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1308         /* check if the cpu supports writing r/o exit information fields */
1309         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1310                 return false;
1311
1312         return vmcs_config.cpu_based_2nd_exec_ctrl &
1313                 SECONDARY_EXEC_SHADOW_VMCS;
1314 }
1315
1316 static inline bool cpu_has_vmx_pml(void)
1317 {
1318         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1319 }
1320
1321 static inline bool cpu_has_vmx_tsc_scaling(void)
1322 {
1323         return vmcs_config.cpu_based_2nd_exec_ctrl &
1324                 SECONDARY_EXEC_TSC_SCALING;
1325 }
1326
1327 static inline bool report_flexpriority(void)
1328 {
1329         return flexpriority_enabled;
1330 }
1331
1332 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1333 {
1334         return vmcs12->cpu_based_vm_exec_control & bit;
1335 }
1336
1337 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1338 {
1339         return (vmcs12->cpu_based_vm_exec_control &
1340                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1341                 (vmcs12->secondary_vm_exec_control & bit);
1342 }
1343
1344 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1345 {
1346         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1347 }
1348
1349 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1350 {
1351         return vmcs12->pin_based_vm_exec_control &
1352                 PIN_BASED_VMX_PREEMPTION_TIMER;
1353 }
1354
1355 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1356 {
1357         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1358 }
1359
1360 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1361 {
1362         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1363                 vmx_xsaves_supported();
1364 }
1365
1366 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1367 {
1368         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1369 }
1370
1371 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1372 {
1373         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1374 }
1375
1376 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1377 {
1378         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1379 }
1380
1381 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1382 {
1383         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1384 }
1385
1386 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1387 {
1388         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1389 }
1390
1391 static inline bool is_nmi(u32 intr_info)
1392 {
1393         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1394                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1395 }
1396
1397 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1398                               u32 exit_intr_info,
1399                               unsigned long exit_qualification);
1400 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1401                         struct vmcs12 *vmcs12,
1402                         u32 reason, unsigned long qualification);
1403
1404 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1405 {
1406         int i;
1407
1408         for (i = 0; i < vmx->nmsrs; ++i)
1409                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1410                         return i;
1411         return -1;
1412 }
1413
1414 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1415 {
1416     struct {
1417         u64 vpid : 16;
1418         u64 rsvd : 48;
1419         u64 gva;
1420     } operand = { vpid, 0, gva };
1421
1422     asm volatile (__ex(ASM_VMX_INVVPID)
1423                   /* CF==1 or ZF==1 --> rc = -1 */
1424                   "; ja 1f ; ud2 ; 1:"
1425                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1426 }
1427
1428 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1429 {
1430         struct {
1431                 u64 eptp, gpa;
1432         } operand = {eptp, gpa};
1433
1434         asm volatile (__ex(ASM_VMX_INVEPT)
1435                         /* CF==1 or ZF==1 --> rc = -1 */
1436                         "; ja 1f ; ud2 ; 1:\n"
1437                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1438 }
1439
1440 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1441 {
1442         int i;
1443
1444         i = __find_msr_index(vmx, msr);
1445         if (i >= 0)
1446                 return &vmx->guest_msrs[i];
1447         return NULL;
1448 }
1449
1450 static void vmcs_clear(struct vmcs *vmcs)
1451 {
1452         u64 phys_addr = __pa(vmcs);
1453         u8 error;
1454
1455         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1456                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1457                       : "cc", "memory");
1458         if (error)
1459                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1460                        vmcs, phys_addr);
1461 }
1462
1463 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1464 {
1465         vmcs_clear(loaded_vmcs->vmcs);
1466         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1467                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1468         loaded_vmcs->cpu = -1;
1469         loaded_vmcs->launched = 0;
1470 }
1471
1472 static void vmcs_load(struct vmcs *vmcs)
1473 {
1474         u64 phys_addr = __pa(vmcs);
1475         u8 error;
1476
1477         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1478                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1479                         : "cc", "memory");
1480         if (error)
1481                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1482                        vmcs, phys_addr);
1483 }
1484
1485 #ifdef CONFIG_KEXEC_CORE
1486 /*
1487  * This bitmap is used to indicate whether the vmclear
1488  * operation is enabled on all cpus. All disabled by
1489  * default.
1490  */
1491 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1492
1493 static inline void crash_enable_local_vmclear(int cpu)
1494 {
1495         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1496 }
1497
1498 static inline void crash_disable_local_vmclear(int cpu)
1499 {
1500         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1501 }
1502
1503 static inline int crash_local_vmclear_enabled(int cpu)
1504 {
1505         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1506 }
1507
1508 static void crash_vmclear_local_loaded_vmcss(void)
1509 {
1510         int cpu = raw_smp_processor_id();
1511         struct loaded_vmcs *v;
1512
1513         if (!crash_local_vmclear_enabled(cpu))
1514                 return;
1515
1516         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1517                             loaded_vmcss_on_cpu_link)
1518                 vmcs_clear(v->vmcs);
1519 }
1520 #else
1521 static inline void crash_enable_local_vmclear(int cpu) { }
1522 static inline void crash_disable_local_vmclear(int cpu) { }
1523 #endif /* CONFIG_KEXEC_CORE */
1524
1525 static void __loaded_vmcs_clear(void *arg)
1526 {
1527         struct loaded_vmcs *loaded_vmcs = arg;
1528         int cpu = raw_smp_processor_id();
1529
1530         if (loaded_vmcs->cpu != cpu)
1531                 return; /* vcpu migration can race with cpu offline */
1532         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1533                 per_cpu(current_vmcs, cpu) = NULL;
1534         crash_disable_local_vmclear(cpu);
1535         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1536
1537         /*
1538          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1539          * is before setting loaded_vmcs->vcpu to -1 which is done in
1540          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1541          * then adds the vmcs into percpu list before it is deleted.
1542          */
1543         smp_wmb();
1544
1545         loaded_vmcs_init(loaded_vmcs);
1546         crash_enable_local_vmclear(cpu);
1547 }
1548
1549 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1550 {
1551         int cpu = loaded_vmcs->cpu;
1552
1553         if (cpu != -1)
1554                 smp_call_function_single(cpu,
1555                          __loaded_vmcs_clear, loaded_vmcs, 1);
1556 }
1557
1558 static inline void vpid_sync_vcpu_single(int vpid)
1559 {
1560         if (vpid == 0)
1561                 return;
1562
1563         if (cpu_has_vmx_invvpid_single())
1564                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1565 }
1566
1567 static inline void vpid_sync_vcpu_global(void)
1568 {
1569         if (cpu_has_vmx_invvpid_global())
1570                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1571 }
1572
1573 static inline void vpid_sync_context(int vpid)
1574 {
1575         if (cpu_has_vmx_invvpid_single())
1576                 vpid_sync_vcpu_single(vpid);
1577         else
1578                 vpid_sync_vcpu_global();
1579 }
1580
1581 static inline void ept_sync_global(void)
1582 {
1583         if (cpu_has_vmx_invept_global())
1584                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1585 }
1586
1587 static inline void ept_sync_context(u64 eptp)
1588 {
1589         if (enable_ept) {
1590                 if (cpu_has_vmx_invept_context())
1591                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1592                 else
1593                         ept_sync_global();
1594         }
1595 }
1596
1597 static __always_inline void vmcs_check16(unsigned long field)
1598 {
1599         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1600                          "16-bit accessor invalid for 64-bit field");
1601         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1602                          "16-bit accessor invalid for 64-bit high field");
1603         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1604                          "16-bit accessor invalid for 32-bit high field");
1605         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1606                          "16-bit accessor invalid for natural width field");
1607 }
1608
1609 static __always_inline void vmcs_check32(unsigned long field)
1610 {
1611         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1612                          "32-bit accessor invalid for 16-bit field");
1613         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1614                          "32-bit accessor invalid for natural width field");
1615 }
1616
1617 static __always_inline void vmcs_check64(unsigned long field)
1618 {
1619         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1620                          "64-bit accessor invalid for 16-bit field");
1621         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1622                          "64-bit accessor invalid for 64-bit high field");
1623         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1624                          "64-bit accessor invalid for 32-bit field");
1625         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1626                          "64-bit accessor invalid for natural width field");
1627 }
1628
1629 static __always_inline void vmcs_checkl(unsigned long field)
1630 {
1631         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1632                          "Natural width accessor invalid for 16-bit field");
1633         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1634                          "Natural width accessor invalid for 64-bit field");
1635         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1636                          "Natural width accessor invalid for 64-bit high field");
1637         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1638                          "Natural width accessor invalid for 32-bit field");
1639 }
1640
1641 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1642 {
1643         unsigned long value;
1644
1645         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1646                       : "=a"(value) : "d"(field) : "cc");
1647         return value;
1648 }
1649
1650 static __always_inline u16 vmcs_read16(unsigned long field)
1651 {
1652         vmcs_check16(field);
1653         return __vmcs_readl(field);
1654 }
1655
1656 static __always_inline u32 vmcs_read32(unsigned long field)
1657 {
1658         vmcs_check32(field);
1659         return __vmcs_readl(field);
1660 }
1661
1662 static __always_inline u64 vmcs_read64(unsigned long field)
1663 {
1664         vmcs_check64(field);
1665 #ifdef CONFIG_X86_64
1666         return __vmcs_readl(field);
1667 #else
1668         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1669 #endif
1670 }
1671
1672 static __always_inline unsigned long vmcs_readl(unsigned long field)
1673 {
1674         vmcs_checkl(field);
1675         return __vmcs_readl(field);
1676 }
1677
1678 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1679 {
1680         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1681                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1682         dump_stack();
1683 }
1684
1685 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1686 {
1687         u8 error;
1688
1689         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1690                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1691         if (unlikely(error))
1692                 vmwrite_error(field, value);
1693 }
1694
1695 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1696 {
1697         vmcs_check16(field);
1698         __vmcs_writel(field, value);
1699 }
1700
1701 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1702 {
1703         vmcs_check32(field);
1704         __vmcs_writel(field, value);
1705 }
1706
1707 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1708 {
1709         vmcs_check64(field);
1710         __vmcs_writel(field, value);
1711 #ifndef CONFIG_X86_64
1712         asm volatile ("");
1713         __vmcs_writel(field+1, value >> 32);
1714 #endif
1715 }
1716
1717 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1718 {
1719         vmcs_checkl(field);
1720         __vmcs_writel(field, value);
1721 }
1722
1723 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1724 {
1725         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1726                          "vmcs_clear_bits does not support 64-bit fields");
1727         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1728 }
1729
1730 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1731 {
1732         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1733                          "vmcs_set_bits does not support 64-bit fields");
1734         __vmcs_writel(field, __vmcs_readl(field) | mask);
1735 }
1736
1737 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1738 {
1739         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1740 }
1741
1742 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1743 {
1744         vmcs_write32(VM_ENTRY_CONTROLS, val);
1745         vmx->vm_entry_controls_shadow = val;
1746 }
1747
1748 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1749 {
1750         if (vmx->vm_entry_controls_shadow != val)
1751                 vm_entry_controls_init(vmx, val);
1752 }
1753
1754 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1755 {
1756         return vmx->vm_entry_controls_shadow;
1757 }
1758
1759
1760 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1761 {
1762         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1763 }
1764
1765 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1766 {
1767         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1768 }
1769
1770 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1771 {
1772         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1773 }
1774
1775 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1776 {
1777         vmcs_write32(VM_EXIT_CONTROLS, val);
1778         vmx->vm_exit_controls_shadow = val;
1779 }
1780
1781 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1782 {
1783         if (vmx->vm_exit_controls_shadow != val)
1784                 vm_exit_controls_init(vmx, val);
1785 }
1786
1787 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1788 {
1789         return vmx->vm_exit_controls_shadow;
1790 }
1791
1792
1793 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1794 {
1795         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1796 }
1797
1798 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1799 {
1800         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1801 }
1802
1803 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1804 {
1805         vmx->segment_cache.bitmask = 0;
1806 }
1807
1808 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1809                                        unsigned field)
1810 {
1811         bool ret;
1812         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1813
1814         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1815                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1816                 vmx->segment_cache.bitmask = 0;
1817         }
1818         ret = vmx->segment_cache.bitmask & mask;
1819         vmx->segment_cache.bitmask |= mask;
1820         return ret;
1821 }
1822
1823 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1824 {
1825         u16 *p = &vmx->segment_cache.seg[seg].selector;
1826
1827         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1828                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1829         return *p;
1830 }
1831
1832 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1833 {
1834         ulong *p = &vmx->segment_cache.seg[seg].base;
1835
1836         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1837                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1838         return *p;
1839 }
1840
1841 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1842 {
1843         u32 *p = &vmx->segment_cache.seg[seg].limit;
1844
1845         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1846                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1847         return *p;
1848 }
1849
1850 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1851 {
1852         u32 *p = &vmx->segment_cache.seg[seg].ar;
1853
1854         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1855                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1856         return *p;
1857 }
1858
1859 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1860 {
1861         u32 eb;
1862
1863         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1864              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1865         if ((vcpu->guest_debug &
1866              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1867             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1868                 eb |= 1u << BP_VECTOR;
1869         if (to_vmx(vcpu)->rmode.vm86_active)
1870                 eb = ~0;
1871         if (enable_ept)
1872                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1873
1874         /* When we are running a nested L2 guest and L1 specified for it a
1875          * certain exception bitmap, we must trap the same exceptions and pass
1876          * them to L1. When running L2, we will only handle the exceptions
1877          * specified above if L1 did not want them.
1878          */
1879         if (is_guest_mode(vcpu))
1880                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1881
1882         vmcs_write32(EXCEPTION_BITMAP, eb);
1883 }
1884
1885 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1886                 unsigned long entry, unsigned long exit)
1887 {
1888         vm_entry_controls_clearbit(vmx, entry);
1889         vm_exit_controls_clearbit(vmx, exit);
1890 }
1891
1892 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1893 {
1894         unsigned i;
1895         struct msr_autoload *m = &vmx->msr_autoload;
1896
1897         switch (msr) {
1898         case MSR_EFER:
1899                 if (cpu_has_load_ia32_efer) {
1900                         clear_atomic_switch_msr_special(vmx,
1901                                         VM_ENTRY_LOAD_IA32_EFER,
1902                                         VM_EXIT_LOAD_IA32_EFER);
1903                         return;
1904                 }
1905                 break;
1906         case MSR_CORE_PERF_GLOBAL_CTRL:
1907                 if (cpu_has_load_perf_global_ctrl) {
1908                         clear_atomic_switch_msr_special(vmx,
1909                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1910                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1911                         return;
1912                 }
1913                 break;
1914         }
1915
1916         for (i = 0; i < m->nr; ++i)
1917                 if (m->guest[i].index == msr)
1918                         break;
1919
1920         if (i == m->nr)
1921                 return;
1922         --m->nr;
1923         m->guest[i] = m->guest[m->nr];
1924         m->host[i] = m->host[m->nr];
1925         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1926         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1927 }
1928
1929 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1930                 unsigned long entry, unsigned long exit,
1931                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1932                 u64 guest_val, u64 host_val)
1933 {
1934         vmcs_write64(guest_val_vmcs, guest_val);
1935         vmcs_write64(host_val_vmcs, host_val);
1936         vm_entry_controls_setbit(vmx, entry);
1937         vm_exit_controls_setbit(vmx, exit);
1938 }
1939
1940 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1941                                   u64 guest_val, u64 host_val)
1942 {
1943         unsigned i;
1944         struct msr_autoload *m = &vmx->msr_autoload;
1945
1946         switch (msr) {
1947         case MSR_EFER:
1948                 if (cpu_has_load_ia32_efer) {
1949                         add_atomic_switch_msr_special(vmx,
1950                                         VM_ENTRY_LOAD_IA32_EFER,
1951                                         VM_EXIT_LOAD_IA32_EFER,
1952                                         GUEST_IA32_EFER,
1953                                         HOST_IA32_EFER,
1954                                         guest_val, host_val);
1955                         return;
1956                 }
1957                 break;
1958         case MSR_CORE_PERF_GLOBAL_CTRL:
1959                 if (cpu_has_load_perf_global_ctrl) {
1960                         add_atomic_switch_msr_special(vmx,
1961                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1962                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1963                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1964                                         HOST_IA32_PERF_GLOBAL_CTRL,
1965                                         guest_val, host_val);
1966                         return;
1967                 }
1968                 break;
1969         case MSR_IA32_PEBS_ENABLE:
1970                 /* PEBS needs a quiescent period after being disabled (to write
1971                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1972                  * provide that period, so a CPU could write host's record into
1973                  * guest's memory.
1974                  */
1975                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1976         }
1977
1978         for (i = 0; i < m->nr; ++i)
1979                 if (m->guest[i].index == msr)
1980                         break;
1981
1982         if (i == NR_AUTOLOAD_MSRS) {
1983                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1984                                 "Can't add msr %x\n", msr);
1985                 return;
1986         } else if (i == m->nr) {
1987                 ++m->nr;
1988                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1989                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1990         }
1991
1992         m->guest[i].index = msr;
1993         m->guest[i].value = guest_val;
1994         m->host[i].index = msr;
1995         m->host[i].value = host_val;
1996 }
1997
1998 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1999 {
2000         u64 guest_efer = vmx->vcpu.arch.efer;
2001         u64 ignore_bits = 0;
2002
2003         if (!enable_ept) {
2004                 /*
2005                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2006                  * host CPUID is more efficient than testing guest CPUID
2007                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2008                  */
2009                 if (boot_cpu_has(X86_FEATURE_SMEP))
2010                         guest_efer |= EFER_NX;
2011                 else if (!(guest_efer & EFER_NX))
2012                         ignore_bits |= EFER_NX;
2013         }
2014
2015         /*
2016          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2017          */
2018         ignore_bits |= EFER_SCE;
2019 #ifdef CONFIG_X86_64
2020         ignore_bits |= EFER_LMA | EFER_LME;
2021         /* SCE is meaningful only in long mode on Intel */
2022         if (guest_efer & EFER_LMA)
2023                 ignore_bits &= ~(u64)EFER_SCE;
2024 #endif
2025
2026         clear_atomic_switch_msr(vmx, MSR_EFER);
2027
2028         /*
2029          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2030          * On CPUs that support "load IA32_EFER", always switch EFER
2031          * atomically, since it's faster than switching it manually.
2032          */
2033         if (cpu_has_load_ia32_efer ||
2034             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2035                 if (!(guest_efer & EFER_LMA))
2036                         guest_efer &= ~EFER_LME;
2037                 if (guest_efer != host_efer)
2038                         add_atomic_switch_msr(vmx, MSR_EFER,
2039                                               guest_efer, host_efer);
2040                 return false;
2041         } else {
2042                 guest_efer &= ~ignore_bits;
2043                 guest_efer |= host_efer & ignore_bits;
2044
2045                 vmx->guest_msrs[efer_offset].data = guest_efer;
2046                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2047
2048                 return true;
2049         }
2050 }
2051
2052 #ifdef CONFIG_X86_32
2053 /*
2054  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2055  * VMCS rather than the segment table.  KVM uses this helper to figure
2056  * out the current bases to poke them into the VMCS before entry.
2057  */
2058 static unsigned long segment_base(u16 selector)
2059 {
2060         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2061         struct desc_struct *table;
2062         unsigned long v;
2063
2064         if (!(selector & ~SEGMENT_RPL_MASK))
2065                 return 0;
2066
2067         table = (struct desc_struct *)gdt->address;
2068
2069         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2070                 u16 ldt_selector = kvm_read_ldt();
2071
2072                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2073                         return 0;
2074
2075                 table = (struct desc_struct *)segment_base(ldt_selector);
2076         }
2077         v = get_desc_base(&table[selector >> 3]);
2078         return v;
2079 }
2080 #endif
2081
2082 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2083 {
2084         struct vcpu_vmx *vmx = to_vmx(vcpu);
2085         int i;
2086
2087         if (vmx->host_state.loaded)
2088                 return;
2089
2090         vmx->host_state.loaded = 1;
2091         /*
2092          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2093          * allow segment selectors with cpl > 0 or ti == 1.
2094          */
2095         vmx->host_state.ldt_sel = kvm_read_ldt();
2096         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2097         savesegment(fs, vmx->host_state.fs_sel);
2098         if (!(vmx->host_state.fs_sel & 7)) {
2099                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2100                 vmx->host_state.fs_reload_needed = 0;
2101         } else {
2102                 vmcs_write16(HOST_FS_SELECTOR, 0);
2103                 vmx->host_state.fs_reload_needed = 1;
2104         }
2105         savesegment(gs, vmx->host_state.gs_sel);
2106         if (!(vmx->host_state.gs_sel & 7))
2107                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2108         else {
2109                 vmcs_write16(HOST_GS_SELECTOR, 0);
2110                 vmx->host_state.gs_ldt_reload_needed = 1;
2111         }
2112
2113 #ifdef CONFIG_X86_64
2114         savesegment(ds, vmx->host_state.ds_sel);
2115         savesegment(es, vmx->host_state.es_sel);
2116 #endif
2117
2118 #ifdef CONFIG_X86_64
2119         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2120         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2121 #else
2122         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2123         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2124 #endif
2125
2126 #ifdef CONFIG_X86_64
2127         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2128         if (is_long_mode(&vmx->vcpu))
2129                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2130 #endif
2131         if (boot_cpu_has(X86_FEATURE_MPX))
2132                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2133         for (i = 0; i < vmx->save_nmsrs; ++i)
2134                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2135                                    vmx->guest_msrs[i].data,
2136                                    vmx->guest_msrs[i].mask);
2137 }
2138
2139 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2140 {
2141         if (!vmx->host_state.loaded)
2142                 return;
2143
2144         ++vmx->vcpu.stat.host_state_reload;
2145         vmx->host_state.loaded = 0;
2146 #ifdef CONFIG_X86_64
2147         if (is_long_mode(&vmx->vcpu))
2148                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2149 #endif
2150         if (vmx->host_state.gs_ldt_reload_needed) {
2151                 kvm_load_ldt(vmx->host_state.ldt_sel);
2152 #ifdef CONFIG_X86_64
2153                 load_gs_index(vmx->host_state.gs_sel);
2154 #else
2155                 loadsegment(gs, vmx->host_state.gs_sel);
2156 #endif
2157         }
2158         if (vmx->host_state.fs_reload_needed)
2159                 loadsegment(fs, vmx->host_state.fs_sel);
2160 #ifdef CONFIG_X86_64
2161         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2162                 loadsegment(ds, vmx->host_state.ds_sel);
2163                 loadsegment(es, vmx->host_state.es_sel);
2164         }
2165 #endif
2166         invalidate_tss_limit();
2167 #ifdef CONFIG_X86_64
2168         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2169 #endif
2170         if (vmx->host_state.msr_host_bndcfgs)
2171                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2172         load_gdt(this_cpu_ptr(&host_gdt));
2173 }
2174
2175 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2176 {
2177         preempt_disable();
2178         __vmx_load_host_state(vmx);
2179         preempt_enable();
2180 }
2181
2182 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2183 {
2184         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2185         struct pi_desc old, new;
2186         unsigned int dest;
2187
2188         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2189                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2190                 !kvm_vcpu_apicv_active(vcpu))
2191                 return;
2192
2193         do {
2194                 old.control = new.control = pi_desc->control;
2195
2196                 /*
2197                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2198                  * are two possible cases:
2199                  * 1. After running 'pre_block', context switch
2200                  *    happened. For this case, 'sn' was set in
2201                  *    vmx_vcpu_put(), so we need to clear it here.
2202                  * 2. After running 'pre_block', we were blocked,
2203                  *    and woken up by some other guy. For this case,
2204                  *    we don't need to do anything, 'pi_post_block'
2205                  *    will do everything for us. However, we cannot
2206                  *    check whether it is case #1 or case #2 here
2207                  *    (maybe, not needed), so we also clear sn here,
2208                  *    I think it is not a big deal.
2209                  */
2210                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2211                         if (vcpu->cpu != cpu) {
2212                                 dest = cpu_physical_id(cpu);
2213
2214                                 if (x2apic_enabled())
2215                                         new.ndst = dest;
2216                                 else
2217                                         new.ndst = (dest << 8) & 0xFF00;
2218                         }
2219
2220                         /* set 'NV' to 'notification vector' */
2221                         new.nv = POSTED_INTR_VECTOR;
2222                 }
2223
2224                 /* Allow posting non-urgent interrupts */
2225                 new.sn = 0;
2226         } while (cmpxchg(&pi_desc->control, old.control,
2227                         new.control) != old.control);
2228 }
2229
2230 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2231 {
2232         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2233         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2234 }
2235
2236 /*
2237  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2238  * vcpu mutex is already taken.
2239  */
2240 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2241 {
2242         struct vcpu_vmx *vmx = to_vmx(vcpu);
2243         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2244         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2245
2246         if (!vmm_exclusive)
2247                 kvm_cpu_vmxon(phys_addr);
2248         else if (!already_loaded)
2249                 loaded_vmcs_clear(vmx->loaded_vmcs);
2250
2251         if (!already_loaded) {
2252                 local_irq_disable();
2253                 crash_disable_local_vmclear(cpu);
2254
2255                 /*
2256                  * Read loaded_vmcs->cpu should be before fetching
2257                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2258                  * See the comments in __loaded_vmcs_clear().
2259                  */
2260                 smp_rmb();
2261
2262                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2263                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2264                 crash_enable_local_vmclear(cpu);
2265                 local_irq_enable();
2266         }
2267
2268         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2269                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2270                 vmcs_load(vmx->loaded_vmcs->vmcs);
2271         }
2272
2273         if (!already_loaded) {
2274                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2275                 unsigned long sysenter_esp;
2276
2277                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2278
2279                 /*
2280                  * Linux uses per-cpu TSS and GDT, so set these when switching
2281                  * processors.  See 22.2.4.
2282                  */
2283                 vmcs_writel(HOST_TR_BASE,
2284                             (unsigned long)this_cpu_ptr(&cpu_tss));
2285                 vmcs_writel(HOST_GDTR_BASE, gdt->address);
2286
2287                 /*
2288                  * VM exits change the host TR limit to 0x67 after a VM
2289                  * exit.  This is okay, since 0x67 covers everything except
2290                  * the IO bitmap and have have code to handle the IO bitmap
2291                  * being lost after a VM exit.
2292                  */
2293                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2294
2295                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2296                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2297
2298                 vmx->loaded_vmcs->cpu = cpu;
2299         }
2300
2301         /* Setup TSC multiplier */
2302         if (kvm_has_tsc_control &&
2303             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2304                 decache_tsc_multiplier(vmx);
2305
2306         vmx_vcpu_pi_load(vcpu, cpu);
2307         vmx->host_pkru = read_pkru();
2308 }
2309
2310 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2311 {
2312         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2313
2314         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2315                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2316                 !kvm_vcpu_apicv_active(vcpu))
2317                 return;
2318
2319         /* Set SN when the vCPU is preempted */
2320         if (vcpu->preempted)
2321                 pi_set_sn(pi_desc);
2322 }
2323
2324 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2325 {
2326         vmx_vcpu_pi_put(vcpu);
2327
2328         __vmx_load_host_state(to_vmx(vcpu));
2329         if (!vmm_exclusive) {
2330                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2331                 vcpu->cpu = -1;
2332                 kvm_cpu_vmxoff();
2333         }
2334 }
2335
2336 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2337
2338 /*
2339  * Return the cr0 value that a nested guest would read. This is a combination
2340  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2341  * its hypervisor (cr0_read_shadow).
2342  */
2343 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2344 {
2345         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2346                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2347 }
2348 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2349 {
2350         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2351                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2352 }
2353
2354 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2355 {
2356         unsigned long rflags, save_rflags;
2357
2358         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2359                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2360                 rflags = vmcs_readl(GUEST_RFLAGS);
2361                 if (to_vmx(vcpu)->rmode.vm86_active) {
2362                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2363                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2364                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2365                 }
2366                 to_vmx(vcpu)->rflags = rflags;
2367         }
2368         return to_vmx(vcpu)->rflags;
2369 }
2370
2371 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2372 {
2373         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2374         to_vmx(vcpu)->rflags = rflags;
2375         if (to_vmx(vcpu)->rmode.vm86_active) {
2376                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2377                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2378         }
2379         vmcs_writel(GUEST_RFLAGS, rflags);
2380 }
2381
2382 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2383 {
2384         return to_vmx(vcpu)->guest_pkru;
2385 }
2386
2387 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2388 {
2389         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2390         int ret = 0;
2391
2392         if (interruptibility & GUEST_INTR_STATE_STI)
2393                 ret |= KVM_X86_SHADOW_INT_STI;
2394         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2395                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2396
2397         return ret;
2398 }
2399
2400 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2401 {
2402         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2403         u32 interruptibility = interruptibility_old;
2404
2405         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2406
2407         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2408                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2409         else if (mask & KVM_X86_SHADOW_INT_STI)
2410                 interruptibility |= GUEST_INTR_STATE_STI;
2411
2412         if ((interruptibility != interruptibility_old))
2413                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2414 }
2415
2416 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2417 {
2418         unsigned long rip;
2419
2420         rip = kvm_rip_read(vcpu);
2421         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2422         kvm_rip_write(vcpu, rip);
2423
2424         /* skipping an emulated instruction also counts */
2425         vmx_set_interrupt_shadow(vcpu, 0);
2426 }
2427
2428 /*
2429  * KVM wants to inject page-faults which it got to the guest. This function
2430  * checks whether in a nested guest, we need to inject them to L1 or L2.
2431  */
2432 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2433 {
2434         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2435
2436         if (!(vmcs12->exception_bitmap & (1u << nr)))
2437                 return 0;
2438
2439         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2440                           vmcs_read32(VM_EXIT_INTR_INFO),
2441                           vmcs_readl(EXIT_QUALIFICATION));
2442         return 1;
2443 }
2444
2445 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2446                                 bool has_error_code, u32 error_code,
2447                                 bool reinject)
2448 {
2449         struct vcpu_vmx *vmx = to_vmx(vcpu);
2450         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2451
2452         if (!reinject && is_guest_mode(vcpu) &&
2453             nested_vmx_check_exception(vcpu, nr))
2454                 return;
2455
2456         if (has_error_code) {
2457                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2458                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2459         }
2460
2461         if (vmx->rmode.vm86_active) {
2462                 int inc_eip = 0;
2463                 if (kvm_exception_is_soft(nr))
2464                         inc_eip = vcpu->arch.event_exit_inst_len;
2465                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2466                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2467                 return;
2468         }
2469
2470         if (kvm_exception_is_soft(nr)) {
2471                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2472                              vmx->vcpu.arch.event_exit_inst_len);
2473                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2474         } else
2475                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2476
2477         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2478 }
2479
2480 static bool vmx_rdtscp_supported(void)
2481 {
2482         return cpu_has_vmx_rdtscp();
2483 }
2484
2485 static bool vmx_invpcid_supported(void)
2486 {
2487         return cpu_has_vmx_invpcid() && enable_ept;
2488 }
2489
2490 /*
2491  * Swap MSR entry in host/guest MSR entry array.
2492  */
2493 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2494 {
2495         struct shared_msr_entry tmp;
2496
2497         tmp = vmx->guest_msrs[to];
2498         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2499         vmx->guest_msrs[from] = tmp;
2500 }
2501
2502 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2503 {
2504         unsigned long *msr_bitmap;
2505
2506         if (is_guest_mode(vcpu))
2507                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2508         else if (cpu_has_secondary_exec_ctrls() &&
2509                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2510                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2511                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2512                         if (is_long_mode(vcpu))
2513                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2514                         else
2515                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2516                 } else {
2517                         if (is_long_mode(vcpu))
2518                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2519                         else
2520                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2521                 }
2522         } else {
2523                 if (is_long_mode(vcpu))
2524                         msr_bitmap = vmx_msr_bitmap_longmode;
2525                 else
2526                         msr_bitmap = vmx_msr_bitmap_legacy;
2527         }
2528
2529         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2530 }
2531
2532 /*
2533  * Set up the vmcs to automatically save and restore system
2534  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2535  * mode, as fiddling with msrs is very expensive.
2536  */
2537 static void setup_msrs(struct vcpu_vmx *vmx)
2538 {
2539         int save_nmsrs, index;
2540
2541         save_nmsrs = 0;
2542 #ifdef CONFIG_X86_64
2543         if (is_long_mode(&vmx->vcpu)) {
2544                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2545                 if (index >= 0)
2546                         move_msr_up(vmx, index, save_nmsrs++);
2547                 index = __find_msr_index(vmx, MSR_LSTAR);
2548                 if (index >= 0)
2549                         move_msr_up(vmx, index, save_nmsrs++);
2550                 index = __find_msr_index(vmx, MSR_CSTAR);
2551                 if (index >= 0)
2552                         move_msr_up(vmx, index, save_nmsrs++);
2553                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2554                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2555                         move_msr_up(vmx, index, save_nmsrs++);
2556                 /*
2557                  * MSR_STAR is only needed on long mode guests, and only
2558                  * if efer.sce is enabled.
2559                  */
2560                 index = __find_msr_index(vmx, MSR_STAR);
2561                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2562                         move_msr_up(vmx, index, save_nmsrs++);
2563         }
2564 #endif
2565         index = __find_msr_index(vmx, MSR_EFER);
2566         if (index >= 0 && update_transition_efer(vmx, index))
2567                 move_msr_up(vmx, index, save_nmsrs++);
2568
2569         vmx->save_nmsrs = save_nmsrs;
2570
2571         if (cpu_has_vmx_msr_bitmap())
2572                 vmx_set_msr_bitmap(&vmx->vcpu);
2573 }
2574
2575 /*
2576  * reads and returns guest's timestamp counter "register"
2577  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2578  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2579  */
2580 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2581 {
2582         u64 host_tsc, tsc_offset;
2583
2584         host_tsc = rdtsc();
2585         tsc_offset = vmcs_read64(TSC_OFFSET);
2586         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2587 }
2588
2589 /*
2590  * writes 'offset' into guest's timestamp counter offset register
2591  */
2592 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2593 {
2594         if (is_guest_mode(vcpu)) {
2595                 /*
2596                  * We're here if L1 chose not to trap WRMSR to TSC. According
2597                  * to the spec, this should set L1's TSC; The offset that L1
2598                  * set for L2 remains unchanged, and still needs to be added
2599                  * to the newly set TSC to get L2's TSC.
2600                  */
2601                 struct vmcs12 *vmcs12;
2602                 /* recalculate vmcs02.TSC_OFFSET: */
2603                 vmcs12 = get_vmcs12(vcpu);
2604                 vmcs_write64(TSC_OFFSET, offset +
2605                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2606                          vmcs12->tsc_offset : 0));
2607         } else {
2608                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2609                                            vmcs_read64(TSC_OFFSET), offset);
2610                 vmcs_write64(TSC_OFFSET, offset);
2611         }
2612 }
2613
2614 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2615 {
2616         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2617         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2618 }
2619
2620 /*
2621  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2622  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2623  * all guests if the "nested" module option is off, and can also be disabled
2624  * for a single guest by disabling its VMX cpuid bit.
2625  */
2626 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2627 {
2628         return nested && guest_cpuid_has_vmx(vcpu);
2629 }
2630
2631 /*
2632  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2633  * returned for the various VMX controls MSRs when nested VMX is enabled.
2634  * The same values should also be used to verify that vmcs12 control fields are
2635  * valid during nested entry from L1 to L2.
2636  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2637  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2638  * bit in the high half is on if the corresponding bit in the control field
2639  * may be on. See also vmx_control_verify().
2640  */
2641 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2642 {
2643         /*
2644          * Note that as a general rule, the high half of the MSRs (bits in
2645          * the control fields which may be 1) should be initialized by the
2646          * intersection of the underlying hardware's MSR (i.e., features which
2647          * can be supported) and the list of features we want to expose -
2648          * because they are known to be properly supported in our code.
2649          * Also, usually, the low half of the MSRs (bits which must be 1) can
2650          * be set to 0, meaning that L1 may turn off any of these bits. The
2651          * reason is that if one of these bits is necessary, it will appear
2652          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2653          * fields of vmcs01 and vmcs02, will turn these bits off - and
2654          * nested_vmx_exit_handled() will not pass related exits to L1.
2655          * These rules have exceptions below.
2656          */
2657
2658         /* pin-based controls */
2659         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2660                 vmx->nested.nested_vmx_pinbased_ctls_low,
2661                 vmx->nested.nested_vmx_pinbased_ctls_high);
2662         vmx->nested.nested_vmx_pinbased_ctls_low |=
2663                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2664         vmx->nested.nested_vmx_pinbased_ctls_high &=
2665                 PIN_BASED_EXT_INTR_MASK |
2666                 PIN_BASED_NMI_EXITING |
2667                 PIN_BASED_VIRTUAL_NMIS;
2668         vmx->nested.nested_vmx_pinbased_ctls_high |=
2669                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2670                 PIN_BASED_VMX_PREEMPTION_TIMER;
2671         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2672                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2673                         PIN_BASED_POSTED_INTR;
2674
2675         /* exit controls */
2676         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2677                 vmx->nested.nested_vmx_exit_ctls_low,
2678                 vmx->nested.nested_vmx_exit_ctls_high);
2679         vmx->nested.nested_vmx_exit_ctls_low =
2680                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2681
2682         vmx->nested.nested_vmx_exit_ctls_high &=
2683 #ifdef CONFIG_X86_64
2684                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2685 #endif
2686                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2687         vmx->nested.nested_vmx_exit_ctls_high |=
2688                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2689                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2690                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2691
2692         if (kvm_mpx_supported())
2693                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2694
2695         /* We support free control of debug control saving. */
2696         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2697
2698         /* entry controls */
2699         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2700                 vmx->nested.nested_vmx_entry_ctls_low,
2701                 vmx->nested.nested_vmx_entry_ctls_high);
2702         vmx->nested.nested_vmx_entry_ctls_low =
2703                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2704         vmx->nested.nested_vmx_entry_ctls_high &=
2705 #ifdef CONFIG_X86_64
2706                 VM_ENTRY_IA32E_MODE |
2707 #endif
2708                 VM_ENTRY_LOAD_IA32_PAT;
2709         vmx->nested.nested_vmx_entry_ctls_high |=
2710                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2711         if (kvm_mpx_supported())
2712                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2713
2714         /* We support free control of debug control loading. */
2715         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2716
2717         /* cpu-based controls */
2718         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2719                 vmx->nested.nested_vmx_procbased_ctls_low,
2720                 vmx->nested.nested_vmx_procbased_ctls_high);
2721         vmx->nested.nested_vmx_procbased_ctls_low =
2722                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2723         vmx->nested.nested_vmx_procbased_ctls_high &=
2724                 CPU_BASED_VIRTUAL_INTR_PENDING |
2725                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2726                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2727                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2728                 CPU_BASED_CR3_STORE_EXITING |
2729 #ifdef CONFIG_X86_64
2730                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2731 #endif
2732                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2733                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2734                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2735                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2736                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2737         /*
2738          * We can allow some features even when not supported by the
2739          * hardware. For example, L1 can specify an MSR bitmap - and we
2740          * can use it to avoid exits to L1 - even when L0 runs L2
2741          * without MSR bitmaps.
2742          */
2743         vmx->nested.nested_vmx_procbased_ctls_high |=
2744                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2745                 CPU_BASED_USE_MSR_BITMAPS;
2746
2747         /* We support free control of CR3 access interception. */
2748         vmx->nested.nested_vmx_procbased_ctls_low &=
2749                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2750
2751         /* secondary cpu-based controls */
2752         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2753                 vmx->nested.nested_vmx_secondary_ctls_low,
2754                 vmx->nested.nested_vmx_secondary_ctls_high);
2755         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2756         vmx->nested.nested_vmx_secondary_ctls_high &=
2757                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2758                 SECONDARY_EXEC_RDTSCP |
2759                 SECONDARY_EXEC_DESC |
2760                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2761                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2762                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2763                 SECONDARY_EXEC_WBINVD_EXITING |
2764                 SECONDARY_EXEC_XSAVES;
2765
2766         if (enable_ept) {
2767                 /* nested EPT: emulate EPT also to L1 */
2768                 vmx->nested.nested_vmx_secondary_ctls_high |=
2769                         SECONDARY_EXEC_ENABLE_EPT;
2770                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2771                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2772                          VMX_EPT_INVEPT_BIT;
2773                 if (cpu_has_vmx_ept_execute_only())
2774                         vmx->nested.nested_vmx_ept_caps |=
2775                                 VMX_EPT_EXECUTE_ONLY_BIT;
2776                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2777                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2778                         VMX_EPT_EXTENT_CONTEXT_BIT;
2779         } else
2780                 vmx->nested.nested_vmx_ept_caps = 0;
2781
2782         /*
2783          * Old versions of KVM use the single-context version without
2784          * checking for support, so declare that it is supported even
2785          * though it is treated as global context.  The alternative is
2786          * not failing the single-context invvpid, and it is worse.
2787          */
2788         if (enable_vpid) {
2789                 vmx->nested.nested_vmx_secondary_ctls_high |=
2790                         SECONDARY_EXEC_ENABLE_VPID;
2791                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2792                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2793         } else
2794                 vmx->nested.nested_vmx_vpid_caps = 0;
2795
2796         if (enable_unrestricted_guest)
2797                 vmx->nested.nested_vmx_secondary_ctls_high |=
2798                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2799
2800         /* miscellaneous data */
2801         rdmsr(MSR_IA32_VMX_MISC,
2802                 vmx->nested.nested_vmx_misc_low,
2803                 vmx->nested.nested_vmx_misc_high);
2804         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2805         vmx->nested.nested_vmx_misc_low |=
2806                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2807                 VMX_MISC_ACTIVITY_HLT;
2808         vmx->nested.nested_vmx_misc_high = 0;
2809
2810         /*
2811          * This MSR reports some information about VMX support. We
2812          * should return information about the VMX we emulate for the
2813          * guest, and the VMCS structure we give it - not about the
2814          * VMX support of the underlying hardware.
2815          */
2816         vmx->nested.nested_vmx_basic =
2817                 VMCS12_REVISION |
2818                 VMX_BASIC_TRUE_CTLS |
2819                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2820                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2821
2822         if (cpu_has_vmx_basic_inout())
2823                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2824
2825         /*
2826          * These MSRs specify bits which the guest must keep fixed on
2827          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2828          * We picked the standard core2 setting.
2829          */
2830 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2831 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2832         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2833         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2834
2835         /* These MSRs specify bits which the guest must keep fixed off. */
2836         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2837         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2838
2839         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2840         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2841 }
2842
2843 /*
2844  * if fixed0[i] == 1: val[i] must be 1
2845  * if fixed1[i] == 0: val[i] must be 0
2846  */
2847 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2848 {
2849         return ((val & fixed1) | fixed0) == val;
2850 }
2851
2852 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2853 {
2854         return fixed_bits_valid(control, low, high);
2855 }
2856
2857 static inline u64 vmx_control_msr(u32 low, u32 high)
2858 {
2859         return low | ((u64)high << 32);
2860 }
2861
2862 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2863 {
2864         superset &= mask;
2865         subset &= mask;
2866
2867         return (superset | subset) == superset;
2868 }
2869
2870 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2871 {
2872         const u64 feature_and_reserved =
2873                 /* feature (except bit 48; see below) */
2874                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2875                 /* reserved */
2876                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2877         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2878
2879         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2880                 return -EINVAL;
2881
2882         /*
2883          * KVM does not emulate a version of VMX that constrains physical
2884          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2885          */
2886         if (data & BIT_ULL(48))
2887                 return -EINVAL;
2888
2889         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2890             vmx_basic_vmcs_revision_id(data))
2891                 return -EINVAL;
2892
2893         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2894                 return -EINVAL;
2895
2896         vmx->nested.nested_vmx_basic = data;
2897         return 0;
2898 }
2899
2900 static int
2901 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2902 {
2903         u64 supported;
2904         u32 *lowp, *highp;
2905
2906         switch (msr_index) {
2907         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2908                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2909                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2910                 break;
2911         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2912                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2913                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2914                 break;
2915         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2916                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2917                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2918                 break;
2919         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2920                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2921                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2922                 break;
2923         case MSR_IA32_VMX_PROCBASED_CTLS2:
2924                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2925                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2926                 break;
2927         default:
2928                 BUG();
2929         }
2930
2931         supported = vmx_control_msr(*lowp, *highp);
2932
2933         /* Check must-be-1 bits are still 1. */
2934         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2935                 return -EINVAL;
2936
2937         /* Check must-be-0 bits are still 0. */
2938         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2939                 return -EINVAL;
2940
2941         *lowp = data;
2942         *highp = data >> 32;
2943         return 0;
2944 }
2945
2946 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2947 {
2948         const u64 feature_and_reserved_bits =
2949                 /* feature */
2950                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2951                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2952                 /* reserved */
2953                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2954         u64 vmx_misc;
2955
2956         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2957                                    vmx->nested.nested_vmx_misc_high);
2958
2959         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2960                 return -EINVAL;
2961
2962         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2963              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2964             vmx_misc_preemption_timer_rate(data) !=
2965             vmx_misc_preemption_timer_rate(vmx_misc))
2966                 return -EINVAL;
2967
2968         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2969                 return -EINVAL;
2970
2971         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2972                 return -EINVAL;
2973
2974         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2975                 return -EINVAL;
2976
2977         vmx->nested.nested_vmx_misc_low = data;
2978         vmx->nested.nested_vmx_misc_high = data >> 32;
2979         return 0;
2980 }
2981
2982 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2983 {
2984         u64 vmx_ept_vpid_cap;
2985
2986         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2987                                            vmx->nested.nested_vmx_vpid_caps);
2988
2989         /* Every bit is either reserved or a feature bit. */
2990         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2991                 return -EINVAL;
2992
2993         vmx->nested.nested_vmx_ept_caps = data;
2994         vmx->nested.nested_vmx_vpid_caps = data >> 32;
2995         return 0;
2996 }
2997
2998 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2999 {
3000         u64 *msr;
3001
3002         switch (msr_index) {
3003         case MSR_IA32_VMX_CR0_FIXED0:
3004                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3005                 break;
3006         case MSR_IA32_VMX_CR4_FIXED0:
3007                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3008                 break;
3009         default:
3010                 BUG();
3011         }
3012
3013         /*
3014          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3015          * must be 1 in the restored value.
3016          */
3017         if (!is_bitwise_subset(data, *msr, -1ULL))
3018                 return -EINVAL;
3019
3020         *msr = data;
3021         return 0;
3022 }
3023
3024 /*
3025  * Called when userspace is restoring VMX MSRs.
3026  *
3027  * Returns 0 on success, non-0 otherwise.
3028  */
3029 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3030 {
3031         struct vcpu_vmx *vmx = to_vmx(vcpu);
3032
3033         switch (msr_index) {
3034         case MSR_IA32_VMX_BASIC:
3035                 return vmx_restore_vmx_basic(vmx, data);
3036         case MSR_IA32_VMX_PINBASED_CTLS:
3037         case MSR_IA32_VMX_PROCBASED_CTLS:
3038         case MSR_IA32_VMX_EXIT_CTLS:
3039         case MSR_IA32_VMX_ENTRY_CTLS:
3040                 /*
3041                  * The "non-true" VMX capability MSRs are generated from the
3042                  * "true" MSRs, so we do not support restoring them directly.
3043                  *
3044                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3045                  * should restore the "true" MSRs with the must-be-1 bits
3046                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3047                  * DEFAULT SETTINGS".
3048                  */
3049                 return -EINVAL;
3050         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3051         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3052         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3053         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3054         case MSR_IA32_VMX_PROCBASED_CTLS2:
3055                 return vmx_restore_control_msr(vmx, msr_index, data);
3056         case MSR_IA32_VMX_MISC:
3057                 return vmx_restore_vmx_misc(vmx, data);
3058         case MSR_IA32_VMX_CR0_FIXED0:
3059         case MSR_IA32_VMX_CR4_FIXED0:
3060                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3061         case MSR_IA32_VMX_CR0_FIXED1:
3062         case MSR_IA32_VMX_CR4_FIXED1:
3063                 /*
3064                  * These MSRs are generated based on the vCPU's CPUID, so we
3065                  * do not support restoring them directly.
3066                  */
3067                 return -EINVAL;
3068         case MSR_IA32_VMX_EPT_VPID_CAP:
3069                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3070         case MSR_IA32_VMX_VMCS_ENUM:
3071                 vmx->nested.nested_vmx_vmcs_enum = data;
3072                 return 0;
3073         default:
3074                 /*
3075                  * The rest of the VMX capability MSRs do not support restore.
3076                  */
3077                 return -EINVAL;
3078         }
3079 }
3080
3081 /* Returns 0 on success, non-0 otherwise. */
3082 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3083 {
3084         struct vcpu_vmx *vmx = to_vmx(vcpu);
3085
3086         switch (msr_index) {
3087         case MSR_IA32_VMX_BASIC:
3088                 *pdata = vmx->nested.nested_vmx_basic;
3089                 break;
3090         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3091         case MSR_IA32_VMX_PINBASED_CTLS:
3092                 *pdata = vmx_control_msr(
3093                         vmx->nested.nested_vmx_pinbased_ctls_low,
3094                         vmx->nested.nested_vmx_pinbased_ctls_high);
3095                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3096                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3097                 break;
3098         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3099         case MSR_IA32_VMX_PROCBASED_CTLS:
3100                 *pdata = vmx_control_msr(
3101                         vmx->nested.nested_vmx_procbased_ctls_low,
3102                         vmx->nested.nested_vmx_procbased_ctls_high);
3103                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3104                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3105                 break;
3106         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3107         case MSR_IA32_VMX_EXIT_CTLS:
3108                 *pdata = vmx_control_msr(
3109                         vmx->nested.nested_vmx_exit_ctls_low,
3110                         vmx->nested.nested_vmx_exit_ctls_high);
3111                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3112                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3113                 break;
3114         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3115         case MSR_IA32_VMX_ENTRY_CTLS:
3116                 *pdata = vmx_control_msr(
3117                         vmx->nested.nested_vmx_entry_ctls_low,
3118                         vmx->nested.nested_vmx_entry_ctls_high);
3119                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3120                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3121                 break;
3122         case MSR_IA32_VMX_MISC:
3123                 *pdata = vmx_control_msr(
3124                         vmx->nested.nested_vmx_misc_low,
3125                         vmx->nested.nested_vmx_misc_high);
3126                 break;
3127         case MSR_IA32_VMX_CR0_FIXED0:
3128                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3129                 break;
3130         case MSR_IA32_VMX_CR0_FIXED1:
3131                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3132                 break;
3133         case MSR_IA32_VMX_CR4_FIXED0:
3134                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3135                 break;
3136         case MSR_IA32_VMX_CR4_FIXED1:
3137                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3138                 break;
3139         case MSR_IA32_VMX_VMCS_ENUM:
3140                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3141                 break;
3142         case MSR_IA32_VMX_PROCBASED_CTLS2:
3143                 *pdata = vmx_control_msr(
3144                         vmx->nested.nested_vmx_secondary_ctls_low,
3145                         vmx->nested.nested_vmx_secondary_ctls_high);
3146                 break;
3147         case MSR_IA32_VMX_EPT_VPID_CAP:
3148                 *pdata = vmx->nested.nested_vmx_ept_caps |
3149                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3150                 break;
3151         default:
3152                 return 1;
3153         }
3154
3155         return 0;
3156 }
3157
3158 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3159                                                  uint64_t val)
3160 {
3161         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3162
3163         return !(val & ~valid_bits);
3164 }
3165
3166 /*
3167  * Reads an msr value (of 'msr_index') into 'pdata'.
3168  * Returns 0 on success, non-0 otherwise.
3169  * Assumes vcpu_load() was already called.
3170  */
3171 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3172 {
3173         struct shared_msr_entry *msr;
3174
3175         switch (msr_info->index) {
3176 #ifdef CONFIG_X86_64
3177         case MSR_FS_BASE:
3178                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3179                 break;
3180         case MSR_GS_BASE:
3181                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3182                 break;
3183         case MSR_KERNEL_GS_BASE:
3184                 vmx_load_host_state(to_vmx(vcpu));
3185                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3186                 break;
3187 #endif
3188         case MSR_EFER:
3189                 return kvm_get_msr_common(vcpu, msr_info);
3190         case MSR_IA32_TSC:
3191                 msr_info->data = guest_read_tsc(vcpu);
3192                 break;
3193         case MSR_IA32_SYSENTER_CS:
3194                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3195                 break;
3196         case MSR_IA32_SYSENTER_EIP:
3197                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3198                 break;
3199         case MSR_IA32_SYSENTER_ESP:
3200                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3201                 break;
3202         case MSR_IA32_BNDCFGS:
3203                 if (!kvm_mpx_supported())
3204                         return 1;
3205                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3206                 break;
3207         case MSR_IA32_MCG_EXT_CTL:
3208                 if (!msr_info->host_initiated &&
3209                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3210                       FEATURE_CONTROL_LMCE))
3211                         return 1;
3212                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3213                 break;
3214         case MSR_IA32_FEATURE_CONTROL:
3215                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3216                 break;
3217         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3218                 if (!nested_vmx_allowed(vcpu))
3219                         return 1;
3220                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3221         case MSR_IA32_XSS:
3222                 if (!vmx_xsaves_supported())
3223                         return 1;
3224                 msr_info->data = vcpu->arch.ia32_xss;
3225                 break;
3226         case MSR_TSC_AUX:
3227                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3228                         return 1;
3229                 /* Otherwise falls through */
3230         default:
3231                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3232                 if (msr) {
3233                         msr_info->data = msr->data;
3234                         break;
3235                 }
3236                 return kvm_get_msr_common(vcpu, msr_info);
3237         }
3238
3239         return 0;
3240 }
3241
3242 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3243
3244 /*
3245  * Writes msr value into into the appropriate "register".
3246  * Returns 0 on success, non-0 otherwise.
3247  * Assumes vcpu_load() was already called.
3248  */
3249 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3250 {
3251         struct vcpu_vmx *vmx = to_vmx(vcpu);
3252         struct shared_msr_entry *msr;
3253         int ret = 0;
3254         u32 msr_index = msr_info->index;
3255         u64 data = msr_info->data;
3256
3257         switch (msr_index) {
3258         case MSR_EFER:
3259                 ret = kvm_set_msr_common(vcpu, msr_info);
3260                 break;
3261 #ifdef CONFIG_X86_64
3262         case MSR_FS_BASE:
3263                 vmx_segment_cache_clear(vmx);
3264                 vmcs_writel(GUEST_FS_BASE, data);
3265                 break;
3266         case MSR_GS_BASE:
3267                 vmx_segment_cache_clear(vmx);
3268                 vmcs_writel(GUEST_GS_BASE, data);
3269                 break;
3270         case MSR_KERNEL_GS_BASE:
3271                 vmx_load_host_state(vmx);
3272                 vmx->msr_guest_kernel_gs_base = data;
3273                 break;
3274 #endif
3275         case MSR_IA32_SYSENTER_CS:
3276                 vmcs_write32(GUEST_SYSENTER_CS, data);
3277                 break;
3278         case MSR_IA32_SYSENTER_EIP:
3279                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3280                 break;
3281         case MSR_IA32_SYSENTER_ESP:
3282                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3283                 break;
3284         case MSR_IA32_BNDCFGS:
3285                 if (!kvm_mpx_supported())
3286                         return 1;
3287                 vmcs_write64(GUEST_BNDCFGS, data);
3288                 break;
3289         case MSR_IA32_TSC:
3290                 kvm_write_tsc(vcpu, msr_info);
3291                 break;
3292         case MSR_IA32_CR_PAT:
3293                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3294                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3295                                 return 1;
3296                         vmcs_write64(GUEST_IA32_PAT, data);
3297                         vcpu->arch.pat = data;
3298                         break;
3299                 }
3300                 ret = kvm_set_msr_common(vcpu, msr_info);
3301                 break;
3302         case MSR_IA32_TSC_ADJUST:
3303                 ret = kvm_set_msr_common(vcpu, msr_info);
3304                 break;
3305         case MSR_IA32_MCG_EXT_CTL:
3306                 if ((!msr_info->host_initiated &&
3307                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3308                        FEATURE_CONTROL_LMCE)) ||
3309                     (data & ~MCG_EXT_CTL_LMCE_EN))
3310                         return 1;
3311                 vcpu->arch.mcg_ext_ctl = data;
3312                 break;
3313         case MSR_IA32_FEATURE_CONTROL:
3314                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3315                     (to_vmx(vcpu)->msr_ia32_feature_control &
3316                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3317                         return 1;
3318                 vmx->msr_ia32_feature_control = data;
3319                 if (msr_info->host_initiated && data == 0)
3320                         vmx_leave_nested(vcpu);
3321                 break;
3322         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3323                 if (!msr_info->host_initiated)
3324                         return 1; /* they are read-only */
3325                 if (!nested_vmx_allowed(vcpu))
3326                         return 1;
3327                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3328         case MSR_IA32_XSS:
3329                 if (!vmx_xsaves_supported())
3330                         return 1;
3331                 /*
3332                  * The only supported bit as of Skylake is bit 8, but
3333                  * it is not supported on KVM.
3334                  */
3335                 if (data != 0)
3336                         return 1;
3337                 vcpu->arch.ia32_xss = data;
3338                 if (vcpu->arch.ia32_xss != host_xss)
3339                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3340                                 vcpu->arch.ia32_xss, host_xss);
3341                 else
3342                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3343                 break;
3344         case MSR_TSC_AUX:
3345                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3346                         return 1;
3347                 /* Check reserved bit, higher 32 bits should be zero */
3348                 if ((data >> 32) != 0)
3349                         return 1;
3350                 /* Otherwise falls through */
3351         default:
3352                 msr = find_msr_entry(vmx, msr_index);
3353                 if (msr) {
3354                         u64 old_msr_data = msr->data;
3355                         msr->data = data;
3356                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3357                                 preempt_disable();
3358                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3359                                                          msr->mask);
3360                                 preempt_enable();
3361                                 if (ret)
3362                                         msr->data = old_msr_data;
3363                         }
3364                         break;
3365                 }
3366                 ret = kvm_set_msr_common(vcpu, msr_info);
3367         }
3368
3369         return ret;
3370 }
3371
3372 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3373 {
3374         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3375         switch (reg) {
3376         case VCPU_REGS_RSP:
3377                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3378                 break;
3379         case VCPU_REGS_RIP:
3380                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3381                 break;
3382         case VCPU_EXREG_PDPTR:
3383                 if (enable_ept)
3384                         ept_save_pdptrs(vcpu);
3385                 break;
3386         default:
3387                 break;
3388         }
3389 }
3390
3391 static __init int cpu_has_kvm_support(void)
3392 {
3393         return cpu_has_vmx();
3394 }
3395
3396 static __init int vmx_disabled_by_bios(void)
3397 {
3398         u64 msr;
3399
3400         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3401         if (msr & FEATURE_CONTROL_LOCKED) {
3402                 /* launched w/ TXT and VMX disabled */
3403                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3404                         && tboot_enabled())
3405                         return 1;
3406                 /* launched w/o TXT and VMX only enabled w/ TXT */
3407                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3408                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3409                         && !tboot_enabled()) {
3410                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3411                                 "activate TXT before enabling KVM\n");
3412                         return 1;
3413                 }
3414                 /* launched w/o TXT and VMX disabled */
3415                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3416                         && !tboot_enabled())
3417                         return 1;
3418         }
3419
3420         return 0;
3421 }
3422
3423 static void kvm_cpu_vmxon(u64 addr)
3424 {
3425         intel_pt_handle_vmx(1);
3426
3427         asm volatile (ASM_VMX_VMXON_RAX
3428                         : : "a"(&addr), "m"(addr)
3429                         : "memory", "cc");
3430 }
3431
3432 static int hardware_enable(void)
3433 {
3434         int cpu = raw_smp_processor_id();
3435         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3436         u64 old, test_bits;
3437
3438         if (cr4_read_shadow() & X86_CR4_VMXE)
3439                 return -EBUSY;
3440
3441         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3442         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3443         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3444
3445         /*
3446          * Now we can enable the vmclear operation in kdump
3447          * since the loaded_vmcss_on_cpu list on this cpu
3448          * has been initialized.
3449          *
3450          * Though the cpu is not in VMX operation now, there
3451          * is no problem to enable the vmclear operation
3452          * for the loaded_vmcss_on_cpu list is empty!
3453          */
3454         crash_enable_local_vmclear(cpu);
3455
3456         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3457
3458         test_bits = FEATURE_CONTROL_LOCKED;
3459         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3460         if (tboot_enabled())
3461                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3462
3463         if ((old & test_bits) != test_bits) {
3464                 /* enable and lock */
3465                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3466         }
3467         cr4_set_bits(X86_CR4_VMXE);
3468
3469         if (vmm_exclusive) {
3470                 kvm_cpu_vmxon(phys_addr);
3471                 ept_sync_global();
3472         }
3473
3474         native_store_gdt(this_cpu_ptr(&host_gdt));
3475
3476         return 0;
3477 }
3478
3479 static void vmclear_local_loaded_vmcss(void)
3480 {
3481         int cpu = raw_smp_processor_id();
3482         struct loaded_vmcs *v, *n;
3483
3484         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3485                                  loaded_vmcss_on_cpu_link)
3486                 __loaded_vmcs_clear(v);
3487 }
3488
3489
3490 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3491  * tricks.
3492  */
3493 static void kvm_cpu_vmxoff(void)
3494 {
3495         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3496
3497         intel_pt_handle_vmx(0);
3498 }
3499
3500 static void hardware_disable(void)
3501 {
3502         if (vmm_exclusive) {
3503                 vmclear_local_loaded_vmcss();
3504                 kvm_cpu_vmxoff();
3505         }
3506         cr4_clear_bits(X86_CR4_VMXE);
3507 }
3508
3509 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3510                                       u32 msr, u32 *result)
3511 {
3512         u32 vmx_msr_low, vmx_msr_high;
3513         u32 ctl = ctl_min | ctl_opt;
3514
3515         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3516
3517         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3518         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3519
3520         /* Ensure minimum (required) set of control bits are supported. */
3521         if (ctl_min & ~ctl)
3522                 return -EIO;
3523
3524         *result = ctl;
3525         return 0;
3526 }
3527
3528 static __init bool allow_1_setting(u32 msr, u32 ctl)
3529 {
3530         u32 vmx_msr_low, vmx_msr_high;
3531
3532         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3533         return vmx_msr_high & ctl;
3534 }
3535
3536 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3537 {
3538         u32 vmx_msr_low, vmx_msr_high;
3539         u32 min, opt, min2, opt2;
3540         u32 _pin_based_exec_control = 0;
3541         u32 _cpu_based_exec_control = 0;
3542         u32 _cpu_based_2nd_exec_control = 0;
3543         u32 _vmexit_control = 0;
3544         u32 _vmentry_control = 0;
3545
3546         min = CPU_BASED_HLT_EXITING |
3547 #ifdef CONFIG_X86_64
3548               CPU_BASED_CR8_LOAD_EXITING |
3549               CPU_BASED_CR8_STORE_EXITING |
3550 #endif
3551               CPU_BASED_CR3_LOAD_EXITING |
3552               CPU_BASED_CR3_STORE_EXITING |
3553               CPU_BASED_USE_IO_BITMAPS |
3554               CPU_BASED_MOV_DR_EXITING |
3555               CPU_BASED_USE_TSC_OFFSETING |
3556               CPU_BASED_MWAIT_EXITING |
3557               CPU_BASED_MONITOR_EXITING |
3558               CPU_BASED_INVLPG_EXITING |
3559               CPU_BASED_RDPMC_EXITING;
3560
3561         opt = CPU_BASED_TPR_SHADOW |
3562               CPU_BASED_USE_MSR_BITMAPS |
3563               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3564         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3565                                 &_cpu_based_exec_control) < 0)
3566                 return -EIO;
3567 #ifdef CONFIG_X86_64
3568         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3569                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3570                                            ~CPU_BASED_CR8_STORE_EXITING;
3571 #endif
3572         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3573                 min2 = 0;
3574                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3575                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3576                         SECONDARY_EXEC_WBINVD_EXITING |
3577                         SECONDARY_EXEC_ENABLE_VPID |
3578                         SECONDARY_EXEC_ENABLE_EPT |
3579                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3580                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3581                         SECONDARY_EXEC_RDTSCP |
3582                         SECONDARY_EXEC_ENABLE_INVPCID |
3583                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3584                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3585                         SECONDARY_EXEC_SHADOW_VMCS |
3586                         SECONDARY_EXEC_XSAVES |
3587                         SECONDARY_EXEC_ENABLE_PML |
3588                         SECONDARY_EXEC_TSC_SCALING;
3589                 if (adjust_vmx_controls(min2, opt2,
3590                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3591                                         &_cpu_based_2nd_exec_control) < 0)
3592                         return -EIO;
3593         }
3594 #ifndef CONFIG_X86_64
3595         if (!(_cpu_based_2nd_exec_control &
3596                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3597                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3598 #endif
3599
3600         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3601                 _cpu_based_2nd_exec_control &= ~(
3602                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3603                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3604                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3605
3606         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3607                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3608                    enabled */
3609                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3610                                              CPU_BASED_CR3_STORE_EXITING |
3611                                              CPU_BASED_INVLPG_EXITING);
3612                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3613                       vmx_capability.ept, vmx_capability.vpid);
3614         }
3615
3616         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3617 #ifdef CONFIG_X86_64
3618         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3619 #endif
3620         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3621                 VM_EXIT_CLEAR_BNDCFGS;
3622         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3623                                 &_vmexit_control) < 0)
3624                 return -EIO;
3625
3626         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3627         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3628                  PIN_BASED_VMX_PREEMPTION_TIMER;
3629         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3630                                 &_pin_based_exec_control) < 0)
3631                 return -EIO;
3632
3633         if (cpu_has_broken_vmx_preemption_timer())
3634                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3635         if (!(_cpu_based_2nd_exec_control &
3636                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3637                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3638
3639         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3640         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3641         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3642                                 &_vmentry_control) < 0)
3643                 return -EIO;
3644
3645         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3646
3647         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3648         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3649                 return -EIO;
3650
3651 #ifdef CONFIG_X86_64
3652         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3653         if (vmx_msr_high & (1u<<16))
3654                 return -EIO;
3655 #endif
3656
3657         /* Require Write-Back (WB) memory type for VMCS accesses. */
3658         if (((vmx_msr_high >> 18) & 15) != 6)
3659                 return -EIO;
3660
3661         vmcs_conf->size = vmx_msr_high & 0x1fff;
3662         vmcs_conf->order = get_order(vmcs_conf->size);
3663         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3664         vmcs_conf->revision_id = vmx_msr_low;
3665
3666         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3667         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3668         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3669         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3670         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3671
3672         cpu_has_load_ia32_efer =
3673                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3674                                 VM_ENTRY_LOAD_IA32_EFER)
3675                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3676                                    VM_EXIT_LOAD_IA32_EFER);
3677
3678         cpu_has_load_perf_global_ctrl =
3679                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3680                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3681                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3682                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3683
3684         /*
3685          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3686          * but due to errata below it can't be used. Workaround is to use
3687          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3688          *
3689          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3690          *
3691          * AAK155             (model 26)
3692          * AAP115             (model 30)
3693          * AAT100             (model 37)
3694          * BC86,AAY89,BD102   (model 44)
3695          * BA97               (model 46)
3696          *
3697          */
3698         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3699                 switch (boot_cpu_data.x86_model) {
3700                 case 26:
3701                 case 30:
3702                 case 37:
3703                 case 44:
3704                 case 46:
3705                         cpu_has_load_perf_global_ctrl = false;
3706                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3707                                         "does not work properly. Using workaround\n");
3708                         break;
3709                 default:
3710                         break;
3711                 }
3712         }
3713
3714         if (boot_cpu_has(X86_FEATURE_XSAVES))
3715                 rdmsrl(MSR_IA32_XSS, host_xss);
3716
3717         return 0;
3718 }
3719
3720 static struct vmcs *alloc_vmcs_cpu(int cpu)
3721 {
3722         int node = cpu_to_node(cpu);
3723         struct page *pages;
3724         struct vmcs *vmcs;
3725
3726         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3727         if (!pages)
3728                 return NULL;
3729         vmcs = page_address(pages);
3730         memset(vmcs, 0, vmcs_config.size);
3731         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3732         return vmcs;
3733 }
3734
3735 static struct vmcs *alloc_vmcs(void)
3736 {
3737         return alloc_vmcs_cpu(raw_smp_processor_id());
3738 }
3739
3740 static void free_vmcs(struct vmcs *vmcs)
3741 {
3742         free_pages((unsigned long)vmcs, vmcs_config.order);
3743 }
3744
3745 /*
3746  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3747  */
3748 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3749 {
3750         if (!loaded_vmcs->vmcs)
3751                 return;
3752         loaded_vmcs_clear(loaded_vmcs);
3753         free_vmcs(loaded_vmcs->vmcs);
3754         loaded_vmcs->vmcs = NULL;
3755         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3756 }
3757
3758 static void free_kvm_area(void)
3759 {
3760         int cpu;
3761
3762         for_each_possible_cpu(cpu) {
3763                 free_vmcs(per_cpu(vmxarea, cpu));
3764                 per_cpu(vmxarea, cpu) = NULL;
3765         }
3766 }
3767
3768 static void init_vmcs_shadow_fields(void)
3769 {
3770         int i, j;
3771
3772         /* No checks for read only fields yet */
3773
3774         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3775                 switch (shadow_read_write_fields[i]) {
3776                 case GUEST_BNDCFGS:
3777                         if (!kvm_mpx_supported())
3778                                 continue;
3779                         break;
3780                 default:
3781                         break;
3782                 }
3783
3784                 if (j < i)
3785                         shadow_read_write_fields[j] =
3786                                 shadow_read_write_fields[i];
3787                 j++;
3788         }
3789         max_shadow_read_write_fields = j;
3790
3791         /* shadowed fields guest access without vmexit */
3792         for (i = 0; i < max_shadow_read_write_fields; i++) {
3793                 clear_bit(shadow_read_write_fields[i],
3794                           vmx_vmwrite_bitmap);
3795                 clear_bit(shadow_read_write_fields[i],
3796                           vmx_vmread_bitmap);
3797         }
3798         for (i = 0; i < max_shadow_read_only_fields; i++)
3799                 clear_bit(shadow_read_only_fields[i],
3800                           vmx_vmread_bitmap);
3801 }
3802
3803 static __init int alloc_kvm_area(void)
3804 {
3805         int cpu;
3806
3807         for_each_possible_cpu(cpu) {
3808                 struct vmcs *vmcs;
3809
3810                 vmcs = alloc_vmcs_cpu(cpu);
3811                 if (!vmcs) {
3812                         free_kvm_area();
3813                         return -ENOMEM;
3814                 }
3815
3816                 per_cpu(vmxarea, cpu) = vmcs;
3817         }
3818         return 0;
3819 }
3820
3821 static bool emulation_required(struct kvm_vcpu *vcpu)
3822 {
3823         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3824 }
3825
3826 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3827                 struct kvm_segment *save)
3828 {
3829         if (!emulate_invalid_guest_state) {
3830                 /*
3831                  * CS and SS RPL should be equal during guest entry according
3832                  * to VMX spec, but in reality it is not always so. Since vcpu
3833                  * is in the middle of the transition from real mode to
3834                  * protected mode it is safe to assume that RPL 0 is a good
3835                  * default value.
3836                  */
3837                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3838                         save->selector &= ~SEGMENT_RPL_MASK;
3839                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3840                 save->s = 1;
3841         }
3842         vmx_set_segment(vcpu, save, seg);
3843 }
3844
3845 static void enter_pmode(struct kvm_vcpu *vcpu)
3846 {
3847         unsigned long flags;
3848         struct vcpu_vmx *vmx = to_vmx(vcpu);
3849
3850         /*
3851          * Update real mode segment cache. It may be not up-to-date if sement
3852          * register was written while vcpu was in a guest mode.
3853          */
3854         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3855         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3856         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3857         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3858         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3859         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3860
3861         vmx->rmode.vm86_active = 0;
3862
3863         vmx_segment_cache_clear(vmx);
3864
3865         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3866
3867         flags = vmcs_readl(GUEST_RFLAGS);
3868         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3869         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3870         vmcs_writel(GUEST_RFLAGS, flags);
3871
3872         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3873                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3874
3875         update_exception_bitmap(vcpu);
3876
3877         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3878         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3879         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3880         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3881         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3882         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3883 }
3884
3885 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3886 {
3887         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3888         struct kvm_segment var = *save;
3889
3890         var.dpl = 0x3;
3891         if (seg == VCPU_SREG_CS)
3892                 var.type = 0x3;
3893
3894         if (!emulate_invalid_guest_state) {
3895                 var.selector = var.base >> 4;
3896                 var.base = var.base & 0xffff0;
3897                 var.limit = 0xffff;
3898                 var.g = 0;
3899                 var.db = 0;
3900                 var.present = 1;
3901                 var.s = 1;
3902                 var.l = 0;
3903                 var.unusable = 0;
3904                 var.type = 0x3;
3905                 var.avl = 0;
3906                 if (save->base & 0xf)
3907                         printk_once(KERN_WARNING "kvm: segment base is not "
3908                                         "paragraph aligned when entering "
3909                                         "protected mode (seg=%d)", seg);
3910         }
3911
3912         vmcs_write16(sf->selector, var.selector);
3913         vmcs_writel(sf->base, var.base);
3914         vmcs_write32(sf->limit, var.limit);
3915         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3916 }
3917
3918 static void enter_rmode(struct kvm_vcpu *vcpu)
3919 {
3920         unsigned long flags;
3921         struct vcpu_vmx *vmx = to_vmx(vcpu);
3922
3923         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3924         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3925         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3926         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3927         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3928         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3929         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3930
3931         vmx->rmode.vm86_active = 1;
3932
3933         /*
3934          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3935          * vcpu. Warn the user that an update is overdue.
3936          */
3937         if (!vcpu->kvm->arch.tss_addr)
3938                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3939                              "called before entering vcpu\n");
3940
3941         vmx_segment_cache_clear(vmx);
3942
3943         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3944         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3945         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3946
3947         flags = vmcs_readl(GUEST_RFLAGS);
3948         vmx->rmode.save_rflags = flags;
3949
3950         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3951
3952         vmcs_writel(GUEST_RFLAGS, flags);
3953         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3954         update_exception_bitmap(vcpu);
3955
3956         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3957         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3958         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3959         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3960         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3961         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3962
3963         kvm_mmu_reset_context(vcpu);
3964 }
3965
3966 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3967 {
3968         struct vcpu_vmx *vmx = to_vmx(vcpu);
3969         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3970
3971         if (!msr)
3972                 return;
3973
3974         /*
3975          * Force kernel_gs_base reloading before EFER changes, as control
3976          * of this msr depends on is_long_mode().
3977          */
3978         vmx_load_host_state(to_vmx(vcpu));
3979         vcpu->arch.efer = efer;
3980         if (efer & EFER_LMA) {
3981                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3982                 msr->data = efer;
3983         } else {
3984                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3985
3986                 msr->data = efer & ~EFER_LME;
3987         }
3988         setup_msrs(vmx);
3989 }
3990
3991 #ifdef CONFIG_X86_64
3992
3993 static void enter_lmode(struct kvm_vcpu *vcpu)
3994 {
3995         u32 guest_tr_ar;
3996
3997         vmx_segment_cache_clear(to_vmx(vcpu));
3998
3999         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4000         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4001                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4002                                      __func__);
4003                 vmcs_write32(GUEST_TR_AR_BYTES,
4004                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4005                              | VMX_AR_TYPE_BUSY_64_TSS);
4006         }
4007         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4008 }
4009
4010 static void exit_lmode(struct kvm_vcpu *vcpu)
4011 {
4012         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4013         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4014 }
4015
4016 #endif
4017
4018 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4019 {
4020         vpid_sync_context(vpid);
4021         if (enable_ept) {
4022                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4023                         return;
4024                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
4025         }
4026 }
4027
4028 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4029 {
4030         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4031 }
4032
4033 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4034 {
4035         if (enable_ept)
4036                 vmx_flush_tlb(vcpu);
4037 }
4038
4039 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4040 {
4041         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4042
4043         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4044         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4045 }
4046
4047 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4048 {
4049         if (enable_ept && is_paging(vcpu))
4050                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4051         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4052 }
4053
4054 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4055 {
4056         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4057
4058         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4059         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4060 }
4061
4062 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4063 {
4064         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4065
4066         if (!test_bit(VCPU_EXREG_PDPTR,
4067                       (unsigned long *)&vcpu->arch.regs_dirty))
4068                 return;
4069
4070         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4071                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4072                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4073                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4074                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4075         }
4076 }
4077
4078 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4079 {
4080         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4081
4082         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4083                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4084                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4085                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4086                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4087         }
4088
4089         __set_bit(VCPU_EXREG_PDPTR,
4090                   (unsigned long *)&vcpu->arch.regs_avail);
4091         __set_bit(VCPU_EXREG_PDPTR,
4092                   (unsigned long *)&vcpu->arch.regs_dirty);
4093 }
4094
4095 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4096 {
4097         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4098         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4099         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4100
4101         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4102                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4103             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4104                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4105
4106         return fixed_bits_valid(val, fixed0, fixed1);
4107 }
4108
4109 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4110 {
4111         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4112         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4113
4114         return fixed_bits_valid(val, fixed0, fixed1);
4115 }
4116
4117 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4118 {
4119         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4120         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4121
4122         return fixed_bits_valid(val, fixed0, fixed1);
4123 }
4124
4125 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4126 #define nested_guest_cr4_valid  nested_cr4_valid
4127 #define nested_host_cr4_valid   nested_cr4_valid
4128
4129 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4130
4131 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4132                                         unsigned long cr0,
4133                                         struct kvm_vcpu *vcpu)
4134 {
4135         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4136                 vmx_decache_cr3(vcpu);
4137         if (!(cr0 & X86_CR0_PG)) {
4138                 /* From paging/starting to nonpaging */
4139                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4140                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4141                              (CPU_BASED_CR3_LOAD_EXITING |
4142                               CPU_BASED_CR3_STORE_EXITING));
4143                 vcpu->arch.cr0 = cr0;
4144                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4145         } else if (!is_paging(vcpu)) {
4146                 /* From nonpaging to paging */
4147                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4148                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4149                              ~(CPU_BASED_CR3_LOAD_EXITING |
4150                                CPU_BASED_CR3_STORE_EXITING));
4151                 vcpu->arch.cr0 = cr0;
4152                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4153         }
4154
4155         if (!(cr0 & X86_CR0_WP))
4156                 *hw_cr0 &= ~X86_CR0_WP;
4157 }
4158
4159 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4160 {
4161         struct vcpu_vmx *vmx = to_vmx(vcpu);
4162         unsigned long hw_cr0;
4163
4164         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4165         if (enable_unrestricted_guest)
4166                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4167         else {
4168                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4169
4170                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4171                         enter_pmode(vcpu);
4172
4173                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4174                         enter_rmode(vcpu);
4175         }
4176
4177 #ifdef CONFIG_X86_64
4178         if (vcpu->arch.efer & EFER_LME) {
4179                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4180                         enter_lmode(vcpu);
4181                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4182                         exit_lmode(vcpu);
4183         }
4184 #endif
4185
4186         if (enable_ept)
4187                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4188
4189         vmcs_writel(CR0_READ_SHADOW, cr0);
4190         vmcs_writel(GUEST_CR0, hw_cr0);
4191         vcpu->arch.cr0 = cr0;
4192
4193         /* depends on vcpu->arch.cr0 to be set to a new value */
4194         vmx->emulation_required = emulation_required(vcpu);
4195 }
4196
4197 static u64 construct_eptp(unsigned long root_hpa)
4198 {
4199         u64 eptp;
4200
4201         /* TODO write the value reading from MSR */
4202         eptp = VMX_EPT_DEFAULT_MT |
4203                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4204         if (enable_ept_ad_bits)
4205                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4206         eptp |= (root_hpa & PAGE_MASK);
4207
4208         return eptp;
4209 }
4210
4211 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4212 {
4213         unsigned long guest_cr3;
4214         u64 eptp;
4215
4216         guest_cr3 = cr3;
4217         if (enable_ept) {
4218                 eptp = construct_eptp(cr3);
4219                 vmcs_write64(EPT_POINTER, eptp);
4220                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4221                         guest_cr3 = kvm_read_cr3(vcpu);
4222                 else
4223                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4224                 ept_load_pdptrs(vcpu);
4225         }
4226
4227         vmx_flush_tlb(vcpu);
4228         vmcs_writel(GUEST_CR3, guest_cr3);
4229 }
4230
4231 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4232 {
4233         /*
4234          * Pass through host's Machine Check Enable value to hw_cr4, which
4235          * is in force while we are in guest mode.  Do not let guests control
4236          * this bit, even if host CR4.MCE == 0.
4237          */
4238         unsigned long hw_cr4 =
4239                 (cr4_read_shadow() & X86_CR4_MCE) |
4240                 (cr4 & ~X86_CR4_MCE) |
4241                 (to_vmx(vcpu)->rmode.vm86_active ?
4242                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4243
4244         if (cr4 & X86_CR4_VMXE) {
4245                 /*
4246                  * To use VMXON (and later other VMX instructions), a guest
4247                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4248                  * So basically the check on whether to allow nested VMX
4249                  * is here.
4250                  */
4251                 if (!nested_vmx_allowed(vcpu))
4252                         return 1;
4253         }
4254
4255         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4256                 return 1;
4257
4258         vcpu->arch.cr4 = cr4;
4259         if (enable_ept) {
4260                 if (!is_paging(vcpu)) {
4261                         hw_cr4 &= ~X86_CR4_PAE;
4262                         hw_cr4 |= X86_CR4_PSE;
4263                 } else if (!(cr4 & X86_CR4_PAE)) {
4264                         hw_cr4 &= ~X86_CR4_PAE;
4265                 }
4266         }
4267
4268         if (!enable_unrestricted_guest && !is_paging(vcpu))
4269                 /*
4270                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4271                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4272                  * to be manually disabled when guest switches to non-paging
4273                  * mode.
4274                  *
4275                  * If !enable_unrestricted_guest, the CPU is always running
4276                  * with CR0.PG=1 and CR4 needs to be modified.
4277                  * If enable_unrestricted_guest, the CPU automatically
4278                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4279                  */
4280                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4281
4282         vmcs_writel(CR4_READ_SHADOW, cr4);
4283         vmcs_writel(GUEST_CR4, hw_cr4);
4284         return 0;
4285 }
4286
4287 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4288                             struct kvm_segment *var, int seg)
4289 {
4290         struct vcpu_vmx *vmx = to_vmx(vcpu);
4291         u32 ar;
4292
4293         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4294                 *var = vmx->rmode.segs[seg];
4295                 if (seg == VCPU_SREG_TR
4296                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4297                         return;
4298                 var->base = vmx_read_guest_seg_base(vmx, seg);
4299                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4300                 return;
4301         }
4302         var->base = vmx_read_guest_seg_base(vmx, seg);
4303         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4304         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4305         ar = vmx_read_guest_seg_ar(vmx, seg);
4306         var->unusable = (ar >> 16) & 1;
4307         var->type = ar & 15;
4308         var->s = (ar >> 4) & 1;
4309         var->dpl = (ar >> 5) & 3;
4310         /*
4311          * Some userspaces do not preserve unusable property. Since usable
4312          * segment has to be present according to VMX spec we can use present
4313          * property to amend userspace bug by making unusable segment always
4314          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4315          * segment as unusable.
4316          */
4317         var->present = !var->unusable;
4318         var->avl = (ar >> 12) & 1;
4319         var->l = (ar >> 13) & 1;
4320         var->db = (ar >> 14) & 1;
4321         var->g = (ar >> 15) & 1;
4322 }
4323
4324 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4325 {
4326         struct kvm_segment s;
4327
4328         if (to_vmx(vcpu)->rmode.vm86_active) {
4329                 vmx_get_segment(vcpu, &s, seg);
4330                 return s.base;
4331         }
4332         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4333 }
4334
4335 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4336 {
4337         struct vcpu_vmx *vmx = to_vmx(vcpu);
4338
4339         if (unlikely(vmx->rmode.vm86_active))
4340                 return 0;
4341         else {
4342                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4343                 return VMX_AR_DPL(ar);
4344         }
4345 }
4346
4347 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4348 {
4349         u32 ar;
4350
4351         if (var->unusable || !var->present)
4352                 ar = 1 << 16;
4353         else {
4354                 ar = var->type & 15;
4355                 ar |= (var->s & 1) << 4;
4356                 ar |= (var->dpl & 3) << 5;
4357                 ar |= (var->present & 1) << 7;
4358                 ar |= (var->avl & 1) << 12;
4359                 ar |= (var->l & 1) << 13;
4360                 ar |= (var->db & 1) << 14;
4361                 ar |= (var->g & 1) << 15;
4362         }
4363
4364         return ar;
4365 }
4366
4367 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4368                             struct kvm_segment *var, int seg)
4369 {
4370         struct vcpu_vmx *vmx = to_vmx(vcpu);
4371         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4372
4373         vmx_segment_cache_clear(vmx);
4374
4375         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4376                 vmx->rmode.segs[seg] = *var;
4377                 if (seg == VCPU_SREG_TR)
4378                         vmcs_write16(sf->selector, var->selector);
4379                 else if (var->s)
4380                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4381                 goto out;
4382         }
4383
4384         vmcs_writel(sf->base, var->base);
4385         vmcs_write32(sf->limit, var->limit);
4386         vmcs_write16(sf->selector, var->selector);
4387
4388         /*
4389          *   Fix the "Accessed" bit in AR field of segment registers for older
4390          * qemu binaries.
4391          *   IA32 arch specifies that at the time of processor reset the
4392          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4393          * is setting it to 0 in the userland code. This causes invalid guest
4394          * state vmexit when "unrestricted guest" mode is turned on.
4395          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4396          * tree. Newer qemu binaries with that qemu fix would not need this
4397          * kvm hack.
4398          */
4399         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4400                 var->type |= 0x1; /* Accessed */
4401
4402         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4403
4404 out:
4405         vmx->emulation_required = emulation_required(vcpu);
4406 }
4407
4408 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4409 {
4410         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4411
4412         *db = (ar >> 14) & 1;
4413         *l = (ar >> 13) & 1;
4414 }
4415
4416 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4417 {
4418         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4419         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4420 }
4421
4422 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4423 {
4424         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4425         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4426 }
4427
4428 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4429 {
4430         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4431         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4432 }
4433
4434 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4435 {
4436         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4437         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4438 }
4439
4440 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4441 {
4442         struct kvm_segment var;
4443         u32 ar;
4444
4445         vmx_get_segment(vcpu, &var, seg);
4446         var.dpl = 0x3;
4447         if (seg == VCPU_SREG_CS)
4448                 var.type = 0x3;
4449         ar = vmx_segment_access_rights(&var);
4450
4451         if (var.base != (var.selector << 4))
4452                 return false;
4453         if (var.limit != 0xffff)
4454                 return false;
4455         if (ar != 0xf3)
4456                 return false;
4457
4458         return true;
4459 }
4460
4461 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4462 {
4463         struct kvm_segment cs;
4464         unsigned int cs_rpl;
4465
4466         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4467         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4468
4469         if (cs.unusable)
4470                 return false;
4471         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4472                 return false;
4473         if (!cs.s)
4474                 return false;
4475         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4476                 if (cs.dpl > cs_rpl)
4477                         return false;
4478         } else {
4479                 if (cs.dpl != cs_rpl)
4480                         return false;
4481         }
4482         if (!cs.present)
4483                 return false;
4484
4485         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4486         return true;
4487 }
4488
4489 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4490 {
4491         struct kvm_segment ss;
4492         unsigned int ss_rpl;
4493
4494         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4495         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4496
4497         if (ss.unusable)
4498                 return true;
4499         if (ss.type != 3 && ss.type != 7)
4500                 return false;
4501         if (!ss.s)
4502                 return false;
4503         if (ss.dpl != ss_rpl) /* DPL != RPL */
4504                 return false;
4505         if (!ss.present)
4506                 return false;
4507
4508         return true;
4509 }
4510
4511 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4512 {
4513         struct kvm_segment var;
4514         unsigned int rpl;
4515
4516         vmx_get_segment(vcpu, &var, seg);
4517         rpl = var.selector & SEGMENT_RPL_MASK;
4518
4519         if (var.unusable)
4520                 return true;
4521         if (!var.s)
4522                 return false;
4523         if (!var.present)
4524                 return false;
4525         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4526                 if (var.dpl < rpl) /* DPL < RPL */
4527                         return false;
4528         }
4529
4530         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4531          * rights flags
4532          */
4533         return true;
4534 }
4535
4536 static bool tr_valid(struct kvm_vcpu *vcpu)
4537 {
4538         struct kvm_segment tr;
4539
4540         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4541
4542         if (tr.unusable)
4543                 return false;
4544         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4545                 return false;
4546         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4547                 return false;
4548         if (!tr.present)
4549                 return false;
4550
4551         return true;
4552 }
4553
4554 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4555 {
4556         struct kvm_segment ldtr;
4557
4558         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4559
4560         if (ldtr.unusable)
4561                 return true;
4562         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4563                 return false;
4564         if (ldtr.type != 2)
4565                 return false;
4566         if (!ldtr.present)
4567                 return false;
4568
4569         return true;
4570 }
4571
4572 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4573 {
4574         struct kvm_segment cs, ss;
4575
4576         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4577         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4578
4579         return ((cs.selector & SEGMENT_RPL_MASK) ==
4580                  (ss.selector & SEGMENT_RPL_MASK));
4581 }
4582
4583 /*
4584  * Check if guest state is valid. Returns true if valid, false if
4585  * not.
4586  * We assume that registers are always usable
4587  */
4588 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4589 {
4590         if (enable_unrestricted_guest)
4591                 return true;
4592
4593         /* real mode guest state checks */
4594         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4595                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4596                         return false;
4597                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4598                         return false;
4599                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4600                         return false;
4601                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4602                         return false;
4603                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4604                         return false;
4605                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4606                         return false;
4607         } else {
4608         /* protected mode guest state checks */
4609                 if (!cs_ss_rpl_check(vcpu))
4610                         return false;
4611                 if (!code_segment_valid(vcpu))
4612                         return false;
4613                 if (!stack_segment_valid(vcpu))
4614                         return false;
4615                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4616                         return false;
4617                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4618                         return false;
4619                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4620                         return false;
4621                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4622                         return false;
4623                 if (!tr_valid(vcpu))
4624                         return false;
4625                 if (!ldtr_valid(vcpu))
4626                         return false;
4627         }
4628         /* TODO:
4629          * - Add checks on RIP
4630          * - Add checks on RFLAGS
4631          */
4632
4633         return true;
4634 }
4635
4636 static int init_rmode_tss(struct kvm *kvm)
4637 {
4638         gfn_t fn;
4639         u16 data = 0;
4640         int idx, r;
4641
4642         idx = srcu_read_lock(&kvm->srcu);
4643         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4644         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4645         if (r < 0)
4646                 goto out;
4647         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4648         r = kvm_write_guest_page(kvm, fn++, &data,
4649                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4650         if (r < 0)
4651                 goto out;
4652         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4653         if (r < 0)
4654                 goto out;
4655         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4656         if (r < 0)
4657                 goto out;
4658         data = ~0;
4659         r = kvm_write_guest_page(kvm, fn, &data,
4660                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4661                                  sizeof(u8));
4662 out:
4663         srcu_read_unlock(&kvm->srcu, idx);
4664         return r;
4665 }
4666
4667 static int init_rmode_identity_map(struct kvm *kvm)
4668 {
4669         int i, idx, r = 0;
4670         kvm_pfn_t identity_map_pfn;
4671         u32 tmp;
4672
4673         if (!enable_ept)
4674                 return 0;
4675
4676         /* Protect kvm->arch.ept_identity_pagetable_done. */
4677         mutex_lock(&kvm->slots_lock);
4678
4679         if (likely(kvm->arch.ept_identity_pagetable_done))
4680                 goto out2;
4681
4682         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4683
4684         r = alloc_identity_pagetable(kvm);
4685         if (r < 0)
4686                 goto out2;
4687
4688         idx = srcu_read_lock(&kvm->srcu);
4689         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4690         if (r < 0)
4691                 goto out;
4692         /* Set up identity-mapping pagetable for EPT in real mode */
4693         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4694                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4695                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4696                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4697                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4698                 if (r < 0)
4699                         goto out;
4700         }
4701         kvm->arch.ept_identity_pagetable_done = true;
4702
4703 out:
4704         srcu_read_unlock(&kvm->srcu, idx);
4705
4706 out2:
4707         mutex_unlock(&kvm->slots_lock);
4708         return r;
4709 }
4710
4711 static void seg_setup(int seg)
4712 {
4713         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4714         unsigned int ar;
4715
4716         vmcs_write16(sf->selector, 0);
4717         vmcs_writel(sf->base, 0);
4718         vmcs_write32(sf->limit, 0xffff);
4719         ar = 0x93;
4720         if (seg == VCPU_SREG_CS)
4721                 ar |= 0x08; /* code segment */
4722
4723         vmcs_write32(sf->ar_bytes, ar);
4724 }
4725
4726 static int alloc_apic_access_page(struct kvm *kvm)
4727 {
4728         struct page *page;
4729         int r = 0;
4730
4731         mutex_lock(&kvm->slots_lock);
4732         if (kvm->arch.apic_access_page_done)
4733                 goto out;
4734         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4735                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4736         if (r)
4737                 goto out;
4738
4739         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4740         if (is_error_page(page)) {
4741                 r = -EFAULT;
4742                 goto out;
4743         }
4744
4745         /*
4746          * Do not pin the page in memory, so that memory hot-unplug
4747          * is able to migrate it.
4748          */
4749         put_page(page);
4750         kvm->arch.apic_access_page_done = true;
4751 out:
4752         mutex_unlock(&kvm->slots_lock);
4753         return r;
4754 }
4755
4756 static int alloc_identity_pagetable(struct kvm *kvm)
4757 {
4758         /* Called with kvm->slots_lock held. */
4759
4760         int r = 0;
4761
4762         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4763
4764         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4765                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4766
4767         return r;
4768 }
4769
4770 static int allocate_vpid(void)
4771 {
4772         int vpid;
4773
4774         if (!enable_vpid)
4775                 return 0;
4776         spin_lock(&vmx_vpid_lock);
4777         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4778         if (vpid < VMX_NR_VPIDS)
4779                 __set_bit(vpid, vmx_vpid_bitmap);
4780         else
4781                 vpid = 0;
4782         spin_unlock(&vmx_vpid_lock);
4783         return vpid;
4784 }
4785
4786 static void free_vpid(int vpid)
4787 {
4788         if (!enable_vpid || vpid == 0)
4789                 return;
4790         spin_lock(&vmx_vpid_lock);
4791         __clear_bit(vpid, vmx_vpid_bitmap);
4792         spin_unlock(&vmx_vpid_lock);
4793 }
4794
4795 #define MSR_TYPE_R      1
4796 #define MSR_TYPE_W      2
4797 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4798                                                 u32 msr, int type)
4799 {
4800         int f = sizeof(unsigned long);
4801
4802         if (!cpu_has_vmx_msr_bitmap())
4803                 return;
4804
4805         /*
4806          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4807          * have the write-low and read-high bitmap offsets the wrong way round.
4808          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4809          */
4810         if (msr <= 0x1fff) {
4811                 if (type & MSR_TYPE_R)
4812                         /* read-low */
4813                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4814
4815                 if (type & MSR_TYPE_W)
4816                         /* write-low */
4817                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4818
4819         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4820                 msr &= 0x1fff;
4821                 if (type & MSR_TYPE_R)
4822                         /* read-high */
4823                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4824
4825                 if (type & MSR_TYPE_W)
4826                         /* write-high */
4827                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4828
4829         }
4830 }
4831
4832 /*
4833  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4834  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4835  */
4836 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4837                                                unsigned long *msr_bitmap_nested,
4838                                                u32 msr, int type)
4839 {
4840         int f = sizeof(unsigned long);
4841
4842         if (!cpu_has_vmx_msr_bitmap()) {
4843                 WARN_ON(1);
4844                 return;
4845         }
4846
4847         /*
4848          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4849          * have the write-low and read-high bitmap offsets the wrong way round.
4850          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4851          */
4852         if (msr <= 0x1fff) {
4853                 if (type & MSR_TYPE_R &&
4854                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4855                         /* read-low */
4856                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4857
4858                 if (type & MSR_TYPE_W &&
4859                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4860                         /* write-low */
4861                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4862
4863         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4864                 msr &= 0x1fff;
4865                 if (type & MSR_TYPE_R &&
4866                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4867                         /* read-high */
4868                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4869
4870                 if (type & MSR_TYPE_W &&
4871                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4872                         /* write-high */
4873                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4874
4875         }
4876 }
4877
4878 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4879 {
4880         if (!longmode_only)
4881                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4882                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4883         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4884                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4885 }
4886
4887 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4888 {
4889         if (apicv_active) {
4890                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4891                                 msr, type);
4892                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4893                                 msr, type);
4894         } else {
4895                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4896                                 msr, type);
4897                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4898                                 msr, type);
4899         }
4900 }
4901
4902 static bool vmx_get_enable_apicv(void)
4903 {
4904         return enable_apicv;
4905 }
4906
4907 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4908 {
4909         struct vcpu_vmx *vmx = to_vmx(vcpu);
4910         int max_irr;
4911         void *vapic_page;
4912         u16 status;
4913
4914         if (vmx->nested.pi_desc &&
4915             vmx->nested.pi_pending) {
4916                 vmx->nested.pi_pending = false;
4917                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4918                         return;
4919
4920                 max_irr = find_last_bit(
4921                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4922
4923                 if (max_irr == 256)
4924                         return;
4925
4926                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4927                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4928                 kunmap(vmx->nested.virtual_apic_page);
4929
4930                 status = vmcs_read16(GUEST_INTR_STATUS);
4931                 if ((u8)max_irr > ((u8)status & 0xff)) {
4932                         status &= ~0xff;
4933                         status |= (u8)max_irr;
4934                         vmcs_write16(GUEST_INTR_STATUS, status);
4935                 }
4936         }
4937 }
4938
4939 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4940 {
4941 #ifdef CONFIG_SMP
4942         if (vcpu->mode == IN_GUEST_MODE) {
4943                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4944
4945                 /*
4946                  * Currently, we don't support urgent interrupt,
4947                  * all interrupts are recognized as non-urgent
4948                  * interrupt, so we cannot post interrupts when
4949                  * 'SN' is set.
4950                  *
4951                  * If the vcpu is in guest mode, it means it is
4952                  * running instead of being scheduled out and
4953                  * waiting in the run queue, and that's the only
4954                  * case when 'SN' is set currently, warning if
4955                  * 'SN' is set.
4956                  */
4957                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4958
4959                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4960                                 POSTED_INTR_VECTOR);
4961                 return true;
4962         }
4963 #endif
4964         return false;
4965 }
4966
4967 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4968                                                 int vector)
4969 {
4970         struct vcpu_vmx *vmx = to_vmx(vcpu);
4971
4972         if (is_guest_mode(vcpu) &&
4973             vector == vmx->nested.posted_intr_nv) {
4974                 /* the PIR and ON have been set by L1. */
4975                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4976                 /*
4977                  * If a posted intr is not recognized by hardware,
4978                  * we will accomplish it in the next vmentry.
4979                  */
4980                 vmx->nested.pi_pending = true;
4981                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4982                 return 0;
4983         }
4984         return -1;
4985 }
4986 /*
4987  * Send interrupt to vcpu via posted interrupt way.
4988  * 1. If target vcpu is running(non-root mode), send posted interrupt
4989  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4990  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4991  * interrupt from PIR in next vmentry.
4992  */
4993 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4994 {
4995         struct vcpu_vmx *vmx = to_vmx(vcpu);
4996         int r;
4997
4998         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4999         if (!r)
5000                 return;
5001
5002         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5003                 return;
5004
5005         /* If a previous notification has sent the IPI, nothing to do.  */
5006         if (pi_test_and_set_on(&vmx->pi_desc))
5007                 return;
5008
5009         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5010                 kvm_vcpu_kick(vcpu);
5011 }
5012
5013 /*
5014  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5015  * will not change in the lifetime of the guest.
5016  * Note that host-state that does change is set elsewhere. E.g., host-state
5017  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5018  */
5019 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5020 {
5021         u32 low32, high32;
5022         unsigned long tmpl;
5023         struct desc_ptr dt;
5024         unsigned long cr0, cr4;
5025
5026         cr0 = read_cr0();
5027         WARN_ON(cr0 & X86_CR0_TS);
5028         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5029         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
5030
5031         /* Save the most likely value for this task's CR4 in the VMCS. */
5032         cr4 = cr4_read_shadow();
5033         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5034         vmx->host_state.vmcs_host_cr4 = cr4;
5035
5036         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5037 #ifdef CONFIG_X86_64
5038         /*
5039          * Load null selectors, so we can avoid reloading them in
5040          * __vmx_load_host_state(), in case userspace uses the null selectors
5041          * too (the expected case).
5042          */
5043         vmcs_write16(HOST_DS_SELECTOR, 0);
5044         vmcs_write16(HOST_ES_SELECTOR, 0);
5045 #else
5046         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5047         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5048 #endif
5049         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5050         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5051
5052         native_store_idt(&dt);
5053         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5054         vmx->host_idt_base = dt.address;
5055
5056         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5057
5058         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5059         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5060         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5061         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5062
5063         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5064                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5065                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5066         }
5067 }
5068
5069 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5070 {
5071         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5072         if (enable_ept)
5073                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5074         if (is_guest_mode(&vmx->vcpu))
5075                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5076                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5077         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5078 }
5079
5080 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5081 {
5082         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5083
5084         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5085                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5086         /* Enable the preemption timer dynamically */
5087         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5088         return pin_based_exec_ctrl;
5089 }
5090
5091 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5092 {
5093         struct vcpu_vmx *vmx = to_vmx(vcpu);
5094
5095         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5096         if (cpu_has_secondary_exec_ctrls()) {
5097                 if (kvm_vcpu_apicv_active(vcpu))
5098                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5099                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5100                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5101                 else
5102                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5103                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5104                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5105         }
5106
5107         if (cpu_has_vmx_msr_bitmap())
5108                 vmx_set_msr_bitmap(vcpu);
5109 }
5110
5111 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5112 {
5113         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5114
5115         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5116                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5117
5118         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5119                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5120 #ifdef CONFIG_X86_64
5121                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5122                                 CPU_BASED_CR8_LOAD_EXITING;
5123 #endif
5124         }
5125         if (!enable_ept)
5126                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5127                                 CPU_BASED_CR3_LOAD_EXITING  |
5128                                 CPU_BASED_INVLPG_EXITING;
5129         return exec_control;
5130 }
5131
5132 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5133 {
5134         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5135         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5136                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5137         if (vmx->vpid == 0)
5138                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5139         if (!enable_ept) {
5140                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5141                 enable_unrestricted_guest = 0;
5142                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5143                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5144         }
5145         if (!enable_unrestricted_guest)
5146                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5147         if (!ple_gap)
5148                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5149         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5150                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5151                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5152         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5153         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5154            (handle_vmptrld).
5155            We can NOT enable shadow_vmcs here because we don't have yet
5156            a current VMCS12
5157         */
5158         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5159
5160         if (!enable_pml)
5161                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5162
5163         return exec_control;
5164 }
5165
5166 static void ept_set_mmio_spte_mask(void)
5167 {
5168         /*
5169          * EPT Misconfigurations can be generated if the value of bits 2:0
5170          * of an EPT paging-structure entry is 110b (write/execute).
5171          */
5172         kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
5173 }
5174
5175 #define VMX_XSS_EXIT_BITMAP 0
5176 /*
5177  * Sets up the vmcs for emulated real mode.
5178  */
5179 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5180 {
5181 #ifdef CONFIG_X86_64
5182         unsigned long a;
5183 #endif
5184         int i;
5185
5186         /* I/O */
5187         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5188         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5189
5190         if (enable_shadow_vmcs) {
5191                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5192                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5193         }
5194         if (cpu_has_vmx_msr_bitmap())
5195                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5196
5197         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5198
5199         /* Control */
5200         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5201         vmx->hv_deadline_tsc = -1;
5202
5203         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5204
5205         if (cpu_has_secondary_exec_ctrls()) {
5206                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5207                                 vmx_secondary_exec_control(vmx));
5208         }
5209
5210         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5211                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5212                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5213                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5214                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5215
5216                 vmcs_write16(GUEST_INTR_STATUS, 0);
5217
5218                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5219                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5220         }
5221
5222         if (ple_gap) {
5223                 vmcs_write32(PLE_GAP, ple_gap);
5224                 vmx->ple_window = ple_window;
5225                 vmx->ple_window_dirty = true;
5226         }
5227
5228         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5229         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5230         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5231
5232         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5233         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5234         vmx_set_constant_host_state(vmx);
5235 #ifdef CONFIG_X86_64
5236         rdmsrl(MSR_FS_BASE, a);
5237         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5238         rdmsrl(MSR_GS_BASE, a);
5239         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5240 #else
5241         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5242         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5243 #endif
5244
5245         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5246         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5247         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5248         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5249         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5250
5251         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5252                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5253
5254         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5255                 u32 index = vmx_msr_index[i];
5256                 u32 data_low, data_high;
5257                 int j = vmx->nmsrs;
5258
5259                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5260                         continue;
5261                 if (wrmsr_safe(index, data_low, data_high) < 0)
5262                         continue;
5263                 vmx->guest_msrs[j].index = i;
5264                 vmx->guest_msrs[j].data = 0;
5265                 vmx->guest_msrs[j].mask = -1ull;
5266                 ++vmx->nmsrs;
5267         }
5268
5269
5270         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5271
5272         /* 22.2.1, 20.8.1 */
5273         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5274
5275         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5276         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5277
5278         set_cr4_guest_host_mask(vmx);
5279
5280         if (vmx_xsaves_supported())
5281                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5282
5283         if (enable_pml) {
5284                 ASSERT(vmx->pml_pg);
5285                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5286                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5287         }
5288
5289         return 0;
5290 }
5291
5292 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5293 {
5294         struct vcpu_vmx *vmx = to_vmx(vcpu);
5295         struct msr_data apic_base_msr;
5296         u64 cr0;
5297
5298         vmx->rmode.vm86_active = 0;
5299
5300         vmx->soft_vnmi_blocked = 0;
5301
5302         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5303         kvm_set_cr8(vcpu, 0);
5304
5305         if (!init_event) {
5306                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5307                                      MSR_IA32_APICBASE_ENABLE;
5308                 if (kvm_vcpu_is_reset_bsp(vcpu))
5309                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5310                 apic_base_msr.host_initiated = true;
5311                 kvm_set_apic_base(vcpu, &apic_base_msr);
5312         }
5313
5314         vmx_segment_cache_clear(vmx);
5315
5316         seg_setup(VCPU_SREG_CS);
5317         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5318         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5319
5320         seg_setup(VCPU_SREG_DS);
5321         seg_setup(VCPU_SREG_ES);
5322         seg_setup(VCPU_SREG_FS);
5323         seg_setup(VCPU_SREG_GS);
5324         seg_setup(VCPU_SREG_SS);
5325
5326         vmcs_write16(GUEST_TR_SELECTOR, 0);
5327         vmcs_writel(GUEST_TR_BASE, 0);
5328         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5329         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5330
5331         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5332         vmcs_writel(GUEST_LDTR_BASE, 0);
5333         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5334         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5335
5336         if (!init_event) {
5337                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5338                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5339                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5340                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5341         }
5342
5343         vmcs_writel(GUEST_RFLAGS, 0x02);
5344         kvm_rip_write(vcpu, 0xfff0);
5345
5346         vmcs_writel(GUEST_GDTR_BASE, 0);
5347         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5348
5349         vmcs_writel(GUEST_IDTR_BASE, 0);
5350         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5351
5352         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5353         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5354         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5355
5356         setup_msrs(vmx);
5357
5358         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5359
5360         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5361                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5362                 if (cpu_need_tpr_shadow(vcpu))
5363                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5364                                      __pa(vcpu->arch.apic->regs));
5365                 vmcs_write32(TPR_THRESHOLD, 0);
5366         }
5367
5368         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5369
5370         if (kvm_vcpu_apicv_active(vcpu))
5371                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5372
5373         if (vmx->vpid != 0)
5374                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5375
5376         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5377         vmx->vcpu.arch.cr0 = cr0;
5378         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5379         vmx_set_cr4(vcpu, 0);
5380         vmx_set_efer(vcpu, 0);
5381
5382         update_exception_bitmap(vcpu);
5383
5384         vpid_sync_context(vmx->vpid);
5385 }
5386
5387 /*
5388  * In nested virtualization, check if L1 asked to exit on external interrupts.
5389  * For most existing hypervisors, this will always return true.
5390  */
5391 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5392 {
5393         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5394                 PIN_BASED_EXT_INTR_MASK;
5395 }
5396
5397 /*
5398  * In nested virtualization, check if L1 has set
5399  * VM_EXIT_ACK_INTR_ON_EXIT
5400  */
5401 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5402 {
5403         return get_vmcs12(vcpu)->vm_exit_controls &
5404                 VM_EXIT_ACK_INTR_ON_EXIT;
5405 }
5406
5407 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5408 {
5409         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5410                 PIN_BASED_NMI_EXITING;
5411 }
5412
5413 static void enable_irq_window(struct kvm_vcpu *vcpu)
5414 {
5415         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5416                       CPU_BASED_VIRTUAL_INTR_PENDING);
5417 }
5418
5419 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5420 {
5421         if (!cpu_has_virtual_nmis() ||
5422             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5423                 enable_irq_window(vcpu);
5424                 return;
5425         }
5426
5427         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5428                       CPU_BASED_VIRTUAL_NMI_PENDING);
5429 }
5430
5431 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5432 {
5433         struct vcpu_vmx *vmx = to_vmx(vcpu);
5434         uint32_t intr;
5435         int irq = vcpu->arch.interrupt.nr;
5436
5437         trace_kvm_inj_virq(irq);
5438
5439         ++vcpu->stat.irq_injections;
5440         if (vmx->rmode.vm86_active) {
5441                 int inc_eip = 0;
5442                 if (vcpu->arch.interrupt.soft)
5443                         inc_eip = vcpu->arch.event_exit_inst_len;
5444                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5445                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5446                 return;
5447         }
5448         intr = irq | INTR_INFO_VALID_MASK;
5449         if (vcpu->arch.interrupt.soft) {
5450                 intr |= INTR_TYPE_SOFT_INTR;
5451                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5452                              vmx->vcpu.arch.event_exit_inst_len);
5453         } else
5454                 intr |= INTR_TYPE_EXT_INTR;
5455         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5456 }
5457
5458 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5459 {
5460         struct vcpu_vmx *vmx = to_vmx(vcpu);
5461
5462         if (!is_guest_mode(vcpu)) {
5463                 if (!cpu_has_virtual_nmis()) {
5464                         /*
5465                          * Tracking the NMI-blocked state in software is built upon
5466                          * finding the next open IRQ window. This, in turn, depends on
5467                          * well-behaving guests: They have to keep IRQs disabled at
5468                          * least as long as the NMI handler runs. Otherwise we may
5469                          * cause NMI nesting, maybe breaking the guest. But as this is
5470                          * highly unlikely, we can live with the residual risk.
5471                          */
5472                         vmx->soft_vnmi_blocked = 1;
5473                         vmx->vnmi_blocked_time = 0;
5474                 }
5475
5476                 ++vcpu->stat.nmi_injections;
5477                 vmx->nmi_known_unmasked = false;
5478         }
5479
5480         if (vmx->rmode.vm86_active) {
5481                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5482                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5483                 return;
5484         }
5485
5486         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5487                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5488 }
5489
5490 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5491 {
5492         if (!cpu_has_virtual_nmis())
5493                 return to_vmx(vcpu)->soft_vnmi_blocked;
5494         if (to_vmx(vcpu)->nmi_known_unmasked)
5495                 return false;
5496         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5497 }
5498
5499 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5500 {
5501         struct vcpu_vmx *vmx = to_vmx(vcpu);
5502
5503         if (!cpu_has_virtual_nmis()) {
5504                 if (vmx->soft_vnmi_blocked != masked) {
5505                         vmx->soft_vnmi_blocked = masked;
5506                         vmx->vnmi_blocked_time = 0;
5507                 }
5508         } else {
5509                 vmx->nmi_known_unmasked = !masked;
5510                 if (masked)
5511                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5512                                       GUEST_INTR_STATE_NMI);
5513                 else
5514                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5515                                         GUEST_INTR_STATE_NMI);
5516         }
5517 }
5518
5519 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5520 {
5521         if (to_vmx(vcpu)->nested.nested_run_pending)
5522                 return 0;
5523
5524         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5525                 return 0;
5526
5527         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5528                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5529                    | GUEST_INTR_STATE_NMI));
5530 }
5531
5532 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5533 {
5534         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5535                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5536                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5537                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5538 }
5539
5540 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5541 {
5542         int ret;
5543
5544         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5545                                     PAGE_SIZE * 3);
5546         if (ret)
5547                 return ret;
5548         kvm->arch.tss_addr = addr;
5549         return init_rmode_tss(kvm);
5550 }
5551
5552 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5553 {
5554         switch (vec) {
5555         case BP_VECTOR:
5556                 /*
5557                  * Update instruction length as we may reinject the exception
5558                  * from user space while in guest debugging mode.
5559                  */
5560                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5561                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5562                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5563                         return false;
5564                 /* fall through */
5565         case DB_VECTOR:
5566                 if (vcpu->guest_debug &
5567                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5568                         return false;
5569                 /* fall through */
5570         case DE_VECTOR:
5571         case OF_VECTOR:
5572         case BR_VECTOR:
5573         case UD_VECTOR:
5574         case DF_VECTOR:
5575         case SS_VECTOR:
5576         case GP_VECTOR:
5577         case MF_VECTOR:
5578                 return true;
5579         break;
5580         }
5581         return false;
5582 }
5583
5584 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5585                                   int vec, u32 err_code)
5586 {
5587         /*
5588          * Instruction with address size override prefix opcode 0x67
5589          * Cause the #SS fault with 0 error code in VM86 mode.
5590          */
5591         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5592                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5593                         if (vcpu->arch.halt_request) {
5594                                 vcpu->arch.halt_request = 0;
5595                                 return kvm_vcpu_halt(vcpu);
5596                         }
5597                         return 1;
5598                 }
5599                 return 0;
5600         }
5601
5602         /*
5603          * Forward all other exceptions that are valid in real mode.
5604          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5605          *        the required debugging infrastructure rework.
5606          */
5607         kvm_queue_exception(vcpu, vec);
5608         return 1;
5609 }
5610
5611 /*
5612  * Trigger machine check on the host. We assume all the MSRs are already set up
5613  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5614  * We pass a fake environment to the machine check handler because we want
5615  * the guest to be always treated like user space, no matter what context
5616  * it used internally.
5617  */
5618 static void kvm_machine_check(void)
5619 {
5620 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5621         struct pt_regs regs = {
5622                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5623                 .flags = X86_EFLAGS_IF,
5624         };
5625
5626         do_machine_check(&regs, 0);
5627 #endif
5628 }
5629
5630 static int handle_machine_check(struct kvm_vcpu *vcpu)
5631 {
5632         /* already handled by vcpu_run */
5633         return 1;
5634 }
5635
5636 static int handle_exception(struct kvm_vcpu *vcpu)
5637 {
5638         struct vcpu_vmx *vmx = to_vmx(vcpu);
5639         struct kvm_run *kvm_run = vcpu->run;
5640         u32 intr_info, ex_no, error_code;
5641         unsigned long cr2, rip, dr6;
5642         u32 vect_info;
5643         enum emulation_result er;
5644
5645         vect_info = vmx->idt_vectoring_info;
5646         intr_info = vmx->exit_intr_info;
5647
5648         if (is_machine_check(intr_info))
5649                 return handle_machine_check(vcpu);
5650
5651         if (is_nmi(intr_info))
5652                 return 1;  /* already handled by vmx_vcpu_run() */
5653
5654         if (is_invalid_opcode(intr_info)) {
5655                 if (is_guest_mode(vcpu)) {
5656                         kvm_queue_exception(vcpu, UD_VECTOR);
5657                         return 1;
5658                 }
5659                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5660                 if (er != EMULATE_DONE)
5661                         kvm_queue_exception(vcpu, UD_VECTOR);
5662                 return 1;
5663         }
5664
5665         error_code = 0;
5666         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5667                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5668
5669         /*
5670          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5671          * MMIO, it is better to report an internal error.
5672          * See the comments in vmx_handle_exit.
5673          */
5674         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5675             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5676                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5677                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5678                 vcpu->run->internal.ndata = 3;
5679                 vcpu->run->internal.data[0] = vect_info;
5680                 vcpu->run->internal.data[1] = intr_info;
5681                 vcpu->run->internal.data[2] = error_code;
5682                 return 0;
5683         }
5684
5685         if (is_page_fault(intr_info)) {
5686                 /* EPT won't cause page fault directly */
5687                 BUG_ON(enable_ept);
5688                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5689                 trace_kvm_page_fault(cr2, error_code);
5690
5691                 if (kvm_event_needs_reinjection(vcpu))
5692                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5693                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5694         }
5695
5696         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5697
5698         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5699                 return handle_rmode_exception(vcpu, ex_no, error_code);
5700
5701         switch (ex_no) {
5702         case AC_VECTOR:
5703                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5704                 return 1;
5705         case DB_VECTOR:
5706                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5707                 if (!(vcpu->guest_debug &
5708                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5709                         vcpu->arch.dr6 &= ~15;
5710                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5711                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5712                                 skip_emulated_instruction(vcpu);
5713
5714                         kvm_queue_exception(vcpu, DB_VECTOR);
5715                         return 1;
5716                 }
5717                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5718                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5719                 /* fall through */
5720         case BP_VECTOR:
5721                 /*
5722                  * Update instruction length as we may reinject #BP from
5723                  * user space while in guest debugging mode. Reading it for
5724                  * #DB as well causes no harm, it is not used in that case.
5725                  */
5726                 vmx->vcpu.arch.event_exit_inst_len =
5727                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5728                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5729                 rip = kvm_rip_read(vcpu);
5730                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5731                 kvm_run->debug.arch.exception = ex_no;
5732                 break;
5733         default:
5734                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5735                 kvm_run->ex.exception = ex_no;
5736                 kvm_run->ex.error_code = error_code;
5737                 break;
5738         }
5739         return 0;
5740 }
5741
5742 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5743 {
5744         ++vcpu->stat.irq_exits;
5745         return 1;
5746 }
5747
5748 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5749 {
5750         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5751         return 0;
5752 }
5753
5754 static int handle_io(struct kvm_vcpu *vcpu)
5755 {
5756         unsigned long exit_qualification;
5757         int size, in, string, ret;
5758         unsigned port;
5759
5760         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5761         string = (exit_qualification & 16) != 0;
5762         in = (exit_qualification & 8) != 0;
5763
5764         ++vcpu->stat.io_exits;
5765
5766         if (string || in)
5767                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5768
5769         port = exit_qualification >> 16;
5770         size = (exit_qualification & 7) + 1;
5771
5772         ret = kvm_skip_emulated_instruction(vcpu);
5773
5774         /*
5775          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5776          * KVM_EXIT_DEBUG here.
5777          */
5778         return kvm_fast_pio_out(vcpu, size, port) && ret;
5779 }
5780
5781 static void
5782 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5783 {
5784         /*
5785          * Patch in the VMCALL instruction:
5786          */
5787         hypercall[0] = 0x0f;
5788         hypercall[1] = 0x01;
5789         hypercall[2] = 0xc1;
5790 }
5791
5792 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5793 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5794 {
5795         if (is_guest_mode(vcpu)) {
5796                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5797                 unsigned long orig_val = val;
5798
5799                 /*
5800                  * We get here when L2 changed cr0 in a way that did not change
5801                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5802                  * but did change L0 shadowed bits. So we first calculate the
5803                  * effective cr0 value that L1 would like to write into the
5804                  * hardware. It consists of the L2-owned bits from the new
5805                  * value combined with the L1-owned bits from L1's guest_cr0.
5806                  */
5807                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5808                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5809
5810                 if (!nested_guest_cr0_valid(vcpu, val))
5811                         return 1;
5812
5813                 if (kvm_set_cr0(vcpu, val))
5814                         return 1;
5815                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5816                 return 0;
5817         } else {
5818                 if (to_vmx(vcpu)->nested.vmxon &&
5819                     !nested_host_cr0_valid(vcpu, val))
5820                         return 1;
5821
5822                 return kvm_set_cr0(vcpu, val);
5823         }
5824 }
5825
5826 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5827 {
5828         if (is_guest_mode(vcpu)) {
5829                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5830                 unsigned long orig_val = val;
5831
5832                 /* analogously to handle_set_cr0 */
5833                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5834                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5835                 if (kvm_set_cr4(vcpu, val))
5836                         return 1;
5837                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5838                 return 0;
5839         } else
5840                 return kvm_set_cr4(vcpu, val);
5841 }
5842
5843 static int handle_cr(struct kvm_vcpu *vcpu)
5844 {
5845         unsigned long exit_qualification, val;
5846         int cr;
5847         int reg;
5848         int err;
5849         int ret;
5850
5851         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5852         cr = exit_qualification & 15;
5853         reg = (exit_qualification >> 8) & 15;
5854         switch ((exit_qualification >> 4) & 3) {
5855         case 0: /* mov to cr */
5856                 val = kvm_register_readl(vcpu, reg);
5857                 trace_kvm_cr_write(cr, val);
5858                 switch (cr) {
5859                 case 0:
5860                         err = handle_set_cr0(vcpu, val);
5861                         return kvm_complete_insn_gp(vcpu, err);
5862                 case 3:
5863                         err = kvm_set_cr3(vcpu, val);
5864                         return kvm_complete_insn_gp(vcpu, err);
5865                 case 4:
5866                         err = handle_set_cr4(vcpu, val);
5867                         return kvm_complete_insn_gp(vcpu, err);
5868                 case 8: {
5869                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5870                                 u8 cr8 = (u8)val;
5871                                 err = kvm_set_cr8(vcpu, cr8);
5872                                 ret = kvm_complete_insn_gp(vcpu, err);
5873                                 if (lapic_in_kernel(vcpu))
5874                                         return ret;
5875                                 if (cr8_prev <= cr8)
5876                                         return ret;
5877                                 /*
5878                                  * TODO: we might be squashing a
5879                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5880                                  * KVM_EXIT_DEBUG here.
5881                                  */
5882                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5883                                 return 0;
5884                         }
5885                 }
5886                 break;
5887         case 2: /* clts */
5888                 WARN_ONCE(1, "Guest should always own CR0.TS");
5889                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5890                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5891                 return kvm_skip_emulated_instruction(vcpu);
5892         case 1: /*mov from cr*/
5893                 switch (cr) {
5894                 case 3:
5895                         val = kvm_read_cr3(vcpu);
5896                         kvm_register_write(vcpu, reg, val);
5897                         trace_kvm_cr_read(cr, val);
5898                         return kvm_skip_emulated_instruction(vcpu);
5899                 case 8:
5900                         val = kvm_get_cr8(vcpu);
5901                         kvm_register_write(vcpu, reg, val);
5902                         trace_kvm_cr_read(cr, val);
5903                         return kvm_skip_emulated_instruction(vcpu);
5904                 }
5905                 break;
5906         case 3: /* lmsw */
5907                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5908                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5909                 kvm_lmsw(vcpu, val);
5910
5911                 return kvm_skip_emulated_instruction(vcpu);
5912         default:
5913                 break;
5914         }
5915         vcpu->run->exit_reason = 0;
5916         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5917                (int)(exit_qualification >> 4) & 3, cr);
5918         return 0;
5919 }
5920
5921 static int handle_dr(struct kvm_vcpu *vcpu)
5922 {
5923         unsigned long exit_qualification;
5924         int dr, dr7, reg;
5925
5926         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5927         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5928
5929         /* First, if DR does not exist, trigger UD */
5930         if (!kvm_require_dr(vcpu, dr))
5931                 return 1;
5932
5933         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5934         if (!kvm_require_cpl(vcpu, 0))
5935                 return 1;
5936         dr7 = vmcs_readl(GUEST_DR7);
5937         if (dr7 & DR7_GD) {
5938                 /*
5939                  * As the vm-exit takes precedence over the debug trap, we
5940                  * need to emulate the latter, either for the host or the
5941                  * guest debugging itself.
5942                  */
5943                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5944                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5945                         vcpu->run->debug.arch.dr7 = dr7;
5946                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5947                         vcpu->run->debug.arch.exception = DB_VECTOR;
5948                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5949                         return 0;
5950                 } else {
5951                         vcpu->arch.dr6 &= ~15;
5952                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5953                         kvm_queue_exception(vcpu, DB_VECTOR);
5954                         return 1;
5955                 }
5956         }
5957
5958         if (vcpu->guest_debug == 0) {
5959                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5960                                 CPU_BASED_MOV_DR_EXITING);
5961
5962                 /*
5963                  * No more DR vmexits; force a reload of the debug registers
5964                  * and reenter on this instruction.  The next vmexit will
5965                  * retrieve the full state of the debug registers.
5966                  */
5967                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5968                 return 1;
5969         }
5970
5971         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5972         if (exit_qualification & TYPE_MOV_FROM_DR) {
5973                 unsigned long val;
5974
5975                 if (kvm_get_dr(vcpu, dr, &val))
5976                         return 1;
5977                 kvm_register_write(vcpu, reg, val);
5978         } else
5979                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5980                         return 1;
5981
5982         return kvm_skip_emulated_instruction(vcpu);
5983 }
5984
5985 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5986 {
5987         return vcpu->arch.dr6;
5988 }
5989
5990 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5991 {
5992 }
5993
5994 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5995 {
5996         get_debugreg(vcpu->arch.db[0], 0);
5997         get_debugreg(vcpu->arch.db[1], 1);
5998         get_debugreg(vcpu->arch.db[2], 2);
5999         get_debugreg(vcpu->arch.db[3], 3);
6000         get_debugreg(vcpu->arch.dr6, 6);
6001         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
6002
6003         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
6004         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
6005 }
6006
6007 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
6008 {
6009         vmcs_writel(GUEST_DR7, val);
6010 }
6011
6012 static int handle_cpuid(struct kvm_vcpu *vcpu)
6013 {
6014         return kvm_emulate_cpuid(vcpu);
6015 }
6016
6017 static int handle_rdmsr(struct kvm_vcpu *vcpu)
6018 {
6019         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6020         struct msr_data msr_info;
6021
6022         msr_info.index = ecx;
6023         msr_info.host_initiated = false;
6024         if (vmx_get_msr(vcpu, &msr_info)) {
6025                 trace_kvm_msr_read_ex(ecx);
6026                 kvm_inject_gp(vcpu, 0);
6027                 return 1;
6028         }
6029
6030         trace_kvm_msr_read(ecx, msr_info.data);
6031
6032         /* FIXME: handling of bits 32:63 of rax, rdx */
6033         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6034         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6035         return kvm_skip_emulated_instruction(vcpu);
6036 }
6037
6038 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6039 {
6040         struct msr_data msr;
6041         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6042         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6043                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6044
6045         msr.data = data;
6046         msr.index = ecx;
6047         msr.host_initiated = false;
6048         if (kvm_set_msr(vcpu, &msr) != 0) {
6049                 trace_kvm_msr_write_ex(ecx, data);
6050                 kvm_inject_gp(vcpu, 0);
6051                 return 1;
6052         }
6053
6054         trace_kvm_msr_write(ecx, data);
6055         return kvm_skip_emulated_instruction(vcpu);
6056 }
6057
6058 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6059 {
6060         kvm_apic_update_ppr(vcpu);
6061         return 1;
6062 }
6063
6064 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6065 {
6066         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6067                         CPU_BASED_VIRTUAL_INTR_PENDING);
6068
6069         kvm_make_request(KVM_REQ_EVENT, vcpu);
6070
6071         ++vcpu->stat.irq_window_exits;
6072         return 1;
6073 }
6074
6075 static int handle_halt(struct kvm_vcpu *vcpu)
6076 {
6077         return kvm_emulate_halt(vcpu);
6078 }
6079
6080 static int handle_vmcall(struct kvm_vcpu *vcpu)
6081 {
6082         return kvm_emulate_hypercall(vcpu);
6083 }
6084
6085 static int handle_invd(struct kvm_vcpu *vcpu)
6086 {
6087         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6088 }
6089
6090 static int handle_invlpg(struct kvm_vcpu *vcpu)
6091 {
6092         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6093
6094         kvm_mmu_invlpg(vcpu, exit_qualification);
6095         return kvm_skip_emulated_instruction(vcpu);
6096 }
6097
6098 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6099 {
6100         int err;
6101
6102         err = kvm_rdpmc(vcpu);
6103         return kvm_complete_insn_gp(vcpu, err);
6104 }
6105
6106 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6107 {
6108         return kvm_emulate_wbinvd(vcpu);
6109 }
6110
6111 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6112 {
6113         u64 new_bv = kvm_read_edx_eax(vcpu);
6114         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6115
6116         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6117                 return kvm_skip_emulated_instruction(vcpu);
6118         return 1;
6119 }
6120
6121 static int handle_xsaves(struct kvm_vcpu *vcpu)
6122 {
6123         kvm_skip_emulated_instruction(vcpu);
6124         WARN(1, "this should never happen\n");
6125         return 1;
6126 }
6127
6128 static int handle_xrstors(struct kvm_vcpu *vcpu)
6129 {
6130         kvm_skip_emulated_instruction(vcpu);
6131         WARN(1, "this should never happen\n");
6132         return 1;
6133 }
6134
6135 static int handle_apic_access(struct kvm_vcpu *vcpu)
6136 {
6137         if (likely(fasteoi)) {
6138                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6139                 int access_type, offset;
6140
6141                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6142                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6143                 /*
6144                  * Sane guest uses MOV to write EOI, with written value
6145                  * not cared. So make a short-circuit here by avoiding
6146                  * heavy instruction emulation.
6147                  */
6148                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6149                     (offset == APIC_EOI)) {
6150                         kvm_lapic_set_eoi(vcpu);
6151                         return kvm_skip_emulated_instruction(vcpu);
6152                 }
6153         }
6154         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6155 }
6156
6157 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6158 {
6159         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6160         int vector = exit_qualification & 0xff;
6161
6162         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6163         kvm_apic_set_eoi_accelerated(vcpu, vector);
6164         return 1;
6165 }
6166
6167 static int handle_apic_write(struct kvm_vcpu *vcpu)
6168 {
6169         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6170         u32 offset = exit_qualification & 0xfff;
6171
6172         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6173         kvm_apic_write_nodecode(vcpu, offset);
6174         return 1;
6175 }
6176
6177 static int handle_task_switch(struct kvm_vcpu *vcpu)
6178 {
6179         struct vcpu_vmx *vmx = to_vmx(vcpu);
6180         unsigned long exit_qualification;
6181         bool has_error_code = false;
6182         u32 error_code = 0;
6183         u16 tss_selector;
6184         int reason, type, idt_v, idt_index;
6185
6186         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6187         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6188         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6189
6190         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6191
6192         reason = (u32)exit_qualification >> 30;
6193         if (reason == TASK_SWITCH_GATE && idt_v) {
6194                 switch (type) {
6195                 case INTR_TYPE_NMI_INTR:
6196                         vcpu->arch.nmi_injected = false;
6197                         vmx_set_nmi_mask(vcpu, true);
6198                         break;
6199                 case INTR_TYPE_EXT_INTR:
6200                 case INTR_TYPE_SOFT_INTR:
6201                         kvm_clear_interrupt_queue(vcpu);
6202                         break;
6203                 case INTR_TYPE_HARD_EXCEPTION:
6204                         if (vmx->idt_vectoring_info &
6205                             VECTORING_INFO_DELIVER_CODE_MASK) {
6206                                 has_error_code = true;
6207                                 error_code =
6208                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6209                         }
6210                         /* fall through */
6211                 case INTR_TYPE_SOFT_EXCEPTION:
6212                         kvm_clear_exception_queue(vcpu);
6213                         break;
6214                 default:
6215                         break;
6216                 }
6217         }
6218         tss_selector = exit_qualification;
6219
6220         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6221                        type != INTR_TYPE_EXT_INTR &&
6222                        type != INTR_TYPE_NMI_INTR))
6223                 skip_emulated_instruction(vcpu);
6224
6225         if (kvm_task_switch(vcpu, tss_selector,
6226                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6227                             has_error_code, error_code) == EMULATE_FAIL) {
6228                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6229                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6230                 vcpu->run->internal.ndata = 0;
6231                 return 0;
6232         }
6233
6234         /*
6235          * TODO: What about debug traps on tss switch?
6236          *       Are we supposed to inject them and update dr6?
6237          */
6238
6239         return 1;
6240 }
6241
6242 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6243 {
6244         unsigned long exit_qualification;
6245         gpa_t gpa;
6246         u32 error_code;
6247         int gla_validity;
6248
6249         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6250
6251         gla_validity = (exit_qualification >> 7) & 0x3;
6252         if (gla_validity == 0x2) {
6253                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6254                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6255                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6256                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6257                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6258                         (long unsigned int)exit_qualification);
6259                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6260                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6261                 return 0;
6262         }
6263
6264         /*
6265          * EPT violation happened while executing iret from NMI,
6266          * "blocked by NMI" bit has to be set before next VM entry.
6267          * There are errata that may cause this bit to not be set:
6268          * AAK134, BY25.
6269          */
6270         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6271                         cpu_has_virtual_nmis() &&
6272                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6273                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6274
6275         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6276         trace_kvm_page_fault(gpa, exit_qualification);
6277
6278         /* Is it a read fault? */
6279         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6280                      ? PFERR_USER_MASK : 0;
6281         /* Is it a write fault? */
6282         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6283                       ? PFERR_WRITE_MASK : 0;
6284         /* Is it a fetch fault? */
6285         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6286                       ? PFERR_FETCH_MASK : 0;
6287         /* ept page table entry is present? */
6288         error_code |= (exit_qualification &
6289                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6290                         EPT_VIOLATION_EXECUTABLE))
6291                       ? PFERR_PRESENT_MASK : 0;
6292
6293         vcpu->arch.gpa_available = true;
6294         vcpu->arch.exit_qualification = exit_qualification;
6295
6296         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6297 }
6298
6299 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6300 {
6301         int ret;
6302         gpa_t gpa;
6303
6304         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6305         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6306                 trace_kvm_fast_mmio(gpa);
6307                 return kvm_skip_emulated_instruction(vcpu);
6308         }
6309
6310         ret = handle_mmio_page_fault(vcpu, gpa, true);
6311         vcpu->arch.gpa_available = true;
6312         if (likely(ret == RET_MMIO_PF_EMULATE))
6313                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6314                                               EMULATE_DONE;
6315
6316         if (unlikely(ret == RET_MMIO_PF_INVALID))
6317                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6318
6319         if (unlikely(ret == RET_MMIO_PF_RETRY))
6320                 return 1;
6321
6322         /* It is the real ept misconfig */
6323         WARN_ON(1);
6324
6325         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6326         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6327
6328         return 0;
6329 }
6330
6331 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6332 {
6333         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6334                         CPU_BASED_VIRTUAL_NMI_PENDING);
6335         ++vcpu->stat.nmi_window_exits;
6336         kvm_make_request(KVM_REQ_EVENT, vcpu);
6337
6338         return 1;
6339 }
6340
6341 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6342 {
6343         struct vcpu_vmx *vmx = to_vmx(vcpu);
6344         enum emulation_result err = EMULATE_DONE;
6345         int ret = 1;
6346         u32 cpu_exec_ctrl;
6347         bool intr_window_requested;
6348         unsigned count = 130;
6349
6350         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6351         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6352
6353         while (vmx->emulation_required && count-- != 0) {
6354                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6355                         return handle_interrupt_window(&vmx->vcpu);
6356
6357                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6358                         return 1;
6359
6360                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6361
6362                 if (err == EMULATE_USER_EXIT) {
6363                         ++vcpu->stat.mmio_exits;
6364                         ret = 0;
6365                         goto out;
6366                 }
6367
6368                 if (err != EMULATE_DONE) {
6369                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6370                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6371                         vcpu->run->internal.ndata = 0;
6372                         return 0;
6373                 }
6374
6375                 if (vcpu->arch.halt_request) {
6376                         vcpu->arch.halt_request = 0;
6377                         ret = kvm_vcpu_halt(vcpu);
6378                         goto out;
6379                 }
6380
6381                 if (signal_pending(current))
6382                         goto out;
6383                 if (need_resched())
6384                         schedule();
6385         }
6386
6387 out:
6388         return ret;
6389 }
6390
6391 static int __grow_ple_window(int val)
6392 {
6393         if (ple_window_grow < 1)
6394                 return ple_window;
6395
6396         val = min(val, ple_window_actual_max);
6397
6398         if (ple_window_grow < ple_window)
6399                 val *= ple_window_grow;
6400         else
6401                 val += ple_window_grow;
6402
6403         return val;
6404 }
6405
6406 static int __shrink_ple_window(int val, int modifier, int minimum)
6407 {
6408         if (modifier < 1)
6409                 return ple_window;
6410
6411         if (modifier < ple_window)
6412                 val /= modifier;
6413         else
6414                 val -= modifier;
6415
6416         return max(val, minimum);
6417 }
6418
6419 static void grow_ple_window(struct kvm_vcpu *vcpu)
6420 {
6421         struct vcpu_vmx *vmx = to_vmx(vcpu);
6422         int old = vmx->ple_window;
6423
6424         vmx->ple_window = __grow_ple_window(old);
6425
6426         if (vmx->ple_window != old)
6427                 vmx->ple_window_dirty = true;
6428
6429         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6430 }
6431
6432 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6433 {
6434         struct vcpu_vmx *vmx = to_vmx(vcpu);
6435         int old = vmx->ple_window;
6436
6437         vmx->ple_window = __shrink_ple_window(old,
6438                                               ple_window_shrink, ple_window);
6439
6440         if (vmx->ple_window != old)
6441                 vmx->ple_window_dirty = true;
6442
6443         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6444 }
6445
6446 /*
6447  * ple_window_actual_max is computed to be one grow_ple_window() below
6448  * ple_window_max. (See __grow_ple_window for the reason.)
6449  * This prevents overflows, because ple_window_max is int.
6450  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6451  * this process.
6452  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6453  */
6454 static void update_ple_window_actual_max(void)
6455 {
6456         ple_window_actual_max =
6457                         __shrink_ple_window(max(ple_window_max, ple_window),
6458                                             ple_window_grow, INT_MIN);
6459 }
6460
6461 /*
6462  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6463  */
6464 static void wakeup_handler(void)
6465 {
6466         struct kvm_vcpu *vcpu;
6467         int cpu = smp_processor_id();
6468
6469         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6470         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6471                         blocked_vcpu_list) {
6472                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6473
6474                 if (pi_test_on(pi_desc) == 1)
6475                         kvm_vcpu_kick(vcpu);
6476         }
6477         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6478 }
6479
6480 void vmx_enable_tdp(void)
6481 {
6482         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6483                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6484                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6485                 0ull, VMX_EPT_EXECUTABLE_MASK,
6486                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6487                 enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
6488
6489         ept_set_mmio_spte_mask();
6490         kvm_enable_tdp();
6491 }
6492
6493 static __init int hardware_setup(void)
6494 {
6495         int r = -ENOMEM, i, msr;
6496
6497         rdmsrl_safe(MSR_EFER, &host_efer);
6498
6499         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6500                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6501
6502         for (i = 0; i < VMX_BITMAP_NR; i++) {
6503                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6504                 if (!vmx_bitmap[i])
6505                         goto out;
6506         }
6507
6508         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6509         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6510         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6511
6512         /*
6513          * Allow direct access to the PC debug port (it is often used for I/O
6514          * delays, but the vmexits simply slow things down).
6515          */
6516         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6517         clear_bit(0x80, vmx_io_bitmap_a);
6518
6519         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6520
6521         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6522         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6523
6524         if (setup_vmcs_config(&vmcs_config) < 0) {
6525                 r = -EIO;
6526                 goto out;
6527         }
6528
6529         if (boot_cpu_has(X86_FEATURE_NX))
6530                 kvm_enable_efer_bits(EFER_NX);
6531
6532         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6533                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6534                 enable_vpid = 0;
6535
6536         if (!cpu_has_vmx_shadow_vmcs())
6537                 enable_shadow_vmcs = 0;
6538         if (enable_shadow_vmcs)
6539                 init_vmcs_shadow_fields();
6540
6541         if (!cpu_has_vmx_ept() ||
6542             !cpu_has_vmx_ept_4levels()) {
6543                 enable_ept = 0;
6544                 enable_unrestricted_guest = 0;
6545                 enable_ept_ad_bits = 0;
6546         }
6547
6548         if (!cpu_has_vmx_ept_ad_bits())
6549                 enable_ept_ad_bits = 0;
6550
6551         if (!cpu_has_vmx_unrestricted_guest())
6552                 enable_unrestricted_guest = 0;
6553
6554         if (!cpu_has_vmx_flexpriority())
6555                 flexpriority_enabled = 0;
6556
6557         /*
6558          * set_apic_access_page_addr() is used to reload apic access
6559          * page upon invalidation.  No need to do anything if not
6560          * using the APIC_ACCESS_ADDR VMCS field.
6561          */
6562         if (!flexpriority_enabled)
6563                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6564
6565         if (!cpu_has_vmx_tpr_shadow())
6566                 kvm_x86_ops->update_cr8_intercept = NULL;
6567
6568         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6569                 kvm_disable_largepages();
6570
6571         if (!cpu_has_vmx_ple())
6572                 ple_gap = 0;
6573
6574         if (!cpu_has_vmx_apicv()) {
6575                 enable_apicv = 0;
6576                 kvm_x86_ops->sync_pir_to_irr = NULL;
6577         }
6578
6579         if (cpu_has_vmx_tsc_scaling()) {
6580                 kvm_has_tsc_control = true;
6581                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6582                 kvm_tsc_scaling_ratio_frac_bits = 48;
6583         }
6584
6585         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6586         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6587         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6588         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6589         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6590         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6591         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6592
6593         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6594                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6595         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6596                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6597         memcpy(vmx_msr_bitmap_legacy_x2apic,
6598                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6599         memcpy(vmx_msr_bitmap_longmode_x2apic,
6600                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6601
6602         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6603
6604         for (msr = 0x800; msr <= 0x8ff; msr++) {
6605                 if (msr == 0x839 /* TMCCT */)
6606                         continue;
6607                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6608         }
6609
6610         /*
6611          * TPR reads and writes can be virtualized even if virtual interrupt
6612          * delivery is not in use.
6613          */
6614         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6615         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6616
6617         /* EOI */
6618         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6619         /* SELF-IPI */
6620         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6621
6622         if (enable_ept)
6623                 vmx_enable_tdp();
6624         else
6625                 kvm_disable_tdp();
6626
6627         update_ple_window_actual_max();
6628
6629         /*
6630          * Only enable PML when hardware supports PML feature, and both EPT
6631          * and EPT A/D bit features are enabled -- PML depends on them to work.
6632          */
6633         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6634                 enable_pml = 0;
6635
6636         if (!enable_pml) {
6637                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6638                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6639                 kvm_x86_ops->flush_log_dirty = NULL;
6640                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6641         }
6642
6643         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6644                 u64 vmx_msr;
6645
6646                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6647                 cpu_preemption_timer_multi =
6648                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6649         } else {
6650                 kvm_x86_ops->set_hv_timer = NULL;
6651                 kvm_x86_ops->cancel_hv_timer = NULL;
6652         }
6653
6654         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6655
6656         kvm_mce_cap_supported |= MCG_LMCE_P;
6657
6658         return alloc_kvm_area();
6659
6660 out:
6661         for (i = 0; i < VMX_BITMAP_NR; i++)
6662                 free_page((unsigned long)vmx_bitmap[i]);
6663
6664     return r;
6665 }
6666
6667 static __exit void hardware_unsetup(void)
6668 {
6669         int i;
6670
6671         for (i = 0; i < VMX_BITMAP_NR; i++)
6672                 free_page((unsigned long)vmx_bitmap[i]);
6673
6674         free_kvm_area();
6675 }
6676
6677 /*
6678  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6679  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6680  */
6681 static int handle_pause(struct kvm_vcpu *vcpu)
6682 {
6683         if (ple_gap)
6684                 grow_ple_window(vcpu);
6685
6686         kvm_vcpu_on_spin(vcpu);
6687         return kvm_skip_emulated_instruction(vcpu);
6688 }
6689
6690 static int handle_nop(struct kvm_vcpu *vcpu)
6691 {
6692         return kvm_skip_emulated_instruction(vcpu);
6693 }
6694
6695 static int handle_mwait(struct kvm_vcpu *vcpu)
6696 {
6697         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6698         return handle_nop(vcpu);
6699 }
6700
6701 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6702 {
6703         return 1;
6704 }
6705
6706 static int handle_monitor(struct kvm_vcpu *vcpu)
6707 {
6708         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6709         return handle_nop(vcpu);
6710 }
6711
6712 /*
6713  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6714  * We could reuse a single VMCS for all the L2 guests, but we also want the
6715  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6716  * allows keeping them loaded on the processor, and in the future will allow
6717  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6718  * every entry if they never change.
6719  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6720  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6721  *
6722  * The following functions allocate and free a vmcs02 in this pool.
6723  */
6724
6725 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6726 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6727 {
6728         struct vmcs02_list *item;
6729         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6730                 if (item->vmptr == vmx->nested.current_vmptr) {
6731                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6732                         return &item->vmcs02;
6733                 }
6734
6735         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6736                 /* Recycle the least recently used VMCS. */
6737                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6738                                        struct vmcs02_list, list);
6739                 item->vmptr = vmx->nested.current_vmptr;
6740                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6741                 return &item->vmcs02;
6742         }
6743
6744         /* Create a new VMCS */
6745         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6746         if (!item)
6747                 return NULL;
6748         item->vmcs02.vmcs = alloc_vmcs();
6749         item->vmcs02.shadow_vmcs = NULL;
6750         if (!item->vmcs02.vmcs) {
6751                 kfree(item);
6752                 return NULL;
6753         }
6754         loaded_vmcs_init(&item->vmcs02);
6755         item->vmptr = vmx->nested.current_vmptr;
6756         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6757         vmx->nested.vmcs02_num++;
6758         return &item->vmcs02;
6759 }
6760
6761 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6762 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6763 {
6764         struct vmcs02_list *item;
6765         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6766                 if (item->vmptr == vmptr) {
6767                         free_loaded_vmcs(&item->vmcs02);
6768                         list_del(&item->list);
6769                         kfree(item);
6770                         vmx->nested.vmcs02_num--;
6771                         return;
6772                 }
6773 }
6774
6775 /*
6776  * Free all VMCSs saved for this vcpu, except the one pointed by
6777  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6778  * must be &vmx->vmcs01.
6779  */
6780 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6781 {
6782         struct vmcs02_list *item, *n;
6783
6784         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6785         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6786                 /*
6787                  * Something will leak if the above WARN triggers.  Better than
6788                  * a use-after-free.
6789                  */
6790                 if (vmx->loaded_vmcs == &item->vmcs02)
6791                         continue;
6792
6793                 free_loaded_vmcs(&item->vmcs02);
6794                 list_del(&item->list);
6795                 kfree(item);
6796                 vmx->nested.vmcs02_num--;
6797         }
6798 }
6799
6800 /*
6801  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6802  * set the success or error code of an emulated VMX instruction, as specified
6803  * by Vol 2B, VMX Instruction Reference, "Conventions".
6804  */
6805 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6806 {
6807         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6808                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6809                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6810 }
6811
6812 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6813 {
6814         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6815                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6816                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6817                         | X86_EFLAGS_CF);
6818 }
6819
6820 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6821                                         u32 vm_instruction_error)
6822 {
6823         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6824                 /*
6825                  * failValid writes the error number to the current VMCS, which
6826                  * can't be done there isn't a current VMCS.
6827                  */
6828                 nested_vmx_failInvalid(vcpu);
6829                 return;
6830         }
6831         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6832                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6833                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6834                         | X86_EFLAGS_ZF);
6835         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6836         /*
6837          * We don't need to force a shadow sync because
6838          * VM_INSTRUCTION_ERROR is not shadowed
6839          */
6840 }
6841
6842 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6843 {
6844         /* TODO: not to reset guest simply here. */
6845         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6846         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6847 }
6848
6849 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6850 {
6851         struct vcpu_vmx *vmx =
6852                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6853
6854         vmx->nested.preemption_timer_expired = true;
6855         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6856         kvm_vcpu_kick(&vmx->vcpu);
6857
6858         return HRTIMER_NORESTART;
6859 }
6860
6861 /*
6862  * Decode the memory-address operand of a vmx instruction, as recorded on an
6863  * exit caused by such an instruction (run by a guest hypervisor).
6864  * On success, returns 0. When the operand is invalid, returns 1 and throws
6865  * #UD or #GP.
6866  */
6867 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6868                                  unsigned long exit_qualification,
6869                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6870 {
6871         gva_t off;
6872         bool exn;
6873         struct kvm_segment s;
6874
6875         /*
6876          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6877          * Execution", on an exit, vmx_instruction_info holds most of the
6878          * addressing components of the operand. Only the displacement part
6879          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6880          * For how an actual address is calculated from all these components,
6881          * refer to Vol. 1, "Operand Addressing".
6882          */
6883         int  scaling = vmx_instruction_info & 3;
6884         int  addr_size = (vmx_instruction_info >> 7) & 7;
6885         bool is_reg = vmx_instruction_info & (1u << 10);
6886         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6887         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6888         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6889         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6890         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6891
6892         if (is_reg) {
6893                 kvm_queue_exception(vcpu, UD_VECTOR);
6894                 return 1;
6895         }
6896
6897         /* Addr = segment_base + offset */
6898         /* offset = base + [index * scale] + displacement */
6899         off = exit_qualification; /* holds the displacement */
6900         if (base_is_valid)
6901                 off += kvm_register_read(vcpu, base_reg);
6902         if (index_is_valid)
6903                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6904         vmx_get_segment(vcpu, &s, seg_reg);
6905         *ret = s.base + off;
6906
6907         if (addr_size == 1) /* 32 bit */
6908                 *ret &= 0xffffffff;
6909
6910         /* Checks for #GP/#SS exceptions. */
6911         exn = false;
6912         if (is_long_mode(vcpu)) {
6913                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6914                  * non-canonical form. This is the only check on the memory
6915                  * destination for long mode!
6916                  */
6917                 exn = is_noncanonical_address(*ret);
6918         } else if (is_protmode(vcpu)) {
6919                 /* Protected mode: apply checks for segment validity in the
6920                  * following order:
6921                  * - segment type check (#GP(0) may be thrown)
6922                  * - usability check (#GP(0)/#SS(0))
6923                  * - limit check (#GP(0)/#SS(0))
6924                  */
6925                 if (wr)
6926                         /* #GP(0) if the destination operand is located in a
6927                          * read-only data segment or any code segment.
6928                          */
6929                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6930                 else
6931                         /* #GP(0) if the source operand is located in an
6932                          * execute-only code segment
6933                          */
6934                         exn = ((s.type & 0xa) == 8);
6935                 if (exn) {
6936                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6937                         return 1;
6938                 }
6939                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6940                  */
6941                 exn = (s.unusable != 0);
6942                 /* Protected mode: #GP(0)/#SS(0) if the memory
6943                  * operand is outside the segment limit.
6944                  */
6945                 exn = exn || (off + sizeof(u64) > s.limit);
6946         }
6947         if (exn) {
6948                 kvm_queue_exception_e(vcpu,
6949                                       seg_reg == VCPU_SREG_SS ?
6950                                                 SS_VECTOR : GP_VECTOR,
6951                                       0);
6952                 return 1;
6953         }
6954
6955         return 0;
6956 }
6957
6958 /*
6959  * This function performs the various checks including
6960  * - if it's 4KB aligned
6961  * - No bits beyond the physical address width are set
6962  * - Returns 0 on success or else 1
6963  * (Intel SDM Section 30.3)
6964  */
6965 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6966                                   gpa_t *vmpointer)
6967 {
6968         gva_t gva;
6969         gpa_t vmptr;
6970         struct x86_exception e;
6971         struct page *page;
6972         struct vcpu_vmx *vmx = to_vmx(vcpu);
6973         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6974
6975         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6976                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6977                 return 1;
6978
6979         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6980                                 sizeof(vmptr), &e)) {
6981                 kvm_inject_page_fault(vcpu, &e);
6982                 return 1;
6983         }
6984
6985         switch (exit_reason) {
6986         case EXIT_REASON_VMON:
6987                 /*
6988                  * SDM 3: 24.11.5
6989                  * The first 4 bytes of VMXON region contain the supported
6990                  * VMCS revision identifier
6991                  *
6992                  * Note - IA32_VMX_BASIC[48] will never be 1
6993                  * for the nested case;
6994                  * which replaces physical address width with 32
6995                  *
6996                  */
6997                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6998                         nested_vmx_failInvalid(vcpu);
6999                         return kvm_skip_emulated_instruction(vcpu);
7000                 }
7001
7002                 page = nested_get_page(vcpu, vmptr);
7003                 if (page == NULL) {
7004                         nested_vmx_failInvalid(vcpu);
7005                         return kvm_skip_emulated_instruction(vcpu);
7006                 }
7007                 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7008                         kunmap(page);
7009                         nested_release_page_clean(page);
7010                         nested_vmx_failInvalid(vcpu);
7011                         return kvm_skip_emulated_instruction(vcpu);
7012                 }
7013                 kunmap(page);
7014                 nested_release_page_clean(page);
7015                 vmx->nested.vmxon_ptr = vmptr;
7016                 break;
7017         case EXIT_REASON_VMCLEAR:
7018                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7019                         nested_vmx_failValid(vcpu,
7020                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
7021                         return kvm_skip_emulated_instruction(vcpu);
7022                 }
7023
7024                 if (vmptr == vmx->nested.vmxon_ptr) {
7025                         nested_vmx_failValid(vcpu,
7026                                              VMXERR_VMCLEAR_VMXON_POINTER);
7027                         return kvm_skip_emulated_instruction(vcpu);
7028                 }
7029                 break;
7030         case EXIT_REASON_VMPTRLD:
7031                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
7032                         nested_vmx_failValid(vcpu,
7033                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
7034                         return kvm_skip_emulated_instruction(vcpu);
7035                 }
7036
7037                 if (vmptr == vmx->nested.vmxon_ptr) {
7038                         nested_vmx_failValid(vcpu,
7039                                              VMXERR_VMPTRLD_VMXON_POINTER);
7040                         return kvm_skip_emulated_instruction(vcpu);
7041                 }
7042                 break;
7043         default:
7044                 return 1; /* shouldn't happen */
7045         }
7046
7047         if (vmpointer)
7048                 *vmpointer = vmptr;
7049         return 0;
7050 }
7051
7052 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
7053 {
7054         struct vcpu_vmx *vmx = to_vmx(vcpu);
7055         struct vmcs *shadow_vmcs;
7056
7057         if (cpu_has_vmx_msr_bitmap()) {
7058                 vmx->nested.msr_bitmap =
7059                                 (unsigned long *)__get_free_page(GFP_KERNEL);
7060                 if (!vmx->nested.msr_bitmap)
7061                         goto out_msr_bitmap;
7062         }
7063
7064         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7065         if (!vmx->nested.cached_vmcs12)
7066                 goto out_cached_vmcs12;
7067
7068         if (enable_shadow_vmcs) {
7069                 shadow_vmcs = alloc_vmcs();
7070                 if (!shadow_vmcs)
7071                         goto out_shadow_vmcs;
7072                 /* mark vmcs as shadow */
7073                 shadow_vmcs->revision_id |= (1u << 31);
7074                 /* init shadow vmcs */
7075                 vmcs_clear(shadow_vmcs);
7076                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
7077         }
7078
7079         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7080         vmx->nested.vmcs02_num = 0;
7081
7082         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7083                      HRTIMER_MODE_REL_PINNED);
7084         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7085
7086         vmx->nested.vmxon = true;
7087         return 0;
7088
7089 out_shadow_vmcs:
7090         kfree(vmx->nested.cached_vmcs12);
7091
7092 out_cached_vmcs12:
7093         free_page((unsigned long)vmx->nested.msr_bitmap);
7094
7095 out_msr_bitmap:
7096         return -ENOMEM;
7097 }
7098
7099 /*
7100  * Emulate the VMXON instruction.
7101  * Currently, we just remember that VMX is active, and do not save or even
7102  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7103  * do not currently need to store anything in that guest-allocated memory
7104  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7105  * argument is different from the VMXON pointer (which the spec says they do).
7106  */
7107 static int handle_vmon(struct kvm_vcpu *vcpu)
7108 {
7109         int ret;
7110         struct kvm_segment cs;
7111         struct vcpu_vmx *vmx = to_vmx(vcpu);
7112         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7113                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7114
7115         /* The Intel VMX Instruction Reference lists a bunch of bits that
7116          * are prerequisite to running VMXON, most notably cr4.VMXE must be
7117          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7118          * Otherwise, we should fail with #UD. We test these now:
7119          */
7120         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
7121             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
7122             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
7123                 kvm_queue_exception(vcpu, UD_VECTOR);
7124                 return 1;
7125         }
7126
7127         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7128         if (is_long_mode(vcpu) && !cs.l) {
7129                 kvm_queue_exception(vcpu, UD_VECTOR);
7130                 return 1;
7131         }
7132
7133         if (vmx_get_cpl(vcpu)) {
7134                 kvm_inject_gp(vcpu, 0);
7135                 return 1;
7136         }
7137
7138         if (vmx->nested.vmxon) {
7139                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7140                 return kvm_skip_emulated_instruction(vcpu);
7141         }
7142
7143         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7144                         != VMXON_NEEDED_FEATURES) {
7145                 kvm_inject_gp(vcpu, 0);
7146                 return 1;
7147         }
7148
7149         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
7150                 return 1;
7151
7152         ret = enter_vmx_operation(vcpu);
7153         if (ret)
7154                 return ret;
7155
7156         nested_vmx_succeed(vcpu);
7157         return kvm_skip_emulated_instruction(vcpu);
7158 }
7159
7160 /*
7161  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7162  * for running VMX instructions (except VMXON, whose prerequisites are
7163  * slightly different). It also specifies what exception to inject otherwise.
7164  */
7165 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7166 {
7167         struct kvm_segment cs;
7168         struct vcpu_vmx *vmx = to_vmx(vcpu);
7169
7170         if (!vmx->nested.vmxon) {
7171                 kvm_queue_exception(vcpu, UD_VECTOR);
7172                 return 0;
7173         }
7174
7175         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7176         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7177             (is_long_mode(vcpu) && !cs.l)) {
7178                 kvm_queue_exception(vcpu, UD_VECTOR);
7179                 return 0;
7180         }
7181
7182         if (vmx_get_cpl(vcpu)) {
7183                 kvm_inject_gp(vcpu, 0);
7184                 return 0;
7185         }
7186
7187         return 1;
7188 }
7189
7190 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7191 {
7192         if (vmx->nested.current_vmptr == -1ull)
7193                 return;
7194
7195         /* current_vmptr and current_vmcs12 are always set/reset together */
7196         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7197                 return;
7198
7199         if (enable_shadow_vmcs) {
7200                 /* copy to memory all shadowed fields in case
7201                    they were modified */
7202                 copy_shadow_to_vmcs12(vmx);
7203                 vmx->nested.sync_shadow_vmcs = false;
7204                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7205                                 SECONDARY_EXEC_SHADOW_VMCS);
7206                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7207         }
7208         vmx->nested.posted_intr_nv = -1;
7209
7210         /* Flush VMCS12 to guest memory */
7211         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7212                VMCS12_SIZE);
7213
7214         kunmap(vmx->nested.current_vmcs12_page);
7215         nested_release_page(vmx->nested.current_vmcs12_page);
7216         vmx->nested.current_vmptr = -1ull;
7217         vmx->nested.current_vmcs12 = NULL;
7218 }
7219
7220 /*
7221  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7222  * just stops using VMX.
7223  */
7224 static void free_nested(struct vcpu_vmx *vmx)
7225 {
7226         if (!vmx->nested.vmxon)
7227                 return;
7228
7229         vmx->nested.vmxon = false;
7230         free_vpid(vmx->nested.vpid02);
7231         nested_release_vmcs12(vmx);
7232         if (vmx->nested.msr_bitmap) {
7233                 free_page((unsigned long)vmx->nested.msr_bitmap);
7234                 vmx->nested.msr_bitmap = NULL;
7235         }
7236         if (enable_shadow_vmcs) {
7237                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7238                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7239                 vmx->vmcs01.shadow_vmcs = NULL;
7240         }
7241         kfree(vmx->nested.cached_vmcs12);
7242         /* Unpin physical memory we referred to in current vmcs02 */
7243         if (vmx->nested.apic_access_page) {
7244                 nested_release_page(vmx->nested.apic_access_page);
7245                 vmx->nested.apic_access_page = NULL;
7246         }
7247         if (vmx->nested.virtual_apic_page) {
7248                 nested_release_page(vmx->nested.virtual_apic_page);
7249                 vmx->nested.virtual_apic_page = NULL;
7250         }
7251         if (vmx->nested.pi_desc_page) {
7252                 kunmap(vmx->nested.pi_desc_page);
7253                 nested_release_page(vmx->nested.pi_desc_page);
7254                 vmx->nested.pi_desc_page = NULL;
7255                 vmx->nested.pi_desc = NULL;
7256         }
7257
7258         nested_free_all_saved_vmcss(vmx);
7259 }
7260
7261 /* Emulate the VMXOFF instruction */
7262 static int handle_vmoff(struct kvm_vcpu *vcpu)
7263 {
7264         if (!nested_vmx_check_permission(vcpu))
7265                 return 1;
7266         free_nested(to_vmx(vcpu));
7267         nested_vmx_succeed(vcpu);
7268         return kvm_skip_emulated_instruction(vcpu);
7269 }
7270
7271 /* Emulate the VMCLEAR instruction */
7272 static int handle_vmclear(struct kvm_vcpu *vcpu)
7273 {
7274         struct vcpu_vmx *vmx = to_vmx(vcpu);
7275         u32 zero = 0;
7276         gpa_t vmptr;
7277
7278         if (!nested_vmx_check_permission(vcpu))
7279                 return 1;
7280
7281         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7282                 return 1;
7283
7284         if (vmptr == vmx->nested.current_vmptr)
7285                 nested_release_vmcs12(vmx);
7286
7287         kvm_vcpu_write_guest(vcpu,
7288                         vmptr + offsetof(struct vmcs12, launch_state),
7289                         &zero, sizeof(zero));
7290
7291         nested_free_vmcs02(vmx, vmptr);
7292
7293         nested_vmx_succeed(vcpu);
7294         return kvm_skip_emulated_instruction(vcpu);
7295 }
7296
7297 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7298
7299 /* Emulate the VMLAUNCH instruction */
7300 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7301 {
7302         return nested_vmx_run(vcpu, true);
7303 }
7304
7305 /* Emulate the VMRESUME instruction */
7306 static int handle_vmresume(struct kvm_vcpu *vcpu)
7307 {
7308
7309         return nested_vmx_run(vcpu, false);
7310 }
7311
7312 enum vmcs_field_type {
7313         VMCS_FIELD_TYPE_U16 = 0,
7314         VMCS_FIELD_TYPE_U64 = 1,
7315         VMCS_FIELD_TYPE_U32 = 2,
7316         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7317 };
7318
7319 static inline int vmcs_field_type(unsigned long field)
7320 {
7321         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7322                 return VMCS_FIELD_TYPE_U32;
7323         return (field >> 13) & 0x3 ;
7324 }
7325
7326 static inline int vmcs_field_readonly(unsigned long field)
7327 {
7328         return (((field >> 10) & 0x3) == 1);
7329 }
7330
7331 /*
7332  * Read a vmcs12 field. Since these can have varying lengths and we return
7333  * one type, we chose the biggest type (u64) and zero-extend the return value
7334  * to that size. Note that the caller, handle_vmread, might need to use only
7335  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7336  * 64-bit fields are to be returned).
7337  */
7338 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7339                                   unsigned long field, u64 *ret)
7340 {
7341         short offset = vmcs_field_to_offset(field);
7342         char *p;
7343
7344         if (offset < 0)
7345                 return offset;
7346
7347         p = ((char *)(get_vmcs12(vcpu))) + offset;
7348
7349         switch (vmcs_field_type(field)) {
7350         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7351                 *ret = *((natural_width *)p);
7352                 return 0;
7353         case VMCS_FIELD_TYPE_U16:
7354                 *ret = *((u16 *)p);
7355                 return 0;
7356         case VMCS_FIELD_TYPE_U32:
7357                 *ret = *((u32 *)p);
7358                 return 0;
7359         case VMCS_FIELD_TYPE_U64:
7360                 *ret = *((u64 *)p);
7361                 return 0;
7362         default:
7363                 WARN_ON(1);
7364                 return -ENOENT;
7365         }
7366 }
7367
7368
7369 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7370                                    unsigned long field, u64 field_value){
7371         short offset = vmcs_field_to_offset(field);
7372         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7373         if (offset < 0)
7374                 return offset;
7375
7376         switch (vmcs_field_type(field)) {
7377         case VMCS_FIELD_TYPE_U16:
7378                 *(u16 *)p = field_value;
7379                 return 0;
7380         case VMCS_FIELD_TYPE_U32:
7381                 *(u32 *)p = field_value;
7382                 return 0;
7383         case VMCS_FIELD_TYPE_U64:
7384                 *(u64 *)p = field_value;
7385                 return 0;
7386         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7387                 *(natural_width *)p = field_value;
7388                 return 0;
7389         default:
7390                 WARN_ON(1);
7391                 return -ENOENT;
7392         }
7393
7394 }
7395
7396 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7397 {
7398         int i;
7399         unsigned long field;
7400         u64 field_value;
7401         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7402         const unsigned long *fields = shadow_read_write_fields;
7403         const int num_fields = max_shadow_read_write_fields;
7404
7405         preempt_disable();
7406
7407         vmcs_load(shadow_vmcs);
7408
7409         for (i = 0; i < num_fields; i++) {
7410                 field = fields[i];
7411                 switch (vmcs_field_type(field)) {
7412                 case VMCS_FIELD_TYPE_U16:
7413                         field_value = vmcs_read16(field);
7414                         break;
7415                 case VMCS_FIELD_TYPE_U32:
7416                         field_value = vmcs_read32(field);
7417                         break;
7418                 case VMCS_FIELD_TYPE_U64:
7419                         field_value = vmcs_read64(field);
7420                         break;
7421                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7422                         field_value = vmcs_readl(field);
7423                         break;
7424                 default:
7425                         WARN_ON(1);
7426                         continue;
7427                 }
7428                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7429         }
7430
7431         vmcs_clear(shadow_vmcs);
7432         vmcs_load(vmx->loaded_vmcs->vmcs);
7433
7434         preempt_enable();
7435 }
7436
7437 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7438 {
7439         const unsigned long *fields[] = {
7440                 shadow_read_write_fields,
7441                 shadow_read_only_fields
7442         };
7443         const int max_fields[] = {
7444                 max_shadow_read_write_fields,
7445                 max_shadow_read_only_fields
7446         };
7447         int i, q;
7448         unsigned long field;
7449         u64 field_value = 0;
7450         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7451
7452         vmcs_load(shadow_vmcs);
7453
7454         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7455                 for (i = 0; i < max_fields[q]; i++) {
7456                         field = fields[q][i];
7457                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7458
7459                         switch (vmcs_field_type(field)) {
7460                         case VMCS_FIELD_TYPE_U16:
7461                                 vmcs_write16(field, (u16)field_value);
7462                                 break;
7463                         case VMCS_FIELD_TYPE_U32:
7464                                 vmcs_write32(field, (u32)field_value);
7465                                 break;
7466                         case VMCS_FIELD_TYPE_U64:
7467                                 vmcs_write64(field, (u64)field_value);
7468                                 break;
7469                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7470                                 vmcs_writel(field, (long)field_value);
7471                                 break;
7472                         default:
7473                                 WARN_ON(1);
7474                                 break;
7475                         }
7476                 }
7477         }
7478
7479         vmcs_clear(shadow_vmcs);
7480         vmcs_load(vmx->loaded_vmcs->vmcs);
7481 }
7482
7483 /*
7484  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7485  * used before) all generate the same failure when it is missing.
7486  */
7487 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7488 {
7489         struct vcpu_vmx *vmx = to_vmx(vcpu);
7490         if (vmx->nested.current_vmptr == -1ull) {
7491                 nested_vmx_failInvalid(vcpu);
7492                 return 0;
7493         }
7494         return 1;
7495 }
7496
7497 static int handle_vmread(struct kvm_vcpu *vcpu)
7498 {
7499         unsigned long field;
7500         u64 field_value;
7501         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7502         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7503         gva_t gva = 0;
7504
7505         if (!nested_vmx_check_permission(vcpu))
7506                 return 1;
7507
7508         if (!nested_vmx_check_vmcs12(vcpu))
7509                 return kvm_skip_emulated_instruction(vcpu);
7510
7511         /* Decode instruction info and find the field to read */
7512         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7513         /* Read the field, zero-extended to a u64 field_value */
7514         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7515                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7516                 return kvm_skip_emulated_instruction(vcpu);
7517         }
7518         /*
7519          * Now copy part of this value to register or memory, as requested.
7520          * Note that the number of bits actually copied is 32 or 64 depending
7521          * on the guest's mode (32 or 64 bit), not on the given field's length.
7522          */
7523         if (vmx_instruction_info & (1u << 10)) {
7524                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7525                         field_value);
7526         } else {
7527                 if (get_vmx_mem_address(vcpu, exit_qualification,
7528                                 vmx_instruction_info, true, &gva))
7529                         return 1;
7530                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7531                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7532                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7533         }
7534
7535         nested_vmx_succeed(vcpu);
7536         return kvm_skip_emulated_instruction(vcpu);
7537 }
7538
7539
7540 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7541 {
7542         unsigned long field;
7543         gva_t gva;
7544         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7545         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7546         /* The value to write might be 32 or 64 bits, depending on L1's long
7547          * mode, and eventually we need to write that into a field of several
7548          * possible lengths. The code below first zero-extends the value to 64
7549          * bit (field_value), and then copies only the appropriate number of
7550          * bits into the vmcs12 field.
7551          */
7552         u64 field_value = 0;
7553         struct x86_exception e;
7554
7555         if (!nested_vmx_check_permission(vcpu))
7556                 return 1;
7557
7558         if (!nested_vmx_check_vmcs12(vcpu))
7559                 return kvm_skip_emulated_instruction(vcpu);
7560
7561         if (vmx_instruction_info & (1u << 10))
7562                 field_value = kvm_register_readl(vcpu,
7563                         (((vmx_instruction_info) >> 3) & 0xf));
7564         else {
7565                 if (get_vmx_mem_address(vcpu, exit_qualification,
7566                                 vmx_instruction_info, false, &gva))
7567                         return 1;
7568                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7569                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7570                         kvm_inject_page_fault(vcpu, &e);
7571                         return 1;
7572                 }
7573         }
7574
7575
7576         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7577         if (vmcs_field_readonly(field)) {
7578                 nested_vmx_failValid(vcpu,
7579                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7580                 return kvm_skip_emulated_instruction(vcpu);
7581         }
7582
7583         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7584                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7585                 return kvm_skip_emulated_instruction(vcpu);
7586         }
7587
7588         nested_vmx_succeed(vcpu);
7589         return kvm_skip_emulated_instruction(vcpu);
7590 }
7591
7592 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7593 {
7594         vmx->nested.current_vmptr = vmptr;
7595         if (enable_shadow_vmcs) {
7596                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7597                               SECONDARY_EXEC_SHADOW_VMCS);
7598                 vmcs_write64(VMCS_LINK_POINTER,
7599                              __pa(vmx->vmcs01.shadow_vmcs));
7600                 vmx->nested.sync_shadow_vmcs = true;
7601         }
7602 }
7603
7604 /* Emulate the VMPTRLD instruction */
7605 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7606 {
7607         struct vcpu_vmx *vmx = to_vmx(vcpu);
7608         gpa_t vmptr;
7609
7610         if (!nested_vmx_check_permission(vcpu))
7611                 return 1;
7612
7613         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7614                 return 1;
7615
7616         if (vmx->nested.current_vmptr != vmptr) {
7617                 struct vmcs12 *new_vmcs12;
7618                 struct page *page;
7619                 page = nested_get_page(vcpu, vmptr);
7620                 if (page == NULL) {
7621                         nested_vmx_failInvalid(vcpu);
7622                         return kvm_skip_emulated_instruction(vcpu);
7623                 }
7624                 new_vmcs12 = kmap(page);
7625                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7626                         kunmap(page);
7627                         nested_release_page_clean(page);
7628                         nested_vmx_failValid(vcpu,
7629                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7630                         return kvm_skip_emulated_instruction(vcpu);
7631                 }
7632
7633                 nested_release_vmcs12(vmx);
7634                 vmx->nested.current_vmcs12 = new_vmcs12;
7635                 vmx->nested.current_vmcs12_page = page;
7636                 /*
7637                  * Load VMCS12 from guest memory since it is not already
7638                  * cached.
7639                  */
7640                 memcpy(vmx->nested.cached_vmcs12,
7641                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7642                 set_current_vmptr(vmx, vmptr);
7643         }
7644
7645         nested_vmx_succeed(vcpu);
7646         return kvm_skip_emulated_instruction(vcpu);
7647 }
7648
7649 /* Emulate the VMPTRST instruction */
7650 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7651 {
7652         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7653         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7654         gva_t vmcs_gva;
7655         struct x86_exception e;
7656
7657         if (!nested_vmx_check_permission(vcpu))
7658                 return 1;
7659
7660         if (get_vmx_mem_address(vcpu, exit_qualification,
7661                         vmx_instruction_info, true, &vmcs_gva))
7662                 return 1;
7663         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7664         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7665                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7666                                  sizeof(u64), &e)) {
7667                 kvm_inject_page_fault(vcpu, &e);
7668                 return 1;
7669         }
7670         nested_vmx_succeed(vcpu);
7671         return kvm_skip_emulated_instruction(vcpu);
7672 }
7673
7674 /* Emulate the INVEPT instruction */
7675 static int handle_invept(struct kvm_vcpu *vcpu)
7676 {
7677         struct vcpu_vmx *vmx = to_vmx(vcpu);
7678         u32 vmx_instruction_info, types;
7679         unsigned long type;
7680         gva_t gva;
7681         struct x86_exception e;
7682         struct {
7683                 u64 eptp, gpa;
7684         } operand;
7685
7686         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7687               SECONDARY_EXEC_ENABLE_EPT) ||
7688             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7689                 kvm_queue_exception(vcpu, UD_VECTOR);
7690                 return 1;
7691         }
7692
7693         if (!nested_vmx_check_permission(vcpu))
7694                 return 1;
7695
7696         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7697                 kvm_queue_exception(vcpu, UD_VECTOR);
7698                 return 1;
7699         }
7700
7701         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7702         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7703
7704         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7705
7706         if (type >= 32 || !(types & (1 << type))) {
7707                 nested_vmx_failValid(vcpu,
7708                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7709                 return kvm_skip_emulated_instruction(vcpu);
7710         }
7711
7712         /* According to the Intel VMX instruction reference, the memory
7713          * operand is read even if it isn't needed (e.g., for type==global)
7714          */
7715         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7716                         vmx_instruction_info, false, &gva))
7717                 return 1;
7718         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7719                                 sizeof(operand), &e)) {
7720                 kvm_inject_page_fault(vcpu, &e);
7721                 return 1;
7722         }
7723
7724         switch (type) {
7725         case VMX_EPT_EXTENT_GLOBAL:
7726         /*
7727          * TODO: track mappings and invalidate
7728          * single context requests appropriately
7729          */
7730         case VMX_EPT_EXTENT_CONTEXT:
7731                 kvm_mmu_sync_roots(vcpu);
7732                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7733                 nested_vmx_succeed(vcpu);
7734                 break;
7735         default:
7736                 BUG_ON(1);
7737                 break;
7738         }
7739
7740         return kvm_skip_emulated_instruction(vcpu);
7741 }
7742
7743 static int handle_invvpid(struct kvm_vcpu *vcpu)
7744 {
7745         struct vcpu_vmx *vmx = to_vmx(vcpu);
7746         u32 vmx_instruction_info;
7747         unsigned long type, types;
7748         gva_t gva;
7749         struct x86_exception e;
7750         int vpid;
7751
7752         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7753               SECONDARY_EXEC_ENABLE_VPID) ||
7754                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7755                 kvm_queue_exception(vcpu, UD_VECTOR);
7756                 return 1;
7757         }
7758
7759         if (!nested_vmx_check_permission(vcpu))
7760                 return 1;
7761
7762         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7763         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7764
7765         types = (vmx->nested.nested_vmx_vpid_caps &
7766                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7767
7768         if (type >= 32 || !(types & (1 << type))) {
7769                 nested_vmx_failValid(vcpu,
7770                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7771                 return kvm_skip_emulated_instruction(vcpu);
7772         }
7773
7774         /* according to the intel vmx instruction reference, the memory
7775          * operand is read even if it isn't needed (e.g., for type==global)
7776          */
7777         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7778                         vmx_instruction_info, false, &gva))
7779                 return 1;
7780         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7781                                 sizeof(u32), &e)) {
7782                 kvm_inject_page_fault(vcpu, &e);
7783                 return 1;
7784         }
7785
7786         switch (type) {
7787         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7788         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7789         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7790                 if (!vpid) {
7791                         nested_vmx_failValid(vcpu,
7792                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7793                         return kvm_skip_emulated_instruction(vcpu);
7794                 }
7795                 break;
7796         case VMX_VPID_EXTENT_ALL_CONTEXT:
7797                 break;
7798         default:
7799                 WARN_ON_ONCE(1);
7800                 return kvm_skip_emulated_instruction(vcpu);
7801         }
7802
7803         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7804         nested_vmx_succeed(vcpu);
7805
7806         return kvm_skip_emulated_instruction(vcpu);
7807 }
7808
7809 static int handle_pml_full(struct kvm_vcpu *vcpu)
7810 {
7811         unsigned long exit_qualification;
7812
7813         trace_kvm_pml_full(vcpu->vcpu_id);
7814
7815         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7816
7817         /*
7818          * PML buffer FULL happened while executing iret from NMI,
7819          * "blocked by NMI" bit has to be set before next VM entry.
7820          */
7821         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7822                         cpu_has_virtual_nmis() &&
7823                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7824                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7825                                 GUEST_INTR_STATE_NMI);
7826
7827         /*
7828          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7829          * here.., and there's no userspace involvement needed for PML.
7830          */
7831         return 1;
7832 }
7833
7834 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7835 {
7836         kvm_lapic_expired_hv_timer(vcpu);
7837         return 1;
7838 }
7839
7840 /*
7841  * The exit handlers return 1 if the exit was handled fully and guest execution
7842  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7843  * to be done to userspace and return 0.
7844  */
7845 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7846         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7847         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7848         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7849         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7850         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7851         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7852         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7853         [EXIT_REASON_CPUID]                   = handle_cpuid,
7854         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7855         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7856         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7857         [EXIT_REASON_HLT]                     = handle_halt,
7858         [EXIT_REASON_INVD]                    = handle_invd,
7859         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7860         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7861         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7862         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7863         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7864         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7865         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7866         [EXIT_REASON_VMREAD]                  = handle_vmread,
7867         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7868         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7869         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7870         [EXIT_REASON_VMON]                    = handle_vmon,
7871         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7872         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7873         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7874         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7875         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7876         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7877         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7878         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7879         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7880         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7881         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7882         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7883         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7884         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7885         [EXIT_REASON_INVEPT]                  = handle_invept,
7886         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7887         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7888         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7889         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7890         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7891 };
7892
7893 static const int kvm_vmx_max_exit_handlers =
7894         ARRAY_SIZE(kvm_vmx_exit_handlers);
7895
7896 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7897                                        struct vmcs12 *vmcs12)
7898 {
7899         unsigned long exit_qualification;
7900         gpa_t bitmap, last_bitmap;
7901         unsigned int port;
7902         int size;
7903         u8 b;
7904
7905         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7906                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7907
7908         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7909
7910         port = exit_qualification >> 16;
7911         size = (exit_qualification & 7) + 1;
7912
7913         last_bitmap = (gpa_t)-1;
7914         b = -1;
7915
7916         while (size > 0) {
7917                 if (port < 0x8000)
7918                         bitmap = vmcs12->io_bitmap_a;
7919                 else if (port < 0x10000)
7920                         bitmap = vmcs12->io_bitmap_b;
7921                 else
7922                         return true;
7923                 bitmap += (port & 0x7fff) / 8;
7924
7925                 if (last_bitmap != bitmap)
7926                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7927                                 return true;
7928                 if (b & (1 << (port & 7)))
7929                         return true;
7930
7931                 port++;
7932                 size--;
7933                 last_bitmap = bitmap;
7934         }
7935
7936         return false;
7937 }
7938
7939 /*
7940  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7941  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7942  * disinterest in the current event (read or write a specific MSR) by using an
7943  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7944  */
7945 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7946         struct vmcs12 *vmcs12, u32 exit_reason)
7947 {
7948         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7949         gpa_t bitmap;
7950
7951         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7952                 return true;
7953
7954         /*
7955          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7956          * for the four combinations of read/write and low/high MSR numbers.
7957          * First we need to figure out which of the four to use:
7958          */
7959         bitmap = vmcs12->msr_bitmap;
7960         if (exit_reason == EXIT_REASON_MSR_WRITE)
7961                 bitmap += 2048;
7962         if (msr_index >= 0xc0000000) {
7963                 msr_index -= 0xc0000000;
7964                 bitmap += 1024;
7965         }
7966
7967         /* Then read the msr_index'th bit from this bitmap: */
7968         if (msr_index < 1024*8) {
7969                 unsigned char b;
7970                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7971                         return true;
7972                 return 1 & (b >> (msr_index & 7));
7973         } else
7974                 return true; /* let L1 handle the wrong parameter */
7975 }
7976
7977 /*
7978  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7979  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7980  * intercept (via guest_host_mask etc.) the current event.
7981  */
7982 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7983         struct vmcs12 *vmcs12)
7984 {
7985         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7986         int cr = exit_qualification & 15;
7987         int reg = (exit_qualification >> 8) & 15;
7988         unsigned long val = kvm_register_readl(vcpu, reg);
7989
7990         switch ((exit_qualification >> 4) & 3) {
7991         case 0: /* mov to cr */
7992                 switch (cr) {
7993                 case 0:
7994                         if (vmcs12->cr0_guest_host_mask &
7995                             (val ^ vmcs12->cr0_read_shadow))
7996                                 return true;
7997                         break;
7998                 case 3:
7999                         if ((vmcs12->cr3_target_count >= 1 &&
8000                                         vmcs12->cr3_target_value0 == val) ||
8001                                 (vmcs12->cr3_target_count >= 2 &&
8002                                         vmcs12->cr3_target_value1 == val) ||
8003                                 (vmcs12->cr3_target_count >= 3 &&
8004                                         vmcs12->cr3_target_value2 == val) ||
8005                                 (vmcs12->cr3_target_count >= 4 &&
8006                                         vmcs12->cr3_target_value3 == val))
8007                                 return false;
8008                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
8009                                 return true;
8010                         break;
8011                 case 4:
8012                         if (vmcs12->cr4_guest_host_mask &
8013                             (vmcs12->cr4_read_shadow ^ val))
8014                                 return true;
8015                         break;
8016                 case 8:
8017                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
8018                                 return true;
8019                         break;
8020                 }
8021                 break;
8022         case 2: /* clts */
8023                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
8024                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
8025                         return true;
8026                 break;
8027         case 1: /* mov from cr */
8028                 switch (cr) {
8029                 case 3:
8030                         if (vmcs12->cpu_based_vm_exec_control &
8031                             CPU_BASED_CR3_STORE_EXITING)
8032                                 return true;
8033                         break;
8034                 case 8:
8035                         if (vmcs12->cpu_based_vm_exec_control &
8036                             CPU_BASED_CR8_STORE_EXITING)
8037                                 return true;
8038                         break;
8039                 }
8040                 break;
8041         case 3: /* lmsw */
8042                 /*
8043                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8044                  * cr0. Other attempted changes are ignored, with no exit.
8045                  */
8046                 if (vmcs12->cr0_guest_host_mask & 0xe &
8047                     (val ^ vmcs12->cr0_read_shadow))
8048                         return true;
8049                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
8050                     !(vmcs12->cr0_read_shadow & 0x1) &&
8051                     (val & 0x1))
8052                         return true;
8053                 break;
8054         }
8055         return false;
8056 }
8057
8058 /*
8059  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8060  * should handle it ourselves in L0 (and then continue L2). Only call this
8061  * when in is_guest_mode (L2).
8062  */
8063 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
8064 {
8065         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8066         struct vcpu_vmx *vmx = to_vmx(vcpu);
8067         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8068         u32 exit_reason = vmx->exit_reason;
8069
8070         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
8071                                 vmcs_readl(EXIT_QUALIFICATION),
8072                                 vmx->idt_vectoring_info,
8073                                 intr_info,
8074                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8075                                 KVM_ISA_VMX);
8076
8077         if (vmx->nested.nested_run_pending)
8078                 return false;
8079
8080         if (unlikely(vmx->fail)) {
8081                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8082                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8083                 return true;
8084         }
8085
8086         switch (exit_reason) {
8087         case EXIT_REASON_EXCEPTION_NMI:
8088                 if (is_nmi(intr_info))
8089                         return false;
8090                 else if (is_page_fault(intr_info))
8091                         return enable_ept;
8092                 else if (is_no_device(intr_info) &&
8093                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8094                         return false;
8095                 else if (is_debug(intr_info) &&
8096                          vcpu->guest_debug &
8097                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8098                         return false;
8099                 else if (is_breakpoint(intr_info) &&
8100                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8101                         return false;
8102                 return vmcs12->exception_bitmap &
8103                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8104         case EXIT_REASON_EXTERNAL_INTERRUPT:
8105                 return false;
8106         case EXIT_REASON_TRIPLE_FAULT:
8107                 return true;
8108         case EXIT_REASON_PENDING_INTERRUPT:
8109                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8110         case EXIT_REASON_NMI_WINDOW:
8111                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8112         case EXIT_REASON_TASK_SWITCH:
8113                 return true;
8114         case EXIT_REASON_CPUID:
8115                 return true;
8116         case EXIT_REASON_HLT:
8117                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8118         case EXIT_REASON_INVD:
8119                 return true;
8120         case EXIT_REASON_INVLPG:
8121                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8122         case EXIT_REASON_RDPMC:
8123                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8124         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8125                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8126         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8127         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8128         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8129         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8130         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8131         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8132                 /*
8133                  * VMX instructions trap unconditionally. This allows L1 to
8134                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8135                  */
8136                 return true;
8137         case EXIT_REASON_CR_ACCESS:
8138                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8139         case EXIT_REASON_DR_ACCESS:
8140                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8141         case EXIT_REASON_IO_INSTRUCTION:
8142                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8143         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8144                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8145         case EXIT_REASON_MSR_READ:
8146         case EXIT_REASON_MSR_WRITE:
8147                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8148         case EXIT_REASON_INVALID_STATE:
8149                 return true;
8150         case EXIT_REASON_MWAIT_INSTRUCTION:
8151                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8152         case EXIT_REASON_MONITOR_TRAP_FLAG:
8153                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8154         case EXIT_REASON_MONITOR_INSTRUCTION:
8155                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8156         case EXIT_REASON_PAUSE_INSTRUCTION:
8157                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8158                         nested_cpu_has2(vmcs12,
8159                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8160         case EXIT_REASON_MCE_DURING_VMENTRY:
8161                 return false;
8162         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8163                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8164         case EXIT_REASON_APIC_ACCESS:
8165                 return nested_cpu_has2(vmcs12,
8166                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8167         case EXIT_REASON_APIC_WRITE:
8168         case EXIT_REASON_EOI_INDUCED:
8169                 /* apic_write and eoi_induced should exit unconditionally. */
8170                 return true;
8171         case EXIT_REASON_EPT_VIOLATION:
8172                 /*
8173                  * L0 always deals with the EPT violation. If nested EPT is
8174                  * used, and the nested mmu code discovers that the address is
8175                  * missing in the guest EPT table (EPT12), the EPT violation
8176                  * will be injected with nested_ept_inject_page_fault()
8177                  */
8178                 return false;
8179         case EXIT_REASON_EPT_MISCONFIG:
8180                 /*
8181                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8182                  * table (shadow on EPT) or a merged EPT table that L0 built
8183                  * (EPT on EPT). So any problems with the structure of the
8184                  * table is L0's fault.
8185                  */
8186                 return false;
8187         case EXIT_REASON_WBINVD:
8188                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8189         case EXIT_REASON_XSETBV:
8190                 return true;
8191         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8192                 /*
8193                  * This should never happen, since it is not possible to
8194                  * set XSS to a non-zero value---neither in L1 nor in L2.
8195                  * If if it were, XSS would have to be checked against
8196                  * the XSS exit bitmap in vmcs12.
8197                  */
8198                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8199         case EXIT_REASON_PREEMPTION_TIMER:
8200                 return false;
8201         case EXIT_REASON_PML_FULL:
8202                 /* We don't expose PML support to L1. */
8203                 return false;
8204         default:
8205                 return true;
8206         }
8207 }
8208
8209 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8210 {
8211         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8212         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8213 }
8214
8215 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8216 {
8217         if (vmx->pml_pg) {
8218                 __free_page(vmx->pml_pg);
8219                 vmx->pml_pg = NULL;
8220         }
8221 }
8222
8223 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8224 {
8225         struct vcpu_vmx *vmx = to_vmx(vcpu);
8226         u64 *pml_buf;
8227         u16 pml_idx;
8228
8229         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8230
8231         /* Do nothing if PML buffer is empty */
8232         if (pml_idx == (PML_ENTITY_NUM - 1))
8233                 return;
8234
8235         /* PML index always points to next available PML buffer entity */
8236         if (pml_idx >= PML_ENTITY_NUM)
8237                 pml_idx = 0;
8238         else
8239                 pml_idx++;
8240
8241         pml_buf = page_address(vmx->pml_pg);
8242         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8243                 u64 gpa;
8244
8245                 gpa = pml_buf[pml_idx];
8246                 WARN_ON(gpa & (PAGE_SIZE - 1));
8247                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8248         }
8249
8250         /* reset PML index */
8251         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8252 }
8253
8254 /*
8255  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8256  * Called before reporting dirty_bitmap to userspace.
8257  */
8258 static void kvm_flush_pml_buffers(struct kvm *kvm)
8259 {
8260         int i;
8261         struct kvm_vcpu *vcpu;
8262         /*
8263          * We only need to kick vcpu out of guest mode here, as PML buffer
8264          * is flushed at beginning of all VMEXITs, and it's obvious that only
8265          * vcpus running in guest are possible to have unflushed GPAs in PML
8266          * buffer.
8267          */
8268         kvm_for_each_vcpu(i, vcpu, kvm)
8269                 kvm_vcpu_kick(vcpu);
8270 }
8271
8272 static void vmx_dump_sel(char *name, uint32_t sel)
8273 {
8274         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8275                name, vmcs_read16(sel),
8276                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8277                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8278                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8279 }
8280
8281 static void vmx_dump_dtsel(char *name, uint32_t limit)
8282 {
8283         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8284                name, vmcs_read32(limit),
8285                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8286 }
8287
8288 static void dump_vmcs(void)
8289 {
8290         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8291         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8292         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8293         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8294         u32 secondary_exec_control = 0;
8295         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8296         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8297         int i, n;
8298
8299         if (cpu_has_secondary_exec_ctrls())
8300                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8301
8302         pr_err("*** Guest State ***\n");
8303         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8304                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8305                vmcs_readl(CR0_GUEST_HOST_MASK));
8306         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8307                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8308         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8309         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8310             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8311         {
8312                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8313                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8314                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8315                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8316         }
8317         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8318                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8319         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8320                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8321         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8322                vmcs_readl(GUEST_SYSENTER_ESP),
8323                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8324         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8325         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8326         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8327         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8328         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8329         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8330         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8331         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8332         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8333         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8334         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8335             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8336                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8337                        efer, vmcs_read64(GUEST_IA32_PAT));
8338         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8339                vmcs_read64(GUEST_IA32_DEBUGCTL),
8340                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8341         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8342                 pr_err("PerfGlobCtl = 0x%016llx\n",
8343                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8344         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8345                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8346         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8347                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8348                vmcs_read32(GUEST_ACTIVITY_STATE));
8349         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8350                 pr_err("InterruptStatus = %04x\n",
8351                        vmcs_read16(GUEST_INTR_STATUS));
8352
8353         pr_err("*** Host State ***\n");
8354         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8355                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8356         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8357                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8358                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8359                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8360                vmcs_read16(HOST_TR_SELECTOR));
8361         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8362                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8363                vmcs_readl(HOST_TR_BASE));
8364         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8365                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8366         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8367                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8368                vmcs_readl(HOST_CR4));
8369         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8370                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8371                vmcs_read32(HOST_IA32_SYSENTER_CS),
8372                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8373         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8374                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8375                        vmcs_read64(HOST_IA32_EFER),
8376                        vmcs_read64(HOST_IA32_PAT));
8377         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8378                 pr_err("PerfGlobCtl = 0x%016llx\n",
8379                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8380
8381         pr_err("*** Control State ***\n");
8382         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8383                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8384         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8385         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8386                vmcs_read32(EXCEPTION_BITMAP),
8387                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8388                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8389         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8390                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8391                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8392                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8393         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8394                vmcs_read32(VM_EXIT_INTR_INFO),
8395                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8396                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8397         pr_err("        reason=%08x qualification=%016lx\n",
8398                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8399         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8400                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8401                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8402         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8403         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8404                 pr_err("TSC Multiplier = 0x%016llx\n",
8405                        vmcs_read64(TSC_MULTIPLIER));
8406         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8407                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8408         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8409                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8410         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8411                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8412         n = vmcs_read32(CR3_TARGET_COUNT);
8413         for (i = 0; i + 1 < n; i += 4)
8414                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8415                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8416                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8417         if (i < n)
8418                 pr_err("CR3 target%u=%016lx\n",
8419                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8420         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8421                 pr_err("PLE Gap=%08x Window=%08x\n",
8422                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8423         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8424                 pr_err("Virtual processor ID = 0x%04x\n",
8425                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8426 }
8427
8428 /*
8429  * The guest has exited.  See if we can fix it or if we need userspace
8430  * assistance.
8431  */
8432 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8433 {
8434         struct vcpu_vmx *vmx = to_vmx(vcpu);
8435         u32 exit_reason = vmx->exit_reason;
8436         u32 vectoring_info = vmx->idt_vectoring_info;
8437
8438         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8439         vcpu->arch.gpa_available = false;
8440
8441         /*
8442          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8443          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8444          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8445          * mode as if vcpus is in root mode, the PML buffer must has been
8446          * flushed already.
8447          */
8448         if (enable_pml)
8449                 vmx_flush_pml_buffer(vcpu);
8450
8451         /* If guest state is invalid, start emulating */
8452         if (vmx->emulation_required)
8453                 return handle_invalid_guest_state(vcpu);
8454
8455         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8456                 nested_vmx_vmexit(vcpu, exit_reason,
8457                                   vmcs_read32(VM_EXIT_INTR_INFO),
8458                                   vmcs_readl(EXIT_QUALIFICATION));
8459                 return 1;
8460         }
8461
8462         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8463                 dump_vmcs();
8464                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8465                 vcpu->run->fail_entry.hardware_entry_failure_reason
8466                         = exit_reason;
8467                 return 0;
8468         }
8469
8470         if (unlikely(vmx->fail)) {
8471                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8472                 vcpu->run->fail_entry.hardware_entry_failure_reason
8473                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8474                 return 0;
8475         }
8476
8477         /*
8478          * Note:
8479          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8480          * delivery event since it indicates guest is accessing MMIO.
8481          * The vm-exit can be triggered again after return to guest that
8482          * will cause infinite loop.
8483          */
8484         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8485                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8486                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8487                         exit_reason != EXIT_REASON_PML_FULL &&
8488                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8489                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8490                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8491                 vcpu->run->internal.ndata = 2;
8492                 vcpu->run->internal.data[0] = vectoring_info;
8493                 vcpu->run->internal.data[1] = exit_reason;
8494                 return 0;
8495         }
8496
8497         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8498             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8499                                         get_vmcs12(vcpu))))) {
8500                 if (vmx_interrupt_allowed(vcpu)) {
8501                         vmx->soft_vnmi_blocked = 0;
8502                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8503                            vcpu->arch.nmi_pending) {
8504                         /*
8505                          * This CPU don't support us in finding the end of an
8506                          * NMI-blocked window if the guest runs with IRQs
8507                          * disabled. So we pull the trigger after 1 s of
8508                          * futile waiting, but inform the user about this.
8509                          */
8510                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8511                                "state on VCPU %d after 1 s timeout\n",
8512                                __func__, vcpu->vcpu_id);
8513                         vmx->soft_vnmi_blocked = 0;
8514                 }
8515         }
8516
8517         if (exit_reason < kvm_vmx_max_exit_handlers
8518             && kvm_vmx_exit_handlers[exit_reason])
8519                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8520         else {
8521                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8522                                 exit_reason);
8523                 kvm_queue_exception(vcpu, UD_VECTOR);
8524                 return 1;
8525         }
8526 }
8527
8528 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8529 {
8530         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8531
8532         if (is_guest_mode(vcpu) &&
8533                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8534                 return;
8535
8536         if (irr == -1 || tpr < irr) {
8537                 vmcs_write32(TPR_THRESHOLD, 0);
8538                 return;
8539         }
8540
8541         vmcs_write32(TPR_THRESHOLD, irr);
8542 }
8543
8544 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8545 {
8546         u32 sec_exec_control;
8547
8548         /* Postpone execution until vmcs01 is the current VMCS. */
8549         if (is_guest_mode(vcpu)) {
8550                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8551                 return;
8552         }
8553
8554         if (!cpu_has_vmx_virtualize_x2apic_mode())
8555                 return;
8556
8557         if (!cpu_need_tpr_shadow(vcpu))
8558                 return;
8559
8560         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8561
8562         if (set) {
8563                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8564                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8565         } else {
8566                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8567                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8568                 vmx_flush_tlb_ept_only(vcpu);
8569         }
8570         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8571
8572         vmx_set_msr_bitmap(vcpu);
8573 }
8574
8575 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8576 {
8577         struct vcpu_vmx *vmx = to_vmx(vcpu);
8578
8579         /*
8580          * Currently we do not handle the nested case where L2 has an
8581          * APIC access page of its own; that page is still pinned.
8582          * Hence, we skip the case where the VCPU is in guest mode _and_
8583          * L1 prepared an APIC access page for L2.
8584          *
8585          * For the case where L1 and L2 share the same APIC access page
8586          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8587          * in the vmcs12), this function will only update either the vmcs01
8588          * or the vmcs02.  If the former, the vmcs02 will be updated by
8589          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8590          * the next L2->L1 exit.
8591          */
8592         if (!is_guest_mode(vcpu) ||
8593             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8594                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8595                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8596                 vmx_flush_tlb_ept_only(vcpu);
8597         }
8598 }
8599
8600 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8601 {
8602         u16 status;
8603         u8 old;
8604
8605         if (max_isr == -1)
8606                 max_isr = 0;
8607
8608         status = vmcs_read16(GUEST_INTR_STATUS);
8609         old = status >> 8;
8610         if (max_isr != old) {
8611                 status &= 0xff;
8612                 status |= max_isr << 8;
8613                 vmcs_write16(GUEST_INTR_STATUS, status);
8614         }
8615 }
8616
8617 static void vmx_set_rvi(int vector)
8618 {
8619         u16 status;
8620         u8 old;
8621
8622         if (vector == -1)
8623                 vector = 0;
8624
8625         status = vmcs_read16(GUEST_INTR_STATUS);
8626         old = (u8)status & 0xff;
8627         if ((u8)vector != old) {
8628                 status &= ~0xff;
8629                 status |= (u8)vector;
8630                 vmcs_write16(GUEST_INTR_STATUS, status);
8631         }
8632 }
8633
8634 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8635 {
8636         if (!is_guest_mode(vcpu)) {
8637                 vmx_set_rvi(max_irr);
8638                 return;
8639         }
8640
8641         if (max_irr == -1)
8642                 return;
8643
8644         /*
8645          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8646          * handles it.
8647          */
8648         if (nested_exit_on_intr(vcpu))
8649                 return;
8650
8651         /*
8652          * Else, fall back to pre-APICv interrupt injection since L2
8653          * is run without virtual interrupt delivery.
8654          */
8655         if (!kvm_event_needs_reinjection(vcpu) &&
8656             vmx_interrupt_allowed(vcpu)) {
8657                 kvm_queue_interrupt(vcpu, max_irr, false);
8658                 vmx_inject_irq(vcpu);
8659         }
8660 }
8661
8662 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8663 {
8664         struct vcpu_vmx *vmx = to_vmx(vcpu);
8665         int max_irr;
8666
8667         WARN_ON(!vcpu->arch.apicv_active);
8668         if (pi_test_on(&vmx->pi_desc)) {
8669                 pi_clear_on(&vmx->pi_desc);
8670                 /*
8671                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8672                  * But on x86 this is just a compiler barrier anyway.
8673                  */
8674                 smp_mb__after_atomic();
8675                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8676         } else {
8677                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8678         }
8679         vmx_hwapic_irr_update(vcpu, max_irr);
8680         return max_irr;
8681 }
8682
8683 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8684 {
8685         if (!kvm_vcpu_apicv_active(vcpu))
8686                 return;
8687
8688         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8689         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8690         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8691         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8692 }
8693
8694 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8695 {
8696         struct vcpu_vmx *vmx = to_vmx(vcpu);
8697
8698         pi_clear_on(&vmx->pi_desc);
8699         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8700 }
8701
8702 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8703 {
8704         u32 exit_intr_info;
8705
8706         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8707               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8708                 return;
8709
8710         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8711         exit_intr_info = vmx->exit_intr_info;
8712
8713         /* Handle machine checks before interrupts are enabled */
8714         if (is_machine_check(exit_intr_info))
8715                 kvm_machine_check();
8716
8717         /* We need to handle NMIs before interrupts are enabled */
8718         if (is_nmi(exit_intr_info)) {
8719                 kvm_before_handle_nmi(&vmx->vcpu);
8720                 asm("int $2");
8721                 kvm_after_handle_nmi(&vmx->vcpu);
8722         }
8723 }
8724
8725 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8726 {
8727         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8728         register void *__sp asm(_ASM_SP);
8729
8730         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8731                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8732                 unsigned int vector;
8733                 unsigned long entry;
8734                 gate_desc *desc;
8735                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8736 #ifdef CONFIG_X86_64
8737                 unsigned long tmp;
8738 #endif
8739
8740                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8741                 desc = (gate_desc *)vmx->host_idt_base + vector;
8742                 entry = gate_offset(*desc);
8743                 asm volatile(
8744 #ifdef CONFIG_X86_64
8745                         "mov %%" _ASM_SP ", %[sp]\n\t"
8746                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8747                         "push $%c[ss]\n\t"
8748                         "push %[sp]\n\t"
8749 #endif
8750                         "pushf\n\t"
8751                         __ASM_SIZE(push) " $%c[cs]\n\t"
8752                         "call *%[entry]\n\t"
8753                         :
8754 #ifdef CONFIG_X86_64
8755                         [sp]"=&r"(tmp),
8756 #endif
8757                         "+r"(__sp)
8758                         :
8759                         [entry]"r"(entry),
8760                         [ss]"i"(__KERNEL_DS),
8761                         [cs]"i"(__KERNEL_CS)
8762                         );
8763         }
8764 }
8765
8766 static bool vmx_has_high_real_mode_segbase(void)
8767 {
8768         return enable_unrestricted_guest || emulate_invalid_guest_state;
8769 }
8770
8771 static bool vmx_mpx_supported(void)
8772 {
8773         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8774                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8775 }
8776
8777 static bool vmx_xsaves_supported(void)
8778 {
8779         return vmcs_config.cpu_based_2nd_exec_ctrl &
8780                 SECONDARY_EXEC_XSAVES;
8781 }
8782
8783 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8784 {
8785         u32 exit_intr_info;
8786         bool unblock_nmi;
8787         u8 vector;
8788         bool idtv_info_valid;
8789
8790         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8791
8792         if (cpu_has_virtual_nmis()) {
8793                 if (vmx->nmi_known_unmasked)
8794                         return;
8795                 /*
8796                  * Can't use vmx->exit_intr_info since we're not sure what
8797                  * the exit reason is.
8798                  */
8799                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8800                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8801                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8802                 /*
8803                  * SDM 3: 27.7.1.2 (September 2008)
8804                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8805                  * a guest IRET fault.
8806                  * SDM 3: 23.2.2 (September 2008)
8807                  * Bit 12 is undefined in any of the following cases:
8808                  *  If the VM exit sets the valid bit in the IDT-vectoring
8809                  *   information field.
8810                  *  If the VM exit is due to a double fault.
8811                  */
8812                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8813                     vector != DF_VECTOR && !idtv_info_valid)
8814                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8815                                       GUEST_INTR_STATE_NMI);
8816                 else
8817                         vmx->nmi_known_unmasked =
8818                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8819                                   & GUEST_INTR_STATE_NMI);
8820         } else if (unlikely(vmx->soft_vnmi_blocked))
8821                 vmx->vnmi_blocked_time +=
8822                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8823 }
8824
8825 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8826                                       u32 idt_vectoring_info,
8827                                       int instr_len_field,
8828                                       int error_code_field)
8829 {
8830         u8 vector;
8831         int type;
8832         bool idtv_info_valid;
8833
8834         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8835
8836         vcpu->arch.nmi_injected = false;
8837         kvm_clear_exception_queue(vcpu);
8838         kvm_clear_interrupt_queue(vcpu);
8839
8840         if (!idtv_info_valid)
8841                 return;
8842
8843         kvm_make_request(KVM_REQ_EVENT, vcpu);
8844
8845         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8846         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8847
8848         switch (type) {
8849         case INTR_TYPE_NMI_INTR:
8850                 vcpu->arch.nmi_injected = true;
8851                 /*
8852                  * SDM 3: 27.7.1.2 (September 2008)
8853                  * Clear bit "block by NMI" before VM entry if a NMI
8854                  * delivery faulted.
8855                  */
8856                 vmx_set_nmi_mask(vcpu, false);
8857                 break;
8858         case INTR_TYPE_SOFT_EXCEPTION:
8859                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8860                 /* fall through */
8861         case INTR_TYPE_HARD_EXCEPTION:
8862                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8863                         u32 err = vmcs_read32(error_code_field);
8864                         kvm_requeue_exception_e(vcpu, vector, err);
8865                 } else
8866                         kvm_requeue_exception(vcpu, vector);
8867                 break;
8868         case INTR_TYPE_SOFT_INTR:
8869                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8870                 /* fall through */
8871         case INTR_TYPE_EXT_INTR:
8872                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8873                 break;
8874         default:
8875                 break;
8876         }
8877 }
8878
8879 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8880 {
8881         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8882                                   VM_EXIT_INSTRUCTION_LEN,
8883                                   IDT_VECTORING_ERROR_CODE);
8884 }
8885
8886 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8887 {
8888         __vmx_complete_interrupts(vcpu,
8889                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8890                                   VM_ENTRY_INSTRUCTION_LEN,
8891                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8892
8893         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8894 }
8895
8896 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8897 {
8898         int i, nr_msrs;
8899         struct perf_guest_switch_msr *msrs;
8900
8901         msrs = perf_guest_get_msrs(&nr_msrs);
8902
8903         if (!msrs)
8904                 return;
8905
8906         for (i = 0; i < nr_msrs; i++)
8907                 if (msrs[i].host == msrs[i].guest)
8908                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8909                 else
8910                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8911                                         msrs[i].host);
8912 }
8913
8914 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8915 {
8916         struct vcpu_vmx *vmx = to_vmx(vcpu);
8917         u64 tscl;
8918         u32 delta_tsc;
8919
8920         if (vmx->hv_deadline_tsc == -1)
8921                 return;
8922
8923         tscl = rdtsc();
8924         if (vmx->hv_deadline_tsc > tscl)
8925                 /* sure to be 32 bit only because checked on set_hv_timer */
8926                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8927                         cpu_preemption_timer_multi);
8928         else
8929                 delta_tsc = 0;
8930
8931         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8932 }
8933
8934 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8935 {
8936         struct vcpu_vmx *vmx = to_vmx(vcpu);
8937         unsigned long debugctlmsr, cr4;
8938
8939         /* Record the guest's net vcpu time for enforced NMI injections. */
8940         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8941                 vmx->entry_time = ktime_get();
8942
8943         /* Don't enter VMX if guest state is invalid, let the exit handler
8944            start emulation until we arrive back to a valid state */
8945         if (vmx->emulation_required)
8946                 return;
8947
8948         if (vmx->ple_window_dirty) {
8949                 vmx->ple_window_dirty = false;
8950                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8951         }
8952
8953         if (vmx->nested.sync_shadow_vmcs) {
8954                 copy_vmcs12_to_shadow(vmx);
8955                 vmx->nested.sync_shadow_vmcs = false;
8956         }
8957
8958         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8959                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8960         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8961                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8962
8963         cr4 = cr4_read_shadow();
8964         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8965                 vmcs_writel(HOST_CR4, cr4);
8966                 vmx->host_state.vmcs_host_cr4 = cr4;
8967         }
8968
8969         /* When single-stepping over STI and MOV SS, we must clear the
8970          * corresponding interruptibility bits in the guest state. Otherwise
8971          * vmentry fails as it then expects bit 14 (BS) in pending debug
8972          * exceptions being set, but that's not correct for the guest debugging
8973          * case. */
8974         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8975                 vmx_set_interrupt_shadow(vcpu, 0);
8976
8977         if (vmx->guest_pkru_valid)
8978                 __write_pkru(vmx->guest_pkru);
8979
8980         atomic_switch_perf_msrs(vmx);
8981         debugctlmsr = get_debugctlmsr();
8982
8983         vmx_arm_hv_timer(vcpu);
8984
8985         vmx->__launched = vmx->loaded_vmcs->launched;
8986         asm(
8987                 /* Store host registers */
8988                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8989                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8990                 "push %%" _ASM_CX " \n\t"
8991                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8992                 "je 1f \n\t"
8993                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8994                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8995                 "1: \n\t"
8996                 /* Reload cr2 if changed */
8997                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8998                 "mov %%cr2, %%" _ASM_DX " \n\t"
8999                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
9000                 "je 2f \n\t"
9001                 "mov %%" _ASM_AX", %%cr2 \n\t"
9002                 "2: \n\t"
9003                 /* Check if vmlaunch of vmresume is needed */
9004                 "cmpl $0, %c[launched](%0) \n\t"
9005                 /* Load guest registers.  Don't clobber flags. */
9006                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
9007                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
9008                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
9009                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
9010                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
9011                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
9012 #ifdef CONFIG_X86_64
9013                 "mov %c[r8](%0),  %%r8  \n\t"
9014                 "mov %c[r9](%0),  %%r9  \n\t"
9015                 "mov %c[r10](%0), %%r10 \n\t"
9016                 "mov %c[r11](%0), %%r11 \n\t"
9017                 "mov %c[r12](%0), %%r12 \n\t"
9018                 "mov %c[r13](%0), %%r13 \n\t"
9019                 "mov %c[r14](%0), %%r14 \n\t"
9020                 "mov %c[r15](%0), %%r15 \n\t"
9021 #endif
9022                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
9023
9024                 /* Enter guest mode */
9025                 "jne 1f \n\t"
9026                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
9027                 "jmp 2f \n\t"
9028                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
9029                 "2: "
9030                 /* Save guest registers, load host registers, keep flags */
9031                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
9032                 "pop %0 \n\t"
9033                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
9034                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
9035                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
9036                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
9037                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
9038                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
9039                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
9040 #ifdef CONFIG_X86_64
9041                 "mov %%r8,  %c[r8](%0) \n\t"
9042                 "mov %%r9,  %c[r9](%0) \n\t"
9043                 "mov %%r10, %c[r10](%0) \n\t"
9044                 "mov %%r11, %c[r11](%0) \n\t"
9045                 "mov %%r12, %c[r12](%0) \n\t"
9046                 "mov %%r13, %c[r13](%0) \n\t"
9047                 "mov %%r14, %c[r14](%0) \n\t"
9048                 "mov %%r15, %c[r15](%0) \n\t"
9049 #endif
9050                 "mov %%cr2, %%" _ASM_AX "   \n\t"
9051                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
9052
9053                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
9054                 "setbe %c[fail](%0) \n\t"
9055                 ".pushsection .rodata \n\t"
9056                 ".global vmx_return \n\t"
9057                 "vmx_return: " _ASM_PTR " 2b \n\t"
9058                 ".popsection"
9059               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
9060                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
9061                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
9062                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
9063                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
9064                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
9065                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
9066                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
9067                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
9068                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
9069                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
9070 #ifdef CONFIG_X86_64
9071                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
9072                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
9073                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
9074                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
9075                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
9076                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
9077                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
9078                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
9079 #endif
9080                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
9081                 [wordsize]"i"(sizeof(ulong))
9082               : "cc", "memory"
9083 #ifdef CONFIG_X86_64
9084                 , "rax", "rbx", "rdi", "rsi"
9085                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9086 #else
9087                 , "eax", "ebx", "edi", "esi"
9088 #endif
9089               );
9090
9091         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9092         if (debugctlmsr)
9093                 update_debugctlmsr(debugctlmsr);
9094
9095 #ifndef CONFIG_X86_64
9096         /*
9097          * The sysexit path does not restore ds/es, so we must set them to
9098          * a reasonable value ourselves.
9099          *
9100          * We can't defer this to vmx_load_host_state() since that function
9101          * may be executed in interrupt context, which saves and restore segments
9102          * around it, nullifying its effect.
9103          */
9104         loadsegment(ds, __USER_DS);
9105         loadsegment(es, __USER_DS);
9106 #endif
9107
9108         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9109                                   | (1 << VCPU_EXREG_RFLAGS)
9110                                   | (1 << VCPU_EXREG_PDPTR)
9111                                   | (1 << VCPU_EXREG_SEGMENTS)
9112                                   | (1 << VCPU_EXREG_CR3));
9113         vcpu->arch.regs_dirty = 0;
9114
9115         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9116
9117         vmx->loaded_vmcs->launched = 1;
9118
9119         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9120
9121         /*
9122          * eager fpu is enabled if PKEY is supported and CR4 is switched
9123          * back on host, so it is safe to read guest PKRU from current
9124          * XSAVE.
9125          */
9126         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9127                 vmx->guest_pkru = __read_pkru();
9128                 if (vmx->guest_pkru != vmx->host_pkru) {
9129                         vmx->guest_pkru_valid = true;
9130                         __write_pkru(vmx->host_pkru);
9131                 } else
9132                         vmx->guest_pkru_valid = false;
9133         }
9134
9135         /*
9136          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9137          * we did not inject a still-pending event to L1 now because of
9138          * nested_run_pending, we need to re-enable this bit.
9139          */
9140         if (vmx->nested.nested_run_pending)
9141                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9142
9143         vmx->nested.nested_run_pending = 0;
9144
9145         vmx_complete_atomic_exit(vmx);
9146         vmx_recover_nmi_blocking(vmx);
9147         vmx_complete_interrupts(vmx);
9148 }
9149
9150 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9151 {
9152         struct vcpu_vmx *vmx = to_vmx(vcpu);
9153         int cpu;
9154
9155         if (vmx->loaded_vmcs == &vmx->vmcs01)
9156                 return;
9157
9158         cpu = get_cpu();
9159         vmx->loaded_vmcs = &vmx->vmcs01;
9160         vmx_vcpu_put(vcpu);
9161         vmx_vcpu_load(vcpu, cpu);
9162         vcpu->cpu = cpu;
9163         put_cpu();
9164 }
9165
9166 /*
9167  * Ensure that the current vmcs of the logical processor is the
9168  * vmcs01 of the vcpu before calling free_nested().
9169  */
9170 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9171 {
9172        struct vcpu_vmx *vmx = to_vmx(vcpu);
9173        int r;
9174
9175        r = vcpu_load(vcpu);
9176        BUG_ON(r);
9177        vmx_load_vmcs01(vcpu);
9178        free_nested(vmx);
9179        vcpu_put(vcpu);
9180 }
9181
9182 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9183 {
9184         struct vcpu_vmx *vmx = to_vmx(vcpu);
9185
9186         if (enable_pml)
9187                 vmx_destroy_pml_buffer(vmx);
9188         free_vpid(vmx->vpid);
9189         leave_guest_mode(vcpu);
9190         vmx_free_vcpu_nested(vcpu);
9191         free_loaded_vmcs(vmx->loaded_vmcs);
9192         kfree(vmx->guest_msrs);
9193         kvm_vcpu_uninit(vcpu);
9194         kmem_cache_free(kvm_vcpu_cache, vmx);
9195 }
9196
9197 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9198 {
9199         int err;
9200         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9201         int cpu;
9202
9203         if (!vmx)
9204                 return ERR_PTR(-ENOMEM);
9205
9206         vmx->vpid = allocate_vpid();
9207
9208         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9209         if (err)
9210                 goto free_vcpu;
9211
9212         err = -ENOMEM;
9213
9214         /*
9215          * If PML is turned on, failure on enabling PML just results in failure
9216          * of creating the vcpu, therefore we can simplify PML logic (by
9217          * avoiding dealing with cases, such as enabling PML partially on vcpus
9218          * for the guest, etc.
9219          */
9220         if (enable_pml) {
9221                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9222                 if (!vmx->pml_pg)
9223                         goto uninit_vcpu;
9224         }
9225
9226         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9227         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9228                      > PAGE_SIZE);
9229
9230         if (!vmx->guest_msrs)
9231                 goto free_pml;
9232
9233         vmx->loaded_vmcs = &vmx->vmcs01;
9234         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9235         vmx->loaded_vmcs->shadow_vmcs = NULL;
9236         if (!vmx->loaded_vmcs->vmcs)
9237                 goto free_msrs;
9238         if (!vmm_exclusive)
9239                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9240         loaded_vmcs_init(vmx->loaded_vmcs);
9241         if (!vmm_exclusive)
9242                 kvm_cpu_vmxoff();
9243
9244         cpu = get_cpu();
9245         vmx_vcpu_load(&vmx->vcpu, cpu);
9246         vmx->vcpu.cpu = cpu;
9247         err = vmx_vcpu_setup(vmx);
9248         vmx_vcpu_put(&vmx->vcpu);
9249         put_cpu();
9250         if (err)
9251                 goto free_vmcs;
9252         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9253                 err = alloc_apic_access_page(kvm);
9254                 if (err)
9255                         goto free_vmcs;
9256         }
9257
9258         if (enable_ept) {
9259                 if (!kvm->arch.ept_identity_map_addr)
9260                         kvm->arch.ept_identity_map_addr =
9261                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9262                 err = init_rmode_identity_map(kvm);
9263                 if (err)
9264                         goto free_vmcs;
9265         }
9266
9267         if (nested) {
9268                 nested_vmx_setup_ctls_msrs(vmx);
9269                 vmx->nested.vpid02 = allocate_vpid();
9270         }
9271
9272         vmx->nested.posted_intr_nv = -1;
9273         vmx->nested.current_vmptr = -1ull;
9274         vmx->nested.current_vmcs12 = NULL;
9275
9276         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9277
9278         return &vmx->vcpu;
9279
9280 free_vmcs:
9281         free_vpid(vmx->nested.vpid02);
9282         free_loaded_vmcs(vmx->loaded_vmcs);
9283 free_msrs:
9284         kfree(vmx->guest_msrs);
9285 free_pml:
9286         vmx_destroy_pml_buffer(vmx);
9287 uninit_vcpu:
9288         kvm_vcpu_uninit(&vmx->vcpu);
9289 free_vcpu:
9290         free_vpid(vmx->vpid);
9291         kmem_cache_free(kvm_vcpu_cache, vmx);
9292         return ERR_PTR(err);
9293 }
9294
9295 static void __init vmx_check_processor_compat(void *rtn)
9296 {
9297         struct vmcs_config vmcs_conf;
9298
9299         *(int *)rtn = 0;
9300         if (setup_vmcs_config(&vmcs_conf) < 0)
9301                 *(int *)rtn = -EIO;
9302         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9303                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9304                                 smp_processor_id());
9305                 *(int *)rtn = -EIO;
9306         }
9307 }
9308
9309 static int get_ept_level(void)
9310 {
9311         return VMX_EPT_DEFAULT_GAW + 1;
9312 }
9313
9314 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9315 {
9316         u8 cache;
9317         u64 ipat = 0;
9318
9319         /* For VT-d and EPT combination
9320          * 1. MMIO: always map as UC
9321          * 2. EPT with VT-d:
9322          *   a. VT-d without snooping control feature: can't guarantee the
9323          *      result, try to trust guest.
9324          *   b. VT-d with snooping control feature: snooping control feature of
9325          *      VT-d engine can guarantee the cache correctness. Just set it
9326          *      to WB to keep consistent with host. So the same as item 3.
9327          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9328          *    consistent with host MTRR
9329          */
9330         if (is_mmio) {
9331                 cache = MTRR_TYPE_UNCACHABLE;
9332                 goto exit;
9333         }
9334
9335         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9336                 ipat = VMX_EPT_IPAT_BIT;
9337                 cache = MTRR_TYPE_WRBACK;
9338                 goto exit;
9339         }
9340
9341         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9342                 ipat = VMX_EPT_IPAT_BIT;
9343                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9344                         cache = MTRR_TYPE_WRBACK;
9345                 else
9346                         cache = MTRR_TYPE_UNCACHABLE;
9347                 goto exit;
9348         }
9349
9350         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9351
9352 exit:
9353         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9354 }
9355
9356 static int vmx_get_lpage_level(void)
9357 {
9358         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9359                 return PT_DIRECTORY_LEVEL;
9360         else
9361                 /* For shadow and EPT supported 1GB page */
9362                 return PT_PDPE_LEVEL;
9363 }
9364
9365 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9366 {
9367         /*
9368          * These bits in the secondary execution controls field
9369          * are dynamic, the others are mostly based on the hypervisor
9370          * architecture and the guest's CPUID.  Do not touch the
9371          * dynamic bits.
9372          */
9373         u32 mask =
9374                 SECONDARY_EXEC_SHADOW_VMCS |
9375                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9376                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9377
9378         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9379
9380         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9381                      (new_ctl & ~mask) | (cur_ctl & mask));
9382 }
9383
9384 /*
9385  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9386  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9387  */
9388 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9389 {
9390         struct vcpu_vmx *vmx = to_vmx(vcpu);
9391         struct kvm_cpuid_entry2 *entry;
9392
9393         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9394         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9395
9396 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9397         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9398                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9399 } while (0)
9400
9401         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9402         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9403         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9404         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9405         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9406         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9407         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9408         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9409         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9410         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9411         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9412         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9413         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9414         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9415         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9416
9417         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9418         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9419         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9420         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9421         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9422         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9423         cr4_fixed1_update(bit(11),            ecx, bit(2));
9424
9425 #undef cr4_fixed1_update
9426 }
9427
9428 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9429 {
9430         struct kvm_cpuid_entry2 *best;
9431         struct vcpu_vmx *vmx = to_vmx(vcpu);
9432         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9433
9434         if (vmx_rdtscp_supported()) {
9435                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9436                 if (!rdtscp_enabled)
9437                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9438
9439                 if (nested) {
9440                         if (rdtscp_enabled)
9441                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9442                                         SECONDARY_EXEC_RDTSCP;
9443                         else
9444                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9445                                         ~SECONDARY_EXEC_RDTSCP;
9446                 }
9447         }
9448
9449         /* Exposing INVPCID only when PCID is exposed */
9450         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9451         if (vmx_invpcid_supported() &&
9452             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9453             !guest_cpuid_has_pcid(vcpu))) {
9454                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9455
9456                 if (best)
9457                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9458         }
9459
9460         if (cpu_has_secondary_exec_ctrls())
9461                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9462
9463         if (nested_vmx_allowed(vcpu))
9464                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9465                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9466         else
9467                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9468                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9469
9470         if (nested_vmx_allowed(vcpu))
9471                 nested_vmx_cr_fixed1_bits_update(vcpu);
9472 }
9473
9474 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9475 {
9476         if (func == 1 && nested)
9477                 entry->ecx |= bit(X86_FEATURE_VMX);
9478 }
9479
9480 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9481                 struct x86_exception *fault)
9482 {
9483         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9484         u32 exit_reason;
9485
9486         if (fault->error_code & PFERR_RSVD_MASK)
9487                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9488         else
9489                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9490         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9491         vmcs12->guest_physical_address = fault->address;
9492 }
9493
9494 /* Callbacks for nested_ept_init_mmu_context: */
9495
9496 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9497 {
9498         /* return the page table to be shadowed - in our case, EPT12 */
9499         return get_vmcs12(vcpu)->ept_pointer;
9500 }
9501
9502 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9503 {
9504         WARN_ON(mmu_is_nested(vcpu));
9505         kvm_init_shadow_ept_mmu(vcpu,
9506                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9507                         VMX_EPT_EXECUTE_ONLY_BIT);
9508         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9509         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9510         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9511
9512         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9513 }
9514
9515 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9516 {
9517         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9518 }
9519
9520 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9521                                             u16 error_code)
9522 {
9523         bool inequality, bit;
9524
9525         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9526         inequality =
9527                 (error_code & vmcs12->page_fault_error_code_mask) !=
9528                  vmcs12->page_fault_error_code_match;
9529         return inequality ^ bit;
9530 }
9531
9532 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9533                 struct x86_exception *fault)
9534 {
9535         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9536
9537         WARN_ON(!is_guest_mode(vcpu));
9538
9539         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9540                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9541                                   vmcs_read32(VM_EXIT_INTR_INFO),
9542                                   vmcs_readl(EXIT_QUALIFICATION));
9543         else
9544                 kvm_inject_page_fault(vcpu, fault);
9545 }
9546
9547 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9548                                                struct vmcs12 *vmcs12);
9549
9550 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9551                                         struct vmcs12 *vmcs12)
9552 {
9553         struct vcpu_vmx *vmx = to_vmx(vcpu);
9554         u64 hpa;
9555
9556         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9557                 /*
9558                  * Translate L1 physical address to host physical
9559                  * address for vmcs02. Keep the page pinned, so this
9560                  * physical address remains valid. We keep a reference
9561                  * to it so we can release it later.
9562                  */
9563                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9564                         nested_release_page(vmx->nested.apic_access_page);
9565                 vmx->nested.apic_access_page =
9566                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9567                 /*
9568                  * If translation failed, no matter: This feature asks
9569                  * to exit when accessing the given address, and if it
9570                  * can never be accessed, this feature won't do
9571                  * anything anyway.
9572                  */
9573                 if (vmx->nested.apic_access_page) {
9574                         hpa = page_to_phys(vmx->nested.apic_access_page);
9575                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9576                 } else {
9577                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9578                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9579                 }
9580         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9581                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9582                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9583                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9584                 kvm_vcpu_reload_apic_access_page(vcpu);
9585         }
9586
9587         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9588                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9589                         nested_release_page(vmx->nested.virtual_apic_page);
9590                 vmx->nested.virtual_apic_page =
9591                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9592
9593                 /*
9594                  * If translation failed, VM entry will fail because
9595                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9596                  * Failing the vm entry is _not_ what the processor
9597                  * does but it's basically the only possibility we
9598                  * have.  We could still enter the guest if CR8 load
9599                  * exits are enabled, CR8 store exits are enabled, and
9600                  * virtualize APIC access is disabled; in this case
9601                  * the processor would never use the TPR shadow and we
9602                  * could simply clear the bit from the execution
9603                  * control.  But such a configuration is useless, so
9604                  * let's keep the code simple.
9605                  */
9606                 if (vmx->nested.virtual_apic_page) {
9607                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9608                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9609                 }
9610         }
9611
9612         if (nested_cpu_has_posted_intr(vmcs12)) {
9613                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9614                         kunmap(vmx->nested.pi_desc_page);
9615                         nested_release_page(vmx->nested.pi_desc_page);
9616                 }
9617                 vmx->nested.pi_desc_page =
9618                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9619                 vmx->nested.pi_desc =
9620                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9621                 if (!vmx->nested.pi_desc) {
9622                         nested_release_page_clean(vmx->nested.pi_desc_page);
9623                         return;
9624                 }
9625                 vmx->nested.pi_desc =
9626                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9627                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9628                         (PAGE_SIZE - 1)));
9629                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9630                         page_to_phys(vmx->nested.pi_desc_page) +
9631                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9632                         (PAGE_SIZE - 1)));
9633         }
9634         if (cpu_has_vmx_msr_bitmap() &&
9635             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9636             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9637                 ;
9638         else
9639                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9640                                 CPU_BASED_USE_MSR_BITMAPS);
9641 }
9642
9643 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9644 {
9645         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9646         struct vcpu_vmx *vmx = to_vmx(vcpu);
9647
9648         if (vcpu->arch.virtual_tsc_khz == 0)
9649                 return;
9650
9651         /* Make sure short timeouts reliably trigger an immediate vmexit.
9652          * hrtimer_start does not guarantee this. */
9653         if (preemption_timeout <= 1) {
9654                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9655                 return;
9656         }
9657
9658         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9659         preemption_timeout *= 1000000;
9660         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9661         hrtimer_start(&vmx->nested.preemption_timer,
9662                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9663 }
9664
9665 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9666                                                 struct vmcs12 *vmcs12)
9667 {
9668         int maxphyaddr;
9669         u64 addr;
9670
9671         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9672                 return 0;
9673
9674         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9675                 WARN_ON(1);
9676                 return -EINVAL;
9677         }
9678         maxphyaddr = cpuid_maxphyaddr(vcpu);
9679
9680         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9681            ((addr + PAGE_SIZE) >> maxphyaddr))
9682                 return -EINVAL;
9683
9684         return 0;
9685 }
9686
9687 /*
9688  * Merge L0's and L1's MSR bitmap, return false to indicate that
9689  * we do not use the hardware.
9690  */
9691 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9692                                                struct vmcs12 *vmcs12)
9693 {
9694         int msr;
9695         struct page *page;
9696         unsigned long *msr_bitmap_l1;
9697         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9698
9699         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9700         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9701                 return false;
9702
9703         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9704         if (!page)
9705                 return false;
9706         msr_bitmap_l1 = (unsigned long *)kmap(page);
9707
9708         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9709
9710         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9711                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9712                         for (msr = 0x800; msr <= 0x8ff; msr++)
9713                                 nested_vmx_disable_intercept_for_msr(
9714                                         msr_bitmap_l1, msr_bitmap_l0,
9715                                         msr, MSR_TYPE_R);
9716
9717                 nested_vmx_disable_intercept_for_msr(
9718                                 msr_bitmap_l1, msr_bitmap_l0,
9719                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9720                                 MSR_TYPE_R | MSR_TYPE_W);
9721
9722                 if (nested_cpu_has_vid(vmcs12)) {
9723                         nested_vmx_disable_intercept_for_msr(
9724                                 msr_bitmap_l1, msr_bitmap_l0,
9725                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9726                                 MSR_TYPE_W);
9727                         nested_vmx_disable_intercept_for_msr(
9728                                 msr_bitmap_l1, msr_bitmap_l0,
9729                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9730                                 MSR_TYPE_W);
9731                 }
9732         }
9733         kunmap(page);
9734         nested_release_page_clean(page);
9735
9736         return true;
9737 }
9738
9739 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9740                                            struct vmcs12 *vmcs12)
9741 {
9742         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9743             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9744             !nested_cpu_has_vid(vmcs12) &&
9745             !nested_cpu_has_posted_intr(vmcs12))
9746                 return 0;
9747
9748         /*
9749          * If virtualize x2apic mode is enabled,
9750          * virtualize apic access must be disabled.
9751          */
9752         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9753             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9754                 return -EINVAL;
9755
9756         /*
9757          * If virtual interrupt delivery is enabled,
9758          * we must exit on external interrupts.
9759          */
9760         if (nested_cpu_has_vid(vmcs12) &&
9761            !nested_exit_on_intr(vcpu))
9762                 return -EINVAL;
9763
9764         /*
9765          * bits 15:8 should be zero in posted_intr_nv,
9766          * the descriptor address has been already checked
9767          * in nested_get_vmcs12_pages.
9768          */
9769         if (nested_cpu_has_posted_intr(vmcs12) &&
9770            (!nested_cpu_has_vid(vmcs12) ||
9771             !nested_exit_intr_ack_set(vcpu) ||
9772             vmcs12->posted_intr_nv & 0xff00))
9773                 return -EINVAL;
9774
9775         /* tpr shadow is needed by all apicv features. */
9776         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9777                 return -EINVAL;
9778
9779         return 0;
9780 }
9781
9782 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9783                                        unsigned long count_field,
9784                                        unsigned long addr_field)
9785 {
9786         int maxphyaddr;
9787         u64 count, addr;
9788
9789         if (vmcs12_read_any(vcpu, count_field, &count) ||
9790             vmcs12_read_any(vcpu, addr_field, &addr)) {
9791                 WARN_ON(1);
9792                 return -EINVAL;
9793         }
9794         if (count == 0)
9795                 return 0;
9796         maxphyaddr = cpuid_maxphyaddr(vcpu);
9797         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9798             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9799                 pr_debug_ratelimited(
9800                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9801                         addr_field, maxphyaddr, count, addr);
9802                 return -EINVAL;
9803         }
9804         return 0;
9805 }
9806
9807 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9808                                                 struct vmcs12 *vmcs12)
9809 {
9810         if (vmcs12->vm_exit_msr_load_count == 0 &&
9811             vmcs12->vm_exit_msr_store_count == 0 &&
9812             vmcs12->vm_entry_msr_load_count == 0)
9813                 return 0; /* Fast path */
9814         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9815                                         VM_EXIT_MSR_LOAD_ADDR) ||
9816             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9817                                         VM_EXIT_MSR_STORE_ADDR) ||
9818             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9819                                         VM_ENTRY_MSR_LOAD_ADDR))
9820                 return -EINVAL;
9821         return 0;
9822 }
9823
9824 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9825                                        struct vmx_msr_entry *e)
9826 {
9827         /* x2APIC MSR accesses are not allowed */
9828         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9829                 return -EINVAL;
9830         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9831             e->index == MSR_IA32_UCODE_REV)
9832                 return -EINVAL;
9833         if (e->reserved != 0)
9834                 return -EINVAL;
9835         return 0;
9836 }
9837
9838 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9839                                      struct vmx_msr_entry *e)
9840 {
9841         if (e->index == MSR_FS_BASE ||
9842             e->index == MSR_GS_BASE ||
9843             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9844             nested_vmx_msr_check_common(vcpu, e))
9845                 return -EINVAL;
9846         return 0;
9847 }
9848
9849 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9850                                       struct vmx_msr_entry *e)
9851 {
9852         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9853             nested_vmx_msr_check_common(vcpu, e))
9854                 return -EINVAL;
9855         return 0;
9856 }
9857
9858 /*
9859  * Load guest's/host's msr at nested entry/exit.
9860  * return 0 for success, entry index for failure.
9861  */
9862 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9863 {
9864         u32 i;
9865         struct vmx_msr_entry e;
9866         struct msr_data msr;
9867
9868         msr.host_initiated = false;
9869         for (i = 0; i < count; i++) {
9870                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9871                                         &e, sizeof(e))) {
9872                         pr_debug_ratelimited(
9873                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9874                                 __func__, i, gpa + i * sizeof(e));
9875                         goto fail;
9876                 }
9877                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9878                         pr_debug_ratelimited(
9879                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9880                                 __func__, i, e.index, e.reserved);
9881                         goto fail;
9882                 }
9883                 msr.index = e.index;
9884                 msr.data = e.value;
9885                 if (kvm_set_msr(vcpu, &msr)) {
9886                         pr_debug_ratelimited(
9887                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9888                                 __func__, i, e.index, e.value);
9889                         goto fail;
9890                 }
9891         }
9892         return 0;
9893 fail:
9894         return i + 1;
9895 }
9896
9897 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9898 {
9899         u32 i;
9900         struct vmx_msr_entry e;
9901
9902         for (i = 0; i < count; i++) {
9903                 struct msr_data msr_info;
9904                 if (kvm_vcpu_read_guest(vcpu,
9905                                         gpa + i * sizeof(e),
9906                                         &e, 2 * sizeof(u32))) {
9907                         pr_debug_ratelimited(
9908                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9909                                 __func__, i, gpa + i * sizeof(e));
9910                         return -EINVAL;
9911                 }
9912                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9913                         pr_debug_ratelimited(
9914                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9915                                 __func__, i, e.index, e.reserved);
9916                         return -EINVAL;
9917                 }
9918                 msr_info.host_initiated = false;
9919                 msr_info.index = e.index;
9920                 if (kvm_get_msr(vcpu, &msr_info)) {
9921                         pr_debug_ratelimited(
9922                                 "%s cannot read MSR (%u, 0x%x)\n",
9923                                 __func__, i, e.index);
9924                         return -EINVAL;
9925                 }
9926                 if (kvm_vcpu_write_guest(vcpu,
9927                                          gpa + i * sizeof(e) +
9928                                              offsetof(struct vmx_msr_entry, value),
9929                                          &msr_info.data, sizeof(msr_info.data))) {
9930                         pr_debug_ratelimited(
9931                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9932                                 __func__, i, e.index, msr_info.data);
9933                         return -EINVAL;
9934                 }
9935         }
9936         return 0;
9937 }
9938
9939 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9940 {
9941         unsigned long invalid_mask;
9942
9943         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9944         return (val & invalid_mask) == 0;
9945 }
9946
9947 /*
9948  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9949  * emulating VM entry into a guest with EPT enabled.
9950  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9951  * is assigned to entry_failure_code on failure.
9952  */
9953 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9954                                u32 *entry_failure_code)
9955 {
9956         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9957                 if (!nested_cr3_valid(vcpu, cr3)) {
9958                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9959                         return 1;
9960                 }
9961
9962                 /*
9963                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9964                  * must not be dereferenced.
9965                  */
9966                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9967                     !nested_ept) {
9968                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9969                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9970                                 return 1;
9971                         }
9972                 }
9973
9974                 vcpu->arch.cr3 = cr3;
9975                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9976         }
9977
9978         kvm_mmu_reset_context(vcpu);
9979         return 0;
9980 }
9981
9982 /*
9983  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9984  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9985  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9986  * guest in a way that will both be appropriate to L1's requests, and our
9987  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9988  * function also has additional necessary side-effects, like setting various
9989  * vcpu->arch fields.
9990  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9991  * is assigned to entry_failure_code on failure.
9992  */
9993 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9994                           bool from_vmentry, u32 *entry_failure_code)
9995 {
9996         struct vcpu_vmx *vmx = to_vmx(vcpu);
9997         u32 exec_control;
9998
9999         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
10000         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
10001         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
10002         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
10003         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
10004         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
10005         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
10006         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
10007         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
10008         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
10009         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
10010         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
10011         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
10012         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
10013         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
10014         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
10015         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
10016         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
10017         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
10018         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
10019         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
10020         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
10021         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
10022         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
10023         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
10024         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
10025         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
10026         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
10027         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
10028         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
10029         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
10030         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
10031         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
10032         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
10033         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
10034         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
10035
10036         if (from_vmentry &&
10037             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
10038                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
10039                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
10040         } else {
10041                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
10042                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
10043         }
10044         if (from_vmentry) {
10045                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
10046                              vmcs12->vm_entry_intr_info_field);
10047                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
10048                              vmcs12->vm_entry_exception_error_code);
10049                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
10050                              vmcs12->vm_entry_instruction_len);
10051                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
10052                              vmcs12->guest_interruptibility_info);
10053         } else {
10054                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
10055         }
10056         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10057         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10058         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10059                 vmcs12->guest_pending_dbg_exceptions);
10060         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10061         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10062
10063         if (nested_cpu_has_xsaves(vmcs12))
10064                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10065         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10066
10067         exec_control = vmcs12->pin_based_vm_exec_control;
10068
10069         /* Preemption timer setting is only taken from vmcs01.  */
10070         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10071         exec_control |= vmcs_config.pin_based_exec_ctrl;
10072         if (vmx->hv_deadline_tsc == -1)
10073                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10074
10075         /* Posted interrupts setting is only taken from vmcs12.  */
10076         if (nested_cpu_has_posted_intr(vmcs12)) {
10077                 /*
10078                  * Note that we use L0's vector here and in
10079                  * vmx_deliver_nested_posted_interrupt.
10080                  */
10081                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10082                 vmx->nested.pi_pending = false;
10083                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10084         } else {
10085                 exec_control &= ~PIN_BASED_POSTED_INTR;
10086         }
10087
10088         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10089
10090         vmx->nested.preemption_timer_expired = false;
10091         if (nested_cpu_has_preemption_timer(vmcs12))
10092                 vmx_start_preemption_timer(vcpu);
10093
10094         /*
10095          * Whether page-faults are trapped is determined by a combination of
10096          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10097          * If enable_ept, L0 doesn't care about page faults and we should
10098          * set all of these to L1's desires. However, if !enable_ept, L0 does
10099          * care about (at least some) page faults, and because it is not easy
10100          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10101          * to exit on each and every L2 page fault. This is done by setting
10102          * MASK=MATCH=0 and (see below) EB.PF=1.
10103          * Note that below we don't need special code to set EB.PF beyond the
10104          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10105          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10106          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10107          *
10108          * A problem with this approach (when !enable_ept) is that L1 may be
10109          * injected with more page faults than it asked for. This could have
10110          * caused problems, but in practice existing hypervisors don't care.
10111          * To fix this, we will need to emulate the PFEC checking (on the L1
10112          * page tables), using walk_addr(), when injecting PFs to L1.
10113          */
10114         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10115                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10116         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10117                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10118
10119         if (cpu_has_secondary_exec_ctrls()) {
10120                 exec_control = vmx_secondary_exec_control(vmx);
10121
10122                 /* Take the following fields only from vmcs12 */
10123                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10124                                   SECONDARY_EXEC_RDTSCP |
10125                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10126                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10127                 if (nested_cpu_has(vmcs12,
10128                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
10129                         exec_control |= vmcs12->secondary_vm_exec_control;
10130
10131                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10132                         vmcs_write64(EOI_EXIT_BITMAP0,
10133                                 vmcs12->eoi_exit_bitmap0);
10134                         vmcs_write64(EOI_EXIT_BITMAP1,
10135                                 vmcs12->eoi_exit_bitmap1);
10136                         vmcs_write64(EOI_EXIT_BITMAP2,
10137                                 vmcs12->eoi_exit_bitmap2);
10138                         vmcs_write64(EOI_EXIT_BITMAP3,
10139                                 vmcs12->eoi_exit_bitmap3);
10140                         vmcs_write16(GUEST_INTR_STATUS,
10141                                 vmcs12->guest_intr_status);
10142                 }
10143
10144                 /*
10145                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10146                  * nested_get_vmcs12_pages will either fix it up or
10147                  * remove the VM execution control.
10148                  */
10149                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10150                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10151
10152                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10153         }
10154
10155
10156         /*
10157          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10158          * Some constant fields are set here by vmx_set_constant_host_state().
10159          * Other fields are different per CPU, and will be set later when
10160          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10161          */
10162         vmx_set_constant_host_state(vmx);
10163
10164         /*
10165          * Set the MSR load/store lists to match L0's settings.
10166          */
10167         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10168         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10169         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10170         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10171         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10172
10173         /*
10174          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10175          * entry, but only if the current (host) sp changed from the value
10176          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10177          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10178          * here we just force the write to happen on entry.
10179          */
10180         vmx->host_rsp = 0;
10181
10182         exec_control = vmx_exec_control(vmx); /* L0's desires */
10183         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10184         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10185         exec_control &= ~CPU_BASED_TPR_SHADOW;
10186         exec_control |= vmcs12->cpu_based_vm_exec_control;
10187
10188         /*
10189          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10190          * nested_get_vmcs12_pages can't fix it up, the illegal value
10191          * will result in a VM entry failure.
10192          */
10193         if (exec_control & CPU_BASED_TPR_SHADOW) {
10194                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10195                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10196         }
10197
10198         /*
10199          * Merging of IO bitmap not currently supported.
10200          * Rather, exit every time.
10201          */
10202         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10203         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10204
10205         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10206
10207         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10208          * bitwise-or of what L1 wants to trap for L2, and what we want to
10209          * trap. Note that CR0.TS also needs updating - we do this later.
10210          */
10211         update_exception_bitmap(vcpu);
10212         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10213         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10214
10215         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10216          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10217          * bits are further modified by vmx_set_efer() below.
10218          */
10219         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10220
10221         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10222          * emulated by vmx_set_efer(), below.
10223          */
10224         vm_entry_controls_init(vmx,
10225                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10226                         ~VM_ENTRY_IA32E_MODE) |
10227                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10228
10229         if (from_vmentry &&
10230             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10231                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10232                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10233         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10234                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10235         }
10236
10237         set_cr4_guest_host_mask(vmx);
10238
10239         if (from_vmentry &&
10240             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10241                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10242
10243         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10244                 vmcs_write64(TSC_OFFSET,
10245                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10246         else
10247                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10248         if (kvm_has_tsc_control)
10249                 decache_tsc_multiplier(vmx);
10250
10251         if (enable_vpid) {
10252                 /*
10253                  * There is no direct mapping between vpid02 and vpid12, the
10254                  * vpid02 is per-vCPU for L0 and reused while the value of
10255                  * vpid12 is changed w/ one invvpid during nested vmentry.
10256                  * The vpid12 is allocated by L1 for L2, so it will not
10257                  * influence global bitmap(for vpid01 and vpid02 allocation)
10258                  * even if spawn a lot of nested vCPUs.
10259                  */
10260                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10261                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10262                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10263                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10264                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10265                         }
10266                 } else {
10267                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10268                         vmx_flush_tlb(vcpu);
10269                 }
10270
10271         }
10272
10273         if (enable_pml) {
10274                 /*
10275                  * Conceptually we want to copy the PML address and index from
10276                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10277                  * since we always flush the log on each vmexit, this happens
10278                  * to be equivalent to simply resetting the fields in vmcs02.
10279                  */
10280                 ASSERT(vmx->pml_pg);
10281                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10282                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10283         }
10284
10285         if (nested_cpu_has_ept(vmcs12)) {
10286                 kvm_mmu_unload(vcpu);
10287                 nested_ept_init_mmu_context(vcpu);
10288         } else if (nested_cpu_has2(vmcs12,
10289                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10290                 vmx_flush_tlb_ept_only(vcpu);
10291         }
10292
10293         /*
10294          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10295          * bits which we consider mandatory enabled.
10296          * The CR0_READ_SHADOW is what L2 should have expected to read given
10297          * the specifications by L1; It's not enough to take
10298          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10299          * have more bits than L1 expected.
10300          */
10301         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10302         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10303
10304         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10305         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10306
10307         if (from_vmentry &&
10308             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10309                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10310         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10311                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10312         else
10313                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10314         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10315         vmx_set_efer(vcpu, vcpu->arch.efer);
10316
10317         /* Shadow page tables on either EPT or shadow page tables. */
10318         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10319                                 entry_failure_code))
10320                 return 1;
10321
10322         if (!enable_ept)
10323                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10324
10325         /*
10326          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10327          */
10328         if (enable_ept) {
10329                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10330                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10331                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10332                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10333         }
10334
10335         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10336         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10337         return 0;
10338 }
10339
10340 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10341 {
10342         struct vcpu_vmx *vmx = to_vmx(vcpu);
10343
10344         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10345             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10346                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10347
10348         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10349                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10350
10351         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10352                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10353
10354         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10355                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10356
10357         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10358                                 vmx->nested.nested_vmx_procbased_ctls_low,
10359                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10360             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10361                                 vmx->nested.nested_vmx_secondary_ctls_low,
10362                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10363             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10364                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10365                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10366             !vmx_control_verify(vmcs12->vm_exit_controls,
10367                                 vmx->nested.nested_vmx_exit_ctls_low,
10368                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10369             !vmx_control_verify(vmcs12->vm_entry_controls,
10370                                 vmx->nested.nested_vmx_entry_ctls_low,
10371                                 vmx->nested.nested_vmx_entry_ctls_high))
10372                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10373
10374         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10375             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10376             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10377                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10378
10379         return 0;
10380 }
10381
10382 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10383                                   u32 *exit_qual)
10384 {
10385         bool ia32e;
10386
10387         *exit_qual = ENTRY_FAIL_DEFAULT;
10388
10389         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10390             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10391                 return 1;
10392
10393         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10394             vmcs12->vmcs_link_pointer != -1ull) {
10395                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10396                 return 1;
10397         }
10398
10399         /*
10400          * If the load IA32_EFER VM-entry control is 1, the following checks
10401          * are performed on the field for the IA32_EFER MSR:
10402          * - Bits reserved in the IA32_EFER MSR must be 0.
10403          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10404          *   the IA-32e mode guest VM-exit control. It must also be identical
10405          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10406          *   CR0.PG) is 1.
10407          */
10408         if (to_vmx(vcpu)->nested.nested_run_pending &&
10409             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10410                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10411                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10412                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10413                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10414                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10415                         return 1;
10416         }
10417
10418         /*
10419          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10420          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10421          * the values of the LMA and LME bits in the field must each be that of
10422          * the host address-space size VM-exit control.
10423          */
10424         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10425                 ia32e = (vmcs12->vm_exit_controls &
10426                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10427                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10428                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10429                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10430                         return 1;
10431         }
10432
10433         return 0;
10434 }
10435
10436 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10437 {
10438         struct vcpu_vmx *vmx = to_vmx(vcpu);
10439         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10440         struct loaded_vmcs *vmcs02;
10441         int cpu;
10442         u32 msr_entry_idx;
10443         u32 exit_qual;
10444
10445         vmcs02 = nested_get_current_vmcs02(vmx);
10446         if (!vmcs02)
10447                 return -ENOMEM;
10448
10449         enter_guest_mode(vcpu);
10450
10451         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10452                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10453
10454         cpu = get_cpu();
10455         vmx->loaded_vmcs = vmcs02;
10456         vmx_vcpu_put(vcpu);
10457         vmx_vcpu_load(vcpu, cpu);
10458         vcpu->cpu = cpu;
10459         put_cpu();
10460
10461         vmx_segment_cache_clear(vmx);
10462
10463         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10464                 leave_guest_mode(vcpu);
10465                 vmx_load_vmcs01(vcpu);
10466                 nested_vmx_entry_failure(vcpu, vmcs12,
10467                                          EXIT_REASON_INVALID_STATE, exit_qual);
10468                 return 1;
10469         }
10470
10471         nested_get_vmcs12_pages(vcpu, vmcs12);
10472
10473         msr_entry_idx = nested_vmx_load_msr(vcpu,
10474                                             vmcs12->vm_entry_msr_load_addr,
10475                                             vmcs12->vm_entry_msr_load_count);
10476         if (msr_entry_idx) {
10477                 leave_guest_mode(vcpu);
10478                 vmx_load_vmcs01(vcpu);
10479                 nested_vmx_entry_failure(vcpu, vmcs12,
10480                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10481                 return 1;
10482         }
10483
10484         vmcs12->launch_state = 1;
10485
10486         /*
10487          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10488          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10489          * returned as far as L1 is concerned. It will only return (and set
10490          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10491          */
10492         return 0;
10493 }
10494
10495 /*
10496  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10497  * for running an L2 nested guest.
10498  */
10499 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10500 {
10501         struct vmcs12 *vmcs12;
10502         struct vcpu_vmx *vmx = to_vmx(vcpu);
10503         u32 exit_qual;
10504         int ret;
10505
10506         if (!nested_vmx_check_permission(vcpu))
10507                 return 1;
10508
10509         if (!nested_vmx_check_vmcs12(vcpu))
10510                 goto out;
10511
10512         vmcs12 = get_vmcs12(vcpu);
10513
10514         if (enable_shadow_vmcs)
10515                 copy_shadow_to_vmcs12(vmx);
10516
10517         /*
10518          * The nested entry process starts with enforcing various prerequisites
10519          * on vmcs12 as required by the Intel SDM, and act appropriately when
10520          * they fail: As the SDM explains, some conditions should cause the
10521          * instruction to fail, while others will cause the instruction to seem
10522          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10523          * To speed up the normal (success) code path, we should avoid checking
10524          * for misconfigurations which will anyway be caught by the processor
10525          * when using the merged vmcs02.
10526          */
10527         if (vmcs12->launch_state == launch) {
10528                 nested_vmx_failValid(vcpu,
10529                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10530                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10531                 goto out;
10532         }
10533
10534         ret = check_vmentry_prereqs(vcpu, vmcs12);
10535         if (ret) {
10536                 nested_vmx_failValid(vcpu, ret);
10537                 goto out;
10538         }
10539
10540         /*
10541          * After this point, the trap flag no longer triggers a singlestep trap
10542          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10543          * This is not 100% correct; for performance reasons, we delegate most
10544          * of the checks on host state to the processor.  If those fail,
10545          * the singlestep trap is missed.
10546          */
10547         skip_emulated_instruction(vcpu);
10548
10549         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10550         if (ret) {
10551                 nested_vmx_entry_failure(vcpu, vmcs12,
10552                                          EXIT_REASON_INVALID_STATE, exit_qual);
10553                 return 1;
10554         }
10555
10556         /*
10557          * We're finally done with prerequisite checking, and can start with
10558          * the nested entry.
10559          */
10560
10561         ret = enter_vmx_non_root_mode(vcpu, true);
10562         if (ret)
10563                 return ret;
10564
10565         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10566                 return kvm_vcpu_halt(vcpu);
10567
10568         vmx->nested.nested_run_pending = 1;
10569
10570         return 1;
10571
10572 out:
10573         return kvm_skip_emulated_instruction(vcpu);
10574 }
10575
10576 /*
10577  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10578  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10579  * This function returns the new value we should put in vmcs12.guest_cr0.
10580  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10581  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10582  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10583  *     didn't trap the bit, because if L1 did, so would L0).
10584  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10585  *     been modified by L2, and L1 knows it. So just leave the old value of
10586  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10587  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10588  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10589  *     changed these bits, and therefore they need to be updated, but L0
10590  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10591  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10592  */
10593 static inline unsigned long
10594 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10595 {
10596         return
10597         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10598         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10599         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10600                         vcpu->arch.cr0_guest_owned_bits));
10601 }
10602
10603 static inline unsigned long
10604 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10605 {
10606         return
10607         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10608         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10609         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10610                         vcpu->arch.cr4_guest_owned_bits));
10611 }
10612
10613 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10614                                        struct vmcs12 *vmcs12)
10615 {
10616         u32 idt_vectoring;
10617         unsigned int nr;
10618
10619         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10620                 nr = vcpu->arch.exception.nr;
10621                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10622
10623                 if (kvm_exception_is_soft(nr)) {
10624                         vmcs12->vm_exit_instruction_len =
10625                                 vcpu->arch.event_exit_inst_len;
10626                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10627                 } else
10628                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10629
10630                 if (vcpu->arch.exception.has_error_code) {
10631                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10632                         vmcs12->idt_vectoring_error_code =
10633                                 vcpu->arch.exception.error_code;
10634                 }
10635
10636                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10637         } else if (vcpu->arch.nmi_injected) {
10638                 vmcs12->idt_vectoring_info_field =
10639                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10640         } else if (vcpu->arch.interrupt.pending) {
10641                 nr = vcpu->arch.interrupt.nr;
10642                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10643
10644                 if (vcpu->arch.interrupt.soft) {
10645                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10646                         vmcs12->vm_entry_instruction_len =
10647                                 vcpu->arch.event_exit_inst_len;
10648                 } else
10649                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10650
10651                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10652         }
10653 }
10654
10655 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10656 {
10657         struct vcpu_vmx *vmx = to_vmx(vcpu);
10658
10659         if (vcpu->arch.exception.pending ||
10660                 vcpu->arch.nmi_injected ||
10661                 vcpu->arch.interrupt.pending)
10662                 return -EBUSY;
10663
10664         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10665             vmx->nested.preemption_timer_expired) {
10666                 if (vmx->nested.nested_run_pending)
10667                         return -EBUSY;
10668                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10669                 return 0;
10670         }
10671
10672         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10673                 if (vmx->nested.nested_run_pending)
10674                         return -EBUSY;
10675                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10676                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10677                                   INTR_INFO_VALID_MASK, 0);
10678                 /*
10679                  * The NMI-triggered VM exit counts as injection:
10680                  * clear this one and block further NMIs.
10681                  */
10682                 vcpu->arch.nmi_pending = 0;
10683                 vmx_set_nmi_mask(vcpu, true);
10684                 return 0;
10685         }
10686
10687         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10688             nested_exit_on_intr(vcpu)) {
10689                 if (vmx->nested.nested_run_pending)
10690                         return -EBUSY;
10691                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10692                 return 0;
10693         }
10694
10695         vmx_complete_nested_posted_interrupt(vcpu);
10696         return 0;
10697 }
10698
10699 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10700 {
10701         ktime_t remaining =
10702                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10703         u64 value;
10704
10705         if (ktime_to_ns(remaining) <= 0)
10706                 return 0;
10707
10708         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10709         do_div(value, 1000000);
10710         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10711 }
10712
10713 /*
10714  * Update the guest state fields of vmcs12 to reflect changes that
10715  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10716  * VM-entry controls is also updated, since this is really a guest
10717  * state bit.)
10718  */
10719 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10720 {
10721         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10722         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10723
10724         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10725         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10726         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10727
10728         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10729         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10730         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10731         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10732         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10733         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10734         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10735         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10736         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10737         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10738         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10739         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10740         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10741         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10742         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10743         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10744         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10745         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10746         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10747         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10748         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10749         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10750         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10751         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10752         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10753         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10754         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10755         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10756         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10757         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10758         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10759         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10760         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10761         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10762         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10763         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10764
10765         vmcs12->guest_interruptibility_info =
10766                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10767         vmcs12->guest_pending_dbg_exceptions =
10768                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10769         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10770                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10771         else
10772                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10773
10774         if (nested_cpu_has_preemption_timer(vmcs12)) {
10775                 if (vmcs12->vm_exit_controls &
10776                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10777                         vmcs12->vmx_preemption_timer_value =
10778                                 vmx_get_preemption_timer_value(vcpu);
10779                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10780         }
10781
10782         /*
10783          * In some cases (usually, nested EPT), L2 is allowed to change its
10784          * own CR3 without exiting. If it has changed it, we must keep it.
10785          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10786          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10787          *
10788          * Additionally, restore L2's PDPTR to vmcs12.
10789          */
10790         if (enable_ept) {
10791                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10792                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10793                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10794                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10795                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10796         }
10797
10798         if (nested_cpu_has_ept(vmcs12))
10799                 vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10800
10801         if (nested_cpu_has_vid(vmcs12))
10802                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10803
10804         vmcs12->vm_entry_controls =
10805                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10806                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10807
10808         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10809                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10810                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10811         }
10812
10813         /* TODO: These cannot have changed unless we have MSR bitmaps and
10814          * the relevant bit asks not to trap the change */
10815         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10816                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10817         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10818                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10819         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10820         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10821         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10822         if (kvm_mpx_supported())
10823                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10824         if (nested_cpu_has_xsaves(vmcs12))
10825                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10826 }
10827
10828 /*
10829  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10830  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10831  * and this function updates it to reflect the changes to the guest state while
10832  * L2 was running (and perhaps made some exits which were handled directly by L0
10833  * without going back to L1), and to reflect the exit reason.
10834  * Note that we do not have to copy here all VMCS fields, just those that
10835  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10836  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10837  * which already writes to vmcs12 directly.
10838  */
10839 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10840                            u32 exit_reason, u32 exit_intr_info,
10841                            unsigned long exit_qualification)
10842 {
10843         /* update guest state fields: */
10844         sync_vmcs12(vcpu, vmcs12);
10845
10846         /* update exit information fields: */
10847
10848         vmcs12->vm_exit_reason = exit_reason;
10849         vmcs12->exit_qualification = exit_qualification;
10850
10851         vmcs12->vm_exit_intr_info = exit_intr_info;
10852         if ((vmcs12->vm_exit_intr_info &
10853              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10854             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10855                 vmcs12->vm_exit_intr_error_code =
10856                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10857         vmcs12->idt_vectoring_info_field = 0;
10858         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10859         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10860
10861         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10862                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10863                  * instead of reading the real value. */
10864                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10865
10866                 /*
10867                  * Transfer the event that L0 or L1 may wanted to inject into
10868                  * L2 to IDT_VECTORING_INFO_FIELD.
10869                  */
10870                 vmcs12_save_pending_event(vcpu, vmcs12);
10871         }
10872
10873         /*
10874          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10875          * preserved above and would only end up incorrectly in L1.
10876          */
10877         vcpu->arch.nmi_injected = false;
10878         kvm_clear_exception_queue(vcpu);
10879         kvm_clear_interrupt_queue(vcpu);
10880 }
10881
10882 /*
10883  * A part of what we need to when the nested L2 guest exits and we want to
10884  * run its L1 parent, is to reset L1's guest state to the host state specified
10885  * in vmcs12.
10886  * This function is to be called not only on normal nested exit, but also on
10887  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10888  * Failures During or After Loading Guest State").
10889  * This function should be called when the active VMCS is L1's (vmcs01).
10890  */
10891 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10892                                    struct vmcs12 *vmcs12)
10893 {
10894         struct kvm_segment seg;
10895         u32 entry_failure_code;
10896
10897         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10898                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10899         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10900                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10901         else
10902                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10903         vmx_set_efer(vcpu, vcpu->arch.efer);
10904
10905         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10906         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10907         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10908         /*
10909          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10910          * actually changed, because vmx_set_cr0 refers to efer set above.
10911          *
10912          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10913          * (KVM doesn't change it);
10914          */
10915         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10916         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10917
10918         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10919         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10920         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10921
10922         nested_ept_uninit_mmu_context(vcpu);
10923
10924         /*
10925          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10926          * couldn't have changed.
10927          */
10928         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10929                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10930
10931         if (!enable_ept)
10932                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10933
10934         if (enable_vpid) {
10935                 /*
10936                  * Trivially support vpid by letting L2s share their parent
10937                  * L1's vpid. TODO: move to a more elaborate solution, giving
10938                  * each L2 its own vpid and exposing the vpid feature to L1.
10939                  */
10940                 vmx_flush_tlb(vcpu);
10941         }
10942
10943
10944         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10945         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10946         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10947         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10948         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10949
10950         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10951         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10952                 vmcs_write64(GUEST_BNDCFGS, 0);
10953
10954         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10955                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10956                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10957         }
10958         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10959                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10960                         vmcs12->host_ia32_perf_global_ctrl);
10961
10962         /* Set L1 segment info according to Intel SDM
10963             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10964         seg = (struct kvm_segment) {
10965                 .base = 0,
10966                 .limit = 0xFFFFFFFF,
10967                 .selector = vmcs12->host_cs_selector,
10968                 .type = 11,
10969                 .present = 1,
10970                 .s = 1,
10971                 .g = 1
10972         };
10973         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10974                 seg.l = 1;
10975         else
10976                 seg.db = 1;
10977         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10978         seg = (struct kvm_segment) {
10979                 .base = 0,
10980                 .limit = 0xFFFFFFFF,
10981                 .type = 3,
10982                 .present = 1,
10983                 .s = 1,
10984                 .db = 1,
10985                 .g = 1
10986         };
10987         seg.selector = vmcs12->host_ds_selector;
10988         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10989         seg.selector = vmcs12->host_es_selector;
10990         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10991         seg.selector = vmcs12->host_ss_selector;
10992         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10993         seg.selector = vmcs12->host_fs_selector;
10994         seg.base = vmcs12->host_fs_base;
10995         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10996         seg.selector = vmcs12->host_gs_selector;
10997         seg.base = vmcs12->host_gs_base;
10998         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10999         seg = (struct kvm_segment) {
11000                 .base = vmcs12->host_tr_base,
11001                 .limit = 0x67,
11002                 .selector = vmcs12->host_tr_selector,
11003                 .type = 11,
11004                 .present = 1
11005         };
11006         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
11007
11008         kvm_set_dr(vcpu, 7, 0x400);
11009         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
11010
11011         if (cpu_has_vmx_msr_bitmap())
11012                 vmx_set_msr_bitmap(vcpu);
11013
11014         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
11015                                 vmcs12->vm_exit_msr_load_count))
11016                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
11017 }
11018
11019 /*
11020  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11021  * and modify vmcs12 to make it see what it would expect to see there if
11022  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11023  */
11024 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
11025                               u32 exit_intr_info,
11026                               unsigned long exit_qualification)
11027 {
11028         struct vcpu_vmx *vmx = to_vmx(vcpu);
11029         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
11030         u32 vm_inst_error = 0;
11031
11032         /* trying to cancel vmlaunch/vmresume is a bug */
11033         WARN_ON_ONCE(vmx->nested.nested_run_pending);
11034
11035         leave_guest_mode(vcpu);
11036         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
11037                        exit_qualification);
11038
11039         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
11040                                  vmcs12->vm_exit_msr_store_count))
11041                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
11042
11043         if (unlikely(vmx->fail))
11044                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
11045
11046         vmx_load_vmcs01(vcpu);
11047
11048         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
11049             && nested_exit_intr_ack_set(vcpu)) {
11050                 int irq = kvm_cpu_get_interrupt(vcpu);
11051                 WARN_ON(irq < 0);
11052                 vmcs12->vm_exit_intr_info = irq |
11053                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
11054         }
11055
11056         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11057                                        vmcs12->exit_qualification,
11058                                        vmcs12->idt_vectoring_info_field,
11059                                        vmcs12->vm_exit_intr_info,
11060                                        vmcs12->vm_exit_intr_error_code,
11061                                        KVM_ISA_VMX);
11062
11063         vm_entry_controls_reset_shadow(vmx);
11064         vm_exit_controls_reset_shadow(vmx);
11065         vmx_segment_cache_clear(vmx);
11066
11067         /* if no vmcs02 cache requested, remove the one we used */
11068         if (VMCS02_POOL_SIZE == 0)
11069                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11070
11071         load_vmcs12_host_state(vcpu, vmcs12);
11072
11073         /* Update any VMCS fields that might have changed while L2 ran */
11074         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11075         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11076         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11077         if (vmx->hv_deadline_tsc == -1)
11078                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11079                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11080         else
11081                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11082                               PIN_BASED_VMX_PREEMPTION_TIMER);
11083         if (kvm_has_tsc_control)
11084                 decache_tsc_multiplier(vmx);
11085
11086         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11087                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11088                 vmx_set_virtual_x2apic_mode(vcpu,
11089                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11090         } else if (!nested_cpu_has_ept(vmcs12) &&
11091                    nested_cpu_has2(vmcs12,
11092                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11093                 vmx_flush_tlb_ept_only(vcpu);
11094         }
11095
11096         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11097         vmx->host_rsp = 0;
11098
11099         /* Unpin physical memory we referred to in vmcs02 */
11100         if (vmx->nested.apic_access_page) {
11101                 nested_release_page(vmx->nested.apic_access_page);
11102                 vmx->nested.apic_access_page = NULL;
11103         }
11104         if (vmx->nested.virtual_apic_page) {
11105                 nested_release_page(vmx->nested.virtual_apic_page);
11106                 vmx->nested.virtual_apic_page = NULL;
11107         }
11108         if (vmx->nested.pi_desc_page) {
11109                 kunmap(vmx->nested.pi_desc_page);
11110                 nested_release_page(vmx->nested.pi_desc_page);
11111                 vmx->nested.pi_desc_page = NULL;
11112                 vmx->nested.pi_desc = NULL;
11113         }
11114
11115         /*
11116          * We are now running in L2, mmu_notifier will force to reload the
11117          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11118          */
11119         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11120
11121         /*
11122          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11123          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11124          * success or failure flag accordingly.
11125          */
11126         if (unlikely(vmx->fail)) {
11127                 vmx->fail = 0;
11128                 nested_vmx_failValid(vcpu, vm_inst_error);
11129         } else
11130                 nested_vmx_succeed(vcpu);
11131         if (enable_shadow_vmcs)
11132                 vmx->nested.sync_shadow_vmcs = true;
11133
11134         /* in case we halted in L2 */
11135         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11136 }
11137
11138 /*
11139  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11140  */
11141 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11142 {
11143         if (is_guest_mode(vcpu)) {
11144                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11145                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11146         }
11147         free_nested(to_vmx(vcpu));
11148 }
11149
11150 /*
11151  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11152  * 23.7 "VM-entry failures during or after loading guest state" (this also
11153  * lists the acceptable exit-reason and exit-qualification parameters).
11154  * It should only be called before L2 actually succeeded to run, and when
11155  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11156  */
11157 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11158                         struct vmcs12 *vmcs12,
11159                         u32 reason, unsigned long qualification)
11160 {
11161         load_vmcs12_host_state(vcpu, vmcs12);
11162         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11163         vmcs12->exit_qualification = qualification;
11164         nested_vmx_succeed(vcpu);
11165         if (enable_shadow_vmcs)
11166                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11167 }
11168
11169 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11170                                struct x86_instruction_info *info,
11171                                enum x86_intercept_stage stage)
11172 {
11173         return X86EMUL_CONTINUE;
11174 }
11175
11176 #ifdef CONFIG_X86_64
11177 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11178 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11179                                   u64 divisor, u64 *result)
11180 {
11181         u64 low = a << shift, high = a >> (64 - shift);
11182
11183         /* To avoid the overflow on divq */
11184         if (high >= divisor)
11185                 return 1;
11186
11187         /* Low hold the result, high hold rem which is discarded */
11188         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11189             "rm" (divisor), "0" (low), "1" (high));
11190         *result = low;
11191
11192         return 0;
11193 }
11194
11195 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11196 {
11197         struct vcpu_vmx *vmx = to_vmx(vcpu);
11198         u64 tscl = rdtsc();
11199         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11200         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11201
11202         /* Convert to host delta tsc if tsc scaling is enabled */
11203         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11204                         u64_shl_div_u64(delta_tsc,
11205                                 kvm_tsc_scaling_ratio_frac_bits,
11206                                 vcpu->arch.tsc_scaling_ratio,
11207                                 &delta_tsc))
11208                 return -ERANGE;
11209
11210         /*
11211          * If the delta tsc can't fit in the 32 bit after the multi shift,
11212          * we can't use the preemption timer.
11213          * It's possible that it fits on later vmentries, but checking
11214          * on every vmentry is costly so we just use an hrtimer.
11215          */
11216         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11217                 return -ERANGE;
11218
11219         vmx->hv_deadline_tsc = tscl + delta_tsc;
11220         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11221                         PIN_BASED_VMX_PREEMPTION_TIMER);
11222         return 0;
11223 }
11224
11225 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11226 {
11227         struct vcpu_vmx *vmx = to_vmx(vcpu);
11228         vmx->hv_deadline_tsc = -1;
11229         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11230                         PIN_BASED_VMX_PREEMPTION_TIMER);
11231 }
11232 #endif
11233
11234 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11235 {
11236         if (ple_gap)
11237                 shrink_ple_window(vcpu);
11238 }
11239
11240 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11241                                      struct kvm_memory_slot *slot)
11242 {
11243         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11244         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11245 }
11246
11247 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11248                                        struct kvm_memory_slot *slot)
11249 {
11250         kvm_mmu_slot_set_dirty(kvm, slot);
11251 }
11252
11253 static void vmx_flush_log_dirty(struct kvm *kvm)
11254 {
11255         kvm_flush_pml_buffers(kvm);
11256 }
11257
11258 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11259                                            struct kvm_memory_slot *memslot,
11260                                            gfn_t offset, unsigned long mask)
11261 {
11262         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11263 }
11264
11265 /*
11266  * This routine does the following things for vCPU which is going
11267  * to be blocked if VT-d PI is enabled.
11268  * - Store the vCPU to the wakeup list, so when interrupts happen
11269  *   we can find the right vCPU to wake up.
11270  * - Change the Posted-interrupt descriptor as below:
11271  *      'NDST' <-- vcpu->pre_pcpu
11272  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11273  * - If 'ON' is set during this process, which means at least one
11274  *   interrupt is posted for this vCPU, we cannot block it, in
11275  *   this case, return 1, otherwise, return 0.
11276  *
11277  */
11278 static int pi_pre_block(struct kvm_vcpu *vcpu)
11279 {
11280         unsigned long flags;
11281         unsigned int dest;
11282         struct pi_desc old, new;
11283         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11284
11285         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11286                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11287                 !kvm_vcpu_apicv_active(vcpu))
11288                 return 0;
11289
11290         vcpu->pre_pcpu = vcpu->cpu;
11291         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11292                           vcpu->pre_pcpu), flags);
11293         list_add_tail(&vcpu->blocked_vcpu_list,
11294                       &per_cpu(blocked_vcpu_on_cpu,
11295                       vcpu->pre_pcpu));
11296         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11297                                vcpu->pre_pcpu), flags);
11298
11299         do {
11300                 old.control = new.control = pi_desc->control;
11301
11302                 /*
11303                  * We should not block the vCPU if
11304                  * an interrupt is posted for it.
11305                  */
11306                 if (pi_test_on(pi_desc) == 1) {
11307                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11308                                           vcpu->pre_pcpu), flags);
11309                         list_del(&vcpu->blocked_vcpu_list);
11310                         spin_unlock_irqrestore(
11311                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11312                                         vcpu->pre_pcpu), flags);
11313                         vcpu->pre_pcpu = -1;
11314
11315                         return 1;
11316                 }
11317
11318                 WARN((pi_desc->sn == 1),
11319                      "Warning: SN field of posted-interrupts "
11320                      "is set before blocking\n");
11321
11322                 /*
11323                  * Since vCPU can be preempted during this process,
11324                  * vcpu->cpu could be different with pre_pcpu, we
11325                  * need to set pre_pcpu as the destination of wakeup
11326                  * notification event, then we can find the right vCPU
11327                  * to wakeup in wakeup handler if interrupts happen
11328                  * when the vCPU is in blocked state.
11329                  */
11330                 dest = cpu_physical_id(vcpu->pre_pcpu);
11331
11332                 if (x2apic_enabled())
11333                         new.ndst = dest;
11334                 else
11335                         new.ndst = (dest << 8) & 0xFF00;
11336
11337                 /* set 'NV' to 'wakeup vector' */
11338                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11339         } while (cmpxchg(&pi_desc->control, old.control,
11340                         new.control) != old.control);
11341
11342         return 0;
11343 }
11344
11345 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11346 {
11347         if (pi_pre_block(vcpu))
11348                 return 1;
11349
11350         if (kvm_lapic_hv_timer_in_use(vcpu))
11351                 kvm_lapic_switch_to_sw_timer(vcpu);
11352
11353         return 0;
11354 }
11355
11356 static void pi_post_block(struct kvm_vcpu *vcpu)
11357 {
11358         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11359         struct pi_desc old, new;
11360         unsigned int dest;
11361         unsigned long flags;
11362
11363         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11364                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11365                 !kvm_vcpu_apicv_active(vcpu))
11366                 return;
11367
11368         do {
11369                 old.control = new.control = pi_desc->control;
11370
11371                 dest = cpu_physical_id(vcpu->cpu);
11372
11373                 if (x2apic_enabled())
11374                         new.ndst = dest;
11375                 else
11376                         new.ndst = (dest << 8) & 0xFF00;
11377
11378                 /* Allow posting non-urgent interrupts */
11379                 new.sn = 0;
11380
11381                 /* set 'NV' to 'notification vector' */
11382                 new.nv = POSTED_INTR_VECTOR;
11383         } while (cmpxchg(&pi_desc->control, old.control,
11384                         new.control) != old.control);
11385
11386         if(vcpu->pre_pcpu != -1) {
11387                 spin_lock_irqsave(
11388                         &per_cpu(blocked_vcpu_on_cpu_lock,
11389                         vcpu->pre_pcpu), flags);
11390                 list_del(&vcpu->blocked_vcpu_list);
11391                 spin_unlock_irqrestore(
11392                         &per_cpu(blocked_vcpu_on_cpu_lock,
11393                         vcpu->pre_pcpu), flags);
11394                 vcpu->pre_pcpu = -1;
11395         }
11396 }
11397
11398 static void vmx_post_block(struct kvm_vcpu *vcpu)
11399 {
11400         if (kvm_x86_ops->set_hv_timer)
11401                 kvm_lapic_switch_to_hv_timer(vcpu);
11402
11403         pi_post_block(vcpu);
11404 }
11405
11406 /*
11407  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11408  *
11409  * @kvm: kvm
11410  * @host_irq: host irq of the interrupt
11411  * @guest_irq: gsi of the interrupt
11412  * @set: set or unset PI
11413  * returns 0 on success, < 0 on failure
11414  */
11415 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11416                               uint32_t guest_irq, bool set)
11417 {
11418         struct kvm_kernel_irq_routing_entry *e;
11419         struct kvm_irq_routing_table *irq_rt;
11420         struct kvm_lapic_irq irq;
11421         struct kvm_vcpu *vcpu;
11422         struct vcpu_data vcpu_info;
11423         int idx, ret = -EINVAL;
11424
11425         if (!kvm_arch_has_assigned_device(kvm) ||
11426                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11427                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11428                 return 0;
11429
11430         idx = srcu_read_lock(&kvm->irq_srcu);
11431         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11432         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11433
11434         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11435                 if (e->type != KVM_IRQ_ROUTING_MSI)
11436                         continue;
11437                 /*
11438                  * VT-d PI cannot support posting multicast/broadcast
11439                  * interrupts to a vCPU, we still use interrupt remapping
11440                  * for these kind of interrupts.
11441                  *
11442                  * For lowest-priority interrupts, we only support
11443                  * those with single CPU as the destination, e.g. user
11444                  * configures the interrupts via /proc/irq or uses
11445                  * irqbalance to make the interrupts single-CPU.
11446                  *
11447                  * We will support full lowest-priority interrupt later.
11448                  */
11449
11450                 kvm_set_msi_irq(kvm, e, &irq);
11451                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11452                         /*
11453                          * Make sure the IRTE is in remapped mode if
11454                          * we don't handle it in posted mode.
11455                          */
11456                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11457                         if (ret < 0) {
11458                                 printk(KERN_INFO
11459                                    "failed to back to remapped mode, irq: %u\n",
11460                                    host_irq);
11461                                 goto out;
11462                         }
11463
11464                         continue;
11465                 }
11466
11467                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11468                 vcpu_info.vector = irq.vector;
11469
11470                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11471                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11472
11473                 if (set)
11474                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11475                 else {
11476                         /* suppress notification event before unposting */
11477                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11478                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11479                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11480                 }
11481
11482                 if (ret < 0) {
11483                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11484                                         __func__);
11485                         goto out;
11486                 }
11487         }
11488
11489         ret = 0;
11490 out:
11491         srcu_read_unlock(&kvm->irq_srcu, idx);
11492         return ret;
11493 }
11494
11495 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11496 {
11497         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11498                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11499                         FEATURE_CONTROL_LMCE;
11500         else
11501                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11502                         ~FEATURE_CONTROL_LMCE;
11503 }
11504
11505 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11506         .cpu_has_kvm_support = cpu_has_kvm_support,
11507         .disabled_by_bios = vmx_disabled_by_bios,
11508         .hardware_setup = hardware_setup,
11509         .hardware_unsetup = hardware_unsetup,
11510         .check_processor_compatibility = vmx_check_processor_compat,
11511         .hardware_enable = hardware_enable,
11512         .hardware_disable = hardware_disable,
11513         .cpu_has_accelerated_tpr = report_flexpriority,
11514         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11515
11516         .vcpu_create = vmx_create_vcpu,
11517         .vcpu_free = vmx_free_vcpu,
11518         .vcpu_reset = vmx_vcpu_reset,
11519
11520         .prepare_guest_switch = vmx_save_host_state,
11521         .vcpu_load = vmx_vcpu_load,
11522         .vcpu_put = vmx_vcpu_put,
11523
11524         .update_bp_intercept = update_exception_bitmap,
11525         .get_msr = vmx_get_msr,
11526         .set_msr = vmx_set_msr,
11527         .get_segment_base = vmx_get_segment_base,
11528         .get_segment = vmx_get_segment,
11529         .set_segment = vmx_set_segment,
11530         .get_cpl = vmx_get_cpl,
11531         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11532         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11533         .decache_cr3 = vmx_decache_cr3,
11534         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11535         .set_cr0 = vmx_set_cr0,
11536         .set_cr3 = vmx_set_cr3,
11537         .set_cr4 = vmx_set_cr4,
11538         .set_efer = vmx_set_efer,
11539         .get_idt = vmx_get_idt,
11540         .set_idt = vmx_set_idt,
11541         .get_gdt = vmx_get_gdt,
11542         .set_gdt = vmx_set_gdt,
11543         .get_dr6 = vmx_get_dr6,
11544         .set_dr6 = vmx_set_dr6,
11545         .set_dr7 = vmx_set_dr7,
11546         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11547         .cache_reg = vmx_cache_reg,
11548         .get_rflags = vmx_get_rflags,
11549         .set_rflags = vmx_set_rflags,
11550
11551         .get_pkru = vmx_get_pkru,
11552
11553         .tlb_flush = vmx_flush_tlb,
11554
11555         .run = vmx_vcpu_run,
11556         .handle_exit = vmx_handle_exit,
11557         .skip_emulated_instruction = skip_emulated_instruction,
11558         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11559         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11560         .patch_hypercall = vmx_patch_hypercall,
11561         .set_irq = vmx_inject_irq,
11562         .set_nmi = vmx_inject_nmi,
11563         .queue_exception = vmx_queue_exception,
11564         .cancel_injection = vmx_cancel_injection,
11565         .interrupt_allowed = vmx_interrupt_allowed,
11566         .nmi_allowed = vmx_nmi_allowed,
11567         .get_nmi_mask = vmx_get_nmi_mask,
11568         .set_nmi_mask = vmx_set_nmi_mask,
11569         .enable_nmi_window = enable_nmi_window,
11570         .enable_irq_window = enable_irq_window,
11571         .update_cr8_intercept = update_cr8_intercept,
11572         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11573         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11574         .get_enable_apicv = vmx_get_enable_apicv,
11575         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11576         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11577         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11578         .hwapic_irr_update = vmx_hwapic_irr_update,
11579         .hwapic_isr_update = vmx_hwapic_isr_update,
11580         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11581         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11582
11583         .set_tss_addr = vmx_set_tss_addr,
11584         .get_tdp_level = get_ept_level,
11585         .get_mt_mask = vmx_get_mt_mask,
11586
11587         .get_exit_info = vmx_get_exit_info,
11588
11589         .get_lpage_level = vmx_get_lpage_level,
11590
11591         .cpuid_update = vmx_cpuid_update,
11592
11593         .rdtscp_supported = vmx_rdtscp_supported,
11594         .invpcid_supported = vmx_invpcid_supported,
11595
11596         .set_supported_cpuid = vmx_set_supported_cpuid,
11597
11598         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11599
11600         .write_tsc_offset = vmx_write_tsc_offset,
11601
11602         .set_tdp_cr3 = vmx_set_cr3,
11603
11604         .check_intercept = vmx_check_intercept,
11605         .handle_external_intr = vmx_handle_external_intr,
11606         .mpx_supported = vmx_mpx_supported,
11607         .xsaves_supported = vmx_xsaves_supported,
11608
11609         .check_nested_events = vmx_check_nested_events,
11610
11611         .sched_in = vmx_sched_in,
11612
11613         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11614         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11615         .flush_log_dirty = vmx_flush_log_dirty,
11616         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11617
11618         .pre_block = vmx_pre_block,
11619         .post_block = vmx_post_block,
11620
11621         .pmu_ops = &intel_pmu_ops,
11622
11623         .update_pi_irte = vmx_update_pi_irte,
11624
11625 #ifdef CONFIG_X86_64
11626         .set_hv_timer = vmx_set_hv_timer,
11627         .cancel_hv_timer = vmx_cancel_hv_timer,
11628 #endif
11629
11630         .setup_mce = vmx_setup_mce,
11631 };
11632
11633 static int __init vmx_init(void)
11634 {
11635         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11636                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11637         if (r)
11638                 return r;
11639
11640 #ifdef CONFIG_KEXEC_CORE
11641         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11642                            crash_vmclear_local_loaded_vmcss);
11643 #endif
11644
11645         return 0;
11646 }
11647
11648 static void __exit vmx_exit(void)
11649 {
11650 #ifdef CONFIG_KEXEC_CORE
11651         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11652         synchronize_rcu();
11653 #endif
11654
11655         kvm_exit();
11656 }
11657
11658 module_init(vmx_init)
11659 module_exit(vmx_exit)