arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affilates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31
  32 #include <asm/tlbflush.h>
  33 #include <asm/desc.h>
  34
  35 #include <asm/virtext.h>
  36 #include "trace.h"
  37
  38 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  39
  40 MODULE_AUTHOR("Qumranet");
  41 MODULE_LICENSE("GPL");
  42
  43 #define IOPM_ALLOC_ORDER 2
  44 #define MSRPM_ALLOC_ORDER 1
  45
  46 #define SEG_TYPE_LDT 2
  47 #define SEG_TYPE_BUSY_TSS16 3
  48
  49 #define SVM_FEATURE_NPT            (1 <<  0)
  50 #define SVM_FEATURE_LBRV           (1 <<  1)
  51 #define SVM_FEATURE_SVML           (1 <<  2)
  52 #define SVM_FEATURE_NRIP           (1 <<  3)
  53 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  54
  55 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  56 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  57 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  58
  59 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  60
  61 static bool erratum_383_found __read_mostly;
  62
  63 static const u32 host_save_user_msrs[] = {
  64 #ifdef CONFIG_X86_64
  65         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  66         MSR_FS_BASE,
  67 #endif
  68         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  69 };
  70
  71 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  72
  73 struct kvm_vcpu;
  74
  75 struct nested_state {
  76         struct vmcb *hsave;
  77         u64 hsave_msr;
  78         u64 vm_cr_msr;
  79         u64 vmcb;
  80
  81         /* These are the merged vectors */
  82         u32 *msrpm;
  83
  84         /* gpa pointers to the real vectors */
  85         u64 vmcb_msrpm;
  86         u64 vmcb_iopm;
  87
  88         /* A VMEXIT is required but not yet emulated */
  89         bool exit_required;
  90
  91         /* cache for intercepts of the guest */
  92         u16 intercept_cr_read;
  93         u16 intercept_cr_write;
  94         u16 intercept_dr_read;
  95         u16 intercept_dr_write;
  96         u32 intercept_exceptions;
  97         u64 intercept;
  98
  99 };
 100
 101 #define MSRPM_OFFSETS   16
 102 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 103
 104 struct vcpu_svm {
 105         struct kvm_vcpu vcpu;
 106         struct vmcb *vmcb;
 107         unsigned long vmcb_pa;
 108         struct svm_cpu_data *svm_data;
 109         uint64_t asid_generation;
 110         uint64_t sysenter_esp;
 111         uint64_t sysenter_eip;
 112
 113         u64 next_rip;
 114
 115         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 116         u64 host_gs_base;
 117
 118         u32 *msrpm;
 119
 120         struct nested_state nested;
 121
 122         bool nmi_singlestep;
 123
 124         unsigned int3_injected;
 125         unsigned long int3_rip;
 126 };
 127
 128 #define MSR_INVALID                     0xffffffffU
 129
 130 static struct svm_direct_access_msrs {
 131         u32 index;   /* Index of the MSR */
 132         bool always; /* True if intercept is always on */
 133 } direct_access_msrs[] = {
 134         { .index = MSR_K6_STAR,                         .always = true  },
 135         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 136 #ifdef CONFIG_X86_64
 137         { .index = MSR_GS_BASE,                         .always = true  },
 138         { .index = MSR_FS_BASE,                         .always = true  },
 139         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 140         { .index = MSR_LSTAR,                           .always = true  },
 141         { .index = MSR_CSTAR,                           .always = true  },
 142         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 143 #endif
 144         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 145         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 146         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 147         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 148         { .index = MSR_INVALID,                         .always = false },
 149 };
 150
 151 /* enable NPT for AMD64 and X86 with PAE */
 152 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 153 static bool npt_enabled = true;
 154 #else
 155 static bool npt_enabled;
 156 #endif
 157 static int npt = 1;
 158
 159 module_param(npt, int, S_IRUGO);
 160
 161 static int nested = 1;
 162 module_param(nested, int, S_IRUGO);
 163
 164 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 165 static void svm_complete_interrupts(struct vcpu_svm *svm);
 166
 167 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 168 static int nested_svm_intercept(struct vcpu_svm *svm);
 169 static int nested_svm_vmexit(struct vcpu_svm *svm);
 170 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 171                                       bool has_error_code, u32 error_code);
 172
 173 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 174 {
 175         return container_of(vcpu, struct vcpu_svm, vcpu);
 176 }
 177
 178 static inline bool is_nested(struct vcpu_svm *svm)
 179 {
 180         return svm->nested.vmcb;
 181 }
 182
 183 static inline void enable_gif(struct vcpu_svm *svm)
 184 {
 185         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 186 }
 187
 188 static inline void disable_gif(struct vcpu_svm *svm)
 189 {
 190         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 191 }
 192
 193 static inline bool gif_set(struct vcpu_svm *svm)
 194 {
 195         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 196 }
 197
 198 static unsigned long iopm_base;
 199
 200 struct kvm_ldttss_desc {
 201         u16 limit0;
 202         u16 base0;
 203         unsigned base1:8, type:5, dpl:2, p:1;
 204         unsigned limit1:4, zero0:3, g:1, base2:8;
 205         u32 base3;
 206         u32 zero1;
 207 } __attribute__((packed));
 208
 209 struct svm_cpu_data {
 210         int cpu;
 211
 212         u64 asid_generation;
 213         u32 max_asid;
 214         u32 next_asid;
 215         struct kvm_ldttss_desc *tss_desc;
 216
 217         struct page *save_area;
 218 };
 219
 220 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 221 static uint32_t svm_features;
 222
 223 struct svm_init_data {
 224         int cpu;
 225         int r;
 226 };
 227
 228 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 229
 230 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 231 #define MSRS_RANGE_SIZE 2048
 232 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 233
 234 static u32 svm_msrpm_offset(u32 msr)
 235 {
 236         u32 offset;
 237         int i;
 238
 239         for (i = 0; i < NUM_MSR_MAPS; i++) {
 240                 if (msr < msrpm_ranges[i] ||
 241                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 242                         continue;
 243
 244                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 245                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 246
 247                 /* Now we have the u8 offset - but need the u32 offset */
 248                 return offset / 4;
 249         }
 250
 251         /* MSR not in any range */
 252         return MSR_INVALID;
 253 }
 254
 255 #define MAX_INST_SIZE 15
 256
 257 static inline u32 svm_has(u32 feat)
 258 {
 259         return svm_features & feat;
 260 }
 261
 262 static inline void clgi(void)
 263 {
 264         asm volatile (__ex(SVM_CLGI));
 265 }
 266
 267 static inline void stgi(void)
 268 {
 269         asm volatile (__ex(SVM_STGI));
 270 }
 271
 272 static inline void invlpga(unsigned long addr, u32 asid)
 273 {
 274         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 275 }
 276
 277 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 278 {
 279         to_svm(vcpu)->asid_generation--;
 280 }
 281
 282 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 283 {
 284         force_new_asid(vcpu);
 285 }
 286
 287 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 288 {
 289         vcpu->arch.efer = efer;
 290         if (!npt_enabled && !(efer & EFER_LMA))
 291                 efer &= ~EFER_LME;
 292
 293         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 294 }
 295
 296 static int is_external_interrupt(u32 info)
 297 {
 298         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 299         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 300 }
 301
 302 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 303 {
 304         struct vcpu_svm *svm = to_svm(vcpu);
 305         u32 ret = 0;
 306
 307         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 308                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 309         return ret & mask;
 310 }
 311
 312 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 313 {
 314         struct vcpu_svm *svm = to_svm(vcpu);
 315
 316         if (mask == 0)
 317                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 318         else
 319                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 320
 321 }
 322
 323 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 324 {
 325         struct vcpu_svm *svm = to_svm(vcpu);
 326
 327         if (svm->vmcb->control.next_rip != 0)
 328                 svm->next_rip = svm->vmcb->control.next_rip;
 329
 330         if (!svm->next_rip) {
 331                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 332                                 EMULATE_DONE)
 333                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 334                 return;
 335         }
 336         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 337                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 338                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 339
 340         kvm_rip_write(vcpu, svm->next_rip);
 341         svm_set_interrupt_shadow(vcpu, 0);
 342 }
 343
 344 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 345                                 bool has_error_code, u32 error_code,
 346                                 bool reinject)
 347 {
 348         struct vcpu_svm *svm = to_svm(vcpu);
 349
 350         /*
 351          * If we are within a nested VM we'd better #VMEXIT and let the guest
 352          * handle the exception
 353          */
 354         if (!reinject &&
 355             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 356                 return;
 357
 358         if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
 359                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 360
 361                 /*
 362                  * For guest debugging where we have to reinject #BP if some
 363                  * INT3 is guest-owned:
 364                  * Emulate nRIP by moving RIP forward. Will fail if injection
 365                  * raises a fault that is not intercepted. Still better than
 366                  * failing in all cases.
 367                  */
 368                 skip_emulated_instruction(&svm->vcpu);
 369                 rip = kvm_rip_read(&svm->vcpu);
 370                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 371                 svm->int3_injected = rip - old_rip;
 372         }
 373
 374         svm->vmcb->control.event_inj = nr
 375                 | SVM_EVTINJ_VALID
 376                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 377                 | SVM_EVTINJ_TYPE_EXEPT;
 378         svm->vmcb->control.event_inj_err = error_code;
 379 }
 380
 381 static void svm_init_erratum_383(void)
 382 {
 383         u32 low, high;
 384         int err;
 385         u64 val;
 386
 387         /* Only Fam10h is affected */
 388         if (boot_cpu_data.x86 != 0x10)
 389                 return;
 390
 391         /* Use _safe variants to not break nested virtualization */
 392         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 393         if (err)
 394                 return;
 395
 396         val |= (1ULL << 47);
 397
 398         low  = lower_32_bits(val);
 399         high = upper_32_bits(val);
 400
 401         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 402
 403         erratum_383_found = true;
 404 }
 405
 406 static int has_svm(void)
 407 {
 408         const char *msg;
 409
 410         if (!cpu_has_svm(&msg)) {
 411                 printk(KERN_INFO "has_svm: %s\n", msg);
 412                 return 0;
 413         }
 414
 415         return 1;
 416 }
 417
 418 static void svm_hardware_disable(void *garbage)
 419 {
 420         cpu_svm_disable();
 421 }
 422
 423 static int svm_hardware_enable(void *garbage)
 424 {
 425
 426         struct svm_cpu_data *sd;
 427         uint64_t efer;
 428         struct desc_ptr gdt_descr;
 429         struct desc_struct *gdt;
 430         int me = raw_smp_processor_id();
 431
 432         rdmsrl(MSR_EFER, efer);
 433         if (efer & EFER_SVME)
 434                 return -EBUSY;
 435
 436         if (!has_svm()) {
 437                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 438                        me);
 439                 return -EINVAL;
 440         }
 441         sd = per_cpu(svm_data, me);
 442
 443         if (!sd) {
 444                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 445                        me);
 446                 return -EINVAL;
 447         }
 448
 449         sd->asid_generation = 1;
 450         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 451         sd->next_asid = sd->max_asid + 1;
 452
 453         native_store_gdt(&gdt_descr);
 454         gdt = (struct desc_struct *)gdt_descr.address;
 455         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 456
 457         wrmsrl(MSR_EFER, efer | EFER_SVME);
 458
 459         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 460
 461         svm_init_erratum_383();
 462
 463         return 0;
 464 }
 465
 466 static void svm_cpu_uninit(int cpu)
 467 {
 468         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 469
 470         if (!sd)
 471                 return;
 472
 473         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 474         __free_page(sd->save_area);
 475         kfree(sd);
 476 }
 477
 478 static int svm_cpu_init(int cpu)
 479 {
 480         struct svm_cpu_data *sd;
 481         int r;
 482
 483         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 484         if (!sd)
 485                 return -ENOMEM;
 486         sd->cpu = cpu;
 487         sd->save_area = alloc_page(GFP_KERNEL);
 488         r = -ENOMEM;
 489         if (!sd->save_area)
 490                 goto err_1;
 491
 492         per_cpu(svm_data, cpu) = sd;
 493
 494         return 0;
 495
 496 err_1:
 497         kfree(sd);
 498         return r;
 499
 500 }
 501
 502 static bool valid_msr_intercept(u32 index)
 503 {
 504         int i;
 505
 506         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 507                 if (direct_access_msrs[i].index == index)
 508                         return true;
 509
 510         return false;
 511 }
 512
 513 static void set_msr_interception(u32 *msrpm, unsigned msr,
 514                                  int read, int write)
 515 {
 516         u8 bit_read, bit_write;
 517         unsigned long tmp;
 518         u32 offset;
 519
 520         /*
 521          * If this warning triggers extend the direct_access_msrs list at the
 522          * beginning of the file
 523          */
 524         WARN_ON(!valid_msr_intercept(msr));
 525
 526         offset    = svm_msrpm_offset(msr);
 527         bit_read  = 2 * (msr & 0x0f);
 528         bit_write = 2 * (msr & 0x0f) + 1;
 529         tmp       = msrpm[offset];
 530
 531         BUG_ON(offset == MSR_INVALID);
 532
 533         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 534         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 535
 536         msrpm[offset] = tmp;
 537 }
 538
 539 static void svm_vcpu_init_msrpm(u32 *msrpm)
 540 {
 541         int i;
 542
 543         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 544
 545         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 546                 if (!direct_access_msrs[i].always)
 547                         continue;
 548
 549                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 550         }
 551 }
 552
 553 static void add_msr_offset(u32 offset)
 554 {
 555         int i;
 556
 557         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 558
 559                 /* Offset already in list? */
 560                 if (msrpm_offsets[i] == offset)
 561                         return;
 562
 563                 /* Slot used by another offset? */
 564                 if (msrpm_offsets[i] != MSR_INVALID)
 565                         continue;
 566
 567                 /* Add offset to list */
 568                 msrpm_offsets[i] = offset;
 569
 570                 return;
 571         }
 572
 573         /*
 574          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 575          * increase MSRPM_OFFSETS in this case.
 576          */
 577         BUG();
 578 }
 579
 580 static void init_msrpm_offsets(void)
 581 {
 582         int i;
 583
 584         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 585
 586         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 587                 u32 offset;
 588
 589                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 590                 BUG_ON(offset == MSR_INVALID);
 591
 592                 add_msr_offset(offset);
 593         }
 594 }
 595
 596 static void svm_enable_lbrv(struct vcpu_svm *svm)
 597 {
 598         u32 *msrpm = svm->msrpm;
 599
 600         svm->vmcb->control.lbr_ctl = 1;
 601         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 602         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 603         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 604         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 605 }
 606
 607 static void svm_disable_lbrv(struct vcpu_svm *svm)
 608 {
 609         u32 *msrpm = svm->msrpm;
 610
 611         svm->vmcb->control.lbr_ctl = 0;
 612         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 613         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 614         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 615         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 616 }
 617
 618 static __init int svm_hardware_setup(void)
 619 {
 620         int cpu;
 621         struct page *iopm_pages;
 622         void *iopm_va;
 623         int r;
 624
 625         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 626
 627         if (!iopm_pages)
 628                 return -ENOMEM;
 629
 630         iopm_va = page_address(iopm_pages);
 631         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 632         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 633
 634         init_msrpm_offsets();
 635
 636         if (boot_cpu_has(X86_FEATURE_NX))
 637                 kvm_enable_efer_bits(EFER_NX);
 638
 639         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 640                 kvm_enable_efer_bits(EFER_FFXSR);
 641
 642         if (nested) {
 643                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 644                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 645         }
 646
 647         for_each_possible_cpu(cpu) {
 648                 r = svm_cpu_init(cpu);
 649                 if (r)
 650                         goto err;
 651         }
 652
 653         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 654
 655         if (!svm_has(SVM_FEATURE_NPT))
 656                 npt_enabled = false;
 657
 658         if (npt_enabled && !npt) {
 659                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 660                 npt_enabled = false;
 661         }
 662
 663         if (npt_enabled) {
 664                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 665                 kvm_enable_tdp();
 666         } else
 667                 kvm_disable_tdp();
 668
 669         return 0;
 670
 671 err:
 672         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 673         iopm_base = 0;
 674         return r;
 675 }
 676
 677 static __exit void svm_hardware_unsetup(void)
 678 {
 679         int cpu;
 680
 681         for_each_possible_cpu(cpu)
 682                 svm_cpu_uninit(cpu);
 683
 684         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 685         iopm_base = 0;
 686 }
 687
 688 static void init_seg(struct vmcb_seg *seg)
 689 {
 690         seg->selector = 0;
 691         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 692                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 693         seg->limit = 0xffff;
 694         seg->base = 0;
 695 }
 696
 697 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 698 {
 699         seg->selector = 0;
 700         seg->attrib = SVM_SELECTOR_P_MASK | type;
 701         seg->limit = 0xffff;
 702         seg->base = 0;
 703 }
 704
 705 static void init_vmcb(struct vcpu_svm *svm)
 706 {
 707         struct vmcb_control_area *control = &svm->vmcb->control;
 708         struct vmcb_save_area *save = &svm->vmcb->save;
 709
 710         svm->vcpu.fpu_active = 1;
 711
 712         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 713                                         INTERCEPT_CR3_MASK |
 714                                         INTERCEPT_CR4_MASK;
 715
 716         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 717                                         INTERCEPT_CR3_MASK |
 718                                         INTERCEPT_CR4_MASK |
 719                                         INTERCEPT_CR8_MASK;
 720
 721         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 722                                         INTERCEPT_DR1_MASK |
 723                                         INTERCEPT_DR2_MASK |
 724                                         INTERCEPT_DR3_MASK |
 725                                         INTERCEPT_DR4_MASK |
 726                                         INTERCEPT_DR5_MASK |
 727                                         INTERCEPT_DR6_MASK |
 728                                         INTERCEPT_DR7_MASK;
 729
 730         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 731                                         INTERCEPT_DR1_MASK |
 732                                         INTERCEPT_DR2_MASK |
 733                                         INTERCEPT_DR3_MASK |
 734                                         INTERCEPT_DR4_MASK |
 735                                         INTERCEPT_DR5_MASK |
 736                                         INTERCEPT_DR6_MASK |
 737                                         INTERCEPT_DR7_MASK;
 738
 739         control->intercept_exceptions = (1 << PF_VECTOR) |
 740                                         (1 << UD_VECTOR) |
 741                                         (1 << MC_VECTOR);
 742
 743
 744         control->intercept =    (1ULL << INTERCEPT_INTR) |
 745                                 (1ULL << INTERCEPT_NMI) |
 746                                 (1ULL << INTERCEPT_SMI) |
 747                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 748                                 (1ULL << INTERCEPT_CPUID) |
 749                                 (1ULL << INTERCEPT_INVD) |
 750                                 (1ULL << INTERCEPT_HLT) |
 751                                 (1ULL << INTERCEPT_INVLPG) |
 752                                 (1ULL << INTERCEPT_INVLPGA) |
 753                                 (1ULL << INTERCEPT_IOIO_PROT) |
 754                                 (1ULL << INTERCEPT_MSR_PROT) |
 755                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 756                                 (1ULL << INTERCEPT_SHUTDOWN) |
 757                                 (1ULL << INTERCEPT_VMRUN) |
 758                                 (1ULL << INTERCEPT_VMMCALL) |
 759                                 (1ULL << INTERCEPT_VMLOAD) |
 760                                 (1ULL << INTERCEPT_VMSAVE) |
 761                                 (1ULL << INTERCEPT_STGI) |
 762                                 (1ULL << INTERCEPT_CLGI) |
 763                                 (1ULL << INTERCEPT_SKINIT) |
 764                                 (1ULL << INTERCEPT_WBINVD) |
 765                                 (1ULL << INTERCEPT_MONITOR) |
 766                                 (1ULL << INTERCEPT_MWAIT);
 767
 768         control->iopm_base_pa = iopm_base;
 769         control->msrpm_base_pa = __pa(svm->msrpm);
 770         control->tsc_offset = 0;
 771         control->int_ctl = V_INTR_MASKING_MASK;
 772
 773         init_seg(&save->es);
 774         init_seg(&save->ss);
 775         init_seg(&save->ds);
 776         init_seg(&save->fs);
 777         init_seg(&save->gs);
 778
 779         save->cs.selector = 0xf000;
 780         /* Executable/Readable Code Segment */
 781         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 782                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 783         save->cs.limit = 0xffff;
 784         /*
 785          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 786          * be consistent with it.
 787          *
 788          * Replace when we have real mode working for vmx.
 789          */
 790         save->cs.base = 0xf0000;
 791
 792         save->gdtr.limit = 0xffff;
 793         save->idtr.limit = 0xffff;
 794
 795         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 796         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 797
 798         save->efer = EFER_SVME;
 799         save->dr6 = 0xffff0ff0;
 800         save->dr7 = 0x400;
 801         save->rflags = 2;
 802         save->rip = 0x0000fff0;
 803         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 804
 805         /*
 806          * This is the guest-visible cr0 value.
 807          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 808          */
 809         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 810         (void)kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 811
 812         save->cr4 = X86_CR4_PAE;
 813         /* rdx = ?? */
 814
 815         if (npt_enabled) {
 816                 /* Setup VMCB for Nested Paging */
 817                 control->nested_ctl = 1;
 818                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 819                                         (1ULL << INTERCEPT_INVLPG));
 820                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 821                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 822                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 823                 save->g_pat = 0x0007040600070406ULL;
 824                 save->cr3 = 0;
 825                 save->cr4 = 0;
 826         }
 827         force_new_asid(&svm->vcpu);
 828
 829         svm->nested.vmcb = 0;
 830         svm->vcpu.arch.hflags = 0;
 831
 832         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 833                 control->pause_filter_count = 3000;
 834                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 835         }
 836
 837         enable_gif(svm);
 838 }
 839
 840 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 841 {
 842         struct vcpu_svm *svm = to_svm(vcpu);
 843
 844         init_vmcb(svm);
 845
 846         if (!kvm_vcpu_is_bsp(vcpu)) {
 847                 kvm_rip_write(vcpu, 0);
 848                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 849                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 850         }
 851         vcpu->arch.regs_avail = ~0;
 852         vcpu->arch.regs_dirty = ~0;
 853
 854         return 0;
 855 }
 856
 857 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 858 {
 859         struct vcpu_svm *svm;
 860         struct page *page;
 861         struct page *msrpm_pages;
 862         struct page *hsave_page;
 863         struct page *nested_msrpm_pages;
 864         int err;
 865
 866         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 867         if (!svm) {
 868                 err = -ENOMEM;
 869                 goto out;
 870         }
 871
 872         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 873         if (err)
 874                 goto free_svm;
 875
 876         err = -ENOMEM;
 877         page = alloc_page(GFP_KERNEL);
 878         if (!page)
 879                 goto uninit;
 880
 881         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 882         if (!msrpm_pages)
 883                 goto free_page1;
 884
 885         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 886         if (!nested_msrpm_pages)
 887                 goto free_page2;
 888
 889         hsave_page = alloc_page(GFP_KERNEL);
 890         if (!hsave_page)
 891                 goto free_page3;
 892
 893         svm->nested.hsave = page_address(hsave_page);
 894
 895         svm->msrpm = page_address(msrpm_pages);
 896         svm_vcpu_init_msrpm(svm->msrpm);
 897
 898         svm->nested.msrpm = page_address(nested_msrpm_pages);
 899         svm_vcpu_init_msrpm(svm->nested.msrpm);
 900
 901         svm->vmcb = page_address(page);
 902         clear_page(svm->vmcb);
 903         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 904         svm->asid_generation = 0;
 905         init_vmcb(svm);
 906
 907         err = fx_init(&svm->vcpu);
 908         if (err)
 909                 goto free_page4;
 910
 911         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 912         if (kvm_vcpu_is_bsp(&svm->vcpu))
 913                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 914
 915         return &svm->vcpu;
 916
 917 free_page4:
 918         __free_page(hsave_page);
 919 free_page3:
 920         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 921 free_page2:
 922         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 923 free_page1:
 924         __free_page(page);
 925 uninit:
 926         kvm_vcpu_uninit(&svm->vcpu);
 927 free_svm:
 928         kmem_cache_free(kvm_vcpu_cache, svm);
 929 out:
 930         return ERR_PTR(err);
 931 }
 932
 933 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 934 {
 935         struct vcpu_svm *svm = to_svm(vcpu);
 936
 937         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 938         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 939         __free_page(virt_to_page(svm->nested.hsave));
 940         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 941         kvm_vcpu_uninit(vcpu);
 942         kmem_cache_free(kvm_vcpu_cache, svm);
 943 }
 944
 945 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 946 {
 947         struct vcpu_svm *svm = to_svm(vcpu);
 948         int i;
 949
 950         if (unlikely(cpu != vcpu->cpu)) {
 951                 u64 delta;
 952
 953                 if (check_tsc_unstable()) {
 954                         /*
 955                          * Make sure that the guest sees a monotonically
 956                          * increasing TSC.
 957                          */
 958                         delta = vcpu->arch.host_tsc - native_read_tsc();
 959                         svm->vmcb->control.tsc_offset += delta;
 960                         if (is_nested(svm))
 961                                 svm->nested.hsave->control.tsc_offset += delta;
 962                 }
 963                 vcpu->cpu = cpu;
 964                 kvm_migrate_timers(vcpu);
 965                 svm->asid_generation = 0;
 966         }
 967
 968         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 969                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 970 }
 971
 972 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 973 {
 974         struct vcpu_svm *svm = to_svm(vcpu);
 975         int i;
 976
 977         ++vcpu->stat.host_state_reload;
 978         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 979                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 980
 981         vcpu->arch.host_tsc = native_read_tsc();
 982 }
 983
 984 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 985 {
 986         return to_svm(vcpu)->vmcb->save.rflags;
 987 }
 988
 989 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 990 {
 991         to_svm(vcpu)->vmcb->save.rflags = rflags;
 992 }
 993
 994 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 995 {
 996         switch (reg) {
 997         case VCPU_EXREG_PDPTR:
 998                 BUG_ON(!npt_enabled);
 999                 load_pdptrs(vcpu, vcpu->arch.cr3);
1000                 break;
1001         default:
1002                 BUG();
1003         }
1004 }
1005
1006 static void svm_set_vintr(struct vcpu_svm *svm)
1007 {
1008         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1009 }
1010
1011 static void svm_clear_vintr(struct vcpu_svm *svm)
1012 {
1013         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1014 }
1015
1016 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1017 {
1018         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1019
1020         switch (seg) {
1021         case VCPU_SREG_CS: return &save->cs;
1022         case VCPU_SREG_DS: return &save->ds;
1023         case VCPU_SREG_ES: return &save->es;
1024         case VCPU_SREG_FS: return &save->fs;
1025         case VCPU_SREG_GS: return &save->gs;
1026         case VCPU_SREG_SS: return &save->ss;
1027         case VCPU_SREG_TR: return &save->tr;
1028         case VCPU_SREG_LDTR: return &save->ldtr;
1029         }
1030         BUG();
1031         return NULL;
1032 }
1033
1034 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1035 {
1036         struct vmcb_seg *s = svm_seg(vcpu, seg);
1037
1038         return s->base;
1039 }
1040
1041 static void svm_get_segment(struct kvm_vcpu *vcpu,
1042                             struct kvm_segment *var, int seg)
1043 {
1044         struct vmcb_seg *s = svm_seg(vcpu, seg);
1045
1046         var->base = s->base;
1047         var->limit = s->limit;
1048         var->selector = s->selector;
1049         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1050         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1051         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1052         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1053         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1054         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1055         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1056         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1057
1058         /*
1059          * AMD's VMCB does not have an explicit unusable field, so emulate it
1060          * for cross vendor migration purposes by "not present"
1061          */
1062         var->unusable = !var->present || (var->type == 0);
1063
1064         switch (seg) {
1065         case VCPU_SREG_CS:
1066                 /*
1067                  * SVM always stores 0 for the 'G' bit in the CS selector in
1068                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1069                  * Intel's VMENTRY has a check on the 'G' bit.
1070                  */
1071                 var->g = s->limit > 0xfffff;
1072                 break;
1073         case VCPU_SREG_TR:
1074                 /*
1075                  * Work around a bug where the busy flag in the tr selector
1076                  * isn't exposed
1077                  */
1078                 var->type |= 0x2;
1079                 break;
1080         case VCPU_SREG_DS:
1081         case VCPU_SREG_ES:
1082         case VCPU_SREG_FS:
1083         case VCPU_SREG_GS:
1084                 /*
1085                  * The accessed bit must always be set in the segment
1086                  * descriptor cache, although it can be cleared in the
1087                  * descriptor, the cached bit always remains at 1. Since
1088                  * Intel has a check on this, set it here to support
1089                  * cross-vendor migration.
1090                  */
1091                 if (!var->unusable)
1092                         var->type |= 0x1;
1093                 break;
1094         case VCPU_SREG_SS:
1095                 /*
1096                  * On AMD CPUs sometimes the DB bit in the segment
1097                  * descriptor is left as 1, although the whole segment has
1098                  * been made unusable. Clear it here to pass an Intel VMX
1099                  * entry check when cross vendor migrating.
1100                  */
1101                 if (var->unusable)
1102                         var->db = 0;
1103                 break;
1104         }
1105 }
1106
1107 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1108 {
1109         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1110
1111         return save->cpl;
1112 }
1113
1114 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1115 {
1116         struct vcpu_svm *svm = to_svm(vcpu);
1117
1118         dt->size = svm->vmcb->save.idtr.limit;
1119         dt->address = svm->vmcb->save.idtr.base;
1120 }
1121
1122 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1123 {
1124         struct vcpu_svm *svm = to_svm(vcpu);
1125
1126         svm->vmcb->save.idtr.limit = dt->size;
1127         svm->vmcb->save.idtr.base = dt->address ;
1128 }
1129
1130 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1131 {
1132         struct vcpu_svm *svm = to_svm(vcpu);
1133
1134         dt->size = svm->vmcb->save.gdtr.limit;
1135         dt->address = svm->vmcb->save.gdtr.base;
1136 }
1137
1138 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1139 {
1140         struct vcpu_svm *svm = to_svm(vcpu);
1141
1142         svm->vmcb->save.gdtr.limit = dt->size;
1143         svm->vmcb->save.gdtr.base = dt->address ;
1144 }
1145
1146 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1147 {
1148 }
1149
1150 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1151 {
1152 }
1153
1154 static void update_cr0_intercept(struct vcpu_svm *svm)
1155 {
1156         struct vmcb *vmcb = svm->vmcb;
1157         ulong gcr0 = svm->vcpu.arch.cr0;
1158         u64 *hcr0 = &svm->vmcb->save.cr0;
1159
1160         if (!svm->vcpu.fpu_active)
1161                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1162         else
1163                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1164                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1165
1166
1167         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1168                 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1169                 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1170                 if (is_nested(svm)) {
1171                         struct vmcb *hsave = svm->nested.hsave;
1172
1173                         hsave->control.intercept_cr_read  &= ~INTERCEPT_CR0_MASK;
1174                         hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1175                         vmcb->control.intercept_cr_read  |= svm->nested.intercept_cr_read;
1176                         vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1177                 }
1178         } else {
1179                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1180                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1181                 if (is_nested(svm)) {
1182                         struct vmcb *hsave = svm->nested.hsave;
1183
1184                         hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1185                         hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1186                 }
1187         }
1188 }
1189
1190 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1191 {
1192         struct vcpu_svm *svm = to_svm(vcpu);
1193
1194         if (is_nested(svm)) {
1195                 /*
1196                  * We are here because we run in nested mode, the host kvm
1197                  * intercepts cr0 writes but the l1 hypervisor does not.
1198                  * But the L1 hypervisor may intercept selective cr0 writes.
1199                  * This needs to be checked here.
1200                  */
1201                 unsigned long old, new;
1202
1203                 /* Remove bits that would trigger a real cr0 write intercept */
1204                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1205                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1206
1207                 if (old == new) {
1208                         /* cr0 write with ts and mp unchanged */
1209                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1210                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1211                                 return;
1212                 }
1213         }
1214
1215 #ifdef CONFIG_X86_64
1216         if (vcpu->arch.efer & EFER_LME) {
1217                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1218                         vcpu->arch.efer |= EFER_LMA;
1219                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1220                 }
1221
1222                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1223                         vcpu->arch.efer &= ~EFER_LMA;
1224                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1225                 }
1226         }
1227 #endif
1228         vcpu->arch.cr0 = cr0;
1229
1230         if (!npt_enabled)
1231                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1232
1233         if (!vcpu->fpu_active)
1234                 cr0 |= X86_CR0_TS;
1235         /*
1236          * re-enable caching here because the QEMU bios
1237          * does not do it - this results in some delay at
1238          * reboot
1239          */
1240         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1241         svm->vmcb->save.cr0 = cr0;
1242         update_cr0_intercept(svm);
1243 }
1244
1245 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1246 {
1247         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1248         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1249
1250         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1251                 force_new_asid(vcpu);
1252
1253         vcpu->arch.cr4 = cr4;
1254         if (!npt_enabled)
1255                 cr4 |= X86_CR4_PAE;
1256         cr4 |= host_cr4_mce;
1257         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1258 }
1259
1260 static void svm_set_segment(struct kvm_vcpu *vcpu,
1261                             struct kvm_segment *var, int seg)
1262 {
1263         struct vcpu_svm *svm = to_svm(vcpu);
1264         struct vmcb_seg *s = svm_seg(vcpu, seg);
1265
1266         s->base = var->base;
1267         s->limit = var->limit;
1268         s->selector = var->selector;
1269         if (var->unusable)
1270                 s->attrib = 0;
1271         else {
1272                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1273                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1274                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1275                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1276                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1277                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1278                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1279                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1280         }
1281         if (seg == VCPU_SREG_CS)
1282                 svm->vmcb->save.cpl
1283                         = (svm->vmcb->save.cs.attrib
1284                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1285
1286 }
1287
1288 static void update_db_intercept(struct kvm_vcpu *vcpu)
1289 {
1290         struct vcpu_svm *svm = to_svm(vcpu);
1291
1292         svm->vmcb->control.intercept_exceptions &=
1293                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1294
1295         if (svm->nmi_singlestep)
1296                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1297
1298         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1299                 if (vcpu->guest_debug &
1300                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1301                         svm->vmcb->control.intercept_exceptions |=
1302                                 1 << DB_VECTOR;
1303                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1304                         svm->vmcb->control.intercept_exceptions |=
1305                                 1 << BP_VECTOR;
1306         } else
1307                 vcpu->guest_debug = 0;
1308 }
1309
1310 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1311 {
1312         struct vcpu_svm *svm = to_svm(vcpu);
1313
1314         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1315                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1316         else
1317                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1318
1319         update_db_intercept(vcpu);
1320 }
1321
1322 static void load_host_msrs(struct kvm_vcpu *vcpu)
1323 {
1324 #ifdef CONFIG_X86_64
1325         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1326 #endif
1327 }
1328
1329 static void save_host_msrs(struct kvm_vcpu *vcpu)
1330 {
1331 #ifdef CONFIG_X86_64
1332         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1333 #endif
1334 }
1335
1336 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1337 {
1338         if (sd->next_asid > sd->max_asid) {
1339                 ++sd->asid_generation;
1340                 sd->next_asid = 1;
1341                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1342         }
1343
1344         svm->asid_generation = sd->asid_generation;
1345         svm->vmcb->control.asid = sd->next_asid++;
1346 }
1347
1348 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1349 {
1350         struct vcpu_svm *svm = to_svm(vcpu);
1351
1352         svm->vmcb->save.dr7 = value;
1353 }
1354
1355 static int pf_interception(struct vcpu_svm *svm)
1356 {
1357         u64 fault_address;
1358         u32 error_code;
1359
1360         fault_address  = svm->vmcb->control.exit_info_2;
1361         error_code = svm->vmcb->control.exit_info_1;
1362
1363         trace_kvm_page_fault(fault_address, error_code);
1364         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1365                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1366         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1367 }
1368
1369 static int db_interception(struct vcpu_svm *svm)
1370 {
1371         struct kvm_run *kvm_run = svm->vcpu.run;
1372
1373         if (!(svm->vcpu.guest_debug &
1374               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1375                 !svm->nmi_singlestep) {
1376                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1377                 return 1;
1378         }
1379
1380         if (svm->nmi_singlestep) {
1381                 svm->nmi_singlestep = false;
1382                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1383                         svm->vmcb->save.rflags &=
1384                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1385                 update_db_intercept(&svm->vcpu);
1386         }
1387
1388         if (svm->vcpu.guest_debug &
1389             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1390                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1391                 kvm_run->debug.arch.pc =
1392                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1393                 kvm_run->debug.arch.exception = DB_VECTOR;
1394                 return 0;
1395         }
1396
1397         return 1;
1398 }
1399
1400 static int bp_interception(struct vcpu_svm *svm)
1401 {
1402         struct kvm_run *kvm_run = svm->vcpu.run;
1403
1404         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1405         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1406         kvm_run->debug.arch.exception = BP_VECTOR;
1407         return 0;
1408 }
1409
1410 static int ud_interception(struct vcpu_svm *svm)
1411 {
1412         int er;
1413
1414         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1415         if (er != EMULATE_DONE)
1416                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1417         return 1;
1418 }
1419
1420 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1421 {
1422         struct vcpu_svm *svm = to_svm(vcpu);
1423         u32 excp;
1424
1425         if (is_nested(svm)) {
1426                 u32 h_excp, n_excp;
1427
1428                 h_excp  = svm->nested.hsave->control.intercept_exceptions;
1429                 n_excp  = svm->nested.intercept_exceptions;
1430                 h_excp &= ~(1 << NM_VECTOR);
1431                 excp    = h_excp | n_excp;
1432         } else {
1433                 excp  = svm->vmcb->control.intercept_exceptions;
1434                 excp &= ~(1 << NM_VECTOR);
1435         }
1436
1437         svm->vmcb->control.intercept_exceptions = excp;
1438
1439         svm->vcpu.fpu_active = 1;
1440         update_cr0_intercept(svm);
1441 }
1442
1443 static int nm_interception(struct vcpu_svm *svm)
1444 {
1445         svm_fpu_activate(&svm->vcpu);
1446         return 1;
1447 }
1448
1449 static bool is_erratum_383(void)
1450 {
1451         int err, i;
1452         u64 value;
1453
1454         if (!erratum_383_found)
1455                 return false;
1456
1457         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1458         if (err)
1459                 return false;
1460
1461         /* Bit 62 may or may not be set for this mce */
1462         value &= ~(1ULL << 62);
1463
1464         if (value != 0xb600000000010015ULL)
1465                 return false;
1466
1467         /* Clear MCi_STATUS registers */
1468         for (i = 0; i < 6; ++i)
1469                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1470
1471         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1472         if (!err) {
1473                 u32 low, high;
1474
1475                 value &= ~(1ULL << 2);
1476                 low    = lower_32_bits(value);
1477                 high   = upper_32_bits(value);
1478
1479                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1480         }
1481
1482         /* Flush tlb to evict multi-match entries */
1483         __flush_tlb_all();
1484
1485         return true;
1486 }
1487
1488 static void svm_handle_mce(struct vcpu_svm *svm)
1489 {
1490         if (is_erratum_383()) {
1491                 /*
1492                  * Erratum 383 triggered. Guest state is corrupt so kill the
1493                  * guest.
1494                  */
1495                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1496
1497                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1498
1499                 return;
1500         }
1501
1502         /*
1503          * On an #MC intercept the MCE handler is not called automatically in
1504          * the host. So do it by hand here.
1505          */
1506         asm volatile (
1507                 "int $0x12\n");
1508         /* not sure if we ever come back to this point */
1509
1510         return;
1511 }
1512
1513 static int mc_interception(struct vcpu_svm *svm)
1514 {
1515         return 1;
1516 }
1517
1518 static int shutdown_interception(struct vcpu_svm *svm)
1519 {
1520         struct kvm_run *kvm_run = svm->vcpu.run;
1521
1522         /*
1523          * VMCB is undefined after a SHUTDOWN intercept
1524          * so reinitialize it.
1525          */
1526         clear_page(svm->vmcb);
1527         init_vmcb(svm);
1528
1529         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1530         return 0;
1531 }
1532
1533 static int io_interception(struct vcpu_svm *svm)
1534 {
1535         struct kvm_vcpu *vcpu = &svm->vcpu;
1536         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1537         int size, in, string;
1538         unsigned port;
1539
1540         ++svm->vcpu.stat.io_exits;
1541         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1542         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1543         if (string || in)
1544                 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1545
1546         port = io_info >> 16;
1547         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1548         svm->next_rip = svm->vmcb->control.exit_info_2;
1549         skip_emulated_instruction(&svm->vcpu);
1550
1551         return kvm_fast_pio_out(vcpu, size, port);
1552 }
1553
1554 static int nmi_interception(struct vcpu_svm *svm)
1555 {
1556         return 1;
1557 }
1558
1559 static int intr_interception(struct vcpu_svm *svm)
1560 {
1561         ++svm->vcpu.stat.irq_exits;
1562         return 1;
1563 }
1564
1565 static int nop_on_interception(struct vcpu_svm *svm)
1566 {
1567         return 1;
1568 }
1569
1570 static int halt_interception(struct vcpu_svm *svm)
1571 {
1572         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1573         skip_emulated_instruction(&svm->vcpu);
1574         return kvm_emulate_halt(&svm->vcpu);
1575 }
1576
1577 static int vmmcall_interception(struct vcpu_svm *svm)
1578 {
1579         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1580         skip_emulated_instruction(&svm->vcpu);
1581         kvm_emulate_hypercall(&svm->vcpu);
1582         return 1;
1583 }
1584
1585 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1586 {
1587         if (!(svm->vcpu.arch.efer & EFER_SVME)
1588             || !is_paging(&svm->vcpu)) {
1589                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1590                 return 1;
1591         }
1592
1593         if (svm->vmcb->save.cpl) {
1594                 kvm_inject_gp(&svm->vcpu, 0);
1595                 return 1;
1596         }
1597
1598        return 0;
1599 }
1600
1601 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1602                                       bool has_error_code, u32 error_code)
1603 {
1604         int vmexit;
1605
1606         if (!is_nested(svm))
1607                 return 0;
1608
1609         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1610         svm->vmcb->control.exit_code_hi = 0;
1611         svm->vmcb->control.exit_info_1 = error_code;
1612         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1613
1614         vmexit = nested_svm_intercept(svm);
1615         if (vmexit == NESTED_EXIT_DONE)
1616                 svm->nested.exit_required = true;
1617
1618         return vmexit;
1619 }
1620
1621 /* This function returns true if it is save to enable the irq window */
1622 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1623 {
1624         if (!is_nested(svm))
1625                 return true;
1626
1627         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1628                 return true;
1629
1630         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1631                 return false;
1632
1633         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1634         svm->vmcb->control.exit_info_1 = 0;
1635         svm->vmcb->control.exit_info_2 = 0;
1636
1637         if (svm->nested.intercept & 1ULL) {
1638                 /*
1639                  * The #vmexit can't be emulated here directly because this
1640                  * code path runs with irqs and preemtion disabled. A
1641                  * #vmexit emulation might sleep. Only signal request for
1642                  * the #vmexit here.
1643                  */
1644                 svm->nested.exit_required = true;
1645                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1646                 return false;
1647         }
1648
1649         return true;
1650 }
1651
1652 /* This function returns true if it is save to enable the nmi window */
1653 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1654 {
1655         if (!is_nested(svm))
1656                 return true;
1657
1658         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1659                 return true;
1660
1661         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1662         svm->nested.exit_required = true;
1663
1664         return false;
1665 }
1666
1667 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1668 {
1669         struct page *page;
1670
1671         might_sleep();
1672
1673         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1674         if (is_error_page(page))
1675                 goto error;
1676
1677         *_page = page;
1678
1679         return kmap(page);
1680
1681 error:
1682         kvm_release_page_clean(page);
1683         kvm_inject_gp(&svm->vcpu, 0);
1684
1685         return NULL;
1686 }
1687
1688 static void nested_svm_unmap(struct page *page)
1689 {
1690         kunmap(page);
1691         kvm_release_page_dirty(page);
1692 }
1693
1694 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1695 {
1696         unsigned port;
1697         u8 val, bit;
1698         u64 gpa;
1699
1700         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1701                 return NESTED_EXIT_HOST;
1702
1703         port = svm->vmcb->control.exit_info_1 >> 16;
1704         gpa  = svm->nested.vmcb_iopm + (port / 8);
1705         bit  = port % 8;
1706         val  = 0;
1707
1708         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1709                 val &= (1 << bit);
1710
1711         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1712 }
1713
1714 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1715 {
1716         u32 offset, msr, value;
1717         int write, mask;
1718
1719         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1720                 return NESTED_EXIT_HOST;
1721
1722         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1723         offset = svm_msrpm_offset(msr);
1724         write  = svm->vmcb->control.exit_info_1 & 1;
1725         mask   = 1 << ((2 * (msr & 0xf)) + write);
1726
1727         if (offset == MSR_INVALID)
1728                 return NESTED_EXIT_DONE;
1729
1730         /* Offset is in 32 bit units but need in 8 bit units */
1731         offset *= 4;
1732
1733         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1734                 return NESTED_EXIT_DONE;
1735
1736         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1737 }
1738
1739 static int nested_svm_exit_special(struct vcpu_svm *svm)
1740 {
1741         u32 exit_code = svm->vmcb->control.exit_code;
1742
1743         switch (exit_code) {
1744         case SVM_EXIT_INTR:
1745         case SVM_EXIT_NMI:
1746         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1747                 return NESTED_EXIT_HOST;
1748         case SVM_EXIT_NPF:
1749                 /* For now we are always handling NPFs when using them */
1750                 if (npt_enabled)
1751                         return NESTED_EXIT_HOST;
1752                 break;
1753         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1754                 /* When we're shadowing, trap PFs */
1755                 if (!npt_enabled)
1756                         return NESTED_EXIT_HOST;
1757                 break;
1758         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1759                 nm_interception(svm);
1760                 break;
1761         default:
1762                 break;
1763         }
1764
1765         return NESTED_EXIT_CONTINUE;
1766 }
1767
1768 /*
1769  * If this function returns true, this #vmexit was already handled
1770  */
1771 static int nested_svm_intercept(struct vcpu_svm *svm)
1772 {
1773         u32 exit_code = svm->vmcb->control.exit_code;
1774         int vmexit = NESTED_EXIT_HOST;
1775
1776         switch (exit_code) {
1777         case SVM_EXIT_MSR:
1778                 vmexit = nested_svm_exit_handled_msr(svm);
1779                 break;
1780         case SVM_EXIT_IOIO:
1781                 vmexit = nested_svm_intercept_ioio(svm);
1782                 break;
1783         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1784                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1785                 if (svm->nested.intercept_cr_read & cr_bits)
1786                         vmexit = NESTED_EXIT_DONE;
1787                 break;
1788         }
1789         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1790                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1791                 if (svm->nested.intercept_cr_write & cr_bits)
1792                         vmexit = NESTED_EXIT_DONE;
1793                 break;
1794         }
1795         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1796                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1797                 if (svm->nested.intercept_dr_read & dr_bits)
1798                         vmexit = NESTED_EXIT_DONE;
1799                 break;
1800         }
1801         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1802                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1803                 if (svm->nested.intercept_dr_write & dr_bits)
1804                         vmexit = NESTED_EXIT_DONE;
1805                 break;
1806         }
1807         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1808                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1809                 if (svm->nested.intercept_exceptions & excp_bits)
1810                         vmexit = NESTED_EXIT_DONE;
1811                 break;
1812         }
1813         case SVM_EXIT_ERR: {
1814                 vmexit = NESTED_EXIT_DONE;
1815                 break;
1816         }
1817         default: {
1818                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1819                 if (svm->nested.intercept & exit_bits)
1820                         vmexit = NESTED_EXIT_DONE;
1821         }
1822         }
1823
1824         return vmexit;
1825 }
1826
1827 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1828 {
1829         int vmexit;
1830
1831         vmexit = nested_svm_intercept(svm);
1832
1833         if (vmexit == NESTED_EXIT_DONE)
1834                 nested_svm_vmexit(svm);
1835
1836         return vmexit;
1837 }
1838
1839 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1840 {
1841         struct vmcb_control_area *dst  = &dst_vmcb->control;
1842         struct vmcb_control_area *from = &from_vmcb->control;
1843
1844         dst->intercept_cr_read    = from->intercept_cr_read;
1845         dst->intercept_cr_write   = from->intercept_cr_write;
1846         dst->intercept_dr_read    = from->intercept_dr_read;
1847         dst->intercept_dr_write   = from->intercept_dr_write;
1848         dst->intercept_exceptions = from->intercept_exceptions;
1849         dst->intercept            = from->intercept;
1850         dst->iopm_base_pa         = from->iopm_base_pa;
1851         dst->msrpm_base_pa        = from->msrpm_base_pa;
1852         dst->tsc_offset           = from->tsc_offset;
1853         dst->asid                 = from->asid;
1854         dst->tlb_ctl              = from->tlb_ctl;
1855         dst->int_ctl              = from->int_ctl;
1856         dst->int_vector           = from->int_vector;
1857         dst->int_state            = from->int_state;
1858         dst->exit_code            = from->exit_code;
1859         dst->exit_code_hi         = from->exit_code_hi;
1860         dst->exit_info_1          = from->exit_info_1;
1861         dst->exit_info_2          = from->exit_info_2;
1862         dst->exit_int_info        = from->exit_int_info;
1863         dst->exit_int_info_err    = from->exit_int_info_err;
1864         dst->nested_ctl           = from->nested_ctl;
1865         dst->event_inj            = from->event_inj;
1866         dst->event_inj_err        = from->event_inj_err;
1867         dst->nested_cr3           = from->nested_cr3;
1868         dst->lbr_ctl              = from->lbr_ctl;
1869 }
1870
1871 static int nested_svm_vmexit(struct vcpu_svm *svm)
1872 {
1873         struct vmcb *nested_vmcb;
1874         struct vmcb *hsave = svm->nested.hsave;
1875         struct vmcb *vmcb = svm->vmcb;
1876         struct page *page;
1877
1878         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1879                                        vmcb->control.exit_info_1,
1880                                        vmcb->control.exit_info_2,
1881                                        vmcb->control.exit_int_info,
1882                                        vmcb->control.exit_int_info_err);
1883
1884         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1885         if (!nested_vmcb)
1886                 return 1;
1887
1888         /* Exit nested SVM mode */
1889         svm->nested.vmcb = 0;
1890
1891         /* Give the current vmcb to the guest */
1892         disable_gif(svm);
1893
1894         nested_vmcb->save.es     = vmcb->save.es;
1895         nested_vmcb->save.cs     = vmcb->save.cs;
1896         nested_vmcb->save.ss     = vmcb->save.ss;
1897         nested_vmcb->save.ds     = vmcb->save.ds;
1898         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1899         nested_vmcb->save.idtr   = vmcb->save.idtr;
1900         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
1901         nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
1902         nested_vmcb->save.cr2    = vmcb->save.cr2;
1903         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
1904         nested_vmcb->save.rflags = vmcb->save.rflags;
1905         nested_vmcb->save.rip    = vmcb->save.rip;
1906         nested_vmcb->save.rsp    = vmcb->save.rsp;
1907         nested_vmcb->save.rax    = vmcb->save.rax;
1908         nested_vmcb->save.dr7    = vmcb->save.dr7;
1909         nested_vmcb->save.dr6    = vmcb->save.dr6;
1910         nested_vmcb->save.cpl    = vmcb->save.cpl;
1911
1912         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1913         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1914         nested_vmcb->control.int_state         = vmcb->control.int_state;
1915         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1916         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1917         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1918         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1919         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1920         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1921
1922         /*
1923          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1924          * to make sure that we do not lose injected events. So check event_inj
1925          * here and copy it to exit_int_info if it is valid.
1926          * Exit_int_info and event_inj can't be both valid because the case
1927          * below only happens on a VMRUN instruction intercept which has
1928          * no valid exit_int_info set.
1929          */
1930         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1931                 struct vmcb_control_area *nc = &nested_vmcb->control;
1932
1933                 nc->exit_int_info     = vmcb->control.event_inj;
1934                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1935         }
1936
1937         nested_vmcb->control.tlb_ctl           = 0;
1938         nested_vmcb->control.event_inj         = 0;
1939         nested_vmcb->control.event_inj_err     = 0;
1940
1941         /* We always set V_INTR_MASKING and remember the old value in hflags */
1942         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1943                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1944
1945         /* Restore the original control entries */
1946         copy_vmcb_control_area(vmcb, hsave);
1947
1948         kvm_clear_exception_queue(&svm->vcpu);
1949         kvm_clear_interrupt_queue(&svm->vcpu);
1950
1951         /* Restore selected save entries */
1952         svm->vmcb->save.es = hsave->save.es;
1953         svm->vmcb->save.cs = hsave->save.cs;
1954         svm->vmcb->save.ss = hsave->save.ss;
1955         svm->vmcb->save.ds = hsave->save.ds;
1956         svm->vmcb->save.gdtr = hsave->save.gdtr;
1957         svm->vmcb->save.idtr = hsave->save.idtr;
1958         svm->vmcb->save.rflags = hsave->save.rflags;
1959         svm_set_efer(&svm->vcpu, hsave->save.efer);
1960         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1961         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1962         if (npt_enabled) {
1963                 svm->vmcb->save.cr3 = hsave->save.cr3;
1964                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1965         } else {
1966                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1967         }
1968         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1969         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1970         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1971         svm->vmcb->save.dr7 = 0;
1972         svm->vmcb->save.cpl = 0;
1973         svm->vmcb->control.exit_int_info = 0;
1974
1975         nested_svm_unmap(page);
1976
1977         kvm_mmu_reset_context(&svm->vcpu);
1978         kvm_mmu_load(&svm->vcpu);
1979
1980         return 0;
1981 }
1982
1983 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1984 {
1985         /*
1986          * This function merges the msr permission bitmaps of kvm and the
1987          * nested vmcb. It is omptimized in that it only merges the parts where
1988          * the kvm msr permission bitmap may contain zero bits
1989          */
1990         int i;
1991
1992         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1993                 return true;
1994
1995         for (i = 0; i < MSRPM_OFFSETS; i++) {
1996                 u32 value, p;
1997                 u64 offset;
1998
1999                 if (msrpm_offsets[i] == 0xffffffff)
2000                         break;
2001
2002                 p      = msrpm_offsets[i];
2003                 offset = svm->nested.vmcb_msrpm + (p * 4);
2004
2005                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2006                         return false;
2007
2008                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2009         }
2010
2011         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2012
2013         return true;
2014 }
2015
2016 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2017 {
2018         struct vmcb *nested_vmcb;
2019         struct vmcb *hsave = svm->nested.hsave;
2020         struct vmcb *vmcb = svm->vmcb;
2021         struct page *page;
2022         u64 vmcb_gpa;
2023
2024         vmcb_gpa = svm->vmcb->save.rax;
2025
2026         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2027         if (!nested_vmcb)
2028                 return false;
2029
2030         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
2031                                nested_vmcb->save.rip,
2032                                nested_vmcb->control.int_ctl,
2033                                nested_vmcb->control.event_inj,
2034                                nested_vmcb->control.nested_ctl);
2035
2036         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2037                                     nested_vmcb->control.intercept_cr_write,
2038                                     nested_vmcb->control.intercept_exceptions,
2039                                     nested_vmcb->control.intercept);
2040
2041         /* Clear internal status */
2042         kvm_clear_exception_queue(&svm->vcpu);
2043         kvm_clear_interrupt_queue(&svm->vcpu);
2044
2045         /*
2046          * Save the old vmcb, so we don't need to pick what we save, but can
2047          * restore everything when a VMEXIT occurs
2048          */
2049         hsave->save.es     = vmcb->save.es;
2050         hsave->save.cs     = vmcb->save.cs;
2051         hsave->save.ss     = vmcb->save.ss;
2052         hsave->save.ds     = vmcb->save.ds;
2053         hsave->save.gdtr   = vmcb->save.gdtr;
2054         hsave->save.idtr   = vmcb->save.idtr;
2055         hsave->save.efer   = svm->vcpu.arch.efer;
2056         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2057         hsave->save.cr4    = svm->vcpu.arch.cr4;
2058         hsave->save.rflags = vmcb->save.rflags;
2059         hsave->save.rip    = svm->next_rip;
2060         hsave->save.rsp    = vmcb->save.rsp;
2061         hsave->save.rax    = vmcb->save.rax;
2062         if (npt_enabled)
2063                 hsave->save.cr3    = vmcb->save.cr3;
2064         else
2065                 hsave->save.cr3    = svm->vcpu.arch.cr3;
2066
2067         copy_vmcb_control_area(hsave, vmcb);
2068
2069         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2070                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2071         else
2072                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2073
2074         /* Load the nested guest state */
2075         svm->vmcb->save.es = nested_vmcb->save.es;
2076         svm->vmcb->save.cs = nested_vmcb->save.cs;
2077         svm->vmcb->save.ss = nested_vmcb->save.ss;
2078         svm->vmcb->save.ds = nested_vmcb->save.ds;
2079         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2080         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2081         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2082         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2083         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2084         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2085         if (npt_enabled) {
2086                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2087                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2088         } else
2089                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2090
2091         /* Guest paging mode is active - reset mmu */
2092         kvm_mmu_reset_context(&svm->vcpu);
2093
2094         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2095         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2096         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2097         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2098
2099         /* In case we don't even reach vcpu_run, the fields are not updated */
2100         svm->vmcb->save.rax = nested_vmcb->save.rax;
2101         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2102         svm->vmcb->save.rip = nested_vmcb->save.rip;
2103         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2104         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2105         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2106
2107         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2108         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2109
2110         /* cache intercepts */
2111         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
2112         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
2113         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
2114         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
2115         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2116         svm->nested.intercept            = nested_vmcb->control.intercept;
2117
2118         force_new_asid(&svm->vcpu);
2119         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2120         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2121                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2122         else
2123                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2124
2125         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2126                 /* We only want the cr8 intercept bits of the guest */
2127                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2128                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2129         }
2130
2131         /* We don't want to see VMMCALLs from a nested guest */
2132         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2133
2134         /*
2135          * We don't want a nested guest to be more powerful than the guest, so
2136          * all intercepts are ORed
2137          */
2138         svm->vmcb->control.intercept_cr_read |=
2139                 nested_vmcb->control.intercept_cr_read;
2140         svm->vmcb->control.intercept_cr_write |=
2141                 nested_vmcb->control.intercept_cr_write;
2142         svm->vmcb->control.intercept_dr_read |=
2143                 nested_vmcb->control.intercept_dr_read;
2144         svm->vmcb->control.intercept_dr_write |=
2145                 nested_vmcb->control.intercept_dr_write;
2146         svm->vmcb->control.intercept_exceptions |=
2147                 nested_vmcb->control.intercept_exceptions;
2148
2149         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2150
2151         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2152         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2153         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2154         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2155         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2156         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2157
2158         nested_svm_unmap(page);
2159
2160         /* nested_vmcb is our indicator if nested SVM is activated */
2161         svm->nested.vmcb = vmcb_gpa;
2162
2163         enable_gif(svm);
2164
2165         return true;
2166 }
2167
2168 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2169 {
2170         to_vmcb->save.fs = from_vmcb->save.fs;
2171         to_vmcb->save.gs = from_vmcb->save.gs;
2172         to_vmcb->save.tr = from_vmcb->save.tr;
2173         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2174         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2175         to_vmcb->save.star = from_vmcb->save.star;
2176         to_vmcb->save.lstar = from_vmcb->save.lstar;
2177         to_vmcb->save.cstar = from_vmcb->save.cstar;
2178         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2179         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2180         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2181         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2182 }
2183
2184 static int vmload_interception(struct vcpu_svm *svm)
2185 {
2186         struct vmcb *nested_vmcb;
2187         struct page *page;
2188
2189         if (nested_svm_check_permissions(svm))
2190                 return 1;
2191
2192         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2193         skip_emulated_instruction(&svm->vcpu);
2194
2195         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2196         if (!nested_vmcb)
2197                 return 1;
2198
2199         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2200         nested_svm_unmap(page);
2201
2202         return 1;
2203 }
2204
2205 static int vmsave_interception(struct vcpu_svm *svm)
2206 {
2207         struct vmcb *nested_vmcb;
2208         struct page *page;
2209
2210         if (nested_svm_check_permissions(svm))
2211                 return 1;
2212
2213         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2214         skip_emulated_instruction(&svm->vcpu);
2215
2216         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2217         if (!nested_vmcb)
2218                 return 1;
2219
2220         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2221         nested_svm_unmap(page);
2222
2223         return 1;
2224 }
2225
2226 static int vmrun_interception(struct vcpu_svm *svm)
2227 {
2228         if (nested_svm_check_permissions(svm))
2229                 return 1;
2230
2231         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2232         skip_emulated_instruction(&svm->vcpu);
2233
2234         if (!nested_svm_vmrun(svm))
2235                 return 1;
2236
2237         if (!nested_svm_vmrun_msrpm(svm))
2238                 goto failed;
2239
2240         return 1;
2241
2242 failed:
2243
2244         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2245         svm->vmcb->control.exit_code_hi = 0;
2246         svm->vmcb->control.exit_info_1  = 0;
2247         svm->vmcb->control.exit_info_2  = 0;
2248
2249         nested_svm_vmexit(svm);
2250
2251         return 1;
2252 }
2253
2254 static int stgi_interception(struct vcpu_svm *svm)
2255 {
2256         if (nested_svm_check_permissions(svm))
2257                 return 1;
2258
2259         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2260         skip_emulated_instruction(&svm->vcpu);
2261
2262         enable_gif(svm);
2263
2264         return 1;
2265 }
2266
2267 static int clgi_interception(struct vcpu_svm *svm)
2268 {
2269         if (nested_svm_check_permissions(svm))
2270                 return 1;
2271
2272         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2273         skip_emulated_instruction(&svm->vcpu);
2274
2275         disable_gif(svm);
2276
2277         /* After a CLGI no interrupts should come */
2278         svm_clear_vintr(svm);
2279         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2280
2281         return 1;
2282 }
2283
2284 static int invlpga_interception(struct vcpu_svm *svm)
2285 {
2286         struct kvm_vcpu *vcpu = &svm->vcpu;
2287
2288         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2289                           vcpu->arch.regs[VCPU_REGS_RAX]);
2290
2291         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2292         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2293
2294         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2295         skip_emulated_instruction(&svm->vcpu);
2296         return 1;
2297 }
2298
2299 static int skinit_interception(struct vcpu_svm *svm)
2300 {
2301         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2302
2303         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2304         return 1;
2305 }
2306
2307 static int invalid_op_interception(struct vcpu_svm *svm)
2308 {
2309         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2310         return 1;
2311 }
2312
2313 static int task_switch_interception(struct vcpu_svm *svm)
2314 {
2315         u16 tss_selector;
2316         int reason;
2317         int int_type = svm->vmcb->control.exit_int_info &
2318                 SVM_EXITINTINFO_TYPE_MASK;
2319         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2320         uint32_t type =
2321                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2322         uint32_t idt_v =
2323                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2324         bool has_error_code = false;
2325         u32 error_code = 0;
2326
2327         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2328
2329         if (svm->vmcb->control.exit_info_2 &
2330             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2331                 reason = TASK_SWITCH_IRET;
2332         else if (svm->vmcb->control.exit_info_2 &
2333                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2334                 reason = TASK_SWITCH_JMP;
2335         else if (idt_v)
2336                 reason = TASK_SWITCH_GATE;
2337         else
2338                 reason = TASK_SWITCH_CALL;
2339
2340         if (reason == TASK_SWITCH_GATE) {
2341                 switch (type) {
2342                 case SVM_EXITINTINFO_TYPE_NMI:
2343                         svm->vcpu.arch.nmi_injected = false;
2344                         break;
2345                 case SVM_EXITINTINFO_TYPE_EXEPT:
2346                         if (svm->vmcb->control.exit_info_2 &
2347                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2348                                 has_error_code = true;
2349                                 error_code =
2350                                         (u32)svm->vmcb->control.exit_info_2;
2351                         }
2352                         kvm_clear_exception_queue(&svm->vcpu);
2353                         break;
2354                 case SVM_EXITINTINFO_TYPE_INTR:
2355                         kvm_clear_interrupt_queue(&svm->vcpu);
2356                         break;
2357                 default:
2358                         break;
2359                 }
2360         }
2361
2362         if (reason != TASK_SWITCH_GATE ||
2363             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2364             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2365              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2366                 skip_emulated_instruction(&svm->vcpu);
2367
2368         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2369                                 has_error_code, error_code) == EMULATE_FAIL) {
2370                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2371                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2372                 svm->vcpu.run->internal.ndata = 0;
2373                 return 0;
2374         }
2375         return 1;
2376 }
2377
2378 static int cpuid_interception(struct vcpu_svm *svm)
2379 {
2380         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2381         kvm_emulate_cpuid(&svm->vcpu);
2382         return 1;
2383 }
2384
2385 static int iret_interception(struct vcpu_svm *svm)
2386 {
2387         ++svm->vcpu.stat.nmi_window_exits;
2388         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2389         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2390         return 1;
2391 }
2392
2393 static int invlpg_interception(struct vcpu_svm *svm)
2394 {
2395         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2396 }
2397
2398 static int emulate_on_interception(struct vcpu_svm *svm)
2399 {
2400         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2401 }
2402
2403 static int cr8_write_interception(struct vcpu_svm *svm)
2404 {
2405         struct kvm_run *kvm_run = svm->vcpu.run;
2406
2407         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2408         /* instruction emulation calls kvm_set_cr8() */
2409         emulate_instruction(&svm->vcpu, 0, 0, 0);
2410         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2411                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2412                 return 1;
2413         }
2414         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2415                 return 1;
2416         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2417         return 0;
2418 }
2419
2420 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2421 {
2422         struct vcpu_svm *svm = to_svm(vcpu);
2423
2424         switch (ecx) {
2425         case MSR_IA32_TSC: {
2426                 u64 tsc_offset;
2427
2428                 if (is_nested(svm))
2429                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2430                 else
2431                         tsc_offset = svm->vmcb->control.tsc_offset;
2432
2433                 *data = tsc_offset + native_read_tsc();
2434                 break;
2435         }
2436         case MSR_K6_STAR:
2437                 *data = svm->vmcb->save.star;
2438                 break;
2439 #ifdef CONFIG_X86_64
2440         case MSR_LSTAR:
2441                 *data = svm->vmcb->save.lstar;
2442                 break;
2443         case MSR_CSTAR:
2444                 *data = svm->vmcb->save.cstar;
2445                 break;
2446         case MSR_KERNEL_GS_BASE:
2447                 *data = svm->vmcb->save.kernel_gs_base;
2448                 break;
2449         case MSR_SYSCALL_MASK:
2450                 *data = svm->vmcb->save.sfmask;
2451                 break;
2452 #endif
2453         case MSR_IA32_SYSENTER_CS:
2454                 *data = svm->vmcb->save.sysenter_cs;
2455                 break;
2456         case MSR_IA32_SYSENTER_EIP:
2457                 *data = svm->sysenter_eip;
2458                 break;
2459         case MSR_IA32_SYSENTER_ESP:
2460                 *data = svm->sysenter_esp;
2461                 break;
2462         /*
2463          * Nobody will change the following 5 values in the VMCB so we can
2464          * safely return them on rdmsr. They will always be 0 until LBRV is
2465          * implemented.
2466          */
2467         case MSR_IA32_DEBUGCTLMSR:
2468                 *data = svm->vmcb->save.dbgctl;
2469                 break;
2470         case MSR_IA32_LASTBRANCHFROMIP:
2471                 *data = svm->vmcb->save.br_from;
2472                 break;
2473         case MSR_IA32_LASTBRANCHTOIP:
2474                 *data = svm->vmcb->save.br_to;
2475                 break;
2476         case MSR_IA32_LASTINTFROMIP:
2477                 *data = svm->vmcb->save.last_excp_from;
2478                 break;
2479         case MSR_IA32_LASTINTTOIP:
2480                 *data = svm->vmcb->save.last_excp_to;
2481                 break;
2482         case MSR_VM_HSAVE_PA:
2483                 *data = svm->nested.hsave_msr;
2484                 break;
2485         case MSR_VM_CR:
2486                 *data = svm->nested.vm_cr_msr;
2487                 break;
2488         case MSR_IA32_UCODE_REV:
2489                 *data = 0x01000065;
2490                 break;
2491         default:
2492                 return kvm_get_msr_common(vcpu, ecx, data);
2493         }
2494         return 0;
2495 }
2496
2497 static int rdmsr_interception(struct vcpu_svm *svm)
2498 {
2499         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2500         u64 data;
2501
2502         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2503                 trace_kvm_msr_read_ex(ecx);
2504                 kvm_inject_gp(&svm->vcpu, 0);
2505         } else {
2506                 trace_kvm_msr_read(ecx, data);
2507
2508                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2509                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2510                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2511                 skip_emulated_instruction(&svm->vcpu);
2512         }
2513         return 1;
2514 }
2515
2516 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2517 {
2518         struct vcpu_svm *svm = to_svm(vcpu);
2519         int svm_dis, chg_mask;
2520
2521         if (data & ~SVM_VM_CR_VALID_MASK)
2522                 return 1;
2523
2524         chg_mask = SVM_VM_CR_VALID_MASK;
2525
2526         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2527                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2528
2529         svm->nested.vm_cr_msr &= ~chg_mask;
2530         svm->nested.vm_cr_msr |= (data & chg_mask);
2531
2532         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2533
2534         /* check for svm_disable while efer.svme is set */
2535         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2536                 return 1;
2537
2538         return 0;
2539 }
2540
2541 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2542 {
2543         struct vcpu_svm *svm = to_svm(vcpu);
2544
2545         switch (ecx) {
2546         case MSR_IA32_TSC: {
2547                 u64 tsc_offset = data - native_read_tsc();
2548                 u64 g_tsc_offset = 0;
2549
2550                 if (is_nested(svm)) {
2551                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2552                                        svm->nested.hsave->control.tsc_offset;
2553                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2554                 }
2555
2556                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2557
2558                 break;
2559         }
2560         case MSR_K6_STAR:
2561                 svm->vmcb->save.star = data;
2562                 break;
2563 #ifdef CONFIG_X86_64
2564         case MSR_LSTAR:
2565                 svm->vmcb->save.lstar = data;
2566                 break;
2567         case MSR_CSTAR:
2568                 svm->vmcb->save.cstar = data;
2569                 break;
2570         case MSR_KERNEL_GS_BASE:
2571                 svm->vmcb->save.kernel_gs_base = data;
2572                 break;
2573         case MSR_SYSCALL_MASK:
2574                 svm->vmcb->save.sfmask = data;
2575                 break;
2576 #endif
2577         case MSR_IA32_SYSENTER_CS:
2578                 svm->vmcb->save.sysenter_cs = data;
2579                 break;
2580         case MSR_IA32_SYSENTER_EIP:
2581                 svm->sysenter_eip = data;
2582                 svm->vmcb->save.sysenter_eip = data;
2583                 break;
2584         case MSR_IA32_SYSENTER_ESP:
2585                 svm->sysenter_esp = data;
2586                 svm->vmcb->save.sysenter_esp = data;
2587                 break;
2588         case MSR_IA32_DEBUGCTLMSR:
2589                 if (!svm_has(SVM_FEATURE_LBRV)) {
2590                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2591                                         __func__, data);
2592                         break;
2593                 }
2594                 if (data & DEBUGCTL_RESERVED_BITS)
2595                         return 1;
2596
2597                 svm->vmcb->save.dbgctl = data;
2598                 if (data & (1ULL<<0))
2599                         svm_enable_lbrv(svm);
2600                 else
2601                         svm_disable_lbrv(svm);
2602                 break;
2603         case MSR_VM_HSAVE_PA:
2604                 svm->nested.hsave_msr = data;
2605                 break;
2606         case MSR_VM_CR:
2607                 return svm_set_vm_cr(vcpu, data);
2608         case MSR_VM_IGNNE:
2609                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2610                 break;
2611         default:
2612                 return kvm_set_msr_common(vcpu, ecx, data);
2613         }
2614         return 0;
2615 }
2616
2617 static int wrmsr_interception(struct vcpu_svm *svm)
2618 {
2619         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2620         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2621                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2622
2623
2624         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2625         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2626                 trace_kvm_msr_write_ex(ecx, data);
2627                 kvm_inject_gp(&svm->vcpu, 0);
2628         } else {
2629                 trace_kvm_msr_write(ecx, data);
2630                 skip_emulated_instruction(&svm->vcpu);
2631         }
2632         return 1;
2633 }
2634
2635 static int msr_interception(struct vcpu_svm *svm)
2636 {
2637         if (svm->vmcb->control.exit_info_1)
2638                 return wrmsr_interception(svm);
2639         else
2640                 return rdmsr_interception(svm);
2641 }
2642
2643 static int interrupt_window_interception(struct vcpu_svm *svm)
2644 {
2645         struct kvm_run *kvm_run = svm->vcpu.run;
2646
2647         svm_clear_vintr(svm);
2648         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2649         /*
2650          * If the user space waits to inject interrupts, exit as soon as
2651          * possible
2652          */
2653         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2654             kvm_run->request_interrupt_window &&
2655             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2656                 ++svm->vcpu.stat.irq_window_exits;
2657                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2658                 return 0;
2659         }
2660
2661         return 1;
2662 }
2663
2664 static int pause_interception(struct vcpu_svm *svm)
2665 {
2666         kvm_vcpu_on_spin(&(svm->vcpu));
2667         return 1;
2668 }
2669
2670 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2671         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2672         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2673         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2674         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2675         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2676         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2677         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2678         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2679         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2680         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2681         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2682         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2683         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2684         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2685         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2686         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2687         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2688         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2689         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2690         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2691         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2692         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2693         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2694         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2695         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2696         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2697         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2698         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2699         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2700         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2701         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2702         [SVM_EXIT_INTR]                         = intr_interception,
2703         [SVM_EXIT_NMI]                          = nmi_interception,
2704         [SVM_EXIT_SMI]                          = nop_on_interception,
2705         [SVM_EXIT_INIT]                         = nop_on_interception,
2706         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2707         [SVM_EXIT_CPUID]                        = cpuid_interception,
2708         [SVM_EXIT_IRET]                         = iret_interception,
2709         [SVM_EXIT_INVD]                         = emulate_on_interception,
2710         [SVM_EXIT_PAUSE]                        = pause_interception,
2711         [SVM_EXIT_HLT]                          = halt_interception,
2712         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2713         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2714         [SVM_EXIT_IOIO]                         = io_interception,
2715         [SVM_EXIT_MSR]                          = msr_interception,
2716         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2717         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2718         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2719         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2720         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2721         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2722         [SVM_EXIT_STGI]                         = stgi_interception,
2723         [SVM_EXIT_CLGI]                         = clgi_interception,
2724         [SVM_EXIT_SKINIT]                       = skinit_interception,
2725         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2726         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2727         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2728         [SVM_EXIT_NPF]                          = pf_interception,
2729 };
2730
2731 void dump_vmcb(struct kvm_vcpu *vcpu)
2732 {
2733         struct vcpu_svm *svm = to_svm(vcpu);
2734         struct vmcb_control_area *control = &svm->vmcb->control;
2735         struct vmcb_save_area *save = &svm->vmcb->save;
2736
2737         pr_err("VMCB Control Area:\n");
2738         pr_err("cr_read:            %04x\n", control->intercept_cr_read);
2739         pr_err("cr_write:           %04x\n", control->intercept_cr_write);
2740         pr_err("dr_read:            %04x\n", control->intercept_dr_read);
2741         pr_err("dr_write:           %04x\n", control->intercept_dr_write);
2742         pr_err("exceptions:         %08x\n", control->intercept_exceptions);
2743         pr_err("intercepts:         %016llx\n", control->intercept);
2744         pr_err("pause filter count: %d\n", control->pause_filter_count);
2745         pr_err("iopm_base_pa:       %016llx\n", control->iopm_base_pa);
2746         pr_err("msrpm_base_pa:      %016llx\n", control->msrpm_base_pa);
2747         pr_err("tsc_offset:         %016llx\n", control->tsc_offset);
2748         pr_err("asid:               %d\n", control->asid);
2749         pr_err("tlb_ctl:            %d\n", control->tlb_ctl);
2750         pr_err("int_ctl:            %08x\n", control->int_ctl);
2751         pr_err("int_vector:         %08x\n", control->int_vector);
2752         pr_err("int_state:          %08x\n", control->int_state);
2753         pr_err("exit_code:          %08x\n", control->exit_code);
2754         pr_err("exit_info1:         %016llx\n", control->exit_info_1);
2755         pr_err("exit_info2:         %016llx\n", control->exit_info_2);
2756         pr_err("exit_int_info:      %08x\n", control->exit_int_info);
2757         pr_err("exit_int_info_err:  %08x\n", control->exit_int_info_err);
2758         pr_err("nested_ctl:         %lld\n", control->nested_ctl);
2759         pr_err("nested_cr3:         %016llx\n", control->nested_cr3);
2760         pr_err("event_inj:          %08x\n", control->event_inj);
2761         pr_err("event_inj_err:      %08x\n", control->event_inj_err);
2762         pr_err("lbr_ctl:            %lld\n", control->lbr_ctl);
2763         pr_err("next_rip:           %016llx\n", control->next_rip);
2764         pr_err("VMCB State Save Area:\n");
2765         pr_err("es:   s: %04x a: %04x l: %08x b: %016llx\n",
2766                 save->es.selector, save->es.attrib,
2767                 save->es.limit, save->es.base);
2768         pr_err("cs:   s: %04x a: %04x l: %08x b: %016llx\n",
2769                 save->cs.selector, save->cs.attrib,
2770                 save->cs.limit, save->cs.base);
2771         pr_err("ss:   s: %04x a: %04x l: %08x b: %016llx\n",
2772                 save->ss.selector, save->ss.attrib,
2773                 save->ss.limit, save->ss.base);
2774         pr_err("ds:   s: %04x a: %04x l: %08x b: %016llx\n",
2775                 save->ds.selector, save->ds.attrib,
2776                 save->ds.limit, save->ds.base);
2777         pr_err("fs:   s: %04x a: %04x l: %08x b: %016llx\n",
2778                 save->fs.selector, save->fs.attrib,
2779                 save->fs.limit, save->fs.base);
2780         pr_err("gs:   s: %04x a: %04x l: %08x b: %016llx\n",
2781                 save->gs.selector, save->gs.attrib,
2782                 save->gs.limit, save->gs.base);
2783         pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2784                 save->gdtr.selector, save->gdtr.attrib,
2785                 save->gdtr.limit, save->gdtr.base);
2786         pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2787                 save->ldtr.selector, save->ldtr.attrib,
2788                 save->ldtr.limit, save->ldtr.base);
2789         pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2790                 save->idtr.selector, save->idtr.attrib,
2791                 save->idtr.limit, save->idtr.base);
2792         pr_err("tr:   s: %04x a: %04x l: %08x b: %016llx\n",
2793                 save->tr.selector, save->tr.attrib,
2794                 save->tr.limit, save->tr.base);
2795         pr_err("cpl:            %d                efer:         %016llx\n",
2796                 save->cpl, save->efer);
2797         pr_err("cr0:            %016llx cr2:          %016llx\n",
2798                 save->cr0, save->cr2);
2799         pr_err("cr3:            %016llx cr4:          %016llx\n",
2800                 save->cr3, save->cr4);
2801         pr_err("dr6:            %016llx dr7:          %016llx\n",
2802                 save->dr6, save->dr7);
2803         pr_err("rip:            %016llx rflags:       %016llx\n",
2804                 save->rip, save->rflags);
2805         pr_err("rsp:            %016llx rax:          %016llx\n",
2806                 save->rsp, save->rax);
2807         pr_err("star:           %016llx lstar:        %016llx\n",
2808                 save->star, save->lstar);
2809         pr_err("cstar:          %016llx sfmask:       %016llx\n",
2810                 save->cstar, save->sfmask);
2811         pr_err("kernel_gs_base: %016llx sysenter_cs:  %016llx\n",
2812                 save->kernel_gs_base, save->sysenter_cs);
2813         pr_err("sysenter_esp:   %016llx sysenter_eip: %016llx\n",
2814                 save->sysenter_esp, save->sysenter_eip);
2815         pr_err("gpat:           %016llx dbgctl:       %016llx\n",
2816                 save->g_pat, save->dbgctl);
2817         pr_err("br_from:        %016llx br_to:        %016llx\n",
2818                 save->br_from, save->br_to);
2819         pr_err("excp_from:      %016llx excp_to:      %016llx\n",
2820                 save->last_excp_from, save->last_excp_to);
2821
2822 }
2823
2824 static int handle_exit(struct kvm_vcpu *vcpu)
2825 {
2826         struct vcpu_svm *svm = to_svm(vcpu);
2827         struct kvm_run *kvm_run = vcpu->run;
2828         u32 exit_code = svm->vmcb->control.exit_code;
2829
2830         trace_kvm_exit(exit_code, vcpu);
2831
2832         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2833                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2834         if (npt_enabled)
2835                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2836
2837         if (unlikely(svm->nested.exit_required)) {
2838                 nested_svm_vmexit(svm);
2839                 svm->nested.exit_required = false;
2840
2841                 return 1;
2842         }
2843
2844         if (is_nested(svm)) {
2845                 int vmexit;
2846
2847                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2848                                         svm->vmcb->control.exit_info_1,
2849                                         svm->vmcb->control.exit_info_2,
2850                                         svm->vmcb->control.exit_int_info,
2851                                         svm->vmcb->control.exit_int_info_err);
2852
2853                 vmexit = nested_svm_exit_special(svm);
2854
2855                 if (vmexit == NESTED_EXIT_CONTINUE)
2856                         vmexit = nested_svm_exit_handled(svm);
2857
2858                 if (vmexit == NESTED_EXIT_DONE)
2859                         return 1;
2860         }
2861
2862         svm_complete_interrupts(svm);
2863
2864         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2865                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2866                 kvm_run->fail_entry.hardware_entry_failure_reason
2867                         = svm->vmcb->control.exit_code;
2868                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2869                 dump_vmcb(vcpu);
2870                 return 0;
2871         }
2872
2873         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2874             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2875             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2876                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2877                        "exit_code 0x%x\n",
2878                        __func__, svm->vmcb->control.exit_int_info,
2879                        exit_code);
2880
2881         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2882             || !svm_exit_handlers[exit_code]) {
2883                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2884                 kvm_run->hw.hardware_exit_reason = exit_code;
2885                 return 0;
2886         }
2887
2888         return svm_exit_handlers[exit_code](svm);
2889 }
2890
2891 static void reload_tss(struct kvm_vcpu *vcpu)
2892 {
2893         int cpu = raw_smp_processor_id();
2894
2895         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2896         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2897         load_TR_desc();
2898 }
2899
2900 static void pre_svm_run(struct vcpu_svm *svm)
2901 {
2902         int cpu = raw_smp_processor_id();
2903
2904         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2905
2906         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2907         /* FIXME: handle wraparound of asid_generation */
2908         if (svm->asid_generation != sd->asid_generation)
2909                 new_asid(svm, sd);
2910 }
2911
2912 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2913 {
2914         struct vcpu_svm *svm = to_svm(vcpu);
2915
2916         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2917         vcpu->arch.hflags |= HF_NMI_MASK;
2918         svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2919         ++vcpu->stat.nmi_injections;
2920 }
2921
2922 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2923 {
2924         struct vmcb_control_area *control;
2925
2926         control = &svm->vmcb->control;
2927         control->int_vector = irq;
2928         control->int_ctl &= ~V_INTR_PRIO_MASK;
2929         control->int_ctl |= V_IRQ_MASK |
2930                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2931 }
2932
2933 static void svm_set_irq(struct kvm_vcpu *vcpu)
2934 {
2935         struct vcpu_svm *svm = to_svm(vcpu);
2936
2937         BUG_ON(!(gif_set(svm)));
2938
2939         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
2940         ++vcpu->stat.irq_injections;
2941
2942         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2943                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2944 }
2945
2946 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2947 {
2948         struct vcpu_svm *svm = to_svm(vcpu);
2949
2950         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2951                 return;
2952
2953         if (irr == -1)
2954                 return;
2955
2956         if (tpr >= irr)
2957                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2958 }
2959
2960 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2961 {
2962         struct vcpu_svm *svm = to_svm(vcpu);
2963         struct vmcb *vmcb = svm->vmcb;
2964         int ret;
2965         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2966               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2967         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2968
2969         return ret;
2970 }
2971
2972 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2973 {
2974         struct vcpu_svm *svm = to_svm(vcpu);
2975
2976         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2977 }
2978
2979 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2980 {
2981         struct vcpu_svm *svm = to_svm(vcpu);
2982
2983         if (masked) {
2984                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2985                 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2986         } else {
2987                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2988                 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2989         }
2990 }
2991
2992 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2993 {
2994         struct vcpu_svm *svm = to_svm(vcpu);
2995         struct vmcb *vmcb = svm->vmcb;
2996         int ret;
2997
2998         if (!gif_set(svm) ||
2999              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3000                 return 0;
3001
3002         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3003
3004         if (is_nested(svm))
3005                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3006
3007         return ret;
3008 }
3009
3010 static void enable_irq_window(struct kvm_vcpu *vcpu)
3011 {
3012         struct vcpu_svm *svm = to_svm(vcpu);
3013
3014         /*
3015          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3016          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3017          * get that intercept, this function will be called again though and
3018          * we'll get the vintr intercept.
3019          */
3020         if (gif_set(svm) && nested_svm_intr(svm)) {
3021                 svm_set_vintr(svm);
3022                 svm_inject_irq(svm, 0x0);
3023         }
3024 }
3025
3026 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3027 {
3028         struct vcpu_svm *svm = to_svm(vcpu);
3029
3030         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3031             == HF_NMI_MASK)
3032                 return; /* IRET will cause a vm exit */
3033
3034         /*
3035          * Something prevents NMI from been injected. Single step over possible
3036          * problem (IRET or exception injection or interrupt shadow)
3037          */
3038         svm->nmi_singlestep = true;
3039         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3040         update_db_intercept(vcpu);
3041 }
3042
3043 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3044 {
3045         return 0;
3046 }
3047
3048 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3049 {
3050         force_new_asid(vcpu);
3051 }
3052
3053 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3054 {
3055 }
3056
3057 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3058 {
3059         struct vcpu_svm *svm = to_svm(vcpu);
3060
3061         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3062                 return;
3063
3064         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3065                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3066                 kvm_set_cr8(vcpu, cr8);
3067         }
3068 }
3069
3070 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3071 {
3072         struct vcpu_svm *svm = to_svm(vcpu);
3073         u64 cr8;
3074
3075         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3076                 return;
3077
3078         cr8 = kvm_get_cr8(vcpu);
3079         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3080         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3081 }
3082
3083 static void svm_complete_interrupts(struct vcpu_svm *svm)
3084 {
3085         u8 vector;
3086         int type;
3087         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3088         unsigned int3_injected = svm->int3_injected;
3089
3090         svm->int3_injected = 0;
3091
3092         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
3093                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3094
3095         svm->vcpu.arch.nmi_injected = false;
3096         kvm_clear_exception_queue(&svm->vcpu);
3097         kvm_clear_interrupt_queue(&svm->vcpu);
3098
3099         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3100                 return;
3101
3102         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3103         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3104
3105         switch (type) {
3106         case SVM_EXITINTINFO_TYPE_NMI:
3107                 svm->vcpu.arch.nmi_injected = true;
3108                 break;
3109         case SVM_EXITINTINFO_TYPE_EXEPT:
3110                 /*
3111                  * In case of software exceptions, do not reinject the vector,
3112                  * but re-execute the instruction instead. Rewind RIP first
3113                  * if we emulated INT3 before.
3114                  */
3115                 if (kvm_exception_is_soft(vector)) {
3116                         if (vector == BP_VECTOR && int3_injected &&
3117                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3118                                 kvm_rip_write(&svm->vcpu,
3119                                               kvm_rip_read(&svm->vcpu) -
3120                                               int3_injected);
3121                         break;
3122                 }
3123                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3124                         u32 err = svm->vmcb->control.exit_int_info_err;
3125                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3126
3127                 } else
3128                         kvm_requeue_exception(&svm->vcpu, vector);
3129                 break;
3130         case SVM_EXITINTINFO_TYPE_INTR:
3131                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3132                 break;
3133         default:
3134                 break;
3135         }
3136 }
3137
3138 #ifdef CONFIG_X86_64
3139 #define R "r"
3140 #else
3141 #define R "e"
3142 #endif
3143
3144 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3145 {
3146         struct vcpu_svm *svm = to_svm(vcpu);
3147         u16 fs_selector;
3148         u16 gs_selector;
3149         u16 ldt_selector;
3150
3151         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3152         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3153         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3154
3155         /*
3156          * A vmexit emulation is required before the vcpu can be executed
3157          * again.
3158          */
3159         if (unlikely(svm->nested.exit_required))
3160                 return;
3161
3162         pre_svm_run(svm);
3163
3164         sync_lapic_to_cr8(vcpu);
3165
3166         save_host_msrs(vcpu);
3167         fs_selector = kvm_read_fs();
3168         gs_selector = kvm_read_gs();
3169         ldt_selector = kvm_read_ldt();
3170         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3171         /* required for live migration with NPT */
3172         if (npt_enabled)
3173                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3174
3175         clgi();
3176
3177         local_irq_enable();
3178
3179         asm volatile (
3180                 "push %%"R"bp; \n\t"
3181                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3182                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3183                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3184                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3185                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3186                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3187 #ifdef CONFIG_X86_64
3188                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3189                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3190                 "mov %c[r10](%[svm]), %%r10 \n\t"
3191                 "mov %c[r11](%[svm]), %%r11 \n\t"
3192                 "mov %c[r12](%[svm]), %%r12 \n\t"
3193                 "mov %c[r13](%[svm]), %%r13 \n\t"
3194                 "mov %c[r14](%[svm]), %%r14 \n\t"
3195                 "mov %c[r15](%[svm]), %%r15 \n\t"
3196 #endif
3197
3198                 /* Enter guest mode */
3199                 "push %%"R"ax \n\t"
3200                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3201                 __ex(SVM_VMLOAD) "\n\t"
3202                 __ex(SVM_VMRUN) "\n\t"
3203                 __ex(SVM_VMSAVE) "\n\t"
3204                 "pop %%"R"ax \n\t"
3205
3206                 /* Save guest registers, load host registers */
3207                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3208                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3209                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3210                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3211                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3212                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3213 #ifdef CONFIG_X86_64
3214                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3215                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3216                 "mov %%r10, %c[r10](%[svm]) \n\t"
3217                 "mov %%r11, %c[r11](%[svm]) \n\t"
3218                 "mov %%r12, %c[r12](%[svm]) \n\t"
3219                 "mov %%r13, %c[r13](%[svm]) \n\t"
3220                 "mov %%r14, %c[r14](%[svm]) \n\t"
3221                 "mov %%r15, %c[r15](%[svm]) \n\t"
3222 #endif
3223                 "pop %%"R"bp"
3224                 :
3225                 : [svm]"a"(svm),
3226                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3227                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3228                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3229                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3230                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3231                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3232                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3233 #ifdef CONFIG_X86_64
3234                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3235                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3236                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3237                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3238                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3239                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3240                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3241                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3242 #endif
3243                 : "cc", "memory"
3244                 , R"bx", R"cx", R"dx", R"si", R"di"
3245 #ifdef CONFIG_X86_64
3246                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3247 #endif
3248                 );
3249
3250         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3251         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3252         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3253         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3254
3255         kvm_load_fs(fs_selector);
3256         kvm_load_gs(gs_selector);
3257         kvm_load_ldt(ldt_selector);
3258         load_host_msrs(vcpu);
3259
3260         reload_tss(vcpu);
3261
3262         local_irq_disable();
3263
3264         stgi();
3265
3266         sync_cr8_to_lapic(vcpu);
3267
3268         svm->next_rip = 0;
3269
3270         if (npt_enabled) {
3271                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3272                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3273         }
3274
3275         /*
3276          * We need to handle MC intercepts here before the vcpu has a chance to
3277          * change the physical cpu
3278          */
3279         if (unlikely(svm->vmcb->control.exit_code ==
3280                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3281                 svm_handle_mce(svm);
3282 }
3283
3284 #undef R
3285
3286 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3287 {
3288         struct vcpu_svm *svm = to_svm(vcpu);
3289
3290         if (npt_enabled) {
3291                 svm->vmcb->control.nested_cr3 = root;
3292                 force_new_asid(vcpu);
3293                 return;
3294         }
3295
3296         svm->vmcb->save.cr3 = root;
3297         force_new_asid(vcpu);
3298 }
3299
3300 static int is_disabled(void)
3301 {
3302         u64 vm_cr;
3303
3304         rdmsrl(MSR_VM_CR, vm_cr);
3305         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3306                 return 1;
3307
3308         return 0;
3309 }
3310
3311 static void
3312 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3313 {
3314         /*
3315          * Patch in the VMMCALL instruction:
3316          */
3317         hypercall[0] = 0x0f;
3318         hypercall[1] = 0x01;
3319         hypercall[2] = 0xd9;
3320 }
3321
3322 static void svm_check_processor_compat(void *rtn)
3323 {
3324         *(int *)rtn = 0;
3325 }
3326
3327 static bool svm_cpu_has_accelerated_tpr(void)
3328 {
3329         return false;
3330 }
3331
3332 static int get_npt_level(void)
3333 {
3334 #ifdef CONFIG_X86_64
3335         return PT64_ROOT_LEVEL;
3336 #else
3337         return PT32E_ROOT_LEVEL;
3338 #endif
3339 }
3340
3341 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3342 {
3343         return 0;
3344 }
3345
3346 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3347 {
3348 }
3349
3350 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3351 {
3352         switch (func) {
3353         case 0x8000000A:
3354                 entry->eax = 1; /* SVM revision 1 */
3355                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3356                                    ASID emulation to nested SVM */
3357                 entry->ecx = 0; /* Reserved */
3358                 entry->edx = 0; /* Do not support any additional features */
3359
3360                 break;
3361         }
3362 }
3363
3364 static const struct trace_print_flags svm_exit_reasons_str[] = {
3365         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3366         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3367         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3368         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3369         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3370         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3371         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3372         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3373         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3374         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3375         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3376         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3377         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3378         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3379         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3380         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3381         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3382         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3383         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3384         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3385         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3386         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3387         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3388         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3389         { SVM_EXIT_INTR,                        "interrupt" },
3390         { SVM_EXIT_NMI,                         "nmi" },
3391         { SVM_EXIT_SMI,                         "smi" },
3392         { SVM_EXIT_INIT,                        "init" },
3393         { SVM_EXIT_VINTR,                       "vintr" },
3394         { SVM_EXIT_CPUID,                       "cpuid" },
3395         { SVM_EXIT_INVD,                        "invd" },
3396         { SVM_EXIT_HLT,                         "hlt" },
3397         { SVM_EXIT_INVLPG,                      "invlpg" },
3398         { SVM_EXIT_INVLPGA,                     "invlpga" },
3399         { SVM_EXIT_IOIO,                        "io" },
3400         { SVM_EXIT_MSR,                         "msr" },
3401         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3402         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3403         { SVM_EXIT_VMRUN,                       "vmrun" },
3404         { SVM_EXIT_VMMCALL,                     "hypercall" },
3405         { SVM_EXIT_VMLOAD,                      "vmload" },
3406         { SVM_EXIT_VMSAVE,                      "vmsave" },
3407         { SVM_EXIT_STGI,                        "stgi" },
3408         { SVM_EXIT_CLGI,                        "clgi" },
3409         { SVM_EXIT_SKINIT,                      "skinit" },
3410         { SVM_EXIT_WBINVD,                      "wbinvd" },
3411         { SVM_EXIT_MONITOR,                     "monitor" },
3412         { SVM_EXIT_MWAIT,                       "mwait" },
3413         { SVM_EXIT_NPF,                         "npf" },
3414         { -1, NULL }
3415 };
3416
3417 static int svm_get_lpage_level(void)
3418 {
3419         return PT_PDPE_LEVEL;
3420 }
3421
3422 static bool svm_rdtscp_supported(void)
3423 {
3424         return false;
3425 }
3426
3427 static bool svm_has_wbinvd_exit(void)
3428 {
3429         return true;
3430 }
3431
3432 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3433 {
3434         struct vcpu_svm *svm = to_svm(vcpu);
3435
3436         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3437         if (is_nested(svm))
3438                 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3439         update_cr0_intercept(svm);
3440 }
3441
3442 static struct kvm_x86_ops svm_x86_ops = {
3443         .cpu_has_kvm_support = has_svm,
3444         .disabled_by_bios = is_disabled,
3445         .hardware_setup = svm_hardware_setup,
3446         .hardware_unsetup = svm_hardware_unsetup,
3447         .check_processor_compatibility = svm_check_processor_compat,
3448         .hardware_enable = svm_hardware_enable,
3449         .hardware_disable = svm_hardware_disable,
3450         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3451
3452         .vcpu_create = svm_create_vcpu,
3453         .vcpu_free = svm_free_vcpu,
3454         .vcpu_reset = svm_vcpu_reset,
3455
3456         .prepare_guest_switch = svm_prepare_guest_switch,
3457         .vcpu_load = svm_vcpu_load,
3458         .vcpu_put = svm_vcpu_put,
3459
3460         .set_guest_debug = svm_guest_debug,
3461         .get_msr = svm_get_msr,
3462         .set_msr = svm_set_msr,
3463         .get_segment_base = svm_get_segment_base,
3464         .get_segment = svm_get_segment,
3465         .set_segment = svm_set_segment,
3466         .get_cpl = svm_get_cpl,
3467         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3468         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3469         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3470         .set_cr0 = svm_set_cr0,
3471         .set_cr3 = svm_set_cr3,
3472         .set_cr4 = svm_set_cr4,
3473         .set_efer = svm_set_efer,
3474         .get_idt = svm_get_idt,
3475         .set_idt = svm_set_idt,
3476         .get_gdt = svm_get_gdt,
3477         .set_gdt = svm_set_gdt,
3478         .set_dr7 = svm_set_dr7,
3479         .cache_reg = svm_cache_reg,
3480         .get_rflags = svm_get_rflags,
3481         .set_rflags = svm_set_rflags,
3482         .fpu_activate = svm_fpu_activate,
3483         .fpu_deactivate = svm_fpu_deactivate,
3484
3485         .tlb_flush = svm_flush_tlb,
3486
3487         .run = svm_vcpu_run,
3488         .handle_exit = handle_exit,
3489         .skip_emulated_instruction = skip_emulated_instruction,
3490         .set_interrupt_shadow = svm_set_interrupt_shadow,
3491         .get_interrupt_shadow = svm_get_interrupt_shadow,
3492         .patch_hypercall = svm_patch_hypercall,
3493         .set_irq = svm_set_irq,
3494         .set_nmi = svm_inject_nmi,
3495         .queue_exception = svm_queue_exception,
3496         .interrupt_allowed = svm_interrupt_allowed,
3497         .nmi_allowed = svm_nmi_allowed,
3498         .get_nmi_mask = svm_get_nmi_mask,
3499         .set_nmi_mask = svm_set_nmi_mask,
3500         .enable_nmi_window = enable_nmi_window,
3501         .enable_irq_window = enable_irq_window,
3502         .update_cr8_intercept = update_cr8_intercept,
3503
3504         .set_tss_addr = svm_set_tss_addr,
3505         .get_tdp_level = get_npt_level,
3506         .get_mt_mask = svm_get_mt_mask,
3507
3508         .exit_reasons_str = svm_exit_reasons_str,
3509         .get_lpage_level = svm_get_lpage_level,
3510
3511         .cpuid_update = svm_cpuid_update,
3512
3513         .rdtscp_supported = svm_rdtscp_supported,
3514
3515         .set_supported_cpuid = svm_set_supported_cpuid,
3516
3517         .has_wbinvd_exit = svm_has_wbinvd_exit,
3518 };
3519
3520 static int __init svm_init(void)
3521 {
3522         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3523                         __alignof__(struct vcpu_svm), THIS_MODULE);
3524 }
3525
3526 static void __exit svm_exit(void)
3527 {
3528         kvm_exit();
3529 }
3530
3531 module_init(svm_init)
3532 module_exit(svm_exit)