arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28
  29 #include <asm/desc.h>
  30
  31 #include <asm/virtext.h>
  32
  33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 #define IOPM_ALLOC_ORDER 2
  39 #define MSRPM_ALLOC_ORDER 1
  40
  41 #define DR7_GD_MASK (1 << 13)
  42 #define DR6_BD_MASK (1 << 13)
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT  (1 << 0)
  48 #define SVM_FEATURE_LBRV (1 << 1)
  49 #define SVM_FEATURE_SVML (1 << 2)
  50
  51 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  52
  53 /* Turn on to get debugging output*/
  54 /* #define NESTED_DEBUG */
  55
  56 #ifdef NESTED_DEBUG
  57 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  58 #else
  59 #define nsvm_printk(fmt, args...) do {} while(0)
  60 #endif
  61
  62 /* enable NPT for AMD64 and X86 with PAE */
  63 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  64 static bool npt_enabled = true;
  65 #else
  66 static bool npt_enabled = false;
  67 #endif
  68 static int npt = 1;
  69
  70 module_param(npt, int, S_IRUGO);
  71
  72 static void kvm_reput_irq(struct vcpu_svm *svm);
  73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  74
  75 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
  76 static int nested_svm_vmexit(struct vcpu_svm *svm);
  77 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
  78                              void *arg2, void *opaque);
  79 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
  80                                       bool has_error_code, u32 error_code);
  81
  82 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  83 {
  84         return container_of(vcpu, struct vcpu_svm, vcpu);
  85 }
  86
  87 static inline bool is_nested(struct vcpu_svm *svm)
  88 {
  89         return svm->nested_vmcb;
  90 }
  91
  92 static unsigned long iopm_base;
  93
  94 struct kvm_ldttss_desc {
  95         u16 limit0;
  96         u16 base0;
  97         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  98         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  99         u32 base3;
 100         u32 zero1;
 101 } __attribute__((packed));
 102
 103 struct svm_cpu_data {
 104         int cpu;
 105
 106         u64 asid_generation;
 107         u32 max_asid;
 108         u32 next_asid;
 109         struct kvm_ldttss_desc *tss_desc;
 110
 111         struct page *save_area;
 112 };
 113
 114 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 115 static uint32_t svm_features;
 116
 117 struct svm_init_data {
 118         int cpu;
 119         int r;
 120 };
 121
 122 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 123
 124 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 125 #define MSRS_RANGE_SIZE 2048
 126 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 127
 128 #define MAX_INST_SIZE 15
 129
 130 static inline u32 svm_has(u32 feat)
 131 {
 132         return svm_features & feat;
 133 }
 134
 135 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 136 {
 137         int word_index = __ffs(vcpu->arch.irq_summary);
 138         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 139         int irq = word_index * BITS_PER_LONG + bit_index;
 140
 141         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 142         if (!vcpu->arch.irq_pending[word_index])
 143                 clear_bit(word_index, &vcpu->arch.irq_summary);
 144         return irq;
 145 }
 146
 147 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 148 {
 149         set_bit(irq, vcpu->arch.irq_pending);
 150         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 151 }
 152
 153 static inline void clgi(void)
 154 {
 155         asm volatile (__ex(SVM_CLGI));
 156 }
 157
 158 static inline void stgi(void)
 159 {
 160         asm volatile (__ex(SVM_STGI));
 161 }
 162
 163 static inline void invlpga(unsigned long addr, u32 asid)
 164 {
 165         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 166 }
 167
 168 static inline unsigned long kvm_read_cr2(void)
 169 {
 170         unsigned long cr2;
 171
 172         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 173         return cr2;
 174 }
 175
 176 static inline void kvm_write_cr2(unsigned long val)
 177 {
 178         asm volatile ("mov %0, %%cr2" :: "r" (val));
 179 }
 180
 181 static inline unsigned long read_dr6(void)
 182 {
 183         unsigned long dr6;
 184
 185         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 186         return dr6;
 187 }
 188
 189 static inline void write_dr6(unsigned long val)
 190 {
 191         asm volatile ("mov %0, %%dr6" :: "r" (val));
 192 }
 193
 194 static inline unsigned long read_dr7(void)
 195 {
 196         unsigned long dr7;
 197
 198         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 199         return dr7;
 200 }
 201
 202 static inline void write_dr7(unsigned long val)
 203 {
 204         asm volatile ("mov %0, %%dr7" :: "r" (val));
 205 }
 206
 207 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 208 {
 209         to_svm(vcpu)->asid_generation--;
 210 }
 211
 212 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 213 {
 214         force_new_asid(vcpu);
 215 }
 216
 217 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 218 {
 219         if (!npt_enabled && !(efer & EFER_LMA))
 220                 efer &= ~EFER_LME;
 221
 222         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 223         vcpu->arch.shadow_efer = efer;
 224 }
 225
 226 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 227                                 bool has_error_code, u32 error_code)
 228 {
 229         struct vcpu_svm *svm = to_svm(vcpu);
 230
 231         /* If we are within a nested VM we'd better #VMEXIT and let the
 232            guest handle the exception */
 233         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 234                 return;
 235
 236         svm->vmcb->control.event_inj = nr
 237                 | SVM_EVTINJ_VALID
 238                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 239                 | SVM_EVTINJ_TYPE_EXEPT;
 240         svm->vmcb->control.event_inj_err = error_code;
 241 }
 242
 243 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 244 {
 245         struct vcpu_svm *svm = to_svm(vcpu);
 246
 247         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 248 }
 249
 250 static int is_external_interrupt(u32 info)
 251 {
 252         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 253         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 254 }
 255
 256 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 257 {
 258         struct vcpu_svm *svm = to_svm(vcpu);
 259
 260         if (!svm->next_rip) {
 261                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 262                 return;
 263         }
 264         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 265                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 266                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 267
 268         kvm_rip_write(vcpu, svm->next_rip);
 269         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 270
 271         vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK);
 272 }
 273
 274 static int has_svm(void)
 275 {
 276         const char *msg;
 277
 278         if (!cpu_has_svm(&msg)) {
 279                 printk(KERN_INFO "has_svn: %s\n", msg);
 280                 return 0;
 281         }
 282
 283         return 1;
 284 }
 285
 286 static void svm_hardware_disable(void *garbage)
 287 {
 288         cpu_svm_disable();
 289 }
 290
 291 static void svm_hardware_enable(void *garbage)
 292 {
 293
 294         struct svm_cpu_data *svm_data;
 295         uint64_t efer;
 296         struct desc_ptr gdt_descr;
 297         struct desc_struct *gdt;
 298         int me = raw_smp_processor_id();
 299
 300         if (!has_svm()) {
 301                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 302                 return;
 303         }
 304         svm_data = per_cpu(svm_data, me);
 305
 306         if (!svm_data) {
 307                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 308                        me);
 309                 return;
 310         }
 311
 312         svm_data->asid_generation = 1;
 313         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 314         svm_data->next_asid = svm_data->max_asid + 1;
 315
 316         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 317         gdt = (struct desc_struct *)gdt_descr.address;
 318         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 319
 320         rdmsrl(MSR_EFER, efer);
 321         wrmsrl(MSR_EFER, efer | EFER_SVME);
 322
 323         wrmsrl(MSR_VM_HSAVE_PA,
 324                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 325 }
 326
 327 static void svm_cpu_uninit(int cpu)
 328 {
 329         struct svm_cpu_data *svm_data
 330                 = per_cpu(svm_data, raw_smp_processor_id());
 331
 332         if (!svm_data)
 333                 return;
 334
 335         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 336         __free_page(svm_data->save_area);
 337         kfree(svm_data);
 338 }
 339
 340 static int svm_cpu_init(int cpu)
 341 {
 342         struct svm_cpu_data *svm_data;
 343         int r;
 344
 345         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 346         if (!svm_data)
 347                 return -ENOMEM;
 348         svm_data->cpu = cpu;
 349         svm_data->save_area = alloc_page(GFP_KERNEL);
 350         r = -ENOMEM;
 351         if (!svm_data->save_area)
 352                 goto err_1;
 353
 354         per_cpu(svm_data, cpu) = svm_data;
 355
 356         return 0;
 357
 358 err_1:
 359         kfree(svm_data);
 360         return r;
 361
 362 }
 363
 364 static void set_msr_interception(u32 *msrpm, unsigned msr,
 365                                  int read, int write)
 366 {
 367         int i;
 368
 369         for (i = 0; i < NUM_MSR_MAPS; i++) {
 370                 if (msr >= msrpm_ranges[i] &&
 371                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 372                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 373                                           msrpm_ranges[i]) * 2;
 374
 375                         u32 *base = msrpm + (msr_offset / 32);
 376                         u32 msr_shift = msr_offset % 32;
 377                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 378                         *base = (*base & ~(0x3 << msr_shift)) |
 379                                 (mask << msr_shift);
 380                         return;
 381                 }
 382         }
 383         BUG();
 384 }
 385
 386 static void svm_vcpu_init_msrpm(u32 *msrpm)
 387 {
 388         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 389
 390 #ifdef CONFIG_X86_64
 391         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 392         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 393         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 394         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 395         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 396         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 397 #endif
 398         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 399         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 400         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 401         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 402 }
 403
 404 static void svm_enable_lbrv(struct vcpu_svm *svm)
 405 {
 406         u32 *msrpm = svm->msrpm;
 407
 408         svm->vmcb->control.lbr_ctl = 1;
 409         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 410         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 411         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 412         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 413 }
 414
 415 static void svm_disable_lbrv(struct vcpu_svm *svm)
 416 {
 417         u32 *msrpm = svm->msrpm;
 418
 419         svm->vmcb->control.lbr_ctl = 0;
 420         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 421         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 422         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 423         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 424 }
 425
 426 static __init int svm_hardware_setup(void)
 427 {
 428         int cpu;
 429         struct page *iopm_pages;
 430         void *iopm_va;
 431         int r;
 432
 433         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 434
 435         if (!iopm_pages)
 436                 return -ENOMEM;
 437
 438         iopm_va = page_address(iopm_pages);
 439         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 440         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 441         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 442
 443         if (boot_cpu_has(X86_FEATURE_NX))
 444                 kvm_enable_efer_bits(EFER_NX);
 445
 446         for_each_online_cpu(cpu) {
 447                 r = svm_cpu_init(cpu);
 448                 if (r)
 449                         goto err;
 450         }
 451
 452         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 453
 454         if (!svm_has(SVM_FEATURE_NPT))
 455                 npt_enabled = false;
 456
 457         if (npt_enabled && !npt) {
 458                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 459                 npt_enabled = false;
 460         }
 461
 462         if (npt_enabled) {
 463                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 464                 kvm_enable_tdp();
 465         } else
 466                 kvm_disable_tdp();
 467
 468         return 0;
 469
 470 err:
 471         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 472         iopm_base = 0;
 473         return r;
 474 }
 475
 476 static __exit void svm_hardware_unsetup(void)
 477 {
 478         int cpu;
 479
 480         for_each_online_cpu(cpu)
 481                 svm_cpu_uninit(cpu);
 482
 483         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 484         iopm_base = 0;
 485 }
 486
 487 static void init_seg(struct vmcb_seg *seg)
 488 {
 489         seg->selector = 0;
 490         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 491                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 492         seg->limit = 0xffff;
 493         seg->base = 0;
 494 }
 495
 496 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 497 {
 498         seg->selector = 0;
 499         seg->attrib = SVM_SELECTOR_P_MASK | type;
 500         seg->limit = 0xffff;
 501         seg->base = 0;
 502 }
 503
 504 static void init_vmcb(struct vcpu_svm *svm)
 505 {
 506         struct vmcb_control_area *control = &svm->vmcb->control;
 507         struct vmcb_save_area *save = &svm->vmcb->save;
 508
 509         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 510                                         INTERCEPT_CR3_MASK |
 511                                         INTERCEPT_CR4_MASK;
 512
 513         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 514                                         INTERCEPT_CR3_MASK |
 515                                         INTERCEPT_CR4_MASK |
 516                                         INTERCEPT_CR8_MASK;
 517
 518         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 519                                         INTERCEPT_DR1_MASK |
 520                                         INTERCEPT_DR2_MASK |
 521                                         INTERCEPT_DR3_MASK;
 522
 523         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 524                                         INTERCEPT_DR1_MASK |
 525                                         INTERCEPT_DR2_MASK |
 526                                         INTERCEPT_DR3_MASK |
 527                                         INTERCEPT_DR5_MASK |
 528                                         INTERCEPT_DR7_MASK;
 529
 530         control->intercept_exceptions = (1 << PF_VECTOR) |
 531                                         (1 << UD_VECTOR) |
 532                                         (1 << MC_VECTOR);
 533
 534
 535         control->intercept =    (1ULL << INTERCEPT_INTR) |
 536                                 (1ULL << INTERCEPT_NMI) |
 537                                 (1ULL << INTERCEPT_SMI) |
 538                                 (1ULL << INTERCEPT_CPUID) |
 539                                 (1ULL << INTERCEPT_INVD) |
 540                                 (1ULL << INTERCEPT_HLT) |
 541                                 (1ULL << INTERCEPT_INVLPG) |
 542                                 (1ULL << INTERCEPT_INVLPGA) |
 543                                 (1ULL << INTERCEPT_IOIO_PROT) |
 544                                 (1ULL << INTERCEPT_MSR_PROT) |
 545                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 546                                 (1ULL << INTERCEPT_SHUTDOWN) |
 547                                 (1ULL << INTERCEPT_VMRUN) |
 548                                 (1ULL << INTERCEPT_VMMCALL) |
 549                                 (1ULL << INTERCEPT_VMLOAD) |
 550                                 (1ULL << INTERCEPT_VMSAVE) |
 551                                 (1ULL << INTERCEPT_STGI) |
 552                                 (1ULL << INTERCEPT_CLGI) |
 553                                 (1ULL << INTERCEPT_SKINIT) |
 554                                 (1ULL << INTERCEPT_WBINVD) |
 555                                 (1ULL << INTERCEPT_MONITOR) |
 556                                 (1ULL << INTERCEPT_MWAIT);
 557
 558         control->iopm_base_pa = iopm_base;
 559         control->msrpm_base_pa = __pa(svm->msrpm);
 560         control->tsc_offset = 0;
 561         control->int_ctl = V_INTR_MASKING_MASK;
 562
 563         init_seg(&save->es);
 564         init_seg(&save->ss);
 565         init_seg(&save->ds);
 566         init_seg(&save->fs);
 567         init_seg(&save->gs);
 568
 569         save->cs.selector = 0xf000;
 570         /* Executable/Readable Code Segment */
 571         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 572                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 573         save->cs.limit = 0xffff;
 574         /*
 575          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 576          * be consistent with it.
 577          *
 578          * Replace when we have real mode working for vmx.
 579          */
 580         save->cs.base = 0xf0000;
 581
 582         save->gdtr.limit = 0xffff;
 583         save->idtr.limit = 0xffff;
 584
 585         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 586         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 587
 588         save->efer = EFER_SVME;
 589         save->dr6 = 0xffff0ff0;
 590         save->dr7 = 0x400;
 591         save->rflags = 2;
 592         save->rip = 0x0000fff0;
 593         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 594
 595         /*
 596          * cr0 val on cpu init should be 0x60000010, we enable cpu
 597          * cache by default. the orderly way is to enable cache in bios.
 598          */
 599         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 600         save->cr4 = X86_CR4_PAE;
 601         /* rdx = ?? */
 602
 603         if (npt_enabled) {
 604                 /* Setup VMCB for Nested Paging */
 605                 control->nested_ctl = 1;
 606                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 607                                         (1ULL << INTERCEPT_INVLPG));
 608                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 609                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 610                                                 INTERCEPT_CR3_MASK);
 611                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 612                                                  INTERCEPT_CR3_MASK);
 613                 save->g_pat = 0x0007040600070406ULL;
 614                 /* enable caching because the QEMU Bios doesn't enable it */
 615                 save->cr0 = X86_CR0_ET;
 616                 save->cr3 = 0;
 617                 save->cr4 = 0;
 618         }
 619         force_new_asid(&svm->vcpu);
 620
 621         svm->nested_vmcb = 0;
 622         svm->vcpu.arch.hflags = HF_GIF_MASK;
 623 }
 624
 625 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 626 {
 627         struct vcpu_svm *svm = to_svm(vcpu);
 628
 629         init_vmcb(svm);
 630
 631         if (vcpu->vcpu_id != 0) {
 632                 kvm_rip_write(vcpu, 0);
 633                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 634                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 635         }
 636         vcpu->arch.regs_avail = ~0;
 637         vcpu->arch.regs_dirty = ~0;
 638
 639         return 0;
 640 }
 641
 642 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 643 {
 644         struct vcpu_svm *svm;
 645         struct page *page;
 646         struct page *msrpm_pages;
 647         struct page *hsave_page;
 648         struct page *nested_msrpm_pages;
 649         int err;
 650
 651         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 652         if (!svm) {
 653                 err = -ENOMEM;
 654                 goto out;
 655         }
 656
 657         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 658         if (err)
 659                 goto free_svm;
 660
 661         page = alloc_page(GFP_KERNEL);
 662         if (!page) {
 663                 err = -ENOMEM;
 664                 goto uninit;
 665         }
 666
 667         err = -ENOMEM;
 668         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 669         if (!msrpm_pages)
 670                 goto uninit;
 671
 672         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 673         if (!nested_msrpm_pages)
 674                 goto uninit;
 675
 676         svm->msrpm = page_address(msrpm_pages);
 677         svm_vcpu_init_msrpm(svm->msrpm);
 678
 679         hsave_page = alloc_page(GFP_KERNEL);
 680         if (!hsave_page)
 681                 goto uninit;
 682         svm->hsave = page_address(hsave_page);
 683
 684         svm->nested_msrpm = page_address(nested_msrpm_pages);
 685
 686         svm->vmcb = page_address(page);
 687         clear_page(svm->vmcb);
 688         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 689         svm->asid_generation = 0;
 690         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 691         init_vmcb(svm);
 692
 693         fx_init(&svm->vcpu);
 694         svm->vcpu.fpu_active = 1;
 695         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 696         if (svm->vcpu.vcpu_id == 0)
 697                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 698
 699         return &svm->vcpu;
 700
 701 uninit:
 702         kvm_vcpu_uninit(&svm->vcpu);
 703 free_svm:
 704         kmem_cache_free(kvm_vcpu_cache, svm);
 705 out:
 706         return ERR_PTR(err);
 707 }
 708
 709 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 710 {
 711         struct vcpu_svm *svm = to_svm(vcpu);
 712
 713         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 714         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 715         __free_page(virt_to_page(svm->hsave));
 716         __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
 717         kvm_vcpu_uninit(vcpu);
 718         kmem_cache_free(kvm_vcpu_cache, svm);
 719 }
 720
 721 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 722 {
 723         struct vcpu_svm *svm = to_svm(vcpu);
 724         int i;
 725
 726         if (unlikely(cpu != vcpu->cpu)) {
 727                 u64 tsc_this, delta;
 728
 729                 /*
 730                  * Make sure that the guest sees a monotonically
 731                  * increasing TSC.
 732                  */
 733                 rdtscll(tsc_this);
 734                 delta = vcpu->arch.host_tsc - tsc_this;
 735                 svm->vmcb->control.tsc_offset += delta;
 736                 vcpu->cpu = cpu;
 737                 kvm_migrate_timers(vcpu);
 738         }
 739
 740         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 741                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 742 }
 743
 744 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 745 {
 746         struct vcpu_svm *svm = to_svm(vcpu);
 747         int i;
 748
 749         ++vcpu->stat.host_state_reload;
 750         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 751                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 752
 753         rdtscll(vcpu->arch.host_tsc);
 754 }
 755
 756 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 757 {
 758         return to_svm(vcpu)->vmcb->save.rflags;
 759 }
 760
 761 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 762 {
 763         to_svm(vcpu)->vmcb->save.rflags = rflags;
 764 }
 765
 766 static void svm_set_vintr(struct vcpu_svm *svm)
 767 {
 768         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 769 }
 770
 771 static void svm_clear_vintr(struct vcpu_svm *svm)
 772 {
 773         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 774 }
 775
 776 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 777 {
 778         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 779
 780         switch (seg) {
 781         case VCPU_SREG_CS: return &save->cs;
 782         case VCPU_SREG_DS: return &save->ds;
 783         case VCPU_SREG_ES: return &save->es;
 784         case VCPU_SREG_FS: return &save->fs;
 785         case VCPU_SREG_GS: return &save->gs;
 786         case VCPU_SREG_SS: return &save->ss;
 787         case VCPU_SREG_TR: return &save->tr;
 788         case VCPU_SREG_LDTR: return &save->ldtr;
 789         }
 790         BUG();
 791         return NULL;
 792 }
 793
 794 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 795 {
 796         struct vmcb_seg *s = svm_seg(vcpu, seg);
 797
 798         return s->base;
 799 }
 800
 801 static void svm_get_segment(struct kvm_vcpu *vcpu,
 802                             struct kvm_segment *var, int seg)
 803 {
 804         struct vmcb_seg *s = svm_seg(vcpu, seg);
 805
 806         var->base = s->base;
 807         var->limit = s->limit;
 808         var->selector = s->selector;
 809         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 810         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 811         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 812         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 813         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 814         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 815         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 816         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 817
 818         /*
 819          * SVM always stores 0 for the 'G' bit in the CS selector in
 820          * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 821          * Intel's VMENTRY has a check on the 'G' bit.
 822          */
 823         if (seg == VCPU_SREG_CS)
 824                 var->g = s->limit > 0xfffff;
 825
 826         /*
 827          * Work around a bug where the busy flag in the tr selector
 828          * isn't exposed
 829          */
 830         if (seg == VCPU_SREG_TR)
 831                 var->type |= 0x2;
 832
 833         var->unusable = !var->present;
 834 }
 835
 836 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 837 {
 838         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 839
 840         return save->cpl;
 841 }
 842
 843 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 844 {
 845         struct vcpu_svm *svm = to_svm(vcpu);
 846
 847         dt->limit = svm->vmcb->save.idtr.limit;
 848         dt->base = svm->vmcb->save.idtr.base;
 849 }
 850
 851 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 852 {
 853         struct vcpu_svm *svm = to_svm(vcpu);
 854
 855         svm->vmcb->save.idtr.limit = dt->limit;
 856         svm->vmcb->save.idtr.base = dt->base ;
 857 }
 858
 859 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 860 {
 861         struct vcpu_svm *svm = to_svm(vcpu);
 862
 863         dt->limit = svm->vmcb->save.gdtr.limit;
 864         dt->base = svm->vmcb->save.gdtr.base;
 865 }
 866
 867 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 868 {
 869         struct vcpu_svm *svm = to_svm(vcpu);
 870
 871         svm->vmcb->save.gdtr.limit = dt->limit;
 872         svm->vmcb->save.gdtr.base = dt->base ;
 873 }
 874
 875 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 876 {
 877 }
 878
 879 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 880 {
 881         struct vcpu_svm *svm = to_svm(vcpu);
 882
 883 #ifdef CONFIG_X86_64
 884         if (vcpu->arch.shadow_efer & EFER_LME) {
 885                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 886                         vcpu->arch.shadow_efer |= EFER_LMA;
 887                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 888                 }
 889
 890                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 891                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 892                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 893                 }
 894         }
 895 #endif
 896         if (npt_enabled)
 897                 goto set;
 898
 899         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 900                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 901                 vcpu->fpu_active = 1;
 902         }
 903
 904         vcpu->arch.cr0 = cr0;
 905         cr0 |= X86_CR0_PG | X86_CR0_WP;
 906         if (!vcpu->fpu_active) {
 907                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 908                 cr0 |= X86_CR0_TS;
 909         }
 910 set:
 911         /*
 912          * re-enable caching here because the QEMU bios
 913          * does not do it - this results in some delay at
 914          * reboot
 915          */
 916         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 917         svm->vmcb->save.cr0 = cr0;
 918 }
 919
 920 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 921 {
 922         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 923         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 924
 925         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 926                 force_new_asid(vcpu);
 927
 928         vcpu->arch.cr4 = cr4;
 929         if (!npt_enabled)
 930                 cr4 |= X86_CR4_PAE;
 931         cr4 |= host_cr4_mce;
 932         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 933 }
 934
 935 static void svm_set_segment(struct kvm_vcpu *vcpu,
 936                             struct kvm_segment *var, int seg)
 937 {
 938         struct vcpu_svm *svm = to_svm(vcpu);
 939         struct vmcb_seg *s = svm_seg(vcpu, seg);
 940
 941         s->base = var->base;
 942         s->limit = var->limit;
 943         s->selector = var->selector;
 944         if (var->unusable)
 945                 s->attrib = 0;
 946         else {
 947                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 948                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 949                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 950                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 951                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 952                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 953                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 954                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 955         }
 956         if (seg == VCPU_SREG_CS)
 957                 svm->vmcb->save.cpl
 958                         = (svm->vmcb->save.cs.attrib
 959                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 960
 961 }
 962
 963 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 964 {
 965         return -EOPNOTSUPP;
 966 }
 967
 968 static int svm_get_irq(struct kvm_vcpu *vcpu)
 969 {
 970         struct vcpu_svm *svm = to_svm(vcpu);
 971         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 972
 973         if (is_external_interrupt(exit_int_info))
 974                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 975         return -1;
 976 }
 977
 978 static void load_host_msrs(struct kvm_vcpu *vcpu)
 979 {
 980 #ifdef CONFIG_X86_64
 981         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 982 #endif
 983 }
 984
 985 static void save_host_msrs(struct kvm_vcpu *vcpu)
 986 {
 987 #ifdef CONFIG_X86_64
 988         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 989 #endif
 990 }
 991
 992 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 993 {
 994         if (svm_data->next_asid > svm_data->max_asid) {
 995                 ++svm_data->asid_generation;
 996                 svm_data->next_asid = 1;
 997                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 998         }
 999
1000         svm->vcpu.cpu = svm_data->cpu;
1001         svm->asid_generation = svm_data->asid_generation;
1002         svm->vmcb->control.asid = svm_data->next_asid++;
1003 }
1004
1005 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1006 {
1007         unsigned long val = to_svm(vcpu)->db_regs[dr];
1008         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1009         return val;
1010 }
1011
1012 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1013                        int *exception)
1014 {
1015         struct vcpu_svm *svm = to_svm(vcpu);
1016
1017         *exception = 0;
1018
1019         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
1020                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
1021                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
1022                 *exception = DB_VECTOR;
1023                 return;
1024         }
1025
1026         switch (dr) {
1027         case 0 ... 3:
1028                 svm->db_regs[dr] = value;
1029                 return;
1030         case 4 ... 5:
1031                 if (vcpu->arch.cr4 & X86_CR4_DE) {
1032                         *exception = UD_VECTOR;
1033                         return;
1034                 }
1035         case 7: {
1036                 if (value & ~((1ULL << 32) - 1)) {
1037                         *exception = GP_VECTOR;
1038                         return;
1039                 }
1040                 svm->vmcb->save.dr7 = value;
1041                 return;
1042         }
1043         default:
1044                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1045                        __func__, dr);
1046                 *exception = UD_VECTOR;
1047                 return;
1048         }
1049 }
1050
1051 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1052 {
1053         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1054         struct kvm *kvm = svm->vcpu.kvm;
1055         u64 fault_address;
1056         u32 error_code;
1057         bool event_injection = false;
1058
1059         if (!irqchip_in_kernel(kvm) &&
1060             is_external_interrupt(exit_int_info)) {
1061                 event_injection = true;
1062                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1063         }
1064
1065         fault_address  = svm->vmcb->control.exit_info_2;
1066         error_code = svm->vmcb->control.exit_info_1;
1067
1068         if (!npt_enabled)
1069                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1070                             (u32)fault_address, (u32)(fault_address >> 32),
1071                             handler);
1072         else
1073                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1074                             (u32)fault_address, (u32)(fault_address >> 32),
1075                             handler);
1076         /*
1077          * FIXME: Tis shouldn't be necessary here, but there is a flush
1078          * missing in the MMU code. Until we find this bug, flush the
1079          * complete TLB here on an NPF
1080          */
1081         if (npt_enabled)
1082                 svm_flush_tlb(&svm->vcpu);
1083
1084         if (!npt_enabled && event_injection)
1085                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1086         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1087 }
1088
1089 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1090 {
1091         int er;
1092
1093         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1094         if (er != EMULATE_DONE)
1095                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1096         return 1;
1097 }
1098
1099 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1100 {
1101         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1102         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1103                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1104         svm->vcpu.fpu_active = 1;
1105
1106         return 1;
1107 }
1108
1109 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1110 {
1111         /*
1112          * On an #MC intercept the MCE handler is not called automatically in
1113          * the host. So do it by hand here.
1114          */
1115         asm volatile (
1116                 "int $0x12\n");
1117         /* not sure if we ever come back to this point */
1118
1119         return 1;
1120 }
1121
1122 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1123 {
1124         /*
1125          * VMCB is undefined after a SHUTDOWN intercept
1126          * so reinitialize it.
1127          */
1128         clear_page(svm->vmcb);
1129         init_vmcb(svm);
1130
1131         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1132         return 0;
1133 }
1134
1135 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1136 {
1137         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1138         int size, down, in, string, rep;
1139         unsigned port;
1140
1141         ++svm->vcpu.stat.io_exits;
1142
1143         svm->next_rip = svm->vmcb->control.exit_info_2;
1144
1145         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1146
1147         if (string) {
1148                 if (emulate_instruction(&svm->vcpu,
1149                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1150                         return 0;
1151                 return 1;
1152         }
1153
1154         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1155         port = io_info >> 16;
1156         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1157         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1158         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1159
1160         skip_emulated_instruction(&svm->vcpu);
1161         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1162 }
1163
1164 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1165 {
1166         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1167         return 1;
1168 }
1169
1170 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1171 {
1172         ++svm->vcpu.stat.irq_exits;
1173         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1174         return 1;
1175 }
1176
1177 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1178 {
1179         return 1;
1180 }
1181
1182 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1183 {
1184         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1185         skip_emulated_instruction(&svm->vcpu);
1186         return kvm_emulate_halt(&svm->vcpu);
1187 }
1188
1189 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1190 {
1191         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1192         skip_emulated_instruction(&svm->vcpu);
1193         kvm_emulate_hypercall(&svm->vcpu);
1194         return 1;
1195 }
1196
1197 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1198 {
1199         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1200             || !is_paging(&svm->vcpu)) {
1201                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1202                 return 1;
1203         }
1204
1205         if (svm->vmcb->save.cpl) {
1206                 kvm_inject_gp(&svm->vcpu, 0);
1207                 return 1;
1208         }
1209
1210        return 0;
1211 }
1212
1213 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1214                                       bool has_error_code, u32 error_code)
1215 {
1216         if (is_nested(svm)) {
1217                 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1218                 svm->vmcb->control.exit_code_hi = 0;
1219                 svm->vmcb->control.exit_info_1 = error_code;
1220                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1221                 if (nested_svm_exit_handled(svm, false)) {
1222                         nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1223
1224                         nested_svm_vmexit(svm);
1225                         return 1;
1226                 }
1227         }
1228
1229         return 0;
1230 }
1231
1232 static inline int nested_svm_intr(struct vcpu_svm *svm)
1233 {
1234         if (is_nested(svm)) {
1235                 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1236                         return 0;
1237
1238                 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1239                         return 0;
1240
1241                 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1242
1243                 if (nested_svm_exit_handled(svm, false)) {
1244                         nsvm_printk("VMexit -> INTR\n");
1245                         nested_svm_vmexit(svm);
1246                         return 1;
1247                 }
1248         }
1249
1250         return 0;
1251 }
1252
1253 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1254 {
1255         struct page *page;
1256
1257         down_read(&current->mm->mmap_sem);
1258         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1259         up_read(&current->mm->mmap_sem);
1260
1261         if (is_error_page(page)) {
1262                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1263                        __func__, gpa);
1264                 kvm_release_page_clean(page);
1265                 kvm_inject_gp(&svm->vcpu, 0);
1266                 return NULL;
1267         }
1268         return page;
1269 }
1270
1271 static int nested_svm_do(struct vcpu_svm *svm,
1272                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1273                          int (*handler)(struct vcpu_svm *svm,
1274                                         void *arg1,
1275                                         void *arg2,
1276                                         void *opaque))
1277 {
1278         struct page *arg1_page;
1279         struct page *arg2_page = NULL;
1280         void *arg1;
1281         void *arg2 = NULL;
1282         int retval;
1283
1284         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1285         if(arg1_page == NULL)
1286                 return 1;
1287
1288         if (arg2_gpa) {
1289                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1290                 if(arg2_page == NULL) {
1291                         kvm_release_page_clean(arg1_page);
1292                         return 1;
1293                 }
1294         }
1295
1296         arg1 = kmap_atomic(arg1_page, KM_USER0);
1297         if (arg2_gpa)
1298                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1299
1300         retval = handler(svm, arg1, arg2, opaque);
1301
1302         kunmap_atomic(arg1, KM_USER0);
1303         if (arg2_gpa)
1304                 kunmap_atomic(arg2, KM_USER1);
1305
1306         kvm_release_page_dirty(arg1_page);
1307         if (arg2_gpa)
1308                 kvm_release_page_dirty(arg2_page);
1309
1310         return retval;
1311 }
1312
1313 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1314                                         void *arg1,
1315                                         void *arg2,
1316                                         void *opaque)
1317 {
1318         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1319         bool kvm_overrides = *(bool *)opaque;
1320         u32 exit_code = svm->vmcb->control.exit_code;
1321
1322         if (kvm_overrides) {
1323                 switch (exit_code) {
1324                 case SVM_EXIT_INTR:
1325                 case SVM_EXIT_NMI:
1326                         return 0;
1327                 /* For now we are always handling NPFs when using them */
1328                 case SVM_EXIT_NPF:
1329                         if (npt_enabled)
1330                                 return 0;
1331                         break;
1332                 /* When we're shadowing, trap PFs */
1333                 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1334                         if (!npt_enabled)
1335                                 return 0;
1336                         break;
1337                 default:
1338                         break;
1339                 }
1340         }
1341
1342         switch (exit_code) {
1343         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1344                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1345                 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1346                         return 1;
1347                 break;
1348         }
1349         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1350                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1351                 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1352                         return 1;
1353                 break;
1354         }
1355         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1356                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1357                 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1358                         return 1;
1359                 break;
1360         }
1361         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1362                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1363                 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1364                         return 1;
1365                 break;
1366         }
1367         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1368                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1369                 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1370                         return 1;
1371                 break;
1372         }
1373         default: {
1374                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1375                 nsvm_printk("exit code: 0x%x\n", exit_code);
1376                 if (nested_vmcb->control.intercept & exit_bits)
1377                         return 1;
1378         }
1379         }
1380
1381         return 0;
1382 }
1383
1384 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1385                                        void *arg1, void *arg2,
1386                                        void *opaque)
1387 {
1388         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1389         u8 *msrpm = (u8 *)arg2;
1390         u32 t0, t1;
1391         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1392         u32 param = svm->vmcb->control.exit_info_1 & 1;
1393
1394         if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1395                 return 0;
1396
1397         switch(msr) {
1398         case 0 ... 0x1fff:
1399                 t0 = (msr * 2) % 8;
1400                 t1 = msr / 8;
1401                 break;
1402         case 0xc0000000 ... 0xc0001fff:
1403                 t0 = (8192 + msr - 0xc0000000) * 2;
1404                 t1 = (t0 / 8);
1405                 t0 %= 8;
1406                 break;
1407         case 0xc0010000 ... 0xc0011fff:
1408                 t0 = (16384 + msr - 0xc0010000) * 2;
1409                 t1 = (t0 / 8);
1410                 t0 %= 8;
1411                 break;
1412         default:
1413                 return 1;
1414                 break;
1415         }
1416         if (msrpm[t1] & ((1 << param) << t0))
1417                 return 1;
1418
1419         return 0;
1420 }
1421
1422 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1423 {
1424         bool k = kvm_override;
1425
1426         switch (svm->vmcb->control.exit_code) {
1427         case SVM_EXIT_MSR:
1428                 return nested_svm_do(svm, svm->nested_vmcb,
1429                                      svm->nested_vmcb_msrpm, NULL,
1430                                      nested_svm_exit_handled_msr);
1431         default: break;
1432         }
1433
1434         return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1435                              nested_svm_exit_handled_real);
1436 }
1437
1438 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1439                                   void *arg2, void *opaque)
1440 {
1441         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1442         struct vmcb *hsave = svm->hsave;
1443         u64 nested_save[] = { nested_vmcb->save.cr0,
1444                               nested_vmcb->save.cr3,
1445                               nested_vmcb->save.cr4,
1446                               nested_vmcb->save.efer,
1447                               nested_vmcb->control.intercept_cr_read,
1448                               nested_vmcb->control.intercept_cr_write,
1449                               nested_vmcb->control.intercept_dr_read,
1450                               nested_vmcb->control.intercept_dr_write,
1451                               nested_vmcb->control.intercept_exceptions,
1452                               nested_vmcb->control.intercept,
1453                               nested_vmcb->control.msrpm_base_pa,
1454                               nested_vmcb->control.iopm_base_pa,
1455                               nested_vmcb->control.tsc_offset };
1456
1457         /* Give the current vmcb to the guest */
1458         memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1459         nested_vmcb->save.cr0 = nested_save[0];
1460         if (!npt_enabled)
1461                 nested_vmcb->save.cr3 = nested_save[1];
1462         nested_vmcb->save.cr4 = nested_save[2];
1463         nested_vmcb->save.efer = nested_save[3];
1464         nested_vmcb->control.intercept_cr_read = nested_save[4];
1465         nested_vmcb->control.intercept_cr_write = nested_save[5];
1466         nested_vmcb->control.intercept_dr_read = nested_save[6];
1467         nested_vmcb->control.intercept_dr_write = nested_save[7];
1468         nested_vmcb->control.intercept_exceptions = nested_save[8];
1469         nested_vmcb->control.intercept = nested_save[9];
1470         nested_vmcb->control.msrpm_base_pa = nested_save[10];
1471         nested_vmcb->control.iopm_base_pa = nested_save[11];
1472         nested_vmcb->control.tsc_offset = nested_save[12];
1473
1474         /* We always set V_INTR_MASKING and remember the old value in hflags */
1475         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1476                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1477
1478         if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1479             (nested_vmcb->control.int_vector)) {
1480                 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1481                                 nested_vmcb->control.int_vector);
1482         }
1483
1484         /* Restore the original control entries */
1485         svm->vmcb->control = hsave->control;
1486
1487         /* Kill any pending exceptions */
1488         if (svm->vcpu.arch.exception.pending == true)
1489                 nsvm_printk("WARNING: Pending Exception\n");
1490         svm->vcpu.arch.exception.pending = false;
1491
1492         /* Restore selected save entries */
1493         svm->vmcb->save.es = hsave->save.es;
1494         svm->vmcb->save.cs = hsave->save.cs;
1495         svm->vmcb->save.ss = hsave->save.ss;
1496         svm->vmcb->save.ds = hsave->save.ds;
1497         svm->vmcb->save.gdtr = hsave->save.gdtr;
1498         svm->vmcb->save.idtr = hsave->save.idtr;
1499         svm->vmcb->save.rflags = hsave->save.rflags;
1500         svm_set_efer(&svm->vcpu, hsave->save.efer);
1501         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1502         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1503         if (npt_enabled) {
1504                 svm->vmcb->save.cr3 = hsave->save.cr3;
1505                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1506         } else {
1507                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1508         }
1509         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1510         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1511         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1512         svm->vmcb->save.dr7 = 0;
1513         svm->vmcb->save.cpl = 0;
1514         svm->vmcb->control.exit_int_info = 0;
1515
1516         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1517         /* Exit nested SVM mode */
1518         svm->nested_vmcb = 0;
1519
1520         return 0;
1521 }
1522
1523 static int nested_svm_vmexit(struct vcpu_svm *svm)
1524 {
1525         nsvm_printk("VMexit\n");
1526         if (nested_svm_do(svm, svm->nested_vmcb, 0,
1527                           NULL, nested_svm_vmexit_real))
1528                 return 1;
1529
1530         kvm_mmu_reset_context(&svm->vcpu);
1531         kvm_mmu_load(&svm->vcpu);
1532
1533         return 0;
1534 }
1535
1536 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1537                                   void *arg2, void *opaque)
1538 {
1539         int i;
1540         u32 *nested_msrpm = (u32*)arg1;
1541         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1542                 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1543         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1544
1545         return 0;
1546 }
1547
1548 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1549                             void *arg2, void *opaque)
1550 {
1551         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1552         struct vmcb *hsave = svm->hsave;
1553
1554         /* nested_vmcb is our indicator if nested SVM is activated */
1555         svm->nested_vmcb = svm->vmcb->save.rax;
1556
1557         /* Clear internal status */
1558         svm->vcpu.arch.exception.pending = false;
1559
1560         /* Save the old vmcb, so we don't need to pick what we save, but
1561            can restore everything when a VMEXIT occurs */
1562         memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1563         /* We need to remember the original CR3 in the SPT case */
1564         if (!npt_enabled)
1565                 hsave->save.cr3 = svm->vcpu.arch.cr3;
1566         hsave->save.cr4 = svm->vcpu.arch.cr4;
1567         hsave->save.rip = svm->next_rip;
1568
1569         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1570                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1571         else
1572                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1573
1574         /* Load the nested guest state */
1575         svm->vmcb->save.es = nested_vmcb->save.es;
1576         svm->vmcb->save.cs = nested_vmcb->save.cs;
1577         svm->vmcb->save.ss = nested_vmcb->save.ss;
1578         svm->vmcb->save.ds = nested_vmcb->save.ds;
1579         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1580         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1581         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1582         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1583         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1584         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1585         if (npt_enabled) {
1586                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1587                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1588         } else {
1589                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1590                 kvm_mmu_reset_context(&svm->vcpu);
1591         }
1592         svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1593         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1594         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1595         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1596         /* In case we don't even reach vcpu_run, the fields are not updated */
1597         svm->vmcb->save.rax = nested_vmcb->save.rax;
1598         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1599         svm->vmcb->save.rip = nested_vmcb->save.rip;
1600         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1601         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1602         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1603
1604         /* We don't want a nested guest to be more powerful than the guest,
1605            so all intercepts are ORed */
1606         svm->vmcb->control.intercept_cr_read |=
1607                 nested_vmcb->control.intercept_cr_read;
1608         svm->vmcb->control.intercept_cr_write |=
1609                 nested_vmcb->control.intercept_cr_write;
1610         svm->vmcb->control.intercept_dr_read |=
1611                 nested_vmcb->control.intercept_dr_read;
1612         svm->vmcb->control.intercept_dr_write |=
1613                 nested_vmcb->control.intercept_dr_write;
1614         svm->vmcb->control.intercept_exceptions |=
1615                 nested_vmcb->control.intercept_exceptions;
1616
1617         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1618
1619         svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1620
1621         force_new_asid(&svm->vcpu);
1622         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1623         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1624         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1625         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1626                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1627                                 nested_vmcb->control.int_ctl);
1628         }
1629         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1630                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1631         else
1632                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1633
1634         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1635                         nested_vmcb->control.exit_int_info,
1636                         nested_vmcb->control.int_state);
1637
1638         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1639         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1640         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1641         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1642                 nsvm_printk("Injecting Event: 0x%x\n",
1643                                 nested_vmcb->control.event_inj);
1644         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1645         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1646
1647         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1648
1649         return 0;
1650 }
1651
1652 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1653 {
1654         to_vmcb->save.fs = from_vmcb->save.fs;
1655         to_vmcb->save.gs = from_vmcb->save.gs;
1656         to_vmcb->save.tr = from_vmcb->save.tr;
1657         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1658         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1659         to_vmcb->save.star = from_vmcb->save.star;
1660         to_vmcb->save.lstar = from_vmcb->save.lstar;
1661         to_vmcb->save.cstar = from_vmcb->save.cstar;
1662         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1663         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1664         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1665         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1666
1667         return 1;
1668 }
1669
1670 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1671                              void *arg2, void *opaque)
1672 {
1673         return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1674 }
1675
1676 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1677                              void *arg2, void *opaque)
1678 {
1679         return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1680 }
1681
1682 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1683 {
1684         if (nested_svm_check_permissions(svm))
1685                 return 1;
1686
1687         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1688         skip_emulated_instruction(&svm->vcpu);
1689
1690         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1691
1692         return 1;
1693 }
1694
1695 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1696 {
1697         if (nested_svm_check_permissions(svm))
1698                 return 1;
1699
1700         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1701         skip_emulated_instruction(&svm->vcpu);
1702
1703         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1704
1705         return 1;
1706 }
1707
1708 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1709 {
1710         nsvm_printk("VMrun\n");
1711         if (nested_svm_check_permissions(svm))
1712                 return 1;
1713
1714         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1715         skip_emulated_instruction(&svm->vcpu);
1716
1717         if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1718                           NULL, nested_svm_vmrun))
1719                 return 1;
1720
1721         if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1722                       NULL, nested_svm_vmrun_msrpm))
1723                 return 1;
1724
1725         return 1;
1726 }
1727
1728 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1729 {
1730         if (nested_svm_check_permissions(svm))
1731                 return 1;
1732
1733         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1734         skip_emulated_instruction(&svm->vcpu);
1735
1736         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1737
1738         return 1;
1739 }
1740
1741 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1742 {
1743         if (nested_svm_check_permissions(svm))
1744                 return 1;
1745
1746         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1747         skip_emulated_instruction(&svm->vcpu);
1748
1749         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1750
1751         /* After a CLGI no interrupts should come */
1752         svm_clear_vintr(svm);
1753         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1754
1755         return 1;
1756 }
1757
1758 static int invalid_op_interception(struct vcpu_svm *svm,
1759                                    struct kvm_run *kvm_run)
1760 {
1761         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1762         return 1;
1763 }
1764
1765 static int task_switch_interception(struct vcpu_svm *svm,
1766                                     struct kvm_run *kvm_run)
1767 {
1768         u16 tss_selector;
1769
1770         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1771         if (svm->vmcb->control.exit_info_2 &
1772             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1773                 return kvm_task_switch(&svm->vcpu, tss_selector,
1774                                        TASK_SWITCH_IRET);
1775         if (svm->vmcb->control.exit_info_2 &
1776             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1777                 return kvm_task_switch(&svm->vcpu, tss_selector,
1778                                        TASK_SWITCH_JMP);
1779         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1780 }
1781
1782 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1783 {
1784         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1785         kvm_emulate_cpuid(&svm->vcpu);
1786         return 1;
1787 }
1788
1789 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1790 {
1791         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1792                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1793         return 1;
1794 }
1795
1796 static int emulate_on_interception(struct vcpu_svm *svm,
1797                                    struct kvm_run *kvm_run)
1798 {
1799         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1800                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1801         return 1;
1802 }
1803
1804 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1805 {
1806         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1807         if (irqchip_in_kernel(svm->vcpu.kvm))
1808                 return 1;
1809         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1810         return 0;
1811 }
1812
1813 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1814 {
1815         struct vcpu_svm *svm = to_svm(vcpu);
1816
1817         switch (ecx) {
1818         case MSR_IA32_TIME_STAMP_COUNTER: {
1819                 u64 tsc;
1820
1821                 rdtscll(tsc);
1822                 *data = svm->vmcb->control.tsc_offset + tsc;
1823                 break;
1824         }
1825         case MSR_K6_STAR:
1826                 *data = svm->vmcb->save.star;
1827                 break;
1828 #ifdef CONFIG_X86_64
1829         case MSR_LSTAR:
1830                 *data = svm->vmcb->save.lstar;
1831                 break;
1832         case MSR_CSTAR:
1833                 *data = svm->vmcb->save.cstar;
1834                 break;
1835         case MSR_KERNEL_GS_BASE:
1836                 *data = svm->vmcb->save.kernel_gs_base;
1837                 break;
1838         case MSR_SYSCALL_MASK:
1839                 *data = svm->vmcb->save.sfmask;
1840                 break;
1841 #endif
1842         case MSR_IA32_SYSENTER_CS:
1843                 *data = svm->vmcb->save.sysenter_cs;
1844                 break;
1845         case MSR_IA32_SYSENTER_EIP:
1846                 *data = svm->vmcb->save.sysenter_eip;
1847                 break;
1848         case MSR_IA32_SYSENTER_ESP:
1849                 *data = svm->vmcb->save.sysenter_esp;
1850                 break;
1851         /* Nobody will change the following 5 values in the VMCB so
1852            we can safely return them on rdmsr. They will always be 0
1853            until LBRV is implemented. */
1854         case MSR_IA32_DEBUGCTLMSR:
1855                 *data = svm->vmcb->save.dbgctl;
1856                 break;
1857         case MSR_IA32_LASTBRANCHFROMIP:
1858                 *data = svm->vmcb->save.br_from;
1859                 break;
1860         case MSR_IA32_LASTBRANCHTOIP:
1861                 *data = svm->vmcb->save.br_to;
1862                 break;
1863         case MSR_IA32_LASTINTFROMIP:
1864                 *data = svm->vmcb->save.last_excp_from;
1865                 break;
1866         case MSR_IA32_LASTINTTOIP:
1867                 *data = svm->vmcb->save.last_excp_to;
1868                 break;
1869         case MSR_VM_HSAVE_PA:
1870                 *data = svm->hsave_msr;
1871                 break;
1872         default:
1873                 return kvm_get_msr_common(vcpu, ecx, data);
1874         }
1875         return 0;
1876 }
1877
1878 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1879 {
1880         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1881         u64 data;
1882
1883         if (svm_get_msr(&svm->vcpu, ecx, &data))
1884                 kvm_inject_gp(&svm->vcpu, 0);
1885         else {
1886                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1887                             (u32)(data >> 32), handler);
1888
1889                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1890                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1891                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1892                 skip_emulated_instruction(&svm->vcpu);
1893         }
1894         return 1;
1895 }
1896
1897 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1898 {
1899         struct vcpu_svm *svm = to_svm(vcpu);
1900
1901         switch (ecx) {
1902         case MSR_IA32_TIME_STAMP_COUNTER: {
1903                 u64 tsc;
1904
1905                 rdtscll(tsc);
1906                 svm->vmcb->control.tsc_offset = data - tsc;
1907                 break;
1908         }
1909         case MSR_K6_STAR:
1910                 svm->vmcb->save.star = data;
1911                 break;
1912 #ifdef CONFIG_X86_64
1913         case MSR_LSTAR:
1914                 svm->vmcb->save.lstar = data;
1915                 break;
1916         case MSR_CSTAR:
1917                 svm->vmcb->save.cstar = data;
1918                 break;
1919         case MSR_KERNEL_GS_BASE:
1920                 svm->vmcb->save.kernel_gs_base = data;
1921                 break;
1922         case MSR_SYSCALL_MASK:
1923                 svm->vmcb->save.sfmask = data;
1924                 break;
1925 #endif
1926         case MSR_IA32_SYSENTER_CS:
1927                 svm->vmcb->save.sysenter_cs = data;
1928                 break;
1929         case MSR_IA32_SYSENTER_EIP:
1930                 svm->vmcb->save.sysenter_eip = data;
1931                 break;
1932         case MSR_IA32_SYSENTER_ESP:
1933                 svm->vmcb->save.sysenter_esp = data;
1934                 break;
1935         case MSR_IA32_DEBUGCTLMSR:
1936                 if (!svm_has(SVM_FEATURE_LBRV)) {
1937                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1938                                         __func__, data);
1939                         break;
1940                 }
1941                 if (data & DEBUGCTL_RESERVED_BITS)
1942                         return 1;
1943
1944                 svm->vmcb->save.dbgctl = data;
1945                 if (data & (1ULL<<0))
1946                         svm_enable_lbrv(svm);
1947                 else
1948                         svm_disable_lbrv(svm);
1949                 break;
1950         case MSR_K7_EVNTSEL0:
1951         case MSR_K7_EVNTSEL1:
1952         case MSR_K7_EVNTSEL2:
1953         case MSR_K7_EVNTSEL3:
1954         case MSR_K7_PERFCTR0:
1955         case MSR_K7_PERFCTR1:
1956         case MSR_K7_PERFCTR2:
1957         case MSR_K7_PERFCTR3:
1958                 /*
1959                  * Just discard all writes to the performance counters; this
1960                  * should keep both older linux and windows 64-bit guests
1961                  * happy
1962                  */
1963                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1964
1965                 break;
1966         case MSR_VM_HSAVE_PA:
1967                 svm->hsave_msr = data;
1968                 break;
1969         default:
1970                 return kvm_set_msr_common(vcpu, ecx, data);
1971         }
1972         return 0;
1973 }
1974
1975 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1976 {
1977         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1978         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
1979                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1980
1981         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1982                     handler);
1983
1984         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1985         if (svm_set_msr(&svm->vcpu, ecx, data))
1986                 kvm_inject_gp(&svm->vcpu, 0);
1987         else
1988                 skip_emulated_instruction(&svm->vcpu);
1989         return 1;
1990 }
1991
1992 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1993 {
1994         if (svm->vmcb->control.exit_info_1)
1995                 return wrmsr_interception(svm, kvm_run);
1996         else
1997                 return rdmsr_interception(svm, kvm_run);
1998 }
1999
2000 static int interrupt_window_interception(struct vcpu_svm *svm,
2001                                    struct kvm_run *kvm_run)
2002 {
2003         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2004
2005         svm_clear_vintr(svm);
2006         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2007         /*
2008          * If the user space waits to inject interrupts, exit as soon as
2009          * possible
2010          */
2011         if (kvm_run->request_interrupt_window &&
2012             !svm->vcpu.arch.irq_summary) {
2013                 ++svm->vcpu.stat.irq_window_exits;
2014                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2015                 return 0;
2016         }
2017
2018         return 1;
2019 }
2020
2021 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2022                                       struct kvm_run *kvm_run) = {
2023         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2024         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2025         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2026         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2027         /* for now: */
2028         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2029         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2030         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2031         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2032         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2033         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2034         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2035         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2036         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2037         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2038         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2039         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2040         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2041         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2042         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2043         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2044         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2045         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2046         [SVM_EXIT_INTR]                         = intr_interception,
2047         [SVM_EXIT_NMI]                          = nmi_interception,
2048         [SVM_EXIT_SMI]                          = nop_on_interception,
2049         [SVM_EXIT_INIT]                         = nop_on_interception,
2050         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2051         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2052         [SVM_EXIT_CPUID]                        = cpuid_interception,
2053         [SVM_EXIT_INVD]                         = emulate_on_interception,
2054         [SVM_EXIT_HLT]                          = halt_interception,
2055         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2056         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
2057         [SVM_EXIT_IOIO]                         = io_interception,
2058         [SVM_EXIT_MSR]                          = msr_interception,
2059         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2060         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2061         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2062         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2063         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2064         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2065         [SVM_EXIT_STGI]                         = stgi_interception,
2066         [SVM_EXIT_CLGI]                         = clgi_interception,
2067         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2068         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2069         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2070         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2071         [SVM_EXIT_NPF]                          = pf_interception,
2072 };
2073
2074 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2075 {
2076         struct vcpu_svm *svm = to_svm(vcpu);
2077         u32 exit_code = svm->vmcb->control.exit_code;
2078
2079         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2080                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2081
2082         if (is_nested(svm)) {
2083                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2084                             exit_code, svm->vmcb->control.exit_info_1,
2085                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2086                 if (nested_svm_exit_handled(svm, true)) {
2087                         nested_svm_vmexit(svm);
2088                         nsvm_printk("-> #VMEXIT\n");
2089                         return 1;
2090                 }
2091         }
2092
2093         if (npt_enabled) {
2094                 int mmu_reload = 0;
2095                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2096                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2097                         mmu_reload = 1;
2098                 }
2099                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2100                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2101                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2102                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2103                                 kvm_inject_gp(vcpu, 0);
2104                                 return 1;
2105                         }
2106                 }
2107                 if (mmu_reload) {
2108                         kvm_mmu_reset_context(vcpu);
2109                         kvm_mmu_load(vcpu);
2110                 }
2111         }
2112
2113         kvm_reput_irq(svm);
2114
2115         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2116                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2117                 kvm_run->fail_entry.hardware_entry_failure_reason
2118                         = svm->vmcb->control.exit_code;
2119                 return 0;
2120         }
2121
2122         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2123             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2124             exit_code != SVM_EXIT_NPF)
2125                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2126                        "exit_code 0x%x\n",
2127                        __func__, svm->vmcb->control.exit_int_info,
2128                        exit_code);
2129
2130         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2131             || !svm_exit_handlers[exit_code]) {
2132                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2133                 kvm_run->hw.hardware_exit_reason = exit_code;
2134                 return 0;
2135         }
2136
2137         return svm_exit_handlers[exit_code](svm, kvm_run);
2138 }
2139
2140 static void reload_tss(struct kvm_vcpu *vcpu)
2141 {
2142         int cpu = raw_smp_processor_id();
2143
2144         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2145         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2146         load_TR_desc();
2147 }
2148
2149 static void pre_svm_run(struct vcpu_svm *svm)
2150 {
2151         int cpu = raw_smp_processor_id();
2152
2153         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2154
2155         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2156         if (svm->vcpu.cpu != cpu ||
2157             svm->asid_generation != svm_data->asid_generation)
2158                 new_asid(svm, svm_data);
2159 }
2160
2161
2162 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2163 {
2164         struct vmcb_control_area *control;
2165
2166         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2167
2168         ++svm->vcpu.stat.irq_injections;
2169         control = &svm->vmcb->control;
2170         control->int_vector = irq;
2171         control->int_ctl &= ~V_INTR_PRIO_MASK;
2172         control->int_ctl |= V_IRQ_MASK |
2173                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2174 }
2175
2176 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2177 {
2178         struct vcpu_svm *svm = to_svm(vcpu);
2179
2180         nested_svm_intr(svm);
2181
2182         svm_inject_irq(svm, irq);
2183 }
2184
2185 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
2186 {
2187         struct vcpu_svm *svm = to_svm(vcpu);
2188         struct vmcb *vmcb = svm->vmcb;
2189         int max_irr, tpr;
2190
2191         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
2192                 return;
2193
2194         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2195
2196         max_irr = kvm_lapic_find_highest_irr(vcpu);
2197         if (max_irr == -1)
2198                 return;
2199
2200         tpr = kvm_lapic_get_cr8(vcpu) << 4;
2201
2202         if (tpr >= (max_irr & 0xf0))
2203                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2204 }
2205
2206 static void svm_intr_assist(struct kvm_vcpu *vcpu)
2207 {
2208         struct vcpu_svm *svm = to_svm(vcpu);
2209         struct vmcb *vmcb = svm->vmcb;
2210         int intr_vector = -1;
2211
2212         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
2213             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
2214                 intr_vector = vmcb->control.exit_int_info &
2215                               SVM_EVTINJ_VEC_MASK;
2216                 vmcb->control.exit_int_info = 0;
2217                 svm_inject_irq(svm, intr_vector);
2218                 goto out;
2219         }
2220
2221         if (vmcb->control.int_ctl & V_IRQ_MASK)
2222                 goto out;
2223
2224         if (!kvm_cpu_has_interrupt(vcpu))
2225                 goto out;
2226
2227         if (nested_svm_intr(svm))
2228                 goto out;
2229
2230         if (!(svm->vcpu.arch.hflags & HF_GIF_MASK))
2231                 goto out;
2232
2233         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
2234             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
2235             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
2236                 /* unable to deliver irq, set pending irq */
2237                 svm_set_vintr(svm);
2238                 svm_inject_irq(svm, 0x0);
2239                 goto out;
2240         }
2241         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
2242         intr_vector = kvm_cpu_get_interrupt(vcpu);
2243         svm_inject_irq(svm, intr_vector);
2244 out:
2245         update_cr8_intercept(vcpu);
2246 }
2247
2248 static void kvm_reput_irq(struct vcpu_svm *svm)
2249 {
2250         struct vmcb_control_area *control = &svm->vmcb->control;
2251
2252         if ((control->int_ctl & V_IRQ_MASK)
2253             && !irqchip_in_kernel(svm->vcpu.kvm)) {
2254                 control->int_ctl &= ~V_IRQ_MASK;
2255                 push_irq(&svm->vcpu, control->int_vector);
2256         }
2257
2258         svm->vcpu.arch.interrupt_window_open =
2259                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2260                  (svm->vcpu.arch.hflags & HF_GIF_MASK);
2261 }
2262
2263 static void svm_do_inject_vector(struct vcpu_svm *svm)
2264 {
2265         struct kvm_vcpu *vcpu = &svm->vcpu;
2266         int word_index = __ffs(vcpu->arch.irq_summary);
2267         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2268         int irq = word_index * BITS_PER_LONG + bit_index;
2269
2270         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2271         if (!vcpu->arch.irq_pending[word_index])
2272                 clear_bit(word_index, &vcpu->arch.irq_summary);
2273         svm_inject_irq(svm, irq);
2274 }
2275
2276 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2277                                        struct kvm_run *kvm_run)
2278 {
2279         struct vcpu_svm *svm = to_svm(vcpu);
2280         struct vmcb_control_area *control = &svm->vmcb->control;
2281
2282         if (nested_svm_intr(svm))
2283                 return;
2284
2285         svm->vcpu.arch.interrupt_window_open =
2286                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2287                  (svm->vmcb->save.rflags & X86_EFLAGS_IF) &&
2288                  (svm->vcpu.arch.hflags & HF_GIF_MASK));
2289
2290         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
2291                 /*
2292                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
2293                  */
2294                 svm_do_inject_vector(svm);
2295
2296         /*
2297          * Interrupts blocked.  Wait for unblock.
2298          */
2299         if (!svm->vcpu.arch.interrupt_window_open &&
2300             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
2301                 svm_set_vintr(svm);
2302         else
2303                 svm_clear_vintr(svm);
2304 }
2305
2306 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2307 {
2308         return 0;
2309 }
2310
2311 static void save_db_regs(unsigned long *db_regs)
2312 {
2313         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
2314         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
2315         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
2316         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
2317 }
2318
2319 static void load_db_regs(unsigned long *db_regs)
2320 {
2321         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
2322         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
2323         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
2324         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
2325 }
2326
2327 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2328 {
2329         force_new_asid(vcpu);
2330 }
2331
2332 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2333 {
2334 }
2335
2336 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2337 {
2338         struct vcpu_svm *svm = to_svm(vcpu);
2339
2340         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2341                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2342                 kvm_lapic_set_tpr(vcpu, cr8);
2343         }
2344 }
2345
2346 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2347 {
2348         struct vcpu_svm *svm = to_svm(vcpu);
2349         u64 cr8;
2350
2351         if (!irqchip_in_kernel(vcpu->kvm))
2352                 return;
2353
2354         cr8 = kvm_get_cr8(vcpu);
2355         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2356         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2357 }
2358
2359 #ifdef CONFIG_X86_64
2360 #define R "r"
2361 #else
2362 #define R "e"
2363 #endif
2364
2365 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2366 {
2367         struct vcpu_svm *svm = to_svm(vcpu);
2368         u16 fs_selector;
2369         u16 gs_selector;
2370         u16 ldt_selector;
2371
2372         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2373         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2374         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2375
2376         pre_svm_run(svm);
2377
2378         sync_lapic_to_cr8(vcpu);
2379
2380         save_host_msrs(vcpu);
2381         fs_selector = kvm_read_fs();
2382         gs_selector = kvm_read_gs();
2383         ldt_selector = kvm_read_ldt();
2384         svm->host_cr2 = kvm_read_cr2();
2385         svm->host_dr6 = read_dr6();
2386         svm->host_dr7 = read_dr7();
2387         if (!is_nested(svm))
2388                 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2389         /* required for live migration with NPT */
2390         if (npt_enabled)
2391                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2392
2393         if (svm->vmcb->save.dr7 & 0xff) {
2394                 write_dr7(0);
2395                 save_db_regs(svm->host_db_regs);
2396                 load_db_regs(svm->db_regs);
2397         }
2398
2399         clgi();
2400
2401         local_irq_enable();
2402
2403         asm volatile (
2404                 "push %%"R"bp; \n\t"
2405                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2406                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2407                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2408                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2409                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2410                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2411 #ifdef CONFIG_X86_64
2412                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2413                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2414                 "mov %c[r10](%[svm]), %%r10 \n\t"
2415                 "mov %c[r11](%[svm]), %%r11 \n\t"
2416                 "mov %c[r12](%[svm]), %%r12 \n\t"
2417                 "mov %c[r13](%[svm]), %%r13 \n\t"
2418                 "mov %c[r14](%[svm]), %%r14 \n\t"
2419                 "mov %c[r15](%[svm]), %%r15 \n\t"
2420 #endif
2421
2422                 /* Enter guest mode */
2423                 "push %%"R"ax \n\t"
2424                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2425                 __ex(SVM_VMLOAD) "\n\t"
2426                 __ex(SVM_VMRUN) "\n\t"
2427                 __ex(SVM_VMSAVE) "\n\t"
2428                 "pop %%"R"ax \n\t"
2429
2430                 /* Save guest registers, load host registers */
2431                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2432                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2433                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2434                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2435                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2436                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2437 #ifdef CONFIG_X86_64
2438                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2439                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2440                 "mov %%r10, %c[r10](%[svm]) \n\t"
2441                 "mov %%r11, %c[r11](%[svm]) \n\t"
2442                 "mov %%r12, %c[r12](%[svm]) \n\t"
2443                 "mov %%r13, %c[r13](%[svm]) \n\t"
2444                 "mov %%r14, %c[r14](%[svm]) \n\t"
2445                 "mov %%r15, %c[r15](%[svm]) \n\t"
2446 #endif
2447                 "pop %%"R"bp"
2448                 :
2449                 : [svm]"a"(svm),
2450                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2451                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2452                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2453                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2454                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2455                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2456                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2457 #ifdef CONFIG_X86_64
2458                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2459                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2460                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2461                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2462                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2463                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2464                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2465                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2466 #endif
2467                 : "cc", "memory"
2468                 , R"bx", R"cx", R"dx", R"si", R"di"
2469 #ifdef CONFIG_X86_64
2470                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2471 #endif
2472                 );
2473
2474         if ((svm->vmcb->save.dr7 & 0xff))
2475                 load_db_regs(svm->host_db_regs);
2476
2477         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2478         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2479         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2480         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2481
2482         write_dr6(svm->host_dr6);
2483         write_dr7(svm->host_dr7);
2484         kvm_write_cr2(svm->host_cr2);
2485
2486         kvm_load_fs(fs_selector);
2487         kvm_load_gs(gs_selector);
2488         kvm_load_ldt(ldt_selector);
2489         load_host_msrs(vcpu);
2490
2491         reload_tss(vcpu);
2492
2493         local_irq_disable();
2494
2495         stgi();
2496
2497         sync_cr8_to_lapic(vcpu);
2498
2499         svm->next_rip = 0;
2500 }
2501
2502 #undef R
2503
2504 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2505 {
2506         struct vcpu_svm *svm = to_svm(vcpu);
2507
2508         if (npt_enabled) {
2509                 svm->vmcb->control.nested_cr3 = root;
2510                 force_new_asid(vcpu);
2511                 return;
2512         }
2513
2514         svm->vmcb->save.cr3 = root;
2515         force_new_asid(vcpu);
2516
2517         if (vcpu->fpu_active) {
2518                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2519                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2520                 vcpu->fpu_active = 0;
2521         }
2522 }
2523
2524 static int is_disabled(void)
2525 {
2526         u64 vm_cr;
2527
2528         rdmsrl(MSR_VM_CR, vm_cr);
2529         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2530                 return 1;
2531
2532         return 0;
2533 }
2534
2535 static void
2536 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2537 {
2538         /*
2539          * Patch in the VMMCALL instruction:
2540          */
2541         hypercall[0] = 0x0f;
2542         hypercall[1] = 0x01;
2543         hypercall[2] = 0xd9;
2544 }
2545
2546 static void svm_check_processor_compat(void *rtn)
2547 {
2548         *(int *)rtn = 0;
2549 }
2550
2551 static bool svm_cpu_has_accelerated_tpr(void)
2552 {
2553         return false;
2554 }
2555
2556 static int get_npt_level(void)
2557 {
2558 #ifdef CONFIG_X86_64
2559         return PT64_ROOT_LEVEL;
2560 #else
2561         return PT32E_ROOT_LEVEL;
2562 #endif
2563 }
2564
2565 static int svm_get_mt_mask_shift(void)
2566 {
2567         return 0;
2568 }
2569
2570 static struct kvm_x86_ops svm_x86_ops = {
2571         .cpu_has_kvm_support = has_svm,
2572         .disabled_by_bios = is_disabled,
2573         .hardware_setup = svm_hardware_setup,
2574         .hardware_unsetup = svm_hardware_unsetup,
2575         .check_processor_compatibility = svm_check_processor_compat,
2576         .hardware_enable = svm_hardware_enable,
2577         .hardware_disable = svm_hardware_disable,
2578         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2579
2580         .vcpu_create = svm_create_vcpu,
2581         .vcpu_free = svm_free_vcpu,
2582         .vcpu_reset = svm_vcpu_reset,
2583
2584         .prepare_guest_switch = svm_prepare_guest_switch,
2585         .vcpu_load = svm_vcpu_load,
2586         .vcpu_put = svm_vcpu_put,
2587
2588         .set_guest_debug = svm_guest_debug,
2589         .get_msr = svm_get_msr,
2590         .set_msr = svm_set_msr,
2591         .get_segment_base = svm_get_segment_base,
2592         .get_segment = svm_get_segment,
2593         .set_segment = svm_set_segment,
2594         .get_cpl = svm_get_cpl,
2595         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2596         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2597         .set_cr0 = svm_set_cr0,
2598         .set_cr3 = svm_set_cr3,
2599         .set_cr4 = svm_set_cr4,
2600         .set_efer = svm_set_efer,
2601         .get_idt = svm_get_idt,
2602         .set_idt = svm_set_idt,
2603         .get_gdt = svm_get_gdt,
2604         .set_gdt = svm_set_gdt,
2605         .get_dr = svm_get_dr,
2606         .set_dr = svm_set_dr,
2607         .get_rflags = svm_get_rflags,
2608         .set_rflags = svm_set_rflags,
2609
2610         .tlb_flush = svm_flush_tlb,
2611
2612         .run = svm_vcpu_run,
2613         .handle_exit = handle_exit,
2614         .skip_emulated_instruction = skip_emulated_instruction,
2615         .patch_hypercall = svm_patch_hypercall,
2616         .get_irq = svm_get_irq,
2617         .set_irq = svm_set_irq,
2618         .queue_exception = svm_queue_exception,
2619         .exception_injected = svm_exception_injected,
2620         .inject_pending_irq = svm_intr_assist,
2621         .inject_pending_vectors = do_interrupt_requests,
2622
2623         .set_tss_addr = svm_set_tss_addr,
2624         .get_tdp_level = get_npt_level,
2625         .get_mt_mask_shift = svm_get_mt_mask_shift,
2626 };
2627
2628 static int __init svm_init(void)
2629 {
2630         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2631                               THIS_MODULE);
2632 }
2633
2634 static void __exit svm_exit(void)
2635 {
2636         kvm_exit();
2637 }
2638
2639 module_init(svm_init)
2640 module_exit(svm_exit)