arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28
  29 #include <asm/desc.h>
  30
  31 #include <asm/virtext.h>
  32
  33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 #define IOPM_ALLOC_ORDER 2
  39 #define MSRPM_ALLOC_ORDER 1
  40
  41 #define DR7_GD_MASK (1 << 13)
  42 #define DR6_BD_MASK (1 << 13)
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT  (1 << 0)
  48 #define SVM_FEATURE_LBRV (1 << 1)
  49 #define SVM_FEATURE_SVML (1 << 2)
  50
  51 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  52
  53 /* Turn on to get debugging output*/
  54 /* #define NESTED_DEBUG */
  55
  56 #ifdef NESTED_DEBUG
  57 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  58 #else
  59 #define nsvm_printk(fmt, args...) do {} while(0)
  60 #endif
  61
  62 /* enable NPT for AMD64 and X86 with PAE */
  63 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  64 static bool npt_enabled = true;
  65 #else
  66 static bool npt_enabled = false;
  67 #endif
  68 static int npt = 1;
  69
  70 module_param(npt, int, S_IRUGO);
  71
  72 static void kvm_reput_irq(struct vcpu_svm *svm);
  73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  74
  75 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  76 {
  77         return container_of(vcpu, struct vcpu_svm, vcpu);
  78 }
  79
  80 static inline bool is_nested(struct vcpu_svm *svm)
  81 {
  82         return svm->nested_vmcb;
  83 }
  84
  85 static unsigned long iopm_base;
  86
  87 struct kvm_ldttss_desc {
  88         u16 limit0;
  89         u16 base0;
  90         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  91         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  92         u32 base3;
  93         u32 zero1;
  94 } __attribute__((packed));
  95
  96 struct svm_cpu_data {
  97         int cpu;
  98
  99         u64 asid_generation;
 100         u32 max_asid;
 101         u32 next_asid;
 102         struct kvm_ldttss_desc *tss_desc;
 103
 104         struct page *save_area;
 105 };
 106
 107 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 108 static uint32_t svm_features;
 109
 110 struct svm_init_data {
 111         int cpu;
 112         int r;
 113 };
 114
 115 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 116
 117 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 118 #define MSRS_RANGE_SIZE 2048
 119 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 120
 121 #define MAX_INST_SIZE 15
 122
 123 static inline u32 svm_has(u32 feat)
 124 {
 125         return svm_features & feat;
 126 }
 127
 128 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 129 {
 130         int word_index = __ffs(vcpu->arch.irq_summary);
 131         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 132         int irq = word_index * BITS_PER_LONG + bit_index;
 133
 134         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 135         if (!vcpu->arch.irq_pending[word_index])
 136                 clear_bit(word_index, &vcpu->arch.irq_summary);
 137         return irq;
 138 }
 139
 140 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 141 {
 142         set_bit(irq, vcpu->arch.irq_pending);
 143         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 144 }
 145
 146 static inline void clgi(void)
 147 {
 148         asm volatile (__ex(SVM_CLGI));
 149 }
 150
 151 static inline void stgi(void)
 152 {
 153         asm volatile (__ex(SVM_STGI));
 154 }
 155
 156 static inline void invlpga(unsigned long addr, u32 asid)
 157 {
 158         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 159 }
 160
 161 static inline unsigned long kvm_read_cr2(void)
 162 {
 163         unsigned long cr2;
 164
 165         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 166         return cr2;
 167 }
 168
 169 static inline void kvm_write_cr2(unsigned long val)
 170 {
 171         asm volatile ("mov %0, %%cr2" :: "r" (val));
 172 }
 173
 174 static inline unsigned long read_dr6(void)
 175 {
 176         unsigned long dr6;
 177
 178         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 179         return dr6;
 180 }
 181
 182 static inline void write_dr6(unsigned long val)
 183 {
 184         asm volatile ("mov %0, %%dr6" :: "r" (val));
 185 }
 186
 187 static inline unsigned long read_dr7(void)
 188 {
 189         unsigned long dr7;
 190
 191         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 192         return dr7;
 193 }
 194
 195 static inline void write_dr7(unsigned long val)
 196 {
 197         asm volatile ("mov %0, %%dr7" :: "r" (val));
 198 }
 199
 200 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 201 {
 202         to_svm(vcpu)->asid_generation--;
 203 }
 204
 205 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 206 {
 207         force_new_asid(vcpu);
 208 }
 209
 210 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 211 {
 212         if (!npt_enabled && !(efer & EFER_LMA))
 213                 efer &= ~EFER_LME;
 214
 215         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 216         vcpu->arch.shadow_efer = efer;
 217 }
 218
 219 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 220                                 bool has_error_code, u32 error_code)
 221 {
 222         struct vcpu_svm *svm = to_svm(vcpu);
 223
 224         svm->vmcb->control.event_inj = nr
 225                 | SVM_EVTINJ_VALID
 226                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 227                 | SVM_EVTINJ_TYPE_EXEPT;
 228         svm->vmcb->control.event_inj_err = error_code;
 229 }
 230
 231 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 232 {
 233         struct vcpu_svm *svm = to_svm(vcpu);
 234
 235         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 236 }
 237
 238 static int is_external_interrupt(u32 info)
 239 {
 240         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 241         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 242 }
 243
 244 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 245 {
 246         struct vcpu_svm *svm = to_svm(vcpu);
 247
 248         if (!svm->next_rip) {
 249                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 250                 return;
 251         }
 252         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 253                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 254                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 255
 256         kvm_rip_write(vcpu, svm->next_rip);
 257         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 258
 259         vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK);
 260 }
 261
 262 static int has_svm(void)
 263 {
 264         const char *msg;
 265
 266         if (!cpu_has_svm(&msg)) {
 267                 printk(KERN_INFO "has_svn: %s\n", msg);
 268                 return 0;
 269         }
 270
 271         return 1;
 272 }
 273
 274 static void svm_hardware_disable(void *garbage)
 275 {
 276         cpu_svm_disable();
 277 }
 278
 279 static void svm_hardware_enable(void *garbage)
 280 {
 281
 282         struct svm_cpu_data *svm_data;
 283         uint64_t efer;
 284         struct desc_ptr gdt_descr;
 285         struct desc_struct *gdt;
 286         int me = raw_smp_processor_id();
 287
 288         if (!has_svm()) {
 289                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 290                 return;
 291         }
 292         svm_data = per_cpu(svm_data, me);
 293
 294         if (!svm_data) {
 295                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 296                        me);
 297                 return;
 298         }
 299
 300         svm_data->asid_generation = 1;
 301         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 302         svm_data->next_asid = svm_data->max_asid + 1;
 303
 304         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 305         gdt = (struct desc_struct *)gdt_descr.address;
 306         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 307
 308         rdmsrl(MSR_EFER, efer);
 309         wrmsrl(MSR_EFER, efer | EFER_SVME);
 310
 311         wrmsrl(MSR_VM_HSAVE_PA,
 312                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 313 }
 314
 315 static void svm_cpu_uninit(int cpu)
 316 {
 317         struct svm_cpu_data *svm_data
 318                 = per_cpu(svm_data, raw_smp_processor_id());
 319
 320         if (!svm_data)
 321                 return;
 322
 323         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 324         __free_page(svm_data->save_area);
 325         kfree(svm_data);
 326 }
 327
 328 static int svm_cpu_init(int cpu)
 329 {
 330         struct svm_cpu_data *svm_data;
 331         int r;
 332
 333         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 334         if (!svm_data)
 335                 return -ENOMEM;
 336         svm_data->cpu = cpu;
 337         svm_data->save_area = alloc_page(GFP_KERNEL);
 338         r = -ENOMEM;
 339         if (!svm_data->save_area)
 340                 goto err_1;
 341
 342         per_cpu(svm_data, cpu) = svm_data;
 343
 344         return 0;
 345
 346 err_1:
 347         kfree(svm_data);
 348         return r;
 349
 350 }
 351
 352 static void set_msr_interception(u32 *msrpm, unsigned msr,
 353                                  int read, int write)
 354 {
 355         int i;
 356
 357         for (i = 0; i < NUM_MSR_MAPS; i++) {
 358                 if (msr >= msrpm_ranges[i] &&
 359                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 360                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 361                                           msrpm_ranges[i]) * 2;
 362
 363                         u32 *base = msrpm + (msr_offset / 32);
 364                         u32 msr_shift = msr_offset % 32;
 365                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 366                         *base = (*base & ~(0x3 << msr_shift)) |
 367                                 (mask << msr_shift);
 368                         return;
 369                 }
 370         }
 371         BUG();
 372 }
 373
 374 static void svm_vcpu_init_msrpm(u32 *msrpm)
 375 {
 376         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 377
 378 #ifdef CONFIG_X86_64
 379         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 380         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 381         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 382         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 383         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 384         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 385 #endif
 386         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 387         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 388         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 389         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 390 }
 391
 392 static void svm_enable_lbrv(struct vcpu_svm *svm)
 393 {
 394         u32 *msrpm = svm->msrpm;
 395
 396         svm->vmcb->control.lbr_ctl = 1;
 397         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 398         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 399         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 400         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 401 }
 402
 403 static void svm_disable_lbrv(struct vcpu_svm *svm)
 404 {
 405         u32 *msrpm = svm->msrpm;
 406
 407         svm->vmcb->control.lbr_ctl = 0;
 408         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 409         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 410         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 411         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 412 }
 413
 414 static __init int svm_hardware_setup(void)
 415 {
 416         int cpu;
 417         struct page *iopm_pages;
 418         void *iopm_va;
 419         int r;
 420
 421         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 422
 423         if (!iopm_pages)
 424                 return -ENOMEM;
 425
 426         iopm_va = page_address(iopm_pages);
 427         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 428         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 429         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 430
 431         if (boot_cpu_has(X86_FEATURE_NX))
 432                 kvm_enable_efer_bits(EFER_NX);
 433
 434         for_each_online_cpu(cpu) {
 435                 r = svm_cpu_init(cpu);
 436                 if (r)
 437                         goto err;
 438         }
 439
 440         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 441
 442         if (!svm_has(SVM_FEATURE_NPT))
 443                 npt_enabled = false;
 444
 445         if (npt_enabled && !npt) {
 446                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 447                 npt_enabled = false;
 448         }
 449
 450         if (npt_enabled) {
 451                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 452                 kvm_enable_tdp();
 453         } else
 454                 kvm_disable_tdp();
 455
 456         return 0;
 457
 458 err:
 459         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 460         iopm_base = 0;
 461         return r;
 462 }
 463
 464 static __exit void svm_hardware_unsetup(void)
 465 {
 466         int cpu;
 467
 468         for_each_online_cpu(cpu)
 469                 svm_cpu_uninit(cpu);
 470
 471         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 472         iopm_base = 0;
 473 }
 474
 475 static void init_seg(struct vmcb_seg *seg)
 476 {
 477         seg->selector = 0;
 478         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 479                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 480         seg->limit = 0xffff;
 481         seg->base = 0;
 482 }
 483
 484 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 485 {
 486         seg->selector = 0;
 487         seg->attrib = SVM_SELECTOR_P_MASK | type;
 488         seg->limit = 0xffff;
 489         seg->base = 0;
 490 }
 491
 492 static void init_vmcb(struct vcpu_svm *svm)
 493 {
 494         struct vmcb_control_area *control = &svm->vmcb->control;
 495         struct vmcb_save_area *save = &svm->vmcb->save;
 496
 497         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 498                                         INTERCEPT_CR3_MASK |
 499                                         INTERCEPT_CR4_MASK;
 500
 501         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 502                                         INTERCEPT_CR3_MASK |
 503                                         INTERCEPT_CR4_MASK |
 504                                         INTERCEPT_CR8_MASK;
 505
 506         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 507                                         INTERCEPT_DR1_MASK |
 508                                         INTERCEPT_DR2_MASK |
 509                                         INTERCEPT_DR3_MASK;
 510
 511         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 512                                         INTERCEPT_DR1_MASK |
 513                                         INTERCEPT_DR2_MASK |
 514                                         INTERCEPT_DR3_MASK |
 515                                         INTERCEPT_DR5_MASK |
 516                                         INTERCEPT_DR7_MASK;
 517
 518         control->intercept_exceptions = (1 << PF_VECTOR) |
 519                                         (1 << UD_VECTOR) |
 520                                         (1 << MC_VECTOR);
 521
 522
 523         control->intercept =    (1ULL << INTERCEPT_INTR) |
 524                                 (1ULL << INTERCEPT_NMI) |
 525                                 (1ULL << INTERCEPT_SMI) |
 526                                 (1ULL << INTERCEPT_CPUID) |
 527                                 (1ULL << INTERCEPT_INVD) |
 528                                 (1ULL << INTERCEPT_HLT) |
 529                                 (1ULL << INTERCEPT_INVLPG) |
 530                                 (1ULL << INTERCEPT_INVLPGA) |
 531                                 (1ULL << INTERCEPT_IOIO_PROT) |
 532                                 (1ULL << INTERCEPT_MSR_PROT) |
 533                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 534                                 (1ULL << INTERCEPT_SHUTDOWN) |
 535                                 (1ULL << INTERCEPT_VMRUN) |
 536                                 (1ULL << INTERCEPT_VMMCALL) |
 537                                 (1ULL << INTERCEPT_VMLOAD) |
 538                                 (1ULL << INTERCEPT_VMSAVE) |
 539                                 (1ULL << INTERCEPT_STGI) |
 540                                 (1ULL << INTERCEPT_CLGI) |
 541                                 (1ULL << INTERCEPT_SKINIT) |
 542                                 (1ULL << INTERCEPT_WBINVD) |
 543                                 (1ULL << INTERCEPT_MONITOR) |
 544                                 (1ULL << INTERCEPT_MWAIT);
 545
 546         control->iopm_base_pa = iopm_base;
 547         control->msrpm_base_pa = __pa(svm->msrpm);
 548         control->tsc_offset = 0;
 549         control->int_ctl = V_INTR_MASKING_MASK;
 550
 551         init_seg(&save->es);
 552         init_seg(&save->ss);
 553         init_seg(&save->ds);
 554         init_seg(&save->fs);
 555         init_seg(&save->gs);
 556
 557         save->cs.selector = 0xf000;
 558         /* Executable/Readable Code Segment */
 559         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 560                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 561         save->cs.limit = 0xffff;
 562         /*
 563          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 564          * be consistent with it.
 565          *
 566          * Replace when we have real mode working for vmx.
 567          */
 568         save->cs.base = 0xf0000;
 569
 570         save->gdtr.limit = 0xffff;
 571         save->idtr.limit = 0xffff;
 572
 573         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 574         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 575
 576         save->efer = EFER_SVME;
 577         save->dr6 = 0xffff0ff0;
 578         save->dr7 = 0x400;
 579         save->rflags = 2;
 580         save->rip = 0x0000fff0;
 581         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 582
 583         /*
 584          * cr0 val on cpu init should be 0x60000010, we enable cpu
 585          * cache by default. the orderly way is to enable cache in bios.
 586          */
 587         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 588         save->cr4 = X86_CR4_PAE;
 589         /* rdx = ?? */
 590
 591         if (npt_enabled) {
 592                 /* Setup VMCB for Nested Paging */
 593                 control->nested_ctl = 1;
 594                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 595                                         (1ULL << INTERCEPT_INVLPG));
 596                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 597                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 598                                                 INTERCEPT_CR3_MASK);
 599                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 600                                                  INTERCEPT_CR3_MASK);
 601                 save->g_pat = 0x0007040600070406ULL;
 602                 /* enable caching because the QEMU Bios doesn't enable it */
 603                 save->cr0 = X86_CR0_ET;
 604                 save->cr3 = 0;
 605                 save->cr4 = 0;
 606         }
 607         force_new_asid(&svm->vcpu);
 608
 609         svm->nested_vmcb = 0;
 610         svm->vcpu.arch.hflags = HF_GIF_MASK;
 611 }
 612
 613 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 614 {
 615         struct vcpu_svm *svm = to_svm(vcpu);
 616
 617         init_vmcb(svm);
 618
 619         if (vcpu->vcpu_id != 0) {
 620                 kvm_rip_write(vcpu, 0);
 621                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 622                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 623         }
 624         vcpu->arch.regs_avail = ~0;
 625         vcpu->arch.regs_dirty = ~0;
 626
 627         return 0;
 628 }
 629
 630 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 631 {
 632         struct vcpu_svm *svm;
 633         struct page *page;
 634         struct page *msrpm_pages;
 635         struct page *hsave_page;
 636         struct page *nested_msrpm_pages;
 637         int err;
 638
 639         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 640         if (!svm) {
 641                 err = -ENOMEM;
 642                 goto out;
 643         }
 644
 645         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 646         if (err)
 647                 goto free_svm;
 648
 649         page = alloc_page(GFP_KERNEL);
 650         if (!page) {
 651                 err = -ENOMEM;
 652                 goto uninit;
 653         }
 654
 655         err = -ENOMEM;
 656         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 657         if (!msrpm_pages)
 658                 goto uninit;
 659
 660         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 661         if (!nested_msrpm_pages)
 662                 goto uninit;
 663
 664         svm->msrpm = page_address(msrpm_pages);
 665         svm_vcpu_init_msrpm(svm->msrpm);
 666
 667         hsave_page = alloc_page(GFP_KERNEL);
 668         if (!hsave_page)
 669                 goto uninit;
 670         svm->hsave = page_address(hsave_page);
 671
 672         svm->nested_msrpm = page_address(nested_msrpm_pages);
 673
 674         svm->vmcb = page_address(page);
 675         clear_page(svm->vmcb);
 676         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 677         svm->asid_generation = 0;
 678         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 679         init_vmcb(svm);
 680
 681         fx_init(&svm->vcpu);
 682         svm->vcpu.fpu_active = 1;
 683         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 684         if (svm->vcpu.vcpu_id == 0)
 685                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 686
 687         return &svm->vcpu;
 688
 689 uninit:
 690         kvm_vcpu_uninit(&svm->vcpu);
 691 free_svm:
 692         kmem_cache_free(kvm_vcpu_cache, svm);
 693 out:
 694         return ERR_PTR(err);
 695 }
 696
 697 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 698 {
 699         struct vcpu_svm *svm = to_svm(vcpu);
 700
 701         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 702         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 703         __free_page(virt_to_page(svm->hsave));
 704         __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
 705         kvm_vcpu_uninit(vcpu);
 706         kmem_cache_free(kvm_vcpu_cache, svm);
 707 }
 708
 709 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 710 {
 711         struct vcpu_svm *svm = to_svm(vcpu);
 712         int i;
 713
 714         if (unlikely(cpu != vcpu->cpu)) {
 715                 u64 tsc_this, delta;
 716
 717                 /*
 718                  * Make sure that the guest sees a monotonically
 719                  * increasing TSC.
 720                  */
 721                 rdtscll(tsc_this);
 722                 delta = vcpu->arch.host_tsc - tsc_this;
 723                 svm->vmcb->control.tsc_offset += delta;
 724                 vcpu->cpu = cpu;
 725                 kvm_migrate_timers(vcpu);
 726         }
 727
 728         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 729                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 730 }
 731
 732 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 733 {
 734         struct vcpu_svm *svm = to_svm(vcpu);
 735         int i;
 736
 737         ++vcpu->stat.host_state_reload;
 738         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 739                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 740
 741         rdtscll(vcpu->arch.host_tsc);
 742 }
 743
 744 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 745 {
 746         return to_svm(vcpu)->vmcb->save.rflags;
 747 }
 748
 749 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 750 {
 751         to_svm(vcpu)->vmcb->save.rflags = rflags;
 752 }
 753
 754 static void svm_set_vintr(struct vcpu_svm *svm)
 755 {
 756         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 757 }
 758
 759 static void svm_clear_vintr(struct vcpu_svm *svm)
 760 {
 761         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 762 }
 763
 764 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 765 {
 766         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 767
 768         switch (seg) {
 769         case VCPU_SREG_CS: return &save->cs;
 770         case VCPU_SREG_DS: return &save->ds;
 771         case VCPU_SREG_ES: return &save->es;
 772         case VCPU_SREG_FS: return &save->fs;
 773         case VCPU_SREG_GS: return &save->gs;
 774         case VCPU_SREG_SS: return &save->ss;
 775         case VCPU_SREG_TR: return &save->tr;
 776         case VCPU_SREG_LDTR: return &save->ldtr;
 777         }
 778         BUG();
 779         return NULL;
 780 }
 781
 782 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 783 {
 784         struct vmcb_seg *s = svm_seg(vcpu, seg);
 785
 786         return s->base;
 787 }
 788
 789 static void svm_get_segment(struct kvm_vcpu *vcpu,
 790                             struct kvm_segment *var, int seg)
 791 {
 792         struct vmcb_seg *s = svm_seg(vcpu, seg);
 793
 794         var->base = s->base;
 795         var->limit = s->limit;
 796         var->selector = s->selector;
 797         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 798         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 799         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 800         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 801         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 802         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 803         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 804         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 805
 806         /*
 807          * SVM always stores 0 for the 'G' bit in the CS selector in
 808          * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 809          * Intel's VMENTRY has a check on the 'G' bit.
 810          */
 811         if (seg == VCPU_SREG_CS)
 812                 var->g = s->limit > 0xfffff;
 813
 814         /*
 815          * Work around a bug where the busy flag in the tr selector
 816          * isn't exposed
 817          */
 818         if (seg == VCPU_SREG_TR)
 819                 var->type |= 0x2;
 820
 821         var->unusable = !var->present;
 822 }
 823
 824 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 825 {
 826         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 827
 828         return save->cpl;
 829 }
 830
 831 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 832 {
 833         struct vcpu_svm *svm = to_svm(vcpu);
 834
 835         dt->limit = svm->vmcb->save.idtr.limit;
 836         dt->base = svm->vmcb->save.idtr.base;
 837 }
 838
 839 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 840 {
 841         struct vcpu_svm *svm = to_svm(vcpu);
 842
 843         svm->vmcb->save.idtr.limit = dt->limit;
 844         svm->vmcb->save.idtr.base = dt->base ;
 845 }
 846
 847 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 848 {
 849         struct vcpu_svm *svm = to_svm(vcpu);
 850
 851         dt->limit = svm->vmcb->save.gdtr.limit;
 852         dt->base = svm->vmcb->save.gdtr.base;
 853 }
 854
 855 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 856 {
 857         struct vcpu_svm *svm = to_svm(vcpu);
 858
 859         svm->vmcb->save.gdtr.limit = dt->limit;
 860         svm->vmcb->save.gdtr.base = dt->base ;
 861 }
 862
 863 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 864 {
 865 }
 866
 867 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 868 {
 869         struct vcpu_svm *svm = to_svm(vcpu);
 870
 871 #ifdef CONFIG_X86_64
 872         if (vcpu->arch.shadow_efer & EFER_LME) {
 873                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 874                         vcpu->arch.shadow_efer |= EFER_LMA;
 875                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 876                 }
 877
 878                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 879                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 880                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 881                 }
 882         }
 883 #endif
 884         if (npt_enabled)
 885                 goto set;
 886
 887         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 888                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 889                 vcpu->fpu_active = 1;
 890         }
 891
 892         vcpu->arch.cr0 = cr0;
 893         cr0 |= X86_CR0_PG | X86_CR0_WP;
 894         if (!vcpu->fpu_active) {
 895                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 896                 cr0 |= X86_CR0_TS;
 897         }
 898 set:
 899         /*
 900          * re-enable caching here because the QEMU bios
 901          * does not do it - this results in some delay at
 902          * reboot
 903          */
 904         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 905         svm->vmcb->save.cr0 = cr0;
 906 }
 907
 908 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 909 {
 910         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 911         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 912
 913         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 914                 force_new_asid(vcpu);
 915
 916         vcpu->arch.cr4 = cr4;
 917         if (!npt_enabled)
 918                 cr4 |= X86_CR4_PAE;
 919         cr4 |= host_cr4_mce;
 920         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 921 }
 922
 923 static void svm_set_segment(struct kvm_vcpu *vcpu,
 924                             struct kvm_segment *var, int seg)
 925 {
 926         struct vcpu_svm *svm = to_svm(vcpu);
 927         struct vmcb_seg *s = svm_seg(vcpu, seg);
 928
 929         s->base = var->base;
 930         s->limit = var->limit;
 931         s->selector = var->selector;
 932         if (var->unusable)
 933                 s->attrib = 0;
 934         else {
 935                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 936                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 937                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 938                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 939                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 940                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 941                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 942                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 943         }
 944         if (seg == VCPU_SREG_CS)
 945                 svm->vmcb->save.cpl
 946                         = (svm->vmcb->save.cs.attrib
 947                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 948
 949 }
 950
 951 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 952 {
 953         return -EOPNOTSUPP;
 954 }
 955
 956 static int svm_get_irq(struct kvm_vcpu *vcpu)
 957 {
 958         struct vcpu_svm *svm = to_svm(vcpu);
 959         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 960
 961         if (is_external_interrupt(exit_int_info))
 962                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 963         return -1;
 964 }
 965
 966 static void load_host_msrs(struct kvm_vcpu *vcpu)
 967 {
 968 #ifdef CONFIG_X86_64
 969         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 970 #endif
 971 }
 972
 973 static void save_host_msrs(struct kvm_vcpu *vcpu)
 974 {
 975 #ifdef CONFIG_X86_64
 976         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 977 #endif
 978 }
 979
 980 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 981 {
 982         if (svm_data->next_asid > svm_data->max_asid) {
 983                 ++svm_data->asid_generation;
 984                 svm_data->next_asid = 1;
 985                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 986         }
 987
 988         svm->vcpu.cpu = svm_data->cpu;
 989         svm->asid_generation = svm_data->asid_generation;
 990         svm->vmcb->control.asid = svm_data->next_asid++;
 991 }
 992
 993 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 994 {
 995         unsigned long val = to_svm(vcpu)->db_regs[dr];
 996         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
 997         return val;
 998 }
 999
1000 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1001                        int *exception)
1002 {
1003         struct vcpu_svm *svm = to_svm(vcpu);
1004
1005         *exception = 0;
1006
1007         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
1008                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
1009                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
1010                 *exception = DB_VECTOR;
1011                 return;
1012         }
1013
1014         switch (dr) {
1015         case 0 ... 3:
1016                 svm->db_regs[dr] = value;
1017                 return;
1018         case 4 ... 5:
1019                 if (vcpu->arch.cr4 & X86_CR4_DE) {
1020                         *exception = UD_VECTOR;
1021                         return;
1022                 }
1023         case 7: {
1024                 if (value & ~((1ULL << 32) - 1)) {
1025                         *exception = GP_VECTOR;
1026                         return;
1027                 }
1028                 svm->vmcb->save.dr7 = value;
1029                 return;
1030         }
1031         default:
1032                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1033                        __func__, dr);
1034                 *exception = UD_VECTOR;
1035                 return;
1036         }
1037 }
1038
1039 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1040 {
1041         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1042         struct kvm *kvm = svm->vcpu.kvm;
1043         u64 fault_address;
1044         u32 error_code;
1045         bool event_injection = false;
1046
1047         if (!irqchip_in_kernel(kvm) &&
1048             is_external_interrupt(exit_int_info)) {
1049                 event_injection = true;
1050                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1051         }
1052
1053         fault_address  = svm->vmcb->control.exit_info_2;
1054         error_code = svm->vmcb->control.exit_info_1;
1055
1056         if (!npt_enabled)
1057                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1058                             (u32)fault_address, (u32)(fault_address >> 32),
1059                             handler);
1060         else
1061                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1062                             (u32)fault_address, (u32)(fault_address >> 32),
1063                             handler);
1064         /*
1065          * FIXME: Tis shouldn't be necessary here, but there is a flush
1066          * missing in the MMU code. Until we find this bug, flush the
1067          * complete TLB here on an NPF
1068          */
1069         if (npt_enabled)
1070                 svm_flush_tlb(&svm->vcpu);
1071
1072         if (!npt_enabled && event_injection)
1073                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1074         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1075 }
1076
1077 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1078 {
1079         int er;
1080
1081         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1082         if (er != EMULATE_DONE)
1083                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1084         return 1;
1085 }
1086
1087 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1088 {
1089         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1090         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1091                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1092         svm->vcpu.fpu_active = 1;
1093
1094         return 1;
1095 }
1096
1097 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1098 {
1099         /*
1100          * On an #MC intercept the MCE handler is not called automatically in
1101          * the host. So do it by hand here.
1102          */
1103         asm volatile (
1104                 "int $0x12\n");
1105         /* not sure if we ever come back to this point */
1106
1107         return 1;
1108 }
1109
1110 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1111 {
1112         /*
1113          * VMCB is undefined after a SHUTDOWN intercept
1114          * so reinitialize it.
1115          */
1116         clear_page(svm->vmcb);
1117         init_vmcb(svm);
1118
1119         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1120         return 0;
1121 }
1122
1123 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1124 {
1125         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1126         int size, down, in, string, rep;
1127         unsigned port;
1128
1129         ++svm->vcpu.stat.io_exits;
1130
1131         svm->next_rip = svm->vmcb->control.exit_info_2;
1132
1133         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1134
1135         if (string) {
1136                 if (emulate_instruction(&svm->vcpu,
1137                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1138                         return 0;
1139                 return 1;
1140         }
1141
1142         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1143         port = io_info >> 16;
1144         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1145         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1146         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1147
1148         skip_emulated_instruction(&svm->vcpu);
1149         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1150 }
1151
1152 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1153 {
1154         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1155         return 1;
1156 }
1157
1158 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1159 {
1160         ++svm->vcpu.stat.irq_exits;
1161         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1162         return 1;
1163 }
1164
1165 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1166 {
1167         return 1;
1168 }
1169
1170 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1171 {
1172         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1173         skip_emulated_instruction(&svm->vcpu);
1174         return kvm_emulate_halt(&svm->vcpu);
1175 }
1176
1177 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1178 {
1179         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1180         skip_emulated_instruction(&svm->vcpu);
1181         kvm_emulate_hypercall(&svm->vcpu);
1182         return 1;
1183 }
1184
1185 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1186 {
1187         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1188             || !is_paging(&svm->vcpu)) {
1189                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1190                 return 1;
1191         }
1192
1193         if (svm->vmcb->save.cpl) {
1194                 kvm_inject_gp(&svm->vcpu, 0);
1195                 return 1;
1196         }
1197
1198        return 0;
1199 }
1200
1201 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1202 {
1203         struct page *page;
1204
1205         down_read(&current->mm->mmap_sem);
1206         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1207         up_read(&current->mm->mmap_sem);
1208
1209         if (is_error_page(page)) {
1210                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1211                        __func__, gpa);
1212                 kvm_release_page_clean(page);
1213                 kvm_inject_gp(&svm->vcpu, 0);
1214                 return NULL;
1215         }
1216         return page;
1217 }
1218
1219 static int nested_svm_do(struct vcpu_svm *svm,
1220                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1221                          int (*handler)(struct vcpu_svm *svm,
1222                                         void *arg1,
1223                                         void *arg2,
1224                                         void *opaque))
1225 {
1226         struct page *arg1_page;
1227         struct page *arg2_page = NULL;
1228         void *arg1;
1229         void *arg2 = NULL;
1230         int retval;
1231
1232         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1233         if(arg1_page == NULL)
1234                 return 1;
1235
1236         if (arg2_gpa) {
1237                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1238                 if(arg2_page == NULL) {
1239                         kvm_release_page_clean(arg1_page);
1240                         return 1;
1241                 }
1242         }
1243
1244         arg1 = kmap_atomic(arg1_page, KM_USER0);
1245         if (arg2_gpa)
1246                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1247
1248         retval = handler(svm, arg1, arg2, opaque);
1249
1250         kunmap_atomic(arg1, KM_USER0);
1251         if (arg2_gpa)
1252                 kunmap_atomic(arg2, KM_USER1);
1253
1254         kvm_release_page_dirty(arg1_page);
1255         if (arg2_gpa)
1256                 kvm_release_page_dirty(arg2_page);
1257
1258         return retval;
1259 }
1260
1261
1262 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1263                                   void *arg2, void *opaque)
1264 {
1265         int i;
1266         u32 *nested_msrpm = (u32*)arg1;
1267         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1268                 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1269         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1270
1271         return 0;
1272 }
1273
1274 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1275                             void *arg2, void *opaque)
1276 {
1277         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1278         struct vmcb *hsave = svm->hsave;
1279
1280         /* nested_vmcb is our indicator if nested SVM is activated */
1281         svm->nested_vmcb = svm->vmcb->save.rax;
1282
1283         /* Clear internal status */
1284         svm->vcpu.arch.exception.pending = false;
1285
1286         /* Save the old vmcb, so we don't need to pick what we save, but
1287            can restore everything when a VMEXIT occurs */
1288         memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1289         /* We need to remember the original CR3 in the SPT case */
1290         if (!npt_enabled)
1291                 hsave->save.cr3 = svm->vcpu.arch.cr3;
1292         hsave->save.cr4 = svm->vcpu.arch.cr4;
1293         hsave->save.rip = svm->next_rip;
1294
1295         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1296                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1297         else
1298                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1299
1300         /* Load the nested guest state */
1301         svm->vmcb->save.es = nested_vmcb->save.es;
1302         svm->vmcb->save.cs = nested_vmcb->save.cs;
1303         svm->vmcb->save.ss = nested_vmcb->save.ss;
1304         svm->vmcb->save.ds = nested_vmcb->save.ds;
1305         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1306         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1307         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1308         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1309         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1310         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1311         if (npt_enabled) {
1312                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1313                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1314         } else {
1315                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1316                 kvm_mmu_reset_context(&svm->vcpu);
1317         }
1318         svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1319         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1320         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1321         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1322         /* In case we don't even reach vcpu_run, the fields are not updated */
1323         svm->vmcb->save.rax = nested_vmcb->save.rax;
1324         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1325         svm->vmcb->save.rip = nested_vmcb->save.rip;
1326         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1327         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1328         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1329
1330         /* We don't want a nested guest to be more powerful than the guest,
1331            so all intercepts are ORed */
1332         svm->vmcb->control.intercept_cr_read |=
1333                 nested_vmcb->control.intercept_cr_read;
1334         svm->vmcb->control.intercept_cr_write |=
1335                 nested_vmcb->control.intercept_cr_write;
1336         svm->vmcb->control.intercept_dr_read |=
1337                 nested_vmcb->control.intercept_dr_read;
1338         svm->vmcb->control.intercept_dr_write |=
1339                 nested_vmcb->control.intercept_dr_write;
1340         svm->vmcb->control.intercept_exceptions |=
1341                 nested_vmcb->control.intercept_exceptions;
1342
1343         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1344
1345         svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1346
1347         force_new_asid(&svm->vcpu);
1348         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1349         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1350         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1351         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1352                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1353                                 nested_vmcb->control.int_ctl);
1354         }
1355         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1356                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1357         else
1358                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1359
1360         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1361                         nested_vmcb->control.exit_int_info,
1362                         nested_vmcb->control.int_state);
1363
1364         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1365         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1366         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1367         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1368                 nsvm_printk("Injecting Event: 0x%x\n",
1369                                 nested_vmcb->control.event_inj);
1370         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1371         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1372
1373         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1374
1375         return 0;
1376 }
1377
1378 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1379 {
1380         to_vmcb->save.fs = from_vmcb->save.fs;
1381         to_vmcb->save.gs = from_vmcb->save.gs;
1382         to_vmcb->save.tr = from_vmcb->save.tr;
1383         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1384         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1385         to_vmcb->save.star = from_vmcb->save.star;
1386         to_vmcb->save.lstar = from_vmcb->save.lstar;
1387         to_vmcb->save.cstar = from_vmcb->save.cstar;
1388         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1389         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1390         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1391         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1392
1393         return 1;
1394 }
1395
1396 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1397                              void *arg2, void *opaque)
1398 {
1399         return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1400 }
1401
1402 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1403                              void *arg2, void *opaque)
1404 {
1405         return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1406 }
1407
1408 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1409 {
1410         if (nested_svm_check_permissions(svm))
1411                 return 1;
1412
1413         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1414         skip_emulated_instruction(&svm->vcpu);
1415
1416         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1417
1418         return 1;
1419 }
1420
1421 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1422 {
1423         if (nested_svm_check_permissions(svm))
1424                 return 1;
1425
1426         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1427         skip_emulated_instruction(&svm->vcpu);
1428
1429         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1430
1431         return 1;
1432 }
1433
1434 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1435 {
1436         nsvm_printk("VMrun\n");
1437         if (nested_svm_check_permissions(svm))
1438                 return 1;
1439
1440         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1441         skip_emulated_instruction(&svm->vcpu);
1442
1443         if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1444                           NULL, nested_svm_vmrun))
1445                 return 1;
1446
1447         if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1448                       NULL, nested_svm_vmrun_msrpm))
1449                 return 1;
1450
1451         return 1;
1452 }
1453
1454 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1455 {
1456         if (nested_svm_check_permissions(svm))
1457                 return 1;
1458
1459         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1460         skip_emulated_instruction(&svm->vcpu);
1461
1462         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1463
1464         return 1;
1465 }
1466
1467 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1468 {
1469         if (nested_svm_check_permissions(svm))
1470                 return 1;
1471
1472         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1473         skip_emulated_instruction(&svm->vcpu);
1474
1475         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1476
1477         /* After a CLGI no interrupts should come */
1478         svm_clear_vintr(svm);
1479         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1480
1481         return 1;
1482 }
1483
1484 static int invalid_op_interception(struct vcpu_svm *svm,
1485                                    struct kvm_run *kvm_run)
1486 {
1487         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1488         return 1;
1489 }
1490
1491 static int task_switch_interception(struct vcpu_svm *svm,
1492                                     struct kvm_run *kvm_run)
1493 {
1494         u16 tss_selector;
1495
1496         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1497         if (svm->vmcb->control.exit_info_2 &
1498             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1499                 return kvm_task_switch(&svm->vcpu, tss_selector,
1500                                        TASK_SWITCH_IRET);
1501         if (svm->vmcb->control.exit_info_2 &
1502             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1503                 return kvm_task_switch(&svm->vcpu, tss_selector,
1504                                        TASK_SWITCH_JMP);
1505         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1506 }
1507
1508 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1509 {
1510         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1511         kvm_emulate_cpuid(&svm->vcpu);
1512         return 1;
1513 }
1514
1515 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1516 {
1517         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1518                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1519         return 1;
1520 }
1521
1522 static int emulate_on_interception(struct vcpu_svm *svm,
1523                                    struct kvm_run *kvm_run)
1524 {
1525         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1526                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1527         return 1;
1528 }
1529
1530 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1531 {
1532         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1533         if (irqchip_in_kernel(svm->vcpu.kvm))
1534                 return 1;
1535         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1536         return 0;
1537 }
1538
1539 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1540 {
1541         struct vcpu_svm *svm = to_svm(vcpu);
1542
1543         switch (ecx) {
1544         case MSR_IA32_TIME_STAMP_COUNTER: {
1545                 u64 tsc;
1546
1547                 rdtscll(tsc);
1548                 *data = svm->vmcb->control.tsc_offset + tsc;
1549                 break;
1550         }
1551         case MSR_K6_STAR:
1552                 *data = svm->vmcb->save.star;
1553                 break;
1554 #ifdef CONFIG_X86_64
1555         case MSR_LSTAR:
1556                 *data = svm->vmcb->save.lstar;
1557                 break;
1558         case MSR_CSTAR:
1559                 *data = svm->vmcb->save.cstar;
1560                 break;
1561         case MSR_KERNEL_GS_BASE:
1562                 *data = svm->vmcb->save.kernel_gs_base;
1563                 break;
1564         case MSR_SYSCALL_MASK:
1565                 *data = svm->vmcb->save.sfmask;
1566                 break;
1567 #endif
1568         case MSR_IA32_SYSENTER_CS:
1569                 *data = svm->vmcb->save.sysenter_cs;
1570                 break;
1571         case MSR_IA32_SYSENTER_EIP:
1572                 *data = svm->vmcb->save.sysenter_eip;
1573                 break;
1574         case MSR_IA32_SYSENTER_ESP:
1575                 *data = svm->vmcb->save.sysenter_esp;
1576                 break;
1577         /* Nobody will change the following 5 values in the VMCB so
1578            we can safely return them on rdmsr. They will always be 0
1579            until LBRV is implemented. */
1580         case MSR_IA32_DEBUGCTLMSR:
1581                 *data = svm->vmcb->save.dbgctl;
1582                 break;
1583         case MSR_IA32_LASTBRANCHFROMIP:
1584                 *data = svm->vmcb->save.br_from;
1585                 break;
1586         case MSR_IA32_LASTBRANCHTOIP:
1587                 *data = svm->vmcb->save.br_to;
1588                 break;
1589         case MSR_IA32_LASTINTFROMIP:
1590                 *data = svm->vmcb->save.last_excp_from;
1591                 break;
1592         case MSR_IA32_LASTINTTOIP:
1593                 *data = svm->vmcb->save.last_excp_to;
1594                 break;
1595         case MSR_VM_HSAVE_PA:
1596                 *data = svm->hsave_msr;
1597                 break;
1598         default:
1599                 return kvm_get_msr_common(vcpu, ecx, data);
1600         }
1601         return 0;
1602 }
1603
1604 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1605 {
1606         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1607         u64 data;
1608
1609         if (svm_get_msr(&svm->vcpu, ecx, &data))
1610                 kvm_inject_gp(&svm->vcpu, 0);
1611         else {
1612                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1613                             (u32)(data >> 32), handler);
1614
1615                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1616                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1617                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1618                 skip_emulated_instruction(&svm->vcpu);
1619         }
1620         return 1;
1621 }
1622
1623 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1624 {
1625         struct vcpu_svm *svm = to_svm(vcpu);
1626
1627         switch (ecx) {
1628         case MSR_IA32_TIME_STAMP_COUNTER: {
1629                 u64 tsc;
1630
1631                 rdtscll(tsc);
1632                 svm->vmcb->control.tsc_offset = data - tsc;
1633                 break;
1634         }
1635         case MSR_K6_STAR:
1636                 svm->vmcb->save.star = data;
1637                 break;
1638 #ifdef CONFIG_X86_64
1639         case MSR_LSTAR:
1640                 svm->vmcb->save.lstar = data;
1641                 break;
1642         case MSR_CSTAR:
1643                 svm->vmcb->save.cstar = data;
1644                 break;
1645         case MSR_KERNEL_GS_BASE:
1646                 svm->vmcb->save.kernel_gs_base = data;
1647                 break;
1648         case MSR_SYSCALL_MASK:
1649                 svm->vmcb->save.sfmask = data;
1650                 break;
1651 #endif
1652         case MSR_IA32_SYSENTER_CS:
1653                 svm->vmcb->save.sysenter_cs = data;
1654                 break;
1655         case MSR_IA32_SYSENTER_EIP:
1656                 svm->vmcb->save.sysenter_eip = data;
1657                 break;
1658         case MSR_IA32_SYSENTER_ESP:
1659                 svm->vmcb->save.sysenter_esp = data;
1660                 break;
1661         case MSR_IA32_DEBUGCTLMSR:
1662                 if (!svm_has(SVM_FEATURE_LBRV)) {
1663                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1664                                         __func__, data);
1665                         break;
1666                 }
1667                 if (data & DEBUGCTL_RESERVED_BITS)
1668                         return 1;
1669
1670                 svm->vmcb->save.dbgctl = data;
1671                 if (data & (1ULL<<0))
1672                         svm_enable_lbrv(svm);
1673                 else
1674                         svm_disable_lbrv(svm);
1675                 break;
1676         case MSR_K7_EVNTSEL0:
1677         case MSR_K7_EVNTSEL1:
1678         case MSR_K7_EVNTSEL2:
1679         case MSR_K7_EVNTSEL3:
1680         case MSR_K7_PERFCTR0:
1681         case MSR_K7_PERFCTR1:
1682         case MSR_K7_PERFCTR2:
1683         case MSR_K7_PERFCTR3:
1684                 /*
1685                  * Just discard all writes to the performance counters; this
1686                  * should keep both older linux and windows 64-bit guests
1687                  * happy
1688                  */
1689                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1690
1691                 break;
1692         case MSR_VM_HSAVE_PA:
1693                 svm->hsave_msr = data;
1694                 break;
1695         default:
1696                 return kvm_set_msr_common(vcpu, ecx, data);
1697         }
1698         return 0;
1699 }
1700
1701 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1702 {
1703         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1704         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
1705                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1706
1707         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1708                     handler);
1709
1710         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1711         if (svm_set_msr(&svm->vcpu, ecx, data))
1712                 kvm_inject_gp(&svm->vcpu, 0);
1713         else
1714                 skip_emulated_instruction(&svm->vcpu);
1715         return 1;
1716 }
1717
1718 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1719 {
1720         if (svm->vmcb->control.exit_info_1)
1721                 return wrmsr_interception(svm, kvm_run);
1722         else
1723                 return rdmsr_interception(svm, kvm_run);
1724 }
1725
1726 static int interrupt_window_interception(struct vcpu_svm *svm,
1727                                    struct kvm_run *kvm_run)
1728 {
1729         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1730
1731         svm_clear_vintr(svm);
1732         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1733         /*
1734          * If the user space waits to inject interrupts, exit as soon as
1735          * possible
1736          */
1737         if (kvm_run->request_interrupt_window &&
1738             !svm->vcpu.arch.irq_summary) {
1739                 ++svm->vcpu.stat.irq_window_exits;
1740                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1741                 return 0;
1742         }
1743
1744         return 1;
1745 }
1746
1747 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1748                                       struct kvm_run *kvm_run) = {
1749         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1750         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1751         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1752         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1753         /* for now: */
1754         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1755         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1756         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1757         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1758         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1759         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1760         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1761         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1762         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1763         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1764         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1765         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1766         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1767         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1768         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1769         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1770         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1771         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1772         [SVM_EXIT_INTR]                         = intr_interception,
1773         [SVM_EXIT_NMI]                          = nmi_interception,
1774         [SVM_EXIT_SMI]                          = nop_on_interception,
1775         [SVM_EXIT_INIT]                         = nop_on_interception,
1776         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1777         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1778         [SVM_EXIT_CPUID]                        = cpuid_interception,
1779         [SVM_EXIT_INVD]                         = emulate_on_interception,
1780         [SVM_EXIT_HLT]                          = halt_interception,
1781         [SVM_EXIT_INVLPG]                       = invlpg_interception,
1782         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1783         [SVM_EXIT_IOIO]                         = io_interception,
1784         [SVM_EXIT_MSR]                          = msr_interception,
1785         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1786         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1787         [SVM_EXIT_VMRUN]                        = vmrun_interception,
1788         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1789         [SVM_EXIT_VMLOAD]                       = vmload_interception,
1790         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
1791         [SVM_EXIT_STGI]                         = stgi_interception,
1792         [SVM_EXIT_CLGI]                         = clgi_interception,
1793         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1794         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1795         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1796         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1797         [SVM_EXIT_NPF]                          = pf_interception,
1798 };
1799
1800 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1801 {
1802         struct vcpu_svm *svm = to_svm(vcpu);
1803         u32 exit_code = svm->vmcb->control.exit_code;
1804
1805         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1806                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1807
1808         if (npt_enabled) {
1809                 int mmu_reload = 0;
1810                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1811                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1812                         mmu_reload = 1;
1813                 }
1814                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1815                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1816                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1817                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1818                                 kvm_inject_gp(vcpu, 0);
1819                                 return 1;
1820                         }
1821                 }
1822                 if (mmu_reload) {
1823                         kvm_mmu_reset_context(vcpu);
1824                         kvm_mmu_load(vcpu);
1825                 }
1826         }
1827
1828         kvm_reput_irq(svm);
1829
1830         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1831                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1832                 kvm_run->fail_entry.hardware_entry_failure_reason
1833                         = svm->vmcb->control.exit_code;
1834                 return 0;
1835         }
1836
1837         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1838             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1839             exit_code != SVM_EXIT_NPF)
1840                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1841                        "exit_code 0x%x\n",
1842                        __func__, svm->vmcb->control.exit_int_info,
1843                        exit_code);
1844
1845         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1846             || !svm_exit_handlers[exit_code]) {
1847                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1848                 kvm_run->hw.hardware_exit_reason = exit_code;
1849                 return 0;
1850         }
1851
1852         return svm_exit_handlers[exit_code](svm, kvm_run);
1853 }
1854
1855 static void reload_tss(struct kvm_vcpu *vcpu)
1856 {
1857         int cpu = raw_smp_processor_id();
1858
1859         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1860         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1861         load_TR_desc();
1862 }
1863
1864 static void pre_svm_run(struct vcpu_svm *svm)
1865 {
1866         int cpu = raw_smp_processor_id();
1867
1868         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1869
1870         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1871         if (svm->vcpu.cpu != cpu ||
1872             svm->asid_generation != svm_data->asid_generation)
1873                 new_asid(svm, svm_data);
1874 }
1875
1876
1877 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1878 {
1879         struct vmcb_control_area *control;
1880
1881         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1882
1883         ++svm->vcpu.stat.irq_injections;
1884         control = &svm->vmcb->control;
1885         control->int_vector = irq;
1886         control->int_ctl &= ~V_INTR_PRIO_MASK;
1887         control->int_ctl |= V_IRQ_MASK |
1888                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1889 }
1890
1891 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1892 {
1893         struct vcpu_svm *svm = to_svm(vcpu);
1894
1895         svm_inject_irq(svm, irq);
1896 }
1897
1898 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1899 {
1900         struct vcpu_svm *svm = to_svm(vcpu);
1901         struct vmcb *vmcb = svm->vmcb;
1902         int max_irr, tpr;
1903
1904         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1905                 return;
1906
1907         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1908
1909         max_irr = kvm_lapic_find_highest_irr(vcpu);
1910         if (max_irr == -1)
1911                 return;
1912
1913         tpr = kvm_lapic_get_cr8(vcpu) << 4;
1914
1915         if (tpr >= (max_irr & 0xf0))
1916                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1917 }
1918
1919 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1920 {
1921         struct vcpu_svm *svm = to_svm(vcpu);
1922         struct vmcb *vmcb = svm->vmcb;
1923         int intr_vector = -1;
1924
1925         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1926             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1927                 intr_vector = vmcb->control.exit_int_info &
1928                               SVM_EVTINJ_VEC_MASK;
1929                 vmcb->control.exit_int_info = 0;
1930                 svm_inject_irq(svm, intr_vector);
1931                 goto out;
1932         }
1933
1934         if (vmcb->control.int_ctl & V_IRQ_MASK)
1935                 goto out;
1936
1937         if (!kvm_cpu_has_interrupt(vcpu))
1938                 goto out;
1939
1940         if (!(svm->vcpu.arch.hflags & HF_GIF_MASK))
1941                 goto out;
1942
1943         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1944             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1945             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1946                 /* unable to deliver irq, set pending irq */
1947                 svm_set_vintr(svm);
1948                 svm_inject_irq(svm, 0x0);
1949                 goto out;
1950         }
1951         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1952         intr_vector = kvm_cpu_get_interrupt(vcpu);
1953         svm_inject_irq(svm, intr_vector);
1954 out:
1955         update_cr8_intercept(vcpu);
1956 }
1957
1958 static void kvm_reput_irq(struct vcpu_svm *svm)
1959 {
1960         struct vmcb_control_area *control = &svm->vmcb->control;
1961
1962         if ((control->int_ctl & V_IRQ_MASK)
1963             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1964                 control->int_ctl &= ~V_IRQ_MASK;
1965                 push_irq(&svm->vcpu, control->int_vector);
1966         }
1967
1968         svm->vcpu.arch.interrupt_window_open =
1969                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1970                  (svm->vcpu.arch.hflags & HF_GIF_MASK);
1971 }
1972
1973 static void svm_do_inject_vector(struct vcpu_svm *svm)
1974 {
1975         struct kvm_vcpu *vcpu = &svm->vcpu;
1976         int word_index = __ffs(vcpu->arch.irq_summary);
1977         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1978         int irq = word_index * BITS_PER_LONG + bit_index;
1979
1980         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1981         if (!vcpu->arch.irq_pending[word_index])
1982                 clear_bit(word_index, &vcpu->arch.irq_summary);
1983         svm_inject_irq(svm, irq);
1984 }
1985
1986 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1987                                        struct kvm_run *kvm_run)
1988 {
1989         struct vcpu_svm *svm = to_svm(vcpu);
1990         struct vmcb_control_area *control = &svm->vmcb->control;
1991
1992         svm->vcpu.arch.interrupt_window_open =
1993                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1994                  (svm->vmcb->save.rflags & X86_EFLAGS_IF) &&
1995                  (svm->vcpu.arch.hflags & HF_GIF_MASK));
1996
1997         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1998                 /*
1999                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
2000                  */
2001                 svm_do_inject_vector(svm);
2002
2003         /*
2004          * Interrupts blocked.  Wait for unblock.
2005          */
2006         if (!svm->vcpu.arch.interrupt_window_open &&
2007             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
2008                 svm_set_vintr(svm);
2009         else
2010                 svm_clear_vintr(svm);
2011 }
2012
2013 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2014 {
2015         return 0;
2016 }
2017
2018 static void save_db_regs(unsigned long *db_regs)
2019 {
2020         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
2021         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
2022         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
2023         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
2024 }
2025
2026 static void load_db_regs(unsigned long *db_regs)
2027 {
2028         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
2029         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
2030         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
2031         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
2032 }
2033
2034 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2035 {
2036         force_new_asid(vcpu);
2037 }
2038
2039 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2040 {
2041 }
2042
2043 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2044 {
2045         struct vcpu_svm *svm = to_svm(vcpu);
2046
2047         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2048                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2049                 kvm_lapic_set_tpr(vcpu, cr8);
2050         }
2051 }
2052
2053 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2054 {
2055         struct vcpu_svm *svm = to_svm(vcpu);
2056         u64 cr8;
2057
2058         if (!irqchip_in_kernel(vcpu->kvm))
2059                 return;
2060
2061         cr8 = kvm_get_cr8(vcpu);
2062         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2063         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2064 }
2065
2066 #ifdef CONFIG_X86_64
2067 #define R "r"
2068 #else
2069 #define R "e"
2070 #endif
2071
2072 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2073 {
2074         struct vcpu_svm *svm = to_svm(vcpu);
2075         u16 fs_selector;
2076         u16 gs_selector;
2077         u16 ldt_selector;
2078
2079         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2080         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2081         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2082
2083         pre_svm_run(svm);
2084
2085         sync_lapic_to_cr8(vcpu);
2086
2087         save_host_msrs(vcpu);
2088         fs_selector = kvm_read_fs();
2089         gs_selector = kvm_read_gs();
2090         ldt_selector = kvm_read_ldt();
2091         svm->host_cr2 = kvm_read_cr2();
2092         svm->host_dr6 = read_dr6();
2093         svm->host_dr7 = read_dr7();
2094         if (!is_nested(svm))
2095                 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2096         /* required for live migration with NPT */
2097         if (npt_enabled)
2098                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2099
2100         if (svm->vmcb->save.dr7 & 0xff) {
2101                 write_dr7(0);
2102                 save_db_regs(svm->host_db_regs);
2103                 load_db_regs(svm->db_regs);
2104         }
2105
2106         clgi();
2107
2108         local_irq_enable();
2109
2110         asm volatile (
2111                 "push %%"R"bp; \n\t"
2112                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2113                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2114                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2115                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2116                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2117                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2118 #ifdef CONFIG_X86_64
2119                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2120                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2121                 "mov %c[r10](%[svm]), %%r10 \n\t"
2122                 "mov %c[r11](%[svm]), %%r11 \n\t"
2123                 "mov %c[r12](%[svm]), %%r12 \n\t"
2124                 "mov %c[r13](%[svm]), %%r13 \n\t"
2125                 "mov %c[r14](%[svm]), %%r14 \n\t"
2126                 "mov %c[r15](%[svm]), %%r15 \n\t"
2127 #endif
2128
2129                 /* Enter guest mode */
2130                 "push %%"R"ax \n\t"
2131                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2132                 __ex(SVM_VMLOAD) "\n\t"
2133                 __ex(SVM_VMRUN) "\n\t"
2134                 __ex(SVM_VMSAVE) "\n\t"
2135                 "pop %%"R"ax \n\t"
2136
2137                 /* Save guest registers, load host registers */
2138                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2139                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2140                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2141                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2142                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2143                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2144 #ifdef CONFIG_X86_64
2145                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2146                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2147                 "mov %%r10, %c[r10](%[svm]) \n\t"
2148                 "mov %%r11, %c[r11](%[svm]) \n\t"
2149                 "mov %%r12, %c[r12](%[svm]) \n\t"
2150                 "mov %%r13, %c[r13](%[svm]) \n\t"
2151                 "mov %%r14, %c[r14](%[svm]) \n\t"
2152                 "mov %%r15, %c[r15](%[svm]) \n\t"
2153 #endif
2154                 "pop %%"R"bp"
2155                 :
2156                 : [svm]"a"(svm),
2157                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2158                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2159                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2160                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2161                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2162                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2163                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2164 #ifdef CONFIG_X86_64
2165                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2166                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2167                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2168                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2169                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2170                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2171                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2172                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2173 #endif
2174                 : "cc", "memory"
2175                 , R"bx", R"cx", R"dx", R"si", R"di"
2176 #ifdef CONFIG_X86_64
2177                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2178 #endif
2179                 );
2180
2181         if ((svm->vmcb->save.dr7 & 0xff))
2182                 load_db_regs(svm->host_db_regs);
2183
2184         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2185         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2186         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2187         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2188
2189         write_dr6(svm->host_dr6);
2190         write_dr7(svm->host_dr7);
2191         kvm_write_cr2(svm->host_cr2);
2192
2193         kvm_load_fs(fs_selector);
2194         kvm_load_gs(gs_selector);
2195         kvm_load_ldt(ldt_selector);
2196         load_host_msrs(vcpu);
2197
2198         reload_tss(vcpu);
2199
2200         local_irq_disable();
2201
2202         stgi();
2203
2204         sync_cr8_to_lapic(vcpu);
2205
2206         svm->next_rip = 0;
2207 }
2208
2209 #undef R
2210
2211 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2212 {
2213         struct vcpu_svm *svm = to_svm(vcpu);
2214
2215         if (npt_enabled) {
2216                 svm->vmcb->control.nested_cr3 = root;
2217                 force_new_asid(vcpu);
2218                 return;
2219         }
2220
2221         svm->vmcb->save.cr3 = root;
2222         force_new_asid(vcpu);
2223
2224         if (vcpu->fpu_active) {
2225                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2226                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2227                 vcpu->fpu_active = 0;
2228         }
2229 }
2230
2231 static int is_disabled(void)
2232 {
2233         u64 vm_cr;
2234
2235         rdmsrl(MSR_VM_CR, vm_cr);
2236         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2237                 return 1;
2238
2239         return 0;
2240 }
2241
2242 static void
2243 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2244 {
2245         /*
2246          * Patch in the VMMCALL instruction:
2247          */
2248         hypercall[0] = 0x0f;
2249         hypercall[1] = 0x01;
2250         hypercall[2] = 0xd9;
2251 }
2252
2253 static void svm_check_processor_compat(void *rtn)
2254 {
2255         *(int *)rtn = 0;
2256 }
2257
2258 static bool svm_cpu_has_accelerated_tpr(void)
2259 {
2260         return false;
2261 }
2262
2263 static int get_npt_level(void)
2264 {
2265 #ifdef CONFIG_X86_64
2266         return PT64_ROOT_LEVEL;
2267 #else
2268         return PT32E_ROOT_LEVEL;
2269 #endif
2270 }
2271
2272 static int svm_get_mt_mask_shift(void)
2273 {
2274         return 0;
2275 }
2276
2277 static struct kvm_x86_ops svm_x86_ops = {
2278         .cpu_has_kvm_support = has_svm,
2279         .disabled_by_bios = is_disabled,
2280         .hardware_setup = svm_hardware_setup,
2281         .hardware_unsetup = svm_hardware_unsetup,
2282         .check_processor_compatibility = svm_check_processor_compat,
2283         .hardware_enable = svm_hardware_enable,
2284         .hardware_disable = svm_hardware_disable,
2285         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2286
2287         .vcpu_create = svm_create_vcpu,
2288         .vcpu_free = svm_free_vcpu,
2289         .vcpu_reset = svm_vcpu_reset,
2290
2291         .prepare_guest_switch = svm_prepare_guest_switch,
2292         .vcpu_load = svm_vcpu_load,
2293         .vcpu_put = svm_vcpu_put,
2294
2295         .set_guest_debug = svm_guest_debug,
2296         .get_msr = svm_get_msr,
2297         .set_msr = svm_set_msr,
2298         .get_segment_base = svm_get_segment_base,
2299         .get_segment = svm_get_segment,
2300         .set_segment = svm_set_segment,
2301         .get_cpl = svm_get_cpl,
2302         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2303         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2304         .set_cr0 = svm_set_cr0,
2305         .set_cr3 = svm_set_cr3,
2306         .set_cr4 = svm_set_cr4,
2307         .set_efer = svm_set_efer,
2308         .get_idt = svm_get_idt,
2309         .set_idt = svm_set_idt,
2310         .get_gdt = svm_get_gdt,
2311         .set_gdt = svm_set_gdt,
2312         .get_dr = svm_get_dr,
2313         .set_dr = svm_set_dr,
2314         .get_rflags = svm_get_rflags,
2315         .set_rflags = svm_set_rflags,
2316
2317         .tlb_flush = svm_flush_tlb,
2318
2319         .run = svm_vcpu_run,
2320         .handle_exit = handle_exit,
2321         .skip_emulated_instruction = skip_emulated_instruction,
2322         .patch_hypercall = svm_patch_hypercall,
2323         .get_irq = svm_get_irq,
2324         .set_irq = svm_set_irq,
2325         .queue_exception = svm_queue_exception,
2326         .exception_injected = svm_exception_injected,
2327         .inject_pending_irq = svm_intr_assist,
2328         .inject_pending_vectors = do_interrupt_requests,
2329
2330         .set_tss_addr = svm_set_tss_addr,
2331         .get_tdp_level = get_npt_level,
2332         .get_mt_mask_shift = svm_get_mt_mask_shift,
2333 };
2334
2335 static int __init svm_init(void)
2336 {
2337         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2338                               THIS_MODULE);
2339 }
2340
2341 static void __exit svm_exit(void)
2342 {
2343         kvm_exit();
2344 }
2345
2346 module_init(svm_init)
2347 module_exit(svm_exit)