arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) "SVM: " fmt
  19
  20 #include <linux/kvm_host.h>
  21
  22 #include "irq.h"
  23 #include "mmu.h"
  24 #include "kvm_cache_regs.h"
  25 #include "x86.h"
  26 #include "cpuid.h"
  27 #include "pmu.h"
  28
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/kernel.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/highmem.h>
  34 #include <linux/sched.h>
  35 #include <linux/trace_events.h>
  36 #include <linux/slab.h>
  37 #include <linux/amd-iommu.h>
  38 #include <linux/hashtable.h>
  39 #include <linux/frame.h>
  40 #include <linux/psp-sev.h>
  41 #include <linux/file.h>
  42 #include <linux/pagemap.h>
  43 #include <linux/swap.h>
  44
  45 #include <asm/apic.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/desc.h>
  49 #include <asm/debugreg.h>
  50 #include <asm/kvm_para.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/spec-ctrl.h>
  53
  54 #include <asm/virtext.h>
  55 #include "trace.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id svm_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_SVM),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  67
  68 #define IOPM_ALLOC_ORDER 2
  69 #define MSRPM_ALLOC_ORDER 1
  70
  71 #define SEG_TYPE_LDT 2
  72 #define SEG_TYPE_BUSY_TSS16 3
  73
  74 #define SVM_FEATURE_NPT            (1 <<  0)
  75 #define SVM_FEATURE_LBRV           (1 <<  1)
  76 #define SVM_FEATURE_SVML           (1 <<  2)
  77 #define SVM_FEATURE_NRIP           (1 <<  3)
  78 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  79 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  80 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  81 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  82 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  83
  84 #define SVM_AVIC_DOORBELL       0xc001011b
  85
  86 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  87 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  88 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  89
  90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  91
  92 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  93 #define TSC_RATIO_MIN           0x0000000000000001ULL
  94 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  95
  96 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
  97
  98 /*
  99  * 0xff is broadcast, so the max index allowed for physical APIC ID
 100  * table is 0xfe.  APIC IDs above 0xff are reserved.
 101  */
 102 #define AVIC_MAX_PHYSICAL_ID_COUNT      255
 103
 104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK          1
 105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK         0xFF0
 106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK         0xFFFFFFFF
 107
 108 /* AVIC GATAG is encoded using VM and VCPU IDs */
 109 #define AVIC_VCPU_ID_BITS               8
 110 #define AVIC_VCPU_ID_MASK               ((1 << AVIC_VCPU_ID_BITS) - 1)
 111
 112 #define AVIC_VM_ID_BITS                 24
 113 #define AVIC_VM_ID_NR                   (1 << AVIC_VM_ID_BITS)
 114 #define AVIC_VM_ID_MASK                 ((1 << AVIC_VM_ID_BITS) - 1)
 115
 116 #define AVIC_GATAG(x, y)                (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
 117                                                 (y & AVIC_VCPU_ID_MASK))
 118 #define AVIC_GATAG_TO_VMID(x)           ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
 119 #define AVIC_GATAG_TO_VCPUID(x)         (x & AVIC_VCPU_ID_MASK)
 120
 121 static bool erratum_383_found __read_mostly;
 122
 123 static const u32 host_save_user_msrs[] = {
 124 #ifdef CONFIG_X86_64
 125         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
 126         MSR_FS_BASE,
 127 #endif
 128         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 129         MSR_TSC_AUX,
 130 };
 131
 132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
 133
 134 struct kvm_sev_info {
 135         bool active;            /* SEV enabled guest */
 136         unsigned int asid;      /* ASID used for this guest */
 137         unsigned int handle;    /* SEV firmware handle */
 138         int fd;                 /* SEV device fd */
 139         unsigned long pages_locked; /* Number of pages locked */
 140         struct list_head regions_list;  /* List of registered regions */
 141 };
 142
 143 struct kvm_svm {
 144         struct kvm kvm;
 145
 146         /* Struct members for AVIC */
 147         u32 avic_vm_id;
 148         u32 ldr_mode;
 149         struct page *avic_logical_id_table_page;
 150         struct page *avic_physical_id_table_page;
 151         struct hlist_node hnode;
 152
 153         struct kvm_sev_info sev_info;
 154 };
 155
 156 struct kvm_vcpu;
 157
 158 struct nested_state {
 159         struct vmcb *hsave;
 160         u64 hsave_msr;
 161         u64 vm_cr_msr;
 162         u64 vmcb;
 163
 164         /* These are the merged vectors */
 165         u32 *msrpm;
 166
 167         /* gpa pointers to the real vectors */
 168         u64 vmcb_msrpm;
 169         u64 vmcb_iopm;
 170
 171         /* A VMEXIT is required but not yet emulated */
 172         bool exit_required;
 173
 174         /* cache for intercepts of the guest */
 175         u32 intercept_cr;
 176         u32 intercept_dr;
 177         u32 intercept_exceptions;
 178         u64 intercept;
 179
 180         /* Nested Paging related state */
 181         u64 nested_cr3;
 182 };
 183
 184 #define MSRPM_OFFSETS   16
 185 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 186
 187 /*
 188  * Set osvw_len to higher value when updated Revision Guides
 189  * are published and we know what the new status bits are
 190  */
 191 static uint64_t osvw_len = 4, osvw_status;
 192
 193 struct vcpu_svm {
 194         struct kvm_vcpu vcpu;
 195         struct vmcb *vmcb;
 196         unsigned long vmcb_pa;
 197         struct svm_cpu_data *svm_data;
 198         uint64_t asid_generation;
 199         uint64_t sysenter_esp;
 200         uint64_t sysenter_eip;
 201         uint64_t tsc_aux;
 202
 203         u64 msr_decfg;
 204
 205         u64 next_rip;
 206
 207         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 208         struct {
 209                 u16 fs;
 210                 u16 gs;
 211                 u16 ldt;
 212                 u64 gs_base;
 213         } host;
 214
 215         u64 spec_ctrl;
 216         /*
 217          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 218          * translated into the appropriate L2_CFG bits on the host to
 219          * perform speculative control.
 220          */
 221         u64 virt_spec_ctrl;
 222
 223         u32 *msrpm;
 224
 225         ulong nmi_iret_rip;
 226
 227         struct nested_state nested;
 228
 229         bool nmi_singlestep;
 230         u64 nmi_singlestep_guest_rflags;
 231
 232         unsigned int3_injected;
 233         unsigned long int3_rip;
 234
 235         /* cached guest cpuid flags for faster access */
 236         bool nrips_enabled      : 1;
 237
 238         u32 ldr_reg;
 239         struct page *avic_backing_page;
 240         u64 *avic_physical_id_cache;
 241         bool avic_is_running;
 242
 243         /*
 244          * Per-vcpu list of struct amd_svm_iommu_ir:
 245          * This is used mainly to store interrupt remapping information used
 246          * when update the vcpu affinity. This avoids the need to scan for
 247          * IRTE and try to match ga_tag in the IOMMU driver.
 248          */
 249         struct list_head ir_list;
 250         spinlock_t ir_list_lock;
 251
 252         /* which host CPU was used for running this vcpu */
 253         unsigned int last_cpu;
 254 };
 255
 256 /*
 257  * This is a wrapper of struct amd_iommu_ir_data.
 258  */
 259 struct amd_svm_iommu_ir {
 260         struct list_head node;  /* Used by SVM for per-vcpu ir_list */
 261         void *data;             /* Storing pointer to struct amd_ir_data */
 262 };
 263
 264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 265 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 266
 267 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 268 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 269 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 270 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 271
 272 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 273 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 274
 275 #define MSR_INVALID                     0xffffffffU
 276
 277 static const struct svm_direct_access_msrs {
 278         u32 index;   /* Index of the MSR */
 279         bool always; /* True if intercept is always on */
 280 } direct_access_msrs[] = {
 281         { .index = MSR_STAR,                            .always = true  },
 282         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 283 #ifdef CONFIG_X86_64
 284         { .index = MSR_GS_BASE,                         .always = true  },
 285         { .index = MSR_FS_BASE,                         .always = true  },
 286         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 287         { .index = MSR_LSTAR,                           .always = true  },
 288         { .index = MSR_CSTAR,                           .always = true  },
 289         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 290 #endif
 291         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 292         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 293         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 294         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 295         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 296         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 297         { .index = MSR_INVALID,                         .always = false },
 298 };
 299
 300 /* enable NPT for AMD64 and X86 with PAE */
 301 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 302 static bool npt_enabled = true;
 303 #else
 304 static bool npt_enabled;
 305 #endif
 306
 307 /*
 308  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 309  * pause_filter_count: On processors that support Pause filtering(indicated
 310  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 311  *      count value. On VMRUN this value is loaded into an internal counter.
 312  *      Each time a pause instruction is executed, this counter is decremented
 313  *      until it reaches zero at which time a #VMEXIT is generated if pause
 314  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 315  *      Intercept Filtering for more details.
 316  *      This also indicate if ple logic enabled.
 317  *
 318  * pause_filter_thresh: In addition, some processor families support advanced
 319  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 320  *      the amount of time a guest is allowed to execute in a pause loop.
 321  *      In this mode, a 16-bit pause filter threshold field is added in the
 322  *      VMCB. The threshold value is a cycle count that is used to reset the
 323  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 324  *      count value from VMCB into an internal counter. Then, on each pause
 325  *      instruction the hardware checks the elapsed number of cycles since
 326  *      the most recent pause instruction against the pause filter threshold.
 327  *      If the elapsed cycle count is greater than the pause filter threshold,
 328  *      then the internal pause count is reloaded from the VMCB and execution
 329  *      continues. If the elapsed cycle count is less than the pause filter
 330  *      threshold, then the internal pause count is decremented. If the count
 331  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 332  *      triggered. If advanced pause filtering is supported and pause filter
 333  *      threshold field is set to zero, the filter will operate in the simpler,
 334  *      count only mode.
 335  */
 336
 337 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 338 module_param(pause_filter_thresh, ushort, 0444);
 339
 340 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 341 module_param(pause_filter_count, ushort, 0444);
 342
 343 /* Default doubles per-vcpu window every exit. */
 344 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 345 module_param(pause_filter_count_grow, ushort, 0444);
 346
 347 /* Default resets per-vcpu window every exit to pause_filter_count. */
 348 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 349 module_param(pause_filter_count_shrink, ushort, 0444);
 350
 351 /* Default is to compute the maximum so we can never overflow. */
 352 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 353 module_param(pause_filter_count_max, ushort, 0444);
 354
 355 /* allow nested paging (virtualized MMU) for all guests */
 356 static int npt = true;
 357 module_param(npt, int, S_IRUGO);
 358
 359 /* allow nested virtualization in KVM/SVM */
 360 static int nested = true;
 361 module_param(nested, int, S_IRUGO);
 362
 363 /* enable / disable AVIC */
 364 static int avic;
 365 #ifdef CONFIG_X86_LOCAL_APIC
 366 module_param(avic, int, S_IRUGO);
 367 #endif
 368
 369 /* enable/disable Virtual VMLOAD VMSAVE */
 370 static int vls = true;
 371 module_param(vls, int, 0444);
 372
 373 /* enable/disable Virtual GIF */
 374 static int vgif = true;
 375 module_param(vgif, int, 0444);
 376
 377 /* enable/disable SEV support */
 378 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 379 module_param(sev, int, 0444);
 380
 381 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 382
 383 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 384 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
 385 static void svm_complete_interrupts(struct vcpu_svm *svm);
 386
 387 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 388 static int nested_svm_intercept(struct vcpu_svm *svm);
 389 static int nested_svm_vmexit(struct vcpu_svm *svm);
 390 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 391                                       bool has_error_code, u32 error_code);
 392
 393 enum {
 394         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 395                             pause filter count */
 396         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 397         VMCB_ASID,       /* ASID */
 398         VMCB_INTR,       /* int_ctl, int_vector */
 399         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 400         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 401         VMCB_DR,         /* DR6, DR7 */
 402         VMCB_DT,         /* GDT, IDT */
 403         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 404         VMCB_CR2,        /* CR2 only */
 405         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 406         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
 407                           * AVIC PHYSICAL_TABLE pointer,
 408                           * AVIC LOGICAL_TABLE pointer
 409                           */
 410         VMCB_DIRTY_MAX,
 411 };
 412
 413 /* TPR and CR2 are always written before VMRUN */
 414 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 415
 416 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 417
 418 static unsigned int max_sev_asid;
 419 static unsigned int min_sev_asid;
 420 static unsigned long *sev_asid_bitmap;
 421 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
 422
 423 struct enc_region {
 424         struct list_head list;
 425         unsigned long npages;
 426         struct page **pages;
 427         unsigned long uaddr;
 428         unsigned long size;
 429 };
 430
 431
 432 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 433 {
 434         return container_of(kvm, struct kvm_svm, kvm);
 435 }
 436
 437 static inline bool svm_sev_enabled(void)
 438 {
 439         return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
 440 }
 441
 442 static inline bool sev_guest(struct kvm *kvm)
 443 {
 444 #ifdef CONFIG_KVM_AMD_SEV
 445         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 446
 447         return sev->active;
 448 #else
 449         return false;
 450 #endif
 451 }
 452
 453 static inline int sev_get_asid(struct kvm *kvm)
 454 {
 455         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 456
 457         return sev->asid;
 458 }
 459
 460 static inline void mark_all_dirty(struct vmcb *vmcb)
 461 {
 462         vmcb->control.clean = 0;
 463 }
 464
 465 static inline void mark_all_clean(struct vmcb *vmcb)
 466 {
 467         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 468                                & ~VMCB_ALWAYS_DIRTY_MASK;
 469 }
 470
 471 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 472 {
 473         vmcb->control.clean &= ~(1 << bit);
 474 }
 475
 476 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 477 {
 478         return container_of(vcpu, struct vcpu_svm, vcpu);
 479 }
 480
 481 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 482 {
 483         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 484         mark_dirty(svm->vmcb, VMCB_AVIC);
 485 }
 486
 487 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 488 {
 489         struct vcpu_svm *svm = to_svm(vcpu);
 490         u64 *entry = svm->avic_physical_id_cache;
 491
 492         if (!entry)
 493                 return false;
 494
 495         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 496 }
 497
 498 static void recalc_intercepts(struct vcpu_svm *svm)
 499 {
 500         struct vmcb_control_area *c, *h;
 501         struct nested_state *g;
 502
 503         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 504
 505         if (!is_guest_mode(&svm->vcpu))
 506                 return;
 507
 508         c = &svm->vmcb->control;
 509         h = &svm->nested.hsave->control;
 510         g = &svm->nested;
 511
 512         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 513         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 514         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 515         c->intercept = h->intercept | g->intercept;
 516 }
 517
 518 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 519 {
 520         if (is_guest_mode(&svm->vcpu))
 521                 return svm->nested.hsave;
 522         else
 523                 return svm->vmcb;
 524 }
 525
 526 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 527 {
 528         struct vmcb *vmcb = get_host_vmcb(svm);
 529
 530         vmcb->control.intercept_cr |= (1U << bit);
 531
 532         recalc_intercepts(svm);
 533 }
 534
 535 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 536 {
 537         struct vmcb *vmcb = get_host_vmcb(svm);
 538
 539         vmcb->control.intercept_cr &= ~(1U << bit);
 540
 541         recalc_intercepts(svm);
 542 }
 543
 544 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 545 {
 546         struct vmcb *vmcb = get_host_vmcb(svm);
 547
 548         return vmcb->control.intercept_cr & (1U << bit);
 549 }
 550
 551 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 552 {
 553         struct vmcb *vmcb = get_host_vmcb(svm);
 554
 555         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
 556                 | (1 << INTERCEPT_DR1_READ)
 557                 | (1 << INTERCEPT_DR2_READ)
 558                 | (1 << INTERCEPT_DR3_READ)
 559                 | (1 << INTERCEPT_DR4_READ)
 560                 | (1 << INTERCEPT_DR5_READ)
 561                 | (1 << INTERCEPT_DR6_READ)
 562                 | (1 << INTERCEPT_DR7_READ)
 563                 | (1 << INTERCEPT_DR0_WRITE)
 564                 | (1 << INTERCEPT_DR1_WRITE)
 565                 | (1 << INTERCEPT_DR2_WRITE)
 566                 | (1 << INTERCEPT_DR3_WRITE)
 567                 | (1 << INTERCEPT_DR4_WRITE)
 568                 | (1 << INTERCEPT_DR5_WRITE)
 569                 | (1 << INTERCEPT_DR6_WRITE)
 570                 | (1 << INTERCEPT_DR7_WRITE);
 571
 572         recalc_intercepts(svm);
 573 }
 574
 575 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 576 {
 577         struct vmcb *vmcb = get_host_vmcb(svm);
 578
 579         vmcb->control.intercept_dr = 0;
 580
 581         recalc_intercepts(svm);
 582 }
 583
 584 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 585 {
 586         struct vmcb *vmcb = get_host_vmcb(svm);
 587
 588         vmcb->control.intercept_exceptions |= (1U << bit);
 589
 590         recalc_intercepts(svm);
 591 }
 592
 593 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 594 {
 595         struct vmcb *vmcb = get_host_vmcb(svm);
 596
 597         vmcb->control.intercept_exceptions &= ~(1U << bit);
 598
 599         recalc_intercepts(svm);
 600 }
 601
 602 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 603 {
 604         struct vmcb *vmcb = get_host_vmcb(svm);
 605
 606         vmcb->control.intercept |= (1ULL << bit);
 607
 608         recalc_intercepts(svm);
 609 }
 610
 611 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 612 {
 613         struct vmcb *vmcb = get_host_vmcb(svm);
 614
 615         vmcb->control.intercept &= ~(1ULL << bit);
 616
 617         recalc_intercepts(svm);
 618 }
 619
 620 static inline bool vgif_enabled(struct vcpu_svm *svm)
 621 {
 622         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 623 }
 624
 625 static inline void enable_gif(struct vcpu_svm *svm)
 626 {
 627         if (vgif_enabled(svm))
 628                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 629         else
 630                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 631 }
 632
 633 static inline void disable_gif(struct vcpu_svm *svm)
 634 {
 635         if (vgif_enabled(svm))
 636                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 637         else
 638                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 639 }
 640
 641 static inline bool gif_set(struct vcpu_svm *svm)
 642 {
 643         if (vgif_enabled(svm))
 644                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 645         else
 646                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 647 }
 648
 649 static unsigned long iopm_base;
 650
 651 struct kvm_ldttss_desc {
 652         u16 limit0;
 653         u16 base0;
 654         unsigned base1:8, type:5, dpl:2, p:1;
 655         unsigned limit1:4, zero0:3, g:1, base2:8;
 656         u32 base3;
 657         u32 zero1;
 658 } __attribute__((packed));
 659
 660 struct svm_cpu_data {
 661         int cpu;
 662
 663         u64 asid_generation;
 664         u32 max_asid;
 665         u32 next_asid;
 666         u32 min_asid;
 667         struct kvm_ldttss_desc *tss_desc;
 668
 669         struct page *save_area;
 670         struct vmcb *current_vmcb;
 671
 672         /* index = sev_asid, value = vmcb pointer */
 673         struct vmcb **sev_vmcbs;
 674 };
 675
 676 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 677
 678 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 679
 680 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 681 #define MSRS_RANGE_SIZE 2048
 682 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 683
 684 static u32 svm_msrpm_offset(u32 msr)
 685 {
 686         u32 offset;
 687         int i;
 688
 689         for (i = 0; i < NUM_MSR_MAPS; i++) {
 690                 if (msr < msrpm_ranges[i] ||
 691                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 692                         continue;
 693
 694                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 695                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 696
 697                 /* Now we have the u8 offset - but need the u32 offset */
 698                 return offset / 4;
 699         }
 700
 701         /* MSR not in any range */
 702         return MSR_INVALID;
 703 }
 704
 705 #define MAX_INST_SIZE 15
 706
 707 static inline void clgi(void)
 708 {
 709         asm volatile (__ex("clgi"));
 710 }
 711
 712 static inline void stgi(void)
 713 {
 714         asm volatile (__ex("stgi"));
 715 }
 716
 717 static inline void invlpga(unsigned long addr, u32 asid)
 718 {
 719         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
 720 }
 721
 722 static int get_npt_level(struct kvm_vcpu *vcpu)
 723 {
 724 #ifdef CONFIG_X86_64
 725         return PT64_ROOT_4LEVEL;
 726 #else
 727         return PT32E_ROOT_LEVEL;
 728 #endif
 729 }
 730
 731 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 732 {
 733         vcpu->arch.efer = efer;
 734         if (!npt_enabled && !(efer & EFER_LMA))
 735                 efer &= ~EFER_LME;
 736
 737         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 738         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 739 }
 740
 741 static int is_external_interrupt(u32 info)
 742 {
 743         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 744         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 745 }
 746
 747 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 748 {
 749         struct vcpu_svm *svm = to_svm(vcpu);
 750         u32 ret = 0;
 751
 752         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 753                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 754         return ret;
 755 }
 756
 757 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 758 {
 759         struct vcpu_svm *svm = to_svm(vcpu);
 760
 761         if (mask == 0)
 762                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 763         else
 764                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 765
 766 }
 767
 768 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 769 {
 770         struct vcpu_svm *svm = to_svm(vcpu);
 771
 772         if (svm->vmcb->control.next_rip != 0) {
 773                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 774                 svm->next_rip = svm->vmcb->control.next_rip;
 775         }
 776
 777         if (!svm->next_rip) {
 778                 if (kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 779                                 EMULATE_DONE)
 780                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 781                 return;
 782         }
 783         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 784                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 785                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 786
 787         kvm_rip_write(vcpu, svm->next_rip);
 788         svm_set_interrupt_shadow(vcpu, 0);
 789 }
 790
 791 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 792 {
 793         struct vcpu_svm *svm = to_svm(vcpu);
 794         unsigned nr = vcpu->arch.exception.nr;
 795         bool has_error_code = vcpu->arch.exception.has_error_code;
 796         bool reinject = vcpu->arch.exception.injected;
 797         u32 error_code = vcpu->arch.exception.error_code;
 798
 799         /*
 800          * If we are within a nested VM we'd better #VMEXIT and let the guest
 801          * handle the exception
 802          */
 803         if (!reinject &&
 804             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 805                 return;
 806
 807         kvm_deliver_exception_payload(&svm->vcpu);
 808
 809         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 810                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 811
 812                 /*
 813                  * For guest debugging where we have to reinject #BP if some
 814                  * INT3 is guest-owned:
 815                  * Emulate nRIP by moving RIP forward. Will fail if injection
 816                  * raises a fault that is not intercepted. Still better than
 817                  * failing in all cases.
 818                  */
 819                 skip_emulated_instruction(&svm->vcpu);
 820                 rip = kvm_rip_read(&svm->vcpu);
 821                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 822                 svm->int3_injected = rip - old_rip;
 823         }
 824
 825         svm->vmcb->control.event_inj = nr
 826                 | SVM_EVTINJ_VALID
 827                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 828                 | SVM_EVTINJ_TYPE_EXEPT;
 829         svm->vmcb->control.event_inj_err = error_code;
 830 }
 831
 832 static void svm_init_erratum_383(void)
 833 {
 834         u32 low, high;
 835         int err;
 836         u64 val;
 837
 838         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 839                 return;
 840
 841         /* Use _safe variants to not break nested virtualization */
 842         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 843         if (err)
 844                 return;
 845
 846         val |= (1ULL << 47);
 847
 848         low  = lower_32_bits(val);
 849         high = upper_32_bits(val);
 850
 851         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 852
 853         erratum_383_found = true;
 854 }
 855
 856 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 857 {
 858         /*
 859          * Guests should see errata 400 and 415 as fixed (assuming that
 860          * HLT and IO instructions are intercepted).
 861          */
 862         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 863         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 864
 865         /*
 866          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 867          * all osvw.status bits inside that length, including bit 0 (which is
 868          * reserved for erratum 298), are valid. However, if host processor's
 869          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 870          * be conservative here and therefore we tell the guest that erratum 298
 871          * is present (because we really don't know).
 872          */
 873         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 874                 vcpu->arch.osvw.status |= 1;
 875 }
 876
 877 static int has_svm(void)
 878 {
 879         const char *msg;
 880
 881         if (!cpu_has_svm(&msg)) {
 882                 printk(KERN_INFO "has_svm: %s\n", msg);
 883                 return 0;
 884         }
 885
 886         return 1;
 887 }
 888
 889 static void svm_hardware_disable(void)
 890 {
 891         /* Make sure we clean up behind us */
 892         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 893                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 894
 895         cpu_svm_disable();
 896
 897         amd_pmu_disable_virt();
 898 }
 899
 900 static int svm_hardware_enable(void)
 901 {
 902
 903         struct svm_cpu_data *sd;
 904         uint64_t efer;
 905         struct desc_struct *gdt;
 906         int me = raw_smp_processor_id();
 907
 908         rdmsrl(MSR_EFER, efer);
 909         if (efer & EFER_SVME)
 910                 return -EBUSY;
 911
 912         if (!has_svm()) {
 913                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 914                 return -EINVAL;
 915         }
 916         sd = per_cpu(svm_data, me);
 917         if (!sd) {
 918                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 919                 return -EINVAL;
 920         }
 921
 922         sd->asid_generation = 1;
 923         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 924         sd->next_asid = sd->max_asid + 1;
 925         sd->min_asid = max_sev_asid + 1;
 926
 927         gdt = get_current_gdt_rw();
 928         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 929
 930         wrmsrl(MSR_EFER, efer | EFER_SVME);
 931
 932         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 933
 934         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 935                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 936                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 937         }
 938
 939
 940         /*
 941          * Get OSVW bits.
 942          *
 943          * Note that it is possible to have a system with mixed processor
 944          * revisions and therefore different OSVW bits. If bits are not the same
 945          * on different processors then choose the worst case (i.e. if erratum
 946          * is present on one processor and not on another then assume that the
 947          * erratum is present everywhere).
 948          */
 949         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 950                 uint64_t len, status = 0;
 951                 int err;
 952
 953                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 954                 if (!err)
 955                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 956                                                       &err);
 957
 958                 if (err)
 959                         osvw_status = osvw_len = 0;
 960                 else {
 961                         if (len < osvw_len)
 962                                 osvw_len = len;
 963                         osvw_status |= status;
 964                         osvw_status &= (1ULL << osvw_len) - 1;
 965                 }
 966         } else
 967                 osvw_status = osvw_len = 0;
 968
 969         svm_init_erratum_383();
 970
 971         amd_pmu_enable_virt();
 972
 973         return 0;
 974 }
 975
 976 static void svm_cpu_uninit(int cpu)
 977 {
 978         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 979
 980         if (!sd)
 981                 return;
 982
 983         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 984         kfree(sd->sev_vmcbs);
 985         __free_page(sd->save_area);
 986         kfree(sd);
 987 }
 988
 989 static int svm_cpu_init(int cpu)
 990 {
 991         struct svm_cpu_data *sd;
 992         int r;
 993
 994         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 995         if (!sd)
 996                 return -ENOMEM;
 997         sd->cpu = cpu;
 998         r = -ENOMEM;
 999         sd->save_area = alloc_page(GFP_KERNEL);
1000         if (!sd->save_area)
1001                 goto err_1;
1002
1003         if (svm_sev_enabled()) {
1004                 r = -ENOMEM;
1005                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
1006                                               sizeof(void *),
1007                                               GFP_KERNEL);
1008                 if (!sd->sev_vmcbs)
1009                         goto err_1;
1010         }
1011
1012         per_cpu(svm_data, cpu) = sd;
1013
1014         return 0;
1015
1016 err_1:
1017         kfree(sd);
1018         return r;
1019
1020 }
1021
1022 static bool valid_msr_intercept(u32 index)
1023 {
1024         int i;
1025
1026         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1027                 if (direct_access_msrs[i].index == index)
1028                         return true;
1029
1030         return false;
1031 }
1032
1033 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1034 {
1035         u8 bit_write;
1036         unsigned long tmp;
1037         u32 offset;
1038         u32 *msrpm;
1039
1040         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1041                                       to_svm(vcpu)->msrpm;
1042
1043         offset    = svm_msrpm_offset(msr);
1044         bit_write = 2 * (msr & 0x0f) + 1;
1045         tmp       = msrpm[offset];
1046
1047         BUG_ON(offset == MSR_INVALID);
1048
1049         return !!test_bit(bit_write,  &tmp);
1050 }
1051
1052 static void set_msr_interception(u32 *msrpm, unsigned msr,
1053                                  int read, int write)
1054 {
1055         u8 bit_read, bit_write;
1056         unsigned long tmp;
1057         u32 offset;
1058
1059         /*
1060          * If this warning triggers extend the direct_access_msrs list at the
1061          * beginning of the file
1062          */
1063         WARN_ON(!valid_msr_intercept(msr));
1064
1065         offset    = svm_msrpm_offset(msr);
1066         bit_read  = 2 * (msr & 0x0f);
1067         bit_write = 2 * (msr & 0x0f) + 1;
1068         tmp       = msrpm[offset];
1069
1070         BUG_ON(offset == MSR_INVALID);
1071
1072         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
1073         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1074
1075         msrpm[offset] = tmp;
1076 }
1077
1078 static void svm_vcpu_init_msrpm(u32 *msrpm)
1079 {
1080         int i;
1081
1082         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1083
1084         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1085                 if (!direct_access_msrs[i].always)
1086                         continue;
1087
1088                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1089         }
1090 }
1091
1092 static void add_msr_offset(u32 offset)
1093 {
1094         int i;
1095
1096         for (i = 0; i < MSRPM_OFFSETS; ++i) {
1097
1098                 /* Offset already in list? */
1099                 if (msrpm_offsets[i] == offset)
1100                         return;
1101
1102                 /* Slot used by another offset? */
1103                 if (msrpm_offsets[i] != MSR_INVALID)
1104                         continue;
1105
1106                 /* Add offset to list */
1107                 msrpm_offsets[i] = offset;
1108
1109                 return;
1110         }
1111
1112         /*
1113          * If this BUG triggers the msrpm_offsets table has an overflow. Just
1114          * increase MSRPM_OFFSETS in this case.
1115          */
1116         BUG();
1117 }
1118
1119 static void init_msrpm_offsets(void)
1120 {
1121         int i;
1122
1123         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1124
1125         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1126                 u32 offset;
1127
1128                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1129                 BUG_ON(offset == MSR_INVALID);
1130
1131                 add_msr_offset(offset);
1132         }
1133 }
1134
1135 static void svm_enable_lbrv(struct vcpu_svm *svm)
1136 {
1137         u32 *msrpm = svm->msrpm;
1138
1139         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1140         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1141         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1142         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1143         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1144 }
1145
1146 static void svm_disable_lbrv(struct vcpu_svm *svm)
1147 {
1148         u32 *msrpm = svm->msrpm;
1149
1150         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1151         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1152         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1153         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1154         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1155 }
1156
1157 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1158 {
1159         svm->nmi_singlestep = false;
1160
1161         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1162                 /* Clear our flags if they were not set by the guest */
1163                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1164                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1165                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1166                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1167         }
1168 }
1169
1170 /* Note:
1171  * This hash table is used to map VM_ID to a struct kvm_svm,
1172  * when handling AMD IOMMU GALOG notification to schedule in
1173  * a particular vCPU.
1174  */
1175 #define SVM_VM_DATA_HASH_BITS   8
1176 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1177 static u32 next_vm_id = 0;
1178 static bool next_vm_id_wrapped = 0;
1179 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1180
1181 /* Note:
1182  * This function is called from IOMMU driver to notify
1183  * SVM to schedule in a particular vCPU of a particular VM.
1184  */
1185 static int avic_ga_log_notifier(u32 ga_tag)
1186 {
1187         unsigned long flags;
1188         struct kvm_svm *kvm_svm;
1189         struct kvm_vcpu *vcpu = NULL;
1190         u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1191         u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1192
1193         pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1194
1195         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1196         hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1197                 if (kvm_svm->avic_vm_id != vm_id)
1198                         continue;
1199                 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1200                 break;
1201         }
1202         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1203
1204         /* Note:
1205          * At this point, the IOMMU should have already set the pending
1206          * bit in the vAPIC backing page. So, we just need to schedule
1207          * in the vcpu.
1208          */
1209         if (vcpu)
1210                 kvm_vcpu_wake_up(vcpu);
1211
1212         return 0;
1213 }
1214
1215 static __init int sev_hardware_setup(void)
1216 {
1217         struct sev_user_data_status *status;
1218         int rc;
1219
1220         /* Maximum number of encrypted guests supported simultaneously */
1221         max_sev_asid = cpuid_ecx(0x8000001F);
1222
1223         if (!max_sev_asid)
1224                 return 1;
1225
1226         /* Minimum ASID value that should be used for SEV guest */
1227         min_sev_asid = cpuid_edx(0x8000001F);
1228
1229         /* Initialize SEV ASID bitmap */
1230         sev_asid_bitmap = bitmap_zalloc(max_sev_asid, GFP_KERNEL);
1231         if (!sev_asid_bitmap)
1232                 return 1;
1233
1234         status = kmalloc(sizeof(*status), GFP_KERNEL);
1235         if (!status)
1236                 return 1;
1237
1238         /*
1239          * Check SEV platform status.
1240          *
1241          * PLATFORM_STATUS can be called in any state, if we failed to query
1242          * the PLATFORM status then either PSP firmware does not support SEV
1243          * feature or SEV firmware is dead.
1244          */
1245         rc = sev_platform_status(status, NULL);
1246         if (rc)
1247                 goto err;
1248
1249         pr_info("SEV supported\n");
1250
1251 err:
1252         kfree(status);
1253         return rc;
1254 }
1255
1256 static void grow_ple_window(struct kvm_vcpu *vcpu)
1257 {
1258         struct vcpu_svm *svm = to_svm(vcpu);
1259         struct vmcb_control_area *control = &svm->vmcb->control;
1260         int old = control->pause_filter_count;
1261
1262         control->pause_filter_count = __grow_ple_window(old,
1263                                                         pause_filter_count,
1264                                                         pause_filter_count_grow,
1265                                                         pause_filter_count_max);
1266
1267         if (control->pause_filter_count != old)
1268                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1269
1270         trace_kvm_ple_window_grow(vcpu->vcpu_id,
1271                                   control->pause_filter_count, old);
1272 }
1273
1274 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1275 {
1276         struct vcpu_svm *svm = to_svm(vcpu);
1277         struct vmcb_control_area *control = &svm->vmcb->control;
1278         int old = control->pause_filter_count;
1279
1280         control->pause_filter_count =
1281                                 __shrink_ple_window(old,
1282                                                     pause_filter_count,
1283                                                     pause_filter_count_shrink,
1284                                                     pause_filter_count);
1285         if (control->pause_filter_count != old)
1286                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1287
1288         trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1289                                     control->pause_filter_count, old);
1290 }
1291
1292 static __init int svm_hardware_setup(void)
1293 {
1294         int cpu;
1295         struct page *iopm_pages;
1296         void *iopm_va;
1297         int r;
1298
1299         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1300
1301         if (!iopm_pages)
1302                 return -ENOMEM;
1303
1304         iopm_va = page_address(iopm_pages);
1305         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1306         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1307
1308         init_msrpm_offsets();
1309
1310         if (boot_cpu_has(X86_FEATURE_NX))
1311                 kvm_enable_efer_bits(EFER_NX);
1312
1313         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1314                 kvm_enable_efer_bits(EFER_FFXSR);
1315
1316         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1317                 kvm_has_tsc_control = true;
1318                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1319                 kvm_tsc_scaling_ratio_frac_bits = 32;
1320         }
1321
1322         /* Check for pause filtering support */
1323         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1324                 pause_filter_count = 0;
1325                 pause_filter_thresh = 0;
1326         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1327                 pause_filter_thresh = 0;
1328         }
1329
1330         if (nested) {
1331                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1332                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1333         }
1334
1335         if (sev) {
1336                 if (boot_cpu_has(X86_FEATURE_SEV) &&
1337                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1338                         r = sev_hardware_setup();
1339                         if (r)
1340                                 sev = false;
1341                 } else {
1342                         sev = false;
1343                 }
1344         }
1345
1346         for_each_possible_cpu(cpu) {
1347                 r = svm_cpu_init(cpu);
1348                 if (r)
1349                         goto err;
1350         }
1351
1352         if (!boot_cpu_has(X86_FEATURE_NPT))
1353                 npt_enabled = false;
1354
1355         if (npt_enabled && !npt) {
1356                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1357                 npt_enabled = false;
1358         }
1359
1360         if (npt_enabled) {
1361                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1362                 kvm_enable_tdp();
1363         } else
1364                 kvm_disable_tdp();
1365
1366         if (avic) {
1367                 if (!npt_enabled ||
1368                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1369                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1370                         avic = false;
1371                 } else {
1372                         pr_info("AVIC enabled\n");
1373
1374                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1375                 }
1376         }
1377
1378         if (vls) {
1379                 if (!npt_enabled ||
1380                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1381                     !IS_ENABLED(CONFIG_X86_64)) {
1382                         vls = false;
1383                 } else {
1384                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1385                 }
1386         }
1387
1388         if (vgif) {
1389                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1390                         vgif = false;
1391                 else
1392                         pr_info("Virtual GIF supported\n");
1393         }
1394
1395         return 0;
1396
1397 err:
1398         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1399         iopm_base = 0;
1400         return r;
1401 }
1402
1403 static __exit void svm_hardware_unsetup(void)
1404 {
1405         int cpu;
1406
1407         if (svm_sev_enabled())
1408                 bitmap_free(sev_asid_bitmap);
1409
1410         for_each_possible_cpu(cpu)
1411                 svm_cpu_uninit(cpu);
1412
1413         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1414         iopm_base = 0;
1415 }
1416
1417 static void init_seg(struct vmcb_seg *seg)
1418 {
1419         seg->selector = 0;
1420         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1421                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1422         seg->limit = 0xffff;
1423         seg->base = 0;
1424 }
1425
1426 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1427 {
1428         seg->selector = 0;
1429         seg->attrib = SVM_SELECTOR_P_MASK | type;
1430         seg->limit = 0xffff;
1431         seg->base = 0;
1432 }
1433
1434 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1435 {
1436         struct vcpu_svm *svm = to_svm(vcpu);
1437
1438         if (is_guest_mode(vcpu))
1439                 return svm->nested.hsave->control.tsc_offset;
1440
1441         return vcpu->arch.tsc_offset;
1442 }
1443
1444 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1445 {
1446         struct vcpu_svm *svm = to_svm(vcpu);
1447         u64 g_tsc_offset = 0;
1448
1449         if (is_guest_mode(vcpu)) {
1450                 /* Write L1's TSC offset.  */
1451                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1452                                svm->nested.hsave->control.tsc_offset;
1453                 svm->nested.hsave->control.tsc_offset = offset;
1454         }
1455
1456         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1457                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1458                                    offset);
1459
1460         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1461
1462         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1463         return svm->vmcb->control.tsc_offset;
1464 }
1465
1466 static void avic_init_vmcb(struct vcpu_svm *svm)
1467 {
1468         struct vmcb *vmcb = svm->vmcb;
1469         struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1470         phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1471         phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1472         phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1473
1474         vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1475         vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1476         vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1477         vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1478         vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1479 }
1480
1481 static void init_vmcb(struct vcpu_svm *svm)
1482 {
1483         struct vmcb_control_area *control = &svm->vmcb->control;
1484         struct vmcb_save_area *save = &svm->vmcb->save;
1485
1486         svm->vcpu.arch.hflags = 0;
1487
1488         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1489         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1490         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1491         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1492         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1493         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1494         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1495                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1496
1497         set_dr_intercepts(svm);
1498
1499         set_exception_intercept(svm, PF_VECTOR);
1500         set_exception_intercept(svm, UD_VECTOR);
1501         set_exception_intercept(svm, MC_VECTOR);
1502         set_exception_intercept(svm, AC_VECTOR);
1503         set_exception_intercept(svm, DB_VECTOR);
1504         /*
1505          * Guest access to VMware backdoor ports could legitimately
1506          * trigger #GP because of TSS I/O permission bitmap.
1507          * We intercept those #GP and allow access to them anyway
1508          * as VMware does.
1509          */
1510         if (enable_vmware_backdoor)
1511                 set_exception_intercept(svm, GP_VECTOR);
1512
1513         set_intercept(svm, INTERCEPT_INTR);
1514         set_intercept(svm, INTERCEPT_NMI);
1515         set_intercept(svm, INTERCEPT_SMI);
1516         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1517         set_intercept(svm, INTERCEPT_RDPMC);
1518         set_intercept(svm, INTERCEPT_CPUID);
1519         set_intercept(svm, INTERCEPT_INVD);
1520         set_intercept(svm, INTERCEPT_INVLPG);
1521         set_intercept(svm, INTERCEPT_INVLPGA);
1522         set_intercept(svm, INTERCEPT_IOIO_PROT);
1523         set_intercept(svm, INTERCEPT_MSR_PROT);
1524         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1525         set_intercept(svm, INTERCEPT_SHUTDOWN);
1526         set_intercept(svm, INTERCEPT_VMRUN);
1527         set_intercept(svm, INTERCEPT_VMMCALL);
1528         set_intercept(svm, INTERCEPT_VMLOAD);
1529         set_intercept(svm, INTERCEPT_VMSAVE);
1530         set_intercept(svm, INTERCEPT_STGI);
1531         set_intercept(svm, INTERCEPT_CLGI);
1532         set_intercept(svm, INTERCEPT_SKINIT);
1533         set_intercept(svm, INTERCEPT_WBINVD);
1534         set_intercept(svm, INTERCEPT_XSETBV);
1535         set_intercept(svm, INTERCEPT_RSM);
1536
1537         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1538                 set_intercept(svm, INTERCEPT_MONITOR);
1539                 set_intercept(svm, INTERCEPT_MWAIT);
1540         }
1541
1542         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1543                 set_intercept(svm, INTERCEPT_HLT);
1544
1545         control->iopm_base_pa = __sme_set(iopm_base);
1546         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1547         control->int_ctl = V_INTR_MASKING_MASK;
1548
1549         init_seg(&save->es);
1550         init_seg(&save->ss);
1551         init_seg(&save->ds);
1552         init_seg(&save->fs);
1553         init_seg(&save->gs);
1554
1555         save->cs.selector = 0xf000;
1556         save->cs.base = 0xffff0000;
1557         /* Executable/Readable Code Segment */
1558         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1559                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1560         save->cs.limit = 0xffff;
1561
1562         save->gdtr.limit = 0xffff;
1563         save->idtr.limit = 0xffff;
1564
1565         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1566         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1567
1568         svm_set_efer(&svm->vcpu, 0);
1569         save->dr6 = 0xffff0ff0;
1570         kvm_set_rflags(&svm->vcpu, 2);
1571         save->rip = 0x0000fff0;
1572         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1573
1574         /*
1575          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1576          * It also updates the guest-visible cr0 value.
1577          */
1578         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1579         kvm_mmu_reset_context(&svm->vcpu);
1580
1581         save->cr4 = X86_CR4_PAE;
1582         /* rdx = ?? */
1583
1584         if (npt_enabled) {
1585                 /* Setup VMCB for Nested Paging */
1586                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1587                 clr_intercept(svm, INTERCEPT_INVLPG);
1588                 clr_exception_intercept(svm, PF_VECTOR);
1589                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1590                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1591                 save->g_pat = svm->vcpu.arch.pat;
1592                 save->cr3 = 0;
1593                 save->cr4 = 0;
1594         }
1595         svm->asid_generation = 0;
1596
1597         svm->nested.vmcb = 0;
1598         svm->vcpu.arch.hflags = 0;
1599
1600         if (pause_filter_count) {
1601                 control->pause_filter_count = pause_filter_count;
1602                 if (pause_filter_thresh)
1603                         control->pause_filter_thresh = pause_filter_thresh;
1604                 set_intercept(svm, INTERCEPT_PAUSE);
1605         } else {
1606                 clr_intercept(svm, INTERCEPT_PAUSE);
1607         }
1608
1609         if (kvm_vcpu_apicv_active(&svm->vcpu))
1610                 avic_init_vmcb(svm);
1611
1612         /*
1613          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1614          * in VMCB and clear intercepts to avoid #VMEXIT.
1615          */
1616         if (vls) {
1617                 clr_intercept(svm, INTERCEPT_VMLOAD);
1618                 clr_intercept(svm, INTERCEPT_VMSAVE);
1619                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1620         }
1621
1622         if (vgif) {
1623                 clr_intercept(svm, INTERCEPT_STGI);
1624                 clr_intercept(svm, INTERCEPT_CLGI);
1625                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1626         }
1627
1628         if (sev_guest(svm->vcpu.kvm)) {
1629                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1630                 clr_exception_intercept(svm, UD_VECTOR);
1631         }
1632
1633         mark_all_dirty(svm->vmcb);
1634
1635         enable_gif(svm);
1636
1637 }
1638
1639 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1640                                        unsigned int index)
1641 {
1642         u64 *avic_physical_id_table;
1643         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1644
1645         if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1646                 return NULL;
1647
1648         avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1649
1650         return &avic_physical_id_table[index];
1651 }
1652
1653 /**
1654  * Note:
1655  * AVIC hardware walks the nested page table to check permissions,
1656  * but does not use the SPA address specified in the leaf page
1657  * table entry since it uses  address in the AVIC_BACKING_PAGE pointer
1658  * field of the VMCB. Therefore, we set up the
1659  * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1660  */
1661 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1662 {
1663         struct kvm *kvm = vcpu->kvm;
1664         int ret = 0;
1665
1666         mutex_lock(&kvm->slots_lock);
1667         if (kvm->arch.apic_access_page_done)
1668                 goto out;
1669
1670         ret = __x86_set_memory_region(kvm,
1671                                       APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1672                                       APIC_DEFAULT_PHYS_BASE,
1673                                       PAGE_SIZE);
1674         if (ret)
1675                 goto out;
1676
1677         kvm->arch.apic_access_page_done = true;
1678 out:
1679         mutex_unlock(&kvm->slots_lock);
1680         return ret;
1681 }
1682
1683 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1684 {
1685         int ret;
1686         u64 *entry, new_entry;
1687         int id = vcpu->vcpu_id;
1688         struct vcpu_svm *svm = to_svm(vcpu);
1689
1690         ret = avic_init_access_page(vcpu);
1691         if (ret)
1692                 return ret;
1693
1694         if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1695                 return -EINVAL;
1696
1697         if (!svm->vcpu.arch.apic->regs)
1698                 return -EINVAL;
1699
1700         svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1701
1702         /* Setting AVIC backing page address in the phy APIC ID table */
1703         entry = avic_get_physical_id_entry(vcpu, id);
1704         if (!entry)
1705                 return -EINVAL;
1706
1707         new_entry = READ_ONCE(*entry);
1708         new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1709                               AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1710                               AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1711         WRITE_ONCE(*entry, new_entry);
1712
1713         svm->avic_physical_id_cache = entry;
1714
1715         return 0;
1716 }
1717
1718 static void __sev_asid_free(int asid)
1719 {
1720         struct svm_cpu_data *sd;
1721         int cpu, pos;
1722
1723         pos = asid - 1;
1724         clear_bit(pos, sev_asid_bitmap);
1725
1726         for_each_possible_cpu(cpu) {
1727                 sd = per_cpu(svm_data, cpu);
1728                 sd->sev_vmcbs[pos] = NULL;
1729         }
1730 }
1731
1732 static void sev_asid_free(struct kvm *kvm)
1733 {
1734         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1735
1736         __sev_asid_free(sev->asid);
1737 }
1738
1739 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1740 {
1741         struct sev_data_decommission *decommission;
1742         struct sev_data_deactivate *data;
1743
1744         if (!handle)
1745                 return;
1746
1747         data = kzalloc(sizeof(*data), GFP_KERNEL);
1748         if (!data)
1749                 return;
1750
1751         /* deactivate handle */
1752         data->handle = handle;
1753         sev_guest_deactivate(data, NULL);
1754
1755         wbinvd_on_all_cpus();
1756         sev_guest_df_flush(NULL);
1757         kfree(data);
1758
1759         decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1760         if (!decommission)
1761                 return;
1762
1763         /* decommission handle */
1764         decommission->handle = handle;
1765         sev_guest_decommission(decommission, NULL);
1766
1767         kfree(decommission);
1768 }
1769
1770 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1771                                     unsigned long ulen, unsigned long *n,
1772                                     int write)
1773 {
1774         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1775         unsigned long npages, npinned, size;
1776         unsigned long locked, lock_limit;
1777         struct page **pages;
1778         unsigned long first, last;
1779
1780         if (ulen == 0 || uaddr + ulen < uaddr)
1781                 return NULL;
1782
1783         /* Calculate number of pages. */
1784         first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1785         last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1786         npages = (last - first + 1);
1787
1788         locked = sev->pages_locked + npages;
1789         lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1790         if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1791                 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1792                 return NULL;
1793         }
1794
1795         /* Avoid using vmalloc for smaller buffers. */
1796         size = npages * sizeof(struct page *);
1797         if (size > PAGE_SIZE)
1798                 pages = vmalloc(size);
1799         else
1800                 pages = kmalloc(size, GFP_KERNEL);
1801
1802         if (!pages)
1803                 return NULL;
1804
1805         /* Pin the user virtual address. */
1806         npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages);
1807         if (npinned != npages) {
1808                 pr_err("SEV: Failure locking %lu pages.\n", npages);
1809                 goto err;
1810         }
1811
1812         *n = npages;
1813         sev->pages_locked = locked;
1814
1815         return pages;
1816
1817 err:
1818         if (npinned > 0)
1819                 release_pages(pages, npinned);
1820
1821         kvfree(pages);
1822         return NULL;
1823 }
1824
1825 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1826                              unsigned long npages)
1827 {
1828         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1829
1830         release_pages(pages, npages);
1831         kvfree(pages);
1832         sev->pages_locked -= npages;
1833 }
1834
1835 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1836 {
1837         uint8_t *page_virtual;
1838         unsigned long i;
1839
1840         if (npages == 0 || pages == NULL)
1841                 return;
1842
1843         for (i = 0; i < npages; i++) {
1844                 page_virtual = kmap_atomic(pages[i]);
1845                 clflush_cache_range(page_virtual, PAGE_SIZE);
1846                 kunmap_atomic(page_virtual);
1847         }
1848 }
1849
1850 static void __unregister_enc_region_locked(struct kvm *kvm,
1851                                            struct enc_region *region)
1852 {
1853         /*
1854          * The guest may change the memory encryption attribute from C=0 -> C=1
1855          * or vice versa for this memory range. Lets make sure caches are
1856          * flushed to ensure that guest data gets written into memory with
1857          * correct C-bit.
1858          */
1859         sev_clflush_pages(region->pages, region->npages);
1860
1861         sev_unpin_memory(kvm, region->pages, region->npages);
1862         list_del(&region->list);
1863         kfree(region);
1864 }
1865
1866 static struct kvm *svm_vm_alloc(void)
1867 {
1868         struct kvm_svm *kvm_svm = vzalloc(sizeof(struct kvm_svm));
1869         return &kvm_svm->kvm;
1870 }
1871
1872 static void svm_vm_free(struct kvm *kvm)
1873 {
1874         vfree(to_kvm_svm(kvm));
1875 }
1876
1877 static void sev_vm_destroy(struct kvm *kvm)
1878 {
1879         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1880         struct list_head *head = &sev->regions_list;
1881         struct list_head *pos, *q;
1882
1883         if (!sev_guest(kvm))
1884                 return;
1885
1886         mutex_lock(&kvm->lock);
1887
1888         /*
1889          * if userspace was terminated before unregistering the memory regions
1890          * then lets unpin all the registered memory.
1891          */
1892         if (!list_empty(head)) {
1893                 list_for_each_safe(pos, q, head) {
1894                         __unregister_enc_region_locked(kvm,
1895                                 list_entry(pos, struct enc_region, list));
1896                 }
1897         }
1898
1899         mutex_unlock(&kvm->lock);
1900
1901         sev_unbind_asid(kvm, sev->handle);
1902         sev_asid_free(kvm);
1903 }
1904
1905 static void avic_vm_destroy(struct kvm *kvm)
1906 {
1907         unsigned long flags;
1908         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1909
1910         if (!avic)
1911                 return;
1912
1913         if (kvm_svm->avic_logical_id_table_page)
1914                 __free_page(kvm_svm->avic_logical_id_table_page);
1915         if (kvm_svm->avic_physical_id_table_page)
1916                 __free_page(kvm_svm->avic_physical_id_table_page);
1917
1918         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1919         hash_del(&kvm_svm->hnode);
1920         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1921 }
1922
1923 static void svm_vm_destroy(struct kvm *kvm)
1924 {
1925         avic_vm_destroy(kvm);
1926         sev_vm_destroy(kvm);
1927 }
1928
1929 static int avic_vm_init(struct kvm *kvm)
1930 {
1931         unsigned long flags;
1932         int err = -ENOMEM;
1933         struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1934         struct kvm_svm *k2;
1935         struct page *p_page;
1936         struct page *l_page;
1937         u32 vm_id;
1938
1939         if (!avic)
1940                 return 0;
1941
1942         /* Allocating physical APIC ID table (4KB) */
1943         p_page = alloc_page(GFP_KERNEL);
1944         if (!p_page)
1945                 goto free_avic;
1946
1947         kvm_svm->avic_physical_id_table_page = p_page;
1948         clear_page(page_address(p_page));
1949
1950         /* Allocating logical APIC ID table (4KB) */
1951         l_page = alloc_page(GFP_KERNEL);
1952         if (!l_page)
1953                 goto free_avic;
1954
1955         kvm_svm->avic_logical_id_table_page = l_page;
1956         clear_page(page_address(l_page));
1957
1958         spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1959  again:
1960         vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1961         if (vm_id == 0) { /* id is 1-based, zero is not okay */
1962                 next_vm_id_wrapped = 1;
1963                 goto again;
1964         }
1965         /* Is it still in use? Only possible if wrapped at least once */
1966         if (next_vm_id_wrapped) {
1967                 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1968                         if (k2->avic_vm_id == vm_id)
1969                                 goto again;
1970                 }
1971         }
1972         kvm_svm->avic_vm_id = vm_id;
1973         hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1974         spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1975
1976         return 0;
1977
1978 free_avic:
1979         avic_vm_destroy(kvm);
1980         return err;
1981 }
1982
1983 static inline int
1984 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1985 {
1986         int ret = 0;
1987         unsigned long flags;
1988         struct amd_svm_iommu_ir *ir;
1989         struct vcpu_svm *svm = to_svm(vcpu);
1990
1991         if (!kvm_arch_has_assigned_device(vcpu->kvm))
1992                 return 0;
1993
1994         /*
1995          * Here, we go through the per-vcpu ir_list to update all existing
1996          * interrupt remapping table entry targeting this vcpu.
1997          */
1998         spin_lock_irqsave(&svm->ir_list_lock, flags);
1999
2000         if (list_empty(&svm->ir_list))
2001                 goto out;
2002
2003         list_for_each_entry(ir, &svm->ir_list, node) {
2004                 ret = amd_iommu_update_ga(cpu, r, ir->data);
2005                 if (ret)
2006                         break;
2007         }
2008 out:
2009         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
2010         return ret;
2011 }
2012
2013 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2014 {
2015         u64 entry;
2016         /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2017         int h_physical_id = kvm_cpu_get_apicid(cpu);
2018         struct vcpu_svm *svm = to_svm(vcpu);
2019
2020         if (!kvm_vcpu_apicv_active(vcpu))
2021                 return;
2022
2023         if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
2024                 return;
2025
2026         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2027         WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2028
2029         entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2030         entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2031
2032         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2033         if (svm->avic_is_running)
2034                 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2035
2036         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2037         avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2038                                         svm->avic_is_running);
2039 }
2040
2041 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2042 {
2043         u64 entry;
2044         struct vcpu_svm *svm = to_svm(vcpu);
2045
2046         if (!kvm_vcpu_apicv_active(vcpu))
2047                 return;
2048
2049         entry = READ_ONCE(*(svm->avic_physical_id_cache));
2050         if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2051                 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2052
2053         entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2054         WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2055 }
2056
2057 /**
2058  * This function is called during VCPU halt/unhalt.
2059  */
2060 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2061 {
2062         struct vcpu_svm *svm = to_svm(vcpu);
2063
2064         svm->avic_is_running = is_run;
2065         if (is_run)
2066                 avic_vcpu_load(vcpu, vcpu->cpu);
2067         else
2068                 avic_vcpu_put(vcpu);
2069 }
2070
2071 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2072 {
2073         struct vcpu_svm *svm = to_svm(vcpu);
2074         u32 dummy;
2075         u32 eax = 1;
2076
2077         vcpu->arch.microcode_version = 0x01000065;
2078         svm->spec_ctrl = 0;
2079         svm->virt_spec_ctrl = 0;
2080
2081         if (!init_event) {
2082                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2083                                            MSR_IA32_APICBASE_ENABLE;
2084                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2085                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2086         }
2087         init_vmcb(svm);
2088
2089         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2090         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
2091
2092         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2093                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2094 }
2095
2096 static int avic_init_vcpu(struct vcpu_svm *svm)
2097 {
2098         int ret;
2099
2100         if (!kvm_vcpu_apicv_active(&svm->vcpu))
2101                 return 0;
2102
2103         ret = avic_init_backing_page(&svm->vcpu);
2104         if (ret)
2105                 return ret;
2106
2107         INIT_LIST_HEAD(&svm->ir_list);
2108         spin_lock_init(&svm->ir_list_lock);
2109
2110         return ret;
2111 }
2112
2113 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2114 {
2115         struct vcpu_svm *svm;
2116         struct page *page;
2117         struct page *msrpm_pages;
2118         struct page *hsave_page;
2119         struct page *nested_msrpm_pages;
2120         int err;
2121
2122         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2123         if (!svm) {
2124                 err = -ENOMEM;
2125                 goto out;
2126         }
2127
2128         svm->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, GFP_KERNEL);
2129         if (!svm->vcpu.arch.guest_fpu) {
2130                 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
2131                 err = -ENOMEM;
2132                 goto free_partial_svm;
2133         }
2134
2135         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2136         if (err)
2137                 goto free_svm;
2138
2139         err = -ENOMEM;
2140         page = alloc_page(GFP_KERNEL);
2141         if (!page)
2142                 goto uninit;
2143
2144         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2145         if (!msrpm_pages)
2146                 goto free_page1;
2147
2148         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2149         if (!nested_msrpm_pages)
2150                 goto free_page2;
2151
2152         hsave_page = alloc_page(GFP_KERNEL);
2153         if (!hsave_page)
2154                 goto free_page3;
2155
2156         err = avic_init_vcpu(svm);
2157         if (err)
2158                 goto free_page4;
2159
2160         /* We initialize this flag to true to make sure that the is_running
2161          * bit would be set the first time the vcpu is loaded.
2162          */
2163         svm->avic_is_running = true;
2164
2165         svm->nested.hsave = page_address(hsave_page);
2166
2167         svm->msrpm = page_address(msrpm_pages);
2168         svm_vcpu_init_msrpm(svm->msrpm);
2169
2170         svm->nested.msrpm = page_address(nested_msrpm_pages);
2171         svm_vcpu_init_msrpm(svm->nested.msrpm);
2172
2173         svm->vmcb = page_address(page);
2174         clear_page(svm->vmcb);
2175         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2176         svm->asid_generation = 0;
2177         init_vmcb(svm);
2178
2179         svm_init_osvw(&svm->vcpu);
2180
2181         return &svm->vcpu;
2182
2183 free_page4:
2184         __free_page(hsave_page);
2185 free_page3:
2186         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2187 free_page2:
2188         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2189 free_page1:
2190         __free_page(page);
2191 uninit:
2192         kvm_vcpu_uninit(&svm->vcpu);
2193 free_svm:
2194         kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2195 free_partial_svm:
2196         kmem_cache_free(kvm_vcpu_cache, svm);
2197 out:
2198         return ERR_PTR(err);
2199 }
2200
2201 static void svm_clear_current_vmcb(struct vmcb *vmcb)
2202 {
2203         int i;
2204
2205         for_each_online_cpu(i)
2206                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
2207 }
2208
2209 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2210 {
2211         struct vcpu_svm *svm = to_svm(vcpu);
2212
2213         /*
2214          * The vmcb page can be recycled, causing a false negative in
2215          * svm_vcpu_load(). So, ensure that no logical CPU has this
2216          * vmcb page recorded as its current vmcb.
2217          */
2218         svm_clear_current_vmcb(svm->vmcb);
2219
2220         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2221         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2222         __free_page(virt_to_page(svm->nested.hsave));
2223         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2224         kvm_vcpu_uninit(vcpu);
2225         kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu);
2226         kmem_cache_free(kvm_vcpu_cache, svm);
2227 }
2228
2229 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2230 {
2231         struct vcpu_svm *svm = to_svm(vcpu);
2232         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2233         int i;
2234
2235         if (unlikely(cpu != vcpu->cpu)) {
2236                 svm->asid_generation = 0;
2237                 mark_all_dirty(svm->vmcb);
2238         }
2239
2240 #ifdef CONFIG_X86_64
2241         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2242 #endif
2243         savesegment(fs, svm->host.fs);
2244         savesegment(gs, svm->host.gs);
2245         svm->host.ldt = kvm_read_ldt();
2246
2247         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2248                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2249
2250         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2251                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2252                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2253                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
2254                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2255                 }
2256         }
2257         /* This assumes that the kernel never uses MSR_TSC_AUX */
2258         if (static_cpu_has(X86_FEATURE_RDTSCP))
2259                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2260
2261         if (sd->current_vmcb != svm->vmcb) {
2262                 sd->current_vmcb = svm->vmcb;
2263                 indirect_branch_prediction_barrier();
2264         }
2265         avic_vcpu_load(vcpu, cpu);
2266 }
2267
2268 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2269 {
2270         struct vcpu_svm *svm = to_svm(vcpu);
2271         int i;
2272
2273         avic_vcpu_put(vcpu);
2274
2275         ++vcpu->stat.host_state_reload;
2276         kvm_load_ldt(svm->host.ldt);
2277 #ifdef CONFIG_X86_64
2278         loadsegment(fs, svm->host.fs);
2279         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2280         load_gs_index(svm->host.gs);
2281 #else
2282 #ifdef CONFIG_X86_32_LAZY_GS
2283         loadsegment(gs, svm->host.gs);
2284 #endif
2285 #endif
2286         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2287                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2288 }
2289
2290 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2291 {
2292         avic_set_running(vcpu, false);
2293 }
2294
2295 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2296 {
2297         avic_set_running(vcpu, true);
2298 }
2299
2300 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2301 {
2302         struct vcpu_svm *svm = to_svm(vcpu);
2303         unsigned long rflags = svm->vmcb->save.rflags;
2304
2305         if (svm->nmi_singlestep) {
2306                 /* Hide our flags if they were not set by the guest */
2307                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2308                         rflags &= ~X86_EFLAGS_TF;
2309                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2310                         rflags &= ~X86_EFLAGS_RF;
2311         }
2312         return rflags;
2313 }
2314
2315 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2316 {
2317         if (to_svm(vcpu)->nmi_singlestep)
2318                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2319
2320        /*
2321         * Any change of EFLAGS.VM is accompanied by a reload of SS
2322         * (caused by either a task switch or an inter-privilege IRET),
2323         * so we do not need to update the CPL here.
2324         */
2325         to_svm(vcpu)->vmcb->save.rflags = rflags;
2326 }
2327
2328 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2329 {
2330         switch (reg) {
2331         case VCPU_EXREG_PDPTR:
2332                 BUG_ON(!npt_enabled);
2333                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2334                 break;
2335         default:
2336                 BUG();
2337         }
2338 }
2339
2340 static void svm_set_vintr(struct vcpu_svm *svm)
2341 {
2342         set_intercept(svm, INTERCEPT_VINTR);
2343 }
2344
2345 static void svm_clear_vintr(struct vcpu_svm *svm)
2346 {
2347         clr_intercept(svm, INTERCEPT_VINTR);
2348 }
2349
2350 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2351 {
2352         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2353
2354         switch (seg) {
2355         case VCPU_SREG_CS: return &save->cs;
2356         case VCPU_SREG_DS: return &save->ds;
2357         case VCPU_SREG_ES: return &save->es;
2358         case VCPU_SREG_FS: return &save->fs;
2359         case VCPU_SREG_GS: return &save->gs;
2360         case VCPU_SREG_SS: return &save->ss;
2361         case VCPU_SREG_TR: return &save->tr;
2362         case VCPU_SREG_LDTR: return &save->ldtr;
2363         }
2364         BUG();
2365         return NULL;
2366 }
2367
2368 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2369 {
2370         struct vmcb_seg *s = svm_seg(vcpu, seg);
2371
2372         return s->base;
2373 }
2374
2375 static void svm_get_segment(struct kvm_vcpu *vcpu,
2376                             struct kvm_segment *var, int seg)
2377 {
2378         struct vmcb_seg *s = svm_seg(vcpu, seg);
2379
2380         var->base = s->base;
2381         var->limit = s->limit;
2382         var->selector = s->selector;
2383         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2384         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2385         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2386         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2387         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2388         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2389         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2390
2391         /*
2392          * AMD CPUs circa 2014 track the G bit for all segments except CS.
2393          * However, the SVM spec states that the G bit is not observed by the
2394          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2395          * So let's synthesize a legal G bit for all segments, this helps
2396          * running KVM nested. It also helps cross-vendor migration, because
2397          * Intel's vmentry has a check on the 'G' bit.
2398          */
2399         var->g = s->limit > 0xfffff;
2400
2401         /*
2402          * AMD's VMCB does not have an explicit unusable field, so emulate it
2403          * for cross vendor migration purposes by "not present"
2404          */
2405         var->unusable = !var->present;
2406
2407         switch (seg) {
2408         case VCPU_SREG_TR:
2409                 /*
2410                  * Work around a bug where the busy flag in the tr selector
2411                  * isn't exposed
2412                  */
2413                 var->type |= 0x2;
2414                 break;
2415         case VCPU_SREG_DS:
2416         case VCPU_SREG_ES:
2417         case VCPU_SREG_FS:
2418         case VCPU_SREG_GS:
2419                 /*
2420                  * The accessed bit must always be set in the segment
2421                  * descriptor cache, although it can be cleared in the
2422                  * descriptor, the cached bit always remains at 1. Since
2423                  * Intel has a check on this, set it here to support
2424                  * cross-vendor migration.
2425                  */
2426                 if (!var->unusable)
2427                         var->type |= 0x1;
2428                 break;
2429         case VCPU_SREG_SS:
2430                 /*
2431                  * On AMD CPUs sometimes the DB bit in the segment
2432                  * descriptor is left as 1, although the whole segment has
2433                  * been made unusable. Clear it here to pass an Intel VMX
2434                  * entry check when cross vendor migrating.
2435                  */
2436                 if (var->unusable)
2437                         var->db = 0;
2438                 /* This is symmetric with svm_set_segment() */
2439                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2440                 break;
2441         }
2442 }
2443
2444 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2445 {
2446         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2447
2448         return save->cpl;
2449 }
2450
2451 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2452 {
2453         struct vcpu_svm *svm = to_svm(vcpu);
2454
2455         dt->size = svm->vmcb->save.idtr.limit;
2456         dt->address = svm->vmcb->save.idtr.base;
2457 }
2458
2459 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2460 {
2461         struct vcpu_svm *svm = to_svm(vcpu);
2462
2463         svm->vmcb->save.idtr.limit = dt->size;
2464         svm->vmcb->save.idtr.base = dt->address ;
2465         mark_dirty(svm->vmcb, VMCB_DT);
2466 }
2467
2468 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2469 {
2470         struct vcpu_svm *svm = to_svm(vcpu);
2471
2472         dt->size = svm->vmcb->save.gdtr.limit;
2473         dt->address = svm->vmcb->save.gdtr.base;
2474 }
2475
2476 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2477 {
2478         struct vcpu_svm *svm = to_svm(vcpu);
2479
2480         svm->vmcb->save.gdtr.limit = dt->size;
2481         svm->vmcb->save.gdtr.base = dt->address ;
2482         mark_dirty(svm->vmcb, VMCB_DT);
2483 }
2484
2485 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2486 {
2487 }
2488
2489 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2490 {
2491 }
2492
2493 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2494 {
2495 }
2496
2497 static void update_cr0_intercept(struct vcpu_svm *svm)
2498 {
2499         ulong gcr0 = svm->vcpu.arch.cr0;
2500         u64 *hcr0 = &svm->vmcb->save.cr0;
2501
2502         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2503                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2504
2505         mark_dirty(svm->vmcb, VMCB_CR);
2506
2507         if (gcr0 == *hcr0) {
2508                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2509                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2510         } else {
2511                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2512                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2513         }
2514 }
2515
2516 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2517 {
2518         struct vcpu_svm *svm = to_svm(vcpu);
2519
2520 #ifdef CONFIG_X86_64
2521         if (vcpu->arch.efer & EFER_LME) {
2522                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2523                         vcpu->arch.efer |= EFER_LMA;
2524                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2525                 }
2526
2527                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2528                         vcpu->arch.efer &= ~EFER_LMA;
2529                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2530                 }
2531         }
2532 #endif
2533         vcpu->arch.cr0 = cr0;
2534
2535         if (!npt_enabled)
2536                 cr0 |= X86_CR0_PG | X86_CR0_WP;
2537
2538         /*
2539          * re-enable caching here because the QEMU bios
2540          * does not do it - this results in some delay at
2541          * reboot
2542          */
2543         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2544                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2545         svm->vmcb->save.cr0 = cr0;
2546         mark_dirty(svm->vmcb, VMCB_CR);
2547         update_cr0_intercept(svm);
2548 }
2549
2550 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2551 {
2552         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2553         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2554
2555         if (cr4 & X86_CR4_VMXE)
2556                 return 1;
2557
2558         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2559                 svm_flush_tlb(vcpu, true);
2560
2561         vcpu->arch.cr4 = cr4;
2562         if (!npt_enabled)
2563                 cr4 |= X86_CR4_PAE;
2564         cr4 |= host_cr4_mce;
2565         to_svm(vcpu)->vmcb->save.cr4 = cr4;
2566         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2567         return 0;
2568 }
2569
2570 static void svm_set_segment(struct kvm_vcpu *vcpu,
2571                             struct kvm_segment *var, int seg)
2572 {
2573         struct vcpu_svm *svm = to_svm(vcpu);
2574         struct vmcb_seg *s = svm_seg(vcpu, seg);
2575
2576         s->base = var->base;
2577         s->limit = var->limit;
2578         s->selector = var->selector;
2579         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2580         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2581         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2582         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2583         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2584         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2585         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2586         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2587
2588         /*
2589          * This is always accurate, except if SYSRET returned to a segment
2590          * with SS.DPL != 3.  Intel does not have this quirk, and always
2591          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2592          * would entail passing the CPL to userspace and back.
2593          */
2594         if (seg == VCPU_SREG_SS)
2595                 /* This is symmetric with svm_get_segment() */
2596                 svm->vmcb->save.cpl = (var->dpl & 3);
2597
2598         mark_dirty(svm->vmcb, VMCB_SEG);
2599 }
2600
2601 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2602 {
2603         struct vcpu_svm *svm = to_svm(vcpu);
2604
2605         clr_exception_intercept(svm, BP_VECTOR);
2606
2607         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2608                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2609                         set_exception_intercept(svm, BP_VECTOR);
2610         } else
2611                 vcpu->guest_debug = 0;
2612 }
2613
2614 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2615 {
2616         if (sd->next_asid > sd->max_asid) {
2617                 ++sd->asid_generation;
2618                 sd->next_asid = sd->min_asid;
2619                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2620         }
2621
2622         svm->asid_generation = sd->asid_generation;
2623         svm->vmcb->control.asid = sd->next_asid++;
2624
2625         mark_dirty(svm->vmcb, VMCB_ASID);
2626 }
2627
2628 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2629 {
2630         return to_svm(vcpu)->vmcb->save.dr6;
2631 }
2632
2633 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2634 {
2635         struct vcpu_svm *svm = to_svm(vcpu);
2636
2637         svm->vmcb->save.dr6 = value;
2638         mark_dirty(svm->vmcb, VMCB_DR);
2639 }
2640
2641 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2642 {
2643         struct vcpu_svm *svm = to_svm(vcpu);
2644
2645         get_debugreg(vcpu->arch.db[0], 0);
2646         get_debugreg(vcpu->arch.db[1], 1);
2647         get_debugreg(vcpu->arch.db[2], 2);
2648         get_debugreg(vcpu->arch.db[3], 3);
2649         vcpu->arch.dr6 = svm_get_dr6(vcpu);
2650         vcpu->arch.dr7 = svm->vmcb->save.dr7;
2651
2652         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2653         set_dr_intercepts(svm);
2654 }
2655
2656 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2657 {
2658         struct vcpu_svm *svm = to_svm(vcpu);
2659
2660         svm->vmcb->save.dr7 = value;
2661         mark_dirty(svm->vmcb, VMCB_DR);
2662 }
2663
2664 static int pf_interception(struct vcpu_svm *svm)
2665 {
2666         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2667         u64 error_code = svm->vmcb->control.exit_info_1;
2668
2669         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2670                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2671                         svm->vmcb->control.insn_bytes : NULL,
2672                         svm->vmcb->control.insn_len);
2673 }
2674
2675 static int npf_interception(struct vcpu_svm *svm)
2676 {
2677         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2678         u64 error_code = svm->vmcb->control.exit_info_1;
2679
2680         trace_kvm_page_fault(fault_address, error_code);
2681         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2682                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2683                         svm->vmcb->control.insn_bytes : NULL,
2684                         svm->vmcb->control.insn_len);
2685 }
2686
2687 static int db_interception(struct vcpu_svm *svm)
2688 {
2689         struct kvm_run *kvm_run = svm->vcpu.run;
2690
2691         if (!(svm->vcpu.guest_debug &
2692               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2693                 !svm->nmi_singlestep) {
2694                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2695                 return 1;
2696         }
2697
2698         if (svm->nmi_singlestep) {
2699                 disable_nmi_singlestep(svm);
2700         }
2701
2702         if (svm->vcpu.guest_debug &
2703             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2704                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2705                 kvm_run->debug.arch.pc =
2706                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2707                 kvm_run->debug.arch.exception = DB_VECTOR;
2708                 return 0;
2709         }
2710
2711         return 1;
2712 }
2713
2714 static int bp_interception(struct vcpu_svm *svm)
2715 {
2716         struct kvm_run *kvm_run = svm->vcpu.run;
2717
2718         kvm_run->exit_reason = KVM_EXIT_DEBUG;
2719         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2720         kvm_run->debug.arch.exception = BP_VECTOR;
2721         return 0;
2722 }
2723
2724 static int ud_interception(struct vcpu_svm *svm)
2725 {
2726         return handle_ud(&svm->vcpu);
2727 }
2728
2729 static int ac_interception(struct vcpu_svm *svm)
2730 {
2731         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2732         return 1;
2733 }
2734
2735 static int gp_interception(struct vcpu_svm *svm)
2736 {
2737         struct kvm_vcpu *vcpu = &svm->vcpu;
2738         u32 error_code = svm->vmcb->control.exit_info_1;
2739         int er;
2740
2741         WARN_ON_ONCE(!enable_vmware_backdoor);
2742
2743         er = kvm_emulate_instruction(vcpu,
2744                 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2745         if (er == EMULATE_USER_EXIT)
2746                 return 0;
2747         else if (er != EMULATE_DONE)
2748                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2749         return 1;
2750 }
2751
2752 static bool is_erratum_383(void)
2753 {
2754         int err, i;
2755         u64 value;
2756
2757         if (!erratum_383_found)
2758                 return false;
2759
2760         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2761         if (err)
2762                 return false;
2763
2764         /* Bit 62 may or may not be set for this mce */
2765         value &= ~(1ULL << 62);
2766
2767         if (value != 0xb600000000010015ULL)
2768                 return false;
2769
2770         /* Clear MCi_STATUS registers */
2771         for (i = 0; i < 6; ++i)
2772                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2773
2774         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2775         if (!err) {
2776                 u32 low, high;
2777
2778                 value &= ~(1ULL << 2);
2779                 low    = lower_32_bits(value);
2780                 high   = upper_32_bits(value);
2781
2782                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2783         }
2784
2785         /* Flush tlb to evict multi-match entries */
2786         __flush_tlb_all();
2787
2788         return true;
2789 }
2790
2791 static void svm_handle_mce(struct vcpu_svm *svm)
2792 {
2793         if (is_erratum_383()) {
2794                 /*
2795                  * Erratum 383 triggered. Guest state is corrupt so kill the
2796                  * guest.
2797                  */
2798                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2799
2800                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2801
2802                 return;
2803         }
2804
2805         /*
2806          * On an #MC intercept the MCE handler is not called automatically in
2807          * the host. So do it by hand here.
2808          */
2809         asm volatile (
2810                 "int $0x12\n");
2811         /* not sure if we ever come back to this point */
2812
2813         return;
2814 }
2815
2816 static int mc_interception(struct vcpu_svm *svm)
2817 {
2818         return 1;
2819 }
2820
2821 static int shutdown_interception(struct vcpu_svm *svm)
2822 {
2823         struct kvm_run *kvm_run = svm->vcpu.run;
2824
2825         /*
2826          * VMCB is undefined after a SHUTDOWN intercept
2827          * so reinitialize it.
2828          */
2829         clear_page(svm->vmcb);
2830         init_vmcb(svm);
2831
2832         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2833         return 0;
2834 }
2835
2836 static int io_interception(struct vcpu_svm *svm)
2837 {
2838         struct kvm_vcpu *vcpu = &svm->vcpu;
2839         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2840         int size, in, string;
2841         unsigned port;
2842
2843         ++svm->vcpu.stat.io_exits;
2844         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2845         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2846         if (string)
2847                 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
2848
2849         port = io_info >> 16;
2850         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2851         svm->next_rip = svm->vmcb->control.exit_info_2;
2852
2853         return kvm_fast_pio(&svm->vcpu, size, port, in);
2854 }
2855
2856 static int nmi_interception(struct vcpu_svm *svm)
2857 {
2858         return 1;
2859 }
2860
2861 static int intr_interception(struct vcpu_svm *svm)
2862 {
2863         ++svm->vcpu.stat.irq_exits;
2864         return 1;
2865 }
2866
2867 static int nop_on_interception(struct vcpu_svm *svm)
2868 {
2869         return 1;
2870 }
2871
2872 static int halt_interception(struct vcpu_svm *svm)
2873 {
2874         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2875         return kvm_emulate_halt(&svm->vcpu);
2876 }
2877
2878 static int vmmcall_interception(struct vcpu_svm *svm)
2879 {
2880         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2881         return kvm_emulate_hypercall(&svm->vcpu);
2882 }
2883
2884 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2885 {
2886         struct vcpu_svm *svm = to_svm(vcpu);
2887
2888         return svm->nested.nested_cr3;
2889 }
2890
2891 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2892 {
2893         struct vcpu_svm *svm = to_svm(vcpu);
2894         u64 cr3 = svm->nested.nested_cr3;
2895         u64 pdpte;
2896         int ret;
2897
2898         ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2899                                        offset_in_page(cr3) + index * 8, 8);
2900         if (ret)
2901                 return 0;
2902         return pdpte;
2903 }
2904
2905 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2906                                    unsigned long root)
2907 {
2908         struct vcpu_svm *svm = to_svm(vcpu);
2909
2910         svm->vmcb->control.nested_cr3 = __sme_set(root);
2911         mark_dirty(svm->vmcb, VMCB_NPT);
2912 }
2913
2914 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2915                                        struct x86_exception *fault)
2916 {
2917         struct vcpu_svm *svm = to_svm(vcpu);
2918
2919         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2920                 /*
2921                  * TODO: track the cause of the nested page fault, and
2922                  * correctly fill in the high bits of exit_info_1.
2923                  */
2924                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2925                 svm->vmcb->control.exit_code_hi = 0;
2926                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2927                 svm->vmcb->control.exit_info_2 = fault->address;
2928         }
2929
2930         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2931         svm->vmcb->control.exit_info_1 |= fault->error_code;
2932
2933         /*
2934          * The present bit is always zero for page structure faults on real
2935          * hardware.
2936          */
2937         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2938                 svm->vmcb->control.exit_info_1 &= ~1;
2939
2940         nested_svm_vmexit(svm);
2941 }
2942
2943 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2944 {
2945         WARN_ON(mmu_is_nested(vcpu));
2946
2947         vcpu->arch.mmu = &vcpu->arch.guest_mmu;
2948         kvm_init_shadow_mmu(vcpu);
2949         vcpu->arch.mmu->set_cr3           = nested_svm_set_tdp_cr3;
2950         vcpu->arch.mmu->get_cr3           = nested_svm_get_tdp_cr3;
2951         vcpu->arch.mmu->get_pdptr         = nested_svm_get_tdp_pdptr;
2952         vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
2953         vcpu->arch.mmu->shadow_root_level = get_npt_level(vcpu);
2954         reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
2955         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2956 }
2957
2958 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2959 {
2960         vcpu->arch.mmu = &vcpu->arch.root_mmu;
2961         vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
2962 }
2963
2964 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2965 {
2966         if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2967             !is_paging(&svm->vcpu)) {
2968                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2969                 return 1;
2970         }
2971
2972         if (svm->vmcb->save.cpl) {
2973                 kvm_inject_gp(&svm->vcpu, 0);
2974                 return 1;
2975         }
2976
2977         return 0;
2978 }
2979
2980 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2981                                       bool has_error_code, u32 error_code)
2982 {
2983         int vmexit;
2984
2985         if (!is_guest_mode(&svm->vcpu))
2986                 return 0;
2987
2988         vmexit = nested_svm_intercept(svm);
2989         if (vmexit != NESTED_EXIT_DONE)
2990                 return 0;
2991
2992         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2993         svm->vmcb->control.exit_code_hi = 0;
2994         svm->vmcb->control.exit_info_1 = error_code;
2995
2996         /*
2997          * EXITINFO2 is undefined for all exception intercepts other
2998          * than #PF.
2999          */
3000         if (svm->vcpu.arch.exception.nested_apf)
3001                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
3002         else if (svm->vcpu.arch.exception.has_payload)
3003                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
3004         else
3005                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
3006
3007         svm->nested.exit_required = true;
3008         return vmexit;
3009 }
3010
3011 /* This function returns true if it is save to enable the irq window */
3012 static inline bool nested_svm_intr(struct vcpu_svm *svm)
3013 {
3014         if (!is_guest_mode(&svm->vcpu))
3015                 return true;
3016
3017         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3018                 return true;
3019
3020         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
3021                 return false;
3022
3023         /*
3024          * if vmexit was already requested (by intercepted exception
3025          * for instance) do not overwrite it with "external interrupt"
3026          * vmexit.
3027          */
3028         if (svm->nested.exit_required)
3029                 return false;
3030
3031         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
3032         svm->vmcb->control.exit_info_1 = 0;
3033         svm->vmcb->control.exit_info_2 = 0;
3034
3035         if (svm->nested.intercept & 1ULL) {
3036                 /*
3037                  * The #vmexit can't be emulated here directly because this
3038                  * code path runs with irqs and preemption disabled. A
3039                  * #vmexit emulation might sleep. Only signal request for
3040                  * the #vmexit here.
3041                  */
3042                 svm->nested.exit_required = true;
3043                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3044                 return false;
3045         }
3046
3047         return true;
3048 }
3049
3050 /* This function returns true if it is save to enable the nmi window */
3051 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3052 {
3053         if (!is_guest_mode(&svm->vcpu))
3054                 return true;
3055
3056         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3057                 return true;
3058
3059         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3060         svm->nested.exit_required = true;
3061
3062         return false;
3063 }
3064
3065 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
3066 {
3067         struct page *page;
3068
3069         might_sleep();
3070
3071         page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
3072         if (is_error_page(page))
3073                 goto error;
3074
3075         *_page = page;
3076
3077         return kmap(page);
3078
3079 error:
3080         kvm_inject_gp(&svm->vcpu, 0);
3081
3082         return NULL;
3083 }
3084
3085 static void nested_svm_unmap(struct page *page)
3086 {
3087         kunmap(page);
3088         kvm_release_page_dirty(page);
3089 }
3090
3091 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3092 {
3093         unsigned port, size, iopm_len;
3094         u16 val, mask;
3095         u8 start_bit;
3096         u64 gpa;
3097
3098         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3099                 return NESTED_EXIT_HOST;
3100
3101         port = svm->vmcb->control.exit_info_1 >> 16;
3102         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3103                 SVM_IOIO_SIZE_SHIFT;
3104         gpa  = svm->nested.vmcb_iopm + (port / 8);
3105         start_bit = port % 8;
3106         iopm_len = (start_bit + size > 8) ? 2 : 1;
3107         mask = (0xf >> (4 - size)) << start_bit;
3108         val = 0;
3109
3110         if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3111                 return NESTED_EXIT_DONE;
3112
3113         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3114 }
3115
3116 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3117 {
3118         u32 offset, msr, value;
3119         int write, mask;
3120
3121         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3122                 return NESTED_EXIT_HOST;
3123
3124         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3125         offset = svm_msrpm_offset(msr);
3126         write  = svm->vmcb->control.exit_info_1 & 1;
3127         mask   = 1 << ((2 * (msr & 0xf)) + write);
3128
3129         if (offset == MSR_INVALID)
3130                 return NESTED_EXIT_DONE;
3131
3132         /* Offset is in 32 bit units but need in 8 bit units */
3133         offset *= 4;
3134
3135         if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3136                 return NESTED_EXIT_DONE;
3137
3138         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3139 }
3140
3141 /* DB exceptions for our internal use must not cause vmexit */
3142 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3143 {
3144         unsigned long dr6;
3145
3146         /* if we're not singlestepping, it's not ours */
3147         if (!svm->nmi_singlestep)
3148                 return NESTED_EXIT_DONE;
3149
3150         /* if it's not a singlestep exception, it's not ours */
3151         if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3152                 return NESTED_EXIT_DONE;
3153         if (!(dr6 & DR6_BS))
3154                 return NESTED_EXIT_DONE;
3155
3156         /* if the guest is singlestepping, it should get the vmexit */
3157         if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3158                 disable_nmi_singlestep(svm);
3159                 return NESTED_EXIT_DONE;
3160         }
3161
3162         /* it's ours, the nested hypervisor must not see this one */
3163         return NESTED_EXIT_HOST;
3164 }
3165
3166 static int nested_svm_exit_special(struct vcpu_svm *svm)
3167 {
3168         u32 exit_code = svm->vmcb->control.exit_code;
3169
3170         switch (exit_code) {
3171         case SVM_EXIT_INTR:
3172         case SVM_EXIT_NMI:
3173         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3174                 return NESTED_EXIT_HOST;
3175         case SVM_EXIT_NPF:
3176                 /* For now we are always handling NPFs when using them */
3177                 if (npt_enabled)
3178                         return NESTED_EXIT_HOST;
3179                 break;
3180         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3181                 /* When we're shadowing, trap PFs, but not async PF */
3182                 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3183                         return NESTED_EXIT_HOST;
3184                 break;
3185         default:
3186                 break;
3187         }
3188
3189         return NESTED_EXIT_CONTINUE;
3190 }
3191
3192 /*
3193  * If this function returns true, this #vmexit was already handled
3194  */
3195 static int nested_svm_intercept(struct vcpu_svm *svm)
3196 {
3197         u32 exit_code = svm->vmcb->control.exit_code;
3198         int vmexit = NESTED_EXIT_HOST;
3199
3200         switch (exit_code) {
3201         case SVM_EXIT_MSR:
3202                 vmexit = nested_svm_exit_handled_msr(svm);
3203                 break;
3204         case SVM_EXIT_IOIO:
3205                 vmexit = nested_svm_intercept_ioio(svm);
3206                 break;
3207         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3208                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3209                 if (svm->nested.intercept_cr & bit)
3210                         vmexit = NESTED_EXIT_DONE;
3211                 break;
3212         }
3213         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3214                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3215                 if (svm->nested.intercept_dr & bit)
3216                         vmexit = NESTED_EXIT_DONE;
3217                 break;
3218         }
3219         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3220                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3221                 if (svm->nested.intercept_exceptions & excp_bits) {
3222                         if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3223                                 vmexit = nested_svm_intercept_db(svm);
3224                         else
3225                                 vmexit = NESTED_EXIT_DONE;
3226                 }
3227                 /* async page fault always cause vmexit */
3228                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3229                          svm->vcpu.arch.exception.nested_apf != 0)
3230                         vmexit = NESTED_EXIT_DONE;
3231                 break;
3232         }
3233         case SVM_EXIT_ERR: {
3234                 vmexit = NESTED_EXIT_DONE;
3235                 break;
3236         }
3237         default: {
3238                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3239                 if (svm->nested.intercept & exit_bits)
3240                         vmexit = NESTED_EXIT_DONE;
3241         }
3242         }
3243
3244         return vmexit;
3245 }
3246
3247 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3248 {
3249         int vmexit;
3250
3251         vmexit = nested_svm_intercept(svm);
3252
3253         if (vmexit == NESTED_EXIT_DONE)
3254                 nested_svm_vmexit(svm);
3255
3256         return vmexit;
3257 }
3258
3259 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3260 {
3261         struct vmcb_control_area *dst  = &dst_vmcb->control;
3262         struct vmcb_control_area *from = &from_vmcb->control;
3263
3264         dst->intercept_cr         = from->intercept_cr;
3265         dst->intercept_dr         = from->intercept_dr;
3266         dst->intercept_exceptions = from->intercept_exceptions;
3267         dst->intercept            = from->intercept;
3268         dst->iopm_base_pa         = from->iopm_base_pa;
3269         dst->msrpm_base_pa        = from->msrpm_base_pa;
3270         dst->tsc_offset           = from->tsc_offset;
3271         dst->asid                 = from->asid;
3272         dst->tlb_ctl              = from->tlb_ctl;
3273         dst->int_ctl              = from->int_ctl;
3274         dst->int_vector           = from->int_vector;
3275         dst->int_state            = from->int_state;
3276         dst->exit_code            = from->exit_code;
3277         dst->exit_code_hi         = from->exit_code_hi;
3278         dst->exit_info_1          = from->exit_info_1;
3279         dst->exit_info_2          = from->exit_info_2;
3280         dst->exit_int_info        = from->exit_int_info;
3281         dst->exit_int_info_err    = from->exit_int_info_err;
3282         dst->nested_ctl           = from->nested_ctl;
3283         dst->event_inj            = from->event_inj;
3284         dst->event_inj_err        = from->event_inj_err;
3285         dst->nested_cr3           = from->nested_cr3;
3286         dst->virt_ext              = from->virt_ext;
3287         dst->pause_filter_count   = from->pause_filter_count;
3288         dst->pause_filter_thresh  = from->pause_filter_thresh;
3289 }
3290
3291 static int nested_svm_vmexit(struct vcpu_svm *svm)
3292 {
3293         struct vmcb *nested_vmcb;
3294         struct vmcb *hsave = svm->nested.hsave;
3295         struct vmcb *vmcb = svm->vmcb;
3296         struct page *page;
3297
3298         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3299                                        vmcb->control.exit_info_1,
3300                                        vmcb->control.exit_info_2,
3301                                        vmcb->control.exit_int_info,
3302                                        vmcb->control.exit_int_info_err,
3303                                        KVM_ISA_SVM);
3304
3305         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
3306         if (!nested_vmcb)
3307                 return 1;
3308
3309         /* Exit Guest-Mode */
3310         leave_guest_mode(&svm->vcpu);
3311         svm->nested.vmcb = 0;
3312
3313         /* Give the current vmcb to the guest */
3314         disable_gif(svm);
3315
3316         nested_vmcb->save.es     = vmcb->save.es;
3317         nested_vmcb->save.cs     = vmcb->save.cs;
3318         nested_vmcb->save.ss     = vmcb->save.ss;
3319         nested_vmcb->save.ds     = vmcb->save.ds;
3320         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
3321         nested_vmcb->save.idtr   = vmcb->save.idtr;
3322         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
3323         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
3324         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
3325         nested_vmcb->save.cr2    = vmcb->save.cr2;
3326         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
3327         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3328         nested_vmcb->save.rip    = vmcb->save.rip;
3329         nested_vmcb->save.rsp    = vmcb->save.rsp;
3330         nested_vmcb->save.rax    = vmcb->save.rax;
3331         nested_vmcb->save.dr7    = vmcb->save.dr7;
3332         nested_vmcb->save.dr6    = vmcb->save.dr6;
3333         nested_vmcb->save.cpl    = vmcb->save.cpl;
3334
3335         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
3336         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
3337         nested_vmcb->control.int_state         = vmcb->control.int_state;
3338         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
3339         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
3340         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
3341         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
3342         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
3343         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3344
3345         if (svm->nrips_enabled)
3346                 nested_vmcb->control.next_rip  = vmcb->control.next_rip;
3347
3348         /*
3349          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3350          * to make sure that we do not lose injected events. So check event_inj
3351          * here and copy it to exit_int_info if it is valid.
3352          * Exit_int_info and event_inj can't be both valid because the case
3353          * below only happens on a VMRUN instruction intercept which has
3354          * no valid exit_int_info set.
3355          */
3356         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3357                 struct vmcb_control_area *nc = &nested_vmcb->control;
3358
3359                 nc->exit_int_info     = vmcb->control.event_inj;
3360                 nc->exit_int_info_err = vmcb->control.event_inj_err;
3361         }
3362
3363         nested_vmcb->control.tlb_ctl           = 0;
3364         nested_vmcb->control.event_inj         = 0;
3365         nested_vmcb->control.event_inj_err     = 0;
3366
3367         nested_vmcb->control.pause_filter_count =
3368                 svm->vmcb->control.pause_filter_count;
3369         nested_vmcb->control.pause_filter_thresh =
3370                 svm->vmcb->control.pause_filter_thresh;
3371
3372         /* We always set V_INTR_MASKING and remember the old value in hflags */
3373         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3374                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3375
3376         /* Restore the original control entries */
3377         copy_vmcb_control_area(vmcb, hsave);
3378
3379         svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3380         kvm_clear_exception_queue(&svm->vcpu);
3381         kvm_clear_interrupt_queue(&svm->vcpu);
3382
3383         svm->nested.nested_cr3 = 0;
3384
3385         /* Restore selected save entries */
3386         svm->vmcb->save.es = hsave->save.es;
3387         svm->vmcb->save.cs = hsave->save.cs;
3388         svm->vmcb->save.ss = hsave->save.ss;
3389         svm->vmcb->save.ds = hsave->save.ds;
3390         svm->vmcb->save.gdtr = hsave->save.gdtr;
3391         svm->vmcb->save.idtr = hsave->save.idtr;
3392         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3393         svm_set_efer(&svm->vcpu, hsave->save.efer);
3394         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3395         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3396         if (npt_enabled) {
3397                 svm->vmcb->save.cr3 = hsave->save.cr3;
3398                 svm->vcpu.arch.cr3 = hsave->save.cr3;
3399         } else {
3400                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3401         }
3402         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
3403         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
3404         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
3405         svm->vmcb->save.dr7 = 0;
3406         svm->vmcb->save.cpl = 0;
3407         svm->vmcb->control.exit_int_info = 0;
3408
3409         mark_all_dirty(svm->vmcb);
3410
3411         nested_svm_unmap(page);
3412
3413         nested_svm_uninit_mmu_context(&svm->vcpu);
3414         kvm_mmu_reset_context(&svm->vcpu);
3415         kvm_mmu_load(&svm->vcpu);
3416
3417         return 0;
3418 }
3419
3420 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3421 {
3422         /*
3423          * This function merges the msr permission bitmaps of kvm and the
3424          * nested vmcb. It is optimized in that it only merges the parts where
3425          * the kvm msr permission bitmap may contain zero bits
3426          */
3427         int i;
3428
3429         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3430                 return true;
3431
3432         for (i = 0; i < MSRPM_OFFSETS; i++) {
3433                 u32 value, p;
3434                 u64 offset;
3435
3436                 if (msrpm_offsets[i] == 0xffffffff)
3437                         break;
3438
3439                 p      = msrpm_offsets[i];
3440                 offset = svm->nested.vmcb_msrpm + (p * 4);
3441
3442                 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3443                         return false;
3444
3445                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3446         }
3447
3448         svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3449
3450         return true;
3451 }
3452
3453 static bool nested_vmcb_checks(struct vmcb *vmcb)
3454 {
3455         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3456                 return false;
3457
3458         if (vmcb->control.asid == 0)
3459                 return false;
3460
3461         if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3462             !npt_enabled)
3463                 return false;
3464
3465         return true;
3466 }
3467
3468 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3469                                  struct vmcb *nested_vmcb, struct page *page)
3470 {
3471         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3472                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3473         else
3474                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3475
3476         if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3477                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3478                 nested_svm_init_mmu_context(&svm->vcpu);
3479         }
3480
3481         /* Load the nested guest state */
3482         svm->vmcb->save.es = nested_vmcb->save.es;
3483         svm->vmcb->save.cs = nested_vmcb->save.cs;
3484         svm->vmcb->save.ss = nested_vmcb->save.ss;
3485         svm->vmcb->save.ds = nested_vmcb->save.ds;
3486         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3487         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3488         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3489         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3490         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3491         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3492         if (npt_enabled) {
3493                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3494                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3495         } else
3496                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3497
3498         /* Guest paging mode is active - reset mmu */
3499         kvm_mmu_reset_context(&svm->vcpu);
3500
3501         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3502         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3503         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3504         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3505
3506         /* In case we don't even reach vcpu_run, the fields are not updated */
3507         svm->vmcb->save.rax = nested_vmcb->save.rax;
3508         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3509         svm->vmcb->save.rip = nested_vmcb->save.rip;
3510         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3511         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3512         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3513
3514         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3515         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
3516
3517         /* cache intercepts */
3518         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
3519         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
3520         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3521         svm->nested.intercept            = nested_vmcb->control.intercept;
3522
3523         svm_flush_tlb(&svm->vcpu, true);
3524         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3525         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3526                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3527         else
3528                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3529
3530         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3531                 /* We only want the cr8 intercept bits of the guest */
3532                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3533                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3534         }
3535
3536         /* We don't want to see VMMCALLs from a nested guest */
3537         clr_intercept(svm, INTERCEPT_VMMCALL);
3538
3539         svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3540         svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3541
3542         svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3543         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3544         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3545         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3546         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3547
3548         svm->vmcb->control.pause_filter_count =
3549                 nested_vmcb->control.pause_filter_count;
3550         svm->vmcb->control.pause_filter_thresh =
3551                 nested_vmcb->control.pause_filter_thresh;
3552
3553         nested_svm_unmap(page);
3554
3555         /* Enter Guest-Mode */
3556         enter_guest_mode(&svm->vcpu);
3557
3558         /*
3559          * Merge guest and host intercepts - must be called  with vcpu in
3560          * guest-mode to take affect here
3561          */
3562         recalc_intercepts(svm);
3563
3564         svm->nested.vmcb = vmcb_gpa;
3565
3566         enable_gif(svm);
3567
3568         mark_all_dirty(svm->vmcb);
3569 }
3570
3571 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3572 {
3573         struct vmcb *nested_vmcb;
3574         struct vmcb *hsave = svm->nested.hsave;
3575         struct vmcb *vmcb = svm->vmcb;
3576         struct page *page;
3577         u64 vmcb_gpa;
3578
3579         vmcb_gpa = svm->vmcb->save.rax;
3580
3581         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3582         if (!nested_vmcb)
3583                 return false;
3584
3585         if (!nested_vmcb_checks(nested_vmcb)) {
3586                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
3587                 nested_vmcb->control.exit_code_hi = 0;
3588                 nested_vmcb->control.exit_info_1  = 0;
3589                 nested_vmcb->control.exit_info_2  = 0;
3590
3591                 nested_svm_unmap(page);
3592
3593                 return false;
3594         }
3595
3596         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3597                                nested_vmcb->save.rip,
3598                                nested_vmcb->control.int_ctl,
3599                                nested_vmcb->control.event_inj,
3600                                nested_vmcb->control.nested_ctl);
3601
3602         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3603                                     nested_vmcb->control.intercept_cr >> 16,
3604                                     nested_vmcb->control.intercept_exceptions,
3605                                     nested_vmcb->control.intercept);
3606
3607         /* Clear internal status */
3608         kvm_clear_exception_queue(&svm->vcpu);
3609         kvm_clear_interrupt_queue(&svm->vcpu);
3610
3611         /*
3612          * Save the old vmcb, so we don't need to pick what we save, but can
3613          * restore everything when a VMEXIT occurs
3614          */
3615         hsave->save.es     = vmcb->save.es;
3616         hsave->save.cs     = vmcb->save.cs;
3617         hsave->save.ss     = vmcb->save.ss;
3618         hsave->save.ds     = vmcb->save.ds;
3619         hsave->save.gdtr   = vmcb->save.gdtr;
3620         hsave->save.idtr   = vmcb->save.idtr;
3621         hsave->save.efer   = svm->vcpu.arch.efer;
3622         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
3623         hsave->save.cr4    = svm->vcpu.arch.cr4;
3624         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3625         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
3626         hsave->save.rsp    = vmcb->save.rsp;
3627         hsave->save.rax    = vmcb->save.rax;
3628         if (npt_enabled)
3629                 hsave->save.cr3    = vmcb->save.cr3;
3630         else
3631                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
3632
3633         copy_vmcb_control_area(hsave, vmcb);
3634
3635         enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3636
3637         return true;
3638 }
3639
3640 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3641 {
3642         to_vmcb->save.fs = from_vmcb->save.fs;
3643         to_vmcb->save.gs = from_vmcb->save.gs;
3644         to_vmcb->save.tr = from_vmcb->save.tr;
3645         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3646         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3647         to_vmcb->save.star = from_vmcb->save.star;
3648         to_vmcb->save.lstar = from_vmcb->save.lstar;
3649         to_vmcb->save.cstar = from_vmcb->save.cstar;
3650         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3651         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3652         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3653         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3654 }
3655
3656 static int vmload_interception(struct vcpu_svm *svm)
3657 {
3658         struct vmcb *nested_vmcb;
3659         struct page *page;
3660         int ret;
3661
3662         if (nested_svm_check_permissions(svm))
3663                 return 1;
3664
3665         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3666         if (!nested_vmcb)
3667                 return 1;
3668
3669         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3670         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3671
3672         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3673         nested_svm_unmap(page);
3674
3675         return ret;
3676 }
3677
3678 static int vmsave_interception(struct vcpu_svm *svm)
3679 {
3680         struct vmcb *nested_vmcb;
3681         struct page *page;
3682         int ret;
3683
3684         if (nested_svm_check_permissions(svm))
3685                 return 1;
3686
3687         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3688         if (!nested_vmcb)
3689                 return 1;
3690
3691         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3692         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3693
3694         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3695         nested_svm_unmap(page);
3696
3697         return ret;
3698 }
3699
3700 static int vmrun_interception(struct vcpu_svm *svm)
3701 {
3702         if (nested_svm_check_permissions(svm))
3703                 return 1;
3704
3705         /* Save rip after vmrun instruction */
3706         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3707
3708         if (!nested_svm_vmrun(svm))
3709                 return 1;
3710
3711         if (!nested_svm_vmrun_msrpm(svm))
3712                 goto failed;
3713
3714         return 1;
3715
3716 failed:
3717
3718         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
3719         svm->vmcb->control.exit_code_hi = 0;
3720         svm->vmcb->control.exit_info_1  = 0;
3721         svm->vmcb->control.exit_info_2  = 0;
3722
3723         nested_svm_vmexit(svm);
3724
3725         return 1;
3726 }
3727
3728 static int stgi_interception(struct vcpu_svm *svm)
3729 {
3730         int ret;
3731
3732         if (nested_svm_check_permissions(svm))
3733                 return 1;
3734
3735         /*
3736          * If VGIF is enabled, the STGI intercept is only added to
3737          * detect the opening of the SMI/NMI window; remove it now.
3738          */
3739         if (vgif_enabled(svm))
3740                 clr_intercept(svm, INTERCEPT_STGI);
3741
3742         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3743         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3744         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3745
3746         enable_gif(svm);
3747
3748         return ret;
3749 }
3750
3751 static int clgi_interception(struct vcpu_svm *svm)
3752 {
3753         int ret;
3754
3755         if (nested_svm_check_permissions(svm))
3756                 return 1;
3757
3758         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3759         ret = kvm_skip_emulated_instruction(&svm->vcpu);
3760
3761         disable_gif(svm);
3762
3763         /* After a CLGI no interrupts should come */
3764         if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3765                 svm_clear_vintr(svm);
3766                 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3767                 mark_dirty(svm->vmcb, VMCB_INTR);
3768         }
3769
3770         return ret;
3771 }
3772
3773 static int invlpga_interception(struct vcpu_svm *svm)
3774 {
3775         struct kvm_vcpu *vcpu = &svm->vcpu;
3776
3777         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3778                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3779
3780         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3781         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3782
3783         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3784         return kvm_skip_emulated_instruction(&svm->vcpu);
3785 }
3786
3787 static int skinit_interception(struct vcpu_svm *svm)
3788 {
3789         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3790
3791         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3792         return 1;
3793 }
3794
3795 static int wbinvd_interception(struct vcpu_svm *svm)
3796 {
3797         return kvm_emulate_wbinvd(&svm->vcpu);
3798 }
3799
3800 static int xsetbv_interception(struct vcpu_svm *svm)
3801 {
3802         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3803         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3804
3805         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3806                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3807                 return kvm_skip_emulated_instruction(&svm->vcpu);
3808         }
3809
3810         return 1;
3811 }
3812
3813 static int task_switch_interception(struct vcpu_svm *svm)
3814 {
3815         u16 tss_selector;
3816         int reason;
3817         int int_type = svm->vmcb->control.exit_int_info &
3818                 SVM_EXITINTINFO_TYPE_MASK;
3819         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3820         uint32_t type =
3821                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3822         uint32_t idt_v =
3823                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3824         bool has_error_code = false;
3825         u32 error_code = 0;
3826
3827         tss_selector = (u16)svm->vmcb->control.exit_info_1;
3828
3829         if (svm->vmcb->control.exit_info_2 &
3830             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3831                 reason = TASK_SWITCH_IRET;
3832         else if (svm->vmcb->control.exit_info_2 &
3833                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3834                 reason = TASK_SWITCH_JMP;
3835         else if (idt_v)
3836                 reason = TASK_SWITCH_GATE;
3837         else
3838                 reason = TASK_SWITCH_CALL;
3839
3840         if (reason == TASK_SWITCH_GATE) {
3841                 switch (type) {
3842                 case SVM_EXITINTINFO_TYPE_NMI:
3843                         svm->vcpu.arch.nmi_injected = false;
3844                         break;
3845                 case SVM_EXITINTINFO_TYPE_EXEPT:
3846                         if (svm->vmcb->control.exit_info_2 &
3847                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3848                                 has_error_code = true;
3849                                 error_code =
3850                                         (u32)svm->vmcb->control.exit_info_2;
3851                         }
3852                         kvm_clear_exception_queue(&svm->vcpu);
3853                         break;
3854                 case SVM_EXITINTINFO_TYPE_INTR:
3855                         kvm_clear_interrupt_queue(&svm->vcpu);
3856                         break;
3857                 default:
3858                         break;
3859                 }
3860         }
3861
3862         if (reason != TASK_SWITCH_GATE ||
3863             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3864             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3865              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3866                 skip_emulated_instruction(&svm->vcpu);
3867
3868         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3869                 int_vec = -1;
3870
3871         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3872                                 has_error_code, error_code) == EMULATE_FAIL) {
3873                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3874                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3875                 svm->vcpu.run->internal.ndata = 0;
3876                 return 0;
3877         }
3878         return 1;
3879 }
3880
3881 static int cpuid_interception(struct vcpu_svm *svm)
3882 {
3883         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3884         return kvm_emulate_cpuid(&svm->vcpu);
3885 }
3886
3887 static int iret_interception(struct vcpu_svm *svm)
3888 {
3889         ++svm->vcpu.stat.nmi_window_exits;
3890         clr_intercept(svm, INTERCEPT_IRET);
3891         svm->vcpu.arch.hflags |= HF_IRET_MASK;
3892         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3893         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3894         return 1;
3895 }
3896
3897 static int invlpg_interception(struct vcpu_svm *svm)
3898 {
3899         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3900                 return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3901
3902         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3903         return kvm_skip_emulated_instruction(&svm->vcpu);
3904 }
3905
3906 static int emulate_on_interception(struct vcpu_svm *svm)
3907 {
3908         return kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3909 }
3910
3911 static int rsm_interception(struct vcpu_svm *svm)
3912 {
3913         return kvm_emulate_instruction_from_buffer(&svm->vcpu,
3914                                         rsm_ins_bytes, 2) == EMULATE_DONE;
3915 }
3916
3917 static int rdpmc_interception(struct vcpu_svm *svm)
3918 {
3919         int err;
3920
3921         if (!static_cpu_has(X86_FEATURE_NRIPS))
3922                 return emulate_on_interception(svm);
3923
3924         err = kvm_rdpmc(&svm->vcpu);
3925         return kvm_complete_insn_gp(&svm->vcpu, err);
3926 }
3927
3928 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3929                                             unsigned long val)
3930 {
3931         unsigned long cr0 = svm->vcpu.arch.cr0;
3932         bool ret = false;
3933         u64 intercept;
3934
3935         intercept = svm->nested.intercept;
3936
3937         if (!is_guest_mode(&svm->vcpu) ||
3938             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3939                 return false;
3940
3941         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3942         val &= ~SVM_CR0_SELECTIVE_MASK;
3943
3944         if (cr0 ^ val) {
3945                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3946                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3947         }
3948
3949         return ret;
3950 }
3951
3952 #define CR_VALID (1ULL << 63)
3953
3954 static int cr_interception(struct vcpu_svm *svm)
3955 {
3956         int reg, cr;
3957         unsigned long val;
3958         int err;
3959
3960         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3961                 return emulate_on_interception(svm);
3962
3963         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3964                 return emulate_on_interception(svm);
3965
3966         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3967         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3968                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3969         else
3970                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3971
3972         err = 0;
3973         if (cr >= 16) { /* mov to cr */
3974                 cr -= 16;
3975                 val = kvm_register_read(&svm->vcpu, reg);
3976                 switch (cr) {
3977                 case 0:
3978                         if (!check_selective_cr0_intercepted(svm, val))
3979                                 err = kvm_set_cr0(&svm->vcpu, val);
3980                         else
3981                                 return 1;
3982
3983                         break;
3984                 case 3:
3985                         err = kvm_set_cr3(&svm->vcpu, val);
3986                         break;
3987                 case 4:
3988                         err = kvm_set_cr4(&svm->vcpu, val);
3989                         break;
3990                 case 8:
3991                         err = kvm_set_cr8(&svm->vcpu, val);
3992                         break;
3993                 default:
3994                         WARN(1, "unhandled write to CR%d", cr);
3995                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3996                         return 1;
3997                 }
3998         } else { /* mov from cr */
3999                 switch (cr) {
4000                 case 0:
4001                         val = kvm_read_cr0(&svm->vcpu);
4002                         break;
4003                 case 2:
4004                         val = svm->vcpu.arch.cr2;
4005                         break;
4006                 case 3:
4007                         val = kvm_read_cr3(&svm->vcpu);
4008                         break;
4009                 case 4:
4010                         val = kvm_read_cr4(&svm->vcpu);
4011                         break;
4012                 case 8:
4013                         val = kvm_get_cr8(&svm->vcpu);
4014                         break;
4015                 default:
4016                         WARN(1, "unhandled read from CR%d", cr);
4017                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
4018                         return 1;
4019                 }
4020                 kvm_register_write(&svm->vcpu, reg, val);
4021         }
4022         return kvm_complete_insn_gp(&svm->vcpu, err);
4023 }
4024
4025 static int dr_interception(struct vcpu_svm *svm)
4026 {
4027         int reg, dr;
4028         unsigned long val;
4029
4030         if (svm->vcpu.guest_debug == 0) {
4031                 /*
4032                  * No more DR vmexits; force a reload of the debug registers
4033                  * and reenter on this instruction.  The next vmexit will
4034                  * retrieve the full state of the debug registers.
4035                  */
4036                 clr_dr_intercepts(svm);
4037                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4038                 return 1;
4039         }
4040
4041         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
4042                 return emulate_on_interception(svm);
4043
4044         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
4045         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4046
4047         if (dr >= 16) { /* mov to DRn */
4048                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4049                         return 1;
4050                 val = kvm_register_read(&svm->vcpu, reg);
4051                 kvm_set_dr(&svm->vcpu, dr - 16, val);
4052         } else {
4053                 if (!kvm_require_dr(&svm->vcpu, dr))
4054                         return 1;
4055                 kvm_get_dr(&svm->vcpu, dr, &val);
4056                 kvm_register_write(&svm->vcpu, reg, val);
4057         }
4058
4059         return kvm_skip_emulated_instruction(&svm->vcpu);
4060 }
4061
4062 static int cr8_write_interception(struct vcpu_svm *svm)
4063 {
4064         struct kvm_run *kvm_run = svm->vcpu.run;
4065         int r;
4066
4067         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4068         /* instruction emulation calls kvm_set_cr8() */
4069         r = cr_interception(svm);
4070         if (lapic_in_kernel(&svm->vcpu))
4071                 return r;
4072         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4073                 return r;
4074         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4075         return 0;
4076 }
4077
4078 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4079 {
4080         msr->data = 0;
4081
4082         switch (msr->index) {
4083         case MSR_F10H_DECFG:
4084                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4085                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4086                 break;
4087         default:
4088                 return 1;
4089         }
4090
4091         return 0;
4092 }
4093
4094 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4095 {
4096         struct vcpu_svm *svm = to_svm(vcpu);
4097
4098         switch (msr_info->index) {
4099         case MSR_STAR:
4100                 msr_info->data = svm->vmcb->save.star;
4101                 break;
4102 #ifdef CONFIG_X86_64
4103         case MSR_LSTAR:
4104                 msr_info->data = svm->vmcb->save.lstar;
4105                 break;
4106         case MSR_CSTAR:
4107                 msr_info->data = svm->vmcb->save.cstar;
4108                 break;
4109         case MSR_KERNEL_GS_BASE:
4110                 msr_info->data = svm->vmcb->save.kernel_gs_base;
4111                 break;
4112         case MSR_SYSCALL_MASK:
4113                 msr_info->data = svm->vmcb->save.sfmask;
4114                 break;
4115 #endif
4116         case MSR_IA32_SYSENTER_CS:
4117                 msr_info->data = svm->vmcb->save.sysenter_cs;
4118                 break;
4119         case MSR_IA32_SYSENTER_EIP:
4120                 msr_info->data = svm->sysenter_eip;
4121                 break;
4122         case MSR_IA32_SYSENTER_ESP:
4123                 msr_info->data = svm->sysenter_esp;
4124                 break;
4125         case MSR_TSC_AUX:
4126                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4127                         return 1;
4128                 msr_info->data = svm->tsc_aux;
4129                 break;
4130         /*
4131          * Nobody will change the following 5 values in the VMCB so we can
4132          * safely return them on rdmsr. They will always be 0 until LBRV is
4133          * implemented.
4134          */
4135         case MSR_IA32_DEBUGCTLMSR:
4136                 msr_info->data = svm->vmcb->save.dbgctl;
4137                 break;
4138         case MSR_IA32_LASTBRANCHFROMIP:
4139                 msr_info->data = svm->vmcb->save.br_from;
4140                 break;
4141         case MSR_IA32_LASTBRANCHTOIP:
4142                 msr_info->data = svm->vmcb->save.br_to;
4143                 break;
4144         case MSR_IA32_LASTINTFROMIP:
4145                 msr_info->data = svm->vmcb->save.last_excp_from;
4146                 break;
4147         case MSR_IA32_LASTINTTOIP:
4148                 msr_info->data = svm->vmcb->save.last_excp_to;
4149                 break;
4150         case MSR_VM_HSAVE_PA:
4151                 msr_info->data = svm->nested.hsave_msr;
4152                 break;
4153         case MSR_VM_CR:
4154                 msr_info->data = svm->nested.vm_cr_msr;
4155                 break;
4156         case MSR_IA32_SPEC_CTRL:
4157                 if (!msr_info->host_initiated &&
4158                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4159                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4160                         return 1;
4161
4162                 msr_info->data = svm->spec_ctrl;
4163                 break;
4164         case MSR_AMD64_VIRT_SPEC_CTRL:
4165                 if (!msr_info->host_initiated &&
4166                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4167                         return 1;
4168
4169                 msr_info->data = svm->virt_spec_ctrl;
4170                 break;
4171         case MSR_F15H_IC_CFG: {
4172
4173                 int family, model;
4174
4175                 family = guest_cpuid_family(vcpu);
4176                 model  = guest_cpuid_model(vcpu);
4177
4178                 if (family < 0 || model < 0)
4179                         return kvm_get_msr_common(vcpu, msr_info);
4180
4181                 msr_info->data = 0;
4182
4183                 if (family == 0x15 &&
4184                     (model >= 0x2 && model < 0x20))
4185                         msr_info->data = 0x1E;
4186                 }
4187                 break;
4188         case MSR_F10H_DECFG:
4189                 msr_info->data = svm->msr_decfg;
4190                 break;
4191         default:
4192                 return kvm_get_msr_common(vcpu, msr_info);
4193         }
4194         return 0;
4195 }
4196
4197 static int rdmsr_interception(struct vcpu_svm *svm)
4198 {
4199         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4200         struct msr_data msr_info;
4201
4202         msr_info.index = ecx;
4203         msr_info.host_initiated = false;
4204         if (svm_get_msr(&svm->vcpu, &msr_info)) {
4205                 trace_kvm_msr_read_ex(ecx);
4206                 kvm_inject_gp(&svm->vcpu, 0);
4207                 return 1;
4208         } else {
4209                 trace_kvm_msr_read(ecx, msr_info.data);
4210
4211                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
4212                                    msr_info.data & 0xffffffff);
4213                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
4214                                    msr_info.data >> 32);
4215                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4216                 return kvm_skip_emulated_instruction(&svm->vcpu);
4217         }
4218 }
4219
4220 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4221 {
4222         struct vcpu_svm *svm = to_svm(vcpu);
4223         int svm_dis, chg_mask;
4224
4225         if (data & ~SVM_VM_CR_VALID_MASK)
4226                 return 1;
4227
4228         chg_mask = SVM_VM_CR_VALID_MASK;
4229
4230         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4231                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4232
4233         svm->nested.vm_cr_msr &= ~chg_mask;
4234         svm->nested.vm_cr_msr |= (data & chg_mask);
4235
4236         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4237
4238         /* check for svm_disable while efer.svme is set */
4239         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4240                 return 1;
4241
4242         return 0;
4243 }
4244
4245 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4246 {
4247         struct vcpu_svm *svm = to_svm(vcpu);
4248
4249         u32 ecx = msr->index;
4250         u64 data = msr->data;
4251         switch (ecx) {
4252         case MSR_IA32_CR_PAT:
4253                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4254                         return 1;
4255                 vcpu->arch.pat = data;
4256                 svm->vmcb->save.g_pat = data;
4257                 mark_dirty(svm->vmcb, VMCB_NPT);
4258                 break;
4259         case MSR_IA32_SPEC_CTRL:
4260                 if (!msr->host_initiated &&
4261                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
4262                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
4263                         return 1;
4264
4265                 /* The STIBP bit doesn't fault even if it's not advertised */
4266                 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
4267                         return 1;
4268
4269                 svm->spec_ctrl = data;
4270
4271                 if (!data)
4272                         break;
4273
4274                 /*
4275                  * For non-nested:
4276                  * When it's written (to non-zero) for the first time, pass
4277                  * it through.
4278                  *
4279                  * For nested:
4280                  * The handling of the MSR bitmap for L2 guests is done in
4281                  * nested_svm_vmrun_msrpm.
4282                  * We update the L1 MSR bit as well since it will end up
4283                  * touching the MSR anyway now.
4284                  */
4285                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4286                 break;
4287         case MSR_IA32_PRED_CMD:
4288                 if (!msr->host_initiated &&
4289                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4290                         return 1;
4291
4292                 if (data & ~PRED_CMD_IBPB)
4293                         return 1;
4294
4295                 if (!data)
4296                         break;
4297
4298                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4299                 if (is_guest_mode(vcpu))
4300                         break;
4301                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4302                 break;
4303         case MSR_AMD64_VIRT_SPEC_CTRL:
4304                 if (!msr->host_initiated &&
4305                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
4306                         return 1;
4307
4308                 if (data & ~SPEC_CTRL_SSBD)
4309                         return 1;
4310
4311                 svm->virt_spec_ctrl = data;
4312                 break;
4313         case MSR_STAR:
4314                 svm->vmcb->save.star = data;
4315                 break;
4316 #ifdef CONFIG_X86_64
4317         case MSR_LSTAR:
4318                 svm->vmcb->save.lstar = data;
4319                 break;
4320         case MSR_CSTAR:
4321                 svm->vmcb->save.cstar = data;
4322                 break;
4323         case MSR_KERNEL_GS_BASE:
4324                 svm->vmcb->save.kernel_gs_base = data;
4325                 break;
4326         case MSR_SYSCALL_MASK:
4327                 svm->vmcb->save.sfmask = data;
4328                 break;
4329 #endif
4330         case MSR_IA32_SYSENTER_CS:
4331                 svm->vmcb->save.sysenter_cs = data;
4332                 break;
4333         case MSR_IA32_SYSENTER_EIP:
4334                 svm->sysenter_eip = data;
4335                 svm->vmcb->save.sysenter_eip = data;
4336                 break;
4337         case MSR_IA32_SYSENTER_ESP:
4338                 svm->sysenter_esp = data;
4339                 svm->vmcb->save.sysenter_esp = data;
4340                 break;
4341         case MSR_TSC_AUX:
4342                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4343                         return 1;
4344
4345                 /*
4346                  * This is rare, so we update the MSR here instead of using
4347                  * direct_access_msrs.  Doing that would require a rdmsr in
4348                  * svm_vcpu_put.
4349                  */
4350                 svm->tsc_aux = data;
4351                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4352                 break;
4353         case MSR_IA32_DEBUGCTLMSR:
4354                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4355                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4356                                     __func__, data);
4357                         break;
4358                 }
4359                 if (data & DEBUGCTL_RESERVED_BITS)
4360                         return 1;
4361
4362                 svm->vmcb->save.dbgctl = data;
4363                 mark_dirty(svm->vmcb, VMCB_LBR);
4364                 if (data & (1ULL<<0))
4365                         svm_enable_lbrv(svm);
4366                 else
4367                         svm_disable_lbrv(svm);
4368                 break;
4369         case MSR_VM_HSAVE_PA:
4370                 svm->nested.hsave_msr = data;
4371                 break;
4372         case MSR_VM_CR:
4373                 return svm_set_vm_cr(vcpu, data);
4374         case MSR_VM_IGNNE:
4375                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4376                 break;
4377         case MSR_F10H_DECFG: {
4378                 struct kvm_msr_entry msr_entry;
4379
4380                 msr_entry.index = msr->index;
4381                 if (svm_get_msr_feature(&msr_entry))
4382                         return 1;
4383
4384                 /* Check the supported bits */
4385                 if (data & ~msr_entry.data)
4386                         return 1;
4387
4388                 /* Don't allow the guest to change a bit, #GP */
4389                 if (!msr->host_initiated && (data ^ msr_entry.data))
4390                         return 1;
4391
4392                 svm->msr_decfg = data;
4393                 break;
4394         }
4395         case MSR_IA32_APICBASE:
4396                 if (kvm_vcpu_apicv_active(vcpu))
4397                         avic_update_vapic_bar(to_svm(vcpu), data);
4398                 /* Follow through */
4399         default:
4400                 return kvm_set_msr_common(vcpu, msr);
4401         }
4402         return 0;
4403 }
4404
4405 static int wrmsr_interception(struct vcpu_svm *svm)
4406 {
4407         struct msr_data msr;
4408         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4409         u64 data = kvm_read_edx_eax(&svm->vcpu);
4410
4411         msr.data = data;
4412         msr.index = ecx;
4413         msr.host_initiated = false;
4414
4415         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4416         if (kvm_set_msr(&svm->vcpu, &msr)) {
4417                 trace_kvm_msr_write_ex(ecx, data);
4418                 kvm_inject_gp(&svm->vcpu, 0);
4419                 return 1;
4420         } else {
4421                 trace_kvm_msr_write(ecx, data);
4422                 return kvm_skip_emulated_instruction(&svm->vcpu);
4423         }
4424 }
4425
4426 static int msr_interception(struct vcpu_svm *svm)
4427 {
4428         if (svm->vmcb->control.exit_info_1)
4429                 return wrmsr_interception(svm);
4430         else
4431                 return rdmsr_interception(svm);
4432 }
4433
4434 static int interrupt_window_interception(struct vcpu_svm *svm)
4435 {
4436         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4437         svm_clear_vintr(svm);
4438         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4439         mark_dirty(svm->vmcb, VMCB_INTR);
4440         ++svm->vcpu.stat.irq_window_exits;
4441         return 1;
4442 }
4443
4444 static int pause_interception(struct vcpu_svm *svm)
4445 {
4446         struct kvm_vcpu *vcpu = &svm->vcpu;
4447         bool in_kernel = (svm_get_cpl(vcpu) == 0);
4448
4449         if (pause_filter_thresh)
4450                 grow_ple_window(vcpu);
4451
4452         kvm_vcpu_on_spin(vcpu, in_kernel);
4453         return 1;
4454 }
4455
4456 static int nop_interception(struct vcpu_svm *svm)
4457 {
4458         return kvm_skip_emulated_instruction(&(svm->vcpu));
4459 }
4460
4461 static int monitor_interception(struct vcpu_svm *svm)
4462 {
4463         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4464         return nop_interception(svm);
4465 }
4466
4467 static int mwait_interception(struct vcpu_svm *svm)
4468 {
4469         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4470         return nop_interception(svm);
4471 }
4472
4473 enum avic_ipi_failure_cause {
4474         AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4475         AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4476         AVIC_IPI_FAILURE_INVALID_TARGET,
4477         AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4478 };
4479
4480 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4481 {
4482         u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4483         u32 icrl = svm->vmcb->control.exit_info_1;
4484         u32 id = svm->vmcb->control.exit_info_2 >> 32;
4485         u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4486         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4487
4488         trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4489
4490         switch (id) {
4491         case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4492                 /*
4493                  * AVIC hardware handles the generation of
4494                  * IPIs when the specified Message Type is Fixed
4495                  * (also known as fixed delivery mode) and
4496                  * the Trigger Mode is edge-triggered. The hardware
4497                  * also supports self and broadcast delivery modes
4498                  * specified via the Destination Shorthand(DSH)
4499                  * field of the ICRL. Logical and physical APIC ID
4500                  * formats are supported. All other IPI types cause
4501                  * a #VMEXIT, which needs to emulated.
4502                  */
4503                 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4504                 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4505                 break;
4506         case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4507                 int i;
4508                 struct kvm_vcpu *vcpu;
4509                 struct kvm *kvm = svm->vcpu.kvm;
4510                 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4511
4512                 /*
4513                  * At this point, we expect that the AVIC HW has already
4514                  * set the appropriate IRR bits on the valid target
4515                  * vcpus. So, we just need to kick the appropriate vcpu.
4516                  */
4517                 kvm_for_each_vcpu(i, vcpu, kvm) {
4518                         bool m = kvm_apic_match_dest(vcpu, apic,
4519                                                      icrl & KVM_APIC_SHORT_MASK,
4520                                                      GET_APIC_DEST_FIELD(icrh),
4521                                                      icrl & KVM_APIC_DEST_MASK);
4522
4523                         if (m && !avic_vcpu_is_running(vcpu))
4524                                 kvm_vcpu_wake_up(vcpu);
4525                 }
4526                 break;
4527         }
4528         case AVIC_IPI_FAILURE_INVALID_TARGET:
4529                 break;
4530         case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4531                 WARN_ONCE(1, "Invalid backing page\n");
4532                 break;
4533         default:
4534                 pr_err("Unknown IPI interception\n");
4535         }
4536
4537         return 1;
4538 }
4539
4540 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4541 {
4542         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4543         int index;
4544         u32 *logical_apic_id_table;
4545         int dlid = GET_APIC_LOGICAL_ID(ldr);
4546
4547         if (!dlid)
4548                 return NULL;
4549
4550         if (flat) { /* flat */
4551                 index = ffs(dlid) - 1;
4552                 if (index > 7)
4553                         return NULL;
4554         } else { /* cluster */
4555                 int cluster = (dlid & 0xf0) >> 4;
4556                 int apic = ffs(dlid & 0x0f) - 1;
4557
4558                 if ((apic < 0) || (apic > 7) ||
4559                     (cluster >= 0xf))
4560                         return NULL;
4561                 index = (cluster << 2) + apic;
4562         }
4563
4564         logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4565
4566         return &logical_apic_id_table[index];
4567 }
4568
4569 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
4570                           bool valid)
4571 {
4572         bool flat;
4573         u32 *entry, new_entry;
4574
4575         flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4576         entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4577         if (!entry)
4578                 return -EINVAL;
4579
4580         new_entry = READ_ONCE(*entry);
4581         new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4582         new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4583         if (valid)
4584                 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4585         else
4586                 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4587         WRITE_ONCE(*entry, new_entry);
4588
4589         return 0;
4590 }
4591
4592 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4593 {
4594         int ret;
4595         struct vcpu_svm *svm = to_svm(vcpu);
4596         u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4597
4598         if (!ldr)
4599                 return 1;
4600
4601         ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
4602         if (ret && svm->ldr_reg) {
4603                 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
4604                 svm->ldr_reg = 0;
4605         } else {
4606                 svm->ldr_reg = ldr;
4607         }
4608         return ret;
4609 }
4610
4611 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4612 {
4613         u64 *old, *new;
4614         struct vcpu_svm *svm = to_svm(vcpu);
4615         u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4616         u32 id = (apic_id_reg >> 24) & 0xff;
4617
4618         if (vcpu->vcpu_id == id)
4619                 return 0;
4620
4621         old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4622         new = avic_get_physical_id_entry(vcpu, id);
4623         if (!new || !old)
4624                 return 1;
4625
4626         /* We need to move physical_id_entry to new offset */
4627         *new = *old;
4628         *old = 0ULL;
4629         to_svm(vcpu)->avic_physical_id_cache = new;
4630
4631         /*
4632          * Also update the guest physical APIC ID in the logical
4633          * APIC ID table entry if already setup the LDR.
4634          */
4635         if (svm->ldr_reg)
4636                 avic_handle_ldr_update(vcpu);
4637
4638         return 0;
4639 }
4640
4641 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4642 {
4643         struct vcpu_svm *svm = to_svm(vcpu);
4644         struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4645         u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4646         u32 mod = (dfr >> 28) & 0xf;
4647
4648         /*
4649          * We assume that all local APICs are using the same type.
4650          * If this changes, we need to flush the AVIC logical
4651          * APID id table.
4652          */
4653         if (kvm_svm->ldr_mode == mod)
4654                 return 0;
4655
4656         clear_page(page_address(kvm_svm->avic_logical_id_table_page));
4657         kvm_svm->ldr_mode = mod;
4658
4659         if (svm->ldr_reg)
4660                 avic_handle_ldr_update(vcpu);
4661         return 0;
4662 }
4663
4664 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4665 {
4666         struct kvm_lapic *apic = svm->vcpu.arch.apic;
4667         u32 offset = svm->vmcb->control.exit_info_1 &
4668                                 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4669
4670         switch (offset) {
4671         case APIC_ID:
4672                 if (avic_handle_apic_id_update(&svm->vcpu))
4673                         return 0;
4674                 break;
4675         case APIC_LDR:
4676                 if (avic_handle_ldr_update(&svm->vcpu))
4677                         return 0;
4678                 break;
4679         case APIC_DFR:
4680                 avic_handle_dfr_update(&svm->vcpu);
4681                 break;
4682         default:
4683                 break;
4684         }
4685
4686         kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4687
4688         return 1;
4689 }
4690
4691 static bool is_avic_unaccelerated_access_trap(u32 offset)
4692 {
4693         bool ret = false;
4694
4695         switch (offset) {
4696         case APIC_ID:
4697         case APIC_EOI:
4698         case APIC_RRR:
4699         case APIC_LDR:
4700         case APIC_DFR:
4701         case APIC_SPIV:
4702         case APIC_ESR:
4703         case APIC_ICR:
4704         case APIC_LVTT:
4705         case APIC_LVTTHMR:
4706         case APIC_LVTPC:
4707         case APIC_LVT0:
4708         case APIC_LVT1:
4709         case APIC_LVTERR:
4710         case APIC_TMICT:
4711         case APIC_TDCR:
4712                 ret = true;
4713                 break;
4714         default:
4715                 break;
4716         }
4717         return ret;
4718 }
4719
4720 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4721 {
4722         int ret = 0;
4723         u32 offset = svm->vmcb->control.exit_info_1 &
4724                      AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4725         u32 vector = svm->vmcb->control.exit_info_2 &
4726                      AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4727         bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4728                      AVIC_UNACCEL_ACCESS_WRITE_MASK;
4729         bool trap = is_avic_unaccelerated_access_trap(offset);
4730
4731         trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4732                                             trap, write, vector);
4733         if (trap) {
4734                 /* Handling Trap */
4735                 WARN_ONCE(!write, "svm: Handling trap read.\n");
4736                 ret = avic_unaccel_trap_write(svm);
4737         } else {
4738                 /* Handling Fault */
4739                 ret = (kvm_emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4740         }
4741
4742         return ret;
4743 }
4744
4745 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4746         [SVM_EXIT_READ_CR0]                     = cr_interception,
4747         [SVM_EXIT_READ_CR3]                     = cr_interception,
4748         [SVM_EXIT_READ_CR4]                     = cr_interception,
4749         [SVM_EXIT_READ_CR8]                     = cr_interception,
4750         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
4751         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
4752         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
4753         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
4754         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
4755         [SVM_EXIT_READ_DR0]                     = dr_interception,
4756         [SVM_EXIT_READ_DR1]                     = dr_interception,
4757         [SVM_EXIT_READ_DR2]                     = dr_interception,
4758         [SVM_EXIT_READ_DR3]                     = dr_interception,
4759         [SVM_EXIT_READ_DR4]                     = dr_interception,
4760         [SVM_EXIT_READ_DR5]                     = dr_interception,
4761         [SVM_EXIT_READ_DR6]                     = dr_interception,
4762         [SVM_EXIT_READ_DR7]                     = dr_interception,
4763         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
4764         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
4765         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
4766         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
4767         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
4768         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
4769         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
4770         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
4771         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
4772         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
4773         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
4774         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
4775         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
4776         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
4777         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
4778         [SVM_EXIT_INTR]                         = intr_interception,
4779         [SVM_EXIT_NMI]                          = nmi_interception,
4780         [SVM_EXIT_SMI]                          = nop_on_interception,
4781         [SVM_EXIT_INIT]                         = nop_on_interception,
4782         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
4783         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
4784         [SVM_EXIT_CPUID]                        = cpuid_interception,
4785         [SVM_EXIT_IRET]                         = iret_interception,
4786         [SVM_EXIT_INVD]                         = emulate_on_interception,
4787         [SVM_EXIT_PAUSE]                        = pause_interception,
4788         [SVM_EXIT_HLT]                          = halt_interception,
4789         [SVM_EXIT_INVLPG]                       = invlpg_interception,
4790         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
4791         [SVM_EXIT_IOIO]                         = io_interception,
4792         [SVM_EXIT_MSR]                          = msr_interception,
4793         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
4794         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
4795         [SVM_EXIT_VMRUN]                        = vmrun_interception,
4796         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
4797         [SVM_EXIT_VMLOAD]                       = vmload_interception,
4798         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
4799         [SVM_EXIT_STGI]                         = stgi_interception,
4800         [SVM_EXIT_CLGI]                         = clgi_interception,
4801         [SVM_EXIT_SKINIT]                       = skinit_interception,
4802         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
4803         [SVM_EXIT_MONITOR]                      = monitor_interception,
4804         [SVM_EXIT_MWAIT]                        = mwait_interception,
4805         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
4806         [SVM_EXIT_NPF]                          = npf_interception,
4807         [SVM_EXIT_RSM]                          = rsm_interception,
4808         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
4809         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
4810 };
4811
4812 static void dump_vmcb(struct kvm_vcpu *vcpu)
4813 {
4814         struct vcpu_svm *svm = to_svm(vcpu);
4815         struct vmcb_control_area *control = &svm->vmcb->control;
4816         struct vmcb_save_area *save = &svm->vmcb->save;
4817
4818         pr_err("VMCB Control Area:\n");
4819         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4820         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4821         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4822         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4823         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4824         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4825         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4826         pr_err("%-20s%d\n", "pause filter threshold:",
4827                control->pause_filter_thresh);
4828         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4829         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4830         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4831         pr_err("%-20s%d\n", "asid:", control->asid);
4832         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4833         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4834         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4835         pr_err("%-20s%08x\n", "int_state:", control->int_state);
4836         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4837         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4838         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4839         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4840         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4841         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4842         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4843         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4844         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4845         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4846         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4847         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4848         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4849         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4850         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4851         pr_err("VMCB State Save Area:\n");
4852         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4853                "es:",
4854                save->es.selector, save->es.attrib,
4855                save->es.limit, save->es.base);
4856         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4857                "cs:",
4858                save->cs.selector, save->cs.attrib,
4859                save->cs.limit, save->cs.base);
4860         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4861                "ss:",
4862                save->ss.selector, save->ss.attrib,
4863                save->ss.limit, save->ss.base);
4864         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4865                "ds:",
4866                save->ds.selector, save->ds.attrib,
4867                save->ds.limit, save->ds.base);
4868         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4869                "fs:",
4870                save->fs.selector, save->fs.attrib,
4871                save->fs.limit, save->fs.base);
4872         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4873                "gs:",
4874                save->gs.selector, save->gs.attrib,
4875                save->gs.limit, save->gs.base);
4876         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4877                "gdtr:",
4878                save->gdtr.selector, save->gdtr.attrib,
4879                save->gdtr.limit, save->gdtr.base);
4880         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4881                "ldtr:",
4882                save->ldtr.selector, save->ldtr.attrib,
4883                save->ldtr.limit, save->ldtr.base);
4884         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4885                "idtr:",
4886                save->idtr.selector, save->idtr.attrib,
4887                save->idtr.limit, save->idtr.base);
4888         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4889                "tr:",
4890                save->tr.selector, save->tr.attrib,
4891                save->tr.limit, save->tr.base);
4892         pr_err("cpl:            %d                efer:         %016llx\n",
4893                 save->cpl, save->efer);
4894         pr_err("%-15s %016llx %-13s %016llx\n",
4895                "cr0:", save->cr0, "cr2:", save->cr2);
4896         pr_err("%-15s %016llx %-13s %016llx\n",
4897                "cr3:", save->cr3, "cr4:", save->cr4);
4898         pr_err("%-15s %016llx %-13s %016llx\n",
4899                "dr6:", save->dr6, "dr7:", save->dr7);
4900         pr_err("%-15s %016llx %-13s %016llx\n",
4901                "rip:", save->rip, "rflags:", save->rflags);
4902         pr_err("%-15s %016llx %-13s %016llx\n",
4903                "rsp:", save->rsp, "rax:", save->rax);
4904         pr_err("%-15s %016llx %-13s %016llx\n",
4905                "star:", save->star, "lstar:", save->lstar);
4906         pr_err("%-15s %016llx %-13s %016llx\n",
4907                "cstar:", save->cstar, "sfmask:", save->sfmask);
4908         pr_err("%-15s %016llx %-13s %016llx\n",
4909                "kernel_gs_base:", save->kernel_gs_base,
4910                "sysenter_cs:", save->sysenter_cs);
4911         pr_err("%-15s %016llx %-13s %016llx\n",
4912                "sysenter_esp:", save->sysenter_esp,
4913                "sysenter_eip:", save->sysenter_eip);
4914         pr_err("%-15s %016llx %-13s %016llx\n",
4915                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4916         pr_err("%-15s %016llx %-13s %016llx\n",
4917                "br_from:", save->br_from, "br_to:", save->br_to);
4918         pr_err("%-15s %016llx %-13s %016llx\n",
4919                "excp_from:", save->last_excp_from,
4920                "excp_to:", save->last_excp_to);
4921 }
4922
4923 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4924 {
4925         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4926
4927         *info1 = control->exit_info_1;
4928         *info2 = control->exit_info_2;
4929 }
4930
4931 static int handle_exit(struct kvm_vcpu *vcpu)
4932 {
4933         struct vcpu_svm *svm = to_svm(vcpu);
4934         struct kvm_run *kvm_run = vcpu->run;
4935         u32 exit_code = svm->vmcb->control.exit_code;
4936
4937         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4938
4939         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4940                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4941         if (npt_enabled)
4942                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4943
4944         if (unlikely(svm->nested.exit_required)) {
4945                 nested_svm_vmexit(svm);
4946                 svm->nested.exit_required = false;
4947
4948                 return 1;
4949         }
4950
4951         if (is_guest_mode(vcpu)) {
4952                 int vmexit;
4953
4954                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4955                                         svm->vmcb->control.exit_info_1,
4956                                         svm->vmcb->control.exit_info_2,
4957                                         svm->vmcb->control.exit_int_info,
4958                                         svm->vmcb->control.exit_int_info_err,
4959                                         KVM_ISA_SVM);
4960
4961                 vmexit = nested_svm_exit_special(svm);
4962
4963                 if (vmexit == NESTED_EXIT_CONTINUE)
4964                         vmexit = nested_svm_exit_handled(svm);
4965
4966                 if (vmexit == NESTED_EXIT_DONE)
4967                         return 1;
4968         }
4969
4970         svm_complete_interrupts(svm);
4971
4972         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4973                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4974                 kvm_run->fail_entry.hardware_entry_failure_reason
4975                         = svm->vmcb->control.exit_code;
4976                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4977                 dump_vmcb(vcpu);
4978                 return 0;
4979         }
4980
4981         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4982             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4983             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4984             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4985                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4986                        "exit_code 0x%x\n",
4987                        __func__, svm->vmcb->control.exit_int_info,
4988                        exit_code);
4989
4990         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4991             || !svm_exit_handlers[exit_code]) {
4992                 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4993                 kvm_queue_exception(vcpu, UD_VECTOR);
4994                 return 1;
4995         }
4996
4997         return svm_exit_handlers[exit_code](svm);
4998 }
4999
5000 static void reload_tss(struct kvm_vcpu *vcpu)
5001 {
5002         int cpu = raw_smp_processor_id();
5003
5004         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5005         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
5006         load_TR_desc();
5007 }
5008
5009 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
5010 {
5011         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5012         int asid = sev_get_asid(svm->vcpu.kvm);
5013
5014         /* Assign the asid allocated with this SEV guest */
5015         svm->vmcb->control.asid = asid;
5016
5017         /*
5018          * Flush guest TLB:
5019          *
5020          * 1) when different VMCB for the same ASID is to be run on the same host CPU.
5021          * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
5022          */
5023         if (sd->sev_vmcbs[asid] == svm->vmcb &&
5024             svm->last_cpu == cpu)
5025                 return;
5026
5027         svm->last_cpu = cpu;
5028         sd->sev_vmcbs[asid] = svm->vmcb;
5029         svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5030         mark_dirty(svm->vmcb, VMCB_ASID);
5031 }
5032
5033 static void pre_svm_run(struct vcpu_svm *svm)
5034 {
5035         int cpu = raw_smp_processor_id();
5036
5037         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
5038
5039         if (sev_guest(svm->vcpu.kvm))
5040                 return pre_sev_run(svm, cpu);
5041
5042         /* FIXME: handle wraparound of asid_generation */
5043         if (svm->asid_generation != sd->asid_generation)
5044                 new_asid(svm, sd);
5045 }
5046
5047 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
5048 {
5049         struct vcpu_svm *svm = to_svm(vcpu);
5050
5051         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
5052         vcpu->arch.hflags |= HF_NMI_MASK;
5053         set_intercept(svm, INTERCEPT_IRET);
5054         ++vcpu->stat.nmi_injections;
5055 }
5056
5057 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
5058 {
5059         struct vmcb_control_area *control;
5060
5061         /* The following fields are ignored when AVIC is enabled */
5062         control = &svm->vmcb->control;
5063         control->int_vector = irq;
5064         control->int_ctl &= ~V_INTR_PRIO_MASK;
5065         control->int_ctl |= V_IRQ_MASK |
5066                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5067         mark_dirty(svm->vmcb, VMCB_INTR);
5068 }
5069
5070 static void svm_set_irq(struct kvm_vcpu *vcpu)
5071 {
5072         struct vcpu_svm *svm = to_svm(vcpu);
5073
5074         BUG_ON(!(gif_set(svm)));
5075
5076         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5077         ++vcpu->stat.irq_injections;
5078
5079         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5080                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5081 }
5082
5083 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5084 {
5085         return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5086 }
5087
5088 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5089 {
5090         struct vcpu_svm *svm = to_svm(vcpu);
5091
5092         if (svm_nested_virtualize_tpr(vcpu) ||
5093             kvm_vcpu_apicv_active(vcpu))
5094                 return;
5095
5096         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5097
5098         if (irr == -1)
5099                 return;
5100
5101         if (tpr >= irr)
5102                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5103 }
5104
5105 static void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
5106 {
5107         return;
5108 }
5109
5110 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5111 {
5112         return avic && irqchip_split(vcpu->kvm);
5113 }
5114
5115 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5116 {
5117 }
5118
5119 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5120 {
5121 }
5122
5123 /* Note: Currently only used by Hyper-V. */
5124 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5125 {
5126         struct vcpu_svm *svm = to_svm(vcpu);
5127         struct vmcb *vmcb = svm->vmcb;
5128
5129         if (!kvm_vcpu_apicv_active(&svm->vcpu))
5130                 return;
5131
5132         vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5133         mark_dirty(vmcb, VMCB_INTR);
5134 }
5135
5136 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5137 {
5138         return;
5139 }
5140
5141 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5142 {
5143         kvm_lapic_set_irr(vec, vcpu->arch.apic);
5144         smp_mb__after_atomic();
5145
5146         if (avic_vcpu_is_running(vcpu))
5147                 wrmsrl(SVM_AVIC_DOORBELL,
5148                        kvm_cpu_get_apicid(vcpu->cpu));
5149         else
5150                 kvm_vcpu_wake_up(vcpu);
5151 }
5152
5153 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5154 {
5155         unsigned long flags;
5156         struct amd_svm_iommu_ir *cur;
5157
5158         spin_lock_irqsave(&svm->ir_list_lock, flags);
5159         list_for_each_entry(cur, &svm->ir_list, node) {
5160                 if (cur->data != pi->ir_data)
5161                         continue;
5162                 list_del(&cur->node);
5163                 kfree(cur);
5164                 break;
5165         }
5166         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5167 }
5168
5169 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5170 {
5171         int ret = 0;
5172         unsigned long flags;
5173         struct amd_svm_iommu_ir *ir;
5174
5175         /**
5176          * In some cases, the existing irte is updaed and re-set,
5177          * so we need to check here if it's already been * added
5178          * to the ir_list.
5179          */
5180         if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5181                 struct kvm *kvm = svm->vcpu.kvm;
5182                 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5183                 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5184                 struct vcpu_svm *prev_svm;
5185
5186                 if (!prev_vcpu) {
5187                         ret = -EINVAL;
5188                         goto out;
5189                 }
5190
5191                 prev_svm = to_svm(prev_vcpu);
5192                 svm_ir_list_del(prev_svm, pi);
5193         }
5194
5195         /**
5196          * Allocating new amd_iommu_pi_data, which will get
5197          * add to the per-vcpu ir_list.
5198          */
5199         ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
5200         if (!ir) {
5201                 ret = -ENOMEM;
5202                 goto out;
5203         }
5204         ir->data = pi->ir_data;
5205
5206         spin_lock_irqsave(&svm->ir_list_lock, flags);
5207         list_add(&ir->node, &svm->ir_list);
5208         spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5209 out:
5210         return ret;
5211 }
5212
5213 /**
5214  * Note:
5215  * The HW cannot support posting multicast/broadcast
5216  * interrupts to a vCPU. So, we still use legacy interrupt
5217  * remapping for these kind of interrupts.
5218  *
5219  * For lowest-priority interrupts, we only support
5220  * those with single CPU as the destination, e.g. user
5221  * configures the interrupts via /proc/irq or uses
5222  * irqbalance to make the interrupts single-CPU.
5223  */
5224 static int
5225 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5226                  struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5227 {
5228         struct kvm_lapic_irq irq;
5229         struct kvm_vcpu *vcpu = NULL;
5230
5231         kvm_set_msi_irq(kvm, e, &irq);
5232
5233         if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5234                 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5235                          __func__, irq.vector);
5236                 return -1;
5237         }
5238
5239         pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5240                  irq.vector);
5241         *svm = to_svm(vcpu);
5242         vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5243         vcpu_info->vector = irq.vector;
5244
5245         return 0;
5246 }
5247
5248 /*
5249  * svm_update_pi_irte - set IRTE for Posted-Interrupts
5250  *
5251  * @kvm: kvm
5252  * @host_irq: host irq of the interrupt
5253  * @guest_irq: gsi of the interrupt
5254  * @set: set or unset PI
5255  * returns 0 on success, < 0 on failure
5256  */
5257 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5258                               uint32_t guest_irq, bool set)
5259 {
5260         struct kvm_kernel_irq_routing_entry *e;
5261         struct kvm_irq_routing_table *irq_rt;
5262         int idx, ret = -EINVAL;
5263
5264         if (!kvm_arch_has_assigned_device(kvm) ||
5265             !irq_remapping_cap(IRQ_POSTING_CAP))
5266                 return 0;
5267
5268         pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5269                  __func__, host_irq, guest_irq, set);
5270
5271         idx = srcu_read_lock(&kvm->irq_srcu);
5272         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5273         WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5274
5275         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5276                 struct vcpu_data vcpu_info;
5277                 struct vcpu_svm *svm = NULL;
5278
5279                 if (e->type != KVM_IRQ_ROUTING_MSI)
5280                         continue;
5281
5282                 /**
5283                  * Here, we setup with legacy mode in the following cases:
5284                  * 1. When cannot target interrupt to a specific vcpu.
5285                  * 2. Unsetting posted interrupt.
5286                  * 3. APIC virtialization is disabled for the vcpu.
5287                  */
5288                 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5289                     kvm_vcpu_apicv_active(&svm->vcpu)) {
5290                         struct amd_iommu_pi_data pi;
5291
5292                         /* Try to enable guest_mode in IRTE */
5293                         pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5294                                             AVIC_HPA_MASK);
5295                         pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5296                                                      svm->vcpu.vcpu_id);
5297                         pi.is_guest_mode = true;
5298                         pi.vcpu_data = &vcpu_info;
5299                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5300
5301                         /**
5302                          * Here, we successfully setting up vcpu affinity in
5303                          * IOMMU guest mode. Now, we need to store the posted
5304                          * interrupt information in a per-vcpu ir_list so that
5305                          * we can reference to them directly when we update vcpu
5306                          * scheduling information in IOMMU irte.
5307                          */
5308                         if (!ret && pi.is_guest_mode)
5309                                 svm_ir_list_add(svm, &pi);
5310                 } else {
5311                         /* Use legacy mode in IRTE */
5312                         struct amd_iommu_pi_data pi;
5313
5314                         /**
5315                          * Here, pi is used to:
5316                          * - Tell IOMMU to use legacy mode for this interrupt.
5317                          * - Retrieve ga_tag of prior interrupt remapping data.
5318                          */
5319                         pi.is_guest_mode = false;
5320                         ret = irq_set_vcpu_affinity(host_irq, &pi);
5321
5322                         /**
5323                          * Check if the posted interrupt was previously
5324                          * setup with the guest_mode by checking if the ga_tag
5325                          * was cached. If so, we need to clean up the per-vcpu
5326                          * ir_list.
5327                          */
5328                         if (!ret && pi.prev_ga_tag) {
5329                                 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5330                                 struct kvm_vcpu *vcpu;
5331
5332                                 vcpu = kvm_get_vcpu_by_id(kvm, id);
5333                                 if (vcpu)
5334                                         svm_ir_list_del(to_svm(vcpu), &pi);
5335                         }
5336                 }
5337
5338                 if (!ret && svm) {
5339                         trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5340                                                  e->gsi, vcpu_info.vector,
5341                                                  vcpu_info.pi_desc_addr, set);
5342                 }
5343
5344                 if (ret < 0) {
5345                         pr_err("%s: failed to update PI IRTE\n", __func__);
5346                         goto out;
5347                 }
5348         }
5349
5350         ret = 0;
5351 out:
5352         srcu_read_unlock(&kvm->irq_srcu, idx);
5353         return ret;
5354 }
5355
5356 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5357 {
5358         struct vcpu_svm *svm = to_svm(vcpu);
5359         struct vmcb *vmcb = svm->vmcb;
5360         int ret;
5361         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5362               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5363         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5364
5365         return ret;
5366 }
5367
5368 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5369 {
5370         struct vcpu_svm *svm = to_svm(vcpu);
5371
5372         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5373 }
5374
5375 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5376 {
5377         struct vcpu_svm *svm = to_svm(vcpu);
5378
5379         if (masked) {
5380                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5381                 set_intercept(svm, INTERCEPT_IRET);
5382         } else {
5383                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5384                 clr_intercept(svm, INTERCEPT_IRET);
5385         }
5386 }
5387
5388 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5389 {
5390         struct vcpu_svm *svm = to_svm(vcpu);
5391         struct vmcb *vmcb = svm->vmcb;
5392         int ret;
5393
5394         if (!gif_set(svm) ||
5395              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5396                 return 0;
5397
5398         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5399
5400         if (is_guest_mode(vcpu))
5401                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5402
5403         return ret;
5404 }
5405
5406 static void enable_irq_window(struct kvm_vcpu *vcpu)
5407 {
5408         struct vcpu_svm *svm = to_svm(vcpu);
5409
5410         if (kvm_vcpu_apicv_active(vcpu))
5411                 return;
5412
5413         /*
5414          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5415          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
5416          * get that intercept, this function will be called again though and
5417          * we'll get the vintr intercept. However, if the vGIF feature is
5418          * enabled, the STGI interception will not occur. Enable the irq
5419          * window under the assumption that the hardware will set the GIF.
5420          */
5421         if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5422                 svm_set_vintr(svm);
5423                 svm_inject_irq(svm, 0x0);
5424         }
5425 }
5426
5427 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5428 {
5429         struct vcpu_svm *svm = to_svm(vcpu);
5430
5431         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5432             == HF_NMI_MASK)
5433                 return; /* IRET will cause a vm exit */
5434
5435         if (!gif_set(svm)) {
5436                 if (vgif_enabled(svm))
5437                         set_intercept(svm, INTERCEPT_STGI);
5438                 return; /* STGI will cause a vm exit */
5439         }
5440
5441         if (svm->nested.exit_required)
5442                 return; /* we're not going to run the guest yet */
5443
5444         /*
5445          * Something prevents NMI from been injected. Single step over possible
5446          * problem (IRET or exception injection or interrupt shadow)
5447          */
5448         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5449         svm->nmi_singlestep = true;
5450         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5451 }
5452
5453 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5454 {
5455         return 0;
5456 }
5457
5458 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5459 {
5460         return 0;
5461 }
5462
5463 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5464 {
5465         struct vcpu_svm *svm = to_svm(vcpu);
5466
5467         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5468                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5469         else
5470                 svm->asid_generation--;
5471 }
5472
5473 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
5474 {
5475         struct vcpu_svm *svm = to_svm(vcpu);
5476
5477         invlpga(gva, svm->vmcb->control.asid);
5478 }
5479
5480 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5481 {
5482 }
5483
5484 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5485 {
5486         struct vcpu_svm *svm = to_svm(vcpu);
5487
5488         if (svm_nested_virtualize_tpr(vcpu))
5489                 return;
5490
5491         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5492                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5493                 kvm_set_cr8(vcpu, cr8);
5494         }
5495 }
5496
5497 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5498 {
5499         struct vcpu_svm *svm = to_svm(vcpu);
5500         u64 cr8;
5501
5502         if (svm_nested_virtualize_tpr(vcpu) ||
5503             kvm_vcpu_apicv_active(vcpu))
5504                 return;
5505
5506         cr8 = kvm_get_cr8(vcpu);
5507         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5508         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5509 }
5510
5511 static void svm_complete_interrupts(struct vcpu_svm *svm)
5512 {
5513         u8 vector;
5514         int type;
5515         u32 exitintinfo = svm->vmcb->control.exit_int_info;
5516         unsigned int3_injected = svm->int3_injected;
5517
5518         svm->int3_injected = 0;
5519
5520         /*
5521          * If we've made progress since setting HF_IRET_MASK, we've
5522          * executed an IRET and can allow NMI injection.
5523          */
5524         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5525             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5526                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5527                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5528         }
5529
5530         svm->vcpu.arch.nmi_injected = false;
5531         kvm_clear_exception_queue(&svm->vcpu);
5532         kvm_clear_interrupt_queue(&svm->vcpu);
5533
5534         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5535                 return;
5536
5537         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5538
5539         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5540         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5541
5542         switch (type) {
5543         case SVM_EXITINTINFO_TYPE_NMI:
5544                 svm->vcpu.arch.nmi_injected = true;
5545                 break;
5546         case SVM_EXITINTINFO_TYPE_EXEPT:
5547                 /*
5548                  * In case of software exceptions, do not reinject the vector,
5549                  * but re-execute the instruction instead. Rewind RIP first
5550                  * if we emulated INT3 before.
5551                  */
5552                 if (kvm_exception_is_soft(vector)) {
5553                         if (vector == BP_VECTOR && int3_injected &&
5554                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5555                                 kvm_rip_write(&svm->vcpu,
5556                                               kvm_rip_read(&svm->vcpu) -
5557                                               int3_injected);
5558                         break;
5559                 }
5560                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5561                         u32 err = svm->vmcb->control.exit_int_info_err;
5562                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
5563
5564                 } else
5565                         kvm_requeue_exception(&svm->vcpu, vector);
5566                 break;
5567         case SVM_EXITINTINFO_TYPE_INTR:
5568                 kvm_queue_interrupt(&svm->vcpu, vector, false);
5569                 break;
5570         default:
5571                 break;
5572         }
5573 }
5574
5575 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5576 {
5577         struct vcpu_svm *svm = to_svm(vcpu);
5578         struct vmcb_control_area *control = &svm->vmcb->control;
5579
5580         control->exit_int_info = control->event_inj;
5581         control->exit_int_info_err = control->event_inj_err;
5582         control->event_inj = 0;
5583         svm_complete_interrupts(svm);
5584 }
5585
5586 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5587 {
5588         struct vcpu_svm *svm = to_svm(vcpu);
5589
5590         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5591         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5592         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5593
5594         /*
5595          * A vmexit emulation is required before the vcpu can be executed
5596          * again.
5597          */
5598         if (unlikely(svm->nested.exit_required))
5599                 return;
5600
5601         /*
5602          * Disable singlestep if we're injecting an interrupt/exception.
5603          * We don't want our modified rflags to be pushed on the stack where
5604          * we might not be able to easily reset them if we disabled NMI
5605          * singlestep later.
5606          */
5607         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5608                 /*
5609                  * Event injection happens before external interrupts cause a
5610                  * vmexit and interrupts are disabled here, so smp_send_reschedule
5611                  * is enough to force an immediate vmexit.
5612                  */
5613                 disable_nmi_singlestep(svm);
5614                 smp_send_reschedule(vcpu->cpu);
5615         }
5616
5617         pre_svm_run(svm);
5618
5619         sync_lapic_to_cr8(vcpu);
5620
5621         svm->vmcb->save.cr2 = vcpu->arch.cr2;
5622
5623         clgi();
5624
5625         /*
5626          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5627          * it's non-zero. Since vmentry is serialising on affected CPUs, there
5628          * is no need to worry about the conditional branch over the wrmsr
5629          * being speculatively taken.
5630          */
5631         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
5632
5633         local_irq_enable();
5634
5635         asm volatile (
5636                 "push %%" _ASM_BP "; \n\t"
5637                 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5638                 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5639                 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5640                 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5641                 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5642                 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5643 #ifdef CONFIG_X86_64
5644                 "mov %c[r8](%[svm]),  %%r8  \n\t"
5645                 "mov %c[r9](%[svm]),  %%r9  \n\t"
5646                 "mov %c[r10](%[svm]), %%r10 \n\t"
5647                 "mov %c[r11](%[svm]), %%r11 \n\t"
5648                 "mov %c[r12](%[svm]), %%r12 \n\t"
5649                 "mov %c[r13](%[svm]), %%r13 \n\t"
5650                 "mov %c[r14](%[svm]), %%r14 \n\t"
5651                 "mov %c[r15](%[svm]), %%r15 \n\t"
5652 #endif
5653
5654                 /* Enter guest mode */
5655                 "push %%" _ASM_AX " \n\t"
5656                 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5657                 __ex("vmload %%" _ASM_AX) "\n\t"
5658                 __ex("vmrun %%" _ASM_AX) "\n\t"
5659                 __ex("vmsave %%" _ASM_AX) "\n\t"
5660                 "pop %%" _ASM_AX " \n\t"
5661
5662                 /* Save guest registers, load host registers */
5663                 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5664                 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5665                 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5666                 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5667                 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5668                 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5669 #ifdef CONFIG_X86_64
5670                 "mov %%r8,  %c[r8](%[svm]) \n\t"
5671                 "mov %%r9,  %c[r9](%[svm]) \n\t"
5672                 "mov %%r10, %c[r10](%[svm]) \n\t"
5673                 "mov %%r11, %c[r11](%[svm]) \n\t"
5674                 "mov %%r12, %c[r12](%[svm]) \n\t"
5675                 "mov %%r13, %c[r13](%[svm]) \n\t"
5676                 "mov %%r14, %c[r14](%[svm]) \n\t"
5677                 "mov %%r15, %c[r15](%[svm]) \n\t"
5678                 /*
5679                 * Clear host registers marked as clobbered to prevent
5680                 * speculative use.
5681                 */
5682                 "xor %%r8d, %%r8d \n\t"
5683                 "xor %%r9d, %%r9d \n\t"
5684                 "xor %%r10d, %%r10d \n\t"
5685                 "xor %%r11d, %%r11d \n\t"
5686                 "xor %%r12d, %%r12d \n\t"
5687                 "xor %%r13d, %%r13d \n\t"
5688                 "xor %%r14d, %%r14d \n\t"
5689                 "xor %%r15d, %%r15d \n\t"
5690 #endif
5691                 "xor %%ebx, %%ebx \n\t"
5692                 "xor %%ecx, %%ecx \n\t"
5693                 "xor %%edx, %%edx \n\t"
5694                 "xor %%esi, %%esi \n\t"
5695                 "xor %%edi, %%edi \n\t"
5696                 "pop %%" _ASM_BP
5697                 :
5698                 : [svm]"a"(svm),
5699                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5700                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5701                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5702                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5703                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5704                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5705                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5706 #ifdef CONFIG_X86_64
5707                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5708                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5709                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5710                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5711                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5712                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5713                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5714                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5715 #endif
5716                 : "cc", "memory"
5717 #ifdef CONFIG_X86_64
5718                 , "rbx", "rcx", "rdx", "rsi", "rdi"
5719                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5720 #else
5721                 , "ebx", "ecx", "edx", "esi", "edi"
5722 #endif
5723                 );
5724
5725         /* Eliminate branch target predictions from guest mode */
5726         vmexit_fill_RSB();
5727
5728 #ifdef CONFIG_X86_64
5729         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5730 #else
5731         loadsegment(fs, svm->host.fs);
5732 #ifndef CONFIG_X86_32_LAZY_GS
5733         loadsegment(gs, svm->host.gs);
5734 #endif
5735 #endif
5736
5737         /*
5738          * We do not use IBRS in the kernel. If this vCPU has used the
5739          * SPEC_CTRL MSR it may have left it on; save the value and
5740          * turn it off. This is much more efficient than blindly adding
5741          * it to the atomic save/restore list. Especially as the former
5742          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5743          *
5744          * For non-nested case:
5745          * If the L01 MSR bitmap does not intercept the MSR, then we need to
5746          * save it.
5747          *
5748          * For nested case:
5749          * If the L02 MSR bitmap does not intercept the MSR, then we need to
5750          * save it.
5751          */
5752         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5753                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5754
5755         reload_tss(vcpu);
5756
5757         local_irq_disable();
5758
5759         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
5760
5761         vcpu->arch.cr2 = svm->vmcb->save.cr2;
5762         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5763         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5764         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5765
5766         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5767                 kvm_before_interrupt(&svm->vcpu);
5768
5769         stgi();
5770
5771         /* Any pending NMI will happen here */
5772
5773         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5774                 kvm_after_interrupt(&svm->vcpu);
5775
5776         sync_cr8_to_lapic(vcpu);
5777
5778         svm->next_rip = 0;
5779
5780         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5781
5782         /* if exit due to PF check for async PF */
5783         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5784                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5785
5786         if (npt_enabled) {
5787                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5788                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5789         }
5790
5791         /*
5792          * We need to handle MC intercepts here before the vcpu has a chance to
5793          * change the physical cpu
5794          */
5795         if (unlikely(svm->vmcb->control.exit_code ==
5796                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
5797                 svm_handle_mce(svm);
5798
5799         mark_all_clean(svm->vmcb);
5800 }
5801 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5802
5803 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5804 {
5805         struct vcpu_svm *svm = to_svm(vcpu);
5806
5807         svm->vmcb->save.cr3 = __sme_set(root);
5808         mark_dirty(svm->vmcb, VMCB_CR);
5809 }
5810
5811 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5812 {
5813         struct vcpu_svm *svm = to_svm(vcpu);
5814
5815         svm->vmcb->control.nested_cr3 = __sme_set(root);
5816         mark_dirty(svm->vmcb, VMCB_NPT);
5817
5818         /* Also sync guest cr3 here in case we live migrate */
5819         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5820         mark_dirty(svm->vmcb, VMCB_CR);
5821 }
5822
5823 static int is_disabled(void)
5824 {
5825         u64 vm_cr;
5826
5827         rdmsrl(MSR_VM_CR, vm_cr);
5828         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5829                 return 1;
5830
5831         return 0;
5832 }
5833
5834 static void
5835 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5836 {
5837         /*
5838          * Patch in the VMMCALL instruction:
5839          */
5840         hypercall[0] = 0x0f;
5841         hypercall[1] = 0x01;
5842         hypercall[2] = 0xd9;
5843 }
5844
5845 static void svm_check_processor_compat(void *rtn)
5846 {
5847         *(int *)rtn = 0;
5848 }
5849
5850 static bool svm_cpu_has_accelerated_tpr(void)
5851 {
5852         return false;
5853 }
5854
5855 static bool svm_has_emulated_msr(int index)
5856 {
5857         switch (index) {
5858         case MSR_IA32_MCG_EXT_CTL:
5859                 return false;
5860         default:
5861                 break;
5862         }
5863
5864         return true;
5865 }
5866
5867 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5868 {
5869         return 0;
5870 }
5871
5872 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5873 {
5874         struct vcpu_svm *svm = to_svm(vcpu);
5875
5876         /* Update nrips enabled cache */
5877         svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5878
5879         if (!kvm_vcpu_apicv_active(vcpu))
5880                 return;
5881
5882         guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5883 }
5884
5885 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5886 {
5887         switch (func) {
5888         case 0x1:
5889                 if (avic)
5890                         entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5891                 break;
5892         case 0x80000001:
5893                 if (nested)
5894                         entry->ecx |= (1 << 2); /* Set SVM bit */
5895                 break;
5896         case 0x8000000A:
5897                 entry->eax = 1; /* SVM revision 1 */
5898                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5899                                    ASID emulation to nested SVM */
5900                 entry->ecx = 0; /* Reserved */
5901                 entry->edx = 0; /* Per default do not support any
5902                                    additional features */
5903
5904                 /* Support next_rip if host supports it */
5905                 if (boot_cpu_has(X86_FEATURE_NRIPS))
5906                         entry->edx |= SVM_FEATURE_NRIP;
5907
5908                 /* Support NPT for the guest if enabled */
5909                 if (npt_enabled)
5910                         entry->edx |= SVM_FEATURE_NPT;
5911
5912                 break;
5913         case 0x8000001F:
5914                 /* Support memory encryption cpuid if host supports it */
5915                 if (boot_cpu_has(X86_FEATURE_SEV))
5916                         cpuid(0x8000001f, &entry->eax, &entry->ebx,
5917                                 &entry->ecx, &entry->edx);
5918
5919         }
5920 }
5921
5922 static int svm_get_lpage_level(void)
5923 {
5924         return PT_PDPE_LEVEL;
5925 }
5926
5927 static bool svm_rdtscp_supported(void)
5928 {
5929         return boot_cpu_has(X86_FEATURE_RDTSCP);
5930 }
5931
5932 static bool svm_invpcid_supported(void)
5933 {
5934         return false;
5935 }
5936
5937 static bool svm_mpx_supported(void)
5938 {
5939         return false;
5940 }
5941
5942 static bool svm_xsaves_supported(void)
5943 {
5944         return false;
5945 }
5946
5947 static bool svm_umip_emulated(void)
5948 {
5949         return false;
5950 }
5951
5952 static bool svm_pt_supported(void)
5953 {
5954         return false;
5955 }
5956
5957 static bool svm_has_wbinvd_exit(void)
5958 {
5959         return true;
5960 }
5961
5962 #define PRE_EX(exit)  { .exit_code = (exit), \
5963                         .stage = X86_ICPT_PRE_EXCEPT, }
5964 #define POST_EX(exit) { .exit_code = (exit), \
5965                         .stage = X86_ICPT_POST_EXCEPT, }
5966 #define POST_MEM(exit) { .exit_code = (exit), \
5967                         .stage = X86_ICPT_POST_MEMACCESS, }
5968
5969 static const struct __x86_intercept {
5970         u32 exit_code;
5971         enum x86_intercept_stage stage;
5972 } x86_intercept_map[] = {
5973         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
5974         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
5975         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
5976         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
5977         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
5978         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
5979         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
5980         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
5981         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
5982         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
5983         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
5984         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
5985         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
5986         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
5987         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
5988         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
5989         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
5990         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
5991         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
5992         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
5993         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
5994         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
5995         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
5996         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
5997         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
5998         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
5999         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
6000         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
6001         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
6002         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
6003         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
6004         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
6005         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
6006         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
6007         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
6008         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
6009         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
6010         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
6011         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
6012         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
6013         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
6014         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
6015         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
6016         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
6017         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
6018         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
6019 };
6020
6021 #undef PRE_EX
6022 #undef POST_EX
6023 #undef POST_MEM
6024
6025 static int svm_check_intercept(struct kvm_vcpu *vcpu,
6026                                struct x86_instruction_info *info,
6027                                enum x86_intercept_stage stage)
6028 {
6029         struct vcpu_svm *svm = to_svm(vcpu);
6030         int vmexit, ret = X86EMUL_CONTINUE;
6031         struct __x86_intercept icpt_info;
6032         struct vmcb *vmcb = svm->vmcb;
6033
6034         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
6035                 goto out;
6036
6037         icpt_info = x86_intercept_map[info->intercept];
6038
6039         if (stage != icpt_info.stage)
6040                 goto out;
6041
6042         switch (icpt_info.exit_code) {
6043         case SVM_EXIT_READ_CR0:
6044                 if (info->intercept == x86_intercept_cr_read)
6045                         icpt_info.exit_code += info->modrm_reg;
6046                 break;
6047         case SVM_EXIT_WRITE_CR0: {
6048                 unsigned long cr0, val;
6049                 u64 intercept;
6050
6051                 if (info->intercept == x86_intercept_cr_write)
6052                         icpt_info.exit_code += info->modrm_reg;
6053
6054                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
6055                     info->intercept == x86_intercept_clts)
6056                         break;
6057
6058                 intercept = svm->nested.intercept;
6059
6060                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
6061                         break;
6062
6063                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
6064                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
6065
6066                 if (info->intercept == x86_intercept_lmsw) {
6067                         cr0 &= 0xfUL;
6068                         val &= 0xfUL;
6069                         /* lmsw can't clear PE - catch this here */
6070                         if (cr0 & X86_CR0_PE)
6071                                 val |= X86_CR0_PE;
6072                 }
6073
6074                 if (cr0 ^ val)
6075                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
6076
6077                 break;
6078         }
6079         case SVM_EXIT_READ_DR0:
6080         case SVM_EXIT_WRITE_DR0:
6081                 icpt_info.exit_code += info->modrm_reg;
6082                 break;
6083         case SVM_EXIT_MSR:
6084                 if (info->intercept == x86_intercept_wrmsr)
6085                         vmcb->control.exit_info_1 = 1;
6086                 else
6087                         vmcb->control.exit_info_1 = 0;
6088                 break;
6089         case SVM_EXIT_PAUSE:
6090                 /*
6091                  * We get this for NOP only, but pause
6092                  * is rep not, check this here
6093                  */
6094                 if (info->rep_prefix != REPE_PREFIX)
6095                         goto out;
6096                 break;
6097         case SVM_EXIT_IOIO: {
6098                 u64 exit_info;
6099                 u32 bytes;
6100
6101                 if (info->intercept == x86_intercept_in ||
6102                     info->intercept == x86_intercept_ins) {
6103                         exit_info = ((info->src_val & 0xffff) << 16) |
6104                                 SVM_IOIO_TYPE_MASK;
6105                         bytes = info->dst_bytes;
6106                 } else {
6107                         exit_info = (info->dst_val & 0xffff) << 16;
6108                         bytes = info->src_bytes;
6109                 }
6110
6111                 if (info->intercept == x86_intercept_outs ||
6112                     info->intercept == x86_intercept_ins)
6113                         exit_info |= SVM_IOIO_STR_MASK;
6114
6115                 if (info->rep_prefix)
6116                         exit_info |= SVM_IOIO_REP_MASK;
6117
6118                 bytes = min(bytes, 4u);
6119
6120                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6121
6122                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6123
6124                 vmcb->control.exit_info_1 = exit_info;
6125                 vmcb->control.exit_info_2 = info->next_rip;
6126
6127                 break;
6128         }
6129         default:
6130                 break;
6131         }
6132
6133         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6134         if (static_cpu_has(X86_FEATURE_NRIPS))
6135                 vmcb->control.next_rip  = info->next_rip;
6136         vmcb->control.exit_code = icpt_info.exit_code;
6137         vmexit = nested_svm_exit_handled(svm);
6138
6139         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6140                                            : X86EMUL_CONTINUE;
6141
6142 out:
6143         return ret;
6144 }
6145
6146 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6147 {
6148         local_irq_enable();
6149         /*
6150          * We must have an instruction with interrupts enabled, so
6151          * the timer interrupt isn't delayed by the interrupt shadow.
6152          */
6153         asm("nop");
6154         local_irq_disable();
6155 }
6156
6157 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6158 {
6159         if (pause_filter_thresh)
6160                 shrink_ple_window(vcpu);
6161 }
6162
6163 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6164 {
6165         if (avic_handle_apic_id_update(vcpu) != 0)
6166                 return;
6167         if (avic_handle_dfr_update(vcpu) != 0)
6168                 return;
6169         avic_handle_ldr_update(vcpu);
6170 }
6171
6172 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6173 {
6174         /* [63:9] are reserved. */
6175         vcpu->arch.mcg_cap &= 0x1ff;
6176 }
6177
6178 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6179 {
6180         struct vcpu_svm *svm = to_svm(vcpu);
6181
6182         /* Per APM Vol.2 15.22.2 "Response to SMI" */
6183         if (!gif_set(svm))
6184                 return 0;
6185
6186         if (is_guest_mode(&svm->vcpu) &&
6187             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6188                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6189                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6190                 svm->nested.exit_required = true;
6191                 return 0;
6192         }
6193
6194         return 1;
6195 }
6196
6197 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6198 {
6199         struct vcpu_svm *svm = to_svm(vcpu);
6200         int ret;
6201
6202         if (is_guest_mode(vcpu)) {
6203                 /* FED8h - SVM Guest */
6204                 put_smstate(u64, smstate, 0x7ed8, 1);
6205                 /* FEE0h - SVM Guest VMCB Physical Address */
6206                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6207
6208                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6209                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6210                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6211
6212                 ret = nested_svm_vmexit(svm);
6213                 if (ret)
6214                         return ret;
6215         }
6216         return 0;
6217 }
6218
6219 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
6220 {
6221         struct vcpu_svm *svm = to_svm(vcpu);
6222         struct vmcb *nested_vmcb;
6223         struct page *page;
6224         struct {
6225                 u64 guest;
6226                 u64 vmcb;
6227         } svm_state_save;
6228         int ret;
6229
6230         ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
6231                                   sizeof(svm_state_save));
6232         if (ret)
6233                 return ret;
6234
6235         if (svm_state_save.guest) {
6236                 vcpu->arch.hflags &= ~HF_SMM_MASK;
6237                 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
6238                 if (nested_vmcb)
6239                         enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
6240                 else
6241                         ret = 1;
6242                 vcpu->arch.hflags |= HF_SMM_MASK;
6243         }
6244         return ret;
6245 }
6246
6247 static int enable_smi_window(struct kvm_vcpu *vcpu)
6248 {
6249         struct vcpu_svm *svm = to_svm(vcpu);
6250
6251         if (!gif_set(svm)) {
6252                 if (vgif_enabled(svm))
6253                         set_intercept(svm, INTERCEPT_STGI);
6254                 /* STGI will cause a vm exit */
6255                 return 1;
6256         }
6257         return 0;
6258 }
6259
6260 static int sev_asid_new(void)
6261 {
6262         int pos;
6263
6264         /*
6265          * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6266          */
6267         pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6268         if (pos >= max_sev_asid)
6269                 return -EBUSY;
6270
6271         set_bit(pos, sev_asid_bitmap);
6272         return pos + 1;
6273 }
6274
6275 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6276 {
6277         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6278         int asid, ret;
6279
6280         ret = -EBUSY;
6281         if (unlikely(sev->active))
6282                 return ret;
6283
6284         asid = sev_asid_new();
6285         if (asid < 0)
6286                 return ret;
6287
6288         ret = sev_platform_init(&argp->error);
6289         if (ret)
6290                 goto e_free;
6291
6292         sev->active = true;
6293         sev->asid = asid;
6294         INIT_LIST_HEAD(&sev->regions_list);
6295
6296         return 0;
6297
6298 e_free:
6299         __sev_asid_free(asid);
6300         return ret;
6301 }
6302
6303 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6304 {
6305         struct sev_data_activate *data;
6306         int asid = sev_get_asid(kvm);
6307         int ret;
6308
6309         wbinvd_on_all_cpus();
6310
6311         ret = sev_guest_df_flush(error);
6312         if (ret)
6313                 return ret;
6314
6315         data = kzalloc(sizeof(*data), GFP_KERNEL);
6316         if (!data)
6317                 return -ENOMEM;
6318
6319         /* activate ASID on the given handle */
6320         data->handle = handle;
6321         data->asid   = asid;
6322         ret = sev_guest_activate(data, error);
6323         kfree(data);
6324
6325         return ret;
6326 }
6327
6328 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6329 {
6330         struct fd f;
6331         int ret;
6332
6333         f = fdget(fd);
6334         if (!f.file)
6335                 return -EBADF;
6336
6337         ret = sev_issue_cmd_external_user(f.file, id, data, error);
6338
6339         fdput(f);
6340         return ret;
6341 }
6342
6343 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6344 {
6345         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6346
6347         return __sev_issue_cmd(sev->fd, id, data, error);
6348 }
6349
6350 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6351 {
6352         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6353         struct sev_data_launch_start *start;
6354         struct kvm_sev_launch_start params;
6355         void *dh_blob, *session_blob;
6356         int *error = &argp->error;
6357         int ret;
6358
6359         if (!sev_guest(kvm))
6360                 return -ENOTTY;
6361
6362         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6363                 return -EFAULT;
6364
6365         start = kzalloc(sizeof(*start), GFP_KERNEL);
6366         if (!start)
6367                 return -ENOMEM;
6368
6369         dh_blob = NULL;
6370         if (params.dh_uaddr) {
6371                 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6372                 if (IS_ERR(dh_blob)) {
6373                         ret = PTR_ERR(dh_blob);
6374                         goto e_free;
6375                 }
6376
6377                 start->dh_cert_address = __sme_set(__pa(dh_blob));
6378                 start->dh_cert_len = params.dh_len;
6379         }
6380
6381         session_blob = NULL;
6382         if (params.session_uaddr) {
6383                 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6384                 if (IS_ERR(session_blob)) {
6385                         ret = PTR_ERR(session_blob);
6386                         goto e_free_dh;
6387                 }
6388
6389                 start->session_address = __sme_set(__pa(session_blob));
6390                 start->session_len = params.session_len;
6391         }
6392
6393         start->handle = params.handle;
6394         start->policy = params.policy;
6395
6396         /* create memory encryption context */
6397         ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6398         if (ret)
6399                 goto e_free_session;
6400
6401         /* Bind ASID to this guest */
6402         ret = sev_bind_asid(kvm, start->handle, error);
6403         if (ret)
6404                 goto e_free_session;
6405
6406         /* return handle to userspace */
6407         params.handle = start->handle;
6408         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params))) {
6409                 sev_unbind_asid(kvm, start->handle);
6410                 ret = -EFAULT;
6411                 goto e_free_session;
6412         }
6413
6414         sev->handle = start->handle;
6415         sev->fd = argp->sev_fd;
6416
6417 e_free_session:
6418         kfree(session_blob);
6419 e_free_dh:
6420         kfree(dh_blob);
6421 e_free:
6422         kfree(start);
6423         return ret;
6424 }
6425
6426 static int get_num_contig_pages(int idx, struct page **inpages,
6427                                 unsigned long npages)
6428 {
6429         unsigned long paddr, next_paddr;
6430         int i = idx + 1, pages = 1;
6431
6432         /* find the number of contiguous pages starting from idx */
6433         paddr = __sme_page_pa(inpages[idx]);
6434         while (i < npages) {
6435                 next_paddr = __sme_page_pa(inpages[i++]);
6436                 if ((paddr + PAGE_SIZE) == next_paddr) {
6437                         pages++;
6438                         paddr = next_paddr;
6439                         continue;
6440                 }
6441                 break;
6442         }
6443
6444         return pages;
6445 }
6446
6447 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6448 {
6449         unsigned long vaddr, vaddr_end, next_vaddr, npages, size;
6450         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6451         struct kvm_sev_launch_update_data params;
6452         struct sev_data_launch_update_data *data;
6453         struct page **inpages;
6454         int i, ret, pages;
6455
6456         if (!sev_guest(kvm))
6457                 return -ENOTTY;
6458
6459         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6460                 return -EFAULT;
6461
6462         data = kzalloc(sizeof(*data), GFP_KERNEL);
6463         if (!data)
6464                 return -ENOMEM;
6465
6466         vaddr = params.uaddr;
6467         size = params.len;
6468         vaddr_end = vaddr + size;
6469
6470         /* Lock the user memory. */
6471         inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6472         if (!inpages) {
6473                 ret = -ENOMEM;
6474                 goto e_free;
6475         }
6476
6477         /*
6478          * The LAUNCH_UPDATE command will perform in-place encryption of the
6479          * memory content (i.e it will write the same memory region with C=1).
6480          * It's possible that the cache may contain the data with C=0, i.e.,
6481          * unencrypted so invalidate it first.
6482          */
6483         sev_clflush_pages(inpages, npages);
6484
6485         for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6486                 int offset, len;
6487
6488                 /*
6489                  * If the user buffer is not page-aligned, calculate the offset
6490                  * within the page.
6491                  */
6492                 offset = vaddr & (PAGE_SIZE - 1);
6493
6494                 /* Calculate the number of pages that can be encrypted in one go. */
6495                 pages = get_num_contig_pages(i, inpages, npages);
6496
6497                 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6498
6499                 data->handle = sev->handle;
6500                 data->len = len;
6501                 data->address = __sme_page_pa(inpages[i]) + offset;
6502                 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6503                 if (ret)
6504                         goto e_unpin;
6505
6506                 size -= len;
6507                 next_vaddr = vaddr + len;
6508         }
6509
6510 e_unpin:
6511         /* content of memory is updated, mark pages dirty */
6512         for (i = 0; i < npages; i++) {
6513                 set_page_dirty_lock(inpages[i]);
6514                 mark_page_accessed(inpages[i]);
6515         }
6516         /* unlock the user pages */
6517         sev_unpin_memory(kvm, inpages, npages);
6518 e_free:
6519         kfree(data);
6520         return ret;
6521 }
6522
6523 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6524 {
6525         void __user *measure = (void __user *)(uintptr_t)argp->data;
6526         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6527         struct sev_data_launch_measure *data;
6528         struct kvm_sev_launch_measure params;
6529         void __user *p = NULL;
6530         void *blob = NULL;
6531         int ret;
6532
6533         if (!sev_guest(kvm))
6534                 return -ENOTTY;
6535
6536         if (copy_from_user(&params, measure, sizeof(params)))
6537                 return -EFAULT;
6538
6539         data = kzalloc(sizeof(*data), GFP_KERNEL);
6540         if (!data)
6541                 return -ENOMEM;
6542
6543         /* User wants to query the blob length */
6544         if (!params.len)
6545                 goto cmd;
6546
6547         p = (void __user *)(uintptr_t)params.uaddr;
6548         if (p) {
6549                 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6550                         ret = -EINVAL;
6551                         goto e_free;
6552                 }
6553
6554                 ret = -ENOMEM;
6555                 blob = kmalloc(params.len, GFP_KERNEL);
6556                 if (!blob)
6557                         goto e_free;
6558
6559                 data->address = __psp_pa(blob);
6560                 data->len = params.len;
6561         }
6562
6563 cmd:
6564         data->handle = sev->handle;
6565         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6566
6567         /*
6568          * If we query the session length, FW responded with expected data.
6569          */
6570         if (!params.len)
6571                 goto done;
6572
6573         if (ret)
6574                 goto e_free_blob;
6575
6576         if (blob) {
6577                 if (copy_to_user(p, blob, params.len))
6578                         ret = -EFAULT;
6579         }
6580
6581 done:
6582         params.len = data->len;
6583         if (copy_to_user(measure, &params, sizeof(params)))
6584                 ret = -EFAULT;
6585 e_free_blob:
6586         kfree(blob);
6587 e_free:
6588         kfree(data);
6589         return ret;
6590 }
6591
6592 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6593 {
6594         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6595         struct sev_data_launch_finish *data;
6596         int ret;
6597
6598         if (!sev_guest(kvm))
6599                 return -ENOTTY;
6600
6601         data = kzalloc(sizeof(*data), GFP_KERNEL);
6602         if (!data)
6603                 return -ENOMEM;
6604
6605         data->handle = sev->handle;
6606         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6607
6608         kfree(data);
6609         return ret;
6610 }
6611
6612 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6613 {
6614         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6615         struct kvm_sev_guest_status params;
6616         struct sev_data_guest_status *data;
6617         int ret;
6618
6619         if (!sev_guest(kvm))
6620                 return -ENOTTY;
6621
6622         data = kzalloc(sizeof(*data), GFP_KERNEL);
6623         if (!data)
6624                 return -ENOMEM;
6625
6626         data->handle = sev->handle;
6627         ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6628         if (ret)
6629                 goto e_free;
6630
6631         params.policy = data->policy;
6632         params.state = data->state;
6633         params.handle = data->handle;
6634
6635         if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params)))
6636                 ret = -EFAULT;
6637 e_free:
6638         kfree(data);
6639         return ret;
6640 }
6641
6642 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6643                                unsigned long dst, int size,
6644                                int *error, bool enc)
6645 {
6646         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6647         struct sev_data_dbg *data;
6648         int ret;
6649
6650         data = kzalloc(sizeof(*data), GFP_KERNEL);
6651         if (!data)
6652                 return -ENOMEM;
6653
6654         data->handle = sev->handle;
6655         data->dst_addr = dst;
6656         data->src_addr = src;
6657         data->len = size;
6658
6659         ret = sev_issue_cmd(kvm,
6660                             enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6661                             data, error);
6662         kfree(data);
6663         return ret;
6664 }
6665
6666 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6667                              unsigned long dst_paddr, int sz, int *err)
6668 {
6669         int offset;
6670
6671         /*
6672          * Its safe to read more than we are asked, caller should ensure that
6673          * destination has enough space.
6674          */
6675         src_paddr = round_down(src_paddr, 16);
6676         offset = src_paddr & 15;
6677         sz = round_up(sz + offset, 16);
6678
6679         return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6680 }
6681
6682 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6683                                   unsigned long __user dst_uaddr,
6684                                   unsigned long dst_paddr,
6685                                   int size, int *err)
6686 {
6687         struct page *tpage = NULL;
6688         int ret, offset;
6689
6690         /* if inputs are not 16-byte then use intermediate buffer */
6691         if (!IS_ALIGNED(dst_paddr, 16) ||
6692             !IS_ALIGNED(paddr,     16) ||
6693             !IS_ALIGNED(size,      16)) {
6694                 tpage = (void *)alloc_page(GFP_KERNEL);
6695                 if (!tpage)
6696                         return -ENOMEM;
6697
6698                 dst_paddr = __sme_page_pa(tpage);
6699         }
6700
6701         ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6702         if (ret)
6703                 goto e_free;
6704
6705         if (tpage) {
6706                 offset = paddr & 15;
6707                 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6708                                  page_address(tpage) + offset, size))
6709                         ret = -EFAULT;
6710         }
6711
6712 e_free:
6713         if (tpage)
6714                 __free_page(tpage);
6715
6716         return ret;
6717 }
6718
6719 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6720                                   unsigned long __user vaddr,
6721                                   unsigned long dst_paddr,
6722                                   unsigned long __user dst_vaddr,
6723                                   int size, int *error)
6724 {
6725         struct page *src_tpage = NULL;
6726         struct page *dst_tpage = NULL;
6727         int ret, len = size;
6728
6729         /* If source buffer is not aligned then use an intermediate buffer */
6730         if (!IS_ALIGNED(vaddr, 16)) {
6731                 src_tpage = alloc_page(GFP_KERNEL);
6732                 if (!src_tpage)
6733                         return -ENOMEM;
6734
6735                 if (copy_from_user(page_address(src_tpage),
6736                                 (void __user *)(uintptr_t)vaddr, size)) {
6737                         __free_page(src_tpage);
6738                         return -EFAULT;
6739                 }
6740
6741                 paddr = __sme_page_pa(src_tpage);
6742         }
6743
6744         /*
6745          *  If destination buffer or length is not aligned then do read-modify-write:
6746          *   - decrypt destination in an intermediate buffer
6747          *   - copy the source buffer in an intermediate buffer
6748          *   - use the intermediate buffer as source buffer
6749          */
6750         if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6751                 int dst_offset;
6752
6753                 dst_tpage = alloc_page(GFP_KERNEL);
6754                 if (!dst_tpage) {
6755                         ret = -ENOMEM;
6756                         goto e_free;
6757                 }
6758
6759                 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6760                                         __sme_page_pa(dst_tpage), size, error);
6761                 if (ret)
6762                         goto e_free;
6763
6764                 /*
6765                  *  If source is kernel buffer then use memcpy() otherwise
6766                  *  copy_from_user().
6767                  */
6768                 dst_offset = dst_paddr & 15;
6769
6770                 if (src_tpage)
6771                         memcpy(page_address(dst_tpage) + dst_offset,
6772                                page_address(src_tpage), size);
6773                 else {
6774                         if (copy_from_user(page_address(dst_tpage) + dst_offset,
6775                                            (void __user *)(uintptr_t)vaddr, size)) {
6776                                 ret = -EFAULT;
6777                                 goto e_free;
6778                         }
6779                 }
6780
6781                 paddr = __sme_page_pa(dst_tpage);
6782                 dst_paddr = round_down(dst_paddr, 16);
6783                 len = round_up(size, 16);
6784         }
6785
6786         ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6787
6788 e_free:
6789         if (src_tpage)
6790                 __free_page(src_tpage);
6791         if (dst_tpage)
6792                 __free_page(dst_tpage);
6793         return ret;
6794 }
6795
6796 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6797 {
6798         unsigned long vaddr, vaddr_end, next_vaddr;
6799         unsigned long dst_vaddr;
6800         struct page **src_p, **dst_p;
6801         struct kvm_sev_dbg debug;
6802         unsigned long n;
6803         int ret, size;
6804
6805         if (!sev_guest(kvm))
6806                 return -ENOTTY;
6807
6808         if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6809                 return -EFAULT;
6810
6811         vaddr = debug.src_uaddr;
6812         size = debug.len;
6813         vaddr_end = vaddr + size;
6814         dst_vaddr = debug.dst_uaddr;
6815
6816         for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6817                 int len, s_off, d_off;
6818
6819                 /* lock userspace source and destination page */
6820                 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6821                 if (!src_p)
6822                         return -EFAULT;
6823
6824                 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6825                 if (!dst_p) {
6826                         sev_unpin_memory(kvm, src_p, n);
6827                         return -EFAULT;
6828                 }
6829
6830                 /*
6831                  * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6832                  * memory content (i.e it will write the same memory region with C=1).
6833                  * It's possible that the cache may contain the data with C=0, i.e.,
6834                  * unencrypted so invalidate it first.
6835                  */
6836                 sev_clflush_pages(src_p, 1);
6837                 sev_clflush_pages(dst_p, 1);
6838
6839                 /*
6840                  * Since user buffer may not be page aligned, calculate the
6841                  * offset within the page.
6842                  */
6843                 s_off = vaddr & ~PAGE_MASK;
6844                 d_off = dst_vaddr & ~PAGE_MASK;
6845                 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6846
6847                 if (dec)
6848                         ret = __sev_dbg_decrypt_user(kvm,
6849                                                      __sme_page_pa(src_p[0]) + s_off,
6850                                                      dst_vaddr,
6851                                                      __sme_page_pa(dst_p[0]) + d_off,
6852                                                      len, &argp->error);
6853                 else
6854                         ret = __sev_dbg_encrypt_user(kvm,
6855                                                      __sme_page_pa(src_p[0]) + s_off,
6856                                                      vaddr,
6857                                                      __sme_page_pa(dst_p[0]) + d_off,
6858                                                      dst_vaddr,
6859                                                      len, &argp->error);
6860
6861                 sev_unpin_memory(kvm, src_p, 1);
6862                 sev_unpin_memory(kvm, dst_p, 1);
6863
6864                 if (ret)
6865                         goto err;
6866
6867                 next_vaddr = vaddr + len;
6868                 dst_vaddr = dst_vaddr + len;
6869                 size -= len;
6870         }
6871 err:
6872         return ret;
6873 }
6874
6875 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6876 {
6877         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6878         struct sev_data_launch_secret *data;
6879         struct kvm_sev_launch_secret params;
6880         struct page **pages;
6881         void *blob, *hdr;
6882         unsigned long n;
6883         int ret, offset;
6884
6885         if (!sev_guest(kvm))
6886                 return -ENOTTY;
6887
6888         if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6889                 return -EFAULT;
6890
6891         pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6892         if (!pages)
6893                 return -ENOMEM;
6894
6895         /*
6896          * The secret must be copied into contiguous memory region, lets verify
6897          * that userspace memory pages are contiguous before we issue command.
6898          */
6899         if (get_num_contig_pages(0, pages, n) != n) {
6900                 ret = -EINVAL;
6901                 goto e_unpin_memory;
6902         }
6903
6904         ret = -ENOMEM;
6905         data = kzalloc(sizeof(*data), GFP_KERNEL);
6906         if (!data)
6907                 goto e_unpin_memory;
6908
6909         offset = params.guest_uaddr & (PAGE_SIZE - 1);
6910         data->guest_address = __sme_page_pa(pages[0]) + offset;
6911         data->guest_len = params.guest_len;
6912
6913         blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6914         if (IS_ERR(blob)) {
6915                 ret = PTR_ERR(blob);
6916                 goto e_free;
6917         }
6918
6919         data->trans_address = __psp_pa(blob);
6920         data->trans_len = params.trans_len;
6921
6922         hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6923         if (IS_ERR(hdr)) {
6924                 ret = PTR_ERR(hdr);
6925                 goto e_free_blob;
6926         }
6927         data->hdr_address = __psp_pa(hdr);
6928         data->hdr_len = params.hdr_len;
6929
6930         data->handle = sev->handle;
6931         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6932
6933         kfree(hdr);
6934
6935 e_free_blob:
6936         kfree(blob);
6937 e_free:
6938         kfree(data);
6939 e_unpin_memory:
6940         sev_unpin_memory(kvm, pages, n);
6941         return ret;
6942 }
6943
6944 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6945 {
6946         struct kvm_sev_cmd sev_cmd;
6947         int r;
6948
6949         if (!svm_sev_enabled())
6950                 return -ENOTTY;
6951
6952         if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6953                 return -EFAULT;
6954
6955         mutex_lock(&kvm->lock);
6956
6957         switch (sev_cmd.id) {
6958         case KVM_SEV_INIT:
6959                 r = sev_guest_init(kvm, &sev_cmd);
6960                 break;
6961         case KVM_SEV_LAUNCH_START:
6962                 r = sev_launch_start(kvm, &sev_cmd);
6963                 break;
6964         case KVM_SEV_LAUNCH_UPDATE_DATA:
6965                 r = sev_launch_update_data(kvm, &sev_cmd);
6966                 break;
6967         case KVM_SEV_LAUNCH_MEASURE:
6968                 r = sev_launch_measure(kvm, &sev_cmd);
6969                 break;
6970         case KVM_SEV_LAUNCH_FINISH:
6971                 r = sev_launch_finish(kvm, &sev_cmd);
6972                 break;
6973         case KVM_SEV_GUEST_STATUS:
6974                 r = sev_guest_status(kvm, &sev_cmd);
6975                 break;
6976         case KVM_SEV_DBG_DECRYPT:
6977                 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6978                 break;
6979         case KVM_SEV_DBG_ENCRYPT:
6980                 r = sev_dbg_crypt(kvm, &sev_cmd, false);
6981                 break;
6982         case KVM_SEV_LAUNCH_SECRET:
6983                 r = sev_launch_secret(kvm, &sev_cmd);
6984                 break;
6985         default:
6986                 r = -EINVAL;
6987                 goto out;
6988         }
6989
6990         if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
6991                 r = -EFAULT;
6992
6993 out:
6994         mutex_unlock(&kvm->lock);
6995         return r;
6996 }
6997
6998 static int svm_register_enc_region(struct kvm *kvm,
6999                                    struct kvm_enc_region *range)
7000 {
7001         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7002         struct enc_region *region;
7003         int ret = 0;
7004
7005         if (!sev_guest(kvm))
7006                 return -ENOTTY;
7007
7008         if (range->addr > ULONG_MAX || range->size > ULONG_MAX)
7009                 return -EINVAL;
7010
7011         region = kzalloc(sizeof(*region), GFP_KERNEL);
7012         if (!region)
7013                 return -ENOMEM;
7014
7015         region->pages = sev_pin_memory(kvm, range->addr, range->size, &region->npages, 1);
7016         if (!region->pages) {
7017                 ret = -ENOMEM;
7018                 goto e_free;
7019         }
7020
7021         /*
7022          * The guest may change the memory encryption attribute from C=0 -> C=1
7023          * or vice versa for this memory range. Lets make sure caches are
7024          * flushed to ensure that guest data gets written into memory with
7025          * correct C-bit.
7026          */
7027         sev_clflush_pages(region->pages, region->npages);
7028
7029         region->uaddr = range->addr;
7030         region->size = range->size;
7031
7032         mutex_lock(&kvm->lock);
7033         list_add_tail(&region->list, &sev->regions_list);
7034         mutex_unlock(&kvm->lock);
7035
7036         return ret;
7037
7038 e_free:
7039         kfree(region);
7040         return ret;
7041 }
7042
7043 static struct enc_region *
7044 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
7045 {
7046         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
7047         struct list_head *head = &sev->regions_list;
7048         struct enc_region *i;
7049
7050         list_for_each_entry(i, head, list) {
7051                 if (i->uaddr == range->addr &&
7052                     i->size == range->size)
7053                         return i;
7054         }
7055
7056         return NULL;
7057 }
7058
7059
7060 static int svm_unregister_enc_region(struct kvm *kvm,
7061                                      struct kvm_enc_region *range)
7062 {
7063         struct enc_region *region;
7064         int ret;
7065
7066         mutex_lock(&kvm->lock);
7067
7068         if (!sev_guest(kvm)) {
7069                 ret = -ENOTTY;
7070                 goto failed;
7071         }
7072
7073         region = find_enc_region(kvm, range);
7074         if (!region) {
7075                 ret = -EINVAL;
7076                 goto failed;
7077         }
7078
7079         __unregister_enc_region_locked(kvm, region);
7080
7081         mutex_unlock(&kvm->lock);
7082         return 0;
7083
7084 failed:
7085         mutex_unlock(&kvm->lock);
7086         return ret;
7087 }
7088
7089 static uint16_t nested_get_evmcs_version(struct kvm_vcpu *vcpu)
7090 {
7091         /* Not supported */
7092         return 0;
7093 }
7094
7095 static int nested_enable_evmcs(struct kvm_vcpu *vcpu,
7096                                    uint16_t *vmcs_version)
7097 {
7098         /* Intel-only feature */
7099         return -ENODEV;
7100 }
7101
7102 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7103         .cpu_has_kvm_support = has_svm,
7104         .disabled_by_bios = is_disabled,
7105         .hardware_setup = svm_hardware_setup,
7106         .hardware_unsetup = svm_hardware_unsetup,
7107         .check_processor_compatibility = svm_check_processor_compat,
7108         .hardware_enable = svm_hardware_enable,
7109         .hardware_disable = svm_hardware_disable,
7110         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7111         .has_emulated_msr = svm_has_emulated_msr,
7112
7113         .vcpu_create = svm_create_vcpu,
7114         .vcpu_free = svm_free_vcpu,
7115         .vcpu_reset = svm_vcpu_reset,
7116
7117         .vm_alloc = svm_vm_alloc,
7118         .vm_free = svm_vm_free,
7119         .vm_init = avic_vm_init,
7120         .vm_destroy = svm_vm_destroy,
7121
7122         .prepare_guest_switch = svm_prepare_guest_switch,
7123         .vcpu_load = svm_vcpu_load,
7124         .vcpu_put = svm_vcpu_put,
7125         .vcpu_blocking = svm_vcpu_blocking,
7126         .vcpu_unblocking = svm_vcpu_unblocking,
7127
7128         .update_bp_intercept = update_bp_intercept,
7129         .get_msr_feature = svm_get_msr_feature,
7130         .get_msr = svm_get_msr,
7131         .set_msr = svm_set_msr,
7132         .get_segment_base = svm_get_segment_base,
7133         .get_segment = svm_get_segment,
7134         .set_segment = svm_set_segment,
7135         .get_cpl = svm_get_cpl,
7136         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7137         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7138         .decache_cr3 = svm_decache_cr3,
7139         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7140         .set_cr0 = svm_set_cr0,
7141         .set_cr3 = svm_set_cr3,
7142         .set_cr4 = svm_set_cr4,
7143         .set_efer = svm_set_efer,
7144         .get_idt = svm_get_idt,
7145         .set_idt = svm_set_idt,
7146         .get_gdt = svm_get_gdt,
7147         .set_gdt = svm_set_gdt,
7148         .get_dr6 = svm_get_dr6,
7149         .set_dr6 = svm_set_dr6,
7150         .set_dr7 = svm_set_dr7,
7151         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7152         .cache_reg = svm_cache_reg,
7153         .get_rflags = svm_get_rflags,
7154         .set_rflags = svm_set_rflags,
7155
7156         .tlb_flush = svm_flush_tlb,
7157         .tlb_flush_gva = svm_flush_tlb_gva,
7158
7159         .run = svm_vcpu_run,
7160         .handle_exit = handle_exit,
7161         .skip_emulated_instruction = skip_emulated_instruction,
7162         .set_interrupt_shadow = svm_set_interrupt_shadow,
7163         .get_interrupt_shadow = svm_get_interrupt_shadow,
7164         .patch_hypercall = svm_patch_hypercall,
7165         .set_irq = svm_set_irq,
7166         .set_nmi = svm_inject_nmi,
7167         .queue_exception = svm_queue_exception,
7168         .cancel_injection = svm_cancel_injection,
7169         .interrupt_allowed = svm_interrupt_allowed,
7170         .nmi_allowed = svm_nmi_allowed,
7171         .get_nmi_mask = svm_get_nmi_mask,
7172         .set_nmi_mask = svm_set_nmi_mask,
7173         .enable_nmi_window = enable_nmi_window,
7174         .enable_irq_window = enable_irq_window,
7175         .update_cr8_intercept = update_cr8_intercept,
7176         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
7177         .get_enable_apicv = svm_get_enable_apicv,
7178         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7179         .load_eoi_exitmap = svm_load_eoi_exitmap,
7180         .hwapic_irr_update = svm_hwapic_irr_update,
7181         .hwapic_isr_update = svm_hwapic_isr_update,
7182         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7183         .apicv_post_state_restore = avic_post_state_restore,
7184
7185         .set_tss_addr = svm_set_tss_addr,
7186         .set_identity_map_addr = svm_set_identity_map_addr,
7187         .get_tdp_level = get_npt_level,
7188         .get_mt_mask = svm_get_mt_mask,
7189
7190         .get_exit_info = svm_get_exit_info,
7191
7192         .get_lpage_level = svm_get_lpage_level,
7193
7194         .cpuid_update = svm_cpuid_update,
7195
7196         .rdtscp_supported = svm_rdtscp_supported,
7197         .invpcid_supported = svm_invpcid_supported,
7198         .mpx_supported = svm_mpx_supported,
7199         .xsaves_supported = svm_xsaves_supported,
7200         .umip_emulated = svm_umip_emulated,
7201         .pt_supported = svm_pt_supported,
7202
7203         .set_supported_cpuid = svm_set_supported_cpuid,
7204
7205         .has_wbinvd_exit = svm_has_wbinvd_exit,
7206
7207         .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7208         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
7209
7210         .set_tdp_cr3 = set_tdp_cr3,
7211
7212         .check_intercept = svm_check_intercept,
7213         .handle_external_intr = svm_handle_external_intr,
7214
7215         .request_immediate_exit = __kvm_request_immediate_exit,
7216
7217         .sched_in = svm_sched_in,
7218
7219         .pmu_ops = &amd_pmu_ops,
7220         .deliver_posted_interrupt = svm_deliver_avic_intr,
7221         .update_pi_irte = svm_update_pi_irte,
7222         .setup_mce = svm_setup_mce,
7223
7224         .smi_allowed = svm_smi_allowed,
7225         .pre_enter_smm = svm_pre_enter_smm,
7226         .pre_leave_smm = svm_pre_leave_smm,
7227         .enable_smi_window = enable_smi_window,
7228
7229         .mem_enc_op = svm_mem_enc_op,
7230         .mem_enc_reg_region = svm_register_enc_region,
7231         .mem_enc_unreg_region = svm_unregister_enc_region,
7232
7233         .nested_enable_evmcs = nested_enable_evmcs,
7234         .nested_get_evmcs_version = nested_get_evmcs_version,
7235 };
7236
7237 static int __init svm_init(void)
7238 {
7239         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7240                         __alignof__(struct vcpu_svm), THIS_MODULE);
7241 }
7242
7243 static void __exit svm_exit(void)
7244 {
7245         kvm_exit();
7246 }
7247
7248 module_init(svm_init)
7249 module_exit(svm_exit)