Merge branches 'arm/rockchip', 'arm/exynos', 'arm/smmu', 'x86/vt-d', 'x86/amd', ...
[sfrench/cifs-2.6.git] / arch / x86 / kvm / svm.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * AMD SVM support
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8  *
9  * Authors:
10  *   Yaniv Kamay  <yaniv@qumranet.com>
11  *   Avi Kivity   <avi@qumranet.com>
12  *
13  * This work is licensed under the terms of the GNU GPL, version 2.  See
14  * the COPYING file in the top-level directory.
15  *
16  */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23 #include "cpuid.h"
24
25 #include <linux/module.h>
26 #include <linux/mod_devicetable.h>
27 #include <linux/kernel.h>
28 #include <linux/vmalloc.h>
29 #include <linux/highmem.h>
30 #include <linux/sched.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33
34 #include <asm/perf_event.h>
35 #include <asm/tlbflush.h>
36 #include <asm/desc.h>
37 #include <asm/debugreg.h>
38 #include <asm/kvm_para.h>
39
40 #include <asm/virtext.h>
41 #include "trace.h"
42
43 #define __ex(x) __kvm_handle_fault_on_reboot(x)
44
45 MODULE_AUTHOR("Qumranet");
46 MODULE_LICENSE("GPL");
47
48 static const struct x86_cpu_id svm_cpu_id[] = {
49         X86_FEATURE_MATCH(X86_FEATURE_SVM),
50         {}
51 };
52 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
53
54 #define IOPM_ALLOC_ORDER 2
55 #define MSRPM_ALLOC_ORDER 1
56
57 #define SEG_TYPE_LDT 2
58 #define SEG_TYPE_BUSY_TSS16 3
59
60 #define SVM_FEATURE_NPT            (1 <<  0)
61 #define SVM_FEATURE_LBRV           (1 <<  1)
62 #define SVM_FEATURE_SVML           (1 <<  2)
63 #define SVM_FEATURE_NRIP           (1 <<  3)
64 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
65 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
66 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
67 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
68 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
69
70 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
71 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
72 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
73
74 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
75
76 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
77 #define TSC_RATIO_MIN           0x0000000000000001ULL
78 #define TSC_RATIO_MAX           0x000000ffffffffffULL
79
80 static bool erratum_383_found __read_mostly;
81
82 static const u32 host_save_user_msrs[] = {
83 #ifdef CONFIG_X86_64
84         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
85         MSR_FS_BASE,
86 #endif
87         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
88 };
89
90 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
91
92 struct kvm_vcpu;
93
94 struct nested_state {
95         struct vmcb *hsave;
96         u64 hsave_msr;
97         u64 vm_cr_msr;
98         u64 vmcb;
99
100         /* These are the merged vectors */
101         u32 *msrpm;
102
103         /* gpa pointers to the real vectors */
104         u64 vmcb_msrpm;
105         u64 vmcb_iopm;
106
107         /* A VMEXIT is required but not yet emulated */
108         bool exit_required;
109
110         /* cache for intercepts of the guest */
111         u32 intercept_cr;
112         u32 intercept_dr;
113         u32 intercept_exceptions;
114         u64 intercept;
115
116         /* Nested Paging related state */
117         u64 nested_cr3;
118 };
119
120 #define MSRPM_OFFSETS   16
121 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
122
123 /*
124  * Set osvw_len to higher value when updated Revision Guides
125  * are published and we know what the new status bits are
126  */
127 static uint64_t osvw_len = 4, osvw_status;
128
129 struct vcpu_svm {
130         struct kvm_vcpu vcpu;
131         struct vmcb *vmcb;
132         unsigned long vmcb_pa;
133         struct svm_cpu_data *svm_data;
134         uint64_t asid_generation;
135         uint64_t sysenter_esp;
136         uint64_t sysenter_eip;
137
138         u64 next_rip;
139
140         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
141         struct {
142                 u16 fs;
143                 u16 gs;
144                 u16 ldt;
145                 u64 gs_base;
146         } host;
147
148         u32 *msrpm;
149
150         ulong nmi_iret_rip;
151
152         struct nested_state nested;
153
154         bool nmi_singlestep;
155
156         unsigned int3_injected;
157         unsigned long int3_rip;
158         u32 apf_reason;
159
160         u64  tsc_ratio;
161 };
162
163 static DEFINE_PER_CPU(u64, current_tsc_ratio);
164 #define TSC_RATIO_DEFAULT       0x0100000000ULL
165
166 #define MSR_INVALID                     0xffffffffU
167
168 static const struct svm_direct_access_msrs {
169         u32 index;   /* Index of the MSR */
170         bool always; /* True if intercept is always on */
171 } direct_access_msrs[] = {
172         { .index = MSR_STAR,                            .always = true  },
173         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
174 #ifdef CONFIG_X86_64
175         { .index = MSR_GS_BASE,                         .always = true  },
176         { .index = MSR_FS_BASE,                         .always = true  },
177         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
178         { .index = MSR_LSTAR,                           .always = true  },
179         { .index = MSR_CSTAR,                           .always = true  },
180         { .index = MSR_SYSCALL_MASK,                    .always = true  },
181 #endif
182         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
183         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
184         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
185         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
186         { .index = MSR_INVALID,                         .always = false },
187 };
188
189 /* enable NPT for AMD64 and X86 with PAE */
190 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
191 static bool npt_enabled = true;
192 #else
193 static bool npt_enabled;
194 #endif
195
196 /* allow nested paging (virtualized MMU) for all guests */
197 static int npt = true;
198 module_param(npt, int, S_IRUGO);
199
200 /* allow nested virtualization in KVM/SVM */
201 static int nested = true;
202 module_param(nested, int, S_IRUGO);
203
204 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
205 static void svm_complete_interrupts(struct vcpu_svm *svm);
206
207 static int nested_svm_exit_handled(struct vcpu_svm *svm);
208 static int nested_svm_intercept(struct vcpu_svm *svm);
209 static int nested_svm_vmexit(struct vcpu_svm *svm);
210 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
211                                       bool has_error_code, u32 error_code);
212 static u64 __scale_tsc(u64 ratio, u64 tsc);
213
214 enum {
215         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
216                             pause filter count */
217         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
218         VMCB_ASID,       /* ASID */
219         VMCB_INTR,       /* int_ctl, int_vector */
220         VMCB_NPT,        /* npt_en, nCR3, gPAT */
221         VMCB_CR,         /* CR0, CR3, CR4, EFER */
222         VMCB_DR,         /* DR6, DR7 */
223         VMCB_DT,         /* GDT, IDT */
224         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
225         VMCB_CR2,        /* CR2 only */
226         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
227         VMCB_DIRTY_MAX,
228 };
229
230 /* TPR and CR2 are always written before VMRUN */
231 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
232
233 static inline void mark_all_dirty(struct vmcb *vmcb)
234 {
235         vmcb->control.clean = 0;
236 }
237
238 static inline void mark_all_clean(struct vmcb *vmcb)
239 {
240         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
241                                & ~VMCB_ALWAYS_DIRTY_MASK;
242 }
243
244 static inline void mark_dirty(struct vmcb *vmcb, int bit)
245 {
246         vmcb->control.clean &= ~(1 << bit);
247 }
248
249 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
250 {
251         return container_of(vcpu, struct vcpu_svm, vcpu);
252 }
253
254 static void recalc_intercepts(struct vcpu_svm *svm)
255 {
256         struct vmcb_control_area *c, *h;
257         struct nested_state *g;
258
259         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
260
261         if (!is_guest_mode(&svm->vcpu))
262                 return;
263
264         c = &svm->vmcb->control;
265         h = &svm->nested.hsave->control;
266         g = &svm->nested;
267
268         c->intercept_cr = h->intercept_cr | g->intercept_cr;
269         c->intercept_dr = h->intercept_dr | g->intercept_dr;
270         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
271         c->intercept = h->intercept | g->intercept;
272 }
273
274 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
275 {
276         if (is_guest_mode(&svm->vcpu))
277                 return svm->nested.hsave;
278         else
279                 return svm->vmcb;
280 }
281
282 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
283 {
284         struct vmcb *vmcb = get_host_vmcb(svm);
285
286         vmcb->control.intercept_cr |= (1U << bit);
287
288         recalc_intercepts(svm);
289 }
290
291 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
292 {
293         struct vmcb *vmcb = get_host_vmcb(svm);
294
295         vmcb->control.intercept_cr &= ~(1U << bit);
296
297         recalc_intercepts(svm);
298 }
299
300 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
301 {
302         struct vmcb *vmcb = get_host_vmcb(svm);
303
304         return vmcb->control.intercept_cr & (1U << bit);
305 }
306
307 static inline void set_dr_intercepts(struct vcpu_svm *svm)
308 {
309         struct vmcb *vmcb = get_host_vmcb(svm);
310
311         vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
312                 | (1 << INTERCEPT_DR1_READ)
313                 | (1 << INTERCEPT_DR2_READ)
314                 | (1 << INTERCEPT_DR3_READ)
315                 | (1 << INTERCEPT_DR4_READ)
316                 | (1 << INTERCEPT_DR5_READ)
317                 | (1 << INTERCEPT_DR6_READ)
318                 | (1 << INTERCEPT_DR7_READ)
319                 | (1 << INTERCEPT_DR0_WRITE)
320                 | (1 << INTERCEPT_DR1_WRITE)
321                 | (1 << INTERCEPT_DR2_WRITE)
322                 | (1 << INTERCEPT_DR3_WRITE)
323                 | (1 << INTERCEPT_DR4_WRITE)
324                 | (1 << INTERCEPT_DR5_WRITE)
325                 | (1 << INTERCEPT_DR6_WRITE)
326                 | (1 << INTERCEPT_DR7_WRITE);
327
328         recalc_intercepts(svm);
329 }
330
331 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
332 {
333         struct vmcb *vmcb = get_host_vmcb(svm);
334
335         vmcb->control.intercept_dr = 0;
336
337         recalc_intercepts(svm);
338 }
339
340 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
341 {
342         struct vmcb *vmcb = get_host_vmcb(svm);
343
344         vmcb->control.intercept_exceptions |= (1U << bit);
345
346         recalc_intercepts(svm);
347 }
348
349 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
350 {
351         struct vmcb *vmcb = get_host_vmcb(svm);
352
353         vmcb->control.intercept_exceptions &= ~(1U << bit);
354
355         recalc_intercepts(svm);
356 }
357
358 static inline void set_intercept(struct vcpu_svm *svm, int bit)
359 {
360         struct vmcb *vmcb = get_host_vmcb(svm);
361
362         vmcb->control.intercept |= (1ULL << bit);
363
364         recalc_intercepts(svm);
365 }
366
367 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
368 {
369         struct vmcb *vmcb = get_host_vmcb(svm);
370
371         vmcb->control.intercept &= ~(1ULL << bit);
372
373         recalc_intercepts(svm);
374 }
375
376 static inline void enable_gif(struct vcpu_svm *svm)
377 {
378         svm->vcpu.arch.hflags |= HF_GIF_MASK;
379 }
380
381 static inline void disable_gif(struct vcpu_svm *svm)
382 {
383         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
384 }
385
386 static inline bool gif_set(struct vcpu_svm *svm)
387 {
388         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
389 }
390
391 static unsigned long iopm_base;
392
393 struct kvm_ldttss_desc {
394         u16 limit0;
395         u16 base0;
396         unsigned base1:8, type:5, dpl:2, p:1;
397         unsigned limit1:4, zero0:3, g:1, base2:8;
398         u32 base3;
399         u32 zero1;
400 } __attribute__((packed));
401
402 struct svm_cpu_data {
403         int cpu;
404
405         u64 asid_generation;
406         u32 max_asid;
407         u32 next_asid;
408         struct kvm_ldttss_desc *tss_desc;
409
410         struct page *save_area;
411 };
412
413 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
414
415 struct svm_init_data {
416         int cpu;
417         int r;
418 };
419
420 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
421
422 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
423 #define MSRS_RANGE_SIZE 2048
424 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
425
426 static u32 svm_msrpm_offset(u32 msr)
427 {
428         u32 offset;
429         int i;
430
431         for (i = 0; i < NUM_MSR_MAPS; i++) {
432                 if (msr < msrpm_ranges[i] ||
433                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
434                         continue;
435
436                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
437                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
438
439                 /* Now we have the u8 offset - but need the u32 offset */
440                 return offset / 4;
441         }
442
443         /* MSR not in any range */
444         return MSR_INVALID;
445 }
446
447 #define MAX_INST_SIZE 15
448
449 static inline void clgi(void)
450 {
451         asm volatile (__ex(SVM_CLGI));
452 }
453
454 static inline void stgi(void)
455 {
456         asm volatile (__ex(SVM_STGI));
457 }
458
459 static inline void invlpga(unsigned long addr, u32 asid)
460 {
461         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
462 }
463
464 static int get_npt_level(void)
465 {
466 #ifdef CONFIG_X86_64
467         return PT64_ROOT_LEVEL;
468 #else
469         return PT32E_ROOT_LEVEL;
470 #endif
471 }
472
473 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
474 {
475         vcpu->arch.efer = efer;
476         if (!npt_enabled && !(efer & EFER_LMA))
477                 efer &= ~EFER_LME;
478
479         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
480         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
481 }
482
483 static int is_external_interrupt(u32 info)
484 {
485         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
486         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
487 }
488
489 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
490 {
491         struct vcpu_svm *svm = to_svm(vcpu);
492         u32 ret = 0;
493
494         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
495                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
496         return ret;
497 }
498
499 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
500 {
501         struct vcpu_svm *svm = to_svm(vcpu);
502
503         if (mask == 0)
504                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
505         else
506                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
507
508 }
509
510 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
511 {
512         struct vcpu_svm *svm = to_svm(vcpu);
513
514         if (svm->vmcb->control.next_rip != 0)
515                 svm->next_rip = svm->vmcb->control.next_rip;
516
517         if (!svm->next_rip) {
518                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
519                                 EMULATE_DONE)
520                         printk(KERN_DEBUG "%s: NOP\n", __func__);
521                 return;
522         }
523         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
524                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
525                        __func__, kvm_rip_read(vcpu), svm->next_rip);
526
527         kvm_rip_write(vcpu, svm->next_rip);
528         svm_set_interrupt_shadow(vcpu, 0);
529 }
530
531 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
532                                 bool has_error_code, u32 error_code,
533                                 bool reinject)
534 {
535         struct vcpu_svm *svm = to_svm(vcpu);
536
537         /*
538          * If we are within a nested VM we'd better #VMEXIT and let the guest
539          * handle the exception
540          */
541         if (!reinject &&
542             nested_svm_check_exception(svm, nr, has_error_code, error_code))
543                 return;
544
545         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
546                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
547
548                 /*
549                  * For guest debugging where we have to reinject #BP if some
550                  * INT3 is guest-owned:
551                  * Emulate nRIP by moving RIP forward. Will fail if injection
552                  * raises a fault that is not intercepted. Still better than
553                  * failing in all cases.
554                  */
555                 skip_emulated_instruction(&svm->vcpu);
556                 rip = kvm_rip_read(&svm->vcpu);
557                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
558                 svm->int3_injected = rip - old_rip;
559         }
560
561         svm->vmcb->control.event_inj = nr
562                 | SVM_EVTINJ_VALID
563                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
564                 | SVM_EVTINJ_TYPE_EXEPT;
565         svm->vmcb->control.event_inj_err = error_code;
566 }
567
568 static void svm_init_erratum_383(void)
569 {
570         u32 low, high;
571         int err;
572         u64 val;
573
574         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
575                 return;
576
577         /* Use _safe variants to not break nested virtualization */
578         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
579         if (err)
580                 return;
581
582         val |= (1ULL << 47);
583
584         low  = lower_32_bits(val);
585         high = upper_32_bits(val);
586
587         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
588
589         erratum_383_found = true;
590 }
591
592 static void svm_init_osvw(struct kvm_vcpu *vcpu)
593 {
594         /*
595          * Guests should see errata 400 and 415 as fixed (assuming that
596          * HLT and IO instructions are intercepted).
597          */
598         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
599         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
600
601         /*
602          * By increasing VCPU's osvw.length to 3 we are telling the guest that
603          * all osvw.status bits inside that length, including bit 0 (which is
604          * reserved for erratum 298), are valid. However, if host processor's
605          * osvw_len is 0 then osvw_status[0] carries no information. We need to
606          * be conservative here and therefore we tell the guest that erratum 298
607          * is present (because we really don't know).
608          */
609         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
610                 vcpu->arch.osvw.status |= 1;
611 }
612
613 static int has_svm(void)
614 {
615         const char *msg;
616
617         if (!cpu_has_svm(&msg)) {
618                 printk(KERN_INFO "has_svm: %s\n", msg);
619                 return 0;
620         }
621
622         return 1;
623 }
624
625 static void svm_hardware_disable(void)
626 {
627         /* Make sure we clean up behind us */
628         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
629                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
630
631         cpu_svm_disable();
632
633         amd_pmu_disable_virt();
634 }
635
636 static int svm_hardware_enable(void)
637 {
638
639         struct svm_cpu_data *sd;
640         uint64_t efer;
641         struct desc_ptr gdt_descr;
642         struct desc_struct *gdt;
643         int me = raw_smp_processor_id();
644
645         rdmsrl(MSR_EFER, efer);
646         if (efer & EFER_SVME)
647                 return -EBUSY;
648
649         if (!has_svm()) {
650                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
651                 return -EINVAL;
652         }
653         sd = per_cpu(svm_data, me);
654         if (!sd) {
655                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
656                 return -EINVAL;
657         }
658
659         sd->asid_generation = 1;
660         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
661         sd->next_asid = sd->max_asid + 1;
662
663         native_store_gdt(&gdt_descr);
664         gdt = (struct desc_struct *)gdt_descr.address;
665         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
666
667         wrmsrl(MSR_EFER, efer | EFER_SVME);
668
669         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
670
671         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
672                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
673                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
674         }
675
676
677         /*
678          * Get OSVW bits.
679          *
680          * Note that it is possible to have a system with mixed processor
681          * revisions and therefore different OSVW bits. If bits are not the same
682          * on different processors then choose the worst case (i.e. if erratum
683          * is present on one processor and not on another then assume that the
684          * erratum is present everywhere).
685          */
686         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
687                 uint64_t len, status = 0;
688                 int err;
689
690                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
691                 if (!err)
692                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
693                                                       &err);
694
695                 if (err)
696                         osvw_status = osvw_len = 0;
697                 else {
698                         if (len < osvw_len)
699                                 osvw_len = len;
700                         osvw_status |= status;
701                         osvw_status &= (1ULL << osvw_len) - 1;
702                 }
703         } else
704                 osvw_status = osvw_len = 0;
705
706         svm_init_erratum_383();
707
708         amd_pmu_enable_virt();
709
710         return 0;
711 }
712
713 static void svm_cpu_uninit(int cpu)
714 {
715         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
716
717         if (!sd)
718                 return;
719
720         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
721         __free_page(sd->save_area);
722         kfree(sd);
723 }
724
725 static int svm_cpu_init(int cpu)
726 {
727         struct svm_cpu_data *sd;
728         int r;
729
730         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
731         if (!sd)
732                 return -ENOMEM;
733         sd->cpu = cpu;
734         sd->save_area = alloc_page(GFP_KERNEL);
735         r = -ENOMEM;
736         if (!sd->save_area)
737                 goto err_1;
738
739         per_cpu(svm_data, cpu) = sd;
740
741         return 0;
742
743 err_1:
744         kfree(sd);
745         return r;
746
747 }
748
749 static bool valid_msr_intercept(u32 index)
750 {
751         int i;
752
753         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
754                 if (direct_access_msrs[i].index == index)
755                         return true;
756
757         return false;
758 }
759
760 static void set_msr_interception(u32 *msrpm, unsigned msr,
761                                  int read, int write)
762 {
763         u8 bit_read, bit_write;
764         unsigned long tmp;
765         u32 offset;
766
767         /*
768          * If this warning triggers extend the direct_access_msrs list at the
769          * beginning of the file
770          */
771         WARN_ON(!valid_msr_intercept(msr));
772
773         offset    = svm_msrpm_offset(msr);
774         bit_read  = 2 * (msr & 0x0f);
775         bit_write = 2 * (msr & 0x0f) + 1;
776         tmp       = msrpm[offset];
777
778         BUG_ON(offset == MSR_INVALID);
779
780         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
781         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
782
783         msrpm[offset] = tmp;
784 }
785
786 static void svm_vcpu_init_msrpm(u32 *msrpm)
787 {
788         int i;
789
790         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
791
792         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
793                 if (!direct_access_msrs[i].always)
794                         continue;
795
796                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
797         }
798 }
799
800 static void add_msr_offset(u32 offset)
801 {
802         int i;
803
804         for (i = 0; i < MSRPM_OFFSETS; ++i) {
805
806                 /* Offset already in list? */
807                 if (msrpm_offsets[i] == offset)
808                         return;
809
810                 /* Slot used by another offset? */
811                 if (msrpm_offsets[i] != MSR_INVALID)
812                         continue;
813
814                 /* Add offset to list */
815                 msrpm_offsets[i] = offset;
816
817                 return;
818         }
819
820         /*
821          * If this BUG triggers the msrpm_offsets table has an overflow. Just
822          * increase MSRPM_OFFSETS in this case.
823          */
824         BUG();
825 }
826
827 static void init_msrpm_offsets(void)
828 {
829         int i;
830
831         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
832
833         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
834                 u32 offset;
835
836                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
837                 BUG_ON(offset == MSR_INVALID);
838
839                 add_msr_offset(offset);
840         }
841 }
842
843 static void svm_enable_lbrv(struct vcpu_svm *svm)
844 {
845         u32 *msrpm = svm->msrpm;
846
847         svm->vmcb->control.lbr_ctl = 1;
848         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
849         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
850         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
851         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
852 }
853
854 static void svm_disable_lbrv(struct vcpu_svm *svm)
855 {
856         u32 *msrpm = svm->msrpm;
857
858         svm->vmcb->control.lbr_ctl = 0;
859         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
860         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
861         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
862         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
863 }
864
865 static __init int svm_hardware_setup(void)
866 {
867         int cpu;
868         struct page *iopm_pages;
869         void *iopm_va;
870         int r;
871
872         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
873
874         if (!iopm_pages)
875                 return -ENOMEM;
876
877         iopm_va = page_address(iopm_pages);
878         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
879         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
880
881         init_msrpm_offsets();
882
883         if (boot_cpu_has(X86_FEATURE_NX))
884                 kvm_enable_efer_bits(EFER_NX);
885
886         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
887                 kvm_enable_efer_bits(EFER_FFXSR);
888
889         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
890                 u64 max;
891
892                 kvm_has_tsc_control = true;
893
894                 /*
895                  * Make sure the user can only configure tsc_khz values that
896                  * fit into a signed integer.
897                  * A min value is not calculated needed because it will always
898                  * be 1 on all machines and a value of 0 is used to disable
899                  * tsc-scaling for the vcpu.
900                  */
901                 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
902
903                 kvm_max_guest_tsc_khz = max;
904         }
905
906         if (nested) {
907                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
908                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
909         }
910
911         for_each_possible_cpu(cpu) {
912                 r = svm_cpu_init(cpu);
913                 if (r)
914                         goto err;
915         }
916
917         if (!boot_cpu_has(X86_FEATURE_NPT))
918                 npt_enabled = false;
919
920         if (npt_enabled && !npt) {
921                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
922                 npt_enabled = false;
923         }
924
925         if (npt_enabled) {
926                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
927                 kvm_enable_tdp();
928         } else
929                 kvm_disable_tdp();
930
931         return 0;
932
933 err:
934         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
935         iopm_base = 0;
936         return r;
937 }
938
939 static __exit void svm_hardware_unsetup(void)
940 {
941         int cpu;
942
943         for_each_possible_cpu(cpu)
944                 svm_cpu_uninit(cpu);
945
946         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
947         iopm_base = 0;
948 }
949
950 static void init_seg(struct vmcb_seg *seg)
951 {
952         seg->selector = 0;
953         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
954                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
955         seg->limit = 0xffff;
956         seg->base = 0;
957 }
958
959 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
960 {
961         seg->selector = 0;
962         seg->attrib = SVM_SELECTOR_P_MASK | type;
963         seg->limit = 0xffff;
964         seg->base = 0;
965 }
966
967 static u64 __scale_tsc(u64 ratio, u64 tsc)
968 {
969         u64 mult, frac, _tsc;
970
971         mult  = ratio >> 32;
972         frac  = ratio & ((1ULL << 32) - 1);
973
974         _tsc  = tsc;
975         _tsc *= mult;
976         _tsc += (tsc >> 32) * frac;
977         _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
978
979         return _tsc;
980 }
981
982 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
983 {
984         struct vcpu_svm *svm = to_svm(vcpu);
985         u64 _tsc = tsc;
986
987         if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
988                 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
989
990         return _tsc;
991 }
992
993 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
994 {
995         struct vcpu_svm *svm = to_svm(vcpu);
996         u64 ratio;
997         u64 khz;
998
999         /* Guest TSC same frequency as host TSC? */
1000         if (!scale) {
1001                 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1002                 return;
1003         }
1004
1005         /* TSC scaling supported? */
1006         if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1007                 if (user_tsc_khz > tsc_khz) {
1008                         vcpu->arch.tsc_catchup = 1;
1009                         vcpu->arch.tsc_always_catchup = 1;
1010                 } else
1011                         WARN(1, "user requested TSC rate below hardware speed\n");
1012                 return;
1013         }
1014
1015         khz = user_tsc_khz;
1016
1017         /* TSC scaling required  - calculate ratio */
1018         ratio = khz << 32;
1019         do_div(ratio, tsc_khz);
1020
1021         if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1022                 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1023                                 user_tsc_khz);
1024                 return;
1025         }
1026         svm->tsc_ratio             = ratio;
1027 }
1028
1029 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1030 {
1031         struct vcpu_svm *svm = to_svm(vcpu);
1032
1033         return svm->vmcb->control.tsc_offset;
1034 }
1035
1036 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1037 {
1038         struct vcpu_svm *svm = to_svm(vcpu);
1039         u64 g_tsc_offset = 0;
1040
1041         if (is_guest_mode(vcpu)) {
1042                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1043                                svm->nested.hsave->control.tsc_offset;
1044                 svm->nested.hsave->control.tsc_offset = offset;
1045         } else
1046                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1047                                            svm->vmcb->control.tsc_offset,
1048                                            offset);
1049
1050         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1051
1052         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1053 }
1054
1055 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1056 {
1057         struct vcpu_svm *svm = to_svm(vcpu);
1058
1059         if (host) {
1060                 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
1061                         WARN_ON(adjustment < 0);
1062                 adjustment = svm_scale_tsc(vcpu, (u64)adjustment);
1063         }
1064
1065         svm->vmcb->control.tsc_offset += adjustment;
1066         if (is_guest_mode(vcpu))
1067                 svm->nested.hsave->control.tsc_offset += adjustment;
1068         else
1069                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1070                                      svm->vmcb->control.tsc_offset - adjustment,
1071                                      svm->vmcb->control.tsc_offset);
1072
1073         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1074 }
1075
1076 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1077 {
1078         u64 tsc;
1079
1080         tsc = svm_scale_tsc(vcpu, native_read_tsc());
1081
1082         return target_tsc - tsc;
1083 }
1084
1085 static void init_vmcb(struct vcpu_svm *svm)
1086 {
1087         struct vmcb_control_area *control = &svm->vmcb->control;
1088         struct vmcb_save_area *save = &svm->vmcb->save;
1089
1090         svm->vcpu.fpu_active = 1;
1091         svm->vcpu.arch.hflags = 0;
1092
1093         set_cr_intercept(svm, INTERCEPT_CR0_READ);
1094         set_cr_intercept(svm, INTERCEPT_CR3_READ);
1095         set_cr_intercept(svm, INTERCEPT_CR4_READ);
1096         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1097         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1098         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1099         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1100
1101         set_dr_intercepts(svm);
1102
1103         set_exception_intercept(svm, PF_VECTOR);
1104         set_exception_intercept(svm, UD_VECTOR);
1105         set_exception_intercept(svm, MC_VECTOR);
1106
1107         set_intercept(svm, INTERCEPT_INTR);
1108         set_intercept(svm, INTERCEPT_NMI);
1109         set_intercept(svm, INTERCEPT_SMI);
1110         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1111         set_intercept(svm, INTERCEPT_RDPMC);
1112         set_intercept(svm, INTERCEPT_CPUID);
1113         set_intercept(svm, INTERCEPT_INVD);
1114         set_intercept(svm, INTERCEPT_HLT);
1115         set_intercept(svm, INTERCEPT_INVLPG);
1116         set_intercept(svm, INTERCEPT_INVLPGA);
1117         set_intercept(svm, INTERCEPT_IOIO_PROT);
1118         set_intercept(svm, INTERCEPT_MSR_PROT);
1119         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1120         set_intercept(svm, INTERCEPT_SHUTDOWN);
1121         set_intercept(svm, INTERCEPT_VMRUN);
1122         set_intercept(svm, INTERCEPT_VMMCALL);
1123         set_intercept(svm, INTERCEPT_VMLOAD);
1124         set_intercept(svm, INTERCEPT_VMSAVE);
1125         set_intercept(svm, INTERCEPT_STGI);
1126         set_intercept(svm, INTERCEPT_CLGI);
1127         set_intercept(svm, INTERCEPT_SKINIT);
1128         set_intercept(svm, INTERCEPT_WBINVD);
1129         set_intercept(svm, INTERCEPT_MONITOR);
1130         set_intercept(svm, INTERCEPT_MWAIT);
1131         set_intercept(svm, INTERCEPT_XSETBV);
1132
1133         control->iopm_base_pa = iopm_base;
1134         control->msrpm_base_pa = __pa(svm->msrpm);
1135         control->int_ctl = V_INTR_MASKING_MASK;
1136
1137         init_seg(&save->es);
1138         init_seg(&save->ss);
1139         init_seg(&save->ds);
1140         init_seg(&save->fs);
1141         init_seg(&save->gs);
1142
1143         save->cs.selector = 0xf000;
1144         save->cs.base = 0xffff0000;
1145         /* Executable/Readable Code Segment */
1146         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1147                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1148         save->cs.limit = 0xffff;
1149
1150         save->gdtr.limit = 0xffff;
1151         save->idtr.limit = 0xffff;
1152
1153         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1154         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1155
1156         svm_set_efer(&svm->vcpu, 0);
1157         save->dr6 = 0xffff0ff0;
1158         kvm_set_rflags(&svm->vcpu, 2);
1159         save->rip = 0x0000fff0;
1160         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1161
1162         /*
1163          * This is the guest-visible cr0 value.
1164          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1165          */
1166         svm->vcpu.arch.cr0 = 0;
1167         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1168
1169         save->cr4 = X86_CR4_PAE;
1170         /* rdx = ?? */
1171
1172         if (npt_enabled) {
1173                 /* Setup VMCB for Nested Paging */
1174                 control->nested_ctl = 1;
1175                 clr_intercept(svm, INTERCEPT_INVLPG);
1176                 clr_exception_intercept(svm, PF_VECTOR);
1177                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1178                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1179                 save->g_pat = 0x0007040600070406ULL;
1180                 save->cr3 = 0;
1181                 save->cr4 = 0;
1182         }
1183         svm->asid_generation = 0;
1184
1185         svm->nested.vmcb = 0;
1186         svm->vcpu.arch.hflags = 0;
1187
1188         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1189                 control->pause_filter_count = 3000;
1190                 set_intercept(svm, INTERCEPT_PAUSE);
1191         }
1192
1193         mark_all_dirty(svm->vmcb);
1194
1195         enable_gif(svm);
1196 }
1197
1198 static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
1199 {
1200         struct vcpu_svm *svm = to_svm(vcpu);
1201         u32 dummy;
1202         u32 eax = 1;
1203
1204         init_vmcb(svm);
1205
1206         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1207         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1208 }
1209
1210 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1211 {
1212         struct vcpu_svm *svm;
1213         struct page *page;
1214         struct page *msrpm_pages;
1215         struct page *hsave_page;
1216         struct page *nested_msrpm_pages;
1217         int err;
1218
1219         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1220         if (!svm) {
1221                 err = -ENOMEM;
1222                 goto out;
1223         }
1224
1225         svm->tsc_ratio = TSC_RATIO_DEFAULT;
1226
1227         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1228         if (err)
1229                 goto free_svm;
1230
1231         err = -ENOMEM;
1232         page = alloc_page(GFP_KERNEL);
1233         if (!page)
1234                 goto uninit;
1235
1236         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1237         if (!msrpm_pages)
1238                 goto free_page1;
1239
1240         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1241         if (!nested_msrpm_pages)
1242                 goto free_page2;
1243
1244         hsave_page = alloc_page(GFP_KERNEL);
1245         if (!hsave_page)
1246                 goto free_page3;
1247
1248         svm->nested.hsave = page_address(hsave_page);
1249
1250         svm->msrpm = page_address(msrpm_pages);
1251         svm_vcpu_init_msrpm(svm->msrpm);
1252
1253         svm->nested.msrpm = page_address(nested_msrpm_pages);
1254         svm_vcpu_init_msrpm(svm->nested.msrpm);
1255
1256         svm->vmcb = page_address(page);
1257         clear_page(svm->vmcb);
1258         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1259         svm->asid_generation = 0;
1260         init_vmcb(svm);
1261
1262         svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1263                                    MSR_IA32_APICBASE_ENABLE;
1264         if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1265                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1266
1267         svm_init_osvw(&svm->vcpu);
1268
1269         return &svm->vcpu;
1270
1271 free_page3:
1272         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1273 free_page2:
1274         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1275 free_page1:
1276         __free_page(page);
1277 uninit:
1278         kvm_vcpu_uninit(&svm->vcpu);
1279 free_svm:
1280         kmem_cache_free(kvm_vcpu_cache, svm);
1281 out:
1282         return ERR_PTR(err);
1283 }
1284
1285 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1286 {
1287         struct vcpu_svm *svm = to_svm(vcpu);
1288
1289         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1290         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1291         __free_page(virt_to_page(svm->nested.hsave));
1292         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1293         kvm_vcpu_uninit(vcpu);
1294         kmem_cache_free(kvm_vcpu_cache, svm);
1295 }
1296
1297 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1298 {
1299         struct vcpu_svm *svm = to_svm(vcpu);
1300         int i;
1301
1302         if (unlikely(cpu != vcpu->cpu)) {
1303                 svm->asid_generation = 0;
1304                 mark_all_dirty(svm->vmcb);
1305         }
1306
1307 #ifdef CONFIG_X86_64
1308         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1309 #endif
1310         savesegment(fs, svm->host.fs);
1311         savesegment(gs, svm->host.gs);
1312         svm->host.ldt = kvm_read_ldt();
1313
1314         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1315                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1316
1317         if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1318             svm->tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1319                 __this_cpu_write(current_tsc_ratio, svm->tsc_ratio);
1320                 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1321         }
1322 }
1323
1324 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1325 {
1326         struct vcpu_svm *svm = to_svm(vcpu);
1327         int i;
1328
1329         ++vcpu->stat.host_state_reload;
1330         kvm_load_ldt(svm->host.ldt);
1331 #ifdef CONFIG_X86_64
1332         loadsegment(fs, svm->host.fs);
1333         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1334         load_gs_index(svm->host.gs);
1335 #else
1336 #ifdef CONFIG_X86_32_LAZY_GS
1337         loadsegment(gs, svm->host.gs);
1338 #endif
1339 #endif
1340         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1341                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1342 }
1343
1344 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1345 {
1346         return to_svm(vcpu)->vmcb->save.rflags;
1347 }
1348
1349 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1350 {
1351        /*
1352         * Any change of EFLAGS.VM is accompained by a reload of SS
1353         * (caused by either a task switch or an inter-privilege IRET),
1354         * so we do not need to update the CPL here.
1355         */
1356         to_svm(vcpu)->vmcb->save.rflags = rflags;
1357 }
1358
1359 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1360 {
1361         switch (reg) {
1362         case VCPU_EXREG_PDPTR:
1363                 BUG_ON(!npt_enabled);
1364                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1365                 break;
1366         default:
1367                 BUG();
1368         }
1369 }
1370
1371 static void svm_set_vintr(struct vcpu_svm *svm)
1372 {
1373         set_intercept(svm, INTERCEPT_VINTR);
1374 }
1375
1376 static void svm_clear_vintr(struct vcpu_svm *svm)
1377 {
1378         clr_intercept(svm, INTERCEPT_VINTR);
1379 }
1380
1381 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1382 {
1383         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1384
1385         switch (seg) {
1386         case VCPU_SREG_CS: return &save->cs;
1387         case VCPU_SREG_DS: return &save->ds;
1388         case VCPU_SREG_ES: return &save->es;
1389         case VCPU_SREG_FS: return &save->fs;
1390         case VCPU_SREG_GS: return &save->gs;
1391         case VCPU_SREG_SS: return &save->ss;
1392         case VCPU_SREG_TR: return &save->tr;
1393         case VCPU_SREG_LDTR: return &save->ldtr;
1394         }
1395         BUG();
1396         return NULL;
1397 }
1398
1399 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1400 {
1401         struct vmcb_seg *s = svm_seg(vcpu, seg);
1402
1403         return s->base;
1404 }
1405
1406 static void svm_get_segment(struct kvm_vcpu *vcpu,
1407                             struct kvm_segment *var, int seg)
1408 {
1409         struct vmcb_seg *s = svm_seg(vcpu, seg);
1410
1411         var->base = s->base;
1412         var->limit = s->limit;
1413         var->selector = s->selector;
1414         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1415         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1416         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1417         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1418         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1419         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1420         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1421
1422         /*
1423          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1424          * However, the SVM spec states that the G bit is not observed by the
1425          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1426          * So let's synthesize a legal G bit for all segments, this helps
1427          * running KVM nested. It also helps cross-vendor migration, because
1428          * Intel's vmentry has a check on the 'G' bit.
1429          */
1430         var->g = s->limit > 0xfffff;
1431
1432         /*
1433          * AMD's VMCB does not have an explicit unusable field, so emulate it
1434          * for cross vendor migration purposes by "not present"
1435          */
1436         var->unusable = !var->present || (var->type == 0);
1437
1438         switch (seg) {
1439         case VCPU_SREG_TR:
1440                 /*
1441                  * Work around a bug where the busy flag in the tr selector
1442                  * isn't exposed
1443                  */
1444                 var->type |= 0x2;
1445                 break;
1446         case VCPU_SREG_DS:
1447         case VCPU_SREG_ES:
1448         case VCPU_SREG_FS:
1449         case VCPU_SREG_GS:
1450                 /*
1451                  * The accessed bit must always be set in the segment
1452                  * descriptor cache, although it can be cleared in the
1453                  * descriptor, the cached bit always remains at 1. Since
1454                  * Intel has a check on this, set it here to support
1455                  * cross-vendor migration.
1456                  */
1457                 if (!var->unusable)
1458                         var->type |= 0x1;
1459                 break;
1460         case VCPU_SREG_SS:
1461                 /*
1462                  * On AMD CPUs sometimes the DB bit in the segment
1463                  * descriptor is left as 1, although the whole segment has
1464                  * been made unusable. Clear it here to pass an Intel VMX
1465                  * entry check when cross vendor migrating.
1466                  */
1467                 if (var->unusable)
1468                         var->db = 0;
1469                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1470                 break;
1471         }
1472 }
1473
1474 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1475 {
1476         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1477
1478         return save->cpl;
1479 }
1480
1481 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1482 {
1483         struct vcpu_svm *svm = to_svm(vcpu);
1484
1485         dt->size = svm->vmcb->save.idtr.limit;
1486         dt->address = svm->vmcb->save.idtr.base;
1487 }
1488
1489 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1490 {
1491         struct vcpu_svm *svm = to_svm(vcpu);
1492
1493         svm->vmcb->save.idtr.limit = dt->size;
1494         svm->vmcb->save.idtr.base = dt->address ;
1495         mark_dirty(svm->vmcb, VMCB_DT);
1496 }
1497
1498 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1499 {
1500         struct vcpu_svm *svm = to_svm(vcpu);
1501
1502         dt->size = svm->vmcb->save.gdtr.limit;
1503         dt->address = svm->vmcb->save.gdtr.base;
1504 }
1505
1506 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1507 {
1508         struct vcpu_svm *svm = to_svm(vcpu);
1509
1510         svm->vmcb->save.gdtr.limit = dt->size;
1511         svm->vmcb->save.gdtr.base = dt->address ;
1512         mark_dirty(svm->vmcb, VMCB_DT);
1513 }
1514
1515 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1516 {
1517 }
1518
1519 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1520 {
1521 }
1522
1523 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1524 {
1525 }
1526
1527 static void update_cr0_intercept(struct vcpu_svm *svm)
1528 {
1529         ulong gcr0 = svm->vcpu.arch.cr0;
1530         u64 *hcr0 = &svm->vmcb->save.cr0;
1531
1532         if (!svm->vcpu.fpu_active)
1533                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1534         else
1535                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1536                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1537
1538         mark_dirty(svm->vmcb, VMCB_CR);
1539
1540         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1541                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1542                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1543         } else {
1544                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1545                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1546         }
1547 }
1548
1549 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1550 {
1551         struct vcpu_svm *svm = to_svm(vcpu);
1552
1553 #ifdef CONFIG_X86_64
1554         if (vcpu->arch.efer & EFER_LME) {
1555                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1556                         vcpu->arch.efer |= EFER_LMA;
1557                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1558                 }
1559
1560                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1561                         vcpu->arch.efer &= ~EFER_LMA;
1562                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1563                 }
1564         }
1565 #endif
1566         vcpu->arch.cr0 = cr0;
1567
1568         if (!npt_enabled)
1569                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1570
1571         if (!vcpu->fpu_active)
1572                 cr0 |= X86_CR0_TS;
1573         /*
1574          * re-enable caching here because the QEMU bios
1575          * does not do it - this results in some delay at
1576          * reboot
1577          */
1578         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1579         svm->vmcb->save.cr0 = cr0;
1580         mark_dirty(svm->vmcb, VMCB_CR);
1581         update_cr0_intercept(svm);
1582 }
1583
1584 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1585 {
1586         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1587         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1588
1589         if (cr4 & X86_CR4_VMXE)
1590                 return 1;
1591
1592         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1593                 svm_flush_tlb(vcpu);
1594
1595         vcpu->arch.cr4 = cr4;
1596         if (!npt_enabled)
1597                 cr4 |= X86_CR4_PAE;
1598         cr4 |= host_cr4_mce;
1599         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1600         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1601         return 0;
1602 }
1603
1604 static void svm_set_segment(struct kvm_vcpu *vcpu,
1605                             struct kvm_segment *var, int seg)
1606 {
1607         struct vcpu_svm *svm = to_svm(vcpu);
1608         struct vmcb_seg *s = svm_seg(vcpu, seg);
1609
1610         s->base = var->base;
1611         s->limit = var->limit;
1612         s->selector = var->selector;
1613         if (var->unusable)
1614                 s->attrib = 0;
1615         else {
1616                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1617                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1618                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1619                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1620                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1621                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1622                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1623                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1624         }
1625
1626         /*
1627          * This is always accurate, except if SYSRET returned to a segment
1628          * with SS.DPL != 3.  Intel does not have this quirk, and always
1629          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1630          * would entail passing the CPL to userspace and back.
1631          */
1632         if (seg == VCPU_SREG_SS)
1633                 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1634
1635         mark_dirty(svm->vmcb, VMCB_SEG);
1636 }
1637
1638 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1639 {
1640         struct vcpu_svm *svm = to_svm(vcpu);
1641
1642         clr_exception_intercept(svm, DB_VECTOR);
1643         clr_exception_intercept(svm, BP_VECTOR);
1644
1645         if (svm->nmi_singlestep)
1646                 set_exception_intercept(svm, DB_VECTOR);
1647
1648         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1649                 if (vcpu->guest_debug &
1650                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1651                         set_exception_intercept(svm, DB_VECTOR);
1652                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1653                         set_exception_intercept(svm, BP_VECTOR);
1654         } else
1655                 vcpu->guest_debug = 0;
1656 }
1657
1658 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1659 {
1660         if (sd->next_asid > sd->max_asid) {
1661                 ++sd->asid_generation;
1662                 sd->next_asid = 1;
1663                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1664         }
1665
1666         svm->asid_generation = sd->asid_generation;
1667         svm->vmcb->control.asid = sd->next_asid++;
1668
1669         mark_dirty(svm->vmcb, VMCB_ASID);
1670 }
1671
1672 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1673 {
1674         return to_svm(vcpu)->vmcb->save.dr6;
1675 }
1676
1677 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1678 {
1679         struct vcpu_svm *svm = to_svm(vcpu);
1680
1681         svm->vmcb->save.dr6 = value;
1682         mark_dirty(svm->vmcb, VMCB_DR);
1683 }
1684
1685 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1686 {
1687         struct vcpu_svm *svm = to_svm(vcpu);
1688
1689         get_debugreg(vcpu->arch.db[0], 0);
1690         get_debugreg(vcpu->arch.db[1], 1);
1691         get_debugreg(vcpu->arch.db[2], 2);
1692         get_debugreg(vcpu->arch.db[3], 3);
1693         vcpu->arch.dr6 = svm_get_dr6(vcpu);
1694         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1695
1696         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1697         set_dr_intercepts(svm);
1698 }
1699
1700 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1701 {
1702         struct vcpu_svm *svm = to_svm(vcpu);
1703
1704         svm->vmcb->save.dr7 = value;
1705         mark_dirty(svm->vmcb, VMCB_DR);
1706 }
1707
1708 static int pf_interception(struct vcpu_svm *svm)
1709 {
1710         u64 fault_address = svm->vmcb->control.exit_info_2;
1711         u32 error_code;
1712         int r = 1;
1713
1714         switch (svm->apf_reason) {
1715         default:
1716                 error_code = svm->vmcb->control.exit_info_1;
1717
1718                 trace_kvm_page_fault(fault_address, error_code);
1719                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1720                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1721                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1722                         svm->vmcb->control.insn_bytes,
1723                         svm->vmcb->control.insn_len);
1724                 break;
1725         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1726                 svm->apf_reason = 0;
1727                 local_irq_disable();
1728                 kvm_async_pf_task_wait(fault_address);
1729                 local_irq_enable();
1730                 break;
1731         case KVM_PV_REASON_PAGE_READY:
1732                 svm->apf_reason = 0;
1733                 local_irq_disable();
1734                 kvm_async_pf_task_wake(fault_address);
1735                 local_irq_enable();
1736                 break;
1737         }
1738         return r;
1739 }
1740
1741 static int db_interception(struct vcpu_svm *svm)
1742 {
1743         struct kvm_run *kvm_run = svm->vcpu.run;
1744
1745         if (!(svm->vcpu.guest_debug &
1746               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1747                 !svm->nmi_singlestep) {
1748                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1749                 return 1;
1750         }
1751
1752         if (svm->nmi_singlestep) {
1753                 svm->nmi_singlestep = false;
1754                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1755                         svm->vmcb->save.rflags &=
1756                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1757                 update_db_bp_intercept(&svm->vcpu);
1758         }
1759
1760         if (svm->vcpu.guest_debug &
1761             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1762                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1763                 kvm_run->debug.arch.pc =
1764                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1765                 kvm_run->debug.arch.exception = DB_VECTOR;
1766                 return 0;
1767         }
1768
1769         return 1;
1770 }
1771
1772 static int bp_interception(struct vcpu_svm *svm)
1773 {
1774         struct kvm_run *kvm_run = svm->vcpu.run;
1775
1776         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1777         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1778         kvm_run->debug.arch.exception = BP_VECTOR;
1779         return 0;
1780 }
1781
1782 static int ud_interception(struct vcpu_svm *svm)
1783 {
1784         int er;
1785
1786         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1787         if (er != EMULATE_DONE)
1788                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1789         return 1;
1790 }
1791
1792 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1793 {
1794         struct vcpu_svm *svm = to_svm(vcpu);
1795
1796         clr_exception_intercept(svm, NM_VECTOR);
1797
1798         svm->vcpu.fpu_active = 1;
1799         update_cr0_intercept(svm);
1800 }
1801
1802 static int nm_interception(struct vcpu_svm *svm)
1803 {
1804         svm_fpu_activate(&svm->vcpu);
1805         return 1;
1806 }
1807
1808 static bool is_erratum_383(void)
1809 {
1810         int err, i;
1811         u64 value;
1812
1813         if (!erratum_383_found)
1814                 return false;
1815
1816         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1817         if (err)
1818                 return false;
1819
1820         /* Bit 62 may or may not be set for this mce */
1821         value &= ~(1ULL << 62);
1822
1823         if (value != 0xb600000000010015ULL)
1824                 return false;
1825
1826         /* Clear MCi_STATUS registers */
1827         for (i = 0; i < 6; ++i)
1828                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1829
1830         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1831         if (!err) {
1832                 u32 low, high;
1833
1834                 value &= ~(1ULL << 2);
1835                 low    = lower_32_bits(value);
1836                 high   = upper_32_bits(value);
1837
1838                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1839         }
1840
1841         /* Flush tlb to evict multi-match entries */
1842         __flush_tlb_all();
1843
1844         return true;
1845 }
1846
1847 static void svm_handle_mce(struct vcpu_svm *svm)
1848 {
1849         if (is_erratum_383()) {
1850                 /*
1851                  * Erratum 383 triggered. Guest state is corrupt so kill the
1852                  * guest.
1853                  */
1854                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1855
1856                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1857
1858                 return;
1859         }
1860
1861         /*
1862          * On an #MC intercept the MCE handler is not called automatically in
1863          * the host. So do it by hand here.
1864          */
1865         asm volatile (
1866                 "int $0x12\n");
1867         /* not sure if we ever come back to this point */
1868
1869         return;
1870 }
1871
1872 static int mc_interception(struct vcpu_svm *svm)
1873 {
1874         return 1;
1875 }
1876
1877 static int shutdown_interception(struct vcpu_svm *svm)
1878 {
1879         struct kvm_run *kvm_run = svm->vcpu.run;
1880
1881         /*
1882          * VMCB is undefined after a SHUTDOWN intercept
1883          * so reinitialize it.
1884          */
1885         clear_page(svm->vmcb);
1886         init_vmcb(svm);
1887
1888         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1889         return 0;
1890 }
1891
1892 static int io_interception(struct vcpu_svm *svm)
1893 {
1894         struct kvm_vcpu *vcpu = &svm->vcpu;
1895         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1896         int size, in, string;
1897         unsigned port;
1898
1899         ++svm->vcpu.stat.io_exits;
1900         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1901         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1902         if (string || in)
1903                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1904
1905         port = io_info >> 16;
1906         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1907         svm->next_rip = svm->vmcb->control.exit_info_2;
1908         skip_emulated_instruction(&svm->vcpu);
1909
1910         return kvm_fast_pio_out(vcpu, size, port);
1911 }
1912
1913 static int nmi_interception(struct vcpu_svm *svm)
1914 {
1915         return 1;
1916 }
1917
1918 static int intr_interception(struct vcpu_svm *svm)
1919 {
1920         ++svm->vcpu.stat.irq_exits;
1921         return 1;
1922 }
1923
1924 static int nop_on_interception(struct vcpu_svm *svm)
1925 {
1926         return 1;
1927 }
1928
1929 static int halt_interception(struct vcpu_svm *svm)
1930 {
1931         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1932         return kvm_emulate_halt(&svm->vcpu);
1933 }
1934
1935 static int vmmcall_interception(struct vcpu_svm *svm)
1936 {
1937         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1938         kvm_emulate_hypercall(&svm->vcpu);
1939         return 1;
1940 }
1941
1942 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1943 {
1944         struct vcpu_svm *svm = to_svm(vcpu);
1945
1946         return svm->nested.nested_cr3;
1947 }
1948
1949 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1950 {
1951         struct vcpu_svm *svm = to_svm(vcpu);
1952         u64 cr3 = svm->nested.nested_cr3;
1953         u64 pdpte;
1954         int ret;
1955
1956         ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1957                                   offset_in_page(cr3) + index * 8, 8);
1958         if (ret)
1959                 return 0;
1960         return pdpte;
1961 }
1962
1963 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1964                                    unsigned long root)
1965 {
1966         struct vcpu_svm *svm = to_svm(vcpu);
1967
1968         svm->vmcb->control.nested_cr3 = root;
1969         mark_dirty(svm->vmcb, VMCB_NPT);
1970         svm_flush_tlb(vcpu);
1971 }
1972
1973 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1974                                        struct x86_exception *fault)
1975 {
1976         struct vcpu_svm *svm = to_svm(vcpu);
1977
1978         if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
1979                 /*
1980                  * TODO: track the cause of the nested page fault, and
1981                  * correctly fill in the high bits of exit_info_1.
1982                  */
1983                 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1984                 svm->vmcb->control.exit_code_hi = 0;
1985                 svm->vmcb->control.exit_info_1 = (1ULL << 32);
1986                 svm->vmcb->control.exit_info_2 = fault->address;
1987         }
1988
1989         svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
1990         svm->vmcb->control.exit_info_1 |= fault->error_code;
1991
1992         /*
1993          * The present bit is always zero for page structure faults on real
1994          * hardware.
1995          */
1996         if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
1997                 svm->vmcb->control.exit_info_1 &= ~1;
1998
1999         nested_svm_vmexit(svm);
2000 }
2001
2002 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2003 {
2004         WARN_ON(mmu_is_nested(vcpu));
2005         kvm_init_shadow_mmu(vcpu);
2006         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
2007         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
2008         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
2009         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2010         vcpu->arch.mmu.shadow_root_level = get_npt_level();
2011         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
2012 }
2013
2014 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2015 {
2016         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2017 }
2018
2019 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2020 {
2021         if (!(svm->vcpu.arch.efer & EFER_SVME)
2022             || !is_paging(&svm->vcpu)) {
2023                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2024                 return 1;
2025         }
2026
2027         if (svm->vmcb->save.cpl) {
2028                 kvm_inject_gp(&svm->vcpu, 0);
2029                 return 1;
2030         }
2031
2032        return 0;
2033 }
2034
2035 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2036                                       bool has_error_code, u32 error_code)
2037 {
2038         int vmexit;
2039
2040         if (!is_guest_mode(&svm->vcpu))
2041                 return 0;
2042
2043         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2044         svm->vmcb->control.exit_code_hi = 0;
2045         svm->vmcb->control.exit_info_1 = error_code;
2046         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2047
2048         vmexit = nested_svm_intercept(svm);
2049         if (vmexit == NESTED_EXIT_DONE)
2050                 svm->nested.exit_required = true;
2051
2052         return vmexit;
2053 }
2054
2055 /* This function returns true if it is save to enable the irq window */
2056 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2057 {
2058         if (!is_guest_mode(&svm->vcpu))
2059                 return true;
2060
2061         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2062                 return true;
2063
2064         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2065                 return false;
2066
2067         /*
2068          * if vmexit was already requested (by intercepted exception
2069          * for instance) do not overwrite it with "external interrupt"
2070          * vmexit.
2071          */
2072         if (svm->nested.exit_required)
2073                 return false;
2074
2075         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
2076         svm->vmcb->control.exit_info_1 = 0;
2077         svm->vmcb->control.exit_info_2 = 0;
2078
2079         if (svm->nested.intercept & 1ULL) {
2080                 /*
2081                  * The #vmexit can't be emulated here directly because this
2082                  * code path runs with irqs and preemption disabled. A
2083                  * #vmexit emulation might sleep. Only signal request for
2084                  * the #vmexit here.
2085                  */
2086                 svm->nested.exit_required = true;
2087                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2088                 return false;
2089         }
2090
2091         return true;
2092 }
2093
2094 /* This function returns true if it is save to enable the nmi window */
2095 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2096 {
2097         if (!is_guest_mode(&svm->vcpu))
2098                 return true;
2099
2100         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2101                 return true;
2102
2103         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2104         svm->nested.exit_required = true;
2105
2106         return false;
2107 }
2108
2109 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2110 {
2111         struct page *page;
2112
2113         might_sleep();
2114
2115         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2116         if (is_error_page(page))
2117                 goto error;
2118
2119         *_page = page;
2120
2121         return kmap(page);
2122
2123 error:
2124         kvm_inject_gp(&svm->vcpu, 0);
2125
2126         return NULL;
2127 }
2128
2129 static void nested_svm_unmap(struct page *page)
2130 {
2131         kunmap(page);
2132         kvm_release_page_dirty(page);
2133 }
2134
2135 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2136 {
2137         unsigned port, size, iopm_len;
2138         u16 val, mask;
2139         u8 start_bit;
2140         u64 gpa;
2141
2142         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2143                 return NESTED_EXIT_HOST;
2144
2145         port = svm->vmcb->control.exit_info_1 >> 16;
2146         size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2147                 SVM_IOIO_SIZE_SHIFT;
2148         gpa  = svm->nested.vmcb_iopm + (port / 8);
2149         start_bit = port % 8;
2150         iopm_len = (start_bit + size > 8) ? 2 : 1;
2151         mask = (0xf >> (4 - size)) << start_bit;
2152         val = 0;
2153
2154         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, iopm_len))
2155                 return NESTED_EXIT_DONE;
2156
2157         return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2158 }
2159
2160 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2161 {
2162         u32 offset, msr, value;
2163         int write, mask;
2164
2165         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2166                 return NESTED_EXIT_HOST;
2167
2168         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2169         offset = svm_msrpm_offset(msr);
2170         write  = svm->vmcb->control.exit_info_1 & 1;
2171         mask   = 1 << ((2 * (msr & 0xf)) + write);
2172
2173         if (offset == MSR_INVALID)
2174                 return NESTED_EXIT_DONE;
2175
2176         /* Offset is in 32 bit units but need in 8 bit units */
2177         offset *= 4;
2178
2179         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2180                 return NESTED_EXIT_DONE;
2181
2182         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2183 }
2184
2185 static int nested_svm_exit_special(struct vcpu_svm *svm)
2186 {
2187         u32 exit_code = svm->vmcb->control.exit_code;
2188
2189         switch (exit_code) {
2190         case SVM_EXIT_INTR:
2191         case SVM_EXIT_NMI:
2192         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2193                 return NESTED_EXIT_HOST;
2194         case SVM_EXIT_NPF:
2195                 /* For now we are always handling NPFs when using them */
2196                 if (npt_enabled)
2197                         return NESTED_EXIT_HOST;
2198                 break;
2199         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2200                 /* When we're shadowing, trap PFs, but not async PF */
2201                 if (!npt_enabled && svm->apf_reason == 0)
2202                         return NESTED_EXIT_HOST;
2203                 break;
2204         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2205                 nm_interception(svm);
2206                 break;
2207         default:
2208                 break;
2209         }
2210
2211         return NESTED_EXIT_CONTINUE;
2212 }
2213
2214 /*
2215  * If this function returns true, this #vmexit was already handled
2216  */
2217 static int nested_svm_intercept(struct vcpu_svm *svm)
2218 {
2219         u32 exit_code = svm->vmcb->control.exit_code;
2220         int vmexit = NESTED_EXIT_HOST;
2221
2222         switch (exit_code) {
2223         case SVM_EXIT_MSR:
2224                 vmexit = nested_svm_exit_handled_msr(svm);
2225                 break;
2226         case SVM_EXIT_IOIO:
2227                 vmexit = nested_svm_intercept_ioio(svm);
2228                 break;
2229         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2230                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2231                 if (svm->nested.intercept_cr & bit)
2232                         vmexit = NESTED_EXIT_DONE;
2233                 break;
2234         }
2235         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2236                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2237                 if (svm->nested.intercept_dr & bit)
2238                         vmexit = NESTED_EXIT_DONE;
2239                 break;
2240         }
2241         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2242                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2243                 if (svm->nested.intercept_exceptions & excp_bits)
2244                         vmexit = NESTED_EXIT_DONE;
2245                 /* async page fault always cause vmexit */
2246                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2247                          svm->apf_reason != 0)
2248                         vmexit = NESTED_EXIT_DONE;
2249                 break;
2250         }
2251         case SVM_EXIT_ERR: {
2252                 vmexit = NESTED_EXIT_DONE;
2253                 break;
2254         }
2255         default: {
2256                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2257                 if (svm->nested.intercept & exit_bits)
2258                         vmexit = NESTED_EXIT_DONE;
2259         }
2260         }
2261
2262         return vmexit;
2263 }
2264
2265 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2266 {
2267         int vmexit;
2268
2269         vmexit = nested_svm_intercept(svm);
2270
2271         if (vmexit == NESTED_EXIT_DONE)
2272                 nested_svm_vmexit(svm);
2273
2274         return vmexit;
2275 }
2276
2277 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2278 {
2279         struct vmcb_control_area *dst  = &dst_vmcb->control;
2280         struct vmcb_control_area *from = &from_vmcb->control;
2281
2282         dst->intercept_cr         = from->intercept_cr;
2283         dst->intercept_dr         = from->intercept_dr;
2284         dst->intercept_exceptions = from->intercept_exceptions;
2285         dst->intercept            = from->intercept;
2286         dst->iopm_base_pa         = from->iopm_base_pa;
2287         dst->msrpm_base_pa        = from->msrpm_base_pa;
2288         dst->tsc_offset           = from->tsc_offset;
2289         dst->asid                 = from->asid;
2290         dst->tlb_ctl              = from->tlb_ctl;
2291         dst->int_ctl              = from->int_ctl;
2292         dst->int_vector           = from->int_vector;
2293         dst->int_state            = from->int_state;
2294         dst->exit_code            = from->exit_code;
2295         dst->exit_code_hi         = from->exit_code_hi;
2296         dst->exit_info_1          = from->exit_info_1;
2297         dst->exit_info_2          = from->exit_info_2;
2298         dst->exit_int_info        = from->exit_int_info;
2299         dst->exit_int_info_err    = from->exit_int_info_err;
2300         dst->nested_ctl           = from->nested_ctl;
2301         dst->event_inj            = from->event_inj;
2302         dst->event_inj_err        = from->event_inj_err;
2303         dst->nested_cr3           = from->nested_cr3;
2304         dst->lbr_ctl              = from->lbr_ctl;
2305 }
2306
2307 static int nested_svm_vmexit(struct vcpu_svm *svm)
2308 {
2309         struct vmcb *nested_vmcb;
2310         struct vmcb *hsave = svm->nested.hsave;
2311         struct vmcb *vmcb = svm->vmcb;
2312         struct page *page;
2313
2314         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2315                                        vmcb->control.exit_info_1,
2316                                        vmcb->control.exit_info_2,
2317                                        vmcb->control.exit_int_info,
2318                                        vmcb->control.exit_int_info_err,
2319                                        KVM_ISA_SVM);
2320
2321         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2322         if (!nested_vmcb)
2323                 return 1;
2324
2325         /* Exit Guest-Mode */
2326         leave_guest_mode(&svm->vcpu);
2327         svm->nested.vmcb = 0;
2328
2329         /* Give the current vmcb to the guest */
2330         disable_gif(svm);
2331
2332         nested_vmcb->save.es     = vmcb->save.es;
2333         nested_vmcb->save.cs     = vmcb->save.cs;
2334         nested_vmcb->save.ss     = vmcb->save.ss;
2335         nested_vmcb->save.ds     = vmcb->save.ds;
2336         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2337         nested_vmcb->save.idtr   = vmcb->save.idtr;
2338         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2339         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2340         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2341         nested_vmcb->save.cr2    = vmcb->save.cr2;
2342         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2343         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2344         nested_vmcb->save.rip    = vmcb->save.rip;
2345         nested_vmcb->save.rsp    = vmcb->save.rsp;
2346         nested_vmcb->save.rax    = vmcb->save.rax;
2347         nested_vmcb->save.dr7    = vmcb->save.dr7;
2348         nested_vmcb->save.dr6    = vmcb->save.dr6;
2349         nested_vmcb->save.cpl    = vmcb->save.cpl;
2350
2351         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2352         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2353         nested_vmcb->control.int_state         = vmcb->control.int_state;
2354         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2355         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2356         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2357         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2358         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2359         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2360         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2361
2362         /*
2363          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2364          * to make sure that we do not lose injected events. So check event_inj
2365          * here and copy it to exit_int_info if it is valid.
2366          * Exit_int_info and event_inj can't be both valid because the case
2367          * below only happens on a VMRUN instruction intercept which has
2368          * no valid exit_int_info set.
2369          */
2370         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2371                 struct vmcb_control_area *nc = &nested_vmcb->control;
2372
2373                 nc->exit_int_info     = vmcb->control.event_inj;
2374                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2375         }
2376
2377         nested_vmcb->control.tlb_ctl           = 0;
2378         nested_vmcb->control.event_inj         = 0;
2379         nested_vmcb->control.event_inj_err     = 0;
2380
2381         /* We always set V_INTR_MASKING and remember the old value in hflags */
2382         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2383                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2384
2385         /* Restore the original control entries */
2386         copy_vmcb_control_area(vmcb, hsave);
2387
2388         kvm_clear_exception_queue(&svm->vcpu);
2389         kvm_clear_interrupt_queue(&svm->vcpu);
2390
2391         svm->nested.nested_cr3 = 0;
2392
2393         /* Restore selected save entries */
2394         svm->vmcb->save.es = hsave->save.es;
2395         svm->vmcb->save.cs = hsave->save.cs;
2396         svm->vmcb->save.ss = hsave->save.ss;
2397         svm->vmcb->save.ds = hsave->save.ds;
2398         svm->vmcb->save.gdtr = hsave->save.gdtr;
2399         svm->vmcb->save.idtr = hsave->save.idtr;
2400         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2401         svm_set_efer(&svm->vcpu, hsave->save.efer);
2402         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2403         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2404         if (npt_enabled) {
2405                 svm->vmcb->save.cr3 = hsave->save.cr3;
2406                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2407         } else {
2408                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2409         }
2410         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2411         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2412         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2413         svm->vmcb->save.dr7 = 0;
2414         svm->vmcb->save.cpl = 0;
2415         svm->vmcb->control.exit_int_info = 0;
2416
2417         mark_all_dirty(svm->vmcb);
2418
2419         nested_svm_unmap(page);
2420
2421         nested_svm_uninit_mmu_context(&svm->vcpu);
2422         kvm_mmu_reset_context(&svm->vcpu);
2423         kvm_mmu_load(&svm->vcpu);
2424
2425         return 0;
2426 }
2427
2428 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2429 {
2430         /*
2431          * This function merges the msr permission bitmaps of kvm and the
2432          * nested vmcb. It is optimized in that it only merges the parts where
2433          * the kvm msr permission bitmap may contain zero bits
2434          */
2435         int i;
2436
2437         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2438                 return true;
2439
2440         for (i = 0; i < MSRPM_OFFSETS; i++) {
2441                 u32 value, p;
2442                 u64 offset;
2443
2444                 if (msrpm_offsets[i] == 0xffffffff)
2445                         break;
2446
2447                 p      = msrpm_offsets[i];
2448                 offset = svm->nested.vmcb_msrpm + (p * 4);
2449
2450                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2451                         return false;
2452
2453                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2454         }
2455
2456         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2457
2458         return true;
2459 }
2460
2461 static bool nested_vmcb_checks(struct vmcb *vmcb)
2462 {
2463         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2464                 return false;
2465
2466         if (vmcb->control.asid == 0)
2467                 return false;
2468
2469         if (vmcb->control.nested_ctl && !npt_enabled)
2470                 return false;
2471
2472         return true;
2473 }
2474
2475 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2476 {
2477         struct vmcb *nested_vmcb;
2478         struct vmcb *hsave = svm->nested.hsave;
2479         struct vmcb *vmcb = svm->vmcb;
2480         struct page *page;
2481         u64 vmcb_gpa;
2482
2483         vmcb_gpa = svm->vmcb->save.rax;
2484
2485         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2486         if (!nested_vmcb)
2487                 return false;
2488
2489         if (!nested_vmcb_checks(nested_vmcb)) {
2490                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2491                 nested_vmcb->control.exit_code_hi = 0;
2492                 nested_vmcb->control.exit_info_1  = 0;
2493                 nested_vmcb->control.exit_info_2  = 0;
2494
2495                 nested_svm_unmap(page);
2496
2497                 return false;
2498         }
2499
2500         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2501                                nested_vmcb->save.rip,
2502                                nested_vmcb->control.int_ctl,
2503                                nested_vmcb->control.event_inj,
2504                                nested_vmcb->control.nested_ctl);
2505
2506         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2507                                     nested_vmcb->control.intercept_cr >> 16,
2508                                     nested_vmcb->control.intercept_exceptions,
2509                                     nested_vmcb->control.intercept);
2510
2511         /* Clear internal status */
2512         kvm_clear_exception_queue(&svm->vcpu);
2513         kvm_clear_interrupt_queue(&svm->vcpu);
2514
2515         /*
2516          * Save the old vmcb, so we don't need to pick what we save, but can
2517          * restore everything when a VMEXIT occurs
2518          */
2519         hsave->save.es     = vmcb->save.es;
2520         hsave->save.cs     = vmcb->save.cs;
2521         hsave->save.ss     = vmcb->save.ss;
2522         hsave->save.ds     = vmcb->save.ds;
2523         hsave->save.gdtr   = vmcb->save.gdtr;
2524         hsave->save.idtr   = vmcb->save.idtr;
2525         hsave->save.efer   = svm->vcpu.arch.efer;
2526         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2527         hsave->save.cr4    = svm->vcpu.arch.cr4;
2528         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2529         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2530         hsave->save.rsp    = vmcb->save.rsp;
2531         hsave->save.rax    = vmcb->save.rax;
2532         if (npt_enabled)
2533                 hsave->save.cr3    = vmcb->save.cr3;
2534         else
2535                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2536
2537         copy_vmcb_control_area(hsave, vmcb);
2538
2539         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2540                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2541         else
2542                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2543
2544         if (nested_vmcb->control.nested_ctl) {
2545                 kvm_mmu_unload(&svm->vcpu);
2546                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2547                 nested_svm_init_mmu_context(&svm->vcpu);
2548         }
2549
2550         /* Load the nested guest state */
2551         svm->vmcb->save.es = nested_vmcb->save.es;
2552         svm->vmcb->save.cs = nested_vmcb->save.cs;
2553         svm->vmcb->save.ss = nested_vmcb->save.ss;
2554         svm->vmcb->save.ds = nested_vmcb->save.ds;
2555         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2556         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2557         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2558         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2559         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2560         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2561         if (npt_enabled) {
2562                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2563                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2564         } else
2565                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2566
2567         /* Guest paging mode is active - reset mmu */
2568         kvm_mmu_reset_context(&svm->vcpu);
2569
2570         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2571         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2572         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2573         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2574
2575         /* In case we don't even reach vcpu_run, the fields are not updated */
2576         svm->vmcb->save.rax = nested_vmcb->save.rax;
2577         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2578         svm->vmcb->save.rip = nested_vmcb->save.rip;
2579         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2580         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2581         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2582
2583         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2584         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2585
2586         /* cache intercepts */
2587         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2588         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2589         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2590         svm->nested.intercept            = nested_vmcb->control.intercept;
2591
2592         svm_flush_tlb(&svm->vcpu);
2593         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2594         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2595                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2596         else
2597                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2598
2599         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2600                 /* We only want the cr8 intercept bits of the guest */
2601                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2602                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2603         }
2604
2605         /* We don't want to see VMMCALLs from a nested guest */
2606         clr_intercept(svm, INTERCEPT_VMMCALL);
2607
2608         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2609         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2610         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2611         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2612         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2613         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2614
2615         nested_svm_unmap(page);
2616
2617         /* Enter Guest-Mode */
2618         enter_guest_mode(&svm->vcpu);
2619
2620         /*
2621          * Merge guest and host intercepts - must be called  with vcpu in
2622          * guest-mode to take affect here
2623          */
2624         recalc_intercepts(svm);
2625
2626         svm->nested.vmcb = vmcb_gpa;
2627
2628         enable_gif(svm);
2629
2630         mark_all_dirty(svm->vmcb);
2631
2632         return true;
2633 }
2634
2635 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2636 {
2637         to_vmcb->save.fs = from_vmcb->save.fs;
2638         to_vmcb->save.gs = from_vmcb->save.gs;
2639         to_vmcb->save.tr = from_vmcb->save.tr;
2640         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2641         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2642         to_vmcb->save.star = from_vmcb->save.star;
2643         to_vmcb->save.lstar = from_vmcb->save.lstar;
2644         to_vmcb->save.cstar = from_vmcb->save.cstar;
2645         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2646         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2647         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2648         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2649 }
2650
2651 static int vmload_interception(struct vcpu_svm *svm)
2652 {
2653         struct vmcb *nested_vmcb;
2654         struct page *page;
2655
2656         if (nested_svm_check_permissions(svm))
2657                 return 1;
2658
2659         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2660         if (!nested_vmcb)
2661                 return 1;
2662
2663         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2664         skip_emulated_instruction(&svm->vcpu);
2665
2666         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2667         nested_svm_unmap(page);
2668
2669         return 1;
2670 }
2671
2672 static int vmsave_interception(struct vcpu_svm *svm)
2673 {
2674         struct vmcb *nested_vmcb;
2675         struct page *page;
2676
2677         if (nested_svm_check_permissions(svm))
2678                 return 1;
2679
2680         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2681         if (!nested_vmcb)
2682                 return 1;
2683
2684         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2685         skip_emulated_instruction(&svm->vcpu);
2686
2687         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2688         nested_svm_unmap(page);
2689
2690         return 1;
2691 }
2692
2693 static int vmrun_interception(struct vcpu_svm *svm)
2694 {
2695         if (nested_svm_check_permissions(svm))
2696                 return 1;
2697
2698         /* Save rip after vmrun instruction */
2699         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2700
2701         if (!nested_svm_vmrun(svm))
2702                 return 1;
2703
2704         if (!nested_svm_vmrun_msrpm(svm))
2705                 goto failed;
2706
2707         return 1;
2708
2709 failed:
2710
2711         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2712         svm->vmcb->control.exit_code_hi = 0;
2713         svm->vmcb->control.exit_info_1  = 0;
2714         svm->vmcb->control.exit_info_2  = 0;
2715
2716         nested_svm_vmexit(svm);
2717
2718         return 1;
2719 }
2720
2721 static int stgi_interception(struct vcpu_svm *svm)
2722 {
2723         if (nested_svm_check_permissions(svm))
2724                 return 1;
2725
2726         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2727         skip_emulated_instruction(&svm->vcpu);
2728         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2729
2730         enable_gif(svm);
2731
2732         return 1;
2733 }
2734
2735 static int clgi_interception(struct vcpu_svm *svm)
2736 {
2737         if (nested_svm_check_permissions(svm))
2738                 return 1;
2739
2740         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2741         skip_emulated_instruction(&svm->vcpu);
2742
2743         disable_gif(svm);
2744
2745         /* After a CLGI no interrupts should come */
2746         svm_clear_vintr(svm);
2747         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2748
2749         mark_dirty(svm->vmcb, VMCB_INTR);
2750
2751         return 1;
2752 }
2753
2754 static int invlpga_interception(struct vcpu_svm *svm)
2755 {
2756         struct kvm_vcpu *vcpu = &svm->vcpu;
2757
2758         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
2759                           kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2760
2761         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2762         kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2763
2764         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2765         skip_emulated_instruction(&svm->vcpu);
2766         return 1;
2767 }
2768
2769 static int skinit_interception(struct vcpu_svm *svm)
2770 {
2771         trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2772
2773         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2774         return 1;
2775 }
2776
2777 static int wbinvd_interception(struct vcpu_svm *svm)
2778 {
2779         kvm_emulate_wbinvd(&svm->vcpu);
2780         return 1;
2781 }
2782
2783 static int xsetbv_interception(struct vcpu_svm *svm)
2784 {
2785         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2786         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2787
2788         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2789                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2790                 skip_emulated_instruction(&svm->vcpu);
2791         }
2792
2793         return 1;
2794 }
2795
2796 static int task_switch_interception(struct vcpu_svm *svm)
2797 {
2798         u16 tss_selector;
2799         int reason;
2800         int int_type = svm->vmcb->control.exit_int_info &
2801                 SVM_EXITINTINFO_TYPE_MASK;
2802         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2803         uint32_t type =
2804                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2805         uint32_t idt_v =
2806                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2807         bool has_error_code = false;
2808         u32 error_code = 0;
2809
2810         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2811
2812         if (svm->vmcb->control.exit_info_2 &
2813             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2814                 reason = TASK_SWITCH_IRET;
2815         else if (svm->vmcb->control.exit_info_2 &
2816                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2817                 reason = TASK_SWITCH_JMP;
2818         else if (idt_v)
2819                 reason = TASK_SWITCH_GATE;
2820         else
2821                 reason = TASK_SWITCH_CALL;
2822
2823         if (reason == TASK_SWITCH_GATE) {
2824                 switch (type) {
2825                 case SVM_EXITINTINFO_TYPE_NMI:
2826                         svm->vcpu.arch.nmi_injected = false;
2827                         break;
2828                 case SVM_EXITINTINFO_TYPE_EXEPT:
2829                         if (svm->vmcb->control.exit_info_2 &
2830                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2831                                 has_error_code = true;
2832                                 error_code =
2833                                         (u32)svm->vmcb->control.exit_info_2;
2834                         }
2835                         kvm_clear_exception_queue(&svm->vcpu);
2836                         break;
2837                 case SVM_EXITINTINFO_TYPE_INTR:
2838                         kvm_clear_interrupt_queue(&svm->vcpu);
2839                         break;
2840                 default:
2841                         break;
2842                 }
2843         }
2844
2845         if (reason != TASK_SWITCH_GATE ||
2846             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2847             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2848              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2849                 skip_emulated_instruction(&svm->vcpu);
2850
2851         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2852                 int_vec = -1;
2853
2854         if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2855                                 has_error_code, error_code) == EMULATE_FAIL) {
2856                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2857                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2858                 svm->vcpu.run->internal.ndata = 0;
2859                 return 0;
2860         }
2861         return 1;
2862 }
2863
2864 static int cpuid_interception(struct vcpu_svm *svm)
2865 {
2866         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2867         kvm_emulate_cpuid(&svm->vcpu);
2868         return 1;
2869 }
2870
2871 static int iret_interception(struct vcpu_svm *svm)
2872 {
2873         ++svm->vcpu.stat.nmi_window_exits;
2874         clr_intercept(svm, INTERCEPT_IRET);
2875         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2876         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2877         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2878         return 1;
2879 }
2880
2881 static int invlpg_interception(struct vcpu_svm *svm)
2882 {
2883         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2884                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2885
2886         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2887         skip_emulated_instruction(&svm->vcpu);
2888         return 1;
2889 }
2890
2891 static int emulate_on_interception(struct vcpu_svm *svm)
2892 {
2893         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2894 }
2895
2896 static int rdpmc_interception(struct vcpu_svm *svm)
2897 {
2898         int err;
2899
2900         if (!static_cpu_has(X86_FEATURE_NRIPS))
2901                 return emulate_on_interception(svm);
2902
2903         err = kvm_rdpmc(&svm->vcpu);
2904         kvm_complete_insn_gp(&svm->vcpu, err);
2905
2906         return 1;
2907 }
2908
2909 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2910                                             unsigned long val)
2911 {
2912         unsigned long cr0 = svm->vcpu.arch.cr0;
2913         bool ret = false;
2914         u64 intercept;
2915
2916         intercept = svm->nested.intercept;
2917
2918         if (!is_guest_mode(&svm->vcpu) ||
2919             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2920                 return false;
2921
2922         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2923         val &= ~SVM_CR0_SELECTIVE_MASK;
2924
2925         if (cr0 ^ val) {
2926                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2927                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2928         }
2929
2930         return ret;
2931 }
2932
2933 #define CR_VALID (1ULL << 63)
2934
2935 static int cr_interception(struct vcpu_svm *svm)
2936 {
2937         int reg, cr;
2938         unsigned long val;
2939         int err;
2940
2941         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2942                 return emulate_on_interception(svm);
2943
2944         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2945                 return emulate_on_interception(svm);
2946
2947         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2948         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2949                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2950         else
2951                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2952
2953         err = 0;
2954         if (cr >= 16) { /* mov to cr */
2955                 cr -= 16;
2956                 val = kvm_register_read(&svm->vcpu, reg);
2957                 switch (cr) {
2958                 case 0:
2959                         if (!check_selective_cr0_intercepted(svm, val))
2960                                 err = kvm_set_cr0(&svm->vcpu, val);
2961                         else
2962                                 return 1;
2963
2964                         break;
2965                 case 3:
2966                         err = kvm_set_cr3(&svm->vcpu, val);
2967                         break;
2968                 case 4:
2969                         err = kvm_set_cr4(&svm->vcpu, val);
2970                         break;
2971                 case 8:
2972                         err = kvm_set_cr8(&svm->vcpu, val);
2973                         break;
2974                 default:
2975                         WARN(1, "unhandled write to CR%d", cr);
2976                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2977                         return 1;
2978                 }
2979         } else { /* mov from cr */
2980                 switch (cr) {
2981                 case 0:
2982                         val = kvm_read_cr0(&svm->vcpu);
2983                         break;
2984                 case 2:
2985                         val = svm->vcpu.arch.cr2;
2986                         break;
2987                 case 3:
2988                         val = kvm_read_cr3(&svm->vcpu);
2989                         break;
2990                 case 4:
2991                         val = kvm_read_cr4(&svm->vcpu);
2992                         break;
2993                 case 8:
2994                         val = kvm_get_cr8(&svm->vcpu);
2995                         break;
2996                 default:
2997                         WARN(1, "unhandled read from CR%d", cr);
2998                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2999                         return 1;
3000                 }
3001                 kvm_register_write(&svm->vcpu, reg, val);
3002         }
3003         kvm_complete_insn_gp(&svm->vcpu, err);
3004
3005         return 1;
3006 }
3007
3008 static int dr_interception(struct vcpu_svm *svm)
3009 {
3010         int reg, dr;
3011         unsigned long val;
3012
3013         if (svm->vcpu.guest_debug == 0) {
3014                 /*
3015                  * No more DR vmexits; force a reload of the debug registers
3016                  * and reenter on this instruction.  The next vmexit will
3017                  * retrieve the full state of the debug registers.
3018                  */
3019                 clr_dr_intercepts(svm);
3020                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3021                 return 1;
3022         }
3023
3024         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3025                 return emulate_on_interception(svm);
3026
3027         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3028         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3029
3030         if (dr >= 16) { /* mov to DRn */
3031                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3032                         return 1;
3033                 val = kvm_register_read(&svm->vcpu, reg);
3034                 kvm_set_dr(&svm->vcpu, dr - 16, val);
3035         } else {
3036                 if (!kvm_require_dr(&svm->vcpu, dr))
3037                         return 1;
3038                 kvm_get_dr(&svm->vcpu, dr, &val);
3039                 kvm_register_write(&svm->vcpu, reg, val);
3040         }
3041
3042         skip_emulated_instruction(&svm->vcpu);
3043
3044         return 1;
3045 }
3046
3047 static int cr8_write_interception(struct vcpu_svm *svm)
3048 {
3049         struct kvm_run *kvm_run = svm->vcpu.run;
3050         int r;
3051
3052         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3053         /* instruction emulation calls kvm_set_cr8() */
3054         r = cr_interception(svm);
3055         if (irqchip_in_kernel(svm->vcpu.kvm))
3056                 return r;
3057         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3058                 return r;
3059         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3060         return 0;
3061 }
3062
3063 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3064 {
3065         struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3066         return vmcb->control.tsc_offset +
3067                 svm_scale_tsc(vcpu, host_tsc);
3068 }
3069
3070 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3071 {
3072         struct vcpu_svm *svm = to_svm(vcpu);
3073
3074         switch (ecx) {
3075         case MSR_IA32_TSC: {
3076                 *data = svm->vmcb->control.tsc_offset +
3077                         svm_scale_tsc(vcpu, native_read_tsc());
3078
3079                 break;
3080         }
3081         case MSR_STAR:
3082                 *data = svm->vmcb->save.star;
3083                 break;
3084 #ifdef CONFIG_X86_64
3085         case MSR_LSTAR:
3086                 *data = svm->vmcb->save.lstar;
3087                 break;
3088         case MSR_CSTAR:
3089                 *data = svm->vmcb->save.cstar;
3090                 break;
3091         case MSR_KERNEL_GS_BASE:
3092                 *data = svm->vmcb->save.kernel_gs_base;
3093                 break;
3094         case MSR_SYSCALL_MASK:
3095                 *data = svm->vmcb->save.sfmask;
3096                 break;
3097 #endif
3098         case MSR_IA32_SYSENTER_CS:
3099                 *data = svm->vmcb->save.sysenter_cs;
3100                 break;
3101         case MSR_IA32_SYSENTER_EIP:
3102                 *data = svm->sysenter_eip;
3103                 break;
3104         case MSR_IA32_SYSENTER_ESP:
3105                 *data = svm->sysenter_esp;
3106                 break;
3107         /*
3108          * Nobody will change the following 5 values in the VMCB so we can
3109          * safely return them on rdmsr. They will always be 0 until LBRV is
3110          * implemented.
3111          */
3112         case MSR_IA32_DEBUGCTLMSR:
3113                 *data = svm->vmcb->save.dbgctl;
3114                 break;
3115         case MSR_IA32_LASTBRANCHFROMIP:
3116                 *data = svm->vmcb->save.br_from;
3117                 break;
3118         case MSR_IA32_LASTBRANCHTOIP:
3119                 *data = svm->vmcb->save.br_to;
3120                 break;
3121         case MSR_IA32_LASTINTFROMIP:
3122                 *data = svm->vmcb->save.last_excp_from;
3123                 break;
3124         case MSR_IA32_LASTINTTOIP:
3125                 *data = svm->vmcb->save.last_excp_to;
3126                 break;
3127         case MSR_VM_HSAVE_PA:
3128                 *data = svm->nested.hsave_msr;
3129                 break;
3130         case MSR_VM_CR:
3131                 *data = svm->nested.vm_cr_msr;
3132                 break;
3133         case MSR_IA32_UCODE_REV:
3134                 *data = 0x01000065;
3135                 break;
3136         default:
3137                 return kvm_get_msr_common(vcpu, ecx, data);
3138         }
3139         return 0;
3140 }
3141
3142 static int rdmsr_interception(struct vcpu_svm *svm)
3143 {
3144         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3145         u64 data;
3146
3147         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3148                 trace_kvm_msr_read_ex(ecx);
3149                 kvm_inject_gp(&svm->vcpu, 0);
3150         } else {
3151                 trace_kvm_msr_read(ecx, data);
3152
3153                 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, data & 0xffffffff);
3154                 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX, data >> 32);
3155                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3156                 skip_emulated_instruction(&svm->vcpu);
3157         }
3158         return 1;
3159 }
3160
3161 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3162 {
3163         struct vcpu_svm *svm = to_svm(vcpu);
3164         int svm_dis, chg_mask;
3165
3166         if (data & ~SVM_VM_CR_VALID_MASK)
3167                 return 1;
3168
3169         chg_mask = SVM_VM_CR_VALID_MASK;
3170
3171         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3172                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3173
3174         svm->nested.vm_cr_msr &= ~chg_mask;
3175         svm->nested.vm_cr_msr |= (data & chg_mask);
3176
3177         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3178
3179         /* check for svm_disable while efer.svme is set */
3180         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3181                 return 1;
3182
3183         return 0;
3184 }
3185
3186 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3187 {
3188         struct vcpu_svm *svm = to_svm(vcpu);
3189
3190         u32 ecx = msr->index;
3191         u64 data = msr->data;
3192         switch (ecx) {
3193         case MSR_IA32_TSC:
3194                 kvm_write_tsc(vcpu, msr);
3195                 break;
3196         case MSR_STAR:
3197                 svm->vmcb->save.star = data;
3198                 break;
3199 #ifdef CONFIG_X86_64
3200         case MSR_LSTAR:
3201                 svm->vmcb->save.lstar = data;
3202                 break;
3203         case MSR_CSTAR:
3204                 svm->vmcb->save.cstar = data;
3205                 break;
3206         case MSR_KERNEL_GS_BASE:
3207                 svm->vmcb->save.kernel_gs_base = data;
3208                 break;
3209         case MSR_SYSCALL_MASK:
3210                 svm->vmcb->save.sfmask = data;
3211                 break;
3212 #endif
3213         case MSR_IA32_SYSENTER_CS:
3214                 svm->vmcb->save.sysenter_cs = data;
3215                 break;
3216         case MSR_IA32_SYSENTER_EIP:
3217                 svm->sysenter_eip = data;
3218                 svm->vmcb->save.sysenter_eip = data;
3219                 break;
3220         case MSR_IA32_SYSENTER_ESP:
3221                 svm->sysenter_esp = data;
3222                 svm->vmcb->save.sysenter_esp = data;
3223                 break;
3224         case MSR_IA32_DEBUGCTLMSR:
3225                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3226                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3227                                     __func__, data);
3228                         break;
3229                 }
3230                 if (data & DEBUGCTL_RESERVED_BITS)
3231                         return 1;
3232
3233                 svm->vmcb->save.dbgctl = data;
3234                 mark_dirty(svm->vmcb, VMCB_LBR);
3235                 if (data & (1ULL<<0))
3236                         svm_enable_lbrv(svm);
3237                 else
3238                         svm_disable_lbrv(svm);
3239                 break;
3240         case MSR_VM_HSAVE_PA:
3241                 svm->nested.hsave_msr = data;
3242                 break;
3243         case MSR_VM_CR:
3244                 return svm_set_vm_cr(vcpu, data);
3245         case MSR_VM_IGNNE:
3246                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3247                 break;
3248         default:
3249                 return kvm_set_msr_common(vcpu, msr);
3250         }
3251         return 0;
3252 }
3253
3254 static int wrmsr_interception(struct vcpu_svm *svm)
3255 {
3256         struct msr_data msr;
3257         u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3258         u64 data = kvm_read_edx_eax(&svm->vcpu);
3259
3260         msr.data = data;
3261         msr.index = ecx;
3262         msr.host_initiated = false;
3263
3264         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3265         if (kvm_set_msr(&svm->vcpu, &msr)) {
3266                 trace_kvm_msr_write_ex(ecx, data);
3267                 kvm_inject_gp(&svm->vcpu, 0);
3268         } else {
3269                 trace_kvm_msr_write(ecx, data);
3270                 skip_emulated_instruction(&svm->vcpu);
3271         }
3272         return 1;
3273 }
3274
3275 static int msr_interception(struct vcpu_svm *svm)
3276 {
3277         if (svm->vmcb->control.exit_info_1)
3278                 return wrmsr_interception(svm);
3279         else
3280                 return rdmsr_interception(svm);
3281 }
3282
3283 static int interrupt_window_interception(struct vcpu_svm *svm)
3284 {
3285         struct kvm_run *kvm_run = svm->vcpu.run;
3286
3287         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3288         svm_clear_vintr(svm);
3289         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3290         mark_dirty(svm->vmcb, VMCB_INTR);
3291         ++svm->vcpu.stat.irq_window_exits;
3292         /*
3293          * If the user space waits to inject interrupts, exit as soon as
3294          * possible
3295          */
3296         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3297             kvm_run->request_interrupt_window &&
3298             !kvm_cpu_has_interrupt(&svm->vcpu)) {
3299                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3300                 return 0;
3301         }
3302
3303         return 1;
3304 }
3305
3306 static int pause_interception(struct vcpu_svm *svm)
3307 {
3308         kvm_vcpu_on_spin(&(svm->vcpu));
3309         return 1;
3310 }
3311
3312 static int nop_interception(struct vcpu_svm *svm)
3313 {
3314         skip_emulated_instruction(&(svm->vcpu));
3315         return 1;
3316 }
3317
3318 static int monitor_interception(struct vcpu_svm *svm)
3319 {
3320         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3321         return nop_interception(svm);
3322 }
3323
3324 static int mwait_interception(struct vcpu_svm *svm)
3325 {
3326         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3327         return nop_interception(svm);
3328 }
3329
3330 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3331         [SVM_EXIT_READ_CR0]                     = cr_interception,
3332         [SVM_EXIT_READ_CR3]                     = cr_interception,
3333         [SVM_EXIT_READ_CR4]                     = cr_interception,
3334         [SVM_EXIT_READ_CR8]                     = cr_interception,
3335         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3336         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3337         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3338         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3339         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3340         [SVM_EXIT_READ_DR0]                     = dr_interception,
3341         [SVM_EXIT_READ_DR1]                     = dr_interception,
3342         [SVM_EXIT_READ_DR2]                     = dr_interception,
3343         [SVM_EXIT_READ_DR3]                     = dr_interception,
3344         [SVM_EXIT_READ_DR4]                     = dr_interception,
3345         [SVM_EXIT_READ_DR5]                     = dr_interception,
3346         [SVM_EXIT_READ_DR6]                     = dr_interception,
3347         [SVM_EXIT_READ_DR7]                     = dr_interception,
3348         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3349         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3350         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3351         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3352         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3353         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3354         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3355         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3356         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3357         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3358         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3359         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3360         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
3361         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3362         [SVM_EXIT_INTR]                         = intr_interception,
3363         [SVM_EXIT_NMI]                          = nmi_interception,
3364         [SVM_EXIT_SMI]                          = nop_on_interception,
3365         [SVM_EXIT_INIT]                         = nop_on_interception,
3366         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3367         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3368         [SVM_EXIT_CPUID]                        = cpuid_interception,
3369         [SVM_EXIT_IRET]                         = iret_interception,
3370         [SVM_EXIT_INVD]                         = emulate_on_interception,
3371         [SVM_EXIT_PAUSE]                        = pause_interception,
3372         [SVM_EXIT_HLT]                          = halt_interception,
3373         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3374         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3375         [SVM_EXIT_IOIO]                         = io_interception,
3376         [SVM_EXIT_MSR]                          = msr_interception,
3377         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3378         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3379         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3380         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3381         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3382         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3383         [SVM_EXIT_STGI]                         = stgi_interception,
3384         [SVM_EXIT_CLGI]                         = clgi_interception,
3385         [SVM_EXIT_SKINIT]                       = skinit_interception,
3386         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
3387         [SVM_EXIT_MONITOR]                      = monitor_interception,
3388         [SVM_EXIT_MWAIT]                        = mwait_interception,
3389         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3390         [SVM_EXIT_NPF]                          = pf_interception,
3391 };
3392
3393 static void dump_vmcb(struct kvm_vcpu *vcpu)
3394 {
3395         struct vcpu_svm *svm = to_svm(vcpu);
3396         struct vmcb_control_area *control = &svm->vmcb->control;
3397         struct vmcb_save_area *save = &svm->vmcb->save;
3398
3399         pr_err("VMCB Control Area:\n");
3400         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3401         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3402         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3403         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3404         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3405         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3406         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3407         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3408         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3409         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3410         pr_err("%-20s%d\n", "asid:", control->asid);
3411         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3412         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3413         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3414         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3415         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3416         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3417         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3418         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3419         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_i