arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28
  29 #include <asm/desc.h>
  30
  31 #include <asm/virtext.h>
  32
  33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 #define IOPM_ALLOC_ORDER 2
  39 #define MSRPM_ALLOC_ORDER 1
  40
  41 #define DR7_GD_MASK (1 << 13)
  42 #define DR6_BD_MASK (1 << 13)
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT  (1 << 0)
  48 #define SVM_FEATURE_LBRV (1 << 1)
  49 #define SVM_FEATURE_SVML (1 << 2)
  50
  51 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  52
  53 /* Turn on to get debugging output*/
  54 /* #define NESTED_DEBUG */
  55
  56 #ifdef NESTED_DEBUG
  57 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  58 #else
  59 #define nsvm_printk(fmt, args...) do {} while(0)
  60 #endif
  61
  62 /* enable NPT for AMD64 and X86 with PAE */
  63 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  64 static bool npt_enabled = true;
  65 #else
  66 static bool npt_enabled = false;
  67 #endif
  68 static int npt = 1;
  69
  70 module_param(npt, int, S_IRUGO);
  71
  72 static void kvm_reput_irq(struct vcpu_svm *svm);
  73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  74
  75 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  76 {
  77         return container_of(vcpu, struct vcpu_svm, vcpu);
  78 }
  79
  80 static unsigned long iopm_base;
  81
  82 struct kvm_ldttss_desc {
  83         u16 limit0;
  84         u16 base0;
  85         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  86         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  87         u32 base3;
  88         u32 zero1;
  89 } __attribute__((packed));
  90
  91 struct svm_cpu_data {
  92         int cpu;
  93
  94         u64 asid_generation;
  95         u32 max_asid;
  96         u32 next_asid;
  97         struct kvm_ldttss_desc *tss_desc;
  98
  99         struct page *save_area;
 100 };
 101
 102 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 103 static uint32_t svm_features;
 104
 105 struct svm_init_data {
 106         int cpu;
 107         int r;
 108 };
 109
 110 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 111
 112 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 113 #define MSRS_RANGE_SIZE 2048
 114 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 115
 116 #define MAX_INST_SIZE 15
 117
 118 static inline u32 svm_has(u32 feat)
 119 {
 120         return svm_features & feat;
 121 }
 122
 123 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 124 {
 125         int word_index = __ffs(vcpu->arch.irq_summary);
 126         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 127         int irq = word_index * BITS_PER_LONG + bit_index;
 128
 129         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 130         if (!vcpu->arch.irq_pending[word_index])
 131                 clear_bit(word_index, &vcpu->arch.irq_summary);
 132         return irq;
 133 }
 134
 135 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 136 {
 137         set_bit(irq, vcpu->arch.irq_pending);
 138         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 139 }
 140
 141 static inline void clgi(void)
 142 {
 143         asm volatile (__ex(SVM_CLGI));
 144 }
 145
 146 static inline void stgi(void)
 147 {
 148         asm volatile (__ex(SVM_STGI));
 149 }
 150
 151 static inline void invlpga(unsigned long addr, u32 asid)
 152 {
 153         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 154 }
 155
 156 static inline unsigned long kvm_read_cr2(void)
 157 {
 158         unsigned long cr2;
 159
 160         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 161         return cr2;
 162 }
 163
 164 static inline void kvm_write_cr2(unsigned long val)
 165 {
 166         asm volatile ("mov %0, %%cr2" :: "r" (val));
 167 }
 168
 169 static inline unsigned long read_dr6(void)
 170 {
 171         unsigned long dr6;
 172
 173         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 174         return dr6;
 175 }
 176
 177 static inline void write_dr6(unsigned long val)
 178 {
 179         asm volatile ("mov %0, %%dr6" :: "r" (val));
 180 }
 181
 182 static inline unsigned long read_dr7(void)
 183 {
 184         unsigned long dr7;
 185
 186         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 187         return dr7;
 188 }
 189
 190 static inline void write_dr7(unsigned long val)
 191 {
 192         asm volatile ("mov %0, %%dr7" :: "r" (val));
 193 }
 194
 195 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 196 {
 197         to_svm(vcpu)->asid_generation--;
 198 }
 199
 200 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 201 {
 202         force_new_asid(vcpu);
 203 }
 204
 205 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 206 {
 207         if (!npt_enabled && !(efer & EFER_LMA))
 208                 efer &= ~EFER_LME;
 209
 210         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 211         vcpu->arch.shadow_efer = efer;
 212 }
 213
 214 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 215                                 bool has_error_code, u32 error_code)
 216 {
 217         struct vcpu_svm *svm = to_svm(vcpu);
 218
 219         svm->vmcb->control.event_inj = nr
 220                 | SVM_EVTINJ_VALID
 221                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 222                 | SVM_EVTINJ_TYPE_EXEPT;
 223         svm->vmcb->control.event_inj_err = error_code;
 224 }
 225
 226 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 227 {
 228         struct vcpu_svm *svm = to_svm(vcpu);
 229
 230         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 231 }
 232
 233 static int is_external_interrupt(u32 info)
 234 {
 235         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 236         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 237 }
 238
 239 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 240 {
 241         struct vcpu_svm *svm = to_svm(vcpu);
 242
 243         if (!svm->next_rip) {
 244                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 245                 return;
 246         }
 247         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 248                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 249                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 250
 251         kvm_rip_write(vcpu, svm->next_rip);
 252         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 253
 254         vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK);
 255 }
 256
 257 static int has_svm(void)
 258 {
 259         const char *msg;
 260
 261         if (!cpu_has_svm(&msg)) {
 262                 printk(KERN_INFO "has_svn: %s\n", msg);
 263                 return 0;
 264         }
 265
 266         return 1;
 267 }
 268
 269 static void svm_hardware_disable(void *garbage)
 270 {
 271         cpu_svm_disable();
 272 }
 273
 274 static void svm_hardware_enable(void *garbage)
 275 {
 276
 277         struct svm_cpu_data *svm_data;
 278         uint64_t efer;
 279         struct desc_ptr gdt_descr;
 280         struct desc_struct *gdt;
 281         int me = raw_smp_processor_id();
 282
 283         if (!has_svm()) {
 284                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 285                 return;
 286         }
 287         svm_data = per_cpu(svm_data, me);
 288
 289         if (!svm_data) {
 290                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 291                        me);
 292                 return;
 293         }
 294
 295         svm_data->asid_generation = 1;
 296         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 297         svm_data->next_asid = svm_data->max_asid + 1;
 298
 299         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 300         gdt = (struct desc_struct *)gdt_descr.address;
 301         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 302
 303         rdmsrl(MSR_EFER, efer);
 304         wrmsrl(MSR_EFER, efer | EFER_SVME);
 305
 306         wrmsrl(MSR_VM_HSAVE_PA,
 307                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 308 }
 309
 310 static void svm_cpu_uninit(int cpu)
 311 {
 312         struct svm_cpu_data *svm_data
 313                 = per_cpu(svm_data, raw_smp_processor_id());
 314
 315         if (!svm_data)
 316                 return;
 317
 318         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 319         __free_page(svm_data->save_area);
 320         kfree(svm_data);
 321 }
 322
 323 static int svm_cpu_init(int cpu)
 324 {
 325         struct svm_cpu_data *svm_data;
 326         int r;
 327
 328         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 329         if (!svm_data)
 330                 return -ENOMEM;
 331         svm_data->cpu = cpu;
 332         svm_data->save_area = alloc_page(GFP_KERNEL);
 333         r = -ENOMEM;
 334         if (!svm_data->save_area)
 335                 goto err_1;
 336
 337         per_cpu(svm_data, cpu) = svm_data;
 338
 339         return 0;
 340
 341 err_1:
 342         kfree(svm_data);
 343         return r;
 344
 345 }
 346
 347 static void set_msr_interception(u32 *msrpm, unsigned msr,
 348                                  int read, int write)
 349 {
 350         int i;
 351
 352         for (i = 0; i < NUM_MSR_MAPS; i++) {
 353                 if (msr >= msrpm_ranges[i] &&
 354                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 355                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 356                                           msrpm_ranges[i]) * 2;
 357
 358                         u32 *base = msrpm + (msr_offset / 32);
 359                         u32 msr_shift = msr_offset % 32;
 360                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 361                         *base = (*base & ~(0x3 << msr_shift)) |
 362                                 (mask << msr_shift);
 363                         return;
 364                 }
 365         }
 366         BUG();
 367 }
 368
 369 static void svm_vcpu_init_msrpm(u32 *msrpm)
 370 {
 371         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 372
 373 #ifdef CONFIG_X86_64
 374         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 375         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 376         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 377         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 378         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 379         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 380 #endif
 381         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 382         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 383         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 384         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 385 }
 386
 387 static void svm_enable_lbrv(struct vcpu_svm *svm)
 388 {
 389         u32 *msrpm = svm->msrpm;
 390
 391         svm->vmcb->control.lbr_ctl = 1;
 392         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 393         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 394         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 395         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 396 }
 397
 398 static void svm_disable_lbrv(struct vcpu_svm *svm)
 399 {
 400         u32 *msrpm = svm->msrpm;
 401
 402         svm->vmcb->control.lbr_ctl = 0;
 403         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 404         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 405         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 406         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 407 }
 408
 409 static __init int svm_hardware_setup(void)
 410 {
 411         int cpu;
 412         struct page *iopm_pages;
 413         void *iopm_va;
 414         int r;
 415
 416         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 417
 418         if (!iopm_pages)
 419                 return -ENOMEM;
 420
 421         iopm_va = page_address(iopm_pages);
 422         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 423         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 424         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 425
 426         if (boot_cpu_has(X86_FEATURE_NX))
 427                 kvm_enable_efer_bits(EFER_NX);
 428
 429         for_each_online_cpu(cpu) {
 430                 r = svm_cpu_init(cpu);
 431                 if (r)
 432                         goto err;
 433         }
 434
 435         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 436
 437         if (!svm_has(SVM_FEATURE_NPT))
 438                 npt_enabled = false;
 439
 440         if (npt_enabled && !npt) {
 441                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 442                 npt_enabled = false;
 443         }
 444
 445         if (npt_enabled) {
 446                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 447                 kvm_enable_tdp();
 448         } else
 449                 kvm_disable_tdp();
 450
 451         return 0;
 452
 453 err:
 454         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 455         iopm_base = 0;
 456         return r;
 457 }
 458
 459 static __exit void svm_hardware_unsetup(void)
 460 {
 461         int cpu;
 462
 463         for_each_online_cpu(cpu)
 464                 svm_cpu_uninit(cpu);
 465
 466         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 467         iopm_base = 0;
 468 }
 469
 470 static void init_seg(struct vmcb_seg *seg)
 471 {
 472         seg->selector = 0;
 473         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 474                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 475         seg->limit = 0xffff;
 476         seg->base = 0;
 477 }
 478
 479 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 480 {
 481         seg->selector = 0;
 482         seg->attrib = SVM_SELECTOR_P_MASK | type;
 483         seg->limit = 0xffff;
 484         seg->base = 0;
 485 }
 486
 487 static void init_vmcb(struct vcpu_svm *svm)
 488 {
 489         struct vmcb_control_area *control = &svm->vmcb->control;
 490         struct vmcb_save_area *save = &svm->vmcb->save;
 491
 492         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 493                                         INTERCEPT_CR3_MASK |
 494                                         INTERCEPT_CR4_MASK;
 495
 496         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 497                                         INTERCEPT_CR3_MASK |
 498                                         INTERCEPT_CR4_MASK |
 499                                         INTERCEPT_CR8_MASK;
 500
 501         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 502                                         INTERCEPT_DR1_MASK |
 503                                         INTERCEPT_DR2_MASK |
 504                                         INTERCEPT_DR3_MASK;
 505
 506         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 507                                         INTERCEPT_DR1_MASK |
 508                                         INTERCEPT_DR2_MASK |
 509                                         INTERCEPT_DR3_MASK |
 510                                         INTERCEPT_DR5_MASK |
 511                                         INTERCEPT_DR7_MASK;
 512
 513         control->intercept_exceptions = (1 << PF_VECTOR) |
 514                                         (1 << UD_VECTOR) |
 515                                         (1 << MC_VECTOR);
 516
 517
 518         control->intercept =    (1ULL << INTERCEPT_INTR) |
 519                                 (1ULL << INTERCEPT_NMI) |
 520                                 (1ULL << INTERCEPT_SMI) |
 521                                 (1ULL << INTERCEPT_CPUID) |
 522                                 (1ULL << INTERCEPT_INVD) |
 523                                 (1ULL << INTERCEPT_HLT) |
 524                                 (1ULL << INTERCEPT_INVLPG) |
 525                                 (1ULL << INTERCEPT_INVLPGA) |
 526                                 (1ULL << INTERCEPT_IOIO_PROT) |
 527                                 (1ULL << INTERCEPT_MSR_PROT) |
 528                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 529                                 (1ULL << INTERCEPT_SHUTDOWN) |
 530                                 (1ULL << INTERCEPT_VMRUN) |
 531                                 (1ULL << INTERCEPT_VMMCALL) |
 532                                 (1ULL << INTERCEPT_VMLOAD) |
 533                                 (1ULL << INTERCEPT_VMSAVE) |
 534                                 (1ULL << INTERCEPT_STGI) |
 535                                 (1ULL << INTERCEPT_CLGI) |
 536                                 (1ULL << INTERCEPT_SKINIT) |
 537                                 (1ULL << INTERCEPT_WBINVD) |
 538                                 (1ULL << INTERCEPT_MONITOR) |
 539                                 (1ULL << INTERCEPT_MWAIT);
 540
 541         control->iopm_base_pa = iopm_base;
 542         control->msrpm_base_pa = __pa(svm->msrpm);
 543         control->tsc_offset = 0;
 544         control->int_ctl = V_INTR_MASKING_MASK;
 545
 546         init_seg(&save->es);
 547         init_seg(&save->ss);
 548         init_seg(&save->ds);
 549         init_seg(&save->fs);
 550         init_seg(&save->gs);
 551
 552         save->cs.selector = 0xf000;
 553         /* Executable/Readable Code Segment */
 554         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 555                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 556         save->cs.limit = 0xffff;
 557         /*
 558          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 559          * be consistent with it.
 560          *
 561          * Replace when we have real mode working for vmx.
 562          */
 563         save->cs.base = 0xf0000;
 564
 565         save->gdtr.limit = 0xffff;
 566         save->idtr.limit = 0xffff;
 567
 568         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 569         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 570
 571         save->efer = EFER_SVME;
 572         save->dr6 = 0xffff0ff0;
 573         save->dr7 = 0x400;
 574         save->rflags = 2;
 575         save->rip = 0x0000fff0;
 576         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 577
 578         /*
 579          * cr0 val on cpu init should be 0x60000010, we enable cpu
 580          * cache by default. the orderly way is to enable cache in bios.
 581          */
 582         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 583         save->cr4 = X86_CR4_PAE;
 584         /* rdx = ?? */
 585
 586         if (npt_enabled) {
 587                 /* Setup VMCB for Nested Paging */
 588                 control->nested_ctl = 1;
 589                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 590                                         (1ULL << INTERCEPT_INVLPG));
 591                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 592                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 593                                                 INTERCEPT_CR3_MASK);
 594                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 595                                                  INTERCEPT_CR3_MASK);
 596                 save->g_pat = 0x0007040600070406ULL;
 597                 /* enable caching because the QEMU Bios doesn't enable it */
 598                 save->cr0 = X86_CR0_ET;
 599                 save->cr3 = 0;
 600                 save->cr4 = 0;
 601         }
 602         force_new_asid(&svm->vcpu);
 603
 604         svm->vcpu.arch.hflags = HF_GIF_MASK;
 605 }
 606
 607 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 608 {
 609         struct vcpu_svm *svm = to_svm(vcpu);
 610
 611         init_vmcb(svm);
 612
 613         if (vcpu->vcpu_id != 0) {
 614                 kvm_rip_write(vcpu, 0);
 615                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 616                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 617         }
 618         vcpu->arch.regs_avail = ~0;
 619         vcpu->arch.regs_dirty = ~0;
 620
 621         return 0;
 622 }
 623
 624 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 625 {
 626         struct vcpu_svm *svm;
 627         struct page *page;
 628         struct page *msrpm_pages;
 629         int err;
 630
 631         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 632         if (!svm) {
 633                 err = -ENOMEM;
 634                 goto out;
 635         }
 636
 637         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 638         if (err)
 639                 goto free_svm;
 640
 641         page = alloc_page(GFP_KERNEL);
 642         if (!page) {
 643                 err = -ENOMEM;
 644                 goto uninit;
 645         }
 646
 647         err = -ENOMEM;
 648         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 649         if (!msrpm_pages)
 650                 goto uninit;
 651         svm->msrpm = page_address(msrpm_pages);
 652         svm_vcpu_init_msrpm(svm->msrpm);
 653
 654         svm->vmcb = page_address(page);
 655         clear_page(svm->vmcb);
 656         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 657         svm->asid_generation = 0;
 658         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 659         init_vmcb(svm);
 660
 661         fx_init(&svm->vcpu);
 662         svm->vcpu.fpu_active = 1;
 663         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 664         if (svm->vcpu.vcpu_id == 0)
 665                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 666
 667         return &svm->vcpu;
 668
 669 uninit:
 670         kvm_vcpu_uninit(&svm->vcpu);
 671 free_svm:
 672         kmem_cache_free(kvm_vcpu_cache, svm);
 673 out:
 674         return ERR_PTR(err);
 675 }
 676
 677 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 678 {
 679         struct vcpu_svm *svm = to_svm(vcpu);
 680
 681         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 682         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 683         kvm_vcpu_uninit(vcpu);
 684         kmem_cache_free(kvm_vcpu_cache, svm);
 685 }
 686
 687 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 688 {
 689         struct vcpu_svm *svm = to_svm(vcpu);
 690         int i;
 691
 692         if (unlikely(cpu != vcpu->cpu)) {
 693                 u64 tsc_this, delta;
 694
 695                 /*
 696                  * Make sure that the guest sees a monotonically
 697                  * increasing TSC.
 698                  */
 699                 rdtscll(tsc_this);
 700                 delta = vcpu->arch.host_tsc - tsc_this;
 701                 svm->vmcb->control.tsc_offset += delta;
 702                 vcpu->cpu = cpu;
 703                 kvm_migrate_timers(vcpu);
 704         }
 705
 706         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 707                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 708 }
 709
 710 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 711 {
 712         struct vcpu_svm *svm = to_svm(vcpu);
 713         int i;
 714
 715         ++vcpu->stat.host_state_reload;
 716         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 717                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 718
 719         rdtscll(vcpu->arch.host_tsc);
 720 }
 721
 722 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 723 {
 724         return to_svm(vcpu)->vmcb->save.rflags;
 725 }
 726
 727 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 728 {
 729         to_svm(vcpu)->vmcb->save.rflags = rflags;
 730 }
 731
 732 static void svm_set_vintr(struct vcpu_svm *svm)
 733 {
 734         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 735 }
 736
 737 static void svm_clear_vintr(struct vcpu_svm *svm)
 738 {
 739         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 740 }
 741
 742 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 743 {
 744         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 745
 746         switch (seg) {
 747         case VCPU_SREG_CS: return &save->cs;
 748         case VCPU_SREG_DS: return &save->ds;
 749         case VCPU_SREG_ES: return &save->es;
 750         case VCPU_SREG_FS: return &save->fs;
 751         case VCPU_SREG_GS: return &save->gs;
 752         case VCPU_SREG_SS: return &save->ss;
 753         case VCPU_SREG_TR: return &save->tr;
 754         case VCPU_SREG_LDTR: return &save->ldtr;
 755         }
 756         BUG();
 757         return NULL;
 758 }
 759
 760 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 761 {
 762         struct vmcb_seg *s = svm_seg(vcpu, seg);
 763
 764         return s->base;
 765 }
 766
 767 static void svm_get_segment(struct kvm_vcpu *vcpu,
 768                             struct kvm_segment *var, int seg)
 769 {
 770         struct vmcb_seg *s = svm_seg(vcpu, seg);
 771
 772         var->base = s->base;
 773         var->limit = s->limit;
 774         var->selector = s->selector;
 775         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 776         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 777         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 778         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 779         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 780         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 781         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 782         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 783
 784         /*
 785          * SVM always stores 0 for the 'G' bit in the CS selector in
 786          * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 787          * Intel's VMENTRY has a check on the 'G' bit.
 788          */
 789         if (seg == VCPU_SREG_CS)
 790                 var->g = s->limit > 0xfffff;
 791
 792         /*
 793          * Work around a bug where the busy flag in the tr selector
 794          * isn't exposed
 795          */
 796         if (seg == VCPU_SREG_TR)
 797                 var->type |= 0x2;
 798
 799         var->unusable = !var->present;
 800 }
 801
 802 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 803 {
 804         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 805
 806         return save->cpl;
 807 }
 808
 809 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 810 {
 811         struct vcpu_svm *svm = to_svm(vcpu);
 812
 813         dt->limit = svm->vmcb->save.idtr.limit;
 814         dt->base = svm->vmcb->save.idtr.base;
 815 }
 816
 817 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 818 {
 819         struct vcpu_svm *svm = to_svm(vcpu);
 820
 821         svm->vmcb->save.idtr.limit = dt->limit;
 822         svm->vmcb->save.idtr.base = dt->base ;
 823 }
 824
 825 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 826 {
 827         struct vcpu_svm *svm = to_svm(vcpu);
 828
 829         dt->limit = svm->vmcb->save.gdtr.limit;
 830         dt->base = svm->vmcb->save.gdtr.base;
 831 }
 832
 833 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 834 {
 835         struct vcpu_svm *svm = to_svm(vcpu);
 836
 837         svm->vmcb->save.gdtr.limit = dt->limit;
 838         svm->vmcb->save.gdtr.base = dt->base ;
 839 }
 840
 841 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 842 {
 843 }
 844
 845 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 846 {
 847         struct vcpu_svm *svm = to_svm(vcpu);
 848
 849 #ifdef CONFIG_X86_64
 850         if (vcpu->arch.shadow_efer & EFER_LME) {
 851                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 852                         vcpu->arch.shadow_efer |= EFER_LMA;
 853                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 854                 }
 855
 856                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 857                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 858                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 859                 }
 860         }
 861 #endif
 862         if (npt_enabled)
 863                 goto set;
 864
 865         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 866                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 867                 vcpu->fpu_active = 1;
 868         }
 869
 870         vcpu->arch.cr0 = cr0;
 871         cr0 |= X86_CR0_PG | X86_CR0_WP;
 872         if (!vcpu->fpu_active) {
 873                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 874                 cr0 |= X86_CR0_TS;
 875         }
 876 set:
 877         /*
 878          * re-enable caching here because the QEMU bios
 879          * does not do it - this results in some delay at
 880          * reboot
 881          */
 882         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 883         svm->vmcb->save.cr0 = cr0;
 884 }
 885
 886 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 887 {
 888         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 889         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 890
 891         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 892                 force_new_asid(vcpu);
 893
 894         vcpu->arch.cr4 = cr4;
 895         if (!npt_enabled)
 896                 cr4 |= X86_CR4_PAE;
 897         cr4 |= host_cr4_mce;
 898         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 899 }
 900
 901 static void svm_set_segment(struct kvm_vcpu *vcpu,
 902                             struct kvm_segment *var, int seg)
 903 {
 904         struct vcpu_svm *svm = to_svm(vcpu);
 905         struct vmcb_seg *s = svm_seg(vcpu, seg);
 906
 907         s->base = var->base;
 908         s->limit = var->limit;
 909         s->selector = var->selector;
 910         if (var->unusable)
 911                 s->attrib = 0;
 912         else {
 913                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 914                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 915                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 916                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 917                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 918                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 919                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 920                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 921         }
 922         if (seg == VCPU_SREG_CS)
 923                 svm->vmcb->save.cpl
 924                         = (svm->vmcb->save.cs.attrib
 925                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 926
 927 }
 928
 929 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 930 {
 931         return -EOPNOTSUPP;
 932 }
 933
 934 static int svm_get_irq(struct kvm_vcpu *vcpu)
 935 {
 936         struct vcpu_svm *svm = to_svm(vcpu);
 937         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 938
 939         if (is_external_interrupt(exit_int_info))
 940                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 941         return -1;
 942 }
 943
 944 static void load_host_msrs(struct kvm_vcpu *vcpu)
 945 {
 946 #ifdef CONFIG_X86_64
 947         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 948 #endif
 949 }
 950
 951 static void save_host_msrs(struct kvm_vcpu *vcpu)
 952 {
 953 #ifdef CONFIG_X86_64
 954         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 955 #endif
 956 }
 957
 958 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 959 {
 960         if (svm_data->next_asid > svm_data->max_asid) {
 961                 ++svm_data->asid_generation;
 962                 svm_data->next_asid = 1;
 963                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 964         }
 965
 966         svm->vcpu.cpu = svm_data->cpu;
 967         svm->asid_generation = svm_data->asid_generation;
 968         svm->vmcb->control.asid = svm_data->next_asid++;
 969 }
 970
 971 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 972 {
 973         unsigned long val = to_svm(vcpu)->db_regs[dr];
 974         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
 975         return val;
 976 }
 977
 978 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 979                        int *exception)
 980 {
 981         struct vcpu_svm *svm = to_svm(vcpu);
 982
 983         *exception = 0;
 984
 985         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 986                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 987                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 988                 *exception = DB_VECTOR;
 989                 return;
 990         }
 991
 992         switch (dr) {
 993         case 0 ... 3:
 994                 svm->db_regs[dr] = value;
 995                 return;
 996         case 4 ... 5:
 997                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 998                         *exception = UD_VECTOR;
 999                         return;
1000                 }
1001         case 7: {
1002                 if (value & ~((1ULL << 32) - 1)) {
1003                         *exception = GP_VECTOR;
1004                         return;
1005                 }
1006                 svm->vmcb->save.dr7 = value;
1007                 return;
1008         }
1009         default:
1010                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1011                        __func__, dr);
1012                 *exception = UD_VECTOR;
1013                 return;
1014         }
1015 }
1016
1017 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1018 {
1019         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1020         struct kvm *kvm = svm->vcpu.kvm;
1021         u64 fault_address;
1022         u32 error_code;
1023         bool event_injection = false;
1024
1025         if (!irqchip_in_kernel(kvm) &&
1026             is_external_interrupt(exit_int_info)) {
1027                 event_injection = true;
1028                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1029         }
1030
1031         fault_address  = svm->vmcb->control.exit_info_2;
1032         error_code = svm->vmcb->control.exit_info_1;
1033
1034         if (!npt_enabled)
1035                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1036                             (u32)fault_address, (u32)(fault_address >> 32),
1037                             handler);
1038         else
1039                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1040                             (u32)fault_address, (u32)(fault_address >> 32),
1041                             handler);
1042         /*
1043          * FIXME: Tis shouldn't be necessary here, but there is a flush
1044          * missing in the MMU code. Until we find this bug, flush the
1045          * complete TLB here on an NPF
1046          */
1047         if (npt_enabled)
1048                 svm_flush_tlb(&svm->vcpu);
1049
1050         if (!npt_enabled && event_injection)
1051                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1052         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1053 }
1054
1055 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1056 {
1057         int er;
1058
1059         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1060         if (er != EMULATE_DONE)
1061                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1062         return 1;
1063 }
1064
1065 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1066 {
1067         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1068         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1069                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1070         svm->vcpu.fpu_active = 1;
1071
1072         return 1;
1073 }
1074
1075 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1076 {
1077         /*
1078          * On an #MC intercept the MCE handler is not called automatically in
1079          * the host. So do it by hand here.
1080          */
1081         asm volatile (
1082                 "int $0x12\n");
1083         /* not sure if we ever come back to this point */
1084
1085         return 1;
1086 }
1087
1088 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1089 {
1090         /*
1091          * VMCB is undefined after a SHUTDOWN intercept
1092          * so reinitialize it.
1093          */
1094         clear_page(svm->vmcb);
1095         init_vmcb(svm);
1096
1097         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1098         return 0;
1099 }
1100
1101 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1102 {
1103         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1104         int size, down, in, string, rep;
1105         unsigned port;
1106
1107         ++svm->vcpu.stat.io_exits;
1108
1109         svm->next_rip = svm->vmcb->control.exit_info_2;
1110
1111         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1112
1113         if (string) {
1114                 if (emulate_instruction(&svm->vcpu,
1115                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1116                         return 0;
1117                 return 1;
1118         }
1119
1120         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1121         port = io_info >> 16;
1122         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1123         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1124         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1125
1126         skip_emulated_instruction(&svm->vcpu);
1127         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1128 }
1129
1130 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1131 {
1132         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1133         return 1;
1134 }
1135
1136 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1137 {
1138         ++svm->vcpu.stat.irq_exits;
1139         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1140         return 1;
1141 }
1142
1143 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1144 {
1145         return 1;
1146 }
1147
1148 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1149 {
1150         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1151         skip_emulated_instruction(&svm->vcpu);
1152         return kvm_emulate_halt(&svm->vcpu);
1153 }
1154
1155 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1156 {
1157         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1158         skip_emulated_instruction(&svm->vcpu);
1159         kvm_emulate_hypercall(&svm->vcpu);
1160         return 1;
1161 }
1162
1163 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1164 {
1165         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1166             || !is_paging(&svm->vcpu)) {
1167                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1168                 return 1;
1169         }
1170
1171         if (svm->vmcb->save.cpl) {
1172                 kvm_inject_gp(&svm->vcpu, 0);
1173                 return 1;
1174         }
1175
1176        return 0;
1177 }
1178
1179 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1180 {
1181         struct page *page;
1182
1183         down_read(&current->mm->mmap_sem);
1184         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1185         up_read(&current->mm->mmap_sem);
1186
1187         if (is_error_page(page)) {
1188                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1189                        __func__, gpa);
1190                 kvm_release_page_clean(page);
1191                 kvm_inject_gp(&svm->vcpu, 0);
1192                 return NULL;
1193         }
1194         return page;
1195 }
1196
1197 static int nested_svm_do(struct vcpu_svm *svm,
1198                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1199                          int (*handler)(struct vcpu_svm *svm,
1200                                         void *arg1,
1201                                         void *arg2,
1202                                         void *opaque))
1203 {
1204         struct page *arg1_page;
1205         struct page *arg2_page = NULL;
1206         void *arg1;
1207         void *arg2 = NULL;
1208         int retval;
1209
1210         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1211         if(arg1_page == NULL)
1212                 return 1;
1213
1214         if (arg2_gpa) {
1215                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1216                 if(arg2_page == NULL) {
1217                         kvm_release_page_clean(arg1_page);
1218                         return 1;
1219                 }
1220         }
1221
1222         arg1 = kmap_atomic(arg1_page, KM_USER0);
1223         if (arg2_gpa)
1224                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1225
1226         retval = handler(svm, arg1, arg2, opaque);
1227
1228         kunmap_atomic(arg1, KM_USER0);
1229         if (arg2_gpa)
1230                 kunmap_atomic(arg2, KM_USER1);
1231
1232         kvm_release_page_dirty(arg1_page);
1233         if (arg2_gpa)
1234                 kvm_release_page_dirty(arg2_page);
1235
1236         return retval;
1237 }
1238
1239 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1240 {
1241         if (nested_svm_check_permissions(svm))
1242                 return 1;
1243
1244         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1245         skip_emulated_instruction(&svm->vcpu);
1246
1247         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1248
1249         return 1;
1250 }
1251
1252 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1253 {
1254         if (nested_svm_check_permissions(svm))
1255                 return 1;
1256
1257         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1258         skip_emulated_instruction(&svm->vcpu);
1259
1260         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1261
1262         /* After a CLGI no interrupts should come */
1263         svm_clear_vintr(svm);
1264         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1265
1266         return 1;
1267 }
1268
1269 static int invalid_op_interception(struct vcpu_svm *svm,
1270                                    struct kvm_run *kvm_run)
1271 {
1272         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1273         return 1;
1274 }
1275
1276 static int task_switch_interception(struct vcpu_svm *svm,
1277                                     struct kvm_run *kvm_run)
1278 {
1279         u16 tss_selector;
1280
1281         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1282         if (svm->vmcb->control.exit_info_2 &
1283             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1284                 return kvm_task_switch(&svm->vcpu, tss_selector,
1285                                        TASK_SWITCH_IRET);
1286         if (svm->vmcb->control.exit_info_2 &
1287             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1288                 return kvm_task_switch(&svm->vcpu, tss_selector,
1289                                        TASK_SWITCH_JMP);
1290         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1291 }
1292
1293 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1294 {
1295         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1296         kvm_emulate_cpuid(&svm->vcpu);
1297         return 1;
1298 }
1299
1300 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1301 {
1302         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1303                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1304         return 1;
1305 }
1306
1307 static int emulate_on_interception(struct vcpu_svm *svm,
1308                                    struct kvm_run *kvm_run)
1309 {
1310         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1311                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1312         return 1;
1313 }
1314
1315 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1316 {
1317         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1318         if (irqchip_in_kernel(svm->vcpu.kvm))
1319                 return 1;
1320         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1321         return 0;
1322 }
1323
1324 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1325 {
1326         struct vcpu_svm *svm = to_svm(vcpu);
1327
1328         switch (ecx) {
1329         case MSR_IA32_TIME_STAMP_COUNTER: {
1330                 u64 tsc;
1331
1332                 rdtscll(tsc);
1333                 *data = svm->vmcb->control.tsc_offset + tsc;
1334                 break;
1335         }
1336         case MSR_K6_STAR:
1337                 *data = svm->vmcb->save.star;
1338                 break;
1339 #ifdef CONFIG_X86_64
1340         case MSR_LSTAR:
1341                 *data = svm->vmcb->save.lstar;
1342                 break;
1343         case MSR_CSTAR:
1344                 *data = svm->vmcb->save.cstar;
1345                 break;
1346         case MSR_KERNEL_GS_BASE:
1347                 *data = svm->vmcb->save.kernel_gs_base;
1348                 break;
1349         case MSR_SYSCALL_MASK:
1350                 *data = svm->vmcb->save.sfmask;
1351                 break;
1352 #endif
1353         case MSR_IA32_SYSENTER_CS:
1354                 *data = svm->vmcb->save.sysenter_cs;
1355                 break;
1356         case MSR_IA32_SYSENTER_EIP:
1357                 *data = svm->vmcb->save.sysenter_eip;
1358                 break;
1359         case MSR_IA32_SYSENTER_ESP:
1360                 *data = svm->vmcb->save.sysenter_esp;
1361                 break;
1362         /* Nobody will change the following 5 values in the VMCB so
1363            we can safely return them on rdmsr. They will always be 0
1364            until LBRV is implemented. */
1365         case MSR_IA32_DEBUGCTLMSR:
1366                 *data = svm->vmcb->save.dbgctl;
1367                 break;
1368         case MSR_IA32_LASTBRANCHFROMIP:
1369                 *data = svm->vmcb->save.br_from;
1370                 break;
1371         case MSR_IA32_LASTBRANCHTOIP:
1372                 *data = svm->vmcb->save.br_to;
1373                 break;
1374         case MSR_IA32_LASTINTFROMIP:
1375                 *data = svm->vmcb->save.last_excp_from;
1376                 break;
1377         case MSR_IA32_LASTINTTOIP:
1378                 *data = svm->vmcb->save.last_excp_to;
1379                 break;
1380         default:
1381                 return kvm_get_msr_common(vcpu, ecx, data);
1382         }
1383         return 0;
1384 }
1385
1386 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1387 {
1388         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1389         u64 data;
1390
1391         if (svm_get_msr(&svm->vcpu, ecx, &data))
1392                 kvm_inject_gp(&svm->vcpu, 0);
1393         else {
1394                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1395                             (u32)(data >> 32), handler);
1396
1397                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1398                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1399                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1400                 skip_emulated_instruction(&svm->vcpu);
1401         }
1402         return 1;
1403 }
1404
1405 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1406 {
1407         struct vcpu_svm *svm = to_svm(vcpu);
1408
1409         switch (ecx) {
1410         case MSR_IA32_TIME_STAMP_COUNTER: {
1411                 u64 tsc;
1412
1413                 rdtscll(tsc);
1414                 svm->vmcb->control.tsc_offset = data - tsc;
1415                 break;
1416         }
1417         case MSR_K6_STAR:
1418                 svm->vmcb->save.star = data;
1419                 break;
1420 #ifdef CONFIG_X86_64
1421         case MSR_LSTAR:
1422                 svm->vmcb->save.lstar = data;
1423                 break;
1424         case MSR_CSTAR:
1425                 svm->vmcb->save.cstar = data;
1426                 break;
1427         case MSR_KERNEL_GS_BASE:
1428                 svm->vmcb->save.kernel_gs_base = data;
1429                 break;
1430         case MSR_SYSCALL_MASK:
1431                 svm->vmcb->save.sfmask = data;
1432                 break;
1433 #endif
1434         case MSR_IA32_SYSENTER_CS:
1435                 svm->vmcb->save.sysenter_cs = data;
1436                 break;
1437         case MSR_IA32_SYSENTER_EIP:
1438                 svm->vmcb->save.sysenter_eip = data;
1439                 break;
1440         case MSR_IA32_SYSENTER_ESP:
1441                 svm->vmcb->save.sysenter_esp = data;
1442                 break;
1443         case MSR_IA32_DEBUGCTLMSR:
1444                 if (!svm_has(SVM_FEATURE_LBRV)) {
1445                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1446                                         __func__, data);
1447                         break;
1448                 }
1449                 if (data & DEBUGCTL_RESERVED_BITS)
1450                         return 1;
1451
1452                 svm->vmcb->save.dbgctl = data;
1453                 if (data & (1ULL<<0))
1454                         svm_enable_lbrv(svm);
1455                 else
1456                         svm_disable_lbrv(svm);
1457                 break;
1458         case MSR_K7_EVNTSEL0:
1459         case MSR_K7_EVNTSEL1:
1460         case MSR_K7_EVNTSEL2:
1461         case MSR_K7_EVNTSEL3:
1462         case MSR_K7_PERFCTR0:
1463         case MSR_K7_PERFCTR1:
1464         case MSR_K7_PERFCTR2:
1465         case MSR_K7_PERFCTR3:
1466                 /*
1467                  * Just discard all writes to the performance counters; this
1468                  * should keep both older linux and windows 64-bit guests
1469                  * happy
1470                  */
1471                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1472
1473                 break;
1474         default:
1475                 return kvm_set_msr_common(vcpu, ecx, data);
1476         }
1477         return 0;
1478 }
1479
1480 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1481 {
1482         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1483         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
1484                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1485
1486         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1487                     handler);
1488
1489         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1490         if (svm_set_msr(&svm->vcpu, ecx, data))
1491                 kvm_inject_gp(&svm->vcpu, 0);
1492         else
1493                 skip_emulated_instruction(&svm->vcpu);
1494         return 1;
1495 }
1496
1497 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1498 {
1499         if (svm->vmcb->control.exit_info_1)
1500                 return wrmsr_interception(svm, kvm_run);
1501         else
1502                 return rdmsr_interception(svm, kvm_run);
1503 }
1504
1505 static int interrupt_window_interception(struct vcpu_svm *svm,
1506                                    struct kvm_run *kvm_run)
1507 {
1508         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1509
1510         svm_clear_vintr(svm);
1511         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1512         /*
1513          * If the user space waits to inject interrupts, exit as soon as
1514          * possible
1515          */
1516         if (kvm_run->request_interrupt_window &&
1517             !svm->vcpu.arch.irq_summary) {
1518                 ++svm->vcpu.stat.irq_window_exits;
1519                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1520                 return 0;
1521         }
1522
1523         return 1;
1524 }
1525
1526 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1527                                       struct kvm_run *kvm_run) = {
1528         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1529         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1530         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1531         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1532         /* for now: */
1533         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1534         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1535         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1536         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1537         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1538         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1539         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1540         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1541         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1542         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1543         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1544         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1545         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1546         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1547         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1548         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1549         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1550         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1551         [SVM_EXIT_INTR]                         = intr_interception,
1552         [SVM_EXIT_NMI]                          = nmi_interception,
1553         [SVM_EXIT_SMI]                          = nop_on_interception,
1554         [SVM_EXIT_INIT]                         = nop_on_interception,
1555         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1556         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1557         [SVM_EXIT_CPUID]                        = cpuid_interception,
1558         [SVM_EXIT_INVD]                         = emulate_on_interception,
1559         [SVM_EXIT_HLT]                          = halt_interception,
1560         [SVM_EXIT_INVLPG]                       = invlpg_interception,
1561         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1562         [SVM_EXIT_IOIO]                         = io_interception,
1563         [SVM_EXIT_MSR]                          = msr_interception,
1564         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1565         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1566         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1567         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1568         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1569         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1570         [SVM_EXIT_STGI]                         = stgi_interception,
1571         [SVM_EXIT_CLGI]                         = clgi_interception,
1572         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1573         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1574         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1575         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1576         [SVM_EXIT_NPF]                          = pf_interception,
1577 };
1578
1579 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1580 {
1581         struct vcpu_svm *svm = to_svm(vcpu);
1582         u32 exit_code = svm->vmcb->control.exit_code;
1583
1584         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1585                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1586
1587         if (npt_enabled) {
1588                 int mmu_reload = 0;
1589                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1590                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1591                         mmu_reload = 1;
1592                 }
1593                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1594                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1595                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1596                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1597                                 kvm_inject_gp(vcpu, 0);
1598                                 return 1;
1599                         }
1600                 }
1601                 if (mmu_reload) {
1602                         kvm_mmu_reset_context(vcpu);
1603                         kvm_mmu_load(vcpu);
1604                 }
1605         }
1606
1607         kvm_reput_irq(svm);
1608
1609         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1610                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1611                 kvm_run->fail_entry.hardware_entry_failure_reason
1612                         = svm->vmcb->control.exit_code;
1613                 return 0;
1614         }
1615
1616         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1617             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1618             exit_code != SVM_EXIT_NPF)
1619                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1620                        "exit_code 0x%x\n",
1621                        __func__, svm->vmcb->control.exit_int_info,
1622                        exit_code);
1623
1624         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1625             || !svm_exit_handlers[exit_code]) {
1626                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1627                 kvm_run->hw.hardware_exit_reason = exit_code;
1628                 return 0;
1629         }
1630
1631         return svm_exit_handlers[exit_code](svm, kvm_run);
1632 }
1633
1634 static void reload_tss(struct kvm_vcpu *vcpu)
1635 {
1636         int cpu = raw_smp_processor_id();
1637
1638         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1639         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1640         load_TR_desc();
1641 }
1642
1643 static void pre_svm_run(struct vcpu_svm *svm)
1644 {
1645         int cpu = raw_smp_processor_id();
1646
1647         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1648
1649         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1650         if (svm->vcpu.cpu != cpu ||
1651             svm->asid_generation != svm_data->asid_generation)
1652                 new_asid(svm, svm_data);
1653 }
1654
1655
1656 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1657 {
1658         struct vmcb_control_area *control;
1659
1660         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1661
1662         ++svm->vcpu.stat.irq_injections;
1663         control = &svm->vmcb->control;
1664         control->int_vector = irq;
1665         control->int_ctl &= ~V_INTR_PRIO_MASK;
1666         control->int_ctl |= V_IRQ_MASK |
1667                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1668 }
1669
1670 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1671 {
1672         struct vcpu_svm *svm = to_svm(vcpu);
1673
1674         svm_inject_irq(svm, irq);
1675 }
1676
1677 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1678 {
1679         struct vcpu_svm *svm = to_svm(vcpu);
1680         struct vmcb *vmcb = svm->vmcb;
1681         int max_irr, tpr;
1682
1683         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1684                 return;
1685
1686         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1687
1688         max_irr = kvm_lapic_find_highest_irr(vcpu);
1689         if (max_irr == -1)
1690                 return;
1691
1692         tpr = kvm_lapic_get_cr8(vcpu) << 4;
1693
1694         if (tpr >= (max_irr & 0xf0))
1695                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1696 }
1697
1698 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1699 {
1700         struct vcpu_svm *svm = to_svm(vcpu);
1701         struct vmcb *vmcb = svm->vmcb;
1702         int intr_vector = -1;
1703
1704         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1705             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1706                 intr_vector = vmcb->control.exit_int_info &
1707                               SVM_EVTINJ_VEC_MASK;
1708                 vmcb->control.exit_int_info = 0;
1709                 svm_inject_irq(svm, intr_vector);
1710                 goto out;
1711         }
1712
1713         if (vmcb->control.int_ctl & V_IRQ_MASK)
1714                 goto out;
1715
1716         if (!kvm_cpu_has_interrupt(vcpu))
1717                 goto out;
1718
1719         if (!(svm->vcpu.arch.hflags & HF_GIF_MASK))
1720                 goto out;
1721
1722         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1723             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1724             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1725                 /* unable to deliver irq, set pending irq */
1726                 svm_set_vintr(svm);
1727                 svm_inject_irq(svm, 0x0);
1728                 goto out;
1729         }
1730         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1731         intr_vector = kvm_cpu_get_interrupt(vcpu);
1732         svm_inject_irq(svm, intr_vector);
1733 out:
1734         update_cr8_intercept(vcpu);
1735 }
1736
1737 static void kvm_reput_irq(struct vcpu_svm *svm)
1738 {
1739         struct vmcb_control_area *control = &svm->vmcb->control;
1740
1741         if ((control->int_ctl & V_IRQ_MASK)
1742             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1743                 control->int_ctl &= ~V_IRQ_MASK;
1744                 push_irq(&svm->vcpu, control->int_vector);
1745         }
1746
1747         svm->vcpu.arch.interrupt_window_open =
1748                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1749                  (svm->vcpu.arch.hflags & HF_GIF_MASK);
1750 }
1751
1752 static void svm_do_inject_vector(struct vcpu_svm *svm)
1753 {
1754         struct kvm_vcpu *vcpu = &svm->vcpu;
1755         int word_index = __ffs(vcpu->arch.irq_summary);
1756         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1757         int irq = word_index * BITS_PER_LONG + bit_index;
1758
1759         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1760         if (!vcpu->arch.irq_pending[word_index])
1761                 clear_bit(word_index, &vcpu->arch.irq_summary);
1762         svm_inject_irq(svm, irq);
1763 }
1764
1765 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1766                                        struct kvm_run *kvm_run)
1767 {
1768         struct vcpu_svm *svm = to_svm(vcpu);
1769         struct vmcb_control_area *control = &svm->vmcb->control;
1770
1771         svm->vcpu.arch.interrupt_window_open =
1772                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1773                  (svm->vmcb->save.rflags & X86_EFLAGS_IF) &&
1774                  (svm->vcpu.arch.hflags & HF_GIF_MASK));
1775
1776         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1777                 /*
1778                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1779                  */
1780                 svm_do_inject_vector(svm);
1781
1782         /*
1783          * Interrupts blocked.  Wait for unblock.
1784          */
1785         if (!svm->vcpu.arch.interrupt_window_open &&
1786             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1787                 svm_set_vintr(svm);
1788         else
1789                 svm_clear_vintr(svm);
1790 }
1791
1792 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1793 {
1794         return 0;
1795 }
1796
1797 static void save_db_regs(unsigned long *db_regs)
1798 {
1799         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1800         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1801         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1802         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1803 }
1804
1805 static void load_db_regs(unsigned long *db_regs)
1806 {
1807         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1808         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1809         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1810         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1811 }
1812
1813 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1814 {
1815         force_new_asid(vcpu);
1816 }
1817
1818 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1819 {
1820 }
1821
1822 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1823 {
1824         struct vcpu_svm *svm = to_svm(vcpu);
1825
1826         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1827                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1828                 kvm_lapic_set_tpr(vcpu, cr8);
1829         }
1830 }
1831
1832 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1833 {
1834         struct vcpu_svm *svm = to_svm(vcpu);
1835         u64 cr8;
1836
1837         if (!irqchip_in_kernel(vcpu->kvm))
1838                 return;
1839
1840         cr8 = kvm_get_cr8(vcpu);
1841         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1842         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1843 }
1844
1845 #ifdef CONFIG_X86_64
1846 #define R "r"
1847 #else
1848 #define R "e"
1849 #endif
1850
1851 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1852 {
1853         struct vcpu_svm *svm = to_svm(vcpu);
1854         u16 fs_selector;
1855         u16 gs_selector;
1856         u16 ldt_selector;
1857
1858         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
1859         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
1860         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
1861
1862         pre_svm_run(svm);
1863
1864         sync_lapic_to_cr8(vcpu);
1865
1866         save_host_msrs(vcpu);
1867         fs_selector = kvm_read_fs();
1868         gs_selector = kvm_read_gs();
1869         ldt_selector = kvm_read_ldt();
1870         svm->host_cr2 = kvm_read_cr2();
1871         svm->host_dr6 = read_dr6();
1872         svm->host_dr7 = read_dr7();
1873         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1874         /* required for live migration with NPT */
1875         if (npt_enabled)
1876                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1877
1878         if (svm->vmcb->save.dr7 & 0xff) {
1879                 write_dr7(0);
1880                 save_db_regs(svm->host_db_regs);
1881                 load_db_regs(svm->db_regs);
1882         }
1883
1884         clgi();
1885
1886         local_irq_enable();
1887
1888         asm volatile (
1889                 "push %%"R"bp; \n\t"
1890                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
1891                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
1892                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
1893                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
1894                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
1895                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
1896 #ifdef CONFIG_X86_64
1897                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1898                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1899                 "mov %c[r10](%[svm]), %%r10 \n\t"
1900                 "mov %c[r11](%[svm]), %%r11 \n\t"
1901                 "mov %c[r12](%[svm]), %%r12 \n\t"
1902                 "mov %c[r13](%[svm]), %%r13 \n\t"
1903                 "mov %c[r14](%[svm]), %%r14 \n\t"
1904                 "mov %c[r15](%[svm]), %%r15 \n\t"
1905 #endif
1906
1907                 /* Enter guest mode */
1908                 "push %%"R"ax \n\t"
1909                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
1910                 __ex(SVM_VMLOAD) "\n\t"
1911                 __ex(SVM_VMRUN) "\n\t"
1912                 __ex(SVM_VMSAVE) "\n\t"
1913                 "pop %%"R"ax \n\t"
1914
1915                 /* Save guest registers, load host registers */
1916                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
1917                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
1918                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
1919                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
1920                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
1921                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
1922 #ifdef CONFIG_X86_64
1923                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1924                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1925                 "mov %%r10, %c[r10](%[svm]) \n\t"
1926                 "mov %%r11, %c[r11](%[svm]) \n\t"
1927                 "mov %%r12, %c[r12](%[svm]) \n\t"
1928                 "mov %%r13, %c[r13](%[svm]) \n\t"
1929                 "mov %%r14, %c[r14](%[svm]) \n\t"
1930                 "mov %%r15, %c[r15](%[svm]) \n\t"
1931 #endif
1932                 "pop %%"R"bp"
1933                 :
1934                 : [svm]"a"(svm),
1935                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1936                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1937                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1938                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1939                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1940                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1941                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1942 #ifdef CONFIG_X86_64
1943                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1944                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1945                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1946                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1947                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1948                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1949                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1950                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1951 #endif
1952                 : "cc", "memory"
1953                 , R"bx", R"cx", R"dx", R"si", R"di"
1954 #ifdef CONFIG_X86_64
1955                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1956 #endif
1957                 );
1958
1959         if ((svm->vmcb->save.dr7 & 0xff))
1960                 load_db_regs(svm->host_db_regs);
1961
1962         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1963         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
1964         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
1965         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
1966
1967         write_dr6(svm->host_dr6);
1968         write_dr7(svm->host_dr7);
1969         kvm_write_cr2(svm->host_cr2);
1970
1971         kvm_load_fs(fs_selector);
1972         kvm_load_gs(gs_selector);
1973         kvm_load_ldt(ldt_selector);
1974         load_host_msrs(vcpu);
1975
1976         reload_tss(vcpu);
1977
1978         local_irq_disable();
1979
1980         stgi();
1981
1982         sync_cr8_to_lapic(vcpu);
1983
1984         svm->next_rip = 0;
1985 }
1986
1987 #undef R
1988
1989 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1990 {
1991         struct vcpu_svm *svm = to_svm(vcpu);
1992
1993         if (npt_enabled) {
1994                 svm->vmcb->control.nested_cr3 = root;
1995                 force_new_asid(vcpu);
1996                 return;
1997         }
1998
1999         svm->vmcb->save.cr3 = root;
2000         force_new_asid(vcpu);
2001
2002         if (vcpu->fpu_active) {
2003                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2004                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2005                 vcpu->fpu_active = 0;
2006         }
2007 }
2008
2009 static int is_disabled(void)
2010 {
2011         u64 vm_cr;
2012
2013         rdmsrl(MSR_VM_CR, vm_cr);
2014         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2015                 return 1;
2016
2017         return 0;
2018 }
2019
2020 static void
2021 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2022 {
2023         /*
2024          * Patch in the VMMCALL instruction:
2025          */
2026         hypercall[0] = 0x0f;
2027         hypercall[1] = 0x01;
2028         hypercall[2] = 0xd9;
2029 }
2030
2031 static void svm_check_processor_compat(void *rtn)
2032 {
2033         *(int *)rtn = 0;
2034 }
2035
2036 static bool svm_cpu_has_accelerated_tpr(void)
2037 {
2038         return false;
2039 }
2040
2041 static int get_npt_level(void)
2042 {
2043 #ifdef CONFIG_X86_64
2044         return PT64_ROOT_LEVEL;
2045 #else
2046         return PT32E_ROOT_LEVEL;
2047 #endif
2048 }
2049
2050 static int svm_get_mt_mask_shift(void)
2051 {
2052         return 0;
2053 }
2054
2055 static struct kvm_x86_ops svm_x86_ops = {
2056         .cpu_has_kvm_support = has_svm,
2057         .disabled_by_bios = is_disabled,
2058         .hardware_setup = svm_hardware_setup,
2059         .hardware_unsetup = svm_hardware_unsetup,
2060         .check_processor_compatibility = svm_check_processor_compat,
2061         .hardware_enable = svm_hardware_enable,
2062         .hardware_disable = svm_hardware_disable,
2063         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2064
2065         .vcpu_create = svm_create_vcpu,
2066         .vcpu_free = svm_free_vcpu,
2067         .vcpu_reset = svm_vcpu_reset,
2068
2069         .prepare_guest_switch = svm_prepare_guest_switch,
2070         .vcpu_load = svm_vcpu_load,
2071         .vcpu_put = svm_vcpu_put,
2072
2073         .set_guest_debug = svm_guest_debug,
2074         .get_msr = svm_get_msr,
2075         .set_msr = svm_set_msr,
2076         .get_segment_base = svm_get_segment_base,
2077         .get_segment = svm_get_segment,
2078         .set_segment = svm_set_segment,
2079         .get_cpl = svm_get_cpl,
2080         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2081         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2082         .set_cr0 = svm_set_cr0,
2083         .set_cr3 = svm_set_cr3,
2084         .set_cr4 = svm_set_cr4,
2085         .set_efer = svm_set_efer,
2086         .get_idt = svm_get_idt,
2087         .set_idt = svm_set_idt,
2088         .get_gdt = svm_get_gdt,
2089         .set_gdt = svm_set_gdt,
2090         .get_dr = svm_get_dr,
2091         .set_dr = svm_set_dr,
2092         .get_rflags = svm_get_rflags,
2093         .set_rflags = svm_set_rflags,
2094
2095         .tlb_flush = svm_flush_tlb,
2096
2097         .run = svm_vcpu_run,
2098         .handle_exit = handle_exit,
2099         .skip_emulated_instruction = skip_emulated_instruction,
2100         .patch_hypercall = svm_patch_hypercall,
2101         .get_irq = svm_get_irq,
2102         .set_irq = svm_set_irq,
2103         .queue_exception = svm_queue_exception,
2104         .exception_injected = svm_exception_injected,
2105         .inject_pending_irq = svm_intr_assist,
2106         .inject_pending_vectors = do_interrupt_requests,
2107
2108         .set_tss_addr = svm_set_tss_addr,
2109         .get_tdp_level = get_npt_level,
2110         .get_mt_mask_shift = svm_get_mt_mask_shift,
2111 };
2112
2113 static int __init svm_init(void)
2114 {
2115         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2116                               THIS_MODULE);
2117 }
2118
2119 static void __exit svm_exit(void)
2120 {
2121         kvm_exit();
2122 }
2123
2124 module_init(svm_init)
2125 module_exit(svm_exit)