2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/moduleparam.h>
33 #include <linux/export.h>
34 #include <linux/swap.h>
35 #include <linux/hugetlb.h>
36 #include <linux/compiler.h>
37 #include <linux/srcu.h>
38 #include <linux/slab.h>
39 #include <linux/sched/signal.h>
40 #include <linux/uaccess.h>
41 #include <linux/hash.h>
42 #include <linux/kern_levels.h>
46 #include <asm/cmpxchg.h>
49 #include <asm/kvm_page_track.h>
53 * When setting this variable to true it enables Two-Dimensional-Paging
54 * where the hardware walks 2 page tables:
55 * 1. the guest-virtual to guest-physical
56 * 2. while doing 1. it walks guest-physical to host-physical
57 * If the hardware supports that we don't need to do shadow paging.
59 bool tdp_enabled = false;
63 AUDIT_POST_PAGE_FAULT,
74 module_param(dbg, bool, 0644);
76 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
77 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
78 #define MMU_WARN_ON(x) WARN_ON(x)
80 #define pgprintk(x...) do { } while (0)
81 #define rmap_printk(x...) do { } while (0)
82 #define MMU_WARN_ON(x) do { } while (0)
85 #define PTE_PREFETCH_NUM 8
87 #define PT_FIRST_AVAIL_BITS_SHIFT 10
88 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
90 #define PT64_LEVEL_BITS 9
92 #define PT64_LEVEL_SHIFT(level) \
93 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
95 #define PT64_INDEX(address, level)\
96 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
99 #define PT32_LEVEL_BITS 10
101 #define PT32_LEVEL_SHIFT(level) \
102 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
104 #define PT32_LVL_OFFSET_MASK(level) \
105 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
106 * PT32_LEVEL_BITS))) - 1))
108 #define PT32_INDEX(address, level)\
109 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
112 #define PT64_BASE_ADDR_MASK __sme_clr((((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)))
113 #define PT64_DIR_BASE_ADDR_MASK \
114 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
115 #define PT64_LVL_ADDR_MASK(level) \
116 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
117 * PT64_LEVEL_BITS))) - 1))
118 #define PT64_LVL_OFFSET_MASK(level) \
119 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
120 * PT64_LEVEL_BITS))) - 1))
122 #define PT32_BASE_ADDR_MASK PAGE_MASK
123 #define PT32_DIR_BASE_ADDR_MASK \
124 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
125 #define PT32_LVL_ADDR_MASK(level) \
126 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT32_LEVEL_BITS))) - 1))
129 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
130 | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
132 #define ACC_EXEC_MASK 1
133 #define ACC_WRITE_MASK PT_WRITABLE_MASK
134 #define ACC_USER_MASK PT_USER_MASK
135 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
137 /* The mask for the R/X bits in EPT PTEs */
138 #define PT64_EPT_READABLE_MASK 0x1ull
139 #define PT64_EPT_EXECUTABLE_MASK 0x4ull
141 #include <trace/events/kvm.h>
143 #define CREATE_TRACE_POINTS
144 #include "mmutrace.h"
146 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
147 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
149 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
151 /* make pte_list_desc fit well in cache line */
152 #define PTE_LIST_EXT 3
155 * Return values of handle_mmio_page_fault and mmu.page_fault:
156 * RET_PF_RETRY: let CPU fault again on the address.
157 * RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
159 * For handle_mmio_page_fault only:
160 * RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
168 struct pte_list_desc {
169 u64 *sptes[PTE_LIST_EXT];
170 struct pte_list_desc *more;
173 struct kvm_shadow_walk_iterator {
181 static const union kvm_mmu_page_role mmu_base_role_mask = {
192 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
193 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
195 shadow_walk_okay(&(_walker)); \
196 shadow_walk_next(&(_walker)))
198 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
199 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
200 shadow_walk_okay(&(_walker)); \
201 shadow_walk_next(&(_walker)))
203 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
204 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
205 shadow_walk_okay(&(_walker)) && \
206 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
207 __shadow_walk_next(&(_walker), spte))
209 static struct kmem_cache *pte_list_desc_cache;
210 static struct kmem_cache *mmu_page_header_cache;
211 static struct percpu_counter kvm_total_used_mmu_pages;
213 static u64 __read_mostly shadow_nx_mask;
214 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
215 static u64 __read_mostly shadow_user_mask;
216 static u64 __read_mostly shadow_accessed_mask;
217 static u64 __read_mostly shadow_dirty_mask;
218 static u64 __read_mostly shadow_mmio_mask;
219 static u64 __read_mostly shadow_mmio_value;
220 static u64 __read_mostly shadow_present_mask;
221 static u64 __read_mostly shadow_me_mask;
224 * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value.
225 * Non-present SPTEs with shadow_acc_track_value set are in place for access
228 static u64 __read_mostly shadow_acc_track_mask;
229 static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK;
232 * The mask/shift to use for saving the original R/X bits when marking the PTE
233 * as not-present for access tracking purposes. We do not save the W bit as the
234 * PTEs being access tracked also need to be dirty tracked, so the W bit will be
235 * restored only when a write is attempted to the page.
237 static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK |
238 PT64_EPT_EXECUTABLE_MASK;
239 static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT;
242 * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order
243 * to guard against L1TF attacks.
245 static u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
248 * The number of high-order 1 bits to use in the mask above.
250 static const u64 shadow_nonpresent_or_rsvd_mask_len = 5;
253 * In some cases, we need to preserve the GFN of a non-present or reserved
254 * SPTE when we usurp the upper five bits of the physical address space to
255 * defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll
256 * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask
257 * left into the reserved bits, i.e. the GFN in the SPTE will be split into
258 * high and low parts. This mask covers the lower bits of the GFN.
260 static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
263 static void mmu_spte_set(u64 *sptep, u64 spte);
264 static union kvm_mmu_page_role
265 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
267 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value)
269 BUG_ON((mmio_mask & mmio_value) != mmio_value);
270 shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK;
271 shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK;
273 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
275 static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
277 return sp->role.ad_disabled;
280 static inline bool spte_ad_enabled(u64 spte)
282 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
283 return !(spte & shadow_acc_track_value);
286 static inline u64 spte_shadow_accessed_mask(u64 spte)
288 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
289 return spte_ad_enabled(spte) ? shadow_accessed_mask : 0;
292 static inline u64 spte_shadow_dirty_mask(u64 spte)
294 MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value);
295 return spte_ad_enabled(spte) ? shadow_dirty_mask : 0;
298 static inline bool is_access_track_spte(u64 spte)
300 return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0;
304 * the low bit of the generation number is always presumed to be zero.
305 * This disables mmio caching during memslot updates. The concept is
306 * similar to a seqcount but instead of retrying the access we just punt
307 * and ignore the cache.
309 * spte bits 3-11 are used as bits 1-9 of the generation number,
310 * the bits 52-61 are used as bits 10-19 of the generation number.
312 #define MMIO_SPTE_GEN_LOW_SHIFT 2
313 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
315 #define MMIO_GEN_SHIFT 20
316 #define MMIO_GEN_LOW_SHIFT 10
317 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
318 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
320 static u64 generation_mmio_spte_mask(unsigned int gen)
324 WARN_ON(gen & ~MMIO_GEN_MASK);
326 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
327 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
331 static unsigned int get_mmio_spte_generation(u64 spte)
335 spte &= ~shadow_mmio_mask;
337 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
338 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
342 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
344 return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
347 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
350 unsigned int gen = kvm_current_mmio_generation(vcpu);
351 u64 mask = generation_mmio_spte_mask(gen);
352 u64 gpa = gfn << PAGE_SHIFT;
354 access &= ACC_WRITE_MASK | ACC_USER_MASK;
355 mask |= shadow_mmio_value | access;
356 mask |= gpa | shadow_nonpresent_or_rsvd_mask;
357 mask |= (gpa & shadow_nonpresent_or_rsvd_mask)
358 << shadow_nonpresent_or_rsvd_mask_len;
360 trace_mark_mmio_spte(sptep, gfn, access, gen);
361 mmu_spte_set(sptep, mask);
364 static bool is_mmio_spte(u64 spte)
366 return (spte & shadow_mmio_mask) == shadow_mmio_value;
369 static gfn_t get_mmio_spte_gfn(u64 spte)
371 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
373 gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len)
374 & shadow_nonpresent_or_rsvd_mask;
376 return gpa >> PAGE_SHIFT;
379 static unsigned get_mmio_spte_access(u64 spte)
381 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
382 return (spte & ~mask) & ~PAGE_MASK;
385 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
386 kvm_pfn_t pfn, unsigned access)
388 if (unlikely(is_noslot_pfn(pfn))) {
389 mark_mmio_spte(vcpu, sptep, gfn, access);
396 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
398 unsigned int kvm_gen, spte_gen;
400 kvm_gen = kvm_current_mmio_generation(vcpu);
401 spte_gen = get_mmio_spte_generation(spte);
403 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
404 return likely(kvm_gen == spte_gen);
408 * Sets the shadow PTE masks used by the MMU.
411 * - Setting either @accessed_mask or @dirty_mask requires setting both
412 * - At least one of @accessed_mask or @acc_track_mask must be set
414 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
415 u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
416 u64 acc_track_mask, u64 me_mask)
418 BUG_ON(!dirty_mask != !accessed_mask);
419 BUG_ON(!accessed_mask && !acc_track_mask);
420 BUG_ON(acc_track_mask & shadow_acc_track_value);
422 shadow_user_mask = user_mask;
423 shadow_accessed_mask = accessed_mask;
424 shadow_dirty_mask = dirty_mask;
425 shadow_nx_mask = nx_mask;
426 shadow_x_mask = x_mask;
427 shadow_present_mask = p_mask;
428 shadow_acc_track_mask = acc_track_mask;
429 shadow_me_mask = me_mask;
431 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
433 static void kvm_mmu_reset_all_pte_masks(void)
437 shadow_user_mask = 0;
438 shadow_accessed_mask = 0;
439 shadow_dirty_mask = 0;
442 shadow_mmio_mask = 0;
443 shadow_present_mask = 0;
444 shadow_acc_track_mask = 0;
447 * If the CPU has 46 or less physical address bits, then set an
448 * appropriate mask to guard against L1TF attacks. Otherwise, it is
449 * assumed that the CPU is not vulnerable to L1TF.
451 low_phys_bits = boot_cpu_data.x86_phys_bits;
452 if (boot_cpu_data.x86_phys_bits <
453 52 - shadow_nonpresent_or_rsvd_mask_len) {
454 shadow_nonpresent_or_rsvd_mask =
455 rsvd_bits(boot_cpu_data.x86_phys_bits -
456 shadow_nonpresent_or_rsvd_mask_len,
457 boot_cpu_data.x86_phys_bits - 1);
458 low_phys_bits -= shadow_nonpresent_or_rsvd_mask_len;
460 shadow_nonpresent_or_rsvd_lower_gfn_mask =
461 GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);
464 static int is_cpuid_PSE36(void)
469 static int is_nx(struct kvm_vcpu *vcpu)
471 return vcpu->arch.efer & EFER_NX;
474 static int is_shadow_present_pte(u64 pte)
476 return (pte != 0) && !is_mmio_spte(pte);
479 static int is_large_pte(u64 pte)
481 return pte & PT_PAGE_SIZE_MASK;
484 static int is_last_spte(u64 pte, int level)
486 if (level == PT_PAGE_TABLE_LEVEL)
488 if (is_large_pte(pte))
493 static bool is_executable_pte(u64 spte)
495 return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
498 static kvm_pfn_t spte_to_pfn(u64 pte)
500 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
503 static gfn_t pse36_gfn_delta(u32 gpte)
505 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
507 return (gpte & PT32_DIR_PSE36_MASK) << shift;
511 static void __set_spte(u64 *sptep, u64 spte)
513 WRITE_ONCE(*sptep, spte);
516 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
518 WRITE_ONCE(*sptep, spte);
521 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
523 return xchg(sptep, spte);
526 static u64 __get_spte_lockless(u64 *sptep)
528 return READ_ONCE(*sptep);
539 static void count_spte_clear(u64 *sptep, u64 spte)
541 struct kvm_mmu_page *sp = page_header(__pa(sptep));
543 if (is_shadow_present_pte(spte))
546 /* Ensure the spte is completely set before we increase the count */
548 sp->clear_spte_count++;
551 static void __set_spte(u64 *sptep, u64 spte)
553 union split_spte *ssptep, sspte;
555 ssptep = (union split_spte *)sptep;
556 sspte = (union split_spte)spte;
558 ssptep->spte_high = sspte.spte_high;
561 * If we map the spte from nonpresent to present, We should store
562 * the high bits firstly, then set present bit, so cpu can not
563 * fetch this spte while we are setting the spte.
567 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
570 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
572 union split_spte *ssptep, sspte;
574 ssptep = (union split_spte *)sptep;
575 sspte = (union split_spte)spte;
577 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
580 * If we map the spte from present to nonpresent, we should clear
581 * present bit firstly to avoid vcpu fetch the old high bits.
585 ssptep->spte_high = sspte.spte_high;
586 count_spte_clear(sptep, spte);
589 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
591 union split_spte *ssptep, sspte, orig;
593 ssptep = (union split_spte *)sptep;
594 sspte = (union split_spte)spte;
596 /* xchg acts as a barrier before the setting of the high bits */
597 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
598 orig.spte_high = ssptep->spte_high;
599 ssptep->spte_high = sspte.spte_high;
600 count_spte_clear(sptep, spte);
606 * The idea using the light way get the spte on x86_32 guest is from
607 * gup_get_pte(arch/x86/mm/gup.c).
609 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
610 * coalesces them and we are running out of the MMU lock. Therefore
611 * we need to protect against in-progress updates of the spte.
613 * Reading the spte while an update is in progress may get the old value
614 * for the high part of the spte. The race is fine for a present->non-present
615 * change (because the high part of the spte is ignored for non-present spte),
616 * but for a present->present change we must reread the spte.
618 * All such changes are done in two steps (present->non-present and
619 * non-present->present), hence it is enough to count the number of
620 * present->non-present updates: if it changed while reading the spte,
621 * we might have hit the race. This is done using clear_spte_count.
623 static u64 __get_spte_lockless(u64 *sptep)
625 struct kvm_mmu_page *sp = page_header(__pa(sptep));
626 union split_spte spte, *orig = (union split_spte *)sptep;
630 count = sp->clear_spte_count;
633 spte.spte_low = orig->spte_low;
636 spte.spte_high = orig->spte_high;
639 if (unlikely(spte.spte_low != orig->spte_low ||
640 count != sp->clear_spte_count))
647 static bool spte_can_locklessly_be_made_writable(u64 spte)
649 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
650 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
653 static bool spte_has_volatile_bits(u64 spte)
655 if (!is_shadow_present_pte(spte))
659 * Always atomically update spte if it can be updated
660 * out of mmu-lock, it can ensure dirty bit is not lost,
661 * also, it can help us to get a stable is_writable_pte()
662 * to ensure tlb flush is not missed.
664 if (spte_can_locklessly_be_made_writable(spte) ||
665 is_access_track_spte(spte))
668 if (spte_ad_enabled(spte)) {
669 if ((spte & shadow_accessed_mask) == 0 ||
670 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
677 static bool is_accessed_spte(u64 spte)
679 u64 accessed_mask = spte_shadow_accessed_mask(spte);
681 return accessed_mask ? spte & accessed_mask
682 : !is_access_track_spte(spte);
685 static bool is_dirty_spte(u64 spte)
687 u64 dirty_mask = spte_shadow_dirty_mask(spte);
689 return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK;
692 /* Rules for using mmu_spte_set:
693 * Set the sptep from nonpresent to present.
694 * Note: the sptep being assigned *must* be either not present
695 * or in a state where the hardware will not attempt to update
698 static void mmu_spte_set(u64 *sptep, u64 new_spte)
700 WARN_ON(is_shadow_present_pte(*sptep));
701 __set_spte(sptep, new_spte);
705 * Update the SPTE (excluding the PFN), but do not track changes in its
706 * accessed/dirty status.
708 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
710 u64 old_spte = *sptep;
712 WARN_ON(!is_shadow_present_pte(new_spte));
714 if (!is_shadow_present_pte(old_spte)) {
715 mmu_spte_set(sptep, new_spte);
719 if (!spte_has_volatile_bits(old_spte))
720 __update_clear_spte_fast(sptep, new_spte);
722 old_spte = __update_clear_spte_slow(sptep, new_spte);
724 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
729 /* Rules for using mmu_spte_update:
730 * Update the state bits, it means the mapped pfn is not changed.
732 * Whenever we overwrite a writable spte with a read-only one we
733 * should flush remote TLBs. Otherwise rmap_write_protect
734 * will find a read-only spte, even though the writable spte
735 * might be cached on a CPU's TLB, the return value indicates this
738 * Returns true if the TLB needs to be flushed
740 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
743 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
745 if (!is_shadow_present_pte(old_spte))
749 * For the spte updated out of mmu-lock is safe, since
750 * we always atomically update it, see the comments in
751 * spte_has_volatile_bits().
753 if (spte_can_locklessly_be_made_writable(old_spte) &&
754 !is_writable_pte(new_spte))
758 * Flush TLB when accessed/dirty states are changed in the page tables,
759 * to guarantee consistency between TLB and page tables.
762 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
764 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
767 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
769 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
776 * Rules for using mmu_spte_clear_track_bits:
777 * It sets the sptep from present to nonpresent, and track the
778 * state bits, it is used to clear the last level sptep.
779 * Returns non-zero if the PTE was previously valid.
781 static int mmu_spte_clear_track_bits(u64 *sptep)
784 u64 old_spte = *sptep;
786 if (!spte_has_volatile_bits(old_spte))
787 __update_clear_spte_fast(sptep, 0ull);
789 old_spte = __update_clear_spte_slow(sptep, 0ull);
791 if (!is_shadow_present_pte(old_spte))
794 pfn = spte_to_pfn(old_spte);
797 * KVM does not hold the refcount of the page used by
798 * kvm mmu, before reclaiming the page, we should
799 * unmap it from mmu first.
801 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
803 if (is_accessed_spte(old_spte))
804 kvm_set_pfn_accessed(pfn);
806 if (is_dirty_spte(old_spte))
807 kvm_set_pfn_dirty(pfn);
813 * Rules for using mmu_spte_clear_no_track:
814 * Directly clear spte without caring the state bits of sptep,
815 * it is used to set the upper level spte.
817 static void mmu_spte_clear_no_track(u64 *sptep)
819 __update_clear_spte_fast(sptep, 0ull);
822 static u64 mmu_spte_get_lockless(u64 *sptep)
824 return __get_spte_lockless(sptep);
827 static u64 mark_spte_for_access_track(u64 spte)
829 if (spte_ad_enabled(spte))
830 return spte & ~shadow_accessed_mask;
832 if (is_access_track_spte(spte))
836 * Making an Access Tracking PTE will result in removal of write access
837 * from the PTE. So, verify that we will be able to restore the write
838 * access in the fast page fault path later on.
840 WARN_ONCE((spte & PT_WRITABLE_MASK) &&
841 !spte_can_locklessly_be_made_writable(spte),
842 "kvm: Writable SPTE is not locklessly dirty-trackable\n");
844 WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask <<
845 shadow_acc_track_saved_bits_shift),
846 "kvm: Access Tracking saved bit locations are not zero\n");
848 spte |= (spte & shadow_acc_track_saved_bits_mask) <<
849 shadow_acc_track_saved_bits_shift;
850 spte &= ~shadow_acc_track_mask;
855 /* Restore an acc-track PTE back to a regular PTE */
856 static u64 restore_acc_track_spte(u64 spte)
859 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
860 & shadow_acc_track_saved_bits_mask;
862 WARN_ON_ONCE(spte_ad_enabled(spte));
863 WARN_ON_ONCE(!is_access_track_spte(spte));
865 new_spte &= ~shadow_acc_track_mask;
866 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
867 shadow_acc_track_saved_bits_shift);
868 new_spte |= saved_bits;
873 /* Returns the Accessed status of the PTE and resets it at the same time. */
874 static bool mmu_spte_age(u64 *sptep)
876 u64 spte = mmu_spte_get_lockless(sptep);
878 if (!is_accessed_spte(spte))
881 if (spte_ad_enabled(spte)) {
882 clear_bit((ffs(shadow_accessed_mask) - 1),
883 (unsigned long *)sptep);
886 * Capture the dirty status of the page, so that it doesn't get
887 * lost when the SPTE is marked for access tracking.
889 if (is_writable_pte(spte))
890 kvm_set_pfn_dirty(spte_to_pfn(spte));
892 spte = mark_spte_for_access_track(spte);
893 mmu_spte_update_no_track(sptep, spte);
899 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
902 * Prevent page table teardown by making any free-er wait during
903 * kvm_flush_remote_tlbs() IPI to all active vcpus.
908 * Make sure a following spte read is not reordered ahead of the write
911 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
914 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
917 * Make sure the write to vcpu->mode is not reordered in front of
918 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
919 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
921 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
925 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
926 struct kmem_cache *base_cache, int min)
930 if (cache->nobjs >= min)
932 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
933 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
936 cache->objects[cache->nobjs++] = obj;
941 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
946 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
947 struct kmem_cache *cache)
950 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
953 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
958 if (cache->nobjs >= min)
960 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
961 page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT);
964 cache->objects[cache->nobjs++] = page;
969 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
972 free_page((unsigned long)mc->objects[--mc->nobjs]);
975 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
979 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
980 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
983 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
986 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
987 mmu_page_header_cache, 4);
992 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
994 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
995 pte_list_desc_cache);
996 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
997 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
998 mmu_page_header_cache);
1001 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
1006 p = mc->objects[--mc->nobjs];
1010 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
1012 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
1015 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
1017 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
1020 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
1022 if (!sp->role.direct)
1023 return sp->gfns[index];
1025 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
1028 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
1030 if (sp->role.direct)
1031 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
1033 sp->gfns[index] = gfn;
1037 * Return the pointer to the large page information for a given gfn,
1038 * handling slots that are not large page aligned.
1040 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
1041 struct kvm_memory_slot *slot,
1046 idx = gfn_to_index(gfn, slot->base_gfn, level);
1047 return &slot->arch.lpage_info[level - 2][idx];
1050 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
1051 gfn_t gfn, int count)
1053 struct kvm_lpage_info *linfo;
1056 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1057 linfo = lpage_info_slot(gfn, slot, i);
1058 linfo->disallow_lpage += count;
1059 WARN_ON(linfo->disallow_lpage < 0);
1063 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1065 update_gfn_disallow_lpage_count(slot, gfn, 1);
1068 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
1070 update_gfn_disallow_lpage_count(slot, gfn, -1);
1073 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1075 struct kvm_memslots *slots;
1076 struct kvm_memory_slot *slot;
1079 kvm->arch.indirect_shadow_pages++;
1081 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1082 slot = __gfn_to_memslot(slots, gfn);
1084 /* the non-leaf shadow pages are keeping readonly. */
1085 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1086 return kvm_slot_page_track_add_page(kvm, slot, gfn,
1087 KVM_PAGE_TRACK_WRITE);
1089 kvm_mmu_gfn_disallow_lpage(slot, gfn);
1092 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
1094 struct kvm_memslots *slots;
1095 struct kvm_memory_slot *slot;
1098 kvm->arch.indirect_shadow_pages--;
1100 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1101 slot = __gfn_to_memslot(slots, gfn);
1102 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
1103 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
1104 KVM_PAGE_TRACK_WRITE);
1106 kvm_mmu_gfn_allow_lpage(slot, gfn);
1109 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
1110 struct kvm_memory_slot *slot)
1112 struct kvm_lpage_info *linfo;
1115 linfo = lpage_info_slot(gfn, slot, level);
1116 return !!linfo->disallow_lpage;
1122 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
1125 struct kvm_memory_slot *slot;
1127 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1128 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
1131 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
1133 unsigned long page_size;
1136 page_size = kvm_host_page_size(kvm, gfn);
1138 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1139 if (page_size >= KVM_HPAGE_SIZE(i))
1148 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
1151 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
1153 if (no_dirty_log && slot->dirty_bitmap)
1159 static struct kvm_memory_slot *
1160 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
1163 struct kvm_memory_slot *slot;
1165 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1166 if (!memslot_valid_for_gpte(slot, no_dirty_log))
1172 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
1173 bool *force_pt_level)
1175 int host_level, level, max_level;
1176 struct kvm_memory_slot *slot;
1178 if (unlikely(*force_pt_level))
1179 return PT_PAGE_TABLE_LEVEL;
1181 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
1182 *force_pt_level = !memslot_valid_for_gpte(slot, true);
1183 if (unlikely(*force_pt_level))
1184 return PT_PAGE_TABLE_LEVEL;
1186 host_level = host_mapping_level(vcpu->kvm, large_gfn);
1188 if (host_level == PT_PAGE_TABLE_LEVEL)
1191 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
1193 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
1194 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
1201 * About rmap_head encoding:
1203 * If the bit zero of rmap_head->val is clear, then it points to the only spte
1204 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
1205 * pte_list_desc containing more mappings.
1209 * Returns the number of pointers in the rmap chain, not counting the new one.
1211 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
1212 struct kvm_rmap_head *rmap_head)
1214 struct pte_list_desc *desc;
1217 if (!rmap_head->val) {
1218 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
1219 rmap_head->val = (unsigned long)spte;
1220 } else if (!(rmap_head->val & 1)) {
1221 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
1222 desc = mmu_alloc_pte_list_desc(vcpu);
1223 desc->sptes[0] = (u64 *)rmap_head->val;
1224 desc->sptes[1] = spte;
1225 rmap_head->val = (unsigned long)desc | 1;
1228 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
1229 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1230 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
1232 count += PTE_LIST_EXT;
1234 if (desc->sptes[PTE_LIST_EXT-1]) {
1235 desc->more = mmu_alloc_pte_list_desc(vcpu);
1238 for (i = 0; desc->sptes[i]; ++i)
1240 desc->sptes[i] = spte;
1246 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
1247 struct pte_list_desc *desc, int i,
1248 struct pte_list_desc *prev_desc)
1252 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
1254 desc->sptes[i] = desc->sptes[j];
1255 desc->sptes[j] = NULL;
1258 if (!prev_desc && !desc->more)
1259 rmap_head->val = (unsigned long)desc->sptes[0];
1262 prev_desc->more = desc->more;
1264 rmap_head->val = (unsigned long)desc->more | 1;
1265 mmu_free_pte_list_desc(desc);
1268 static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
1270 struct pte_list_desc *desc;
1271 struct pte_list_desc *prev_desc;
1274 if (!rmap_head->val) {
1275 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
1277 } else if (!(rmap_head->val & 1)) {
1278 rmap_printk("pte_list_remove: %p 1->0\n", spte);
1279 if ((u64 *)rmap_head->val != spte) {
1280 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
1285 rmap_printk("pte_list_remove: %p many->many\n", spte);
1286 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1289 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1290 if (desc->sptes[i] == spte) {
1291 pte_list_desc_remove_entry(rmap_head,
1292 desc, i, prev_desc);
1299 pr_err("pte_list_remove: %p many->many\n", spte);
1304 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1305 struct kvm_memory_slot *slot)
1309 idx = gfn_to_index(gfn, slot->base_gfn, level);
1310 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1313 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1314 struct kvm_mmu_page *sp)
1316 struct kvm_memslots *slots;
1317 struct kvm_memory_slot *slot;
1319 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1320 slot = __gfn_to_memslot(slots, gfn);
1321 return __gfn_to_rmap(gfn, sp->role.level, slot);
1324 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1326 struct kvm_mmu_memory_cache *cache;
1328 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1329 return mmu_memory_cache_free_objects(cache);
1332 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1334 struct kvm_mmu_page *sp;
1335 struct kvm_rmap_head *rmap_head;
1337 sp = page_header(__pa(spte));
1338 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1339 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1340 return pte_list_add(vcpu, spte, rmap_head);
1343 static void rmap_remove(struct kvm *kvm, u64 *spte)
1345 struct kvm_mmu_page *sp;
1347 struct kvm_rmap_head *rmap_head;
1349 sp = page_header(__pa(spte));
1350 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1351 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1352 pte_list_remove(spte, rmap_head);
1356 * Used by the following functions to iterate through the sptes linked by a
1357 * rmap. All fields are private and not assumed to be used outside.
1359 struct rmap_iterator {
1360 /* private fields */
1361 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1362 int pos; /* index of the sptep */
1366 * Iteration must be started by this function. This should also be used after
1367 * removing/dropping sptes from the rmap link because in such cases the
1368 * information in the itererator may not be valid.
1370 * Returns sptep if found, NULL otherwise.
1372 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1373 struct rmap_iterator *iter)
1377 if (!rmap_head->val)
1380 if (!(rmap_head->val & 1)) {
1382 sptep = (u64 *)rmap_head->val;
1386 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1388 sptep = iter->desc->sptes[iter->pos];
1390 BUG_ON(!is_shadow_present_pte(*sptep));
1395 * Must be used with a valid iterator: e.g. after rmap_get_first().
1397 * Returns sptep if found, NULL otherwise.
1399 static u64 *rmap_get_next(struct rmap_iterator *iter)
1404 if (iter->pos < PTE_LIST_EXT - 1) {
1406 sptep = iter->desc->sptes[iter->pos];
1411 iter->desc = iter->desc->more;
1415 /* desc->sptes[0] cannot be NULL */
1416 sptep = iter->desc->sptes[iter->pos];
1423 BUG_ON(!is_shadow_present_pte(*sptep));
1427 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1428 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1429 _spte_; _spte_ = rmap_get_next(_iter_))
1431 static void drop_spte(struct kvm *kvm, u64 *sptep)
1433 if (mmu_spte_clear_track_bits(sptep))
1434 rmap_remove(kvm, sptep);
1438 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1440 if (is_large_pte(*sptep)) {
1441 WARN_ON(page_header(__pa(sptep))->role.level ==
1442 PT_PAGE_TABLE_LEVEL);
1443 drop_spte(kvm, sptep);
1451 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1453 if (__drop_large_spte(vcpu->kvm, sptep))
1454 kvm_flush_remote_tlbs(vcpu->kvm);
1458 * Write-protect on the specified @sptep, @pt_protect indicates whether
1459 * spte write-protection is caused by protecting shadow page table.
1461 * Note: write protection is difference between dirty logging and spte
1463 * - for dirty logging, the spte can be set to writable at anytime if
1464 * its dirty bitmap is properly set.
1465 * - for spte protection, the spte can be writable only after unsync-ing
1468 * Return true if tlb need be flushed.
1470 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1474 if (!is_writable_pte(spte) &&
1475 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1478 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1481 spte &= ~SPTE_MMU_WRITEABLE;
1482 spte = spte & ~PT_WRITABLE_MASK;
1484 return mmu_spte_update(sptep, spte);
1487 static bool __rmap_write_protect(struct kvm *kvm,
1488 struct kvm_rmap_head *rmap_head,
1492 struct rmap_iterator iter;
1495 for_each_rmap_spte(rmap_head, &iter, sptep)
1496 flush |= spte_write_protect(sptep, pt_protect);
1501 static bool spte_clear_dirty(u64 *sptep)
1505 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1507 spte &= ~shadow_dirty_mask;
1509 return mmu_spte_update(sptep, spte);
1512 static bool wrprot_ad_disabled_spte(u64 *sptep)
1514 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1515 (unsigned long *)sptep);
1517 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1519 return was_writable;
1523 * Gets the GFN ready for another round of dirty logging by clearing the
1524 * - D bit on ad-enabled SPTEs, and
1525 * - W bit on ad-disabled SPTEs.
1526 * Returns true iff any D or W bits were cleared.
1528 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1531 struct rmap_iterator iter;
1534 for_each_rmap_spte(rmap_head, &iter, sptep)
1535 if (spte_ad_enabled(*sptep))
1536 flush |= spte_clear_dirty(sptep);
1538 flush |= wrprot_ad_disabled_spte(sptep);
1543 static bool spte_set_dirty(u64 *sptep)
1547 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1549 spte |= shadow_dirty_mask;
1551 return mmu_spte_update(sptep, spte);
1554 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1557 struct rmap_iterator iter;
1560 for_each_rmap_spte(rmap_head, &iter, sptep)
1561 if (spte_ad_enabled(*sptep))
1562 flush |= spte_set_dirty(sptep);
1568 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1569 * @kvm: kvm instance
1570 * @slot: slot to protect
1571 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1572 * @mask: indicates which pages we should protect
1574 * Used when we do not need to care about huge page mappings: e.g. during dirty
1575 * logging we do not have any such mappings.
1577 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1578 struct kvm_memory_slot *slot,
1579 gfn_t gfn_offset, unsigned long mask)
1581 struct kvm_rmap_head *rmap_head;
1584 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1585 PT_PAGE_TABLE_LEVEL, slot);
1586 __rmap_write_protect(kvm, rmap_head, false);
1588 /* clear the first set bit */
1594 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1595 * protect the page if the D-bit isn't supported.
1596 * @kvm: kvm instance
1597 * @slot: slot to clear D-bit
1598 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1599 * @mask: indicates which pages we should clear D-bit
1601 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1603 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1604 struct kvm_memory_slot *slot,
1605 gfn_t gfn_offset, unsigned long mask)
1607 struct kvm_rmap_head *rmap_head;
1610 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1611 PT_PAGE_TABLE_LEVEL, slot);
1612 __rmap_clear_dirty(kvm, rmap_head);
1614 /* clear the first set bit */
1618 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1621 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1624 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1625 * enable dirty logging for them.
1627 * Used when we do not need to care about huge page mappings: e.g. during dirty
1628 * logging we do not have any such mappings.
1630 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1631 struct kvm_memory_slot *slot,
1632 gfn_t gfn_offset, unsigned long mask)
1634 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1635 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1638 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1642 * kvm_arch_write_log_dirty - emulate dirty page logging
1643 * @vcpu: Guest mode vcpu
1645 * Emulate arch specific page modification logging for the
1648 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu)
1650 if (kvm_x86_ops->write_log_dirty)
1651 return kvm_x86_ops->write_log_dirty(vcpu);
1656 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1657 struct kvm_memory_slot *slot, u64 gfn)
1659 struct kvm_rmap_head *rmap_head;
1661 bool write_protected = false;
1663 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1664 rmap_head = __gfn_to_rmap(gfn, i, slot);
1665 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1668 return write_protected;
1671 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1673 struct kvm_memory_slot *slot;
1675 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1676 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1679 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1682 struct rmap_iterator iter;
1685 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1686 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1688 drop_spte(kvm, sptep);
1695 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1696 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1699 return kvm_zap_rmapp(kvm, rmap_head);
1702 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1703 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1707 struct rmap_iterator iter;
1710 pte_t *ptep = (pte_t *)data;
1713 WARN_ON(pte_huge(*ptep));
1714 new_pfn = pte_pfn(*ptep);
1717 for_each_rmap_spte(rmap_head, &iter, sptep) {
1718 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1719 sptep, *sptep, gfn, level);
1723 if (pte_write(*ptep)) {
1724 drop_spte(kvm, sptep);
1727 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1728 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1730 new_spte &= ~PT_WRITABLE_MASK;
1731 new_spte &= ~SPTE_HOST_WRITEABLE;
1733 new_spte = mark_spte_for_access_track(new_spte);
1735 mmu_spte_clear_track_bits(sptep);
1736 mmu_spte_set(sptep, new_spte);
1741 kvm_flush_remote_tlbs(kvm);
1746 struct slot_rmap_walk_iterator {
1748 struct kvm_memory_slot *slot;
1754 /* output fields. */
1756 struct kvm_rmap_head *rmap;
1759 /* private field. */
1760 struct kvm_rmap_head *end_rmap;
1764 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1766 iterator->level = level;
1767 iterator->gfn = iterator->start_gfn;
1768 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1769 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1774 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1775 struct kvm_memory_slot *slot, int start_level,
1776 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1778 iterator->slot = slot;
1779 iterator->start_level = start_level;
1780 iterator->end_level = end_level;
1781 iterator->start_gfn = start_gfn;
1782 iterator->end_gfn = end_gfn;
1784 rmap_walk_init_level(iterator, iterator->start_level);
1787 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1789 return !!iterator->rmap;
1792 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1794 if (++iterator->rmap <= iterator->end_rmap) {
1795 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1799 if (++iterator->level > iterator->end_level) {
1800 iterator->rmap = NULL;
1804 rmap_walk_init_level(iterator, iterator->level);
1807 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1808 _start_gfn, _end_gfn, _iter_) \
1809 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1810 _end_level_, _start_gfn, _end_gfn); \
1811 slot_rmap_walk_okay(_iter_); \
1812 slot_rmap_walk_next(_iter_))
1814 static int kvm_handle_hva_range(struct kvm *kvm,
1815 unsigned long start,
1818 int (*handler)(struct kvm *kvm,
1819 struct kvm_rmap_head *rmap_head,
1820 struct kvm_memory_slot *slot,
1823 unsigned long data))
1825 struct kvm_memslots *slots;
1826 struct kvm_memory_slot *memslot;
1827 struct slot_rmap_walk_iterator iterator;
1831 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1832 slots = __kvm_memslots(kvm, i);
1833 kvm_for_each_memslot(memslot, slots) {
1834 unsigned long hva_start, hva_end;
1835 gfn_t gfn_start, gfn_end;
1837 hva_start = max(start, memslot->userspace_addr);
1838 hva_end = min(end, memslot->userspace_addr +
1839 (memslot->npages << PAGE_SHIFT));
1840 if (hva_start >= hva_end)
1843 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1844 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1846 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1847 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1849 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1850 PT_MAX_HUGEPAGE_LEVEL,
1851 gfn_start, gfn_end - 1,
1853 ret |= handler(kvm, iterator.rmap, memslot,
1854 iterator.gfn, iterator.level, data);
1861 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1863 int (*handler)(struct kvm *kvm,
1864 struct kvm_rmap_head *rmap_head,
1865 struct kvm_memory_slot *slot,
1866 gfn_t gfn, int level,
1867 unsigned long data))
1869 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1872 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1874 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1877 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1879 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1882 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1883 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1887 struct rmap_iterator uninitialized_var(iter);
1890 for_each_rmap_spte(rmap_head, &iter, sptep)
1891 young |= mmu_spte_age(sptep);
1893 trace_kvm_age_page(gfn, level, slot, young);
1897 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1898 struct kvm_memory_slot *slot, gfn_t gfn,
1899 int level, unsigned long data)
1902 struct rmap_iterator iter;
1904 for_each_rmap_spte(rmap_head, &iter, sptep)
1905 if (is_accessed_spte(*sptep))
1910 #define RMAP_RECYCLE_THRESHOLD 1000
1912 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1914 struct kvm_rmap_head *rmap_head;
1915 struct kvm_mmu_page *sp;
1917 sp = page_header(__pa(spte));
1919 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1921 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1922 kvm_flush_remote_tlbs(vcpu->kvm);
1925 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1927 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1930 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1932 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1936 static int is_empty_shadow_page(u64 *spt)
1941 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1942 if (is_shadow_present_pte(*pos)) {
1943 printk(KERN_ERR "%s: %p %llx\n", __func__,
1952 * This value is the sum of all of the kvm instances's
1953 * kvm->arch.n_used_mmu_pages values. We need a global,
1954 * aggregate version in order to make the slab shrinker
1957 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1959 kvm->arch.n_used_mmu_pages += nr;
1960 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1963 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1965 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1966 hlist_del(&sp->hash_link);
1967 list_del(&sp->link);
1968 free_page((unsigned long)sp->spt);
1969 if (!sp->role.direct)
1970 free_page((unsigned long)sp->gfns);
1971 kmem_cache_free(mmu_page_header_cache, sp);
1974 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1976 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1979 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1980 struct kvm_mmu_page *sp, u64 *parent_pte)
1985 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1988 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1991 pte_list_remove(parent_pte, &sp->parent_ptes);
1994 static void drop_parent_pte(struct kvm_mmu_page *sp,
1997 mmu_page_remove_parent_pte(sp, parent_pte);
1998 mmu_spte_clear_no_track(parent_pte);
2001 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
2003 struct kvm_mmu_page *sp;
2005 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
2006 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2008 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
2009 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
2012 * The active_mmu_pages list is the FIFO list, do not move the
2013 * page until it is zapped. kvm_zap_obsolete_pages depends on
2014 * this feature. See the comments in kvm_zap_obsolete_pages().
2016 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
2017 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
2021 static void mark_unsync(u64 *spte);
2022 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
2025 struct rmap_iterator iter;
2027 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
2032 static void mark_unsync(u64 *spte)
2034 struct kvm_mmu_page *sp;
2037 sp = page_header(__pa(spte));
2038 index = spte - sp->spt;
2039 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
2041 if (sp->unsync_children++)
2043 kvm_mmu_mark_parents_unsync(sp);
2046 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
2047 struct kvm_mmu_page *sp)
2052 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root)
2056 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
2057 struct kvm_mmu_page *sp, u64 *spte,
2063 #define KVM_PAGE_ARRAY_NR 16
2065 struct kvm_mmu_pages {
2066 struct mmu_page_and_offset {
2067 struct kvm_mmu_page *sp;
2069 } page[KVM_PAGE_ARRAY_NR];
2073 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
2079 for (i=0; i < pvec->nr; i++)
2080 if (pvec->page[i].sp == sp)
2083 pvec->page[pvec->nr].sp = sp;
2084 pvec->page[pvec->nr].idx = idx;
2086 return (pvec->nr == KVM_PAGE_ARRAY_NR);
2089 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
2091 --sp->unsync_children;
2092 WARN_ON((int)sp->unsync_children < 0);
2093 __clear_bit(idx, sp->unsync_child_bitmap);
2096 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
2097 struct kvm_mmu_pages *pvec)
2099 int i, ret, nr_unsync_leaf = 0;
2101 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
2102 struct kvm_mmu_page *child;
2103 u64 ent = sp->spt[i];
2105 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
2106 clear_unsync_child_bit(sp, i);
2110 child = page_header(ent & PT64_BASE_ADDR_MASK);
2112 if (child->unsync_children) {
2113 if (mmu_pages_add(pvec, child, i))
2116 ret = __mmu_unsync_walk(child, pvec);
2118 clear_unsync_child_bit(sp, i);
2120 } else if (ret > 0) {
2121 nr_unsync_leaf += ret;
2124 } else if (child->unsync) {
2126 if (mmu_pages_add(pvec, child, i))
2129 clear_unsync_child_bit(sp, i);
2132 return nr_unsync_leaf;
2135 #define INVALID_INDEX (-1)
2137 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
2138 struct kvm_mmu_pages *pvec)
2141 if (!sp->unsync_children)
2144 mmu_pages_add(pvec, sp, INVALID_INDEX);
2145 return __mmu_unsync_walk(sp, pvec);
2148 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
2150 WARN_ON(!sp->unsync);
2151 trace_kvm_mmu_sync_page(sp);
2153 --kvm->stat.mmu_unsync;
2156 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2157 struct list_head *invalid_list);
2158 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2159 struct list_head *invalid_list);
2162 * NOTE: we should pay more attention on the zapped-obsolete page
2163 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
2164 * since it has been deleted from active_mmu_pages but still can be found
2167 * for_each_valid_sp() has skipped that kind of pages.
2169 #define for_each_valid_sp(_kvm, _sp, _gfn) \
2170 hlist_for_each_entry(_sp, \
2171 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
2172 if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \
2175 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
2176 for_each_valid_sp(_kvm, _sp, _gfn) \
2177 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
2179 /* @sp->gfn should be write-protected at the call site */
2180 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2181 struct list_head *invalid_list)
2183 if (sp->role.cr4_pae != !!is_pae(vcpu)
2184 || vcpu->arch.mmu.sync_page(vcpu, sp) == 0) {
2185 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
2192 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
2193 struct list_head *invalid_list,
2194 bool remote_flush, bool local_flush)
2196 if (!list_empty(invalid_list)) {
2197 kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list);
2202 kvm_flush_remote_tlbs(vcpu->kvm);
2203 else if (local_flush)
2204 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2207 #ifdef CONFIG_KVM_MMU_AUDIT
2208 #include "mmu_audit.c"
2210 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
2211 static void mmu_audit_disable(void) { }
2214 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2216 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2219 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2220 struct list_head *invalid_list)
2222 kvm_unlink_unsync_page(vcpu->kvm, sp);
2223 return __kvm_sync_page(vcpu, sp, invalid_list);
2226 /* @gfn should be write-protected at the call site */
2227 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
2228 struct list_head *invalid_list)
2230 struct kvm_mmu_page *s;
2233 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2237 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2238 ret |= kvm_sync_page(vcpu, s, invalid_list);
2244 struct mmu_page_path {
2245 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
2246 unsigned int idx[PT64_ROOT_MAX_LEVEL];
2249 #define for_each_sp(pvec, sp, parents, i) \
2250 for (i = mmu_pages_first(&pvec, &parents); \
2251 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
2252 i = mmu_pages_next(&pvec, &parents, i))
2254 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
2255 struct mmu_page_path *parents,
2260 for (n = i+1; n < pvec->nr; n++) {
2261 struct kvm_mmu_page *sp = pvec->page[n].sp;
2262 unsigned idx = pvec->page[n].idx;
2263 int level = sp->role.level;
2265 parents->idx[level-1] = idx;
2266 if (level == PT_PAGE_TABLE_LEVEL)
2269 parents->parent[level-2] = sp;
2275 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
2276 struct mmu_page_path *parents)
2278 struct kvm_mmu_page *sp;
2284 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
2286 sp = pvec->page[0].sp;
2287 level = sp->role.level;
2288 WARN_ON(level == PT_PAGE_TABLE_LEVEL);
2290 parents->parent[level-2] = sp;
2292 /* Also set up a sentinel. Further entries in pvec are all
2293 * children of sp, so this element is never overwritten.
2295 parents->parent[level-1] = NULL;
2296 return mmu_pages_next(pvec, parents, 0);
2299 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2301 struct kvm_mmu_page *sp;
2302 unsigned int level = 0;
2305 unsigned int idx = parents->idx[level];
2306 sp = parents->parent[level];
2310 WARN_ON(idx == INVALID_INDEX);
2311 clear_unsync_child_bit(sp, idx);
2313 } while (!sp->unsync_children);
2316 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2317 struct kvm_mmu_page *parent)
2320 struct kvm_mmu_page *sp;
2321 struct mmu_page_path parents;
2322 struct kvm_mmu_pages pages;
2323 LIST_HEAD(invalid_list);
2326 while (mmu_unsync_walk(parent, &pages)) {
2327 bool protected = false;
2329 for_each_sp(pages, sp, parents, i)
2330 protected |= rmap_write_protect(vcpu, sp->gfn);
2333 kvm_flush_remote_tlbs(vcpu->kvm);
2337 for_each_sp(pages, sp, parents, i) {
2338 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
2339 mmu_pages_clear_parents(&parents);
2341 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
2342 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2343 cond_resched_lock(&vcpu->kvm->mmu_lock);
2348 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2351 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2353 atomic_set(&sp->write_flooding_count, 0);
2356 static void clear_sp_write_flooding_count(u64 *spte)
2358 struct kvm_mmu_page *sp = page_header(__pa(spte));
2360 __clear_sp_write_flooding_count(sp);
2363 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2370 union kvm_mmu_page_role role;
2372 struct kvm_mmu_page *sp;
2373 bool need_sync = false;
2376 LIST_HEAD(invalid_list);
2378 role = vcpu->arch.mmu.base_role;
2380 role.direct = direct;
2383 role.access = access;
2384 if (!vcpu->arch.mmu.direct_map
2385 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2386 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2387 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2388 role.quadrant = quadrant;
2390 for_each_valid_sp(vcpu->kvm, sp, gfn) {
2391 if (sp->gfn != gfn) {
2396 if (!need_sync && sp->unsync)
2399 if (sp->role.word != role.word)
2403 /* The page is good, but __kvm_sync_page might still end
2404 * up zapping it. If so, break in order to rebuild it.
2406 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2409 WARN_ON(!list_empty(&invalid_list));
2410 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2413 if (sp->unsync_children)
2414 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2416 __clear_sp_write_flooding_count(sp);
2417 trace_kvm_mmu_get_page(sp, false);
2421 ++vcpu->kvm->stat.mmu_cache_miss;
2423 sp = kvm_mmu_alloc_page(vcpu, direct);
2427 hlist_add_head(&sp->hash_link,
2428 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2431 * we should do write protection before syncing pages
2432 * otherwise the content of the synced shadow page may
2433 * be inconsistent with guest page table.
2435 account_shadowed(vcpu->kvm, sp);
2436 if (level == PT_PAGE_TABLE_LEVEL &&
2437 rmap_write_protect(vcpu, gfn))
2438 kvm_flush_remote_tlbs(vcpu->kvm);
2440 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2441 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2443 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2444 clear_page(sp->spt);
2445 trace_kvm_mmu_get_page(sp, true);
2447 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2449 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2450 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2454 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2455 struct kvm_vcpu *vcpu, hpa_t root,
2458 iterator->addr = addr;
2459 iterator->shadow_addr = root;
2460 iterator->level = vcpu->arch.mmu.shadow_root_level;
2462 if (iterator->level == PT64_ROOT_4LEVEL &&
2463 vcpu->arch.mmu.root_level < PT64_ROOT_4LEVEL &&
2464 !vcpu->arch.mmu.direct_map)
2467 if (iterator->level == PT32E_ROOT_LEVEL) {
2469 * prev_root is currently only used for 64-bit hosts. So only
2470 * the active root_hpa is valid here.
2472 BUG_ON(root != vcpu->arch.mmu.root_hpa);
2474 iterator->shadow_addr
2475 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2476 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2478 if (!iterator->shadow_addr)
2479 iterator->level = 0;
2483 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2484 struct kvm_vcpu *vcpu, u64 addr)
2486 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu.root_hpa,
2490 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2492 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2495 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2496 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2500 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2503 if (is_last_spte(spte, iterator->level)) {
2504 iterator->level = 0;
2508 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2512 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2514 __shadow_walk_next(iterator, *iterator->sptep);
2517 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2518 struct kvm_mmu_page *sp)
2522 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2524 spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK |
2525 shadow_user_mask | shadow_x_mask | shadow_me_mask;
2527 if (sp_ad_disabled(sp))
2528 spte |= shadow_acc_track_value;
2530 spte |= shadow_accessed_mask;
2532 mmu_spte_set(sptep, spte);
2534 mmu_page_add_parent_pte(vcpu, sp, sptep);
2536 if (sp->unsync_children || sp->unsync)
2540 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2541 unsigned direct_access)
2543 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2544 struct kvm_mmu_page *child;
2547 * For the direct sp, if the guest pte's dirty bit
2548 * changed form clean to dirty, it will corrupt the
2549 * sp's access: allow writable in the read-only sp,
2550 * so we should update the spte at this point to get
2551 * a new sp with the correct access.
2553 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2554 if (child->role.access == direct_access)
2557 drop_parent_pte(child, sptep);
2558 kvm_flush_remote_tlbs(vcpu->kvm);
2562 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2566 struct kvm_mmu_page *child;
2569 if (is_shadow_present_pte(pte)) {
2570 if (is_last_spte(pte, sp->role.level)) {
2571 drop_spte(kvm, spte);
2572 if (is_large_pte(pte))
2575 child = page_header(pte & PT64_BASE_ADDR_MASK);
2576 drop_parent_pte(child, spte);
2581 if (is_mmio_spte(pte))
2582 mmu_spte_clear_no_track(spte);
2587 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2588 struct kvm_mmu_page *sp)
2592 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2593 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2596 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2599 struct rmap_iterator iter;
2601 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2602 drop_parent_pte(sp, sptep);
2605 static int mmu_zap_unsync_children(struct kvm *kvm,
2606 struct kvm_mmu_page *parent,
2607 struct list_head *invalid_list)
2610 struct mmu_page_path parents;
2611 struct kvm_mmu_pages pages;
2613 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2616 while (mmu_unsync_walk(parent, &pages)) {
2617 struct kvm_mmu_page *sp;
2619 for_each_sp(pages, sp, parents, i) {
2620 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2621 mmu_pages_clear_parents(&parents);
2629 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2630 struct list_head *invalid_list)
2634 trace_kvm_mmu_prepare_zap_page(sp);
2635 ++kvm->stat.mmu_shadow_zapped;
2636 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2637 kvm_mmu_page_unlink_children(kvm, sp);
2638 kvm_mmu_unlink_parents(kvm, sp);
2640 if (!sp->role.invalid && !sp->role.direct)
2641 unaccount_shadowed(kvm, sp);
2644 kvm_unlink_unsync_page(kvm, sp);
2645 if (!sp->root_count) {
2648 list_move(&sp->link, invalid_list);
2649 kvm_mod_used_mmu_pages(kvm, -1);
2651 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2654 * The obsolete pages can not be used on any vcpus.
2655 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2657 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2658 kvm_reload_remote_mmus(kvm);
2661 sp->role.invalid = 1;
2665 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2666 struct list_head *invalid_list)
2668 struct kvm_mmu_page *sp, *nsp;
2670 if (list_empty(invalid_list))
2674 * We need to make sure everyone sees our modifications to
2675 * the page tables and see changes to vcpu->mode here. The barrier
2676 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2677 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2679 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2680 * guest mode and/or lockless shadow page table walks.
2682 kvm_flush_remote_tlbs(kvm);
2684 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2685 WARN_ON(!sp->role.invalid || sp->root_count);
2686 kvm_mmu_free_page(sp);
2690 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2691 struct list_head *invalid_list)
2693 struct kvm_mmu_page *sp;
2695 if (list_empty(&kvm->arch.active_mmu_pages))
2698 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2699 struct kvm_mmu_page, link);
2700 return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2704 * Changing the number of mmu pages allocated to the vm
2705 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2707 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2709 LIST_HEAD(invalid_list);
2711 spin_lock(&kvm->mmu_lock);
2713 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2714 /* Need to free some mmu pages to achieve the goal. */
2715 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2716 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2719 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2720 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2723 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2725 spin_unlock(&kvm->mmu_lock);
2728 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2730 struct kvm_mmu_page *sp;
2731 LIST_HEAD(invalid_list);
2734 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2736 spin_lock(&kvm->mmu_lock);
2737 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2738 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2741 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2743 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2744 spin_unlock(&kvm->mmu_lock);
2748 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2750 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2752 trace_kvm_mmu_unsync_page(sp);
2753 ++vcpu->kvm->stat.mmu_unsync;
2756 kvm_mmu_mark_parents_unsync(sp);
2759 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2762 struct kvm_mmu_page *sp;
2764 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2767 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2774 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
2775 kvm_unsync_page(vcpu, sp);
2779 * We need to ensure that the marking of unsync pages is visible
2780 * before the SPTE is updated to allow writes because
2781 * kvm_mmu_sync_roots() checks the unsync flags without holding
2782 * the MMU lock and so can race with this. If the SPTE was updated
2783 * before the page had been marked as unsync-ed, something like the
2784 * following could happen:
2787 * ---------------------------------------------------------------------
2788 * 1.2 Host updates SPTE
2790 * 2.1 Guest writes a GPTE for GVA X.
2791 * (GPTE being in the guest page table shadowed
2792 * by the SP from CPU 1.)
2793 * This reads SPTE during the page table walk.
2794 * Since SPTE.W is read as 1, there is no
2797 * 2.2 Guest issues TLB flush.
2798 * That causes a VM Exit.
2800 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2801 * Since it is false, so it just returns.
2803 * 2.4 Guest accesses GVA X.
2804 * Since the mapping in the SP was not updated,
2805 * so the old mapping for GVA X incorrectly
2809 * (sp->unsync = true)
2811 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2812 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2813 * pairs with this write barrier.
2820 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2823 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) &&
2825 * Some reserved pages, such as those from NVDIMM
2826 * DAX devices, are not for MMIO, and can be mapped
2827 * with cached memory type for better performance.
2828 * However, the above check misconceives those pages
2829 * as MMIO, and results in KVM mapping them with UC
2830 * memory type, which would hurt the performance.
2831 * Therefore, we check the host memory type in addition
2832 * and only treat UC/UC-/WC pages as MMIO.
2834 (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn));
2839 /* Bits which may be returned by set_spte() */
2840 #define SET_SPTE_WRITE_PROTECTED_PT BIT(0)
2841 #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1)
2843 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2844 unsigned pte_access, int level,
2845 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2846 bool can_unsync, bool host_writable)
2850 struct kvm_mmu_page *sp;
2852 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2855 sp = page_header(__pa(sptep));
2856 if (sp_ad_disabled(sp))
2857 spte |= shadow_acc_track_value;
2860 * For the EPT case, shadow_present_mask is 0 if hardware
2861 * supports exec-only page table entries. In that case,
2862 * ACC_USER_MASK and shadow_user_mask are used to represent
2863 * read access. See FNAME(gpte_access) in paging_tmpl.h.
2865 spte |= shadow_present_mask;
2867 spte |= spte_shadow_accessed_mask(spte);
2869 if (pte_access & ACC_EXEC_MASK)
2870 spte |= shadow_x_mask;
2872 spte |= shadow_nx_mask;
2874 if (pte_access & ACC_USER_MASK)
2875 spte |= shadow_user_mask;
2877 if (level > PT_PAGE_TABLE_LEVEL)
2878 spte |= PT_PAGE_SIZE_MASK;
2880 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2881 kvm_is_mmio_pfn(pfn));
2884 spte |= SPTE_HOST_WRITEABLE;
2886 pte_access &= ~ACC_WRITE_MASK;
2888 if (!kvm_is_mmio_pfn(pfn))
2889 spte |= shadow_me_mask;
2891 spte |= (u64)pfn << PAGE_SHIFT;
2893 if (pte_access & ACC_WRITE_MASK) {
2896 * Other vcpu creates new sp in the window between
2897 * mapping_level() and acquiring mmu-lock. We can
2898 * allow guest to retry the access, the mapping can
2899 * be fixed if guest refault.
2901 if (level > PT_PAGE_TABLE_LEVEL &&
2902 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2905 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2908 * Optimization: for pte sync, if spte was writable the hash
2909 * lookup is unnecessary (and expensive). Write protection
2910 * is responsibility of mmu_get_page / kvm_sync_page.
2911 * Same reasoning can be applied to dirty page accounting.
2913 if (!can_unsync && is_writable_pte(*sptep))
2916 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2917 pgprintk("%s: found shadow page for %llx, marking ro\n",
2919 ret |= SET_SPTE_WRITE_PROTECTED_PT;
2920 pte_access &= ~ACC_WRITE_MASK;
2921 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2925 if (pte_access & ACC_WRITE_MASK) {
2926 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2927 spte |= spte_shadow_dirty_mask(spte);
2931 spte = mark_spte_for_access_track(spte);
2934 if (mmu_spte_update(sptep, spte))
2935 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2940 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2941 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2942 bool speculative, bool host_writable)
2944 int was_rmapped = 0;
2947 int ret = RET_PF_RETRY;
2950 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2951 *sptep, write_fault, gfn);
2953 if (is_shadow_present_pte(*sptep)) {
2955 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2956 * the parent of the now unreachable PTE.
2958 if (level > PT_PAGE_TABLE_LEVEL &&
2959 !is_large_pte(*sptep)) {
2960 struct kvm_mmu_page *child;
2963 child = page_header(pte & PT64_BASE_ADDR_MASK);
2964 drop_parent_pte(child, sptep);
2966 } else if (pfn != spte_to_pfn(*sptep)) {
2967 pgprintk("hfn old %llx new %llx\n",
2968 spte_to_pfn(*sptep), pfn);
2969 drop_spte(vcpu->kvm, sptep);
2975 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2976 speculative, true, host_writable);
2977 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2979 ret = RET_PF_EMULATE;
2980 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2982 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2983 kvm_flush_remote_tlbs(vcpu->kvm);
2985 if (unlikely(is_mmio_spte(*sptep)))
2986 ret = RET_PF_EMULATE;
2988 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2989 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2990 is_large_pte(*sptep)? "2MB" : "4kB",
2991 *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn,
2993 if (!was_rmapped && is_large_pte(*sptep))
2994 ++vcpu->kvm->stat.lpages;
2996 if (is_shadow_present_pte(*sptep)) {
2998 rmap_count = rmap_add(vcpu, sptep, gfn);
2999 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
3000 rmap_recycle(vcpu, sptep, gfn);
3004 kvm_release_pfn_clean(pfn);
3009 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
3012 struct kvm_memory_slot *slot;
3014 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
3016 return KVM_PFN_ERR_FAULT;
3018 return gfn_to_pfn_memslot_atomic(slot, gfn);
3021 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
3022 struct kvm_mmu_page *sp,
3023 u64 *start, u64 *end)
3025 struct page *pages[PTE_PREFETCH_NUM];
3026 struct kvm_memory_slot *slot;
3027 unsigned access = sp->role.access;
3031 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
3032 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
3036 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
3040 for (i = 0; i < ret; i++, gfn++, start++)
3041 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
3042 page_to_pfn(pages[i]), true, true);
3047 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
3048 struct kvm_mmu_page *sp, u64 *sptep)
3050 u64 *spte, *start = NULL;
3053 WARN_ON(!sp->role.direct);
3055 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
3058 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
3059 if (is_shadow_present_pte(*spte) || spte == sptep) {
3062 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
3070 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
3072 struct kvm_mmu_page *sp;
3074 sp = page_header(__pa(sptep));
3077 * Without accessed bits, there's no way to distinguish between
3078 * actually accessed translations and prefetched, so disable pte
3079 * prefetch if accessed bits aren't available.
3081 if (sp_ad_disabled(sp))
3084 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3087 __direct_pte_prefetch(vcpu, sp, sptep);
3090 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
3091 int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
3093 struct kvm_shadow_walk_iterator iterator;
3094 struct kvm_mmu_page *sp;
3098 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3101 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
3102 if (iterator.level == level) {
3103 emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
3104 write, level, gfn, pfn, prefault,
3106 direct_pte_prefetch(vcpu, iterator.sptep);
3107 ++vcpu->stat.pf_fixed;
3111 drop_large_spte(vcpu, iterator.sptep);
3112 if (!is_shadow_present_pte(*iterator.sptep)) {
3113 u64 base_addr = iterator.addr;
3115 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
3116 pseudo_gfn = base_addr >> PAGE_SHIFT;
3117 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
3118 iterator.level - 1, 1, ACC_ALL);
3120 link_shadow_page(vcpu, iterator.sptep, sp);
3126 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
3128 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
3131 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
3134 * Do not cache the mmio info caused by writing the readonly gfn
3135 * into the spte otherwise read access on readonly gfn also can
3136 * caused mmio page fault and treat it as mmio access.
3138 if (pfn == KVM_PFN_ERR_RO_FAULT)
3139 return RET_PF_EMULATE;
3141 if (pfn == KVM_PFN_ERR_HWPOISON) {
3142 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
3143 return RET_PF_RETRY;
3149 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
3150 gfn_t *gfnp, kvm_pfn_t *pfnp,
3153 kvm_pfn_t pfn = *pfnp;
3155 int level = *levelp;
3158 * Check if it's a transparent hugepage. If this would be an
3159 * hugetlbfs page, level wouldn't be set to
3160 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
3163 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
3164 level == PT_PAGE_TABLE_LEVEL &&
3165 PageTransCompoundMap(pfn_to_page(pfn)) &&
3166 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
3169 * mmu_notifier_retry was successful and we hold the
3170 * mmu_lock here, so the pmd can't become splitting
3171 * from under us, and in turn
3172 * __split_huge_page_refcount() can't run from under
3173 * us and we can safely transfer the refcount from
3174 * PG_tail to PG_head as we switch the pfn to tail to
3177 *levelp = level = PT_DIRECTORY_LEVEL;
3178 mask = KVM_PAGES_PER_HPAGE(level) - 1;
3179 VM_BUG_ON((gfn & mask) != (pfn & mask));
3183 kvm_release_pfn_clean(pfn);
3191 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
3192 kvm_pfn_t pfn, unsigned access, int *ret_val)
3194 /* The pfn is invalid, report the error! */
3195 if (unlikely(is_error_pfn(pfn))) {
3196 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
3200 if (unlikely(is_noslot_pfn(pfn)))
3201 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
3206 static bool page_fault_can_be_fast(u32 error_code)
3209 * Do not fix the mmio spte with invalid generation number which
3210 * need to be updated by slow page fault path.
3212 if (unlikely(error_code & PFERR_RSVD_MASK))
3215 /* See if the page fault is due to an NX violation */
3216 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
3217 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
3221 * #PF can be fast if:
3222 * 1. The shadow page table entry is not present, which could mean that
3223 * the fault is potentially caused by access tracking (if enabled).
3224 * 2. The shadow page table entry is present and the fault
3225 * is caused by write-protect, that means we just need change the W
3226 * bit of the spte which can be done out of mmu-lock.
3228 * However, if access tracking is disabled we know that a non-present
3229 * page must be a genuine page fault where we have to create a new SPTE.
3230 * So, if access tracking is disabled, we return true only for write
3231 * accesses to a present page.
3234 return shadow_acc_track_mask != 0 ||
3235 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3236 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3240 * Returns true if the SPTE was fixed successfully. Otherwise,
3241 * someone else modified the SPTE from its original value.
3244 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3245 u64 *sptep, u64 old_spte, u64 new_spte)
3249 WARN_ON(!sp->role.direct);
3252 * Theoretically we could also set dirty bit (and flush TLB) here in
3253 * order to eliminate unnecessary PML logging. See comments in
3254 * set_spte. But fast_page_fault is very unlikely to happen with PML
3255 * enabled, so we do not do this. This might result in the same GPA
3256 * to be logged in PML buffer again when the write really happens, and
3257 * eventually to be called by mark_page_dirty twice. But it's also no
3258 * harm. This also avoids the TLB flush needed after setting dirty bit
3259 * so non-PML cases won't be impacted.
3261 * Compare with set_spte where instead shadow_dirty_mask is set.
3263 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3266 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3268 * The gfn of direct spte is stable since it is
3269 * calculated by sp->gfn.
3271 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3272 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3278 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3280 if (fault_err_code & PFERR_FETCH_MASK)
3281 return is_executable_pte(spte);
3283 if (fault_err_code & PFERR_WRITE_MASK)
3284 return is_writable_pte(spte);
3286 /* Fault was on Read access */
3287 return spte & PT_PRESENT_MASK;
3292 * - true: let the vcpu to access on the same address again.
3293 * - false: let the real page fault path to fix it.
3295 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
3298 struct kvm_shadow_walk_iterator iterator;
3299 struct kvm_mmu_page *sp;
3300 bool fault_handled = false;
3302 uint retry_count = 0;
3304 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3307 if (!page_fault_can_be_fast(error_code))
3310 walk_shadow_page_lockless_begin(vcpu);
3315 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
3316 if (!is_shadow_present_pte(spte) ||
3317 iterator.level < level)
3320 sp = page_header(__pa(iterator.sptep));
3321 if (!is_last_spte(spte, sp->role.level))
3325 * Check whether the memory access that caused the fault would
3326 * still cause it if it were to be performed right now. If not,
3327 * then this is a spurious fault caused by TLB lazily flushed,
3328 * or some other CPU has already fixed the PTE after the
3329 * current CPU took the fault.
3331 * Need not check the access of upper level table entries since
3332 * they are always ACC_ALL.
3334 if (is_access_allowed(error_code, spte)) {
3335 fault_handled = true;
3341 if (is_access_track_spte(spte))
3342 new_spte = restore_acc_track_spte(new_spte);
3345 * Currently, to simplify the code, write-protection can
3346 * be removed in the fast path only if the SPTE was
3347 * write-protected for dirty-logging or access tracking.
3349 if ((error_code & PFERR_WRITE_MASK) &&
3350 spte_can_locklessly_be_made_writable(spte))
3352 new_spte |= PT_WRITABLE_MASK;
3355 * Do not fix write-permission on the large spte. Since
3356 * we only dirty the first page into the dirty-bitmap in
3357 * fast_pf_fix_direct_spte(), other pages are missed
3358 * if its slot has dirty logging enabled.
3360 * Instead, we let the slow page fault path create a
3361 * normal spte to fix the access.
3363 * See the comments in kvm_arch_commit_memory_region().
3365 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
3369 /* Verify that the fault can be handled in the fast path */
3370 if (new_spte == spte ||
3371 !is_access_allowed(error_code, new_spte))
3375 * Currently, fast page fault only works for direct mapping
3376 * since the gfn is not stable for indirect shadow page. See
3377 * Documentation/virtual/kvm/locking.txt to get more detail.
3379 fault_handled = fast_pf_fix_direct_spte(vcpu, sp,
3380 iterator.sptep, spte,
3385 if (++retry_count > 4) {
3386 printk_once(KERN_WARNING
3387 "kvm: Fast #PF retrying more than 4 times.\n");
3393 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
3394 spte, fault_handled);
3395 walk_shadow_page_lockless_end(vcpu);
3397 return fault_handled;
3400 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3401 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
3402 static int make_mmu_pages_available(struct kvm_vcpu *vcpu);
3404 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
3405 gfn_t gfn, bool prefault)
3409 bool force_pt_level = false;
3411 unsigned long mmu_seq;
3412 bool map_writable, write = error_code & PFERR_WRITE_MASK;
3414 level = mapping_level(vcpu, gfn, &force_pt_level);
3415 if (likely(!force_pt_level)) {
3417 * This path builds a PAE pagetable - so we can map
3418 * 2mb pages at maximum. Therefore check if the level
3419 * is larger than that.
3421 if (level > PT_DIRECTORY_LEVEL)
3422 level = PT_DIRECTORY_LEVEL;
3424 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3427 if (fast_page_fault(vcpu, v, level, error_code))
3428 return RET_PF_RETRY;
3430 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3433 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3434 return RET_PF_RETRY;
3436 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3439 spin_lock(&vcpu->kvm->mmu_lock);
3440 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3442 if (make_mmu_pages_available(vcpu) < 0)
3444 if (likely(!force_pt_level))
3445 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3446 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3447 spin_unlock(&vcpu->kvm->mmu_lock);
3452 spin_unlock(&vcpu->kvm->mmu_lock);
3453 kvm_release_pfn_clean(pfn);
3454 return RET_PF_RETRY;
3457 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3458 struct list_head *invalid_list)
3460 struct kvm_mmu_page *sp;
3462 if (!VALID_PAGE(*root_hpa))
3465 sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK);
3467 if (!sp->root_count && sp->role.invalid)
3468 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3470 *root_hpa = INVALID_PAGE;
3473 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3474 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, ulong roots_to_free)
3477 LIST_HEAD(invalid_list);
3478 struct kvm_mmu *mmu = &vcpu->arch.mmu;
3479 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3481 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3483 /* Before acquiring the MMU lock, see if we need to do any real work. */
3484 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3485 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3486 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3487 VALID_PAGE(mmu->prev_roots[i].hpa))
3490 if (i == KVM_MMU_NUM_PREV_ROOTS)
3494 spin_lock(&vcpu->kvm->mmu_lock);
3496 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3497 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3498 mmu_free_root_page(vcpu->kvm, &mmu->prev_roots[i].hpa,
3501 if (free_active_root) {
3502 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3503 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3504 mmu_free_root_page(vcpu->kvm, &mmu->root_hpa,
3507 for (i = 0; i < 4; ++i)
3508 if (mmu->pae_root[i] != 0)
3509 mmu_free_root_page(vcpu->kvm,
3512 mmu->root_hpa = INVALID_PAGE;
3516 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3517 spin_unlock(&vcpu->kvm->mmu_lock);
3519 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3521 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3525 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3526 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3533 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3535 struct kvm_mmu_page *sp;
3538 if (vcpu->arch.mmu.shadow_root_level >= PT64_ROOT_4LEVEL) {
3539 spin_lock(&vcpu->kvm->mmu_lock);
3540 if(make_mmu_pages_available(vcpu) < 0) {
3541 spin_unlock(&vcpu->kvm->mmu_lock);
3544 sp = kvm_mmu_get_page(vcpu, 0, 0,
3545 vcpu->arch.mmu.shadow_root_level, 1, ACC_ALL);
3547 spin_unlock(&vcpu->kvm->mmu_lock);
3548 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3549 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3550 for (i = 0; i < 4; ++i) {
3551 hpa_t root = vcpu->arch.mmu.pae_root[i];
3553 MMU_WARN_ON(VALID_PAGE(root));
3554 spin_lock(&vcpu->kvm->mmu_lock);
3555 if (make_mmu_pages_available(vcpu) < 0) {
3556 spin_unlock(&vcpu->kvm->mmu_lock);
3559 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3560 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3561 root = __pa(sp->spt);
3563 spin_unlock(&vcpu->kvm->mmu_lock);
3564 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3566 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3573 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3575 struct kvm_mmu_page *sp;
3580 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3582 if (mmu_check_root(vcpu, root_gfn))
3586 * Do we shadow a long mode page table? If so we need to
3587 * write-protect the guests page table root.
3589 if (vcpu->arch.mmu.root_level >= PT64_ROOT_4LEVEL) {
3590 hpa_t root = vcpu->arch.mmu.root_hpa;
3592 MMU_WARN_ON(VALID_PAGE(root));
3594 spin_lock(&vcpu->kvm->mmu_lock);
3595 if (make_mmu_pages_available(vcpu) < 0) {
3596 spin_unlock(&vcpu->kvm->mmu_lock);
3599 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
3600 vcpu->arch.mmu.shadow_root_level, 0, ACC_ALL);
3601 root = __pa(sp->spt);
3603 spin_unlock(&vcpu->kvm->mmu_lock);
3604 vcpu->arch.mmu.root_hpa = root;
3609 * We shadow a 32 bit page table. This may be a legacy 2-level
3610 * or a PAE 3-level page table. In either case we need to be aware that
3611 * the shadow page table may be a PAE or a long mode page table.
3613 pm_mask = PT_PRESENT_MASK;
3614 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_4LEVEL)
3615 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3617 for (i = 0; i < 4; ++i) {
3618 hpa_t root = vcpu->arch.mmu.pae_root[i];
3620 MMU_WARN_ON(VALID_PAGE(root));
3621 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3622 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3623 if (!(pdptr & PT_PRESENT_MASK)) {
3624 vcpu->arch.mmu.pae_root[i] = 0;
3627 root_gfn = pdptr >> PAGE_SHIFT;
3628 if (mmu_check_root(vcpu, root_gfn))
3631 spin_lock(&vcpu->kvm->mmu_lock);
3632 if (make_mmu_pages_available(vcpu) < 0) {
3633 spin_unlock(&vcpu->kvm->mmu_lock);
3636 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3638 root = __pa(sp->spt);
3640 spin_unlock(&vcpu->kvm->mmu_lock);
3642 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3644 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3647 * If we shadow a 32 bit page table with a long mode page
3648 * table we enter this path.
3650 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_4LEVEL) {
3651 if (vcpu->arch.mmu.lm_root == NULL) {
3653 * The additional page necessary for this is only
3654 * allocated on demand.
3659 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3660 if (lm_root == NULL)
3663 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3665 vcpu->arch.mmu.lm_root = lm_root;
3668 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3674 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3676 if (vcpu->arch.mmu.direct_map)
3677 return mmu_alloc_direct_roots(vcpu);
3679 return mmu_alloc_shadow_roots(vcpu);
3682 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3685 struct kvm_mmu_page *sp;
3687 if (vcpu->arch.mmu.direct_map)
3690 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3693 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3695 if (vcpu->arch.mmu.root_level >= PT64_ROOT_4LEVEL) {
3696 hpa_t root = vcpu->arch.mmu.root_hpa;
3698 sp = page_header(root);
3701 * Even if another CPU was marking the SP as unsync-ed
3702 * simultaneously, any guest page table changes are not
3703 * guaranteed to be visible anyway until this VCPU issues a TLB
3704 * flush strictly after those changes are made. We only need to
3705 * ensure that the other CPU sets these flags before any actual
3706 * changes to the page tables are made. The comments in
3707 * mmu_need_write_protect() describe what could go wrong if this
3708 * requirement isn't satisfied.
3710 if (!smp_load_acquire(&sp->unsync) &&
3711 !smp_load_acquire(&sp->unsync_children))
3714 spin_lock(&vcpu->kvm->mmu_lock);
3715 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3717 mmu_sync_children(vcpu, sp);
3719 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3720 spin_unlock(&vcpu->kvm->mmu_lock);
3724 spin_lock(&vcpu->kvm->mmu_lock);
3725 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3727 for (i = 0; i < 4; ++i) {
3728 hpa_t root = vcpu->arch.mmu.pae_root[i];
3730 if (root && VALID_PAGE(root)) {
3731 root &= PT64_BASE_ADDR_MASK;
3732 sp = page_header(root);
3733 mmu_sync_children(vcpu, sp);
3737 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3738 spin_unlock(&vcpu->kvm->mmu_lock);
3740 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3742 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3743 u32 access, struct x86_exception *exception)
3746 exception->error_code = 0;
3750 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3752 struct x86_exception *exception)
3755 exception->error_code = 0;
3756 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3760 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3762 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3764 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3765 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3768 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3770 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3773 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3775 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3778 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3781 * A nested guest cannot use the MMIO cache if it is using nested
3782 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3784 if (mmu_is_nested(vcpu))
3788 return vcpu_match_mmio_gpa(vcpu, addr);
3790 return vcpu_match_mmio_gva(vcpu, addr);
3793 /* return true if reserved bit is detected on spte. */
3795 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3797 struct kvm_shadow_walk_iterator iterator;
3798 u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull;
3800 bool reserved = false;
3802 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3805 walk_shadow_page_lockless_begin(vcpu);
3807 for (shadow_walk_init(&iterator, vcpu, addr),
3808 leaf = root = iterator.level;
3809 shadow_walk_okay(&iterator);
3810 __shadow_walk_next(&iterator, spte)) {
3811 spte = mmu_spte_get_lockless(iterator.sptep);
3813 sptes[leaf - 1] = spte;
3816 if (!is_shadow_present_pte(spte))
3819 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
3823 walk_shadow_page_lockless_end(vcpu);
3826 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3828 while (root > leaf) {
3829 pr_err("------ spte 0x%llx level %d.\n",
3830 sptes[root - 1], root);
3839 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3844 if (mmio_info_in_cache(vcpu, addr, direct))
3845 return RET_PF_EMULATE;
3847 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3848 if (WARN_ON(reserved))
3851 if (is_mmio_spte(spte)) {
3852 gfn_t gfn = get_mmio_spte_gfn(spte);
3853 unsigned access = get_mmio_spte_access(spte);
3855 if (!check_mmio_spte(vcpu, spte))
3856 return RET_PF_INVALID;
3861 trace_handle_mmio_page_fault(addr, gfn, access);
3862 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3863 return RET_PF_EMULATE;
3867 * If the page table is zapped by other cpus, let CPU fault again on
3870 return RET_PF_RETRY;
3873 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3874 u32 error_code, gfn_t gfn)
3876 if (unlikely(error_code & PFERR_RSVD_MASK))
3879 if (!(error_code & PFERR_PRESENT_MASK) ||
3880 !(error_code & PFERR_WRITE_MASK))
3884 * guest is writing the page which is write tracked which can
3885 * not be fixed by page fault handler.
3887 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3893 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3895 struct kvm_shadow_walk_iterator iterator;
3898 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3901 walk_shadow_page_lockless_begin(vcpu);
3902 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3903 clear_sp_write_flooding_count(iterator.sptep);
3904 if (!is_shadow_present_pte(spte))
3907 walk_shadow_page_lockless_end(vcpu);
3910 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3911 u32 error_code, bool prefault)
3913 gfn_t gfn = gva >> PAGE_SHIFT;
3916 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3918 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3919 return RET_PF_EMULATE;
3921 r = mmu_topup_memory_caches(vcpu);
3925 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3928 return nonpaging_map(vcpu, gva & PAGE_MASK,
3929 error_code, gfn, prefault);
3932 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3934 struct kvm_arch_async_pf arch;
3936 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3938 arch.direct_map = vcpu->arch.mmu.direct_map;
3939 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3941 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3944 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
3946 if (unlikely(!lapic_in_kernel(vcpu) ||
3947 kvm_event_needs_reinjection(vcpu) ||
3948 vcpu->arch.exception.pending))
3951 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
3954 return kvm_x86_ops->interrupt_allowed(vcpu);
3957 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3958 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
3960 struct kvm_memory_slot *slot;
3964 * Don't expose private memslots to L2.
3966 if (is_guest_mode(vcpu) && !kvm_is_visible_gfn(vcpu->kvm, gfn)) {
3967 *pfn = KVM_PFN_NOSLOT;
3971 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3973 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3975 return false; /* *pfn has correct page already */
3977 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3978 trace_kvm_try_async_get_page(gva, gfn);
3979 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3980 trace_kvm_async_pf_doublefault(gva, gfn);
3981 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3983 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3987 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3991 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3992 u64 fault_address, char *insn, int insn_len)
3996 vcpu->arch.l1tf_flush_l1d = true;
3997 switch (vcpu->arch.apf.host_apf_reason) {
3999 trace_kvm_page_fault(fault_address, error_code);
4001 if (kvm_event_needs_reinjection(vcpu))
4002 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
4003 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
4006 case KVM_PV_REASON_PAGE_NOT_PRESENT:
4007 vcpu->arch.apf.host_apf_reason = 0;
4008 local_irq_disable();
4009 kvm_async_pf_task_wait(fault_address, 0);
4012 case KVM_PV_REASON_PAGE_READY:
4013 vcpu->arch.apf.host_apf_reason = 0;
4014 local_irq_disable();
4015 kvm_async_pf_task_wake(fault_address);
4021 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
4024 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
4026 int page_num = KVM_PAGES_PER_HPAGE(level);
4028 gfn &= ~(page_num - 1);
4030 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
4033 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
4039 bool force_pt_level;
4040 gfn_t gfn = gpa >> PAGE_SHIFT;
4041 unsigned long mmu_seq;
4042 int write = error_code & PFERR_WRITE_MASK;
4045 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4047 if (page_fault_handle_page_track(vcpu, error_code, gfn))
4048 return RET_PF_EMULATE;
4050 r = mmu_topup_memory_caches(vcpu);
4054 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
4055 PT_DIRECTORY_LEVEL);
4056 level = mapping_level(vcpu, gfn, &force_pt_level);
4057 if (likely(!force_pt_level)) {
4058 if (level > PT_DIRECTORY_LEVEL &&
4059 !check_hugepage_cache_consistency(vcpu, gfn, level))
4060 level = PT_DIRECTORY_LEVEL;
4061 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
4064 if (fast_page_fault(vcpu, gpa, level, error_code))
4065 return RET_PF_RETRY;
4067 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4070 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
4071 return RET_PF_RETRY;
4073 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
4076 spin_lock(&vcpu->kvm->mmu_lock);
4077 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
4079 if (make_mmu_pages_available(vcpu) < 0)
4081 if (likely(!force_pt_level))
4082 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
4083 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
4084 spin_unlock(&vcpu->kvm->mmu_lock);
4089 spin_unlock(&vcpu->kvm->mmu_lock);
4090 kvm_release_pfn_clean(pfn);
4091 return RET_PF_RETRY;
4094 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
4095 struct kvm_mmu *context)
4097 context->page_fault = nonpaging_page_fault;
4098 context->gva_to_gpa = nonpaging_gva_to_gpa;
4099 context->sync_page = nonpaging_sync_page;
4100 context->invlpg = nonpaging_invlpg;
4101 context->update_pte = nonpaging_update_pte;
4102 context->root_level = 0;
4103 context->shadow_root_level = PT32E_ROOT_LEVEL;
4104 context->direct_map = true;
4105 context->nx = false;
4109 * Find out if a previously cached root matching the new CR3/role is available.
4110 * The current root is also inserted into the cache.
4111 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
4113 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
4114 * false is returned. This root should now be freed by the caller.
4116 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4117 union kvm_mmu_page_role new_role)
4120 struct kvm_mmu_root_info root;
4121 struct kvm_mmu *mmu = &vcpu->arch.mmu;
4123 root.cr3 = mmu->get_cr3(vcpu);
4124 root.hpa = mmu->root_hpa;
4126 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
4127 swap(root, mmu->prev_roots[i]);
4129 if (new_cr3 == root.cr3 && VALID_PAGE(root.hpa) &&
4130 page_header(root.hpa) != NULL &&
4131 new_role.word == page_header(root.hpa)->role.word)
4135 mmu->root_hpa = root.hpa;
4137 return i < KVM_MMU_NUM_PREV_ROOTS;
4140 static bool fast_cr3_switch(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4141 union kvm_mmu_page_role new_role,
4142 bool skip_tlb_flush)
4144 struct kvm_mmu *mmu = &vcpu->arch.mmu;
4147 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
4148 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
4149 * later if necessary.
4151 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
4152 mmu->root_level >= PT64_ROOT_4LEVEL) {
4153 if (mmu_check_root(vcpu, new_cr3 >> PAGE_SHIFT))
4156 if (cached_root_available(vcpu, new_cr3, new_role)) {
4158 * It is possible that the cached previous root page is
4159 * obsolete because of a change in the MMU
4160 * generation number. However, that is accompanied by
4161 * KVM_REQ_MMU_RELOAD, which will free the root that we
4162 * have set here and allocate a new one.
4165 kvm_make_request(KVM_REQ_LOAD_CR3, vcpu);
4166 if (!skip_tlb_flush) {
4167 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4168 kvm_x86_ops->tlb_flush(vcpu, true);
4172 * The last MMIO access's GVA and GPA are cached in the
4173 * VCPU. When switching to a new CR3, that GVA->GPA
4174 * mapping may no longer be valid. So clear any cached
4175 * MMIO info even when we don't need to sync the shadow
4178 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4180 __clear_sp_write_flooding_count(
4181 page_header(mmu->root_hpa));
4190 static void __kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3,
4191 union kvm_mmu_page_role new_role,
4192 bool skip_tlb_flush)
4194 if (!fast_cr3_switch(vcpu, new_cr3, new_role, skip_tlb_flush))
4195 kvm_mmu_free_roots(vcpu, KVM_MMU_ROOT_CURRENT);
4198 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush)
4200 __kvm_mmu_new_cr3(vcpu, new_cr3, kvm_mmu_calc_root_page_role(vcpu),
4203 EXPORT_SYMBOL_GPL(kvm_mmu_new_cr3);
4205 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4207 return kvm_read_cr3(vcpu);
4210 static void inject_page_fault(struct kvm_vcpu *vcpu,
4211 struct x86_exception *fault)
4213 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
4216 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4217 unsigned access, int *nr_present)
4219 if (unlikely(is_mmio_spte(*sptep))) {
4220 if (gfn != get_mmio_spte_gfn(*sptep)) {
4221 mmu_spte_clear_no_track(sptep);
4226 mark_mmio_spte(vcpu, sptep, gfn, access);
4233 static inline bool is_last_gpte(struct kvm_mmu *mmu,
4234 unsigned level, unsigned gpte)
4237 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4238 * If it is clear, there are no large pages at this level, so clear
4239 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4241 gpte &= level - mmu->last_nonleaf_level;
4244 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
4245 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
4246 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
4248 gpte |= level - PT_PAGE_TABLE_LEVEL - 1;
4250 return gpte & PT_PAGE_SIZE_MASK;
4253 #define PTTYPE_EPT 18 /* arbitrary */
4254 #define PTTYPE PTTYPE_EPT
4255 #include "paging_tmpl.h"
4259 #include "paging_tmpl.h"
4263 #include "paging_tmpl.h"
4267 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4268 struct rsvd_bits_validate *rsvd_check,
4269 int maxphyaddr, int level, bool nx, bool gbpages,
4272 u64 exb_bit_rsvd = 0;
4273 u64 gbpages_bit_rsvd = 0;
4274 u64 nonleaf_bit8_rsvd = 0;
4276 rsvd_check->bad_mt_xwr = 0;
4279 exb_bit_rsvd = rsvd_bits(63, 63);
4281 gbpages_bit_rsvd = rsvd_bits(7, 7);
4284 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4285 * leaf entries) on AMD CPUs only.
4288 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4291 case PT32_ROOT_LEVEL:
4292 /* no rsvd bits for 2 level 4K page table entries */
4293 rsvd_check->rsvd_bits_mask[0][1] = 0;
4294 rsvd_check->rsvd_bits_mask[0][0] = 0;
4295 rsvd_check->rsvd_bits_mask[1][0] =
4296 rsvd_check->rsvd_bits_mask[0][0];
4299 rsvd_check->rsvd_bits_mask[1][1] = 0;
4303 if (is_cpuid_PSE36())
4304 /* 36bits PSE 4MB page */
4305 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4307 /* 32 bits PSE 4MB page */
4308 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4310 case PT32E_ROOT_LEVEL:
4311 rsvd_check->rsvd_bits_mask[0][2] =
4312 rsvd_bits(maxphyaddr, 63) |
4313 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
4314 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4315 rsvd_bits(maxphyaddr, 62); /* PDE */
4316 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4317 rsvd_bits(maxphyaddr, 62); /* PTE */
4318 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4319 rsvd_bits(maxphyaddr, 62) |
4320 rsvd_bits(13, 20); /* large page */
4321 rsvd_check->rsvd_bits_mask[1][0] =
4322 rsvd_check->rsvd_bits_mask[0][0];
4324 case PT64_ROOT_5LEVEL:
4325 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
4326 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4327 rsvd_bits(maxphyaddr, 51);
4328 rsvd_check->rsvd_bits_mask[1][4] =
4329 rsvd_check->rsvd_bits_mask[0][4];
4330 case PT64_ROOT_4LEVEL:
4331 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4332 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
4333 rsvd_bits(maxphyaddr, 51);
4334 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
4335 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
4336 rsvd_bits(maxphyaddr, 51);
4337 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4338 rsvd_bits(maxphyaddr, 51);
4339 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
4340 rsvd_bits(maxphyaddr, 51);
4341 rsvd_check->rsvd_bits_mask[1][3] =
4342 rsvd_check->rsvd_bits_mask[0][3];
4343 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
4344 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
4346 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4347 rsvd_bits(maxphyaddr, 51) |
4348 rsvd_bits(13, 20); /* large page */
4349 rsvd_check->rsvd_bits_mask[1][0] =
4350 rsvd_check->rsvd_bits_mask[0][0];
4355 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4356 struct kvm_mmu *context)
4358 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4359 cpuid_maxphyaddr(vcpu), context->root_level,
4361 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4362 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
4366 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4367 int maxphyaddr, bool execonly)
4371 rsvd_check->rsvd_bits_mask[0][4] =
4372 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4373 rsvd_check->rsvd_bits_mask[0][3] =
4374 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4375 rsvd_check->rsvd_bits_mask[0][2] =
4376 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4377 rsvd_check->rsvd_bits_mask[0][1] =
4378 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4379 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4382 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4383 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4384 rsvd_check->rsvd_bits_mask[1][2] =
4385 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4386 rsvd_check->rsvd_bits_mask[1][1] =
4387 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4388 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4390 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4391 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4392 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4393 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4394 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4396 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4397 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4399 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4402 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4403 struct kvm_mmu *context, bool execonly)
4405 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4406 cpuid_maxphyaddr(vcpu), execonly);
4410 * the page table on host is the shadow page table for the page
4411 * table in guest or amd nested guest, its mmu features completely
4412 * follow the features in guest.
4415 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4417 bool uses_nx = context->nx || context->base_role.smep_andnot_wp;
4418 struct rsvd_bits_validate *shadow_zero_check;
4422 * Passing "true" to the last argument is okay; it adds a check
4423 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4425 shadow_zero_check = &context->shadow_zero_check;
4426 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4427 boot_cpu_data.x86_phys_bits,
4428 context->shadow_root_level, uses_nx,
4429 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4430 is_pse(vcpu), true);
4432 if (!shadow_me_mask)
4435 for (i = context->shadow_root_level; --i >= 0;) {
4436 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4437 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4441 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4443 static inline bool boot_cpu_is_amd(void)
4445 WARN_ON_ONCE(!tdp_enabled);
4446 return shadow_x_mask == 0;
4450 * the direct page table on host, use as much mmu features as
4451 * possible, however, kvm currently does not do execution-protection.
4454 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4455 struct kvm_mmu *context)
4457 struct rsvd_bits_validate *shadow_zero_check;
4460 shadow_zero_check = &context->shadow_zero_check;
4462 if (boot_cpu_is_amd())
4463 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4464 boot_cpu_data.x86_phys_bits,
4465 context->shadow_root_level, false,
4466 boot_cpu_has(X86_FEATURE_GBPAGES),
4469 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4470 boot_cpu_data.x86_phys_bits,
4473 if (!shadow_me_mask)
4476 for (i = context->shadow_root_level; --i >= 0;) {
4477 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4478 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4483 * as the comments in reset_shadow_zero_bits_mask() except it
4484 * is the shadow page table for intel nested guest.
4487 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4488 struct kvm_mmu *context, bool execonly)
4490 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4491 boot_cpu_data.x86_phys_bits, execonly);
4494 #define BYTE_MASK(access) \
4495 ((1 & (access) ? 2 : 0) | \
4496 (2 & (access) ? 4 : 0) | \
4497 (3 & (access) ? 8 : 0) | \
4498 (4 & (access) ? 16 : 0) | \
4499 (5 & (access) ? 32 : 0) | \
4500 (6 & (access) ? 64 : 0) | \
4501 (7 & (access) ? 128 : 0))
4504 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4505 struct kvm_mmu *mmu, bool ept)
4509 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4510 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4511 const u8 u = BYTE_MASK(ACC_USER_MASK);
4513 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4514 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4515 bool cr0_wp = is_write_protection(vcpu);
4517 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4518 unsigned pfec = byte << 1;
4521 * Each "*f" variable has a 1 bit for each UWX value
4522 * that causes a fault with the given PFEC.
4525 /* Faults from writes to non-writable pages */
4526 u8 wf = (pfec & PFERR_WRITE_MASK) ? ~w : 0;
4527 /* Faults from user mode accesses to supervisor pages */
4528 u8 uf = (pfec & PFERR_USER_MASK) ? ~u : 0;
4529 /* Faults from fetches of non-executable pages*/
4530 u8 ff = (pfec & PFERR_FETCH_MASK) ? ~x : 0;
4531 /* Faults from kernel mode fetches of user pages */
4533 /* Faults from kernel mode accesses of user pages */
4537 /* Faults from kernel mode accesses to user pages */
4538 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4540 /* Not really needed: !nx will cause pte.nx to fault */
4544 /* Allow supervisor writes if !cr0.wp */
4546 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4548 /* Disallow supervisor fetches of user code if cr4.smep */
4550 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4553 * SMAP:kernel-mode data accesses from user-mode
4554 * mappings should fault. A fault is considered
4555 * as a SMAP violation if all of the following
4556 * conditions are ture:
4557 * - X86_CR4_SMAP is set in CR4
4558 * - A user page is accessed
4559 * - The access is not a fetch
4560 * - Page fault in kernel mode
4561 * - if CPL = 3 or X86_EFLAGS_AC is clear
4563 * Here, we cover the first three conditions.
4564 * The fourth is computed dynamically in permission_fault();
4565 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4566 * *not* subject to SMAP restrictions.
4569 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4572 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4577 * PKU is an additional mechanism by which the paging controls access to
4578 * user-mode addresses based on the value in the PKRU register. Protection
4579 * key violations are reported through a bit in the page fault error code.
4580 * Unlike other bits of the error code, the PK bit is not known at the
4581 * call site of e.g. gva_to_gpa; it must be computed directly in
4582 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4583 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4585 * In particular the following conditions come from the error code, the
4586 * page tables and the machine state:
4587 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4588 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4589 * - PK is always zero if U=0 in the page tables
4590 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4592 * The PKRU bitmask caches the result of these four conditions. The error
4593 * code (minus the P bit) and the page table's U bit form an index into the
4594 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4595 * with the two bits of the PKRU register corresponding to the protection key.
4596 * For the first three conditions above the bits will be 00, thus masking
4597 * away both AD and WD. For all reads or if the last condition holds, WD
4598 * only will be masked away.
4600 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4611 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4612 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4617 wp = is_write_protection(vcpu);
4619 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4620 unsigned pfec, pkey_bits;
4621 bool check_pkey, check_write, ff, uf, wf, pte_user;
4624 ff = pfec & PFERR_FETCH_MASK;
4625 uf = pfec & PFERR_USER_MASK;
4626 wf = pfec & PFERR_WRITE_MASK;
4628 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4629 pte_user = pfec & PFERR_RSVD_MASK;
4632 * Only need to check the access which is not an
4633 * instruction fetch and is to a user page.
4635 check_pkey = (!ff && pte_user);
4637 * write access is controlled by PKRU if it is a
4638 * user access or CR0.WP = 1.
4640 check_write = check_pkey && wf && (uf || wp);
4642 /* PKRU.AD stops both read and write access. */
4643 pkey_bits = !!check_pkey;
4644 /* PKRU.WD stops write access. */
4645 pkey_bits |= (!!check_write) << 1;
4647 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4651 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4653 unsigned root_level = mmu->root_level;
4655 mmu->last_nonleaf_level = root_level;
4656 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4657 mmu->last_nonleaf_level++;
4660 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4661 struct kvm_mmu *context,
4664 context->nx = is_nx(vcpu);
4665 context->root_level = level;
4667 reset_rsvds_bits_mask(vcpu, context);
4668 update_permission_bitmask(vcpu, context, false);
4669 update_pkru_bitmask(vcpu, context, false);
4670 update_last_nonleaf_level(vcpu, context);
4672 MMU_WARN_ON(!is_pae(vcpu));
4673 context->page_fault = paging64_page_fault;
4674 context->gva_to_gpa = paging64_gva_to_gpa;
4675 context->sync_page = paging64_sync_page;
4676 context->invlpg = paging64_invlpg;
4677 context->update_pte = paging64_update_pte;
4678 context->shadow_root_level = level;
4679 context->direct_map = false;
4682 static void paging64_init_context(struct kvm_vcpu *vcpu,
4683 struct kvm_mmu *context)
4685 int root_level = is_la57_mode(vcpu) ?
4686 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4688 paging64_init_context_common(vcpu, context, root_level);
4691 static void paging32_init_context(struct kvm_vcpu *vcpu,
4692 struct kvm_mmu *context)
4694 context->nx = false;
4695 context->root_level = PT32_ROOT_LEVEL;
4697 reset_rsvds_bits_mask(vcpu, context);
4698 update_permission_bitmask(vcpu, context, false);
4699 update_pkru_bitmask(vcpu, context, false);
4700 update_last_nonleaf_level(vcpu, context);
4702 context->page_fault = paging32_page_fault;
4703 context->gva_to_gpa = paging32_gva_to_gpa;
4704 context->sync_page = paging32_sync_page;
4705 context->invlpg = paging32_invlpg;
4706 context->update_pte = paging32_update_pte;
4707 context->shadow_root_level = PT32E_ROOT_LEVEL;
4708 context->direct_map = false;
4711 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4712 struct kvm_mmu *context)
4714 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4717 static union kvm_mmu_page_role
4718 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu)
4720 union kvm_mmu_page_role role = {0};
4722 role.guest_mode = is_guest_mode(vcpu);
4723 role.smm = is_smm(vcpu);
4724 role.ad_disabled = (shadow_accessed_mask == 0);
4725 role.level = kvm_x86_ops->get_tdp_level(vcpu);
4727 role.access = ACC_ALL;
4732 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4734 struct kvm_mmu *context = &vcpu->arch.mmu;
4736 context->base_role.word = mmu_base_role_mask.word &
4737 kvm_calc_tdp_mmu_root_page_role(vcpu).word;
4738 context->page_fault = tdp_page_fault;
4739 context->sync_page = nonpaging_sync_page;
4740 context->invlpg = nonpaging_invlpg;
4741 context->update_pte = nonpaging_update_pte;
4742 context->shadow_root_level = kvm_x86_ops->get_tdp_level(vcpu);
4743 context->direct_map = true;
4744 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
4745 context->get_cr3 = get_cr3;
4746 context->get_pdptr = kvm_pdptr_read;
4747 context->inject_page_fault = kvm_inject_page_fault;
4749 if (!is_paging(vcpu)) {
4750 context->nx = false;
4751 context->gva_to_gpa = nonpaging_gva_to_gpa;
4752 context->root_level = 0;
4753 } else if (is_long_mode(vcpu)) {
4754 context->nx = is_nx(vcpu);
4755 context->root_level = is_la57_mode(vcpu) ?
4756 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4757 reset_rsvds_bits_mask(vcpu, context);
4758 context->gva_to_gpa = paging64_gva_to_gpa;
4759 } else if (is_pae(vcpu)) {
4760 context->nx = is_nx(vcpu);
4761 context->root_level = PT32E_ROOT_LEVEL;
4762 reset_rsvds_bits_mask(vcpu, context);
4763 context->gva_to_gpa = paging64_gva_to_gpa;
4765 context->nx = false;
4766 context->root_level = PT32_ROOT_LEVEL;
4767 reset_rsvds_bits_mask(vcpu, context);
4768 context->gva_to_gpa = paging32_gva_to_gpa;
4771 update_permission_bitmask(vcpu, context, false);
4772 update_pkru_bitmask(vcpu, context, false);
4773 update_last_nonleaf_level(vcpu, context);
4774 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4777 static union kvm_mmu_page_role
4778 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu)
4780 union kvm_mmu_page_role role = {0};
4781 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4782 bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4784 role.nxe = is_nx(vcpu);
4785 role.cr4_pae = !!is_pae(vcpu);
4786 role.cr0_wp = is_write_protection(vcpu);
4787 role.smep_andnot_wp = smep && !is_write_protection(vcpu);
4788 role.smap_andnot_wp = smap && !is_write_protection(vcpu);
4789 role.guest_mode = is_guest_mode(vcpu);
4790 role.smm = is_smm(vcpu);
4791 role.direct = !is_paging(vcpu);
4792 role.access = ACC_ALL;
4794 if (!is_long_mode(vcpu))
4795 role.level = PT32E_ROOT_LEVEL;
4796 else if (is_la57_mode(vcpu))
4797 role.level = PT64_ROOT_5LEVEL;
4799 role.level = PT64_ROOT_4LEVEL;
4804 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
4806 struct kvm_mmu *context = &vcpu->arch.mmu;
4808 if (!is_paging(vcpu))
4809 nonpaging_init_context(vcpu, context);
4810 else if (is_long_mode(vcpu))
4811 paging64_init_context(vcpu, context);
4812 else if (is_pae(vcpu))
4813 paging32E_init_context(vcpu, context);
4815 paging32_init_context(vcpu, context);
4817 context->base_role.word = mmu_base_role_mask.word &
4818 kvm_calc_shadow_mmu_root_page_role(vcpu).word;
4819 reset_shadow_zero_bits_mask(vcpu, context);
4821 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4823 static union kvm_mmu_page_role
4824 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty)
4826 union kvm_mmu_page_role role = vcpu->arch.mmu.base_role;
4828 role.level = PT64_ROOT_4LEVEL;
4829 role.direct = false;
4830 role.ad_disabled = !accessed_dirty;
4831 role.guest_mode = true;
4832 role.access = ACC_ALL;
4837 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4838 bool accessed_dirty, gpa_t new_eptp)
4840 struct kvm_mmu *context = &vcpu->arch.mmu;
4841 union kvm_mmu_page_role root_page_role =
4842 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty);
4844 __kvm_mmu_new_cr3(vcpu, new_eptp, root_page_role, false);
4845 context->shadow_root_level = PT64_ROOT_4LEVEL;
4848 context->ept_ad = accessed_dirty;
4849 context->page_fault = ept_page_fault;
4850 context->gva_to_gpa = ept_gva_to_gpa;
4851 context->sync_page = ept_sync_page;
4852 context->invlpg = ept_invlpg;
4853 context->update_pte = ept_update_pte;
4854 context->root_level = PT64_ROOT_4LEVEL;
4855 context->direct_map = false;
4856 context->base_role.word = root_page_role.word & mmu_base_role_mask.word;
4857 update_permission_bitmask(vcpu, context, true);
4858 update_pkru_bitmask(vcpu, context, true);
4859 update_last_nonleaf_level(vcpu, context);
4860 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4861 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4863 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4865 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4867 struct kvm_mmu *context = &vcpu->arch.mmu;
4869 kvm_init_shadow_mmu(vcpu);
4870 context->set_cr3 = kvm_x86_ops->set_cr3;
4871 context->get_cr3 = get_cr3;
4872 context->get_pdptr = kvm_pdptr_read;
4873 context->inject_page_fault = kvm_inject_page_fault;
4876 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4878 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4880 g_context->get_cr3 = get_cr3;
4881 g_context->get_pdptr = kvm_pdptr_read;
4882 g_context->inject_page_fault = kvm_inject_page_fault;
4885 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4886 * L1's nested page tables (e.g. EPT12). The nested translation
4887 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4888 * L2's page tables as the first level of translation and L1's
4889 * nested page tables as the second level of translation. Basically
4890 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4892 if (!is_paging(vcpu)) {
4893 g_context->nx = false;
4894 g_context->root_level = 0;
4895 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4896 } else if (is_long_mode(vcpu)) {
4897 g_context->nx = is_nx(vcpu);
4898 g_context->root_level = is_la57_mode(vcpu) ?
4899 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4900 reset_rsvds_bits_mask(vcpu, g_context);
4901 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4902 } else if (is_pae(vcpu)) {
4903 g_context->nx = is_nx(vcpu);
4904 g_context->root_level = PT32E_ROOT_LEVEL;
4905 reset_rsvds_bits_mask(vcpu, g_context);
4906 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4908 g_context->nx = false;
4909 g_context->root_level = PT32_ROOT_LEVEL;
4910 reset_rsvds_bits_mask(vcpu, g_context);
4911 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4914 update_permission_bitmask(vcpu, g_context, false);
4915 update_pkru_bitmask(vcpu, g_context, false);
4916 update_last_nonleaf_level(vcpu, g_context);
4919 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
4924 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4926 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
4927 vcpu->arch.mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
4930 if (mmu_is_nested(vcpu))
4931 init_kvm_nested_mmu(vcpu);
4932 else if (tdp_enabled)
4933 init_kvm_tdp_mmu(vcpu);
4935 init_kvm_softmmu(vcpu);
4937 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4939 static union kvm_mmu_page_role
4940 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4943 return kvm_calc_tdp_mmu_root_page_role(vcpu);
4945 return kvm_calc_shadow_mmu_root_page_role(vcpu);
4948 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4950 kvm_mmu_unload(vcpu);
4951 kvm_init_mmu(vcpu, true);
4953 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4955 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4959 r = mmu_topup_memory_caches(vcpu);
4962 r = mmu_alloc_roots(vcpu);
4963 kvm_mmu_sync_roots(vcpu);
4966 kvm_mmu_load_cr3(vcpu);
4967 kvm_x86_ops->tlb_flush(vcpu, true);
4971 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4973 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4975 kvm_mmu_free_roots(vcpu, KVM_MMU_ROOTS_ALL);
4976 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4978 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4980 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4981 struct kvm_mmu_page *sp, u64 *spte,
4984 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4985 ++vcpu->kvm->stat.mmu_pde_zapped;
4989 ++vcpu->kvm->stat.mmu_pte_updated;
4990 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4993 static bool need_remote_flush(u64 old, u64 new)
4995 if (!is_shadow_present_pte(old))
4997 if (!is_shadow_present_pte(new))
4999 if ((old ^ new) & PT64_BASE_ADDR_MASK)
5001 old ^= shadow_nx_mask;
5002 new ^= shadow_nx_mask;
5003 return (old & ~new & PT64_PERM_MASK) != 0;
5006 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
5007 const u8 *new, int *bytes)
5013 * Assume that the pte write on a page table of the same type
5014 * as the current vcpu paging mode since we update the sptes only
5015 * when they have the same mode.
5017 if (is_pae(vcpu) && *bytes == 4) {
5018 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5021 r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8);
5024 new = (const u8 *)&gentry;
5029 gentry = *(const u32 *)new;
5032 gentry = *(const u64 *)new;
5043 * If we're seeing too many writes to a page, it may no longer be a page table,
5044 * or we may be forking, in which case it is better to unmap the page.
5046 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5049 * Skip write-flooding detected for the sp whose level is 1, because
5050 * it can become unsync, then the guest page is not write-protected.
5052 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
5055 atomic_inc(&sp->write_flooding_count);
5056 return atomic_read(&sp->write_flooding_count) >= 3;
5060 * Misaligned accesses are too much trouble to fix up; also, they usually
5061 * indicate a page is not used as a page table.
5063 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5066 unsigned offset, pte_size, misaligned;
5068 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5069 gpa, bytes, sp->role.word);
5071 offset = offset_in_page(gpa);
5072 pte_size = sp->role.cr4_pae ? 8 : 4;
5075 * Sometimes, the OS only writes the last one bytes to update status
5076 * bits, for example, in linux, andb instruction is used in clear_bit().
5078 if (!(offset & (pte_size - 1)) && bytes == 1)
5081 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5082 misaligned |= bytes < 4;
5087 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5089 unsigned page_offset, quadrant;
5093 page_offset = offset_in_page(gpa);
5094 level = sp->role.level;
5096 if (!sp->role.cr4_pae) {
5097 page_offset <<= 1; /* 32->64 */
5099 * A 32-bit pde maps 4MB while the shadow pdes map
5100 * only 2MB. So we need to double the offset again
5101 * and zap two pdes instead of one.
5103 if (level == PT32_ROOT_LEVEL) {
5104 page_offset &= ~7; /* kill rounding error */
5108 quadrant = page_offset >> PAGE_SHIFT;
5109 page_offset &= ~PAGE_MASK;
5110 if (quadrant != sp->role.quadrant)
5114 spte = &sp->spt[page_offset / sizeof(*spte)];
5118 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5119 const u8 *new, int bytes,
5120 struct kvm_page_track_notifier_node *node)
5122 gfn_t gfn = gpa >> PAGE_SHIFT;
5123 struct kvm_mmu_page *sp;
5124 LIST_HEAD(invalid_list);
5125 u64 entry, gentry, *spte;
5127 bool remote_flush, local_flush;
5130 * If we don't have indirect shadow pages, it means no page is
5131 * write-protected, so we can exit simply.
5133 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5136 remote_flush = local_flush = false;
5138 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5140 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
5143 * No need to care whether allocation memory is successful
5144 * or not since pte prefetch is skiped if it does not have
5145 * enough objects in the cache.
5147 mmu_topup_memory_caches(vcpu);
5149 spin_lock(&vcpu->kvm->mmu_lock);
5150 ++vcpu->kvm->stat.mmu_pte_write;
5151 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5153 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5154 if (detect_write_misaligned(sp, gpa, bytes) ||
5155 detect_write_flooding(sp)) {
5156 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5157 ++vcpu->kvm->stat.mmu_flooded;
5161 spte = get_written_sptes(sp, gpa, &npte);
5168 mmu_page_zap_pte(vcpu->kvm, sp, spte);
5170 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
5171 & mmu_base_role_mask.word) && rmap_can_add(vcpu))
5172 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
5173 if (need_remote_flush(entry, *spte))
5174 remote_flush = true;
5178 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5179 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5180 spin_unlock(&vcpu->kvm->mmu_lock);
5183 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
5188 if (vcpu->arch.mmu.direct_map)
5191 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
5193 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
5197 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
5199 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
5201 LIST_HEAD(invalid_list);
5203 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
5206 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
5207 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
5210 ++vcpu->kvm->stat.mmu_recycled;
5212 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
5214 if (!kvm_mmu_available_pages(vcpu->kvm))
5219 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code,
5220 void *insn, int insn_len)
5222 int r, emulation_type = 0;
5223 enum emulation_result er;
5224 bool direct = vcpu->arch.mmu.direct_map;
5226 /* With shadow page tables, fault_address contains a GVA or nGPA. */
5227 if (vcpu->arch.mmu.direct_map) {
5228 vcpu->arch.gpa_available = true;
5229 vcpu->arch.gpa_val = cr2;
5233 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5234 r = handle_mmio_page_fault(vcpu, cr2, direct);
5235 if (r == RET_PF_EMULATE)
5239 if (r == RET_PF_INVALID) {
5240 r = vcpu->arch.mmu.page_fault(vcpu, cr2, lower_32_bits(error_code),
5242 WARN_ON(r == RET_PF_INVALID);
5245 if (r == RET_PF_RETRY)
5251 * Before emulating the instruction, check if the error code
5252 * was due to a RO violation while translating the guest page.
5253 * This can occur when using nested virtualization with nested
5254 * paging in both guests. If true, we simply unprotect the page
5255 * and resume the guest.
5257 if (vcpu->arch.mmu.direct_map &&
5258 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5259 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2));
5264 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5265 * optimistically try to just unprotect the page and let the processor
5266 * re-execute the instruction that caused the page fault. Do not allow
5267 * retrying MMIO emulation, as it's not only pointless but could also
5268 * cause us to enter an infinite loop because the processor will keep
5269 * faulting on the non-existent MMIO address. Retrying an instruction
5270 * from a nested guest is also pointless and dangerous as we are only
5271 * explicitly shadowing L1's page tables, i.e. unprotecting something
5272 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5274 if (!mmio_info_in_cache(vcpu, cr2, direct) && !is_guest_mode(vcpu))
5275 emulation_type = EMULTYPE_ALLOW_RETRY;
5278 * On AMD platforms, under certain conditions insn_len may be zero on #NPF.
5279 * This can happen if a guest gets a page-fault on data access but the HW
5280 * table walker is not able to read the instruction page (e.g instruction
5281 * page is not present in memory). In those cases we simply restart the
5284 if (unlikely(insn && !insn_len))
5287 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
5292 case EMULATE_USER_EXIT:
5293 ++vcpu->stat.mmio_exits;
5301 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5303 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5305 struct kvm_mmu *mmu = &vcpu->arch.mmu;
5308 /* INVLPG on a * non-canonical address is a NOP according to the SDM. */
5309 if (is_noncanonical_address(gva, vcpu))
5312 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5315 * INVLPG is required to invalidate any global mappings for the VA,
5316 * irrespective of PCID. Since it would take us roughly similar amount
5317 * of work to determine whether any of the prev_root mappings of the VA
5318 * is marked global, or to just sync it blindly, so we might as well
5319 * just always sync it.
5321 * Mappings not reachable via the current cr3 or the prev_roots will be
5322 * synced when switching to that cr3, so nothing needs to be done here
5325 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5326 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5327 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5329 kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5330 ++vcpu->stat.invlpg;
5332 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5334 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5336 struct kvm_mmu *mmu = &vcpu->arch.mmu;
5337 bool tlb_flush = false;
5340 if (pcid == kvm_get_active_pcid(vcpu)) {
5341 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5345 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5346 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5347 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].cr3)) {
5348 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5354 kvm_x86_ops->tlb_flush_gva(vcpu, gva);
5356 ++vcpu->stat.invlpg;
5359 * Mappings not reachable via the current cr3 or the prev_roots will be
5360 * synced when switching to that cr3, so nothing needs to be done here
5364 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva);
5366 void kvm_enable_tdp(void)
5370 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
5372 void kvm_disable_tdp(void)
5374 tdp_enabled = false;
5376 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
5378 static void free_mmu_pages(struct kvm_vcpu *vcpu)
5380 free_page((unsigned long)vcpu->arch.mmu.pae_root);
5381 free_page((unsigned long)vcpu->arch.mmu.lm_root);
5384 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
5393 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
5394 * Therefore we need to allocate shadow page tables in the first
5395 * 4GB of memory, which happens to fit the DMA32 zone.
5397 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
5401 vcpu->arch.mmu.pae_root = page_address(page);
5402 for (i = 0; i < 4; ++i)
5403 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
5408 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5412 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
5413 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
5414 vcpu->arch.mmu.translate_gpa = translate_gpa;
5415 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5417 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5418 vcpu->arch.mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5420 return alloc_mmu_pages(vcpu);
5423 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
5425 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
5428 * kvm_mmu_setup() is called only on vCPU initialization.
5429 * Therefore, no need to reset mmu roots as they are not yet
5432 kvm_init_mmu(vcpu, false);
5435 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5436 struct kvm_memory_slot *slot,
5437 struct kvm_page_track_notifier_node *node)
5439 kvm_mmu_invalidate_zap_all_pages(kvm);
5442 void kvm_mmu_init_vm(struct kvm *kvm)
5444 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5446 node->track_write = kvm_mmu_pte_write;
5447 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5448 kvm_page_track_register_notifier(kvm, node);
5451 void kvm_mmu_uninit_vm(struct kvm *kvm)
5453 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5455 kvm_page_track_unregister_notifier(kvm, node);
5458 /* The return value indicates if tlb flush on all vcpus is needed. */
5459 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5461 /* The caller should hold mmu-lock before calling this function. */
5462 static __always_inline bool
5463 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5464 slot_level_handler fn, int start_level, int end_level,
5465 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5467 struct slot_rmap_walk_iterator iterator;
5470 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5471 end_gfn, &iterator) {
5473 flush |= fn(kvm, iterator.rmap);
5475 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5476 if (flush && lock_flush_tlb) {
5477 kvm_flush_remote_tlbs(kvm);
5480 cond_resched_lock(&kvm->mmu_lock);
5484 if (flush && lock_flush_tlb) {
5485 kvm_flush_remote_tlbs(kvm);
5492 static __always_inline bool
5493 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5494 slot_level_handler fn, int start_level, int end_level,
5495 bool lock_flush_tlb)
5497 return slot_handle_level_range(kvm, memslot, fn, start_level,
5498 end_level, memslot->base_gfn,
5499 memslot->base_gfn + memslot->npages - 1,
5503 static __always_inline bool
5504 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5505 slot_level_handler fn, bool lock_flush_tlb)
5507 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5508 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5511 static __always_inline bool
5512 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5513 slot_level_handler fn, bool lock_flush_tlb)
5515 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
5516 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5519 static __always_inline bool
5520 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5521 slot_level_handler fn, bool lock_flush_tlb)
5523 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
5524 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
5527 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5529 struct kvm_memslots *slots;
5530 struct kvm_memory_slot *memslot;
5533 spin_lock(&kvm->mmu_lock);
5534 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5535 slots = __kvm_memslots(kvm, i);
5536 kvm_for_each_memslot(memslot, slots) {
5539 start = max(gfn_start, memslot->base_gfn);
5540 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5544 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5545 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
5546 start, end - 1, true);
5550 spin_unlock(&kvm->mmu_lock);
5553 static bool slot_rmap_write_protect(struct kvm *kvm,
5554 struct kvm_rmap_head *rmap_head)
5556 return __rmap_write_protect(kvm, rmap_head, false);
5559 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5560 struct kvm_memory_slot *memslot)
5564 spin_lock(&kvm->mmu_lock);
5565 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
5567 spin_unlock(&kvm->mmu_lock);
5570 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
5571 * which do tlb flush out of mmu-lock should be serialized by
5572 * kvm->slots_lock otherwise tlb flush would be missed.
5574 lockdep_assert_held(&kvm->slots_lock);
5577 * We can flush all the TLBs out of the mmu lock without TLB
5578 * corruption since we just change the spte from writable to
5579 * readonly so that we only need to care the case of changing
5580 * spte from present to present (changing the spte from present
5581 * to nonpresent will flush all the TLBs immediately), in other
5582 * words, the only case we care is mmu_spte_update() where we
5583 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5584 * instead of PT_WRITABLE_MASK, that means it does not depend
5585 * on PT_WRITABLE_MASK anymore.
5588 kvm_flush_remote_tlbs(kvm);
5591 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5592 struct kvm_rmap_head *rmap_head)
5595 struct rmap_iterator iter;
5596 int need_tlb_flush = 0;
5598 struct kvm_mmu_page *sp;
5601 for_each_rmap_spte(rmap_head, &iter, sptep) {
5602 sp = page_header(__pa(sptep));
5603 pfn = spte_to_pfn(*sptep);
5606 * We cannot do huge page mapping for indirect shadow pages,
5607 * which are found on the last rmap (level = 1) when not using
5608 * tdp; such shadow pages are synced with the page table in
5609 * the guest, and the guest page table is using 4K page size
5610 * mapping if the indirect sp has level = 1.
5612 if (sp->role.direct &&
5613 !kvm_is_reserved_pfn(pfn) &&
5614 PageTransCompoundMap(pfn_to_page(pfn))) {
5615 drop_spte(kvm, sptep);
5621 return need_tlb_flush;
5624 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5625 const struct kvm_memory_slot *memslot)
5627 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5628 spin_lock(&kvm->mmu_lock);
5629 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5630 kvm_mmu_zap_collapsible_spte, true);
5631 spin_unlock(&kvm->mmu_lock);
5634 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5635 struct kvm_memory_slot *memslot)
5639 spin_lock(&kvm->mmu_lock);
5640 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5641 spin_unlock(&kvm->mmu_lock);
5643 lockdep_assert_held(&kvm->slots_lock);
5646 * It's also safe to flush TLBs out of mmu lock here as currently this
5647 * function is only used for dirty logging, in which case flushing TLB
5648 * out of mmu lock also guarantees no dirty pages will be lost in
5652 kvm_flush_remote_tlbs(kvm);
5654 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5656 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5657 struct kvm_memory_slot *memslot)
5661 spin_lock(&kvm->mmu_lock);
5662 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5664 spin_unlock(&kvm->mmu_lock);
5666 /* see kvm_mmu_slot_remove_write_access */
5667 lockdep_assert_held(&kvm->slots_lock);
5670 kvm_flush_remote_tlbs(kvm);
5672 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5674 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5675 struct kvm_memory_slot *memslot)
5679 spin_lock(&kvm->mmu_lock);
5680 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
5681 spin_unlock(&kvm->mmu_lock);
5683 lockdep_assert_held(&kvm->slots_lock);
5685 /* see kvm_mmu_slot_leaf_clear_dirty */
5687 kvm_flush_remote_tlbs(kvm);
5689 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5691 #define BATCH_ZAP_PAGES 10
5692 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5694 struct kvm_mmu_page *sp, *node;
5698 list_for_each_entry_safe_reverse(sp, node,
5699 &kvm->arch.active_mmu_pages, link) {
5703 * No obsolete page exists before new created page since
5704 * active_mmu_pages is the FIFO list.
5706 if (!is_obsolete_sp(kvm, sp))
5710 * Since we are reversely walking the list and the invalid
5711 * list will be moved to the head, skip the invalid page
5712 * can help us to avoid the infinity list walking.
5714 if (sp->role.invalid)
5718 * Need not flush tlb since we only zap the sp with invalid
5719 * generation number.
5721 if (batch >= BATCH_ZAP_PAGES &&
5722 cond_resched_lock(&kvm->mmu_lock)) {
5727 ret = kvm_mmu_prepare_zap_page(kvm, sp,
5728 &kvm->arch.zapped_obsolete_pages);
5736 * Should flush tlb before free page tables since lockless-walking
5737 * may use the pages.
5739 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5743 * Fast invalidate all shadow pages and use lock-break technique
5744 * to zap obsolete pages.
5746 * It's required when memslot is being deleted or VM is being
5747 * destroyed, in these cases, we should ensure that KVM MMU does
5748 * not use any resource of the being-deleted slot or all slots
5749 * after calling the function.
5751 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
5753 spin_lock(&kvm->mmu_lock);
5754 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
5755 kvm->arch.mmu_valid_gen++;
5758 * Notify all vcpus to reload its shadow page table
5759 * and flush TLB. Then all vcpus will switch to new
5760 * shadow page table with the new mmu_valid_gen.
5762 * Note: we should do this under the protection of
5763 * mmu-lock, otherwise, vcpu would purge shadow page
5764 * but miss tlb flush.
5766 kvm_reload_remote_mmus(kvm);
5768 kvm_zap_obsolete_pages(kvm);
5769 spin_unlock(&kvm->mmu_lock);
5772 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5774 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5777 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots)
5780 * The very rare case: if the generation-number is round,
5781 * zap all shadow pages.
5783 if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) {
5784 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5785 kvm_mmu_invalidate_zap_all_pages(kvm);
5789 static unsigned long
5790 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5793 int nr_to_scan = sc->nr_to_scan;
5794 unsigned long freed = 0;
5796 spin_lock(&kvm_lock);
5798 list_for_each_entry(kvm, &vm_list, vm_list) {
5800 LIST_HEAD(invalid_list);
5803 * Never scan more than sc->nr_to_scan VM instances.
5804 * Will not hit this condition practically since we do not try
5805 * to shrink more than one VM and it is very unlikely to see
5806 * !n_used_mmu_pages so many times.
5811 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5812 * here. We may skip a VM instance errorneosly, but we do not
5813 * want to shrink a VM that only started to populate its MMU
5816 if (!kvm->arch.n_used_mmu_pages &&
5817 !kvm_has_zapped_obsolete_pages(kvm))
5820 idx = srcu_read_lock(&kvm->srcu);
5821 spin_lock(&kvm->mmu_lock);
5823 if (kvm_has_zapped_obsolete_pages(kvm)) {
5824 kvm_mmu_commit_zap_page(kvm,
5825 &kvm->arch.zapped_obsolete_pages);
5829 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
5831 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5834 spin_unlock(&kvm->mmu_lock);
5835 srcu_read_unlock(&kvm->srcu, idx);
5838 * unfair on small ones
5839 * per-vm shrinkers cry out
5840 * sadness comes quickly
5842 list_move_tail(&kvm->vm_list, &vm_list);
5846 spin_unlock(&kvm_lock);
5850 static unsigned long
5851 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5853 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5856 static struct shrinker mmu_shrinker = {
5857 .count_objects = mmu_shrink_count,
5858 .scan_objects = mmu_shrink_scan,
5859 .seeks = DEFAULT_SEEKS * 10,
5862 static void mmu_destroy_caches(void)
5864 kmem_cache_destroy(pte_list_desc_cache);
5865 kmem_cache_destroy(mmu_page_header_cache);
5868 int kvm_mmu_module_init(void)
5872 kvm_mmu_reset_all_pte_masks();
5874 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5875 sizeof(struct pte_list_desc),
5876 0, SLAB_ACCOUNT, NULL);
5877 if (!pte_list_desc_cache)
5880 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5881 sizeof(struct kvm_mmu_page),
5882 0, SLAB_ACCOUNT, NULL);
5883 if (!mmu_page_header_cache)
5886 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5889 ret = register_shrinker(&mmu_shrinker);
5896 mmu_destroy_caches();
5901 * Caculate mmu pages needed for kvm.
5903 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
5905 unsigned int nr_mmu_pages;
5906 unsigned int nr_pages = 0;
5907 struct kvm_memslots *slots;
5908 struct kvm_memory_slot *memslot;
5911 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5912 slots = __kvm_memslots(kvm, i);
5914 kvm_for_each_memslot(memslot, slots)
5915 nr_pages += memslot->npages;
5918 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5919 nr_mmu_pages = max(nr_mmu_pages,
5920 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
5922 return nr_mmu_pages;
5925 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5927 kvm_mmu_unload(vcpu);
5928 free_mmu_pages(vcpu);
5929 mmu_free_memory_caches(vcpu);
5932 void kvm_mmu_module_exit(void)
5934 mmu_destroy_caches();
5935 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5936 unregister_shrinker(&mmu_shrinker);
5937 mmu_audit_disable();