Merge branch 'x86/cpufeature' into irq/numa
[sfrench/cifs-2.6.git] / arch / x86 / kvm / i8254.c
1 /*
2  * 8253/8254 interval timer emulation
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  * Copyright (c) 2006 Intel Corporation
6  * Copyright (c) 2007 Keir Fraser, XenSource Inc
7  * Copyright (c) 2008 Intel Corporation
8  *
9  * Permission is hereby granted, free of charge, to any person obtaining a copy
10  * of this software and associated documentation files (the "Software"), to deal
11  * in the Software without restriction, including without limitation the rights
12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13  * copies of the Software, and to permit persons to whom the Software is
14  * furnished to do so, subject to the following conditions:
15  *
16  * The above copyright notice and this permission notice shall be included in
17  * all copies or substantial portions of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25  * THE SOFTWARE.
26  *
27  * Authors:
28  *   Sheng Yang <sheng.yang@intel.com>
29  *   Based on QEMU and Xen.
30  */
31
32 #include <linux/kvm_host.h>
33
34 #include "irq.h"
35 #include "i8254.h"
36
37 #ifndef CONFIG_X86_64
38 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
39 #else
40 #define mod_64(x, y) ((x) % (y))
41 #endif
42
43 #define RW_STATE_LSB 1
44 #define RW_STATE_MSB 2
45 #define RW_STATE_WORD0 3
46 #define RW_STATE_WORD1 4
47
48 /* Compute with 96 bit intermediate result: (a*b)/c */
49 static u64 muldiv64(u64 a, u32 b, u32 c)
50 {
51         union {
52                 u64 ll;
53                 struct {
54                         u32 low, high;
55                 } l;
56         } u, res;
57         u64 rl, rh;
58
59         u.ll = a;
60         rl = (u64)u.l.low * (u64)b;
61         rh = (u64)u.l.high * (u64)b;
62         rh += (rl >> 32);
63         res.l.high = div64_u64(rh, c);
64         res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
65         return res.ll;
66 }
67
68 static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
69 {
70         struct kvm_kpit_channel_state *c =
71                 &kvm->arch.vpit->pit_state.channels[channel];
72
73         WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
74
75         switch (c->mode) {
76         default:
77         case 0:
78         case 4:
79                 /* XXX: just disable/enable counting */
80                 break;
81         case 1:
82         case 2:
83         case 3:
84         case 5:
85                 /* Restart counting on rising edge. */
86                 if (c->gate < val)
87                         c->count_load_time = ktime_get();
88                 break;
89         }
90
91         c->gate = val;
92 }
93
94 static int pit_get_gate(struct kvm *kvm, int channel)
95 {
96         WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
97
98         return kvm->arch.vpit->pit_state.channels[channel].gate;
99 }
100
101 static int pit_get_count(struct kvm *kvm, int channel)
102 {
103         struct kvm_kpit_channel_state *c =
104                 &kvm->arch.vpit->pit_state.channels[channel];
105         s64 d, t;
106         int counter;
107
108         WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
109
110         t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
111         d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
112
113         switch (c->mode) {
114         case 0:
115         case 1:
116         case 4:
117         case 5:
118                 counter = (c->count - d) & 0xffff;
119                 break;
120         case 3:
121                 /* XXX: may be incorrect for odd counts */
122                 counter = c->count - (mod_64((2 * d), c->count));
123                 break;
124         default:
125                 counter = c->count - mod_64(d, c->count);
126                 break;
127         }
128         return counter;
129 }
130
131 static int pit_get_out(struct kvm *kvm, int channel)
132 {
133         struct kvm_kpit_channel_state *c =
134                 &kvm->arch.vpit->pit_state.channels[channel];
135         s64 d, t;
136         int out;
137
138         WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
139
140         t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
141         d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
142
143         switch (c->mode) {
144         default:
145         case 0:
146                 out = (d >= c->count);
147                 break;
148         case 1:
149                 out = (d < c->count);
150                 break;
151         case 2:
152                 out = ((mod_64(d, c->count) == 0) && (d != 0));
153                 break;
154         case 3:
155                 out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
156                 break;
157         case 4:
158         case 5:
159                 out = (d == c->count);
160                 break;
161         }
162
163         return out;
164 }
165
166 static void pit_latch_count(struct kvm *kvm, int channel)
167 {
168         struct kvm_kpit_channel_state *c =
169                 &kvm->arch.vpit->pit_state.channels[channel];
170
171         WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
172
173         if (!c->count_latched) {
174                 c->latched_count = pit_get_count(kvm, channel);
175                 c->count_latched = c->rw_mode;
176         }
177 }
178
179 static void pit_latch_status(struct kvm *kvm, int channel)
180 {
181         struct kvm_kpit_channel_state *c =
182                 &kvm->arch.vpit->pit_state.channels[channel];
183
184         WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
185
186         if (!c->status_latched) {
187                 /* TODO: Return NULL COUNT (bit 6). */
188                 c->status = ((pit_get_out(kvm, channel) << 7) |
189                                 (c->rw_mode << 4) |
190                                 (c->mode << 1) |
191                                 c->bcd);
192                 c->status_latched = 1;
193         }
194 }
195
196 static int __pit_timer_fn(struct kvm_kpit_state *ps)
197 {
198         struct kvm_vcpu *vcpu0 = ps->pit->kvm->vcpus[0];
199         struct kvm_kpit_timer *pt = &ps->pit_timer;
200
201         if (!atomic_inc_and_test(&pt->pending))
202                 set_bit(KVM_REQ_PENDING_TIMER, &vcpu0->requests);
203
204         if (!pt->reinject)
205                 atomic_set(&pt->pending, 1);
206
207         if (vcpu0 && waitqueue_active(&vcpu0->wq))
208                 wake_up_interruptible(&vcpu0->wq);
209
210         hrtimer_add_expires_ns(&pt->timer, pt->period);
211         pt->scheduled = hrtimer_get_expires_ns(&pt->timer);
212         if (pt->period)
213                 ps->channels[0].count_load_time = ktime_get();
214
215         return (pt->period == 0 ? 0 : 1);
216 }
217
218 int pit_has_pending_timer(struct kvm_vcpu *vcpu)
219 {
220         struct kvm_pit *pit = vcpu->kvm->arch.vpit;
221
222         if (pit && vcpu->vcpu_id == 0 && pit->pit_state.irq_ack)
223                 return atomic_read(&pit->pit_state.pit_timer.pending);
224         return 0;
225 }
226
227 static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian)
228 {
229         struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state,
230                                                  irq_ack_notifier);
231         spin_lock(&ps->inject_lock);
232         if (atomic_dec_return(&ps->pit_timer.pending) < 0)
233                 atomic_inc(&ps->pit_timer.pending);
234         ps->irq_ack = 1;
235         spin_unlock(&ps->inject_lock);
236 }
237
238 static enum hrtimer_restart pit_timer_fn(struct hrtimer *data)
239 {
240         struct kvm_kpit_state *ps;
241         int restart_timer = 0;
242
243         ps = container_of(data, struct kvm_kpit_state, pit_timer.timer);
244
245         restart_timer = __pit_timer_fn(ps);
246
247         if (restart_timer)
248                 return HRTIMER_RESTART;
249         else
250                 return HRTIMER_NORESTART;
251 }
252
253 void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
254 {
255         struct kvm_pit *pit = vcpu->kvm->arch.vpit;
256         struct hrtimer *timer;
257
258         if (vcpu->vcpu_id != 0 || !pit)
259                 return;
260
261         timer = &pit->pit_state.pit_timer.timer;
262         if (hrtimer_cancel(timer))
263                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
264 }
265
266 static void destroy_pit_timer(struct kvm_kpit_timer *pt)
267 {
268         pr_debug("pit: execute del timer!\n");
269         hrtimer_cancel(&pt->timer);
270 }
271
272 static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
273 {
274         struct kvm_kpit_timer *pt = &ps->pit_timer;
275         s64 interval;
276
277         interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);
278
279         pr_debug("pit: create pit timer, interval is %llu nsec\n", interval);
280
281         /* TODO The new value only affected after the retriggered */
282         hrtimer_cancel(&pt->timer);
283         pt->period = (is_period == 0) ? 0 : interval;
284         pt->timer.function = pit_timer_fn;
285         atomic_set(&pt->pending, 0);
286         ps->irq_ack = 1;
287
288         hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
289                       HRTIMER_MODE_ABS);
290 }
291
292 static void pit_load_count(struct kvm *kvm, int channel, u32 val)
293 {
294         struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
295
296         WARN_ON(!mutex_is_locked(&ps->lock));
297
298         pr_debug("pit: load_count val is %d, channel is %d\n", val, channel);
299
300         /*
301          * Though spec said the state of 8254 is undefined after power-up,
302          * seems some tricky OS like Windows XP depends on IRQ0 interrupt
303          * when booting up.
304          * So here setting initialize rate for it, and not a specific number
305          */
306         if (val == 0)
307                 val = 0x10000;
308
309         ps->channels[channel].count_load_time = ktime_get();
310         ps->channels[channel].count = val;
311
312         if (channel != 0)
313                 return;
314
315         /* Two types of timer
316          * mode 1 is one shot, mode 2 is period, otherwise del timer */
317         switch (ps->channels[0].mode) {
318         case 1:
319         /* FIXME: enhance mode 4 precision */
320         case 4:
321                 create_pit_timer(ps, val, 0);
322                 break;
323         case 2:
324         case 3:
325                 create_pit_timer(ps, val, 1);
326                 break;
327         default:
328                 destroy_pit_timer(&ps->pit_timer);
329         }
330 }
331
332 void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val)
333 {
334         mutex_lock(&kvm->arch.vpit->pit_state.lock);
335         pit_load_count(kvm, channel, val);
336         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
337 }
338
339 static void pit_ioport_write(struct kvm_io_device *this,
340                              gpa_t addr, int len, const void *data)
341 {
342         struct kvm_pit *pit = (struct kvm_pit *)this->private;
343         struct kvm_kpit_state *pit_state = &pit->pit_state;
344         struct kvm *kvm = pit->kvm;
345         int channel, access;
346         struct kvm_kpit_channel_state *s;
347         u32 val = *(u32 *) data;
348
349         val  &= 0xff;
350         addr &= KVM_PIT_CHANNEL_MASK;
351
352         mutex_lock(&pit_state->lock);
353
354         if (val != 0)
355                 pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n",
356                           (unsigned int)addr, len, val);
357
358         if (addr == 3) {
359                 channel = val >> 6;
360                 if (channel == 3) {
361                         /* Read-Back Command. */
362                         for (channel = 0; channel < 3; channel++) {
363                                 s = &pit_state->channels[channel];
364                                 if (val & (2 << channel)) {
365                                         if (!(val & 0x20))
366                                                 pit_latch_count(kvm, channel);
367                                         if (!(val & 0x10))
368                                                 pit_latch_status(kvm, channel);
369                                 }
370                         }
371                 } else {
372                         /* Select Counter <channel>. */
373                         s = &pit_state->channels[channel];
374                         access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
375                         if (access == 0) {
376                                 pit_latch_count(kvm, channel);
377                         } else {
378                                 s->rw_mode = access;
379                                 s->read_state = access;
380                                 s->write_state = access;
381                                 s->mode = (val >> 1) & 7;
382                                 if (s->mode > 5)
383                                         s->mode -= 4;
384                                 s->bcd = val & 1;
385                         }
386                 }
387         } else {
388                 /* Write Count. */
389                 s = &pit_state->channels[addr];
390                 switch (s->write_state) {
391                 default:
392                 case RW_STATE_LSB:
393                         pit_load_count(kvm, addr, val);
394                         break;
395                 case RW_STATE_MSB:
396                         pit_load_count(kvm, addr, val << 8);
397                         break;
398                 case RW_STATE_WORD0:
399                         s->write_latch = val;
400                         s->write_state = RW_STATE_WORD1;
401                         break;
402                 case RW_STATE_WORD1:
403                         pit_load_count(kvm, addr, s->write_latch | (val << 8));
404                         s->write_state = RW_STATE_WORD0;
405                         break;
406                 }
407         }
408
409         mutex_unlock(&pit_state->lock);
410 }
411
412 static void pit_ioport_read(struct kvm_io_device *this,
413                             gpa_t addr, int len, void *data)
414 {
415         struct kvm_pit *pit = (struct kvm_pit *)this->private;
416         struct kvm_kpit_state *pit_state = &pit->pit_state;
417         struct kvm *kvm = pit->kvm;
418         int ret, count;
419         struct kvm_kpit_channel_state *s;
420
421         addr &= KVM_PIT_CHANNEL_MASK;
422         s = &pit_state->channels[addr];
423
424         mutex_lock(&pit_state->lock);
425
426         if (s->status_latched) {
427                 s->status_latched = 0;
428                 ret = s->status;
429         } else if (s->count_latched) {
430                 switch (s->count_latched) {
431                 default:
432                 case RW_STATE_LSB:
433                         ret = s->latched_count & 0xff;
434                         s->count_latched = 0;
435                         break;
436                 case RW_STATE_MSB:
437                         ret = s->latched_count >> 8;
438                         s->count_latched = 0;
439                         break;
440                 case RW_STATE_WORD0:
441                         ret = s->latched_count & 0xff;
442                         s->count_latched = RW_STATE_MSB;
443                         break;
444                 }
445         } else {
446                 switch (s->read_state) {
447                 default:
448                 case RW_STATE_LSB:
449                         count = pit_get_count(kvm, addr);
450                         ret = count & 0xff;
451                         break;
452                 case RW_STATE_MSB:
453                         count = pit_get_count(kvm, addr);
454                         ret = (count >> 8) & 0xff;
455                         break;
456                 case RW_STATE_WORD0:
457                         count = pit_get_count(kvm, addr);
458                         ret = count & 0xff;
459                         s->read_state = RW_STATE_WORD1;
460                         break;
461                 case RW_STATE_WORD1:
462                         count = pit_get_count(kvm, addr);
463                         ret = (count >> 8) & 0xff;
464                         s->read_state = RW_STATE_WORD0;
465                         break;
466                 }
467         }
468
469         if (len > sizeof(ret))
470                 len = sizeof(ret);
471         memcpy(data, (char *)&ret, len);
472
473         mutex_unlock(&pit_state->lock);
474 }
475
476 static int pit_in_range(struct kvm_io_device *this, gpa_t addr,
477                         int len, int is_write)
478 {
479         return ((addr >= KVM_PIT_BASE_ADDRESS) &&
480                 (addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
481 }
482
483 static void speaker_ioport_write(struct kvm_io_device *this,
484                                  gpa_t addr, int len, const void *data)
485 {
486         struct kvm_pit *pit = (struct kvm_pit *)this->private;
487         struct kvm_kpit_state *pit_state = &pit->pit_state;
488         struct kvm *kvm = pit->kvm;
489         u32 val = *(u32 *) data;
490
491         mutex_lock(&pit_state->lock);
492         pit_state->speaker_data_on = (val >> 1) & 1;
493         pit_set_gate(kvm, 2, val & 1);
494         mutex_unlock(&pit_state->lock);
495 }
496
497 static void speaker_ioport_read(struct kvm_io_device *this,
498                                 gpa_t addr, int len, void *data)
499 {
500         struct kvm_pit *pit = (struct kvm_pit *)this->private;
501         struct kvm_kpit_state *pit_state = &pit->pit_state;
502         struct kvm *kvm = pit->kvm;
503         unsigned int refresh_clock;
504         int ret;
505
506         /* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
507         refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;
508
509         mutex_lock(&pit_state->lock);
510         ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(kvm, 2) |
511                 (pit_get_out(kvm, 2) << 5) | (refresh_clock << 4));
512         if (len > sizeof(ret))
513                 len = sizeof(ret);
514         memcpy(data, (char *)&ret, len);
515         mutex_unlock(&pit_state->lock);
516 }
517
518 static int speaker_in_range(struct kvm_io_device *this, gpa_t addr,
519                             int len, int is_write)
520 {
521         return (addr == KVM_SPEAKER_BASE_ADDRESS);
522 }
523
524 void kvm_pit_reset(struct kvm_pit *pit)
525 {
526         int i;
527         struct kvm_kpit_channel_state *c;
528
529         mutex_lock(&pit->pit_state.lock);
530         for (i = 0; i < 3; i++) {
531                 c = &pit->pit_state.channels[i];
532                 c->mode = 0xff;
533                 c->gate = (i != 2);
534                 pit_load_count(pit->kvm, i, 0);
535         }
536         mutex_unlock(&pit->pit_state.lock);
537
538         atomic_set(&pit->pit_state.pit_timer.pending, 0);
539         pit->pit_state.irq_ack = 1;
540 }
541
542 static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask)
543 {
544         struct kvm_pit *pit = container_of(kimn, struct kvm_pit, mask_notifier);
545
546         if (!mask) {
547                 atomic_set(&pit->pit_state.pit_timer.pending, 0);
548                 pit->pit_state.irq_ack = 1;
549         }
550 }
551
552 struct kvm_pit *kvm_create_pit(struct kvm *kvm)
553 {
554         struct kvm_pit *pit;
555         struct kvm_kpit_state *pit_state;
556
557         pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
558         if (!pit)
559                 return NULL;
560
561         pit->irq_source_id = kvm_request_irq_source_id(kvm);
562         if (pit->irq_source_id < 0) {
563                 kfree(pit);
564                 return NULL;
565         }
566
567         mutex_init(&pit->pit_state.lock);
568         mutex_lock(&pit->pit_state.lock);
569         spin_lock_init(&pit->pit_state.inject_lock);
570
571         /* Initialize PIO device */
572         pit->dev.read = pit_ioport_read;
573         pit->dev.write = pit_ioport_write;
574         pit->dev.in_range = pit_in_range;
575         pit->dev.private = pit;
576         kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);
577
578         pit->speaker_dev.read = speaker_ioport_read;
579         pit->speaker_dev.write = speaker_ioport_write;
580         pit->speaker_dev.in_range = speaker_in_range;
581         pit->speaker_dev.private = pit;
582         kvm_io_bus_register_dev(&kvm->pio_bus, &pit->speaker_dev);
583
584         kvm->arch.vpit = pit;
585         pit->kvm = kvm;
586
587         pit_state = &pit->pit_state;
588         pit_state->pit = pit;
589         hrtimer_init(&pit_state->pit_timer.timer,
590                      CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
591         pit_state->irq_ack_notifier.gsi = 0;
592         pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq;
593         kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier);
594         pit_state->pit_timer.reinject = true;
595         mutex_unlock(&pit->pit_state.lock);
596
597         kvm_pit_reset(pit);
598
599         pit->mask_notifier.func = pit_mask_notifer;
600         kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
601
602         return pit;
603 }
604
605 void kvm_free_pit(struct kvm *kvm)
606 {
607         struct hrtimer *timer;
608
609         if (kvm->arch.vpit) {
610                 kvm_unregister_irq_mask_notifier(kvm, 0,
611                                                &kvm->arch.vpit->mask_notifier);
612                 mutex_lock(&kvm->arch.vpit->pit_state.lock);
613                 timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
614                 hrtimer_cancel(timer);
615                 kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id);
616                 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
617                 kfree(kvm->arch.vpit);
618         }
619 }
620
621 static void __inject_pit_timer_intr(struct kvm *kvm)
622 {
623         struct kvm_vcpu *vcpu;
624         int i;
625
626         mutex_lock(&kvm->lock);
627         kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
628         kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
629         mutex_unlock(&kvm->lock);
630
631         /*
632          * Provides NMI watchdog support via Virtual Wire mode.
633          * The route is: PIT -> PIC -> LVT0 in NMI mode.
634          *
635          * Note: Our Virtual Wire implementation is simplified, only
636          * propagating PIT interrupts to all VCPUs when they have set
637          * LVT0 to NMI delivery. Other PIC interrupts are just sent to
638          * VCPU0, and only if its LVT0 is in EXTINT mode.
639          */
640         if (kvm->arch.vapics_in_nmi_mode > 0)
641                 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
642                         vcpu = kvm->vcpus[i];
643                         if (vcpu)
644                                 kvm_apic_nmi_wd_deliver(vcpu);
645                 }
646 }
647
648 void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
649 {
650         struct kvm_pit *pit = vcpu->kvm->arch.vpit;
651         struct kvm *kvm = vcpu->kvm;
652         struct kvm_kpit_state *ps;
653
654         if (vcpu && pit) {
655                 int inject = 0;
656                 ps = &pit->pit_state;
657
658                 /* Try to inject pending interrupts when
659                  * last one has been acked.
660                  */
661                 spin_lock(&ps->inject_lock);
662                 if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) {
663                         ps->irq_ack = 0;
664                         inject = 1;
665                 }
666                 spin_unlock(&ps->inject_lock);
667                 if (inject)
668                         __inject_pit_timer_intr(kvm);
669         }
670 }