arch/x86/kernel/io_apic_32.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/mc146818rtc.h>
  29 #include <linux/compiler.h>
  30 #include <linux/acpi.h>
  31 #include <linux/module.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/pci.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39
  40 #include <asm/io.h>
  41 #include <asm/smp.h>
  42 #include <asm/desc.h>
  43 #include <asm/timer.h>
  44 #include <asm/i8259.h>
  45 #include <asm/nmi.h>
  46 #include <asm/msidef.h>
  47 #include <asm/hypertransport.h>
  48
  49 #include <mach_apic.h>
  50 #include <mach_apicdef.h>
  51
  52 int (*ioapic_renumber_irq)(int ioapic, int irq);
  53 atomic_t irq_mis_count;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59 static DEFINE_SPINLOCK(vector_lock);
  60
  61 int timer_over_8254 __initdata = 1;
  62
  63 /*
  64  *      Is the SiS APIC rmw bug present ?
  65  *      -1 = don't know, 0 = no, 1 = yes
  66  */
  67 int sis_apic_bug = -1;
  68
  69 /*
  70  * # of IRQ routing registers
  71  */
  72 int nr_ioapic_registers[MAX_IO_APICS];
  73
  74 static int disable_timer_pin_1 __initdata;
  75
  76 /*
  77  * Rough estimation of how many shared IRQs there are, can
  78  * be changed anytime.
  79  */
  80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  82
  83 /*
  84  * This is performance-critical, we want to do it O(1)
  85  *
  86  * the indexing order of this array favors 1:1 mappings
  87  * between pins and IRQs.
  88  */
  89
  90 static struct irq_pin_list {
  91         int apic, pin, next;
  92 } irq_2_pin[PIN_MAP_SIZE];
  93
  94 struct io_apic {
  95         unsigned int index;
  96         unsigned int unused[3];
  97         unsigned int data;
  98 };
  99
 100 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 101 {
 102         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 103                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 104 }
 105
 106 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 107 {
 108         struct io_apic __iomem *io_apic = io_apic_base(apic);
 109         writel(reg, &io_apic->index);
 110         return readl(&io_apic->data);
 111 }
 112
 113 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 114 {
 115         struct io_apic __iomem *io_apic = io_apic_base(apic);
 116         writel(reg, &io_apic->index);
 117         writel(value, &io_apic->data);
 118 }
 119
 120 /*
 121  * Re-write a value: to be used for read-modify-write
 122  * cycles where the read already set up the index register.
 123  *
 124  * Older SiS APIC requires we rewrite the index register
 125  */
 126 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 127 {
 128         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
 129         if (sis_apic_bug)
 130                 writel(reg, &io_apic->index);
 131         writel(value, &io_apic->data);
 132 }
 133
 134 union entry_union {
 135         struct { u32 w1, w2; };
 136         struct IO_APIC_route_entry entry;
 137 };
 138
 139 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 140 {
 141         union entry_union eu;
 142         unsigned long flags;
 143         spin_lock_irqsave(&ioapic_lock, flags);
 144         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 145         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 146         spin_unlock_irqrestore(&ioapic_lock, flags);
 147         return eu.entry;
 148 }
 149
 150 /*
 151  * When we write a new IO APIC routing entry, we need to write the high
 152  * word first! If the mask bit in the low word is clear, we will enable
 153  * the interrupt, and we need to make sure the entry is fully populated
 154  * before that happens.
 155  */
 156 static void
 157 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 158 {
 159         union entry_union eu;
 160         eu.entry = e;
 161         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 162         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 163 }
 164
 165 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 166 {
 167         unsigned long flags;
 168         spin_lock_irqsave(&ioapic_lock, flags);
 169         __ioapic_write_entry(apic, pin, e);
 170         spin_unlock_irqrestore(&ioapic_lock, flags);
 171 }
 172
 173 /*
 174  * When we mask an IO APIC routing entry, we need to write the low
 175  * word first, in order to set the mask bit before we change the
 176  * high bits!
 177  */
 178 static void ioapic_mask_entry(int apic, int pin)
 179 {
 180         unsigned long flags;
 181         union entry_union eu = { .entry.mask = 1 };
 182
 183         spin_lock_irqsave(&ioapic_lock, flags);
 184         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 185         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 186         spin_unlock_irqrestore(&ioapic_lock, flags);
 187 }
 188
 189 /*
 190  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 191  * shared ISA-space IRQs, so we have to support them. We are super
 192  * fast in the common case, and fast for shared ISA-space IRQs.
 193  */
 194 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 195 {
 196         static int first_free_entry = NR_IRQS;
 197         struct irq_pin_list *entry = irq_2_pin + irq;
 198
 199         while (entry->next)
 200                 entry = irq_2_pin + entry->next;
 201
 202         if (entry->pin != -1) {
 203                 entry->next = first_free_entry;
 204                 entry = irq_2_pin + entry->next;
 205                 if (++first_free_entry >= PIN_MAP_SIZE)
 206                         panic("io_apic.c: whoops");
 207         }
 208         entry->apic = apic;
 209         entry->pin = pin;
 210 }
 211
 212 /*
 213  * Reroute an IRQ to a different pin.
 214  */
 215 static void __init replace_pin_at_irq(unsigned int irq,
 216                                       int oldapic, int oldpin,
 217                                       int newapic, int newpin)
 218 {
 219         struct irq_pin_list *entry = irq_2_pin + irq;
 220
 221         while (1) {
 222                 if (entry->apic == oldapic && entry->pin == oldpin) {
 223                         entry->apic = newapic;
 224                         entry->pin = newpin;
 225                 }
 226                 if (!entry->next)
 227                         break;
 228                 entry = irq_2_pin + entry->next;
 229         }
 230 }
 231
 232 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 233 {
 234         struct irq_pin_list *entry = irq_2_pin + irq;
 235         unsigned int pin, reg;
 236
 237         for (;;) {
 238                 pin = entry->pin;
 239                 if (pin == -1)
 240                         break;
 241                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 242                 reg &= ~disable;
 243                 reg |= enable;
 244                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 245                 if (!entry->next)
 246                         break;
 247                 entry = irq_2_pin + entry->next;
 248         }
 249 }
 250
 251 /* mask = 1 */
 252 static void __mask_IO_APIC_irq (unsigned int irq)
 253 {
 254         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 255 }
 256
 257 /* mask = 0 */
 258 static void __unmask_IO_APIC_irq (unsigned int irq)
 259 {
 260         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 261 }
 262
 263 /* mask = 1, trigger = 0 */
 264 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 265 {
 266         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 267 }
 268
 269 /* mask = 0, trigger = 1 */
 270 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 271 {
 272         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 273 }
 274
 275 static void mask_IO_APIC_irq (unsigned int irq)
 276 {
 277         unsigned long flags;
 278
 279         spin_lock_irqsave(&ioapic_lock, flags);
 280         __mask_IO_APIC_irq(irq);
 281         spin_unlock_irqrestore(&ioapic_lock, flags);
 282 }
 283
 284 static void unmask_IO_APIC_irq (unsigned int irq)
 285 {
 286         unsigned long flags;
 287
 288         spin_lock_irqsave(&ioapic_lock, flags);
 289         __unmask_IO_APIC_irq(irq);
 290         spin_unlock_irqrestore(&ioapic_lock, flags);
 291 }
 292
 293 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 294 {
 295         struct IO_APIC_route_entry entry;
 296
 297         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 298         entry = ioapic_read_entry(apic, pin);
 299         if (entry.delivery_mode == dest_SMI)
 300                 return;
 301
 302         /*
 303          * Disable it in the IO-APIC irq-routing table:
 304          */
 305         ioapic_mask_entry(apic, pin);
 306 }
 307
 308 static void clear_IO_APIC (void)
 309 {
 310         int apic, pin;
 311
 312         for (apic = 0; apic < nr_ioapics; apic++)
 313                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 314                         clear_IO_APIC_pin(apic, pin);
 315 }
 316
 317 #ifdef CONFIG_SMP
 318 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 319 {
 320         unsigned long flags;
 321         int pin;
 322         struct irq_pin_list *entry = irq_2_pin + irq;
 323         unsigned int apicid_value;
 324         cpumask_t tmp;
 325
 326         cpus_and(tmp, cpumask, cpu_online_map);
 327         if (cpus_empty(tmp))
 328                 tmp = TARGET_CPUS;
 329
 330         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 331
 332         apicid_value = cpu_mask_to_apicid(cpumask);
 333         /* Prepare to do the io_apic_write */
 334         apicid_value = apicid_value << 24;
 335         spin_lock_irqsave(&ioapic_lock, flags);
 336         for (;;) {
 337                 pin = entry->pin;
 338                 if (pin == -1)
 339                         break;
 340                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 341                 if (!entry->next)
 342                         break;
 343                 entry = irq_2_pin + entry->next;
 344         }
 345         irq_desc[irq].affinity = cpumask;
 346         spin_unlock_irqrestore(&ioapic_lock, flags);
 347 }
 348
 349 #if defined(CONFIG_IRQBALANCE)
 350 # include <asm/processor.h>     /* kernel_thread() */
 351 # include <linux/kernel_stat.h> /* kstat */
 352 # include <linux/slab.h>                /* kmalloc() */
 353 # include <linux/timer.h>
 354
 355 #define IRQBALANCE_CHECK_ARCH -999
 356 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 357 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 358 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 359 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 360
 361 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 362 static int physical_balance __read_mostly;
 363 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 364
 365 static struct irq_cpu_info {
 366         unsigned long * last_irq;
 367         unsigned long * irq_delta;
 368         unsigned long irq;
 369 } irq_cpu_data[NR_CPUS];
 370
 371 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 372 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 373 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 374
 375 #define IDLE_ENOUGH(cpu,now) \
 376         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 377
 378 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 379
 380 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
 381
 382 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 383         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 384 };
 385
 386 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 387 {
 388         balance_irq_affinity[irq] = mask;
 389 }
 390
 391 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 392                         unsigned long now, int direction)
 393 {
 394         int search_idle = 1;
 395         int cpu = curr_cpu;
 396
 397         goto inside;
 398
 399         do {
 400                 if (unlikely(cpu == curr_cpu))
 401                         search_idle = 0;
 402 inside:
 403                 if (direction == 1) {
 404                         cpu++;
 405                         if (cpu >= NR_CPUS)
 406                                 cpu = 0;
 407                 } else {
 408                         cpu--;
 409                         if (cpu == -1)
 410                                 cpu = NR_CPUS-1;
 411                 }
 412         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 413                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 414
 415         return cpu;
 416 }
 417
 418 static inline void balance_irq(int cpu, int irq)
 419 {
 420         unsigned long now = jiffies;
 421         cpumask_t allowed_mask;
 422         unsigned int new_cpu;
 423
 424         if (irqbalance_disabled)
 425                 return;
 426
 427         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 428         new_cpu = move(cpu, allowed_mask, now, 1);
 429         if (cpu != new_cpu) {
 430                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 431         }
 432 }
 433
 434 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 435 {
 436         int i, j;
 437
 438         for_each_online_cpu(i) {
 439                 for (j = 0; j < NR_IRQS; j++) {
 440                         if (!irq_desc[j].action)
 441                                 continue;
 442                         /* Is it a significant load ?  */
 443                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 444                                                 useful_load_threshold)
 445                                 continue;
 446                         balance_irq(i, j);
 447                 }
 448         }
 449         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 450                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 451         return;
 452 }
 453
 454 static void do_irq_balance(void)
 455 {
 456         int i, j;
 457         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 458         unsigned long move_this_load = 0;
 459         int max_loaded = 0, min_loaded = 0;
 460         int load;
 461         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 462         int selected_irq;
 463         int tmp_loaded, first_attempt = 1;
 464         unsigned long tmp_cpu_irq;
 465         unsigned long imbalance = 0;
 466         cpumask_t allowed_mask, target_cpu_mask, tmp;
 467
 468         for_each_possible_cpu(i) {
 469                 int package_index;
 470                 CPU_IRQ(i) = 0;
 471                 if (!cpu_online(i))
 472                         continue;
 473                 package_index = CPU_TO_PACKAGEINDEX(i);
 474                 for (j = 0; j < NR_IRQS; j++) {
 475                         unsigned long value_now, delta;
 476                         /* Is this an active IRQ or balancing disabled ? */
 477                         if (!irq_desc[j].action || irq_balancing_disabled(j))
 478                                 continue;
 479                         if ( package_index == i )
 480                                 IRQ_DELTA(package_index,j) = 0;
 481                         /* Determine the total count per processor per IRQ */
 482                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 483
 484                         /* Determine the activity per processor per IRQ */
 485                         delta = value_now - LAST_CPU_IRQ(i,j);
 486
 487                         /* Update last_cpu_irq[][] for the next time */
 488                         LAST_CPU_IRQ(i,j) = value_now;
 489
 490                         /* Ignore IRQs whose rate is less than the clock */
 491                         if (delta < useful_load_threshold)
 492                                 continue;
 493                         /* update the load for the processor or package total */
 494                         IRQ_DELTA(package_index,j) += delta;
 495
 496                         /* Keep track of the higher numbered sibling as well */
 497                         if (i != package_index)
 498                                 CPU_IRQ(i) += delta;
 499                         /*
 500                          * We have sibling A and sibling B in the package
 501                          *
 502                          * cpu_irq[A] = load for cpu A + load for cpu B
 503                          * cpu_irq[B] = load for cpu B
 504                          */
 505                         CPU_IRQ(package_index) += delta;
 506                 }
 507         }
 508         /* Find the least loaded processor package */
 509         for_each_online_cpu(i) {
 510                 if (i != CPU_TO_PACKAGEINDEX(i))
 511                         continue;
 512                 if (min_cpu_irq > CPU_IRQ(i)) {
 513                         min_cpu_irq = CPU_IRQ(i);
 514                         min_loaded = i;
 515                 }
 516         }
 517         max_cpu_irq = ULONG_MAX;
 518
 519 tryanothercpu:
 520         /* Look for heaviest loaded processor.
 521          * We may come back to get the next heaviest loaded processor.
 522          * Skip processors with trivial loads.
 523          */
 524         tmp_cpu_irq = 0;
 525         tmp_loaded = -1;
 526         for_each_online_cpu(i) {
 527                 if (i != CPU_TO_PACKAGEINDEX(i))
 528                         continue;
 529                 if (max_cpu_irq <= CPU_IRQ(i))
 530                         continue;
 531                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 532                         tmp_cpu_irq = CPU_IRQ(i);
 533                         tmp_loaded = i;
 534                 }
 535         }
 536
 537         if (tmp_loaded == -1) {
 538          /* In the case of small number of heavy interrupt sources,
 539           * loading some of the cpus too much. We use Ingo's original
 540           * approach to rotate them around.
 541           */
 542                 if (!first_attempt && imbalance >= useful_load_threshold) {
 543                         rotate_irqs_among_cpus(useful_load_threshold);
 544                         return;
 545                 }
 546                 goto not_worth_the_effort;
 547         }
 548
 549         first_attempt = 0;              /* heaviest search */
 550         max_cpu_irq = tmp_cpu_irq;      /* load */
 551         max_loaded = tmp_loaded;        /* processor */
 552         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 553
 554         /* if imbalance is less than approx 10% of max load, then
 555          * observe diminishing returns action. - quit
 556          */
 557         if (imbalance < (max_cpu_irq >> 3))
 558                 goto not_worth_the_effort;
 559
 560 tryanotherirq:
 561         /* if we select an IRQ to move that can't go where we want, then
 562          * see if there is another one to try.
 563          */
 564         move_this_load = 0;
 565         selected_irq = -1;
 566         for (j = 0; j < NR_IRQS; j++) {
 567                 /* Is this an active IRQ? */
 568                 if (!irq_desc[j].action)
 569                         continue;
 570                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 571                         continue;
 572                 /* Try to find the IRQ that is closest to the imbalance
 573                  * without going over.
 574                  */
 575                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 576                         move_this_load = IRQ_DELTA(max_loaded,j);
 577                         selected_irq = j;
 578                 }
 579         }
 580         if (selected_irq == -1) {
 581                 goto tryanothercpu;
 582         }
 583
 584         imbalance = move_this_load;
 585
 586         /* For physical_balance case, we accumulated both load
 587          * values in the one of the siblings cpu_irq[],
 588          * to use the same code for physical and logical processors
 589          * as much as possible.
 590          *
 591          * NOTE: the cpu_irq[] array holds the sum of the load for
 592          * sibling A and sibling B in the slot for the lowest numbered
 593          * sibling (A), _AND_ the load for sibling B in the slot for
 594          * the higher numbered sibling.
 595          *
 596          * We seek the least loaded sibling by making the comparison
 597          * (A+B)/2 vs B
 598          */
 599         load = CPU_IRQ(min_loaded) >> 1;
 600         for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
 601                 if (load > CPU_IRQ(j)) {
 602                         /* This won't change cpu_sibling_map[min_loaded] */
 603                         load = CPU_IRQ(j);
 604                         min_loaded = j;
 605                 }
 606         }
 607
 608         cpus_and(allowed_mask,
 609                 cpu_online_map,
 610                 balance_irq_affinity[selected_irq]);
 611         target_cpu_mask = cpumask_of_cpu(min_loaded);
 612         cpus_and(tmp, target_cpu_mask, allowed_mask);
 613
 614         if (!cpus_empty(tmp)) {
 615                 /* mark for change destination */
 616                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 617
 618                 /* Since we made a change, come back sooner to
 619                  * check for more variation.
 620                  */
 621                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 622                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 623                 return;
 624         }
 625         goto tryanotherirq;
 626
 627 not_worth_the_effort:
 628         /*
 629          * if we did not find an IRQ to move, then adjust the time interval
 630          * upward
 631          */
 632         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 633                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 634         return;
 635 }
 636
 637 static int balanced_irq(void *unused)
 638 {
 639         int i;
 640         unsigned long prev_balance_time = jiffies;
 641         long time_remaining = balanced_irq_interval;
 642
 643         /* push everything to CPU 0 to give us a starting point.  */
 644         for (i = 0 ; i < NR_IRQS ; i++) {
 645                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 646                 set_pending_irq(i, cpumask_of_cpu(0));
 647         }
 648
 649         set_freezable();
 650         for ( ; ; ) {
 651                 time_remaining = schedule_timeout_interruptible(time_remaining);
 652                 try_to_freeze();
 653                 if (time_after(jiffies,
 654                                 prev_balance_time+balanced_irq_interval)) {
 655                         preempt_disable();
 656                         do_irq_balance();
 657                         prev_balance_time = jiffies;
 658                         time_remaining = balanced_irq_interval;
 659                         preempt_enable();
 660                 }
 661         }
 662         return 0;
 663 }
 664
 665 static int __init balanced_irq_init(void)
 666 {
 667         int i;
 668         struct cpuinfo_x86 *c;
 669         cpumask_t tmp;
 670
 671         cpus_shift_right(tmp, cpu_online_map, 2);
 672         c = &boot_cpu_data;
 673         /* When not overwritten by the command line ask subarchitecture. */
 674         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 675                 irqbalance_disabled = NO_BALANCE_IRQ;
 676         if (irqbalance_disabled)
 677                 return 0;
 678
 679          /* disable irqbalance completely if there is only one processor online */
 680         if (num_online_cpus() < 2) {
 681                 irqbalance_disabled = 1;
 682                 return 0;
 683         }
 684         /*
 685          * Enable physical balance only if more than 1 physical processor
 686          * is present
 687          */
 688         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 689                 physical_balance = 1;
 690
 691         for_each_online_cpu(i) {
 692                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 693                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 694                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 695                         printk(KERN_ERR "balanced_irq_init: out of memory");
 696                         goto failed;
 697                 }
 698                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 699                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 700         }
 701
 702         printk(KERN_INFO "Starting balanced_irq\n");
 703         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
 704                 return 0;
 705         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 706 failed:
 707         for_each_possible_cpu(i) {
 708                 kfree(irq_cpu_data[i].irq_delta);
 709                 irq_cpu_data[i].irq_delta = NULL;
 710                 kfree(irq_cpu_data[i].last_irq);
 711                 irq_cpu_data[i].last_irq = NULL;
 712         }
 713         return 0;
 714 }
 715
 716 int __devinit irqbalance_disable(char *str)
 717 {
 718         irqbalance_disabled = 1;
 719         return 1;
 720 }
 721
 722 __setup("noirqbalance", irqbalance_disable);
 723
 724 late_initcall(balanced_irq_init);
 725 #endif /* CONFIG_IRQBALANCE */
 726 #endif /* CONFIG_SMP */
 727
 728 #ifndef CONFIG_SMP
 729 void send_IPI_self(int vector)
 730 {
 731         unsigned int cfg;
 732
 733         /*
 734          * Wait for idle.
 735          */
 736         apic_wait_icr_idle();
 737         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 738         /*
 739          * Send the IPI. The write to APIC_ICR fires this off.
 740          */
 741         apic_write_around(APIC_ICR, cfg);
 742 }
 743 #endif /* !CONFIG_SMP */
 744
 745
 746 /*
 747  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 748  * specific CPU-side IRQs.
 749  */
 750
 751 #define MAX_PIRQS 8
 752 static int pirq_entries [MAX_PIRQS];
 753 static int pirqs_enabled;
 754 int skip_ioapic_setup;
 755
 756 static int __init ioapic_pirq_setup(char *str)
 757 {
 758         int i, max;
 759         int ints[MAX_PIRQS+1];
 760
 761         get_options(str, ARRAY_SIZE(ints), ints);
 762
 763         for (i = 0; i < MAX_PIRQS; i++)
 764                 pirq_entries[i] = -1;
 765
 766         pirqs_enabled = 1;
 767         apic_printk(APIC_VERBOSE, KERN_INFO
 768                         "PIRQ redirection, working around broken MP-BIOS.\n");
 769         max = MAX_PIRQS;
 770         if (ints[0] < MAX_PIRQS)
 771                 max = ints[0];
 772
 773         for (i = 0; i < max; i++) {
 774                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 775                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 776                 /*
 777                  * PIRQs are mapped upside down, usually.
 778                  */
 779                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 780         }
 781         return 1;
 782 }
 783
 784 __setup("pirq=", ioapic_pirq_setup);
 785
 786 /*
 787  * Find the IRQ entry number of a certain pin.
 788  */
 789 static int find_irq_entry(int apic, int pin, int type)
 790 {
 791         int i;
 792
 793         for (i = 0; i < mp_irq_entries; i++)
 794                 if (mp_irqs[i].mpc_irqtype == type &&
 795                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 796                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 797                     mp_irqs[i].mpc_dstirq == pin)
 798                         return i;
 799
 800         return -1;
 801 }
 802
 803 /*
 804  * Find the pin to which IRQ[irq] (ISA) is connected
 805  */
 806 static int __init find_isa_irq_pin(int irq, int type)
 807 {
 808         int i;
 809
 810         for (i = 0; i < mp_irq_entries; i++) {
 811                 int lbus = mp_irqs[i].mpc_srcbus;
 812
 813                 if (test_bit(lbus, mp_bus_not_pci) &&
 814                     (mp_irqs[i].mpc_irqtype == type) &&
 815                     (mp_irqs[i].mpc_srcbusirq == irq))
 816
 817                         return mp_irqs[i].mpc_dstirq;
 818         }
 819         return -1;
 820 }
 821
 822 static int __init find_isa_irq_apic(int irq, int type)
 823 {
 824         int i;
 825
 826         for (i = 0; i < mp_irq_entries; i++) {
 827                 int lbus = mp_irqs[i].mpc_srcbus;
 828
 829                 if (test_bit(lbus, mp_bus_not_pci) &&
 830                     (mp_irqs[i].mpc_irqtype == type) &&
 831                     (mp_irqs[i].mpc_srcbusirq == irq))
 832                         break;
 833         }
 834         if (i < mp_irq_entries) {
 835                 int apic;
 836                 for(apic = 0; apic < nr_ioapics; apic++) {
 837                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 838                                 return apic;
 839                 }
 840         }
 841
 842         return -1;
 843 }
 844
 845 /*
 846  * Find a specific PCI IRQ entry.
 847  * Not an __init, possibly needed by modules
 848  */
 849 static int pin_2_irq(int idx, int apic, int pin);
 850
 851 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 852 {
 853         int apic, i, best_guess = -1;
 854
 855         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 856                 "slot:%d, pin:%d.\n", bus, slot, pin);
 857         if (mp_bus_id_to_pci_bus[bus] == -1) {
 858                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 859                 return -1;
 860         }
 861         for (i = 0; i < mp_irq_entries; i++) {
 862                 int lbus = mp_irqs[i].mpc_srcbus;
 863
 864                 for (apic = 0; apic < nr_ioapics; apic++)
 865                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 866                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 867                                 break;
 868
 869                 if (!test_bit(lbus, mp_bus_not_pci) &&
 870                     !mp_irqs[i].mpc_irqtype &&
 871                     (bus == lbus) &&
 872                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 873                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 874
 875                         if (!(apic || IO_APIC_IRQ(irq)))
 876                                 continue;
 877
 878                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 879                                 return irq;
 880                         /*
 881                          * Use the first all-but-pin matching entry as a
 882                          * best-guess fuzzy result for broken mptables.
 883                          */
 884                         if (best_guess < 0)
 885                                 best_guess = irq;
 886                 }
 887         }
 888         return best_guess;
 889 }
 890 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 891
 892 /*
 893  * This function currently is only a helper for the i386 smp boot process where
 894  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 895  * so mask in all cases should simply be TARGET_CPUS
 896  */
 897 #ifdef CONFIG_SMP
 898 void __init setup_ioapic_dest(void)
 899 {
 900         int pin, ioapic, irq, irq_entry;
 901
 902         if (skip_ioapic_setup == 1)
 903                 return;
 904
 905         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 906                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 907                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 908                         if (irq_entry == -1)
 909                                 continue;
 910                         irq = pin_2_irq(irq_entry, ioapic, pin);
 911                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 912                 }
 913
 914         }
 915 }
 916 #endif
 917
 918 /*
 919  * EISA Edge/Level control register, ELCR
 920  */
 921 static int EISA_ELCR(unsigned int irq)
 922 {
 923         if (irq < 16) {
 924                 unsigned int port = 0x4d0 + (irq >> 3);
 925                 return (inb(port) >> (irq & 7)) & 1;
 926         }
 927         apic_printk(APIC_VERBOSE, KERN_INFO
 928                         "Broken MPtable reports ISA irq %d\n", irq);
 929         return 0;
 930 }
 931
 932 /* ISA interrupts are always polarity zero edge triggered,
 933  * when listed as conforming in the MP table. */
 934
 935 #define default_ISA_trigger(idx)        (0)
 936 #define default_ISA_polarity(idx)       (0)
 937
 938 /* EISA interrupts are always polarity zero and can be edge or level
 939  * trigger depending on the ELCR value.  If an interrupt is listed as
 940  * EISA conforming in the MP table, that means its trigger type must
 941  * be read in from the ELCR */
 942
 943 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 944 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
 945
 946 /* PCI interrupts are always polarity one level triggered,
 947  * when listed as conforming in the MP table. */
 948
 949 #define default_PCI_trigger(idx)        (1)
 950 #define default_PCI_polarity(idx)       (1)
 951
 952 /* MCA interrupts are always polarity zero level triggered,
 953  * when listed as conforming in the MP table. */
 954
 955 #define default_MCA_trigger(idx)        (1)
 956 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
 957
 958 static int MPBIOS_polarity(int idx)
 959 {
 960         int bus = mp_irqs[idx].mpc_srcbus;
 961         int polarity;
 962
 963         /*
 964          * Determine IRQ line polarity (high active or low active):
 965          */
 966         switch (mp_irqs[idx].mpc_irqflag & 3)
 967         {
 968                 case 0: /* conforms, ie. bus-type dependent polarity */
 969                 {
 970                         polarity = test_bit(bus, mp_bus_not_pci)?
 971                                 default_ISA_polarity(idx):
 972                                 default_PCI_polarity(idx);
 973                         break;
 974                 }
 975                 case 1: /* high active */
 976                 {
 977                         polarity = 0;
 978                         break;
 979                 }
 980                 case 2: /* reserved */
 981                 {
 982                         printk(KERN_WARNING "broken BIOS!!\n");
 983                         polarity = 1;
 984                         break;
 985                 }
 986                 case 3: /* low active */
 987                 {
 988                         polarity = 1;
 989                         break;
 990                 }
 991                 default: /* invalid */
 992                 {
 993                         printk(KERN_WARNING "broken BIOS!!\n");
 994                         polarity = 1;
 995                         break;
 996                 }
 997         }
 998         return polarity;
 999 }
1000
1001 static int MPBIOS_trigger(int idx)
1002 {
1003         int bus = mp_irqs[idx].mpc_srcbus;
1004         int trigger;
1005
1006         /*
1007          * Determine IRQ trigger mode (edge or level sensitive):
1008          */
1009         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1010         {
1011                 case 0: /* conforms, ie. bus-type dependent */
1012                 {
1013                         trigger = test_bit(bus, mp_bus_not_pci)?
1014                                         default_ISA_trigger(idx):
1015                                         default_PCI_trigger(idx);
1016                         switch (mp_bus_id_to_type[bus])
1017                         {
1018                                 case MP_BUS_ISA: /* ISA pin */
1019                                 {
1020                                         /* set before the switch */
1021                                         break;
1022                                 }
1023                                 case MP_BUS_EISA: /* EISA pin */
1024                                 {
1025                                         trigger = default_EISA_trigger(idx);
1026                                         break;
1027                                 }
1028                                 case MP_BUS_PCI: /* PCI pin */
1029                                 {
1030                                         /* set before the switch */
1031                                         break;
1032                                 }
1033                                 case MP_BUS_MCA: /* MCA pin */
1034                                 {
1035                                         trigger = default_MCA_trigger(idx);
1036                                         break;
1037                                 }
1038                                 default:
1039                                 {
1040                                         printk(KERN_WARNING "broken BIOS!!\n");
1041                                         trigger = 1;
1042                                         break;
1043                                 }
1044                         }
1045                         break;
1046                 }
1047                 case 1: /* edge */
1048                 {
1049                         trigger = 0;
1050                         break;
1051                 }
1052                 case 2: /* reserved */
1053                 {
1054                         printk(KERN_WARNING "broken BIOS!!\n");
1055                         trigger = 1;
1056                         break;
1057                 }
1058                 case 3: /* level */
1059                 {
1060                         trigger = 1;
1061                         break;
1062                 }
1063                 default: /* invalid */
1064                 {
1065                         printk(KERN_WARNING "broken BIOS!!\n");
1066                         trigger = 0;
1067                         break;
1068                 }
1069         }
1070         return trigger;
1071 }
1072
1073 static inline int irq_polarity(int idx)
1074 {
1075         return MPBIOS_polarity(idx);
1076 }
1077
1078 static inline int irq_trigger(int idx)
1079 {
1080         return MPBIOS_trigger(idx);
1081 }
1082
1083 static int pin_2_irq(int idx, int apic, int pin)
1084 {
1085         int irq, i;
1086         int bus = mp_irqs[idx].mpc_srcbus;
1087
1088         /*
1089          * Debugging check, we are in big trouble if this message pops up!
1090          */
1091         if (mp_irqs[idx].mpc_dstirq != pin)
1092                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1093
1094         switch (mp_bus_id_to_type[bus])
1095         {
1096                 case MP_BUS_ISA: /* ISA pin */
1097                 case MP_BUS_EISA:
1098                 case MP_BUS_MCA:
1099                 {
1100                         irq = mp_irqs[idx].mpc_srcbusirq;
1101                         break;
1102                 }
1103                 case MP_BUS_PCI: /* PCI pin */
1104                 {
1105                         /*
1106                          * PCI IRQs are mapped in order
1107                          */
1108                         i = irq = 0;
1109                         while (i < apic)
1110                                 irq += nr_ioapic_registers[i++];
1111                         irq += pin;
1112
1113                         /*
1114                          * For MPS mode, so far only needed by ES7000 platform
1115                          */
1116                         if (ioapic_renumber_irq)
1117                                 irq = ioapic_renumber_irq(apic, irq);
1118
1119                         break;
1120                 }
1121                 default:
1122                 {
1123                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1124                         irq = 0;
1125                         break;
1126                 }
1127         }
1128
1129         /*
1130          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1131          */
1132         if ((pin >= 16) && (pin <= 23)) {
1133                 if (pirq_entries[pin-16] != -1) {
1134                         if (!pirq_entries[pin-16]) {
1135                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1136                                                 "disabling PIRQ%d\n", pin-16);
1137                         } else {
1138                                 irq = pirq_entries[pin-16];
1139                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1140                                                 "using PIRQ%d -> IRQ %d\n",
1141                                                 pin-16, irq);
1142                         }
1143                 }
1144         }
1145         return irq;
1146 }
1147
1148 static inline int IO_APIC_irq_trigger(int irq)
1149 {
1150         int apic, idx, pin;
1151
1152         for (apic = 0; apic < nr_ioapics; apic++) {
1153                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1154                         idx = find_irq_entry(apic,pin,mp_INT);
1155                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1156                                 return irq_trigger(idx);
1157                 }
1158         }
1159         /*
1160          * nonexistent IRQs are edge default
1161          */
1162         return 0;
1163 }
1164
1165 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1166 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1167
1168 static int __assign_irq_vector(int irq)
1169 {
1170         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1171         int vector, offset;
1172
1173         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1174
1175         if (irq_vector[irq] > 0)
1176                 return irq_vector[irq];
1177
1178         vector = current_vector;
1179         offset = current_offset;
1180 next:
1181         vector += 8;
1182         if (vector >= FIRST_SYSTEM_VECTOR) {
1183                 offset = (offset + 1) % 8;
1184                 vector = FIRST_DEVICE_VECTOR + offset;
1185         }
1186         if (vector == current_vector)
1187                 return -ENOSPC;
1188         if (test_and_set_bit(vector, used_vectors))
1189                 goto next;
1190
1191         current_vector = vector;
1192         current_offset = offset;
1193         irq_vector[irq] = vector;
1194
1195         return vector;
1196 }
1197
1198 static int assign_irq_vector(int irq)
1199 {
1200         unsigned long flags;
1201         int vector;
1202
1203         spin_lock_irqsave(&vector_lock, flags);
1204         vector = __assign_irq_vector(irq);
1205         spin_unlock_irqrestore(&vector_lock, flags);
1206
1207         return vector;
1208 }
1209 static struct irq_chip ioapic_chip;
1210
1211 #define IOAPIC_AUTO     -1
1212 #define IOAPIC_EDGE     0
1213 #define IOAPIC_LEVEL    1
1214
1215 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1216 {
1217         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1218             trigger == IOAPIC_LEVEL) {
1219                 irq_desc[irq].status |= IRQ_LEVEL;
1220                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1221                                          handle_fasteoi_irq, "fasteoi");
1222         } else {
1223                 irq_desc[irq].status &= ~IRQ_LEVEL;
1224                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1225                                          handle_edge_irq, "edge");
1226         }
1227         set_intr_gate(vector, interrupt[irq]);
1228 }
1229
1230 static void __init setup_IO_APIC_irqs(void)
1231 {
1232         struct IO_APIC_route_entry entry;
1233         int apic, pin, idx, irq, first_notcon = 1, vector;
1234         unsigned long flags;
1235
1236         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1237
1238         for (apic = 0; apic < nr_ioapics; apic++) {
1239         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1240
1241                 /*
1242                  * add it to the IO-APIC irq-routing table:
1243                  */
1244                 memset(&entry,0,sizeof(entry));
1245
1246                 entry.delivery_mode = INT_DELIVERY_MODE;
1247                 entry.dest_mode = INT_DEST_MODE;
1248                 entry.mask = 0;                         /* enable IRQ */
1249                 entry.dest.logical.logical_dest =
1250                                         cpu_mask_to_apicid(TARGET_CPUS);
1251
1252                 idx = find_irq_entry(apic,pin,mp_INT);
1253                 if (idx == -1) {
1254                         if (first_notcon) {
1255                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1256                                                 " IO-APIC (apicid-pin) %d-%d",
1257                                                 mp_ioapics[apic].mpc_apicid,
1258                                                 pin);
1259                                 first_notcon = 0;
1260                         } else
1261                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1262                                         mp_ioapics[apic].mpc_apicid, pin);
1263                         continue;
1264                 }
1265
1266                 if (!first_notcon) {
1267                         apic_printk(APIC_VERBOSE, " not connected.\n");
1268                         first_notcon = 1;
1269                 }
1270
1271                 entry.trigger = irq_trigger(idx);
1272                 entry.polarity = irq_polarity(idx);
1273
1274                 if (irq_trigger(idx)) {
1275                         entry.trigger = 1;
1276                         entry.mask = 1;
1277                 }
1278
1279                 irq = pin_2_irq(idx, apic, pin);
1280                 /*
1281                  * skip adding the timer int on secondary nodes, which causes
1282                  * a small but painful rift in the time-space continuum
1283                  */
1284                 if (multi_timer_check(apic, irq))
1285                         continue;
1286                 else
1287                         add_pin_to_irq(irq, apic, pin);
1288
1289                 if (!apic && !IO_APIC_IRQ(irq))
1290                         continue;
1291
1292                 if (IO_APIC_IRQ(irq)) {
1293                         vector = assign_irq_vector(irq);
1294                         entry.vector = vector;
1295                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1296
1297                         if (!apic && (irq < 16))
1298                                 disable_8259A_irq(irq);
1299                 }
1300                 spin_lock_irqsave(&ioapic_lock, flags);
1301                 __ioapic_write_entry(apic, pin, entry);
1302                 spin_unlock_irqrestore(&ioapic_lock, flags);
1303         }
1304         }
1305
1306         if (!first_notcon)
1307                 apic_printk(APIC_VERBOSE, " not connected.\n");
1308 }
1309
1310 /*
1311  * Set up the 8259A-master output pin:
1312  */
1313 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1314 {
1315         struct IO_APIC_route_entry entry;
1316
1317         memset(&entry,0,sizeof(entry));
1318
1319         disable_8259A_irq(0);
1320
1321         /* mask LVT0 */
1322         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1323
1324         /*
1325          * We use logical delivery to get the timer IRQ
1326          * to the first CPU.
1327          */
1328         entry.dest_mode = INT_DEST_MODE;
1329         entry.mask = 0;                                 /* unmask IRQ now */
1330         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1331         entry.delivery_mode = INT_DELIVERY_MODE;
1332         entry.polarity = 0;
1333         entry.trigger = 0;
1334         entry.vector = vector;
1335
1336         /*
1337          * The timer IRQ doesn't have to know that behind the
1338          * scene we have a 8259A-master in AEOI mode ...
1339          */
1340         irq_desc[0].chip = &ioapic_chip;
1341         set_irq_handler(0, handle_edge_irq);
1342
1343         /*
1344          * Add it to the IO-APIC irq-routing table:
1345          */
1346         ioapic_write_entry(apic, pin, entry);
1347
1348         enable_8259A_irq(0);
1349 }
1350
1351 void __init print_IO_APIC(void)
1352 {
1353         int apic, i;
1354         union IO_APIC_reg_00 reg_00;
1355         union IO_APIC_reg_01 reg_01;
1356         union IO_APIC_reg_02 reg_02;
1357         union IO_APIC_reg_03 reg_03;
1358         unsigned long flags;
1359
1360         if (apic_verbosity == APIC_QUIET)
1361                 return;
1362
1363         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1364         for (i = 0; i < nr_ioapics; i++)
1365                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1366                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1367
1368         /*
1369          * We are a bit conservative about what we expect.  We have to
1370          * know about every hardware change ASAP.
1371          */
1372         printk(KERN_INFO "testing the IO APIC.......................\n");
1373
1374         for (apic = 0; apic < nr_ioapics; apic++) {
1375
1376         spin_lock_irqsave(&ioapic_lock, flags);
1377         reg_00.raw = io_apic_read(apic, 0);
1378         reg_01.raw = io_apic_read(apic, 1);
1379         if (reg_01.bits.version >= 0x10)
1380                 reg_02.raw = io_apic_read(apic, 2);
1381         if (reg_01.bits.version >= 0x20)
1382                 reg_03.raw = io_apic_read(apic, 3);
1383         spin_unlock_irqrestore(&ioapic_lock, flags);
1384
1385         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1386         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1387         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1388         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1389         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1390
1391         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1392         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1393
1394         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1395         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1396
1397         /*
1398          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1399          * but the value of reg_02 is read as the previous read register
1400          * value, so ignore it if reg_02 == reg_01.
1401          */
1402         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1403                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1404                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1405         }
1406
1407         /*
1408          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1409          * or reg_03, but the value of reg_0[23] is read as the previous read
1410          * register value, so ignore it if reg_03 == reg_0[12].
1411          */
1412         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1413             reg_03.raw != reg_01.raw) {
1414                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1415                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1416         }
1417
1418         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1419
1420         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1421                           " Stat Dest Deli Vect:   \n");
1422
1423         for (i = 0; i <= reg_01.bits.entries; i++) {
1424                 struct IO_APIC_route_entry entry;
1425
1426                 entry = ioapic_read_entry(apic, i);
1427
1428                 printk(KERN_DEBUG " %02x %03X %02X  ",
1429                         i,
1430                         entry.dest.logical.logical_dest,
1431                         entry.dest.physical.physical_dest
1432                 );
1433
1434                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1435                         entry.mask,
1436                         entry.trigger,
1437                         entry.irr,
1438                         entry.polarity,
1439                         entry.delivery_status,
1440                         entry.dest_mode,
1441                         entry.delivery_mode,
1442                         entry.vector
1443                 );
1444         }
1445         }
1446         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1447         for (i = 0; i < NR_IRQS; i++) {
1448                 struct irq_pin_list *entry = irq_2_pin + i;
1449                 if (entry->pin < 0)
1450                         continue;
1451                 printk(KERN_DEBUG "IRQ%d ", i);
1452                 for (;;) {
1453                         printk("-> %d:%d", entry->apic, entry->pin);
1454                         if (!entry->next)
1455                                 break;
1456                         entry = irq_2_pin + entry->next;
1457                 }
1458                 printk("\n");
1459         }
1460
1461         printk(KERN_INFO ".................................... done.\n");
1462
1463         return;
1464 }
1465
1466 #if 0
1467
1468 static void print_APIC_bitfield (int base)
1469 {
1470         unsigned int v;
1471         int i, j;
1472
1473         if (apic_verbosity == APIC_QUIET)
1474                 return;
1475
1476         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1477         for (i = 0; i < 8; i++) {
1478                 v = apic_read(base + i*0x10);
1479                 for (j = 0; j < 32; j++) {
1480                         if (v & (1<<j))
1481                                 printk("1");
1482                         else
1483                                 printk("0");
1484                 }
1485                 printk("\n");
1486         }
1487 }
1488
1489 void /*__init*/ print_local_APIC(void * dummy)
1490 {
1491         unsigned int v, ver, maxlvt;
1492
1493         if (apic_verbosity == APIC_QUIET)
1494                 return;
1495
1496         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1497                 smp_processor_id(), hard_smp_processor_id());
1498         v = apic_read(APIC_ID);
1499         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1500         v = apic_read(APIC_LVR);
1501         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1502         ver = GET_APIC_VERSION(v);
1503         maxlvt = lapic_get_maxlvt();
1504
1505         v = apic_read(APIC_TASKPRI);
1506         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1507
1508         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1509                 v = apic_read(APIC_ARBPRI);
1510                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1511                         v & APIC_ARBPRI_MASK);
1512                 v = apic_read(APIC_PROCPRI);
1513                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1514         }
1515
1516         v = apic_read(APIC_EOI);
1517         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1518         v = apic_read(APIC_RRR);
1519         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1520         v = apic_read(APIC_LDR);
1521         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1522         v = apic_read(APIC_DFR);
1523         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1524         v = apic_read(APIC_SPIV);
1525         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1526
1527         printk(KERN_DEBUG "... APIC ISR field:\n");
1528         print_APIC_bitfield(APIC_ISR);
1529         printk(KERN_DEBUG "... APIC TMR field:\n");
1530         print_APIC_bitfield(APIC_TMR);
1531         printk(KERN_DEBUG "... APIC IRR field:\n");
1532         print_APIC_bitfield(APIC_IRR);
1533
1534         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1535                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1536                         apic_write(APIC_ESR, 0);
1537                 v = apic_read(APIC_ESR);
1538                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1539         }
1540
1541         v = apic_read(APIC_ICR);
1542         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1543         v = apic_read(APIC_ICR2);
1544         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1545
1546         v = apic_read(APIC_LVTT);
1547         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1548
1549         if (maxlvt > 3) {                       /* PC is LVT#4. */
1550                 v = apic_read(APIC_LVTPC);
1551                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1552         }
1553         v = apic_read(APIC_LVT0);
1554         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1555         v = apic_read(APIC_LVT1);
1556         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1557
1558         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1559                 v = apic_read(APIC_LVTERR);
1560                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1561         }
1562
1563         v = apic_read(APIC_TMICT);
1564         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1565         v = apic_read(APIC_TMCCT);
1566         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1567         v = apic_read(APIC_TDCR);
1568         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1569         printk("\n");
1570 }
1571
1572 void print_all_local_APICs (void)
1573 {
1574         on_each_cpu(print_local_APIC, NULL, 1, 1);
1575 }
1576
1577 void /*__init*/ print_PIC(void)
1578 {
1579         unsigned int v;
1580         unsigned long flags;
1581
1582         if (apic_verbosity == APIC_QUIET)
1583                 return;
1584
1585         printk(KERN_DEBUG "\nprinting PIC contents\n");
1586
1587         spin_lock_irqsave(&i8259A_lock, flags);
1588
1589         v = inb(0xa1) << 8 | inb(0x21);
1590         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1591
1592         v = inb(0xa0) << 8 | inb(0x20);
1593         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1594
1595         outb(0x0b,0xa0);
1596         outb(0x0b,0x20);
1597         v = inb(0xa0) << 8 | inb(0x20);
1598         outb(0x0a,0xa0);
1599         outb(0x0a,0x20);
1600
1601         spin_unlock_irqrestore(&i8259A_lock, flags);
1602
1603         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1604
1605         v = inb(0x4d1) << 8 | inb(0x4d0);
1606         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1607 }
1608
1609 #endif  /*  0  */
1610
1611 static void __init enable_IO_APIC(void)
1612 {
1613         union IO_APIC_reg_01 reg_01;
1614         int i8259_apic, i8259_pin;
1615         int i, apic;
1616         unsigned long flags;
1617
1618         for (i = 0; i < PIN_MAP_SIZE; i++) {
1619                 irq_2_pin[i].pin = -1;
1620                 irq_2_pin[i].next = 0;
1621         }
1622         if (!pirqs_enabled)
1623                 for (i = 0; i < MAX_PIRQS; i++)
1624                         pirq_entries[i] = -1;
1625
1626         /*
1627          * The number of IO-APIC IRQ registers (== #pins):
1628          */
1629         for (apic = 0; apic < nr_ioapics; apic++) {
1630                 spin_lock_irqsave(&ioapic_lock, flags);
1631                 reg_01.raw = io_apic_read(apic, 1);
1632                 spin_unlock_irqrestore(&ioapic_lock, flags);
1633                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1634         }
1635         for(apic = 0; apic < nr_ioapics; apic++) {
1636                 int pin;
1637                 /* See if any of the pins is in ExtINT mode */
1638                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1639                         struct IO_APIC_route_entry entry;
1640                         entry = ioapic_read_entry(apic, pin);
1641
1642
1643                         /* If the interrupt line is enabled and in ExtInt mode
1644                          * I have found the pin where the i8259 is connected.
1645                          */
1646                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1647                                 ioapic_i8259.apic = apic;
1648                                 ioapic_i8259.pin  = pin;
1649                                 goto found_i8259;
1650                         }
1651                 }
1652         }
1653  found_i8259:
1654         /* Look to see what if the MP table has reported the ExtINT */
1655         /* If we could not find the appropriate pin by looking at the ioapic
1656          * the i8259 probably is not connected the ioapic but give the
1657          * mptable a chance anyway.
1658          */
1659         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1660         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1661         /* Trust the MP table if nothing is setup in the hardware */
1662         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1663                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1664                 ioapic_i8259.pin  = i8259_pin;
1665                 ioapic_i8259.apic = i8259_apic;
1666         }
1667         /* Complain if the MP table and the hardware disagree */
1668         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1669                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1670         {
1671                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1672         }
1673
1674         /*
1675          * Do not trust the IO-APIC being empty at bootup
1676          */
1677         clear_IO_APIC();
1678 }
1679
1680 /*
1681  * Not an __init, needed by the reboot code
1682  */
1683 void disable_IO_APIC(void)
1684 {
1685         /*
1686          * Clear the IO-APIC before rebooting:
1687          */
1688         clear_IO_APIC();
1689
1690         /*
1691          * If the i8259 is routed through an IOAPIC
1692          * Put that IOAPIC in virtual wire mode
1693          * so legacy interrupts can be delivered.
1694          */
1695         if (ioapic_i8259.pin != -1) {
1696                 struct IO_APIC_route_entry entry;
1697
1698                 memset(&entry, 0, sizeof(entry));
1699                 entry.mask            = 0; /* Enabled */
1700                 entry.trigger         = 0; /* Edge */
1701                 entry.irr             = 0;
1702                 entry.polarity        = 0; /* High */
1703                 entry.delivery_status = 0;
1704                 entry.dest_mode       = 0; /* Physical */
1705                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1706                 entry.vector          = 0;
1707                 entry.dest.physical.physical_dest =
1708                                         GET_APIC_ID(apic_read(APIC_ID));
1709
1710                 /*
1711                  * Add it to the IO-APIC irq-routing table:
1712                  */
1713                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1714         }
1715         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1716 }
1717
1718 /*
1719  * function to set the IO-APIC physical IDs based on the
1720  * values stored in the MPC table.
1721  *
1722  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1723  */
1724
1725 #ifndef CONFIG_X86_NUMAQ
1726 static void __init setup_ioapic_ids_from_mpc(void)
1727 {
1728         union IO_APIC_reg_00 reg_00;
1729         physid_mask_t phys_id_present_map;
1730         int apic;
1731         int i;
1732         unsigned char old_id;
1733         unsigned long flags;
1734
1735         /*
1736          * Don't check I/O APIC IDs for xAPIC systems.  They have
1737          * no meaning without the serial APIC bus.
1738          */
1739         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1740                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1741                 return;
1742         /*
1743          * This is broken; anything with a real cpu count has to
1744          * circumvent this idiocy regardless.
1745          */
1746         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1747
1748         /*
1749          * Set the IOAPIC ID to the value stored in the MPC table.
1750          */
1751         for (apic = 0; apic < nr_ioapics; apic++) {
1752
1753                 /* Read the register 0 value */
1754                 spin_lock_irqsave(&ioapic_lock, flags);
1755                 reg_00.raw = io_apic_read(apic, 0);
1756                 spin_unlock_irqrestore(&ioapic_lock, flags);
1757
1758                 old_id = mp_ioapics[apic].mpc_apicid;
1759
1760                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1761                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1762                                 apic, mp_ioapics[apic].mpc_apicid);
1763                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1764                                 reg_00.bits.ID);
1765                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1766                 }
1767
1768                 /*
1769                  * Sanity check, is the ID really free? Every APIC in a
1770                  * system must have a unique ID or we get lots of nice
1771                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1772                  */
1773                 if (check_apicid_used(phys_id_present_map,
1774                                         mp_ioapics[apic].mpc_apicid)) {
1775                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1776                                 apic, mp_ioapics[apic].mpc_apicid);
1777                         for (i = 0; i < get_physical_broadcast(); i++)
1778                                 if (!physid_isset(i, phys_id_present_map))
1779                                         break;
1780                         if (i >= get_physical_broadcast())
1781                                 panic("Max APIC ID exceeded!\n");
1782                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1783                                 i);
1784                         physid_set(i, phys_id_present_map);
1785                         mp_ioapics[apic].mpc_apicid = i;
1786                 } else {
1787                         physid_mask_t tmp;
1788                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1789                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1790                                         "phys_id_present_map\n",
1791                                         mp_ioapics[apic].mpc_apicid);
1792                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1793                 }
1794
1795
1796                 /*
1797                  * We need to adjust the IRQ routing table
1798                  * if the ID changed.
1799                  */
1800                 if (old_id != mp_ioapics[apic].mpc_apicid)
1801                         for (i = 0; i < mp_irq_entries; i++)
1802                                 if (mp_irqs[i].mpc_dstapic == old_id)
1803                                         mp_irqs[i].mpc_dstapic
1804                                                 = mp_ioapics[apic].mpc_apicid;
1805
1806                 /*
1807                  * Read the right value from the MPC table and
1808                  * write it into the ID register.
1809                  */
1810                 apic_printk(APIC_VERBOSE, KERN_INFO
1811                         "...changing IO-APIC physical APIC ID to %d ...",
1812                         mp_ioapics[apic].mpc_apicid);
1813
1814                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1815                 spin_lock_irqsave(&ioapic_lock, flags);
1816                 io_apic_write(apic, 0, reg_00.raw);
1817                 spin_unlock_irqrestore(&ioapic_lock, flags);
1818
1819                 /*
1820                  * Sanity check
1821                  */
1822                 spin_lock_irqsave(&ioapic_lock, flags);
1823                 reg_00.raw = io_apic_read(apic, 0);
1824                 spin_unlock_irqrestore(&ioapic_lock, flags);
1825                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1826                         printk("could not set ID!\n");
1827                 else
1828                         apic_printk(APIC_VERBOSE, " ok.\n");
1829         }
1830 }
1831 #else
1832 static void __init setup_ioapic_ids_from_mpc(void) { }
1833 #endif
1834
1835 int no_timer_check __initdata;
1836
1837 static int __init notimercheck(char *s)
1838 {
1839         no_timer_check = 1;
1840         return 1;
1841 }
1842 __setup("no_timer_check", notimercheck);
1843
1844 /*
1845  * There is a nasty bug in some older SMP boards, their mptable lies
1846  * about the timer IRQ. We do the following to work around the situation:
1847  *
1848  *      - timer IRQ defaults to IO-APIC IRQ
1849  *      - if this function detects that timer IRQs are defunct, then we fall
1850  *        back to ISA timer IRQs
1851  */
1852 static int __init timer_irq_works(void)
1853 {
1854         unsigned long t1 = jiffies;
1855         unsigned long flags;
1856
1857         if (no_timer_check)
1858                 return 1;
1859
1860         local_save_flags(flags);
1861         local_irq_enable();
1862         /* Let ten ticks pass... */
1863         mdelay((10 * 1000) / HZ);
1864         local_irq_restore(flags);
1865
1866         /*
1867          * Expect a few ticks at least, to be sure some possible
1868          * glue logic does not lock up after one or two first
1869          * ticks in a non-ExtINT mode.  Also the local APIC
1870          * might have cached one ExtINT interrupt.  Finally, at
1871          * least one tick may be lost due to delays.
1872          */
1873         if (time_after(jiffies, t1 + 4))
1874                 return 1;
1875
1876         return 0;
1877 }
1878
1879 /*
1880  * In the SMP+IOAPIC case it might happen that there are an unspecified
1881  * number of pending IRQ events unhandled. These cases are very rare,
1882  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1883  * better to do it this way as thus we do not have to be aware of
1884  * 'pending' interrupts in the IRQ path, except at this point.
1885  */
1886 /*
1887  * Edge triggered needs to resend any interrupt
1888  * that was delayed but this is now handled in the device
1889  * independent code.
1890  */
1891
1892 /*
1893  * Startup quirk:
1894  *
1895  * Starting up a edge-triggered IO-APIC interrupt is
1896  * nasty - we need to make sure that we get the edge.
1897  * If it is already asserted for some reason, we need
1898  * return 1 to indicate that is was pending.
1899  *
1900  * This is not complete - we should be able to fake
1901  * an edge even if it isn't on the 8259A...
1902  *
1903  * (We do this for level-triggered IRQs too - it cannot hurt.)
1904  */
1905 static unsigned int startup_ioapic_irq(unsigned int irq)
1906 {
1907         int was_pending = 0;
1908         unsigned long flags;
1909
1910         spin_lock_irqsave(&ioapic_lock, flags);
1911         if (irq < 16) {
1912                 disable_8259A_irq(irq);
1913                 if (i8259A_irq_pending(irq))
1914                         was_pending = 1;
1915         }
1916         __unmask_IO_APIC_irq(irq);
1917         spin_unlock_irqrestore(&ioapic_lock, flags);
1918
1919         return was_pending;
1920 }
1921
1922 static void ack_ioapic_irq(unsigned int irq)
1923 {
1924         move_native_irq(irq);
1925         ack_APIC_irq();
1926 }
1927
1928 static void ack_ioapic_quirk_irq(unsigned int irq)
1929 {
1930         unsigned long v;
1931         int i;
1932
1933         move_native_irq(irq);
1934 /*
1935  * It appears there is an erratum which affects at least version 0x11
1936  * of I/O APIC (that's the 82093AA and cores integrated into various
1937  * chipsets).  Under certain conditions a level-triggered interrupt is
1938  * erroneously delivered as edge-triggered one but the respective IRR
1939  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1940  * message but it will never arrive and further interrupts are blocked
1941  * from the source.  The exact reason is so far unknown, but the
1942  * phenomenon was observed when two consecutive interrupt requests
1943  * from a given source get delivered to the same CPU and the source is
1944  * temporarily disabled in between.
1945  *
1946  * A workaround is to simulate an EOI message manually.  We achieve it
1947  * by setting the trigger mode to edge and then to level when the edge
1948  * trigger mode gets detected in the TMR of a local APIC for a
1949  * level-triggered interrupt.  We mask the source for the time of the
1950  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1951  * The idea is from Manfred Spraul.  --macro
1952  */
1953         i = irq_vector[irq];
1954
1955         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1956
1957         ack_APIC_irq();
1958
1959         if (!(v & (1 << (i & 0x1f)))) {
1960                 atomic_inc(&irq_mis_count);
1961                 spin_lock(&ioapic_lock);
1962                 __mask_and_edge_IO_APIC_irq(irq);
1963                 __unmask_and_level_IO_APIC_irq(irq);
1964                 spin_unlock(&ioapic_lock);
1965         }
1966 }
1967
1968 static int ioapic_retrigger_irq(unsigned int irq)
1969 {
1970         send_IPI_self(irq_vector[irq]);
1971
1972         return 1;
1973 }
1974
1975 static struct irq_chip ioapic_chip __read_mostly = {
1976         .name           = "IO-APIC",
1977         .startup        = startup_ioapic_irq,
1978         .mask           = mask_IO_APIC_irq,
1979         .unmask         = unmask_IO_APIC_irq,
1980         .ack            = ack_ioapic_irq,
1981         .eoi            = ack_ioapic_quirk_irq,
1982 #ifdef CONFIG_SMP
1983         .set_affinity   = set_ioapic_affinity_irq,
1984 #endif
1985         .retrigger      = ioapic_retrigger_irq,
1986 };
1987
1988
1989 static inline void init_IO_APIC_traps(void)
1990 {
1991         int irq;
1992
1993         /*
1994          * NOTE! The local APIC isn't very good at handling
1995          * multiple interrupts at the same interrupt level.
1996          * As the interrupt level is determined by taking the
1997          * vector number and shifting that right by 4, we
1998          * want to spread these out a bit so that they don't
1999          * all fall in the same interrupt level.
2000          *
2001          * Also, we've got to be careful not to trash gate
2002          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2003          */
2004         for (irq = 0; irq < NR_IRQS ; irq++) {
2005                 int tmp = irq;
2006                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2007                         /*
2008                          * Hmm.. We don't have an entry for this,
2009                          * so default to an old-fashioned 8259
2010                          * interrupt if we can..
2011                          */
2012                         if (irq < 16)
2013                                 make_8259A_irq(irq);
2014                         else
2015                                 /* Strange. Oh, well.. */
2016                                 irq_desc[irq].chip = &no_irq_chip;
2017                 }
2018         }
2019 }
2020
2021 /*
2022  * The local APIC irq-chip implementation:
2023  */
2024
2025 static void ack_apic(unsigned int irq)
2026 {
2027         ack_APIC_irq();
2028 }
2029
2030 static void mask_lapic_irq (unsigned int irq)
2031 {
2032         unsigned long v;
2033
2034         v = apic_read(APIC_LVT0);
2035         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2036 }
2037
2038 static void unmask_lapic_irq (unsigned int irq)
2039 {
2040         unsigned long v;
2041
2042         v = apic_read(APIC_LVT0);
2043         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2044 }
2045
2046 static struct irq_chip lapic_chip __read_mostly = {
2047         .name           = "local-APIC-edge",
2048         .mask           = mask_lapic_irq,
2049         .unmask         = unmask_lapic_irq,
2050         .eoi            = ack_apic,
2051 };
2052
2053 static void __init setup_nmi(void)
2054 {
2055         /*
2056          * Dirty trick to enable the NMI watchdog ...
2057          * We put the 8259A master into AEOI mode and
2058          * unmask on all local APICs LVT0 as NMI.
2059          *
2060          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2061          * is from Maciej W. Rozycki - so we do not have to EOI from
2062          * the NMI handler or the timer interrupt.
2063          */
2064         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2065
2066         enable_NMI_through_LVT0();
2067
2068         apic_printk(APIC_VERBOSE, " done.\n");
2069 }
2070
2071 /*
2072  * This looks a bit hackish but it's about the only one way of sending
2073  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2074  * not support the ExtINT mode, unfortunately.  We need to send these
2075  * cycles as some i82489DX-based boards have glue logic that keeps the
2076  * 8259A interrupt line asserted until INTA.  --macro
2077  */
2078 static inline void unlock_ExtINT_logic(void)
2079 {
2080         int apic, pin, i;
2081         struct IO_APIC_route_entry entry0, entry1;
2082         unsigned char save_control, save_freq_select;
2083
2084         pin  = find_isa_irq_pin(8, mp_INT);
2085         if (pin == -1) {
2086                 WARN_ON_ONCE(1);
2087                 return;
2088         }
2089         apic = find_isa_irq_apic(8, mp_INT);
2090         if (apic == -1) {
2091                 WARN_ON_ONCE(1);
2092                 return;
2093         }
2094
2095         entry0 = ioapic_read_entry(apic, pin);
2096         clear_IO_APIC_pin(apic, pin);
2097
2098         memset(&entry1, 0, sizeof(entry1));
2099
2100         entry1.dest_mode = 0;                   /* physical delivery */
2101         entry1.mask = 0;                        /* unmask IRQ now */
2102         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2103         entry1.delivery_mode = dest_ExtINT;
2104         entry1.polarity = entry0.polarity;
2105         entry1.trigger = 0;
2106         entry1.vector = 0;
2107
2108         ioapic_write_entry(apic, pin, entry1);
2109
2110         save_control = CMOS_READ(RTC_CONTROL);
2111         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2112         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2113                    RTC_FREQ_SELECT);
2114         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2115
2116         i = 100;
2117         while (i-- > 0) {
2118                 mdelay(10);
2119                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2120                         i -= 10;
2121         }
2122
2123         CMOS_WRITE(save_control, RTC_CONTROL);
2124         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2125         clear_IO_APIC_pin(apic, pin);
2126
2127         ioapic_write_entry(apic, pin, entry0);
2128 }
2129
2130 int timer_uses_ioapic_pin_0;
2131
2132 /*
2133  * This code may look a bit paranoid, but it's supposed to cooperate with
2134  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2135  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2136  * fanatically on his truly buggy board.
2137  */
2138 static inline void __init check_timer(void)
2139 {
2140         int apic1, pin1, apic2, pin2;
2141         int vector;
2142         unsigned long flags;
2143
2144         local_irq_save(flags);
2145
2146         /*
2147          * get/set the timer IRQ vector:
2148          */
2149         disable_8259A_irq(0);
2150         vector = assign_irq_vector(0);
2151         set_intr_gate(vector, interrupt[0]);
2152
2153         /*
2154          * Subtle, code in do_timer_interrupt() expects an AEOI
2155          * mode for the 8259A whenever interrupts are routed
2156          * through I/O APICs.  Also IRQ0 has to be enabled in
2157          * the 8259A which implies the virtual wire has to be
2158          * disabled in the local APIC.
2159          */
2160         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2161         init_8259A(1);
2162         timer_ack = 1;
2163         if (timer_over_8254 > 0)
2164                 enable_8259A_irq(0);
2165
2166         pin1  = find_isa_irq_pin(0, mp_INT);
2167         apic1 = find_isa_irq_apic(0, mp_INT);
2168         pin2  = ioapic_i8259.pin;
2169         apic2 = ioapic_i8259.apic;
2170
2171         if (pin1 == 0)
2172                 timer_uses_ioapic_pin_0 = 1;
2173
2174         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2175                 vector, apic1, pin1, apic2, pin2);
2176
2177         if (pin1 != -1) {
2178                 /*
2179                  * Ok, does IRQ0 through the IOAPIC work?
2180                  */
2181                 unmask_IO_APIC_irq(0);
2182                 if (timer_irq_works()) {
2183                         if (nmi_watchdog == NMI_IO_APIC) {
2184                                 disable_8259A_irq(0);
2185                                 setup_nmi();
2186                                 enable_8259A_irq(0);
2187                         }
2188                         if (disable_timer_pin_1 > 0)
2189                                 clear_IO_APIC_pin(0, pin1);
2190                         goto out;
2191                 }
2192                 clear_IO_APIC_pin(apic1, pin1);
2193                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2194                                 "IO-APIC\n");
2195         }
2196
2197         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2198         if (pin2 != -1) {
2199                 printk("\n..... (found pin %d) ...", pin2);
2200                 /*
2201                  * legacy devices should be connected to IO APIC #0
2202                  */
2203                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2204                 if (timer_irq_works()) {
2205                         printk("works.\n");
2206                         if (pin1 != -1)
2207                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2208                         else
2209                                 add_pin_to_irq(0, apic2, pin2);
2210                         if (nmi_watchdog == NMI_IO_APIC) {
2211                                 setup_nmi();
2212                         }
2213                         goto out;
2214                 }
2215                 /*
2216                  * Cleanup, just in case ...
2217                  */
2218                 clear_IO_APIC_pin(apic2, pin2);
2219         }
2220         printk(" failed.\n");
2221
2222         if (nmi_watchdog == NMI_IO_APIC) {
2223                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2224                 nmi_watchdog = 0;
2225         }
2226
2227         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2228
2229         disable_8259A_irq(0);
2230         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2231                                       "fasteoi");
2232         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2233         enable_8259A_irq(0);
2234
2235         if (timer_irq_works()) {
2236                 printk(" works.\n");
2237                 goto out;
2238         }
2239         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2240         printk(" failed.\n");
2241
2242         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2243
2244         timer_ack = 0;
2245         init_8259A(0);
2246         make_8259A_irq(0);
2247         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2248
2249         unlock_ExtINT_logic();
2250
2251         if (timer_irq_works()) {
2252                 printk(" works.\n");
2253                 goto out;
2254         }
2255         printk(" failed :(.\n");
2256         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2257                 "report.  Then try booting with the 'noapic' option");
2258 out:
2259         local_irq_restore(flags);
2260 }
2261
2262 /*
2263  *
2264  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2265  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2266  *   Linux doesn't really care, as it's not actually used
2267  *   for any interrupt handling anyway.
2268  */
2269 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2270
2271 void __init setup_IO_APIC(void)
2272 {
2273         int i;
2274
2275         /* Reserve all the system vectors. */
2276         for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2277                 set_bit(i, used_vectors);
2278
2279         enable_IO_APIC();
2280
2281         if (acpi_ioapic)
2282                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2283         else
2284                 io_apic_irqs = ~PIC_IRQS;
2285
2286         printk("ENABLING IO-APIC IRQs\n");
2287
2288         /*
2289          * Set up IO-APIC IRQ routing.
2290          */
2291         if (!acpi_ioapic)
2292                 setup_ioapic_ids_from_mpc();
2293         sync_Arb_IDs();
2294         setup_IO_APIC_irqs();
2295         init_IO_APIC_traps();
2296         check_timer();
2297         if (!acpi_ioapic)
2298                 print_IO_APIC();
2299 }
2300
2301 static int __init setup_disable_8254_timer(char *s)
2302 {
2303         timer_over_8254 = -1;
2304         return 1;
2305 }
2306 static int __init setup_enable_8254_timer(char *s)
2307 {
2308         timer_over_8254 = 2;
2309         return 1;
2310 }
2311
2312 __setup("disable_8254_timer", setup_disable_8254_timer);
2313 __setup("enable_8254_timer", setup_enable_8254_timer);
2314
2315 /*
2316  *      Called after all the initialization is done. If we didnt find any
2317  *      APIC bugs then we can allow the modify fast path
2318  */
2319
2320 static int __init io_apic_bug_finalize(void)
2321 {
2322         if(sis_apic_bug == -1)
2323                 sis_apic_bug = 0;
2324         return 0;
2325 }
2326
2327 late_initcall(io_apic_bug_finalize);
2328
2329 struct sysfs_ioapic_data {
2330         struct sys_device dev;
2331         struct IO_APIC_route_entry entry[0];
2332 };
2333 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2334
2335 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2336 {
2337         struct IO_APIC_route_entry *entry;
2338         struct sysfs_ioapic_data *data;
2339         int i;
2340
2341         data = container_of(dev, struct sysfs_ioapic_data, dev);
2342         entry = data->entry;
2343         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2344                 entry[i] = ioapic_read_entry(dev->id, i);
2345
2346         return 0;
2347 }
2348
2349 static int ioapic_resume(struct sys_device *dev)
2350 {
2351         struct IO_APIC_route_entry *entry;
2352         struct sysfs_ioapic_data *data;
2353         unsigned long flags;
2354         union IO_APIC_reg_00 reg_00;
2355         int i;
2356
2357         data = container_of(dev, struct sysfs_ioapic_data, dev);
2358         entry = data->entry;
2359
2360         spin_lock_irqsave(&ioapic_lock, flags);
2361         reg_00.raw = io_apic_read(dev->id, 0);
2362         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2363                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2364                 io_apic_write(dev->id, 0, reg_00.raw);
2365         }
2366         spin_unlock_irqrestore(&ioapic_lock, flags);
2367         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2368                 ioapic_write_entry(dev->id, i, entry[i]);
2369
2370         return 0;
2371 }
2372
2373 static struct sysdev_class ioapic_sysdev_class = {
2374         .name = "ioapic",
2375         .suspend = ioapic_suspend,
2376         .resume = ioapic_resume,
2377 };
2378
2379 static int __init ioapic_init_sysfs(void)
2380 {
2381         struct sys_device * dev;
2382         int i, size, error = 0;
2383
2384         error = sysdev_class_register(&ioapic_sysdev_class);
2385         if (error)
2386                 return error;
2387
2388         for (i = 0; i < nr_ioapics; i++ ) {
2389                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2390                         * sizeof(struct IO_APIC_route_entry);
2391                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2392                 if (!mp_ioapic_data[i]) {
2393                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2394                         continue;
2395                 }
2396                 memset(mp_ioapic_data[i], 0, size);
2397                 dev = &mp_ioapic_data[i]->dev;
2398                 dev->id = i;
2399                 dev->cls = &ioapic_sysdev_class;
2400                 error = sysdev_register(dev);
2401                 if (error) {
2402                         kfree(mp_ioapic_data[i]);
2403                         mp_ioapic_data[i] = NULL;
2404                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2405                         continue;
2406                 }
2407         }
2408
2409         return 0;
2410 }
2411
2412 device_initcall(ioapic_init_sysfs);
2413
2414 /*
2415  * Dynamic irq allocate and deallocation
2416  */
2417 int create_irq(void)
2418 {
2419         /* Allocate an unused irq */
2420         int irq, new, vector = 0;
2421         unsigned long flags;
2422
2423         irq = -ENOSPC;
2424         spin_lock_irqsave(&vector_lock, flags);
2425         for (new = (NR_IRQS - 1); new >= 0; new--) {
2426                 if (platform_legacy_irq(new))
2427                         continue;
2428                 if (irq_vector[new] != 0)
2429                         continue;
2430                 vector = __assign_irq_vector(new);
2431                 if (likely(vector > 0))
2432                         irq = new;
2433                 break;
2434         }
2435         spin_unlock_irqrestore(&vector_lock, flags);
2436
2437         if (irq >= 0) {
2438                 set_intr_gate(vector, interrupt[irq]);
2439                 dynamic_irq_init(irq);
2440         }
2441         return irq;
2442 }
2443
2444 void destroy_irq(unsigned int irq)
2445 {
2446         unsigned long flags;
2447
2448         dynamic_irq_cleanup(irq);
2449
2450         spin_lock_irqsave(&vector_lock, flags);
2451         irq_vector[irq] = 0;
2452         spin_unlock_irqrestore(&vector_lock, flags);
2453 }
2454
2455 /*
2456  * MSI message composition
2457  */
2458 #ifdef CONFIG_PCI_MSI
2459 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2460 {
2461         int vector;
2462         unsigned dest;
2463
2464         vector = assign_irq_vector(irq);
2465         if (vector >= 0) {
2466                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2467
2468                 msg->address_hi = MSI_ADDR_BASE_HI;
2469                 msg->address_lo =
2470                         MSI_ADDR_BASE_LO |
2471                         ((INT_DEST_MODE == 0) ?
2472                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2473                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2474                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2475                                 MSI_ADDR_REDIRECTION_CPU:
2476                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2477                         MSI_ADDR_DEST_ID(dest);
2478
2479                 msg->data =
2480                         MSI_DATA_TRIGGER_EDGE |
2481                         MSI_DATA_LEVEL_ASSERT |
2482                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2483                                 MSI_DATA_DELIVERY_FIXED:
2484                                 MSI_DATA_DELIVERY_LOWPRI) |
2485                         MSI_DATA_VECTOR(vector);
2486         }
2487         return vector;
2488 }
2489
2490 #ifdef CONFIG_SMP
2491 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2492 {
2493         struct msi_msg msg;
2494         unsigned int dest;
2495         cpumask_t tmp;
2496         int vector;
2497
2498         cpus_and(tmp, mask, cpu_online_map);
2499         if (cpus_empty(tmp))
2500                 tmp = TARGET_CPUS;
2501
2502         vector = assign_irq_vector(irq);
2503         if (vector < 0)
2504                 return;
2505
2506         dest = cpu_mask_to_apicid(mask);
2507
2508         read_msi_msg(irq, &msg);
2509
2510         msg.data &= ~MSI_DATA_VECTOR_MASK;
2511         msg.data |= MSI_DATA_VECTOR(vector);
2512         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2513         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2514
2515         write_msi_msg(irq, &msg);
2516         irq_desc[irq].affinity = mask;
2517 }
2518 #endif /* CONFIG_SMP */
2519
2520 /*
2521  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2522  * which implement the MSI or MSI-X Capability Structure.
2523  */
2524 static struct irq_chip msi_chip = {
2525         .name           = "PCI-MSI",
2526         .unmask         = unmask_msi_irq,
2527         .mask           = mask_msi_irq,
2528         .ack            = ack_ioapic_irq,
2529 #ifdef CONFIG_SMP
2530         .set_affinity   = set_msi_irq_affinity,
2531 #endif
2532         .retrigger      = ioapic_retrigger_irq,
2533 };
2534
2535 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2536 {
2537         struct msi_msg msg;
2538         int irq, ret;
2539         irq = create_irq();
2540         if (irq < 0)
2541                 return irq;
2542
2543         ret = msi_compose_msg(dev, irq, &msg);
2544         if (ret < 0) {
2545                 destroy_irq(irq);
2546                 return ret;
2547         }
2548
2549         set_irq_msi(irq, desc);
2550         write_msi_msg(irq, &msg);
2551
2552         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2553                                       "edge");
2554
2555         return 0;
2556 }
2557
2558 void arch_teardown_msi_irq(unsigned int irq)
2559 {
2560         destroy_irq(irq);
2561 }
2562
2563 #endif /* CONFIG_PCI_MSI */
2564
2565 /*
2566  * Hypertransport interrupt support
2567  */
2568 #ifdef CONFIG_HT_IRQ
2569
2570 #ifdef CONFIG_SMP
2571
2572 static void target_ht_irq(unsigned int irq, unsigned int dest)
2573 {
2574         struct ht_irq_msg msg;
2575         fetch_ht_irq_msg(irq, &msg);
2576
2577         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2578         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2579
2580         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2581         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2582
2583         write_ht_irq_msg(irq, &msg);
2584 }
2585
2586 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2587 {
2588         unsigned int dest;
2589         cpumask_t tmp;
2590
2591         cpus_and(tmp, mask, cpu_online_map);
2592         if (cpus_empty(tmp))
2593                 tmp = TARGET_CPUS;
2594
2595         cpus_and(mask, tmp, CPU_MASK_ALL);
2596
2597         dest = cpu_mask_to_apicid(mask);
2598
2599         target_ht_irq(irq, dest);
2600         irq_desc[irq].affinity = mask;
2601 }
2602 #endif
2603
2604 static struct irq_chip ht_irq_chip = {
2605         .name           = "PCI-HT",
2606         .mask           = mask_ht_irq,
2607         .unmask         = unmask_ht_irq,
2608         .ack            = ack_ioapic_irq,
2609 #ifdef CONFIG_SMP
2610         .set_affinity   = set_ht_irq_affinity,
2611 #endif
2612         .retrigger      = ioapic_retrigger_irq,
2613 };
2614
2615 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2616 {
2617         int vector;
2618
2619         vector = assign_irq_vector(irq);
2620         if (vector >= 0) {
2621                 struct ht_irq_msg msg;
2622                 unsigned dest;
2623                 cpumask_t tmp;
2624
2625                 cpus_clear(tmp);
2626                 cpu_set(vector >> 8, tmp);
2627                 dest = cpu_mask_to_apicid(tmp);
2628
2629                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2630
2631                 msg.address_lo =
2632                         HT_IRQ_LOW_BASE |
2633                         HT_IRQ_LOW_DEST_ID(dest) |
2634                         HT_IRQ_LOW_VECTOR(vector) |
2635                         ((INT_DEST_MODE == 0) ?
2636                                 HT_IRQ_LOW_DM_PHYSICAL :
2637                                 HT_IRQ_LOW_DM_LOGICAL) |
2638                         HT_IRQ_LOW_RQEOI_EDGE |
2639                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2640                                 HT_IRQ_LOW_MT_FIXED :
2641                                 HT_IRQ_LOW_MT_ARBITRATED) |
2642                         HT_IRQ_LOW_IRQ_MASKED;
2643
2644                 write_ht_irq_msg(irq, &msg);
2645
2646                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2647                                               handle_edge_irq, "edge");
2648         }
2649         return vector;
2650 }
2651 #endif /* CONFIG_HT_IRQ */
2652
2653 /* --------------------------------------------------------------------------
2654                           ACPI-based IOAPIC Configuration
2655    -------------------------------------------------------------------------- */
2656
2657 #ifdef CONFIG_ACPI
2658
2659 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2660 {
2661         union IO_APIC_reg_00 reg_00;
2662         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2663         physid_mask_t tmp;
2664         unsigned long flags;
2665         int i = 0;
2666
2667         /*
2668          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2669          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2670          * supports up to 16 on one shared APIC bus.
2671          *
2672          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2673          *      advantage of new APIC bus architecture.
2674          */
2675
2676         if (physids_empty(apic_id_map))
2677                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2678
2679         spin_lock_irqsave(&ioapic_lock, flags);
2680         reg_00.raw = io_apic_read(ioapic, 0);
2681         spin_unlock_irqrestore(&ioapic_lock, flags);
2682
2683         if (apic_id >= get_physical_broadcast()) {
2684                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2685                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2686                 apic_id = reg_00.bits.ID;
2687         }
2688
2689         /*
2690          * Every APIC in a system must have a unique ID or we get lots of nice
2691          * 'stuck on smp_invalidate_needed IPI wait' messages.
2692          */
2693         if (check_apicid_used(apic_id_map, apic_id)) {
2694
2695                 for (i = 0; i < get_physical_broadcast(); i++) {
2696                         if (!check_apicid_used(apic_id_map, i))
2697                                 break;
2698                 }
2699
2700                 if (i == get_physical_broadcast())
2701                         panic("Max apic_id exceeded!\n");
2702
2703                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2704                         "trying %d\n", ioapic, apic_id, i);
2705
2706                 apic_id = i;
2707         }
2708
2709         tmp = apicid_to_cpu_present(apic_id);
2710         physids_or(apic_id_map, apic_id_map, tmp);
2711
2712         if (reg_00.bits.ID != apic_id) {
2713                 reg_00.bits.ID = apic_id;
2714
2715                 spin_lock_irqsave(&ioapic_lock, flags);
2716                 io_apic_write(ioapic, 0, reg_00.raw);
2717                 reg_00.raw = io_apic_read(ioapic, 0);
2718                 spin_unlock_irqrestore(&ioapic_lock, flags);
2719
2720                 /* Sanity check */
2721                 if (reg_00.bits.ID != apic_id) {
2722                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2723                         return -1;
2724                 }
2725         }
2726
2727         apic_printk(APIC_VERBOSE, KERN_INFO
2728                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2729
2730         return apic_id;
2731 }
2732
2733
2734 int __init io_apic_get_version (int ioapic)
2735 {
2736         union IO_APIC_reg_01    reg_01;
2737         unsigned long flags;
2738
2739         spin_lock_irqsave(&ioapic_lock, flags);
2740         reg_01.raw = io_apic_read(ioapic, 1);
2741         spin_unlock_irqrestore(&ioapic_lock, flags);
2742
2743         return reg_01.bits.version;
2744 }
2745
2746
2747 int __init io_apic_get_redir_entries (int ioapic)
2748 {
2749         union IO_APIC_reg_01    reg_01;
2750         unsigned long flags;
2751
2752         spin_lock_irqsave(&ioapic_lock, flags);
2753         reg_01.raw = io_apic_read(ioapic, 1);
2754         spin_unlock_irqrestore(&ioapic_lock, flags);
2755
2756         return reg_01.bits.entries;
2757 }
2758
2759
2760 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2761 {
2762         struct IO_APIC_route_entry entry;
2763         unsigned long flags;
2764
2765         if (!IO_APIC_IRQ(irq)) {
2766                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2767                         ioapic);
2768                 return -EINVAL;
2769         }
2770
2771         /*
2772          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2773          * Note that we mask (disable) IRQs now -- these get enabled when the
2774          * corresponding device driver registers for this IRQ.
2775          */
2776
2777         memset(&entry,0,sizeof(entry));
2778
2779         entry.delivery_mode = INT_DELIVERY_MODE;
2780         entry.dest_mode = INT_DEST_MODE;
2781         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2782         entry.trigger = edge_level;
2783         entry.polarity = active_high_low;
2784         entry.mask  = 1;
2785
2786         /*
2787          * IRQs < 16 are already in the irq_2_pin[] map
2788          */
2789         if (irq >= 16)
2790                 add_pin_to_irq(irq, ioapic, pin);
2791
2792         entry.vector = assign_irq_vector(irq);
2793
2794         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2795                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2796                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2797                 edge_level, active_high_low);
2798
2799         ioapic_register_intr(irq, entry.vector, edge_level);
2800
2801         if (!ioapic && (irq < 16))
2802                 disable_8259A_irq(irq);
2803
2804         spin_lock_irqsave(&ioapic_lock, flags);
2805         __ioapic_write_entry(ioapic, pin, entry);
2806         spin_unlock_irqrestore(&ioapic_lock, flags);
2807
2808         return 0;
2809 }
2810
2811 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2812 {
2813         int i;
2814
2815         if (skip_ioapic_setup)
2816                 return -1;
2817
2818         for (i = 0; i < mp_irq_entries; i++)
2819                 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2820                     mp_irqs[i].mpc_srcbusirq == bus_irq)
2821                         break;
2822         if (i >= mp_irq_entries)
2823                 return -1;
2824
2825         *trigger = irq_trigger(i);
2826         *polarity = irq_polarity(i);
2827         return 0;
2828 }
2829
2830 #endif /* CONFIG_ACPI */
2831
2832 static int __init parse_disable_timer_pin_1(char *arg)
2833 {
2834         disable_timer_pin_1 = 1;
2835         return 0;
2836 }
2837 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2838
2839 static int __init parse_enable_timer_pin_1(char *arg)
2840 {
2841         disable_timer_pin_1 = -1;
2842         return 0;
2843 }
2844 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2845
2846 static int __init parse_noapic(char *arg)
2847 {
2848         /* disable IO-APIC */
2849         disable_ioapic_setup();
2850         return 0;
2851 }
2852 early_param("noapic", parse_noapic);