b5680780fa951edfcf8b4616d7ee0e95bb18ae6f
[sfrench/cifs-2.6.git] / arch / x86 / kernel / io_apic_32.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h>      /* time_after() */
39
40 #include <asm/io.h>
41 #include <asm/smp.h>
42 #include <asm/desc.h>
43 #include <asm/timer.h>
44 #include <asm/i8259.h>
45 #include <asm/nmi.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
48
49 #include <mach_apic.h>
50 #include <mach_apicdef.h>
51
52 int (*ioapic_renumber_irq)(int ioapic, int irq);
53 atomic_t irq_mis_count;
54
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
57
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
60
61 int timer_over_8254 __initdata = 1;
62
63 /*
64  *      Is the SiS APIC rmw bug present ?
65  *      -1 = don't know, 0 = no, 1 = yes
66  */
67 int sis_apic_bug = -1;
68
69 /*
70  * # of IRQ routing registers
71  */
72 int nr_ioapic_registers[MAX_IO_APICS];
73
74 static int disable_timer_pin_1 __initdata;
75
76 /*
77  * Rough estimation of how many shared IRQs there are, can
78  * be changed anytime.
79  */
80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
82
83 /*
84  * This is performance-critical, we want to do it O(1)
85  *
86  * the indexing order of this array favors 1:1 mappings
87  * between pins and IRQs.
88  */
89
90 static struct irq_pin_list {
91         int apic, pin, next;
92 } irq_2_pin[PIN_MAP_SIZE];
93
94 struct io_apic {
95         unsigned int index;
96         unsigned int unused[3];
97         unsigned int data;
98 };
99
100 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
101 {
102         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
103                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
104 }
105
106 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
107 {
108         struct io_apic __iomem *io_apic = io_apic_base(apic);
109         writel(reg, &io_apic->index);
110         return readl(&io_apic->data);
111 }
112
113 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
114 {
115         struct io_apic __iomem *io_apic = io_apic_base(apic);
116         writel(reg, &io_apic->index);
117         writel(value, &io_apic->data);
118 }
119
120 /*
121  * Re-write a value: to be used for read-modify-write
122  * cycles where the read already set up the index register.
123  *
124  * Older SiS APIC requires we rewrite the index register
125  */
126 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
127 {
128         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
129         if (sis_apic_bug)
130                 writel(reg, &io_apic->index);
131         writel(value, &io_apic->data);
132 }
133
134 union entry_union {
135         struct { u32 w1, w2; };
136         struct IO_APIC_route_entry entry;
137 };
138
139 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
140 {
141         union entry_union eu;
142         unsigned long flags;
143         spin_lock_irqsave(&ioapic_lock, flags);
144         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
145         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
146         spin_unlock_irqrestore(&ioapic_lock, flags);
147         return eu.entry;
148 }
149
150 /*
151  * When we write a new IO APIC routing entry, we need to write the high
152  * word first! If the mask bit in the low word is clear, we will enable
153  * the interrupt, and we need to make sure the entry is fully populated
154  * before that happens.
155  */
156 static void
157 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
158 {
159         union entry_union eu;
160         eu.entry = e;
161         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
162         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
163 }
164
165 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
166 {
167         unsigned long flags;
168         spin_lock_irqsave(&ioapic_lock, flags);
169         __ioapic_write_entry(apic, pin, e);
170         spin_unlock_irqrestore(&ioapic_lock, flags);
171 }
172
173 /*
174  * When we mask an IO APIC routing entry, we need to write the low
175  * word first, in order to set the mask bit before we change the
176  * high bits!
177  */
178 static void ioapic_mask_entry(int apic, int pin)
179 {
180         unsigned long flags;
181         union entry_union eu = { .entry.mask = 1 };
182
183         spin_lock_irqsave(&ioapic_lock, flags);
184         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
185         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
186         spin_unlock_irqrestore(&ioapic_lock, flags);
187 }
188
189 /*
190  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
191  * shared ISA-space IRQs, so we have to support them. We are super
192  * fast in the common case, and fast for shared ISA-space IRQs.
193  */
194 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
195 {
196         static int first_free_entry = NR_IRQS;
197         struct irq_pin_list *entry = irq_2_pin + irq;
198
199         while (entry->next)
200                 entry = irq_2_pin + entry->next;
201
202         if (entry->pin != -1) {
203                 entry->next = first_free_entry;
204                 entry = irq_2_pin + entry->next;
205                 if (++first_free_entry >= PIN_MAP_SIZE)
206                         panic("io_apic.c: whoops");
207         }
208         entry->apic = apic;
209         entry->pin = pin;
210 }
211
212 /*
213  * Reroute an IRQ to a different pin.
214  */
215 static void __init replace_pin_at_irq(unsigned int irq,
216                                       int oldapic, int oldpin,
217                                       int newapic, int newpin)
218 {
219         struct irq_pin_list *entry = irq_2_pin + irq;
220
221         while (1) {
222                 if (entry->apic == oldapic && entry->pin == oldpin) {
223                         entry->apic = newapic;
224                         entry->pin = newpin;
225                 }
226                 if (!entry->next)
227                         break;
228                 entry = irq_2_pin + entry->next;
229         }
230 }
231
232 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
233 {
234         struct irq_pin_list *entry = irq_2_pin + irq;
235         unsigned int pin, reg;
236
237         for (;;) {
238                 pin = entry->pin;
239                 if (pin == -1)
240                         break;
241                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
242                 reg &= ~disable;
243                 reg |= enable;
244                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
245                 if (!entry->next)
246                         break;
247                 entry = irq_2_pin + entry->next;
248         }
249 }
250
251 /* mask = 1 */
252 static void __mask_IO_APIC_irq (unsigned int irq)
253 {
254         __modify_IO_APIC_irq(irq, 0x00010000, 0);
255 }
256
257 /* mask = 0 */
258 static void __unmask_IO_APIC_irq (unsigned int irq)
259 {
260         __modify_IO_APIC_irq(irq, 0, 0x00010000);
261 }
262
263 /* mask = 1, trigger = 0 */
264 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
265 {
266         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
267 }
268
269 /* mask = 0, trigger = 1 */
270 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
271 {
272         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
273 }
274
275 static void mask_IO_APIC_irq (unsigned int irq)
276 {
277         unsigned long flags;
278
279         spin_lock_irqsave(&ioapic_lock, flags);
280         __mask_IO_APIC_irq(irq);
281         spin_unlock_irqrestore(&ioapic_lock, flags);
282 }
283
284 static void unmask_IO_APIC_irq (unsigned int irq)
285 {
286         unsigned long flags;
287
288         spin_lock_irqsave(&ioapic_lock, flags);
289         __unmask_IO_APIC_irq(irq);
290         spin_unlock_irqrestore(&ioapic_lock, flags);
291 }
292
293 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
294 {
295         struct IO_APIC_route_entry entry;
296         
297         /* Check delivery_mode to be sure we're not clearing an SMI pin */
298         entry = ioapic_read_entry(apic, pin);
299         if (entry.delivery_mode == dest_SMI)
300                 return;
301
302         /*
303          * Disable it in the IO-APIC irq-routing table:
304          */
305         ioapic_mask_entry(apic, pin);
306 }
307
308 static void clear_IO_APIC (void)
309 {
310         int apic, pin;
311
312         for (apic = 0; apic < nr_ioapics; apic++)
313                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
314                         clear_IO_APIC_pin(apic, pin);
315 }
316
317 #ifdef CONFIG_SMP
318 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
319 {
320         unsigned long flags;
321         int pin;
322         struct irq_pin_list *entry = irq_2_pin + irq;
323         unsigned int apicid_value;
324         cpumask_t tmp;
325         
326         cpus_and(tmp, cpumask, cpu_online_map);
327         if (cpus_empty(tmp))
328                 tmp = TARGET_CPUS;
329
330         cpus_and(cpumask, tmp, CPU_MASK_ALL);
331
332         apicid_value = cpu_mask_to_apicid(cpumask);
333         /* Prepare to do the io_apic_write */
334         apicid_value = apicid_value << 24;
335         spin_lock_irqsave(&ioapic_lock, flags);
336         for (;;) {
337                 pin = entry->pin;
338                 if (pin == -1)
339                         break;
340                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
341                 if (!entry->next)
342                         break;
343                 entry = irq_2_pin + entry->next;
344         }
345         irq_desc[irq].affinity = cpumask;
346         spin_unlock_irqrestore(&ioapic_lock, flags);
347 }
348
349 #if defined(CONFIG_IRQBALANCE)
350 # include <asm/processor.h>     /* kernel_thread() */
351 # include <linux/kernel_stat.h> /* kstat */
352 # include <linux/slab.h>                /* kmalloc() */
353 # include <linux/timer.h>
354  
355 #define IRQBALANCE_CHECK_ARCH -999
356 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
357 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
358 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
359 #define BALANCED_IRQ_LESS_DELTA         (HZ)
360
361 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
362 static int physical_balance __read_mostly;
363 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
364
365 static struct irq_cpu_info {
366         unsigned long * last_irq;
367         unsigned long * irq_delta;
368         unsigned long irq;
369 } irq_cpu_data[NR_CPUS];
370
371 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
372 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
373 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
374
375 #define IDLE_ENOUGH(cpu,now) \
376         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
377
378 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
379
380 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
381
382 static cpumask_t balance_irq_affinity[NR_IRQS] = {
383         [0 ... NR_IRQS-1] = CPU_MASK_ALL
384 };
385
386 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
387 {
388         balance_irq_affinity[irq] = mask;
389 }
390
391 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
392                         unsigned long now, int direction)
393 {
394         int search_idle = 1;
395         int cpu = curr_cpu;
396
397         goto inside;
398
399         do {
400                 if (unlikely(cpu == curr_cpu))
401                         search_idle = 0;
402 inside:
403                 if (direction == 1) {
404                         cpu++;
405                         if (cpu >= NR_CPUS)
406                                 cpu = 0;
407                 } else {
408                         cpu--;
409                         if (cpu == -1)
410                                 cpu = NR_CPUS-1;
411                 }
412         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
413                         (search_idle && !IDLE_ENOUGH(cpu,now)));
414
415         return cpu;
416 }
417
418 static inline void balance_irq(int cpu, int irq)
419 {
420         unsigned long now = jiffies;
421         cpumask_t allowed_mask;
422         unsigned int new_cpu;
423                 
424         if (irqbalance_disabled)
425                 return; 
426
427         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
428         new_cpu = move(cpu, allowed_mask, now, 1);
429         if (cpu != new_cpu) {
430                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
431         }
432 }
433
434 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
435 {
436         int i, j;
437
438         for_each_online_cpu(i) {
439                 for (j = 0; j < NR_IRQS; j++) {
440                         if (!irq_desc[j].action)
441                                 continue;
442                         /* Is it a significant load ?  */
443                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
444                                                 useful_load_threshold)
445                                 continue;
446                         balance_irq(i, j);
447                 }
448         }
449         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
450                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
451         return;
452 }
453
454 static void do_irq_balance(void)
455 {
456         int i, j;
457         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
458         unsigned long move_this_load = 0;
459         int max_loaded = 0, min_loaded = 0;
460         int load;
461         unsigned long useful_load_threshold = balanced_irq_interval + 10;
462         int selected_irq;
463         int tmp_loaded, first_attempt = 1;
464         unsigned long tmp_cpu_irq;
465         unsigned long imbalance = 0;
466         cpumask_t allowed_mask, target_cpu_mask, tmp;
467
468         for_each_possible_cpu(i) {
469                 int package_index;
470                 CPU_IRQ(i) = 0;
471                 if (!cpu_online(i))
472                         continue;
473                 package_index = CPU_TO_PACKAGEINDEX(i);
474                 for (j = 0; j < NR_IRQS; j++) {
475                         unsigned long value_now, delta;
476                         /* Is this an active IRQ or balancing disabled ? */
477                         if (!irq_desc[j].action || irq_balancing_disabled(j))
478                                 continue;
479                         if ( package_index == i )
480                                 IRQ_DELTA(package_index,j) = 0;
481                         /* Determine the total count per processor per IRQ */
482                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
483
484                         /* Determine the activity per processor per IRQ */
485                         delta = value_now - LAST_CPU_IRQ(i,j);
486
487                         /* Update last_cpu_irq[][] for the next time */
488                         LAST_CPU_IRQ(i,j) = value_now;
489
490                         /* Ignore IRQs whose rate is less than the clock */
491                         if (delta < useful_load_threshold)
492                                 continue;
493                         /* update the load for the processor or package total */
494                         IRQ_DELTA(package_index,j) += delta;
495
496                         /* Keep track of the higher numbered sibling as well */
497                         if (i != package_index)
498                                 CPU_IRQ(i) += delta;
499                         /*
500                          * We have sibling A and sibling B in the package
501                          *
502                          * cpu_irq[A] = load for cpu A + load for cpu B
503                          * cpu_irq[B] = load for cpu B
504                          */
505                         CPU_IRQ(package_index) += delta;
506                 }
507         }
508         /* Find the least loaded processor package */
509         for_each_online_cpu(i) {
510                 if (i != CPU_TO_PACKAGEINDEX(i))
511                         continue;
512                 if (min_cpu_irq > CPU_IRQ(i)) {
513                         min_cpu_irq = CPU_IRQ(i);
514                         min_loaded = i;
515                 }
516         }
517         max_cpu_irq = ULONG_MAX;
518
519 tryanothercpu:
520         /* Look for heaviest loaded processor.
521          * We may come back to get the next heaviest loaded processor.
522          * Skip processors with trivial loads.
523          */
524         tmp_cpu_irq = 0;
525         tmp_loaded = -1;
526         for_each_online_cpu(i) {
527                 if (i != CPU_TO_PACKAGEINDEX(i))
528                         continue;
529                 if (max_cpu_irq <= CPU_IRQ(i)) 
530                         continue;
531                 if (tmp_cpu_irq < CPU_IRQ(i)) {
532                         tmp_cpu_irq = CPU_IRQ(i);
533                         tmp_loaded = i;
534                 }
535         }
536
537         if (tmp_loaded == -1) {
538          /* In the case of small number of heavy interrupt sources, 
539           * loading some of the cpus too much. We use Ingo's original 
540           * approach to rotate them around.
541           */
542                 if (!first_attempt && imbalance >= useful_load_threshold) {
543                         rotate_irqs_among_cpus(useful_load_threshold);
544                         return;
545                 }
546                 goto not_worth_the_effort;
547         }
548         
549         first_attempt = 0;              /* heaviest search */
550         max_cpu_irq = tmp_cpu_irq;      /* load */
551         max_loaded = tmp_loaded;        /* processor */
552         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
553         
554         /* if imbalance is less than approx 10% of max load, then
555          * observe diminishing returns action. - quit
556          */
557         if (imbalance < (max_cpu_irq >> 3))
558                 goto not_worth_the_effort;
559
560 tryanotherirq:
561         /* if we select an IRQ to move that can't go where we want, then
562          * see if there is another one to try.
563          */
564         move_this_load = 0;
565         selected_irq = -1;
566         for (j = 0; j < NR_IRQS; j++) {
567                 /* Is this an active IRQ? */
568                 if (!irq_desc[j].action)
569                         continue;
570                 if (imbalance <= IRQ_DELTA(max_loaded,j))
571                         continue;
572                 /* Try to find the IRQ that is closest to the imbalance
573                  * without going over.
574                  */
575                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
576                         move_this_load = IRQ_DELTA(max_loaded,j);
577                         selected_irq = j;
578                 }
579         }
580         if (selected_irq == -1) {
581                 goto tryanothercpu;
582         }
583
584         imbalance = move_this_load;
585         
586         /* For physical_balance case, we accumulated both load
587          * values in the one of the siblings cpu_irq[],
588          * to use the same code for physical and logical processors
589          * as much as possible. 
590          *
591          * NOTE: the cpu_irq[] array holds the sum of the load for
592          * sibling A and sibling B in the slot for the lowest numbered
593          * sibling (A), _AND_ the load for sibling B in the slot for
594          * the higher numbered sibling.
595          *
596          * We seek the least loaded sibling by making the comparison
597          * (A+B)/2 vs B
598          */
599         load = CPU_IRQ(min_loaded) >> 1;
600         for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
601                 if (load > CPU_IRQ(j)) {
602                         /* This won't change cpu_sibling_map[min_loaded] */
603                         load = CPU_IRQ(j);
604                         min_loaded = j;
605                 }
606         }
607
608         cpus_and(allowed_mask,
609                 cpu_online_map,
610                 balance_irq_affinity[selected_irq]);
611         target_cpu_mask = cpumask_of_cpu(min_loaded);
612         cpus_and(tmp, target_cpu_mask, allowed_mask);
613
614         if (!cpus_empty(tmp)) {
615                 /* mark for change destination */
616                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
617
618                 /* Since we made a change, come back sooner to 
619                  * check for more variation.
620                  */
621                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
622                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
623                 return;
624         }
625         goto tryanotherirq;
626
627 not_worth_the_effort:
628         /*
629          * if we did not find an IRQ to move, then adjust the time interval
630          * upward
631          */
632         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
633                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);       
634         return;
635 }
636
637 static int balanced_irq(void *unused)
638 {
639         int i;
640         unsigned long prev_balance_time = jiffies;
641         long time_remaining = balanced_irq_interval;
642
643         /* push everything to CPU 0 to give us a starting point.  */
644         for (i = 0 ; i < NR_IRQS ; i++) {
645                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
646                 set_pending_irq(i, cpumask_of_cpu(0));
647         }
648
649         set_freezable();
650         for ( ; ; ) {
651                 time_remaining = schedule_timeout_interruptible(time_remaining);
652                 try_to_freeze();
653                 if (time_after(jiffies,
654                                 prev_balance_time+balanced_irq_interval)) {
655                         preempt_disable();
656                         do_irq_balance();
657                         prev_balance_time = jiffies;
658                         time_remaining = balanced_irq_interval;
659                         preempt_enable();
660                 }
661         }
662         return 0;
663 }
664
665 static int __init balanced_irq_init(void)
666 {
667         int i;
668         struct cpuinfo_x86 *c;
669         cpumask_t tmp;
670
671         cpus_shift_right(tmp, cpu_online_map, 2);
672         c = &boot_cpu_data;
673         /* When not overwritten by the command line ask subarchitecture. */
674         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
675                 irqbalance_disabled = NO_BALANCE_IRQ;
676         if (irqbalance_disabled)
677                 return 0;
678         
679          /* disable irqbalance completely if there is only one processor online */
680         if (num_online_cpus() < 2) {
681                 irqbalance_disabled = 1;
682                 return 0;
683         }
684         /*
685          * Enable physical balance only if more than 1 physical processor
686          * is present
687          */
688         if (smp_num_siblings > 1 && !cpus_empty(tmp))
689                 physical_balance = 1;
690
691         for_each_online_cpu(i) {
692                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
693                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
694                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
695                         printk(KERN_ERR "balanced_irq_init: out of memory");
696                         goto failed;
697                 }
698                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
699                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
700         }
701         
702         printk(KERN_INFO "Starting balanced_irq\n");
703         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
704                 return 0;
705         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
706 failed:
707         for_each_possible_cpu(i) {
708                 kfree(irq_cpu_data[i].irq_delta);
709                 irq_cpu_data[i].irq_delta = NULL;
710                 kfree(irq_cpu_data[i].last_irq);
711                 irq_cpu_data[i].last_irq = NULL;
712         }
713         return 0;
714 }
715
716 int __devinit irqbalance_disable(char *str)
717 {
718         irqbalance_disabled = 1;
719         return 1;
720 }
721
722 __setup("noirqbalance", irqbalance_disable);
723
724 late_initcall(balanced_irq_init);
725 #endif /* CONFIG_IRQBALANCE */
726 #endif /* CONFIG_SMP */
727
728 #ifndef CONFIG_SMP
729 void send_IPI_self(int vector)
730 {
731         unsigned int cfg;
732
733         /*
734          * Wait for idle.
735          */
736         apic_wait_icr_idle();
737         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
738         /*
739          * Send the IPI. The write to APIC_ICR fires this off.
740          */
741         apic_write_around(APIC_ICR, cfg);
742 }
743 #endif /* !CONFIG_SMP */
744
745
746 /*
747  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
748  * specific CPU-side IRQs.
749  */
750
751 #define MAX_PIRQS 8
752 static int pirq_entries [MAX_PIRQS];
753 static int pirqs_enabled;
754 int skip_ioapic_setup;
755
756 static int __init ioapic_pirq_setup(char *str)
757 {
758         int i, max;
759         int ints[MAX_PIRQS+1];
760
761         get_options(str, ARRAY_SIZE(ints), ints);
762
763         for (i = 0; i < MAX_PIRQS; i++)
764                 pirq_entries[i] = -1;
765
766         pirqs_enabled = 1;
767         apic_printk(APIC_VERBOSE, KERN_INFO
768                         "PIRQ redirection, working around broken MP-BIOS.\n");
769         max = MAX_PIRQS;
770         if (ints[0] < MAX_PIRQS)
771                 max = ints[0];
772
773         for (i = 0; i < max; i++) {
774                 apic_printk(APIC_VERBOSE, KERN_DEBUG
775                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
776                 /*
777                  * PIRQs are mapped upside down, usually.
778                  */
779                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
780         }
781         return 1;
782 }
783
784 __setup("pirq=", ioapic_pirq_setup);
785
786 /*
787  * Find the IRQ entry number of a certain pin.
788  */
789 static int find_irq_entry(int apic, int pin, int type)
790 {
791         int i;
792
793         for (i = 0; i < mp_irq_entries; i++)
794                 if (mp_irqs[i].mpc_irqtype == type &&
795                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
796                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
797                     mp_irqs[i].mpc_dstirq == pin)
798                         return i;
799
800         return -1;
801 }
802
803 /*
804  * Find the pin to which IRQ[irq] (ISA) is connected
805  */
806 static int __init find_isa_irq_pin(int irq, int type)
807 {
808         int i;
809
810         for (i = 0; i < mp_irq_entries; i++) {
811                 int lbus = mp_irqs[i].mpc_srcbus;
812
813                 if (test_bit(lbus, mp_bus_not_pci) &&
814                     (mp_irqs[i].mpc_irqtype == type) &&
815                     (mp_irqs[i].mpc_srcbusirq == irq))
816
817                         return mp_irqs[i].mpc_dstirq;
818         }
819         return -1;
820 }
821
822 static int __init find_isa_irq_apic(int irq, int type)
823 {
824         int i;
825
826         for (i = 0; i < mp_irq_entries; i++) {
827                 int lbus = mp_irqs[i].mpc_srcbus;
828
829                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
830                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
831                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
832                     ) &&
833                     (mp_irqs[i].mpc_irqtype == type) &&
834                     (mp_irqs[i].mpc_srcbusirq == irq))
835                         break;
836         }
837         if (i < mp_irq_entries) {
838                 int apic;
839                 for(apic = 0; apic < nr_ioapics; apic++) {
840                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
841                                 return apic;
842                 }
843         }
844
845         return -1;
846 }
847
848 /*
849  * Find a specific PCI IRQ entry.
850  * Not an __init, possibly needed by modules
851  */
852 static int pin_2_irq(int idx, int apic, int pin);
853
854 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
855 {
856         int apic, i, best_guess = -1;
857
858         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
859                 "slot:%d, pin:%d.\n", bus, slot, pin);
860         if (mp_bus_id_to_pci_bus[bus] == -1) {
861                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
862                 return -1;
863         }
864         for (i = 0; i < mp_irq_entries; i++) {
865                 int lbus = mp_irqs[i].mpc_srcbus;
866
867                 for (apic = 0; apic < nr_ioapics; apic++)
868                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
869                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
870                                 break;
871
872                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
873                     !mp_irqs[i].mpc_irqtype &&
874                     (bus == lbus) &&
875                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
876                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
877
878                         if (!(apic || IO_APIC_IRQ(irq)))
879                                 continue;
880
881                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
882                                 return irq;
883                         /*
884                          * Use the first all-but-pin matching entry as a
885                          * best-guess fuzzy result for broken mptables.
886                          */
887                         if (best_guess < 0)
888                                 best_guess = irq;
889                 }
890         }
891         return best_guess;
892 }
893 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
894
895 /*
896  * This function currently is only a helper for the i386 smp boot process where 
897  * we need to reprogram the ioredtbls to cater for the cpus which have come online
898  * so mask in all cases should simply be TARGET_CPUS
899  */
900 #ifdef CONFIG_SMP
901 void __init setup_ioapic_dest(void)
902 {
903         int pin, ioapic, irq, irq_entry;
904
905         if (skip_ioapic_setup == 1)
906                 return;
907
908         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
909                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
910                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
911                         if (irq_entry == -1)
912                                 continue;
913                         irq = pin_2_irq(irq_entry, ioapic, pin);
914                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
915                 }
916
917         }
918 }
919 #endif
920
921 /*
922  * EISA Edge/Level control register, ELCR
923  */
924 static int EISA_ELCR(unsigned int irq)
925 {
926         if (irq < 16) {
927                 unsigned int port = 0x4d0 + (irq >> 3);
928                 return (inb(port) >> (irq & 7)) & 1;
929         }
930         apic_printk(APIC_VERBOSE, KERN_INFO
931                         "Broken MPtable reports ISA irq %d\n", irq);
932         return 0;
933 }
934
935 /* EISA interrupts are always polarity zero and can be edge or level
936  * trigger depending on the ELCR value.  If an interrupt is listed as
937  * EISA conforming in the MP table, that means its trigger type must
938  * be read in from the ELCR */
939
940 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
941 #define default_EISA_polarity(idx)      (0)
942
943 /* ISA interrupts are always polarity zero edge triggered,
944  * when listed as conforming in the MP table. */
945
946 #define default_ISA_trigger(idx)        (0)
947 #define default_ISA_polarity(idx)       (0)
948
949 /* PCI interrupts are always polarity one level triggered,
950  * when listed as conforming in the MP table. */
951
952 #define default_PCI_trigger(idx)        (1)
953 #define default_PCI_polarity(idx)       (1)
954
955 /* MCA interrupts are always polarity zero level triggered,
956  * when listed as conforming in the MP table. */
957
958 #define default_MCA_trigger(idx)        (1)
959 #define default_MCA_polarity(idx)       (0)
960
961 static int MPBIOS_polarity(int idx)
962 {
963         int bus = mp_irqs[idx].mpc_srcbus;
964         int polarity;
965
966         /*
967          * Determine IRQ line polarity (high active or low active):
968          */
969         switch (mp_irqs[idx].mpc_irqflag & 3)
970         {
971                 case 0: /* conforms, ie. bus-type dependent polarity */
972                 {
973                         switch (mp_bus_id_to_type[bus])
974                         {
975                                 case MP_BUS_ISA: /* ISA pin */
976                                 {
977                                         polarity = default_ISA_polarity(idx);
978                                         break;
979                                 }
980                                 case MP_BUS_EISA: /* EISA pin */
981                                 {
982                                         polarity = default_EISA_polarity(idx);
983                                         break;
984                                 }
985                                 case MP_BUS_PCI: /* PCI pin */
986                                 {
987                                         polarity = default_PCI_polarity(idx);
988                                         break;
989                                 }
990                                 case MP_BUS_MCA: /* MCA pin */
991                                 {
992                                         polarity = default_MCA_polarity(idx);
993                                         break;
994                                 }
995                                 default:
996                                 {
997                                         printk(KERN_WARNING "broken BIOS!!\n");
998                                         polarity = 1;
999                                         break;
1000                                 }
1001                         }
1002                         break;
1003                 }
1004                 case 1: /* high active */
1005                 {
1006                         polarity = 0;
1007                         break;
1008                 }
1009                 case 2: /* reserved */
1010                 {
1011                         printk(KERN_WARNING "broken BIOS!!\n");
1012                         polarity = 1;
1013                         break;
1014                 }
1015                 case 3: /* low active */
1016                 {
1017                         polarity = 1;
1018                         break;
1019                 }
1020                 default: /* invalid */
1021                 {
1022                         printk(KERN_WARNING "broken BIOS!!\n");
1023                         polarity = 1;
1024                         break;
1025                 }
1026         }
1027         return polarity;
1028 }
1029
1030 static int MPBIOS_trigger(int idx)
1031 {
1032         int bus = mp_irqs[idx].mpc_srcbus;
1033         int trigger;
1034
1035         /*
1036          * Determine IRQ trigger mode (edge or level sensitive):
1037          */
1038         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1039         {
1040                 case 0: /* conforms, ie. bus-type dependent */
1041                 {
1042                         switch (mp_bus_id_to_type[bus])
1043                         {
1044                                 case MP_BUS_ISA: /* ISA pin */
1045                                 {
1046                                         trigger = default_ISA_trigger(idx);
1047                                         break;
1048                                 }
1049                                 case MP_BUS_EISA: /* EISA pin */
1050                                 {
1051                                         trigger = default_EISA_trigger(idx);
1052                                         break;
1053                                 }
1054                                 case MP_BUS_PCI: /* PCI pin */
1055                                 {
1056                                         trigger = default_PCI_trigger(idx);
1057                                         break;
1058                                 }
1059                                 case MP_BUS_MCA: /* MCA pin */
1060                                 {
1061                                         trigger = default_MCA_trigger(idx);
1062                                         break;
1063                                 }
1064                                 default:
1065                                 {
1066                                         printk(KERN_WARNING "broken BIOS!!\n");
1067                                         trigger = 1;
1068                                         break;
1069                                 }
1070                         }
1071                         break;
1072                 }
1073                 case 1: /* edge */
1074                 {
1075                         trigger = 0;
1076                         break;
1077                 }
1078                 case 2: /* reserved */
1079                 {
1080                         printk(KERN_WARNING "broken BIOS!!\n");
1081                         trigger = 1;
1082                         break;
1083                 }
1084                 case 3: /* level */
1085                 {
1086                         trigger = 1;
1087                         break;
1088                 }
1089                 default: /* invalid */
1090                 {
1091                         printk(KERN_WARNING "broken BIOS!!\n");
1092                         trigger = 0;
1093                         break;
1094                 }
1095         }
1096         return trigger;
1097 }
1098
1099 static inline int irq_polarity(int idx)
1100 {
1101         return MPBIOS_polarity(idx);
1102 }
1103
1104 static inline int irq_trigger(int idx)
1105 {
1106         return MPBIOS_trigger(idx);
1107 }
1108
1109 static int pin_2_irq(int idx, int apic, int pin)
1110 {
1111         int irq, i;
1112         int bus = mp_irqs[idx].mpc_srcbus;
1113
1114         /*
1115          * Debugging check, we are in big trouble if this message pops up!
1116          */
1117         if (mp_irqs[idx].mpc_dstirq != pin)
1118                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1119
1120         switch (mp_bus_id_to_type[bus])
1121         {
1122                 case MP_BUS_ISA: /* ISA pin */
1123                 case MP_BUS_EISA:
1124                 case MP_BUS_MCA:
1125                 {
1126                         irq = mp_irqs[idx].mpc_srcbusirq;
1127                         break;
1128                 }
1129                 case MP_BUS_PCI: /* PCI pin */
1130                 {
1131                         /*
1132                          * PCI IRQs are mapped in order
1133                          */
1134                         i = irq = 0;
1135                         while (i < apic)
1136                                 irq += nr_ioapic_registers[i++];
1137                         irq += pin;
1138
1139                         /*
1140                          * For MPS mode, so far only needed by ES7000 platform
1141                          */
1142                         if (ioapic_renumber_irq)
1143                                 irq = ioapic_renumber_irq(apic, irq);
1144
1145                         break;
1146                 }
1147                 default:
1148                 {
1149                         printk(KERN_ERR "unknown bus type %d.\n",bus); 
1150                         irq = 0;
1151                         break;
1152                 }
1153         }
1154
1155         /*
1156          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1157          */
1158         if ((pin >= 16) && (pin <= 23)) {
1159                 if (pirq_entries[pin-16] != -1) {
1160                         if (!pirq_entries[pin-16]) {
1161                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1162                                                 "disabling PIRQ%d\n", pin-16);
1163                         } else {
1164                                 irq = pirq_entries[pin-16];
1165                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1166                                                 "using PIRQ%d -> IRQ %d\n",
1167                                                 pin-16, irq);
1168                         }
1169                 }
1170         }
1171         return irq;
1172 }
1173
1174 static inline int IO_APIC_irq_trigger(int irq)
1175 {
1176         int apic, idx, pin;
1177
1178         for (apic = 0; apic < nr_ioapics; apic++) {
1179                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1180                         idx = find_irq_entry(apic,pin,mp_INT);
1181                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1182                                 return irq_trigger(idx);
1183                 }
1184         }
1185         /*
1186          * nonexistent IRQs are edge default
1187          */
1188         return 0;
1189 }
1190
1191 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1192 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1193
1194 static int __assign_irq_vector(int irq)
1195 {
1196         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1197         int vector, offset;
1198
1199         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1200
1201         if (irq_vector[irq] > 0)
1202                 return irq_vector[irq];
1203
1204         vector = current_vector;
1205         offset = current_offset;
1206 next:
1207         vector += 8;
1208         if (vector >= FIRST_SYSTEM_VECTOR) {
1209                 offset = (offset + 1) % 8;
1210                 vector = FIRST_DEVICE_VECTOR + offset;
1211         }
1212         if (vector == current_vector)
1213                 return -ENOSPC;
1214         if (test_and_set_bit(vector, used_vectors))
1215                 goto next;
1216
1217         current_vector = vector;
1218         current_offset = offset;
1219         irq_vector[irq] = vector;
1220
1221         return vector;
1222 }
1223
1224 static int assign_irq_vector(int irq)
1225 {
1226         unsigned long flags;
1227         int vector;
1228
1229         spin_lock_irqsave(&vector_lock, flags);
1230         vector = __assign_irq_vector(irq);
1231         spin_unlock_irqrestore(&vector_lock, flags);
1232
1233         return vector;
1234 }
1235 static struct irq_chip ioapic_chip;
1236
1237 #define IOAPIC_AUTO     -1
1238 #define IOAPIC_EDGE     0
1239 #define IOAPIC_LEVEL    1
1240
1241 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1242 {
1243         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1244             trigger == IOAPIC_LEVEL) {
1245                 irq_desc[irq].status |= IRQ_LEVEL;
1246                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1247                                          handle_fasteoi_irq, "fasteoi");
1248         } else {
1249                 irq_desc[irq].status &= ~IRQ_LEVEL;
1250                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1251                                          handle_edge_irq, "edge");
1252         }
1253         set_intr_gate(vector, interrupt[irq]);
1254 }
1255
1256 static void __init setup_IO_APIC_irqs(void)
1257 {
1258         struct IO_APIC_route_entry entry;
1259         int apic, pin, idx, irq, first_notcon = 1, vector;
1260         unsigned long flags;
1261
1262         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1263
1264         for (apic = 0; apic < nr_ioapics; apic++) {
1265         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1266
1267                 /*
1268                  * add it to the IO-APIC irq-routing table:
1269                  */
1270                 memset(&entry,0,sizeof(entry));
1271
1272                 entry.delivery_mode = INT_DELIVERY_MODE;
1273                 entry.dest_mode = INT_DEST_MODE;
1274                 entry.mask = 0;                         /* enable IRQ */
1275                 entry.dest.logical.logical_dest = 
1276                                         cpu_mask_to_apicid(TARGET_CPUS);
1277
1278                 idx = find_irq_entry(apic,pin,mp_INT);
1279                 if (idx == -1) {
1280                         if (first_notcon) {
1281                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1282                                                 " IO-APIC (apicid-pin) %d-%d",
1283                                                 mp_ioapics[apic].mpc_apicid,
1284                                                 pin);
1285                                 first_notcon = 0;
1286                         } else
1287                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1288                                         mp_ioapics[apic].mpc_apicid, pin);
1289                         continue;
1290                 }
1291
1292                 if (!first_notcon) {
1293                         apic_printk(APIC_VERBOSE, " not connected.\n");
1294                         first_notcon = 1;
1295                 }
1296
1297                 entry.trigger = irq_trigger(idx);
1298                 entry.polarity = irq_polarity(idx);
1299
1300                 if (irq_trigger(idx)) {
1301                         entry.trigger = 1;
1302                         entry.mask = 1;
1303                 }
1304
1305                 irq = pin_2_irq(idx, apic, pin);
1306                 /*
1307                  * skip adding the timer int on secondary nodes, which causes
1308                  * a small but painful rift in the time-space continuum
1309                  */
1310                 if (multi_timer_check(apic, irq))
1311                         continue;
1312                 else
1313                         add_pin_to_irq(irq, apic, pin);
1314
1315                 if (!apic && !IO_APIC_IRQ(irq))
1316                         continue;
1317
1318                 if (IO_APIC_IRQ(irq)) {
1319                         vector = assign_irq_vector(irq);
1320                         entry.vector = vector;
1321                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1322                 
1323                         if (!apic && (irq < 16))
1324                                 disable_8259A_irq(irq);
1325                 }
1326                 spin_lock_irqsave(&ioapic_lock, flags);
1327                 __ioapic_write_entry(apic, pin, entry);
1328                 spin_unlock_irqrestore(&ioapic_lock, flags);
1329         }
1330         }
1331
1332         if (!first_notcon)
1333                 apic_printk(APIC_VERBOSE, " not connected.\n");
1334 }
1335
1336 /*
1337  * Set up the 8259A-master output pin:
1338  */
1339 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1340 {
1341         struct IO_APIC_route_entry entry;
1342
1343         memset(&entry,0,sizeof(entry));
1344
1345         disable_8259A_irq(0);
1346
1347         /* mask LVT0 */
1348         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1349
1350         /*
1351          * We use logical delivery to get the timer IRQ
1352          * to the first CPU.
1353          */
1354         entry.dest_mode = INT_DEST_MODE;
1355         entry.mask = 0;                                 /* unmask IRQ now */
1356         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1357         entry.delivery_mode = INT_DELIVERY_MODE;
1358         entry.polarity = 0;
1359         entry.trigger = 0;
1360         entry.vector = vector;
1361
1362         /*
1363          * The timer IRQ doesn't have to know that behind the
1364          * scene we have a 8259A-master in AEOI mode ...
1365          */
1366         irq_desc[0].chip = &ioapic_chip;
1367         set_irq_handler(0, handle_edge_irq);
1368
1369         /*
1370          * Add it to the IO-APIC irq-routing table:
1371          */
1372         ioapic_write_entry(apic, pin, entry);
1373
1374         enable_8259A_irq(0);
1375 }
1376
1377 void __init print_IO_APIC(void)
1378 {
1379         int apic, i;
1380         union IO_APIC_reg_00 reg_00;
1381         union IO_APIC_reg_01 reg_01;
1382         union IO_APIC_reg_02 reg_02;
1383         union IO_APIC_reg_03 reg_03;
1384         unsigned long flags;
1385
1386         if (apic_verbosity == APIC_QUIET)
1387                 return;
1388
1389         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1390         for (i = 0; i < nr_ioapics; i++)
1391                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1392                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1393
1394         /*
1395          * We are a bit conservative about what we expect.  We have to
1396          * know about every hardware change ASAP.
1397          */
1398         printk(KERN_INFO "testing the IO APIC.......................\n");
1399
1400         for (apic = 0; apic < nr_ioapics; apic++) {
1401
1402         spin_lock_irqsave(&ioapic_lock, flags);
1403         reg_00.raw = io_apic_read(apic, 0);
1404         reg_01.raw = io_apic_read(apic, 1);
1405         if (reg_01.bits.version >= 0x10)
1406                 reg_02.raw = io_apic_read(apic, 2);
1407         if (reg_01.bits.version >= 0x20)
1408                 reg_03.raw = io_apic_read(apic, 3);
1409         spin_unlock_irqrestore(&ioapic_lock, flags);
1410
1411         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1412         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1413         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1414         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1415         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1416
1417         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1418         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1419
1420         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1421         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1422
1423         /*
1424          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1425          * but the value of reg_02 is read as the previous read register
1426          * value, so ignore it if reg_02 == reg_01.
1427          */
1428         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1429                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1430                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1431         }
1432
1433         /*
1434          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1435          * or reg_03, but the value of reg_0[23] is read as the previous read
1436          * register value, so ignore it if reg_03 == reg_0[12].
1437          */
1438         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1439             reg_03.raw != reg_01.raw) {
1440                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1441                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1442         }
1443
1444         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1445
1446         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1447                           " Stat Dest Deli Vect:   \n");
1448
1449         for (i = 0; i <= reg_01.bits.entries; i++) {
1450                 struct IO_APIC_route_entry entry;
1451
1452                 entry = ioapic_read_entry(apic, i);
1453
1454                 printk(KERN_DEBUG " %02x %03X %02X  ",
1455                         i,
1456                         entry.dest.logical.logical_dest,
1457                         entry.dest.physical.physical_dest
1458                 );
1459
1460                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1461                         entry.mask,
1462                         entry.trigger,
1463                         entry.irr,
1464                         entry.polarity,
1465                         entry.delivery_status,
1466                         entry.dest_mode,
1467                         entry.delivery_mode,
1468                         entry.vector
1469                 );
1470         }
1471         }
1472         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1473         for (i = 0; i < NR_IRQS; i++) {
1474                 struct irq_pin_list *entry = irq_2_pin + i;
1475                 if (entry->pin < 0)
1476                         continue;
1477                 printk(KERN_DEBUG "IRQ%d ", i);
1478                 for (;;) {
1479                         printk("-> %d:%d", entry->apic, entry->pin);
1480                         if (!entry->next)
1481                                 break;
1482                         entry = irq_2_pin + entry->next;
1483                 }
1484                 printk("\n");
1485         }
1486
1487         printk(KERN_INFO ".................................... done.\n");
1488
1489         return;
1490 }
1491
1492 #if 0
1493
1494 static void print_APIC_bitfield (int base)
1495 {
1496         unsigned int v;
1497         int i, j;
1498
1499         if (apic_verbosity == APIC_QUIET)
1500                 return;
1501
1502         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1503         for (i = 0; i < 8; i++) {
1504                 v = apic_read(base + i*0x10);
1505                 for (j = 0; j < 32; j++) {
1506                         if (v & (1<<j))
1507                                 printk("1");
1508                         else
1509                                 printk("0");
1510                 }
1511                 printk("\n");
1512         }
1513 }
1514
1515 void /*__init*/ print_local_APIC(void * dummy)
1516 {
1517         unsigned int v, ver, maxlvt;
1518
1519         if (apic_verbosity == APIC_QUIET)
1520                 return;
1521
1522         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1523                 smp_processor_id(), hard_smp_processor_id());
1524         v = apic_read(APIC_ID);
1525         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1526         v = apic_read(APIC_LVR);
1527         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1528         ver = GET_APIC_VERSION(v);
1529         maxlvt = lapic_get_maxlvt();
1530
1531         v = apic_read(APIC_TASKPRI);
1532         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1533
1534         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1535                 v = apic_read(APIC_ARBPRI);
1536                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1537                         v & APIC_ARBPRI_MASK);
1538                 v = apic_read(APIC_PROCPRI);
1539                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1540         }
1541
1542         v = apic_read(APIC_EOI);
1543         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1544         v = apic_read(APIC_RRR);
1545         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1546         v = apic_read(APIC_LDR);
1547         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1548         v = apic_read(APIC_DFR);
1549         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1550         v = apic_read(APIC_SPIV);
1551         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1552
1553         printk(KERN_DEBUG "... APIC ISR field:\n");
1554         print_APIC_bitfield(APIC_ISR);
1555         printk(KERN_DEBUG "... APIC TMR field:\n");
1556         print_APIC_bitfield(APIC_TMR);
1557         printk(KERN_DEBUG "... APIC IRR field:\n");
1558         print_APIC_bitfield(APIC_IRR);
1559
1560         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1561                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1562                         apic_write(APIC_ESR, 0);
1563                 v = apic_read(APIC_ESR);
1564                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1565         }
1566
1567         v = apic_read(APIC_ICR);
1568         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1569         v = apic_read(APIC_ICR2);
1570         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1571
1572         v = apic_read(APIC_LVTT);
1573         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1574
1575         if (maxlvt > 3) {                       /* PC is LVT#4. */
1576                 v = apic_read(APIC_LVTPC);
1577                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1578         }
1579         v = apic_read(APIC_LVT0);
1580         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1581         v = apic_read(APIC_LVT1);
1582         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1583
1584         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1585                 v = apic_read(APIC_LVTERR);
1586                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1587         }
1588
1589         v = apic_read(APIC_TMICT);
1590         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1591         v = apic_read(APIC_TMCCT);
1592         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1593         v = apic_read(APIC_TDCR);
1594         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1595         printk("\n");
1596 }
1597
1598 void print_all_local_APICs (void)
1599 {
1600         on_each_cpu(print_local_APIC, NULL, 1, 1);
1601 }
1602
1603 void /*__init*/ print_PIC(void)
1604 {
1605         unsigned int v;
1606         unsigned long flags;
1607
1608         if (apic_verbosity == APIC_QUIET)
1609                 return;
1610
1611         printk(KERN_DEBUG "\nprinting PIC contents\n");
1612
1613         spin_lock_irqsave(&i8259A_lock, flags);
1614
1615         v = inb(0xa1) << 8 | inb(0x21);
1616         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1617
1618         v = inb(0xa0) << 8 | inb(0x20);
1619         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1620
1621         outb(0x0b,0xa0);
1622         outb(0x0b,0x20);
1623         v = inb(0xa0) << 8 | inb(0x20);
1624         outb(0x0a,0xa0);
1625         outb(0x0a,0x20);
1626
1627         spin_unlock_irqrestore(&i8259A_lock, flags);
1628
1629         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1630
1631         v = inb(0x4d1) << 8 | inb(0x4d0);
1632         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1633 }
1634
1635 #endif  /*  0  */
1636
1637 static void __init enable_IO_APIC(void)
1638 {
1639         union IO_APIC_reg_01 reg_01;
1640         int i8259_apic, i8259_pin;
1641         int i, apic;
1642         unsigned long flags;
1643
1644         for (i = 0; i < PIN_MAP_SIZE; i++) {
1645                 irq_2_pin[i].pin = -1;
1646                 irq_2_pin[i].next = 0;
1647         }
1648         if (!pirqs_enabled)
1649                 for (i = 0; i < MAX_PIRQS; i++)
1650                         pirq_entries[i] = -1;
1651
1652         /*
1653          * The number of IO-APIC IRQ registers (== #pins):
1654          */
1655         for (apic = 0; apic < nr_ioapics; apic++) {
1656                 spin_lock_irqsave(&ioapic_lock, flags);
1657                 reg_01.raw = io_apic_read(apic, 1);
1658                 spin_unlock_irqrestore(&ioapic_lock, flags);
1659                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1660         }
1661         for(apic = 0; apic < nr_ioapics; apic++) {
1662                 int pin;
1663                 /* See if any of the pins is in ExtINT mode */
1664                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1665                         struct IO_APIC_route_entry entry;
1666                         entry = ioapic_read_entry(apic, pin);
1667
1668
1669                         /* If the interrupt line is enabled and in ExtInt mode
1670                          * I have found the pin where the i8259 is connected.
1671                          */
1672                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1673                                 ioapic_i8259.apic = apic;
1674                                 ioapic_i8259.pin  = pin;
1675                                 goto found_i8259;
1676                         }
1677                 }
1678         }
1679  found_i8259:
1680         /* Look to see what if the MP table has reported the ExtINT */
1681         /* If we could not find the appropriate pin by looking at the ioapic
1682          * the i8259 probably is not connected the ioapic but give the
1683          * mptable a chance anyway.
1684          */
1685         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1686         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1687         /* Trust the MP table if nothing is setup in the hardware */
1688         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1689                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1690                 ioapic_i8259.pin  = i8259_pin;
1691                 ioapic_i8259.apic = i8259_apic;
1692         }
1693         /* Complain if the MP table and the hardware disagree */
1694         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1695                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1696         {
1697                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1698         }
1699
1700         /*
1701          * Do not trust the IO-APIC being empty at bootup
1702          */
1703         clear_IO_APIC();
1704 }
1705
1706 /*
1707  * Not an __init, needed by the reboot code
1708  */
1709 void disable_IO_APIC(void)
1710 {
1711         /*
1712          * Clear the IO-APIC before rebooting:
1713          */
1714         clear_IO_APIC();
1715
1716         /*
1717          * If the i8259 is routed through an IOAPIC
1718          * Put that IOAPIC in virtual wire mode
1719          * so legacy interrupts can be delivered.
1720          */
1721         if (ioapic_i8259.pin != -1) {
1722                 struct IO_APIC_route_entry entry;
1723
1724                 memset(&entry, 0, sizeof(entry));
1725                 entry.mask            = 0; /* Enabled */
1726                 entry.trigger         = 0; /* Edge */
1727                 entry.irr             = 0;
1728                 entry.polarity        = 0; /* High */
1729                 entry.delivery_status = 0;
1730                 entry.dest_mode       = 0; /* Physical */
1731                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1732                 entry.vector          = 0;
1733                 entry.dest.physical.physical_dest =
1734                                         GET_APIC_ID(apic_read(APIC_ID));
1735
1736                 /*
1737                  * Add it to the IO-APIC irq-routing table:
1738                  */
1739                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1740         }
1741         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1742 }
1743
1744 /*
1745  * function to set the IO-APIC physical IDs based on the
1746  * values stored in the MPC table.
1747  *
1748  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1749  */
1750
1751 #ifndef CONFIG_X86_NUMAQ
1752 static void __init setup_ioapic_ids_from_mpc(void)
1753 {
1754         union IO_APIC_reg_00 reg_00;
1755         physid_mask_t phys_id_present_map;
1756         int apic;
1757         int i;
1758         unsigned char old_id;
1759         unsigned long flags;
1760
1761         /*
1762          * Don't check I/O APIC IDs for xAPIC systems.  They have
1763          * no meaning without the serial APIC bus.
1764          */
1765         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1766                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1767                 return;
1768         /*
1769          * This is broken; anything with a real cpu count has to
1770          * circumvent this idiocy regardless.
1771          */
1772         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1773
1774         /*
1775          * Set the IOAPIC ID to the value stored in the MPC table.
1776          */
1777         for (apic = 0; apic < nr_ioapics; apic++) {
1778
1779                 /* Read the register 0 value */
1780                 spin_lock_irqsave(&ioapic_lock, flags);
1781                 reg_00.raw = io_apic_read(apic, 0);
1782                 spin_unlock_irqrestore(&ioapic_lock, flags);
1783                 
1784                 old_id = mp_ioapics[apic].mpc_apicid;
1785
1786                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1787                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1788                                 apic, mp_ioapics[apic].mpc_apicid);
1789                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1790                                 reg_00.bits.ID);
1791                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1792                 }
1793
1794                 /*
1795                  * Sanity check, is the ID really free? Every APIC in a
1796                  * system must have a unique ID or we get lots of nice
1797                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1798                  */
1799                 if (check_apicid_used(phys_id_present_map,
1800                                         mp_ioapics[apic].mpc_apicid)) {
1801                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1802                                 apic, mp_ioapics[apic].mpc_apicid);
1803                         for (i = 0; i < get_physical_broadcast(); i++)
1804                                 if (!physid_isset(i, phys_id_present_map))
1805                                         break;
1806                         if (i >= get_physical_broadcast())
1807                                 panic("Max APIC ID exceeded!\n");
1808                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1809                                 i);
1810                         physid_set(i, phys_id_present_map);
1811                         mp_ioapics[apic].mpc_apicid = i;
1812                 } else {
1813                         physid_mask_t tmp;
1814                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1815                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1816                                         "phys_id_present_map\n",
1817                                         mp_ioapics[apic].mpc_apicid);
1818                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1819                 }
1820
1821
1822                 /*
1823                  * We need to adjust the IRQ routing table
1824                  * if the ID changed.
1825                  */
1826                 if (old_id != mp_ioapics[apic].mpc_apicid)
1827                         for (i = 0; i < mp_irq_entries; i++)
1828                                 if (mp_irqs[i].mpc_dstapic == old_id)
1829                                         mp_irqs[i].mpc_dstapic
1830                                                 = mp_ioapics[apic].mpc_apicid;
1831
1832                 /*
1833                  * Read the right value from the MPC table and
1834                  * write it into the ID register.
1835                  */
1836                 apic_printk(APIC_VERBOSE, KERN_INFO
1837                         "...changing IO-APIC physical APIC ID to %d ...",
1838                         mp_ioapics[apic].mpc_apicid);
1839
1840                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1841                 spin_lock_irqsave(&ioapic_lock, flags);
1842                 io_apic_write(apic, 0, reg_00.raw);
1843                 spin_unlock_irqrestore(&ioapic_lock, flags);
1844
1845                 /*
1846                  * Sanity check
1847                  */
1848                 spin_lock_irqsave(&ioapic_lock, flags);
1849                 reg_00.raw = io_apic_read(apic, 0);
1850                 spin_unlock_irqrestore(&ioapic_lock, flags);
1851                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1852                         printk("could not set ID!\n");
1853                 else
1854                         apic_printk(APIC_VERBOSE, " ok.\n");
1855         }
1856 }
1857 #else
1858 static void __init setup_ioapic_ids_from_mpc(void) { }
1859 #endif
1860
1861 int no_timer_check __initdata;
1862
1863 static int __init notimercheck(char *s)
1864 {
1865         no_timer_check = 1;
1866         return 1;
1867 }
1868 __setup("no_timer_check", notimercheck);
1869
1870 /*
1871  * There is a nasty bug in some older SMP boards, their mptable lies
1872  * about the timer IRQ. We do the following to work around the situation:
1873  *
1874  *      - timer IRQ defaults to IO-APIC IRQ
1875  *      - if this function detects that timer IRQs are defunct, then we fall
1876  *        back to ISA timer IRQs
1877  */
1878 static int __init timer_irq_works(void)
1879 {
1880         unsigned long t1 = jiffies;
1881         unsigned long flags;
1882
1883         if (no_timer_check)
1884                 return 1;
1885
1886         local_save_flags(flags);
1887         local_irq_enable();
1888         /* Let ten ticks pass... */
1889         mdelay((10 * 1000) / HZ);
1890         local_irq_restore(flags);
1891
1892         /*
1893          * Expect a few ticks at least, to be sure some possible
1894          * glue logic does not lock up after one or two first
1895          * ticks in a non-ExtINT mode.  Also the local APIC
1896          * might have cached one ExtINT interrupt.  Finally, at
1897          * least one tick may be lost due to delays.
1898          */
1899         if (time_after(jiffies, t1 + 4))
1900                 return 1;
1901
1902         return 0;
1903 }
1904
1905 /*
1906  * In the SMP+IOAPIC case it might happen that there are an unspecified
1907  * number of pending IRQ events unhandled. These cases are very rare,
1908  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1909  * better to do it this way as thus we do not have to be aware of
1910  * 'pending' interrupts in the IRQ path, except at this point.
1911  */
1912 /*
1913  * Edge triggered needs to resend any interrupt
1914  * that was delayed but this is now handled in the device
1915  * independent code.
1916  */
1917
1918 /*
1919  * Startup quirk:
1920  *
1921  * Starting up a edge-triggered IO-APIC interrupt is
1922  * nasty - we need to make sure that we get the edge.
1923  * If it is already asserted for some reason, we need
1924  * return 1 to indicate that is was pending.
1925  *
1926  * This is not complete - we should be able to fake
1927  * an edge even if it isn't on the 8259A...
1928  *
1929  * (We do this for level-triggered IRQs too - it cannot hurt.)
1930  */
1931 static unsigned int startup_ioapic_irq(unsigned int irq)
1932 {
1933         int was_pending = 0;
1934         unsigned long flags;
1935
1936         spin_lock_irqsave(&ioapic_lock, flags);
1937         if (irq < 16) {
1938                 disable_8259A_irq(irq);
1939                 if (i8259A_irq_pending(irq))
1940                         was_pending = 1;
1941         }
1942         __unmask_IO_APIC_irq(irq);
1943         spin_unlock_irqrestore(&ioapic_lock, flags);
1944
1945         return was_pending;
1946 }
1947
1948 static void ack_ioapic_irq(unsigned int irq)
1949 {
1950         move_native_irq(irq);
1951         ack_APIC_irq();
1952 }
1953
1954 static void ack_ioapic_quirk_irq(unsigned int irq)
1955 {
1956         unsigned long v;
1957         int i;
1958
1959         move_native_irq(irq);
1960 /*
1961  * It appears there is an erratum which affects at least version 0x11
1962  * of I/O APIC (that's the 82093AA and cores integrated into various
1963  * chipsets).  Under certain conditions a level-triggered interrupt is
1964  * erroneously delivered as edge-triggered one but the respective IRR
1965  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1966  * message but it will never arrive and further interrupts are blocked
1967  * from the source.  The exact reason is so far unknown, but the
1968  * phenomenon was observed when two consecutive interrupt requests
1969  * from a given source get delivered to the same CPU and the source is
1970  * temporarily disabled in between.
1971  *
1972  * A workaround is to simulate an EOI message manually.  We achieve it
1973  * by setting the trigger mode to edge and then to level when the edge
1974  * trigger mode gets detected in the TMR of a local APIC for a
1975  * level-triggered interrupt.  We mask the source for the time of the
1976  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1977  * The idea is from Manfred Spraul.  --macro
1978  */
1979         i = irq_vector[irq];
1980
1981         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1982
1983         ack_APIC_irq();
1984
1985         if (!(v & (1 << (i & 0x1f)))) {
1986                 atomic_inc(&irq_mis_count);
1987                 spin_lock(&ioapic_lock);
1988                 __mask_and_edge_IO_APIC_irq(irq);
1989                 __unmask_and_level_IO_APIC_irq(irq);
1990                 spin_unlock(&ioapic_lock);
1991         }
1992 }
1993
1994 static int ioapic_retrigger_irq(unsigned int irq)
1995 {
1996         send_IPI_self(irq_vector[irq]);
1997
1998         return 1;
1999 }
2000
2001 static struct irq_chip ioapic_chip __read_mostly = {
2002         .name           = "IO-APIC",
2003         .startup        = startup_ioapic_irq,
2004         .mask           = mask_IO_APIC_irq,
2005         .unmask         = unmask_IO_APIC_irq,
2006         .ack            = ack_ioapic_irq,
2007         .eoi            = ack_ioapic_quirk_irq,
2008 #ifdef CONFIG_SMP
2009         .set_affinity   = set_ioapic_affinity_irq,
2010 #endif
2011         .retrigger      = ioapic_retrigger_irq,
2012 };
2013
2014
2015 static inline void init_IO_APIC_traps(void)
2016 {
2017         int irq;
2018
2019         /*
2020          * NOTE! The local APIC isn't very good at handling
2021          * multiple interrupts at the same interrupt level.
2022          * As the interrupt level is determined by taking the
2023          * vector number and shifting that right by 4, we
2024          * want to spread these out a bit so that they don't
2025          * all fall in the same interrupt level.
2026          *
2027          * Also, we've got to be careful not to trash gate
2028          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2029          */
2030         for (irq = 0; irq < NR_IRQS ; irq++) {
2031                 int tmp = irq;
2032                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2033                         /*
2034                          * Hmm.. We don't have an entry for this,
2035                          * so default to an old-fashioned 8259
2036                          * interrupt if we can..
2037                          */
2038                         if (irq < 16)
2039                                 make_8259A_irq(irq);
2040                         else
2041                                 /* Strange. Oh, well.. */
2042                                 irq_desc[irq].chip = &no_irq_chip;
2043                 }
2044         }
2045 }
2046
2047 /*
2048  * The local APIC irq-chip implementation:
2049  */
2050
2051 static void ack_apic(unsigned int irq)
2052 {
2053         ack_APIC_irq();
2054 }
2055
2056 static void mask_lapic_irq (unsigned int irq)
2057 {
2058         unsigned long v;
2059
2060         v = apic_read(APIC_LVT0);
2061         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2062 }
2063
2064 static void unmask_lapic_irq (unsigned int irq)
2065 {
2066         unsigned long v;
2067
2068         v = apic_read(APIC_LVT0);
2069         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2070 }
2071
2072 static struct irq_chip lapic_chip __read_mostly = {
2073         .name           = "local-APIC-edge",
2074         .mask           = mask_lapic_irq,
2075         .unmask         = unmask_lapic_irq,
2076         .eoi            = ack_apic,
2077 };
2078
2079 static void __init setup_nmi(void)
2080 {
2081         /*
2082          * Dirty trick to enable the NMI watchdog ...
2083          * We put the 8259A master into AEOI mode and
2084          * unmask on all local APICs LVT0 as NMI.
2085          *
2086          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2087          * is from Maciej W. Rozycki - so we do not have to EOI from
2088          * the NMI handler or the timer interrupt.
2089          */ 
2090         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2091
2092         enable_NMI_through_LVT0();
2093
2094         apic_printk(APIC_VERBOSE, " done.\n");
2095 }
2096
2097 /*
2098  * This looks a bit hackish but it's about the only one way of sending
2099  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2100  * not support the ExtINT mode, unfortunately.  We need to send these
2101  * cycles as some i82489DX-based boards have glue logic that keeps the
2102  * 8259A interrupt line asserted until INTA.  --macro
2103  */
2104 static inline void unlock_ExtINT_logic(void)
2105 {
2106         int apic, pin, i;
2107         struct IO_APIC_route_entry entry0, entry1;
2108         unsigned char save_control, save_freq_select;
2109
2110         pin  = find_isa_irq_pin(8, mp_INT);
2111         if (pin == -1) {
2112                 WARN_ON_ONCE(1);
2113                 return;
2114         }
2115         apic = find_isa_irq_apic(8, mp_INT);
2116         if (apic == -1) {
2117                 WARN_ON_ONCE(1);
2118                 return;
2119         }
2120
2121         entry0 = ioapic_read_entry(apic, pin);
2122         clear_IO_APIC_pin(apic, pin);
2123
2124         memset(&entry1, 0, sizeof(entry1));
2125
2126         entry1.dest_mode = 0;                   /* physical delivery */
2127         entry1.mask = 0;                        /* unmask IRQ now */
2128         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2129         entry1.delivery_mode = dest_ExtINT;
2130         entry1.polarity = entry0.polarity;
2131         entry1.trigger = 0;
2132         entry1.vector = 0;
2133
2134         ioapic_write_entry(apic, pin, entry1);
2135
2136         save_control = CMOS_READ(RTC_CONTROL);
2137         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2138         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2139                    RTC_FREQ_SELECT);
2140         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2141
2142         i = 100;
2143         while (i-- > 0) {
2144                 mdelay(10);
2145                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2146                         i -= 10;
2147         }
2148
2149         CMOS_WRITE(save_control, RTC_CONTROL);
2150         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2151         clear_IO_APIC_pin(apic, pin);
2152
2153         ioapic_write_entry(apic, pin, entry0);
2154 }
2155
2156 int timer_uses_ioapic_pin_0;
2157
2158 /*
2159  * This code may look a bit paranoid, but it's supposed to cooperate with
2160  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2161  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2162  * fanatically on his truly buggy board.
2163  */
2164 static inline void __init check_timer(void)
2165 {
2166         int apic1, pin1, apic2, pin2;
2167         int vector;
2168         unsigned long flags;
2169
2170         local_irq_save(flags);
2171
2172         /*
2173          * get/set the timer IRQ vector:
2174          */
2175         disable_8259A_irq(0);
2176         vector = assign_irq_vector(0);
2177         set_intr_gate(vector, interrupt[0]);
2178
2179         /*
2180          * Subtle, code in do_timer_interrupt() expects an AEOI
2181          * mode for the 8259A whenever interrupts are routed
2182          * through I/O APICs.  Also IRQ0 has to be enabled in
2183          * the 8259A which implies the virtual wire has to be
2184          * disabled in the local APIC.
2185          */
2186         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2187         init_8259A(1);
2188         timer_ack = 1;
2189         if (timer_over_8254 > 0)
2190                 enable_8259A_irq(0);
2191
2192         pin1  = find_isa_irq_pin(0, mp_INT);
2193         apic1 = find_isa_irq_apic(0, mp_INT);
2194         pin2  = ioapic_i8259.pin;
2195         apic2 = ioapic_i8259.apic;
2196
2197         if (pin1 == 0)
2198                 timer_uses_ioapic_pin_0 = 1;
2199
2200         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2201                 vector, apic1, pin1, apic2, pin2);
2202
2203         if (pin1 != -1) {
2204                 /*
2205                  * Ok, does IRQ0 through the IOAPIC work?
2206                  */
2207                 unmask_IO_APIC_irq(0);
2208                 if (timer_irq_works()) {
2209                         if (nmi_watchdog == NMI_IO_APIC) {
2210                                 disable_8259A_irq(0);
2211                                 setup_nmi();
2212                                 enable_8259A_irq(0);
2213                         }
2214                         if (disable_timer_pin_1 > 0)
2215                                 clear_IO_APIC_pin(0, pin1);
2216                         goto out;
2217                 }
2218                 clear_IO_APIC_pin(apic1, pin1);
2219                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2220                                 "IO-APIC\n");
2221         }
2222
2223         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2224         if (pin2 != -1) {
2225                 printk("\n..... (found pin %d) ...", pin2);
2226                 /*
2227                  * legacy devices should be connected to IO APIC #0
2228                  */
2229                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2230                 if (timer_irq_works()) {
2231                         printk("works.\n");
2232                         if (pin1 != -1)
2233                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2234                         else
2235                                 add_pin_to_irq(0, apic2, pin2);
2236                         if (nmi_watchdog == NMI_IO_APIC) {
2237                                 setup_nmi();
2238                         }
2239                         goto out;
2240                 }
2241                 /*
2242                  * Cleanup, just in case ...
2243                  */
2244                 clear_IO_APIC_pin(apic2, pin2);
2245         }
2246         printk(" failed.\n");
2247
2248         if (nmi_watchdog == NMI_IO_APIC) {
2249                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2250                 nmi_watchdog = 0;
2251         }
2252
2253         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2254
2255         disable_8259A_irq(0);
2256         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2257                                       "fasteoi");
2258         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2259         enable_8259A_irq(0);
2260
2261         if (timer_irq_works()) {
2262                 printk(" works.\n");
2263                 goto out;
2264         }
2265         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2266         printk(" failed.\n");
2267
2268         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2269
2270         timer_ack = 0;
2271         init_8259A(0);
2272         make_8259A_irq(0);
2273         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2274
2275         unlock_ExtINT_logic();
2276
2277         if (timer_irq_works()) {
2278                 printk(" works.\n");
2279                 goto out;
2280         }
2281         printk(" failed :(.\n");
2282         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2283                 "report.  Then try booting with the 'noapic' option");
2284 out:
2285         local_irq_restore(flags);
2286 }
2287
2288 /*
2289  *
2290  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2291  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2292  *   Linux doesn't really care, as it's not actually used
2293  *   for any interrupt handling anyway.
2294  */
2295 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2296
2297 void __init setup_IO_APIC(void)
2298 {
2299         int i;
2300
2301         /* Reserve all the system vectors. */
2302         for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2303                 set_bit(i, used_vectors);
2304
2305         enable_IO_APIC();
2306
2307         if (acpi_ioapic)
2308                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2309         else
2310                 io_apic_irqs = ~PIC_IRQS;
2311
2312         printk("ENABLING IO-APIC IRQs\n");
2313
2314         /*
2315          * Set up IO-APIC IRQ routing.
2316          */
2317         if (!acpi_ioapic)
2318                 setup_ioapic_ids_from_mpc();
2319         sync_Arb_IDs();
2320         setup_IO_APIC_irqs();
2321         init_IO_APIC_traps();
2322         check_timer();
2323         if (!acpi_ioapic)
2324                 print_IO_APIC();
2325 }
2326
2327 static int __init setup_disable_8254_timer(char *s)
2328 {
2329         timer_over_8254 = -1;
2330         return 1;
2331 }
2332 static int __init setup_enable_8254_timer(char *s)
2333 {
2334         timer_over_8254 = 2;
2335         return 1;
2336 }
2337
2338 __setup("disable_8254_timer", setup_disable_8254_timer);
2339 __setup("enable_8254_timer", setup_enable_8254_timer);
2340
2341 /*
2342  *      Called after all the initialization is done. If we didnt find any
2343  *      APIC bugs then we can allow the modify fast path
2344  */
2345  
2346 static int __init io_apic_bug_finalize(void)
2347 {
2348         if(sis_apic_bug == -1)
2349                 sis_apic_bug = 0;
2350         return 0;
2351 }
2352
2353 late_initcall(io_apic_bug_finalize);
2354
2355 struct sysfs_ioapic_data {
2356         struct sys_device dev;
2357         struct IO_APIC_route_entry entry[0];
2358 };
2359 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2360
2361 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2362 {
2363         struct IO_APIC_route_entry *entry;
2364         struct sysfs_ioapic_data *data;
2365         int i;
2366         
2367         data = container_of(dev, struct sysfs_ioapic_data, dev);
2368         entry = data->entry;
2369         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2370                 entry[i] = ioapic_read_entry(dev->id, i);
2371
2372         return 0;
2373 }
2374
2375 static int ioapic_resume(struct sys_device *dev)
2376 {
2377         struct IO_APIC_route_entry *entry;
2378         struct sysfs_ioapic_data *data;
2379         unsigned long flags;
2380         union IO_APIC_reg_00 reg_00;
2381         int i;
2382         
2383         data = container_of(dev, struct sysfs_ioapic_data, dev);
2384         entry = data->entry;
2385
2386         spin_lock_irqsave(&ioapic_lock, flags);
2387         reg_00.raw = io_apic_read(dev->id, 0);
2388         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2389                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2390                 io_apic_write(dev->id, 0, reg_00.raw);
2391         }
2392         spin_unlock_irqrestore(&ioapic_lock, flags);
2393         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2394                 ioapic_write_entry(dev->id, i, entry[i]);
2395
2396         return 0;
2397 }
2398
2399 static struct sysdev_class ioapic_sysdev_class = {
2400         .name = "ioapic",
2401         .suspend = ioapic_suspend,
2402         .resume = ioapic_resume,
2403 };
2404
2405 static int __init ioapic_init_sysfs(void)
2406 {
2407         struct sys_device * dev;
2408         int i, size, error = 0;
2409
2410         error = sysdev_class_register(&ioapic_sysdev_class);
2411         if (error)
2412                 return error;
2413
2414         for (i = 0; i < nr_ioapics; i++ ) {
2415                 size = sizeof(struct sys_device) + nr_ioapic_registers[i] 
2416                         * sizeof(struct IO_APIC_route_entry);
2417                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2418                 if (!mp_ioapic_data[i]) {
2419                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2420                         continue;
2421                 }
2422                 memset(mp_ioapic_data[i], 0, size);
2423                 dev = &mp_ioapic_data[i]->dev;
2424                 dev->id = i; 
2425                 dev->cls = &ioapic_sysdev_class;
2426                 error = sysdev_register(dev);
2427                 if (error) {
2428                         kfree(mp_ioapic_data[i]);
2429                         mp_ioapic_data[i] = NULL;
2430                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2431                         continue;
2432                 }
2433         }
2434
2435         return 0;
2436 }
2437
2438 device_initcall(ioapic_init_sysfs);
2439
2440 /*
2441  * Dynamic irq allocate and deallocation
2442  */
2443 int create_irq(void)
2444 {
2445         /* Allocate an unused irq */
2446         int irq, new, vector = 0;
2447         unsigned long flags;
2448
2449         irq = -ENOSPC;
2450         spin_lock_irqsave(&vector_lock, flags);
2451         for (new = (NR_IRQS - 1); new >= 0; new--) {
2452                 if (platform_legacy_irq(new))
2453                         continue;
2454                 if (irq_vector[new] != 0)
2455                         continue;
2456                 vector = __assign_irq_vector(new);
2457                 if (likely(vector > 0))
2458                         irq = new;
2459                 break;
2460         }
2461         spin_unlock_irqrestore(&vector_lock, flags);
2462
2463         if (irq >= 0) {
2464                 set_intr_gate(vector, interrupt[irq]);
2465                 dynamic_irq_init(irq);
2466         }
2467         return irq;
2468 }
2469
2470 void destroy_irq(unsigned int irq)
2471 {
2472         unsigned long flags;
2473
2474         dynamic_irq_cleanup(irq);
2475
2476         spin_lock_irqsave(&vector_lock, flags);
2477         irq_vector[irq] = 0;
2478         spin_unlock_irqrestore(&vector_lock, flags);
2479 }
2480
2481 /*
2482  * MSI message composition
2483  */
2484 #ifdef CONFIG_PCI_MSI
2485 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2486 {
2487         int vector;
2488         unsigned dest;
2489
2490         vector = assign_irq_vector(irq);
2491         if (vector >= 0) {
2492                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2493
2494                 msg->address_hi = MSI_ADDR_BASE_HI;
2495                 msg->address_lo =
2496                         MSI_ADDR_BASE_LO |
2497                         ((INT_DEST_MODE == 0) ?
2498                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2499                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2500                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2501                                 MSI_ADDR_REDIRECTION_CPU:
2502                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2503                         MSI_ADDR_DEST_ID(dest);
2504
2505                 msg->data =
2506                         MSI_DATA_TRIGGER_EDGE |
2507                         MSI_DATA_LEVEL_ASSERT |
2508                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2509                                 MSI_DATA_DELIVERY_FIXED:
2510                                 MSI_DATA_DELIVERY_LOWPRI) |
2511                         MSI_DATA_VECTOR(vector);
2512         }
2513         return vector;
2514 }
2515
2516 #ifdef CONFIG_SMP
2517 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2518 {
2519         struct msi_msg msg;
2520         unsigned int dest;
2521         cpumask_t tmp;
2522         int vector;
2523
2524         cpus_and(tmp, mask, cpu_online_map);
2525         if (cpus_empty(tmp))
2526                 tmp = TARGET_CPUS;
2527
2528         vector = assign_irq_vector(irq);
2529         if (vector < 0)
2530                 return;
2531
2532         dest = cpu_mask_to_apicid(mask);
2533
2534         read_msi_msg(irq, &msg);
2535
2536         msg.data &= ~MSI_DATA_VECTOR_MASK;
2537         msg.data |= MSI_DATA_VECTOR(vector);
2538         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2539         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2540
2541         write_msi_msg(irq, &msg);
2542         irq_desc[irq].affinity = mask;
2543 }
2544 #endif /* CONFIG_SMP */
2545
2546 /*
2547  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2548  * which implement the MSI or MSI-X Capability Structure.
2549  */
2550 static struct irq_chip msi_chip = {
2551         .name           = "PCI-MSI",
2552         .unmask         = unmask_msi_irq,
2553         .mask           = mask_msi_irq,
2554         .ack            = ack_ioapic_irq,
2555 #ifdef CONFIG_SMP
2556         .set_affinity   = set_msi_irq_affinity,
2557 #endif
2558         .retrigger      = ioapic_retrigger_irq,
2559 };
2560
2561 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2562 {
2563         struct msi_msg msg;
2564         int irq, ret;
2565         irq = create_irq();
2566         if (irq < 0)
2567                 return irq;
2568
2569         ret = msi_compose_msg(dev, irq, &msg);
2570         if (ret < 0) {
2571                 destroy_irq(irq);
2572                 return ret;
2573         }
2574
2575         set_irq_msi(irq, desc);
2576         write_msi_msg(irq, &msg);
2577
2578         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2579                                       "edge");
2580
2581         return 0;
2582 }
2583
2584 void arch_teardown_msi_irq(unsigned int irq)
2585 {
2586         destroy_irq(irq);
2587 }
2588
2589 #endif /* CONFIG_PCI_MSI */
2590
2591 /*
2592  * Hypertransport interrupt support
2593  */
2594 #ifdef CONFIG_HT_IRQ
2595
2596 #ifdef CONFIG_SMP
2597
2598 static void target_ht_irq(unsigned int irq, unsigned int dest)
2599 {
2600         struct ht_irq_msg msg;
2601         fetch_ht_irq_msg(irq, &msg);
2602
2603         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2604         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2605
2606         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2607         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2608
2609         write_ht_irq_msg(irq, &msg);
2610 }
2611
2612 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2613 {
2614         unsigned int dest;
2615         cpumask_t tmp;
2616
2617         cpus_and(tmp, mask, cpu_online_map);
2618         if (cpus_empty(tmp))
2619                 tmp = TARGET_CPUS;
2620
2621         cpus_and(mask, tmp, CPU_MASK_ALL);
2622
2623         dest = cpu_mask_to_apicid(mask);
2624
2625         target_ht_irq(irq, dest);
2626         irq_desc[irq].affinity = mask;
2627 }
2628 #endif
2629
2630 static struct irq_chip ht_irq_chip = {
2631         .name           = "PCI-HT",
2632         .mask           = mask_ht_irq,
2633         .unmask         = unmask_ht_irq,
2634         .ack            = ack_ioapic_irq,
2635 #ifdef CONFIG_SMP
2636         .set_affinity   = set_ht_irq_affinity,
2637 #endif
2638         .retrigger      = ioapic_retrigger_irq,
2639 };
2640
2641 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2642 {
2643         int vector;
2644
2645         vector = assign_irq_vector(irq);
2646         if (vector >= 0) {
2647                 struct ht_irq_msg msg;
2648                 unsigned dest;
2649                 cpumask_t tmp;
2650
2651                 cpus_clear(tmp);
2652                 cpu_set(vector >> 8, tmp);
2653                 dest = cpu_mask_to_apicid(tmp);
2654
2655                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2656
2657                 msg.address_lo =
2658                         HT_IRQ_LOW_BASE |
2659                         HT_IRQ_LOW_DEST_ID(dest) |
2660                         HT_IRQ_LOW_VECTOR(vector) |
2661                         ((INT_DEST_MODE == 0) ?
2662                                 HT_IRQ_LOW_DM_PHYSICAL :
2663                                 HT_IRQ_LOW_DM_LOGICAL) |
2664                         HT_IRQ_LOW_RQEOI_EDGE |
2665                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2666                                 HT_IRQ_LOW_MT_FIXED :
2667                                 HT_IRQ_LOW_MT_ARBITRATED) |
2668                         HT_IRQ_LOW_IRQ_MASKED;
2669
2670                 write_ht_irq_msg(irq, &msg);
2671
2672                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2673                                               handle_edge_irq, "edge");
2674         }
2675         return vector;
2676 }
2677 #endif /* CONFIG_HT_IRQ */
2678
2679 /* --------------------------------------------------------------------------
2680                           ACPI-based IOAPIC Configuration
2681    -------------------------------------------------------------------------- */
2682
2683 #ifdef CONFIG_ACPI
2684
2685 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2686 {
2687         union IO_APIC_reg_00 reg_00;
2688         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2689         physid_mask_t tmp;
2690         unsigned long flags;
2691         int i = 0;
2692
2693         /*
2694          * The P4 platform supports up to 256 APIC IDs on two separate APIC 
2695          * buses (one for LAPICs, one for IOAPICs), where predecessors only 
2696          * supports up to 16 on one shared APIC bus.
2697          * 
2698          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2699          *      advantage of new APIC bus architecture.
2700          */
2701
2702         if (physids_empty(apic_id_map))
2703                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2704
2705         spin_lock_irqsave(&ioapic_lock, flags);
2706         reg_00.raw = io_apic_read(ioapic, 0);
2707         spin_unlock_irqrestore(&ioapic_lock, flags);
2708
2709         if (apic_id >= get_physical_broadcast()) {
2710                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2711                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2712                 apic_id = reg_00.bits.ID;
2713         }
2714
2715         /*
2716          * Every APIC in a system must have a unique ID or we get lots of nice 
2717          * 'stuck on smp_invalidate_needed IPI wait' messages.
2718          */
2719         if (check_apicid_used(apic_id_map, apic_id)) {
2720
2721                 for (i = 0; i < get_physical_broadcast(); i++) {
2722                         if (!check_apicid_used(apic_id_map, i))
2723                                 break;
2724                 }
2725
2726                 if (i == get_physical_broadcast())
2727                         panic("Max apic_id exceeded!\n");
2728
2729                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2730                         "trying %d\n", ioapic, apic_id, i);
2731
2732                 apic_id = i;
2733         } 
2734
2735         tmp = apicid_to_cpu_present(apic_id);
2736         physids_or(apic_id_map, apic_id_map, tmp);
2737
2738         if (reg_00.bits.ID != apic_id) {
2739                 reg_00.bits.ID = apic_id;
2740
2741                 spin_lock_irqsave(&ioapic_lock, flags);
2742                 io_apic_write(ioapic, 0, reg_00.raw);
2743                 reg_00.raw = io_apic_read(ioapic, 0);
2744                 spin_unlock_irqrestore(&ioapic_lock, flags);
2745
2746                 /* Sanity check */
2747                 if (reg_00.bits.ID != apic_id) {
2748                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2749                         return -1;
2750                 }
2751         }
2752
2753         apic_printk(APIC_VERBOSE, KERN_INFO
2754                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2755
2756         return apic_id;
2757 }
2758
2759
2760 int __init io_apic_get_version (int ioapic)
2761 {
2762         union IO_APIC_reg_01    reg_01;
2763         unsigned long flags;
2764
2765         spin_lock_irqsave(&ioapic_lock, flags);
2766         reg_01.raw = io_apic_read(ioapic, 1);
2767         spin_unlock_irqrestore(&ioapic_lock, flags);
2768
2769         return reg_01.bits.version;
2770 }
2771
2772
2773 int __init io_apic_get_redir_entries (int ioapic)
2774 {
2775         union IO_APIC_reg_01    reg_01;
2776         unsigned long flags;
2777
2778         spin_lock_irqsave(&ioapic_lock, flags);
2779         reg_01.raw = io_apic_read(ioapic, 1);
2780         spin_unlock_irqrestore(&ioapic_lock, flags);
2781
2782         return reg_01.bits.entries;
2783 }
2784
2785
2786 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2787 {
2788         struct IO_APIC_route_entry entry;
2789         unsigned long flags;
2790
2791         if (!IO_APIC_IRQ(irq)) {
2792                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2793                         ioapic);
2794                 return -EINVAL;
2795         }
2796
2797         /*
2798          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2799          * Note that we mask (disable) IRQs now -- these get enabled when the
2800          * corresponding device driver registers for this IRQ.
2801          */
2802
2803         memset(&entry,0,sizeof(entry));
2804
2805         entry.delivery_mode = INT_DELIVERY_MODE;
2806         entry.dest_mode = INT_DEST_MODE;
2807         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2808         entry.trigger = edge_level;
2809         entry.polarity = active_high_low;
2810         entry.mask  = 1;
2811
2812         /*
2813          * IRQs < 16 are already in the irq_2_pin[] map
2814          */
2815         if (irq >= 16)
2816                 add_pin_to_irq(irq, ioapic, pin);
2817
2818         entry.vector = assign_irq_vector(irq);
2819
2820         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2821                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2822                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2823                 edge_level, active_high_low);
2824
2825         ioapic_register_intr(irq, entry.vector, edge_level);
2826
2827         if (!ioapic && (irq < 16))
2828                 disable_8259A_irq(irq);
2829
2830         spin_lock_irqsave(&ioapic_lock, flags);
2831         __ioapic_write_entry(ioapic, pin, entry);
2832         spin_unlock_irqrestore(&ioapic_lock, flags);
2833
2834         return 0;
2835 }
2836
2837 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2838 {
2839         int i;
2840
2841         if (skip_ioapic_setup)
2842                 return -1;
2843
2844         for (i = 0; i < mp_irq_entries; i++)
2845                 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2846                     mp_irqs[i].mpc_srcbusirq == bus_irq)
2847                         break;
2848         if (i >= mp_irq_entries)
2849                 return -1;
2850
2851         *trigger = irq_trigger(i);
2852         *polarity = irq_polarity(i);
2853         return 0;
2854 }
2855
2856 #endif /* CONFIG_ACPI */
2857
2858 static int __init parse_disable_timer_pin_1(char *arg)
2859 {
2860         disable_timer_pin_1 = 1;
2861         return 0;
2862 }
2863 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2864
2865 static int __init parse_enable_timer_pin_1(char *arg)
2866 {
2867         disable_timer_pin_1 = -1;
2868         return 0;
2869 }
2870 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2871
2872 static int __init parse_noapic(char *arg)
2873 {
2874         /* disable IO-APIC */
2875         disable_ioapic_setup();
2876         return 0;
2877 }
2878 early_param("noapic", parse_noapic);