4ca548632c8dfa61e5a8a95be00a8cb9d1f97fca
[sfrench/cifs-2.6.git] / arch / x86 / kernel / io_apic_32.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h>      /* time_after() */
39
40 #include <asm/io.h>
41 #include <asm/smp.h>
42 #include <asm/desc.h>
43 #include <asm/timer.h>
44 #include <asm/i8259.h>
45 #include <asm/nmi.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
48
49 #include <mach_apic.h>
50 #include <mach_apicdef.h>
51
52 int (*ioapic_renumber_irq)(int ioapic, int irq);
53 atomic_t irq_mis_count;
54
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
57
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
60
61 int timer_over_8254 __initdata = 1;
62
63 /*
64  *      Is the SiS APIC rmw bug present ?
65  *      -1 = don't know, 0 = no, 1 = yes
66  */
67 int sis_apic_bug = -1;
68
69 /*
70  * # of IRQ routing registers
71  */
72 int nr_ioapic_registers[MAX_IO_APICS];
73
74 static int disable_timer_pin_1 __initdata;
75
76 /*
77  * Rough estimation of how many shared IRQs there are, can
78  * be changed anytime.
79  */
80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
82
83 /*
84  * This is performance-critical, we want to do it O(1)
85  *
86  * the indexing order of this array favors 1:1 mappings
87  * between pins and IRQs.
88  */
89
90 static struct irq_pin_list {
91         int apic, pin, next;
92 } irq_2_pin[PIN_MAP_SIZE];
93
94 struct io_apic {
95         unsigned int index;
96         unsigned int unused[3];
97         unsigned int data;
98 };
99
100 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
101 {
102         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
103                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
104 }
105
106 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
107 {
108         struct io_apic __iomem *io_apic = io_apic_base(apic);
109         writel(reg, &io_apic->index);
110         return readl(&io_apic->data);
111 }
112
113 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
114 {
115         struct io_apic __iomem *io_apic = io_apic_base(apic);
116         writel(reg, &io_apic->index);
117         writel(value, &io_apic->data);
118 }
119
120 /*
121  * Re-write a value: to be used for read-modify-write
122  * cycles where the read already set up the index register.
123  *
124  * Older SiS APIC requires we rewrite the index register
125  */
126 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
127 {
128         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
129         if (sis_apic_bug)
130                 writel(reg, &io_apic->index);
131         writel(value, &io_apic->data);
132 }
133
134 union entry_union {
135         struct { u32 w1, w2; };
136         struct IO_APIC_route_entry entry;
137 };
138
139 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
140 {
141         union entry_union eu;
142         unsigned long flags;
143         spin_lock_irqsave(&ioapic_lock, flags);
144         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
145         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
146         spin_unlock_irqrestore(&ioapic_lock, flags);
147         return eu.entry;
148 }
149
150 /*
151  * When we write a new IO APIC routing entry, we need to write the high
152  * word first! If the mask bit in the low word is clear, we will enable
153  * the interrupt, and we need to make sure the entry is fully populated
154  * before that happens.
155  */
156 static void
157 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
158 {
159         union entry_union eu;
160         eu.entry = e;
161         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
162         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
163 }
164
165 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
166 {
167         unsigned long flags;
168         spin_lock_irqsave(&ioapic_lock, flags);
169         __ioapic_write_entry(apic, pin, e);
170         spin_unlock_irqrestore(&ioapic_lock, flags);
171 }
172
173 /*
174  * When we mask an IO APIC routing entry, we need to write the low
175  * word first, in order to set the mask bit before we change the
176  * high bits!
177  */
178 static void ioapic_mask_entry(int apic, int pin)
179 {
180         unsigned long flags;
181         union entry_union eu = { .entry.mask = 1 };
182
183         spin_lock_irqsave(&ioapic_lock, flags);
184         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
185         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
186         spin_unlock_irqrestore(&ioapic_lock, flags);
187 }
188
189 /*
190  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
191  * shared ISA-space IRQs, so we have to support them. We are super
192  * fast in the common case, and fast for shared ISA-space IRQs.
193  */
194 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
195 {
196         static int first_free_entry = NR_IRQS;
197         struct irq_pin_list *entry = irq_2_pin + irq;
198
199         while (entry->next)
200                 entry = irq_2_pin + entry->next;
201
202         if (entry->pin != -1) {
203                 entry->next = first_free_entry;
204                 entry = irq_2_pin + entry->next;
205                 if (++first_free_entry >= PIN_MAP_SIZE)
206                         panic("io_apic.c: whoops");
207         }
208         entry->apic = apic;
209         entry->pin = pin;
210 }
211
212 /*
213  * Reroute an IRQ to a different pin.
214  */
215 static void __init replace_pin_at_irq(unsigned int irq,
216                                       int oldapic, int oldpin,
217                                       int newapic, int newpin)
218 {
219         struct irq_pin_list *entry = irq_2_pin + irq;
220
221         while (1) {
222                 if (entry->apic == oldapic && entry->pin == oldpin) {
223                         entry->apic = newapic;
224                         entry->pin = newpin;
225                 }
226                 if (!entry->next)
227                         break;
228                 entry = irq_2_pin + entry->next;
229         }
230 }
231
232 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
233 {
234         struct irq_pin_list *entry = irq_2_pin + irq;
235         unsigned int pin, reg;
236
237         for (;;) {
238                 pin = entry->pin;
239                 if (pin == -1)
240                         break;
241                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
242                 reg &= ~disable;
243                 reg |= enable;
244                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
245                 if (!entry->next)
246                         break;
247                 entry = irq_2_pin + entry->next;
248         }
249 }
250
251 /* mask = 1 */
252 static void __mask_IO_APIC_irq (unsigned int irq)
253 {
254         __modify_IO_APIC_irq(irq, 0x00010000, 0);
255 }
256
257 /* mask = 0 */
258 static void __unmask_IO_APIC_irq (unsigned int irq)
259 {
260         __modify_IO_APIC_irq(irq, 0, 0x00010000);
261 }
262
263 /* mask = 1, trigger = 0 */
264 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
265 {
266         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
267 }
268
269 /* mask = 0, trigger = 1 */
270 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
271 {
272         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
273 }
274
275 static void mask_IO_APIC_irq (unsigned int irq)
276 {
277         unsigned long flags;
278
279         spin_lock_irqsave(&ioapic_lock, flags);
280         __mask_IO_APIC_irq(irq);
281         spin_unlock_irqrestore(&ioapic_lock, flags);
282 }
283
284 static void unmask_IO_APIC_irq (unsigned int irq)
285 {
286         unsigned long flags;
287
288         spin_lock_irqsave(&ioapic_lock, flags);
289         __unmask_IO_APIC_irq(irq);
290         spin_unlock_irqrestore(&ioapic_lock, flags);
291 }
292
293 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
294 {
295         struct IO_APIC_route_entry entry;
296         
297         /* Check delivery_mode to be sure we're not clearing an SMI pin */
298         entry = ioapic_read_entry(apic, pin);
299         if (entry.delivery_mode == dest_SMI)
300                 return;
301
302         /*
303          * Disable it in the IO-APIC irq-routing table:
304          */
305         ioapic_mask_entry(apic, pin);
306 }
307
308 static void clear_IO_APIC (void)
309 {
310         int apic, pin;
311
312         for (apic = 0; apic < nr_ioapics; apic++)
313                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
314                         clear_IO_APIC_pin(apic, pin);
315 }
316
317 #ifdef CONFIG_SMP
318 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
319 {
320         unsigned long flags;
321         int pin;
322         struct irq_pin_list *entry = irq_2_pin + irq;
323         unsigned int apicid_value;
324         cpumask_t tmp;
325         
326         cpus_and(tmp, cpumask, cpu_online_map);
327         if (cpus_empty(tmp))
328                 tmp = TARGET_CPUS;
329
330         cpus_and(cpumask, tmp, CPU_MASK_ALL);
331
332         apicid_value = cpu_mask_to_apicid(cpumask);
333         /* Prepare to do the io_apic_write */
334         apicid_value = apicid_value << 24;
335         spin_lock_irqsave(&ioapic_lock, flags);
336         for (;;) {
337                 pin = entry->pin;
338                 if (pin == -1)
339                         break;
340                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
341                 if (!entry->next)
342                         break;
343                 entry = irq_2_pin + entry->next;
344         }
345         irq_desc[irq].affinity = cpumask;
346         spin_unlock_irqrestore(&ioapic_lock, flags);
347 }
348
349 #if defined(CONFIG_IRQBALANCE)
350 # include <asm/processor.h>     /* kernel_thread() */
351 # include <linux/kernel_stat.h> /* kstat */
352 # include <linux/slab.h>                /* kmalloc() */
353 # include <linux/timer.h>
354  
355 #define IRQBALANCE_CHECK_ARCH -999
356 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
357 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
358 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
359 #define BALANCED_IRQ_LESS_DELTA         (HZ)
360
361 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
362 static int physical_balance __read_mostly;
363 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
364
365 static struct irq_cpu_info {
366         unsigned long * last_irq;
367         unsigned long * irq_delta;
368         unsigned long irq;
369 } irq_cpu_data[NR_CPUS];
370
371 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
372 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
373 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
374
375 #define IDLE_ENOUGH(cpu,now) \
376         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
377
378 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
379
380 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
381
382 static cpumask_t balance_irq_affinity[NR_IRQS] = {
383         [0 ... NR_IRQS-1] = CPU_MASK_ALL
384 };
385
386 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
387 {
388         balance_irq_affinity[irq] = mask;
389 }
390
391 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
392                         unsigned long now, int direction)
393 {
394         int search_idle = 1;
395         int cpu = curr_cpu;
396
397         goto inside;
398
399         do {
400                 if (unlikely(cpu == curr_cpu))
401                         search_idle = 0;
402 inside:
403                 if (direction == 1) {
404                         cpu++;
405                         if (cpu >= NR_CPUS)
406                                 cpu = 0;
407                 } else {
408                         cpu--;
409                         if (cpu == -1)
410                                 cpu = NR_CPUS-1;
411                 }
412         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
413                         (search_idle && !IDLE_ENOUGH(cpu,now)));
414
415         return cpu;
416 }
417
418 static inline void balance_irq(int cpu, int irq)
419 {
420         unsigned long now = jiffies;
421         cpumask_t allowed_mask;
422         unsigned int new_cpu;
423                 
424         if (irqbalance_disabled)
425                 return; 
426
427         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
428         new_cpu = move(cpu, allowed_mask, now, 1);
429         if (cpu != new_cpu) {
430                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
431         }
432 }
433
434 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
435 {
436         int i, j;
437
438         for_each_online_cpu(i) {
439                 for (j = 0; j < NR_IRQS; j++) {
440                         if (!irq_desc[j].action)
441                                 continue;
442                         /* Is it a significant load ?  */
443                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
444                                                 useful_load_threshold)
445                                 continue;
446                         balance_irq(i, j);
447                 }
448         }
449         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
450                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
451         return;
452 }
453
454 static void do_irq_balance(void)
455 {
456         int i, j;
457         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
458         unsigned long move_this_load = 0;
459         int max_loaded = 0, min_loaded = 0;
460         int load;
461         unsigned long useful_load_threshold = balanced_irq_interval + 10;
462         int selected_irq;
463         int tmp_loaded, first_attempt = 1;
464         unsigned long tmp_cpu_irq;
465         unsigned long imbalance = 0;
466         cpumask_t allowed_mask, target_cpu_mask, tmp;
467
468         for_each_possible_cpu(i) {
469                 int package_index;
470                 CPU_IRQ(i) = 0;
471                 if (!cpu_online(i))
472                         continue;
473                 package_index = CPU_TO_PACKAGEINDEX(i);
474                 for (j = 0; j < NR_IRQS; j++) {
475                         unsigned long value_now, delta;
476                         /* Is this an active IRQ or balancing disabled ? */
477                         if (!irq_desc[j].action || irq_balancing_disabled(j))
478                                 continue;
479                         if ( package_index == i )
480                                 IRQ_DELTA(package_index,j) = 0;
481                         /* Determine the total count per processor per IRQ */
482                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
483
484                         /* Determine the activity per processor per IRQ */
485                         delta = value_now - LAST_CPU_IRQ(i,j);
486
487                         /* Update last_cpu_irq[][] for the next time */
488                         LAST_CPU_IRQ(i,j) = value_now;
489
490                         /* Ignore IRQs whose rate is less than the clock */
491                         if (delta < useful_load_threshold)
492                                 continue;
493                         /* update the load for the processor or package total */
494                         IRQ_DELTA(package_index,j) += delta;
495
496                         /* Keep track of the higher numbered sibling as well */
497                         if (i != package_index)
498                                 CPU_IRQ(i) += delta;
499                         /*
500                          * We have sibling A and sibling B in the package
501                          *
502                          * cpu_irq[A] = load for cpu A + load for cpu B
503                          * cpu_irq[B] = load for cpu B
504                          */
505                         CPU_IRQ(package_index) += delta;
506                 }
507         }
508         /* Find the least loaded processor package */
509         for_each_online_cpu(i) {
510                 if (i != CPU_TO_PACKAGEINDEX(i))
511                         continue;
512                 if (min_cpu_irq > CPU_IRQ(i)) {
513                         min_cpu_irq = CPU_IRQ(i);
514                         min_loaded = i;
515                 }
516         }
517         max_cpu_irq = ULONG_MAX;
518
519 tryanothercpu:
520         /* Look for heaviest loaded processor.
521          * We may come back to get the next heaviest loaded processor.
522          * Skip processors with trivial loads.
523          */
524         tmp_cpu_irq = 0;
525         tmp_loaded = -1;
526         for_each_online_cpu(i) {
527                 if (i != CPU_TO_PACKAGEINDEX(i))
528                         continue;
529                 if (max_cpu_irq <= CPU_IRQ(i)) 
530                         continue;
531                 if (tmp_cpu_irq < CPU_IRQ(i)) {
532                         tmp_cpu_irq = CPU_IRQ(i);
533                         tmp_loaded = i;
534                 }
535         }
536
537         if (tmp_loaded == -1) {
538          /* In the case of small number of heavy interrupt sources, 
539           * loading some of the cpus too much. We use Ingo's original 
540           * approach to rotate them around.
541           */
542                 if (!first_attempt && imbalance >= useful_load_threshold) {
543                         rotate_irqs_among_cpus(useful_load_threshold);
544                         return;
545                 }
546                 goto not_worth_the_effort;
547         }
548         
549         first_attempt = 0;              /* heaviest search */
550         max_cpu_irq = tmp_cpu_irq;      /* load */
551         max_loaded = tmp_loaded;        /* processor */
552         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
553         
554         /* if imbalance is less than approx 10% of max load, then
555          * observe diminishing returns action. - quit
556          */
557         if (imbalance < (max_cpu_irq >> 3))
558                 goto not_worth_the_effort;
559
560 tryanotherirq:
561         /* if we select an IRQ to move that can't go where we want, then
562          * see if there is another one to try.
563          */
564         move_this_load = 0;
565         selected_irq = -1;
566         for (j = 0; j < NR_IRQS; j++) {
567                 /* Is this an active IRQ? */
568                 if (!irq_desc[j].action)
569                         continue;
570                 if (imbalance <= IRQ_DELTA(max_loaded,j))
571                         continue;
572                 /* Try to find the IRQ that is closest to the imbalance
573                  * without going over.
574                  */
575                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
576                         move_this_load = IRQ_DELTA(max_loaded,j);
577                         selected_irq = j;
578                 }
579         }
580         if (selected_irq == -1) {
581                 goto tryanothercpu;
582         }
583
584         imbalance = move_this_load;
585         
586         /* For physical_balance case, we accumulated both load
587          * values in the one of the siblings cpu_irq[],
588          * to use the same code for physical and logical processors
589          * as much as possible. 
590          *
591          * NOTE: the cpu_irq[] array holds the sum of the load for
592          * sibling A and sibling B in the slot for the lowest numbered
593          * sibling (A), _AND_ the load for sibling B in the slot for
594          * the higher numbered sibling.
595          *
596          * We seek the least loaded sibling by making the comparison
597          * (A+B)/2 vs B
598          */
599         load = CPU_IRQ(min_loaded) >> 1;
600         for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
601                 if (load > CPU_IRQ(j)) {
602                         /* This won't change cpu_sibling_map[min_loaded] */
603                         load = CPU_IRQ(j);
604                         min_loaded = j;
605                 }
606         }
607
608         cpus_and(allowed_mask,
609                 cpu_online_map,
610                 balance_irq_affinity[selected_irq]);
611         target_cpu_mask = cpumask_of_cpu(min_loaded);
612         cpus_and(tmp, target_cpu_mask, allowed_mask);
613
614         if (!cpus_empty(tmp)) {
615                 /* mark for change destination */
616                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
617
618                 /* Since we made a change, come back sooner to 
619                  * check for more variation.
620                  */
621                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
622                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
623                 return;
624         }
625         goto tryanotherirq;
626
627 not_worth_the_effort:
628         /*
629          * if we did not find an IRQ to move, then adjust the time interval
630          * upward
631          */
632         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
633                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);       
634         return;
635 }
636
637 static int balanced_irq(void *unused)
638 {
639         int i;
640         unsigned long prev_balance_time = jiffies;
641         long time_remaining = balanced_irq_interval;
642
643         /* push everything to CPU 0 to give us a starting point.  */
644         for (i = 0 ; i < NR_IRQS ; i++) {
645                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
646                 set_pending_irq(i, cpumask_of_cpu(0));
647         }
648
649         set_freezable();
650         for ( ; ; ) {
651                 time_remaining = schedule_timeout_interruptible(time_remaining);
652                 try_to_freeze();
653                 if (time_after(jiffies,
654                                 prev_balance_time+balanced_irq_interval)) {
655                         preempt_disable();
656                         do_irq_balance();
657                         prev_balance_time = jiffies;
658                         time_remaining = balanced_irq_interval;
659                         preempt_enable();
660                 }
661         }
662         return 0;
663 }
664
665 static int __init balanced_irq_init(void)
666 {
667         int i;
668         struct cpuinfo_x86 *c;
669         cpumask_t tmp;
670
671         cpus_shift_right(tmp, cpu_online_map, 2);
672         c = &boot_cpu_data;
673         /* When not overwritten by the command line ask subarchitecture. */
674         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
675                 irqbalance_disabled = NO_BALANCE_IRQ;
676         if (irqbalance_disabled)
677                 return 0;
678         
679          /* disable irqbalance completely if there is only one processor online */
680         if (num_online_cpus() < 2) {
681                 irqbalance_disabled = 1;
682                 return 0;
683         }
684         /*
685          * Enable physical balance only if more than 1 physical processor
686          * is present
687          */
688         if (smp_num_siblings > 1 && !cpus_empty(tmp))
689                 physical_balance = 1;
690
691         for_each_online_cpu(i) {
692                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
693                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
694                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
695                         printk(KERN_ERR "balanced_irq_init: out of memory");
696                         goto failed;
697                 }
698                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
699                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
700         }
701         
702         printk(KERN_INFO "Starting balanced_irq\n");
703         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
704                 return 0;
705         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
706 failed:
707         for_each_possible_cpu(i) {
708                 kfree(irq_cpu_data[i].irq_delta);
709                 irq_cpu_data[i].irq_delta = NULL;
710                 kfree(irq_cpu_data[i].last_irq);
711                 irq_cpu_data[i].last_irq = NULL;
712         }
713         return 0;
714 }
715
716 int __devinit irqbalance_disable(char *str)
717 {
718         irqbalance_disabled = 1;
719         return 1;
720 }
721
722 __setup("noirqbalance", irqbalance_disable);
723
724 late_initcall(balanced_irq_init);
725 #endif /* CONFIG_IRQBALANCE */
726 #endif /* CONFIG_SMP */
727
728 #ifndef CONFIG_SMP
729 void send_IPI_self(int vector)
730 {
731         unsigned int cfg;
732
733         /*
734          * Wait for idle.
735          */
736         apic_wait_icr_idle();
737         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
738         /*
739          * Send the IPI. The write to APIC_ICR fires this off.
740          */
741         apic_write_around(APIC_ICR, cfg);
742 }
743 #endif /* !CONFIG_SMP */
744
745
746 /*
747  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
748  * specific CPU-side IRQs.
749  */
750
751 #define MAX_PIRQS 8
752 static int pirq_entries [MAX_PIRQS];
753 static int pirqs_enabled;
754 int skip_ioapic_setup;
755
756 static int __init ioapic_pirq_setup(char *str)
757 {
758         int i, max;
759         int ints[MAX_PIRQS+1];
760
761         get_options(str, ARRAY_SIZE(ints), ints);
762
763         for (i = 0; i < MAX_PIRQS; i++)
764                 pirq_entries[i] = -1;
765
766         pirqs_enabled = 1;
767         apic_printk(APIC_VERBOSE, KERN_INFO
768                         "PIRQ redirection, working around broken MP-BIOS.\n");
769         max = MAX_PIRQS;
770         if (ints[0] < MAX_PIRQS)
771                 max = ints[0];
772
773         for (i = 0; i < max; i++) {
774                 apic_printk(APIC_VERBOSE, KERN_DEBUG
775                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
776                 /*
777                  * PIRQs are mapped upside down, usually.
778                  */
779                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
780         }
781         return 1;
782 }
783
784 __setup("pirq=", ioapic_pirq_setup);
785
786 /*
787  * Find the IRQ entry number of a certain pin.
788  */
789 static int find_irq_entry(int apic, int pin, int type)
790 {
791         int i;
792
793         for (i = 0; i < mp_irq_entries; i++)
794                 if (mp_irqs[i].mpc_irqtype == type &&
795                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
796                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
797                     mp_irqs[i].mpc_dstirq == pin)
798                         return i;
799
800         return -1;
801 }
802
803 /*
804  * Find the pin to which IRQ[irq] (ISA) is connected
805  */
806 static int __init find_isa_irq_pin(int irq, int type)
807 {
808         int i;
809
810         for (i = 0; i < mp_irq_entries; i++) {
811                 int lbus = mp_irqs[i].mpc_srcbus;
812
813                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
814                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
815                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
816                     ) &&
817                     (mp_irqs[i].mpc_irqtype == type) &&
818                     (mp_irqs[i].mpc_srcbusirq == irq))
819
820                         return mp_irqs[i].mpc_dstirq;
821         }
822         return -1;
823 }
824
825 static int __init find_isa_irq_apic(int irq, int type)
826 {
827         int i;
828
829         for (i = 0; i < mp_irq_entries; i++) {
830                 int lbus = mp_irqs[i].mpc_srcbus;
831
832                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
833                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
834                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
835                     ) &&
836                     (mp_irqs[i].mpc_irqtype == type) &&
837                     (mp_irqs[i].mpc_srcbusirq == irq))
838                         break;
839         }
840         if (i < mp_irq_entries) {
841                 int apic;
842                 for(apic = 0; apic < nr_ioapics; apic++) {
843                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
844                                 return apic;
845                 }
846         }
847
848         return -1;
849 }
850
851 /*
852  * Find a specific PCI IRQ entry.
853  * Not an __init, possibly needed by modules
854  */
855 static int pin_2_irq(int idx, int apic, int pin);
856
857 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
858 {
859         int apic, i, best_guess = -1;
860
861         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
862                 "slot:%d, pin:%d.\n", bus, slot, pin);
863         if (mp_bus_id_to_pci_bus[bus] == -1) {
864                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
865                 return -1;
866         }
867         for (i = 0; i < mp_irq_entries; i++) {
868                 int lbus = mp_irqs[i].mpc_srcbus;
869
870                 for (apic = 0; apic < nr_ioapics; apic++)
871                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
872                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
873                                 break;
874
875                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
876                     !mp_irqs[i].mpc_irqtype &&
877                     (bus == lbus) &&
878                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
879                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
880
881                         if (!(apic || IO_APIC_IRQ(irq)))
882                                 continue;
883
884                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
885                                 return irq;
886                         /*
887                          * Use the first all-but-pin matching entry as a
888                          * best-guess fuzzy result for broken mptables.
889                          */
890                         if (best_guess < 0)
891                                 best_guess = irq;
892                 }
893         }
894         return best_guess;
895 }
896 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
897
898 /*
899  * This function currently is only a helper for the i386 smp boot process where 
900  * we need to reprogram the ioredtbls to cater for the cpus which have come online
901  * so mask in all cases should simply be TARGET_CPUS
902  */
903 #ifdef CONFIG_SMP
904 void __init setup_ioapic_dest(void)
905 {
906         int pin, ioapic, irq, irq_entry;
907
908         if (skip_ioapic_setup == 1)
909                 return;
910
911         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
912                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
913                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
914                         if (irq_entry == -1)
915                                 continue;
916                         irq = pin_2_irq(irq_entry, ioapic, pin);
917                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
918                 }
919
920         }
921 }
922 #endif
923
924 /*
925  * EISA Edge/Level control register, ELCR
926  */
927 static int EISA_ELCR(unsigned int irq)
928 {
929         if (irq < 16) {
930                 unsigned int port = 0x4d0 + (irq >> 3);
931                 return (inb(port) >> (irq & 7)) & 1;
932         }
933         apic_printk(APIC_VERBOSE, KERN_INFO
934                         "Broken MPtable reports ISA irq %d\n", irq);
935         return 0;
936 }
937
938 /* EISA interrupts are always polarity zero and can be edge or level
939  * trigger depending on the ELCR value.  If an interrupt is listed as
940  * EISA conforming in the MP table, that means its trigger type must
941  * be read in from the ELCR */
942
943 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
944 #define default_EISA_polarity(idx)      (0)
945
946 /* ISA interrupts are always polarity zero edge triggered,
947  * when listed as conforming in the MP table. */
948
949 #define default_ISA_trigger(idx)        (0)
950 #define default_ISA_polarity(idx)       (0)
951
952 /* PCI interrupts are always polarity one level triggered,
953  * when listed as conforming in the MP table. */
954
955 #define default_PCI_trigger(idx)        (1)
956 #define default_PCI_polarity(idx)       (1)
957
958 /* MCA interrupts are always polarity zero level triggered,
959  * when listed as conforming in the MP table. */
960
961 #define default_MCA_trigger(idx)        (1)
962 #define default_MCA_polarity(idx)       (0)
963
964 static int MPBIOS_polarity(int idx)
965 {
966         int bus = mp_irqs[idx].mpc_srcbus;
967         int polarity;
968
969         /*
970          * Determine IRQ line polarity (high active or low active):
971          */
972         switch (mp_irqs[idx].mpc_irqflag & 3)
973         {
974                 case 0: /* conforms, ie. bus-type dependent polarity */
975                 {
976                         switch (mp_bus_id_to_type[bus])
977                         {
978                                 case MP_BUS_ISA: /* ISA pin */
979                                 {
980                                         polarity = default_ISA_polarity(idx);
981                                         break;
982                                 }
983                                 case MP_BUS_EISA: /* EISA pin */
984                                 {
985                                         polarity = default_EISA_polarity(idx);
986                                         break;
987                                 }
988                                 case MP_BUS_PCI: /* PCI pin */
989                                 {
990                                         polarity = default_PCI_polarity(idx);
991                                         break;
992                                 }
993                                 case MP_BUS_MCA: /* MCA pin */
994                                 {
995                                         polarity = default_MCA_polarity(idx);
996                                         break;
997                                 }
998                                 default:
999                                 {
1000                                         printk(KERN_WARNING "broken BIOS!!\n");
1001                                         polarity = 1;
1002                                         break;
1003                                 }
1004                         }
1005                         break;
1006                 }
1007                 case 1: /* high active */
1008                 {
1009                         polarity = 0;
1010                         break;
1011                 }
1012                 case 2: /* reserved */
1013                 {
1014                         printk(KERN_WARNING "broken BIOS!!\n");
1015                         polarity = 1;
1016                         break;
1017                 }
1018                 case 3: /* low active */
1019                 {
1020                         polarity = 1;
1021                         break;
1022                 }
1023                 default: /* invalid */
1024                 {
1025                         printk(KERN_WARNING "broken BIOS!!\n");
1026                         polarity = 1;
1027                         break;
1028                 }
1029         }
1030         return polarity;
1031 }
1032
1033 static int MPBIOS_trigger(int idx)
1034 {
1035         int bus = mp_irqs[idx].mpc_srcbus;
1036         int trigger;
1037
1038         /*
1039          * Determine IRQ trigger mode (edge or level sensitive):
1040          */
1041         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1042         {
1043                 case 0: /* conforms, ie. bus-type dependent */
1044                 {
1045                         switch (mp_bus_id_to_type[bus])
1046                         {
1047                                 case MP_BUS_ISA: /* ISA pin */
1048                                 {
1049                                         trigger = default_ISA_trigger(idx);
1050                                         break;
1051                                 }
1052                                 case MP_BUS_EISA: /* EISA pin */
1053                                 {
1054                                         trigger = default_EISA_trigger(idx);
1055                                         break;
1056                                 }
1057                                 case MP_BUS_PCI: /* PCI pin */
1058                                 {
1059                                         trigger = default_PCI_trigger(idx);
1060                                         break;
1061                                 }
1062                                 case MP_BUS_MCA: /* MCA pin */
1063                                 {
1064                                         trigger = default_MCA_trigger(idx);
1065                                         break;
1066                                 }
1067                                 default:
1068                                 {
1069                                         printk(KERN_WARNING "broken BIOS!!\n");
1070                                         trigger = 1;
1071                                         break;
1072                                 }
1073                         }
1074                         break;
1075                 }
1076                 case 1: /* edge */
1077                 {
1078                         trigger = 0;
1079                         break;
1080                 }
1081                 case 2: /* reserved */
1082                 {
1083                         printk(KERN_WARNING "broken BIOS!!\n");
1084                         trigger = 1;
1085                         break;
1086                 }
1087                 case 3: /* level */
1088                 {
1089                         trigger = 1;
1090                         break;
1091                 }
1092                 default: /* invalid */
1093                 {
1094                         printk(KERN_WARNING "broken BIOS!!\n");
1095                         trigger = 0;
1096                         break;
1097                 }
1098         }
1099         return trigger;
1100 }
1101
1102 static inline int irq_polarity(int idx)
1103 {
1104         return MPBIOS_polarity(idx);
1105 }
1106
1107 static inline int irq_trigger(int idx)
1108 {
1109         return MPBIOS_trigger(idx);
1110 }
1111
1112 static int pin_2_irq(int idx, int apic, int pin)
1113 {
1114         int irq, i;
1115         int bus = mp_irqs[idx].mpc_srcbus;
1116
1117         /*
1118          * Debugging check, we are in big trouble if this message pops up!
1119          */
1120         if (mp_irqs[idx].mpc_dstirq != pin)
1121                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1122
1123         switch (mp_bus_id_to_type[bus])
1124         {
1125                 case MP_BUS_ISA: /* ISA pin */
1126                 case MP_BUS_EISA:
1127                 case MP_BUS_MCA:
1128                 {
1129                         irq = mp_irqs[idx].mpc_srcbusirq;
1130                         break;
1131                 }
1132                 case MP_BUS_PCI: /* PCI pin */
1133                 {
1134                         /*
1135                          * PCI IRQs are mapped in order
1136                          */
1137                         i = irq = 0;
1138                         while (i < apic)
1139                                 irq += nr_ioapic_registers[i++];
1140                         irq += pin;
1141
1142                         /*
1143                          * For MPS mode, so far only needed by ES7000 platform
1144                          */
1145                         if (ioapic_renumber_irq)
1146                                 irq = ioapic_renumber_irq(apic, irq);
1147
1148                         break;
1149                 }
1150                 default:
1151                 {
1152                         printk(KERN_ERR "unknown bus type %d.\n",bus); 
1153                         irq = 0;
1154                         break;
1155                 }
1156         }
1157
1158         /*
1159          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1160          */
1161         if ((pin >= 16) && (pin <= 23)) {
1162                 if (pirq_entries[pin-16] != -1) {
1163                         if (!pirq_entries[pin-16]) {
1164                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1165                                                 "disabling PIRQ%d\n", pin-16);
1166                         } else {
1167                                 irq = pirq_entries[pin-16];
1168                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1169                                                 "using PIRQ%d -> IRQ %d\n",
1170                                                 pin-16, irq);
1171                         }
1172                 }
1173         }
1174         return irq;
1175 }
1176
1177 static inline int IO_APIC_irq_trigger(int irq)
1178 {
1179         int apic, idx, pin;
1180
1181         for (apic = 0; apic < nr_ioapics; apic++) {
1182                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1183                         idx = find_irq_entry(apic,pin,mp_INT);
1184                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1185                                 return irq_trigger(idx);
1186                 }
1187         }
1188         /*
1189          * nonexistent IRQs are edge default
1190          */
1191         return 0;
1192 }
1193
1194 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1195 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1196
1197 static int __assign_irq_vector(int irq)
1198 {
1199         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1200         int vector, offset;
1201
1202         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1203
1204         if (irq_vector[irq] > 0)
1205                 return irq_vector[irq];
1206
1207         vector = current_vector;
1208         offset = current_offset;
1209 next:
1210         vector += 8;
1211         if (vector >= FIRST_SYSTEM_VECTOR) {
1212                 offset = (offset + 1) % 8;
1213                 vector = FIRST_DEVICE_VECTOR + offset;
1214         }
1215         if (vector == current_vector)
1216                 return -ENOSPC;
1217         if (test_and_set_bit(vector, used_vectors))
1218                 goto next;
1219
1220         current_vector = vector;
1221         current_offset = offset;
1222         irq_vector[irq] = vector;
1223
1224         return vector;
1225 }
1226
1227 static int assign_irq_vector(int irq)
1228 {
1229         unsigned long flags;
1230         int vector;
1231
1232         spin_lock_irqsave(&vector_lock, flags);
1233         vector = __assign_irq_vector(irq);
1234         spin_unlock_irqrestore(&vector_lock, flags);
1235
1236         return vector;
1237 }
1238 static struct irq_chip ioapic_chip;
1239
1240 #define IOAPIC_AUTO     -1
1241 #define IOAPIC_EDGE     0
1242 #define IOAPIC_LEVEL    1
1243
1244 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1245 {
1246         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1247             trigger == IOAPIC_LEVEL) {
1248                 irq_desc[irq].status |= IRQ_LEVEL;
1249                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1250                                          handle_fasteoi_irq, "fasteoi");
1251         } else {
1252                 irq_desc[irq].status &= ~IRQ_LEVEL;
1253                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1254                                          handle_edge_irq, "edge");
1255         }
1256         set_intr_gate(vector, interrupt[irq]);
1257 }
1258
1259 static void __init setup_IO_APIC_irqs(void)
1260 {
1261         struct IO_APIC_route_entry entry;
1262         int apic, pin, idx, irq, first_notcon = 1, vector;
1263         unsigned long flags;
1264
1265         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1266
1267         for (apic = 0; apic < nr_ioapics; apic++) {
1268         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1269
1270                 /*
1271                  * add it to the IO-APIC irq-routing table:
1272                  */
1273                 memset(&entry,0,sizeof(entry));
1274
1275                 entry.delivery_mode = INT_DELIVERY_MODE;
1276                 entry.dest_mode = INT_DEST_MODE;
1277                 entry.mask = 0;                         /* enable IRQ */
1278                 entry.dest.logical.logical_dest = 
1279                                         cpu_mask_to_apicid(TARGET_CPUS);
1280
1281                 idx = find_irq_entry(apic,pin,mp_INT);
1282                 if (idx == -1) {
1283                         if (first_notcon) {
1284                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1285                                                 " IO-APIC (apicid-pin) %d-%d",
1286                                                 mp_ioapics[apic].mpc_apicid,
1287                                                 pin);
1288                                 first_notcon = 0;
1289                         } else
1290                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1291                                         mp_ioapics[apic].mpc_apicid, pin);
1292                         continue;
1293                 }
1294
1295                 if (!first_notcon) {
1296                         apic_printk(APIC_VERBOSE, " not connected.\n");
1297                         first_notcon = 1;
1298                 }
1299
1300                 entry.trigger = irq_trigger(idx);
1301                 entry.polarity = irq_polarity(idx);
1302
1303                 if (irq_trigger(idx)) {
1304                         entry.trigger = 1;
1305                         entry.mask = 1;
1306                 }
1307
1308                 irq = pin_2_irq(idx, apic, pin);
1309                 /*
1310                  * skip adding the timer int on secondary nodes, which causes
1311                  * a small but painful rift in the time-space continuum
1312                  */
1313                 if (multi_timer_check(apic, irq))
1314                         continue;
1315                 else
1316                         add_pin_to_irq(irq, apic, pin);
1317
1318                 if (!apic && !IO_APIC_IRQ(irq))
1319                         continue;
1320
1321                 if (IO_APIC_IRQ(irq)) {
1322                         vector = assign_irq_vector(irq);
1323                         entry.vector = vector;
1324                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1325                 
1326                         if (!apic && (irq < 16))
1327                                 disable_8259A_irq(irq);
1328                 }
1329                 spin_lock_irqsave(&ioapic_lock, flags);
1330                 __ioapic_write_entry(apic, pin, entry);
1331                 spin_unlock_irqrestore(&ioapic_lock, flags);
1332         }
1333         }
1334
1335         if (!first_notcon)
1336                 apic_printk(APIC_VERBOSE, " not connected.\n");
1337 }
1338
1339 /*
1340  * Set up the 8259A-master output pin:
1341  */
1342 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1343 {
1344         struct IO_APIC_route_entry entry;
1345
1346         memset(&entry,0,sizeof(entry));
1347
1348         disable_8259A_irq(0);
1349
1350         /* mask LVT0 */
1351         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1352
1353         /*
1354          * We use logical delivery to get the timer IRQ
1355          * to the first CPU.
1356          */
1357         entry.dest_mode = INT_DEST_MODE;
1358         entry.mask = 0;                                 /* unmask IRQ now */
1359         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1360         entry.delivery_mode = INT_DELIVERY_MODE;
1361         entry.polarity = 0;
1362         entry.trigger = 0;
1363         entry.vector = vector;
1364
1365         /*
1366          * The timer IRQ doesn't have to know that behind the
1367          * scene we have a 8259A-master in AEOI mode ...
1368          */
1369         irq_desc[0].chip = &ioapic_chip;
1370         set_irq_handler(0, handle_edge_irq);
1371
1372         /*
1373          * Add it to the IO-APIC irq-routing table:
1374          */
1375         ioapic_write_entry(apic, pin, entry);
1376
1377         enable_8259A_irq(0);
1378 }
1379
1380 void __init print_IO_APIC(void)
1381 {
1382         int apic, i;
1383         union IO_APIC_reg_00 reg_00;
1384         union IO_APIC_reg_01 reg_01;
1385         union IO_APIC_reg_02 reg_02;
1386         union IO_APIC_reg_03 reg_03;
1387         unsigned long flags;
1388
1389         if (apic_verbosity == APIC_QUIET)
1390                 return;
1391
1392         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1393         for (i = 0; i < nr_ioapics; i++)
1394                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1395                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1396
1397         /*
1398          * We are a bit conservative about what we expect.  We have to
1399          * know about every hardware change ASAP.
1400          */
1401         printk(KERN_INFO "testing the IO APIC.......................\n");
1402
1403         for (apic = 0; apic < nr_ioapics; apic++) {
1404
1405         spin_lock_irqsave(&ioapic_lock, flags);
1406         reg_00.raw = io_apic_read(apic, 0);
1407         reg_01.raw = io_apic_read(apic, 1);
1408         if (reg_01.bits.version >= 0x10)
1409                 reg_02.raw = io_apic_read(apic, 2);
1410         if (reg_01.bits.version >= 0x20)
1411                 reg_03.raw = io_apic_read(apic, 3);
1412         spin_unlock_irqrestore(&ioapic_lock, flags);
1413
1414         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1415         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1416         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1417         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1418         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1419
1420         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1421         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1422
1423         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1424         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1425
1426         /*
1427          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1428          * but the value of reg_02 is read as the previous read register
1429          * value, so ignore it if reg_02 == reg_01.
1430          */
1431         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1432                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1433                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1434         }
1435
1436         /*
1437          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1438          * or reg_03, but the value of reg_0[23] is read as the previous read
1439          * register value, so ignore it if reg_03 == reg_0[12].
1440          */
1441         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1442             reg_03.raw != reg_01.raw) {
1443                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1444                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1445         }
1446
1447         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1448
1449         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1450                           " Stat Dest Deli Vect:   \n");
1451
1452         for (i = 0; i <= reg_01.bits.entries; i++) {
1453                 struct IO_APIC_route_entry entry;
1454
1455                 entry = ioapic_read_entry(apic, i);
1456
1457                 printk(KERN_DEBUG " %02x %03X %02X  ",
1458                         i,
1459                         entry.dest.logical.logical_dest,
1460                         entry.dest.physical.physical_dest
1461                 );
1462
1463                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1464                         entry.mask,
1465                         entry.trigger,
1466                         entry.irr,
1467                         entry.polarity,
1468                         entry.delivery_status,
1469                         entry.dest_mode,
1470                         entry.delivery_mode,
1471                         entry.vector
1472                 );
1473         }
1474         }
1475         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1476         for (i = 0; i < NR_IRQS; i++) {
1477                 struct irq_pin_list *entry = irq_2_pin + i;
1478                 if (entry->pin < 0)
1479                         continue;
1480                 printk(KERN_DEBUG "IRQ%d ", i);
1481                 for (;;) {
1482                         printk("-> %d:%d", entry->apic, entry->pin);
1483                         if (!entry->next)
1484                                 break;
1485                         entry = irq_2_pin + entry->next;
1486                 }
1487                 printk("\n");
1488         }
1489
1490         printk(KERN_INFO ".................................... done.\n");
1491
1492         return;
1493 }
1494
1495 #if 0
1496
1497 static void print_APIC_bitfield (int base)
1498 {
1499         unsigned int v;
1500         int i, j;
1501
1502         if (apic_verbosity == APIC_QUIET)
1503                 return;
1504
1505         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1506         for (i = 0; i < 8; i++) {
1507                 v = apic_read(base + i*0x10);
1508                 for (j = 0; j < 32; j++) {
1509                         if (v & (1<<j))
1510                                 printk("1");
1511                         else
1512                                 printk("0");
1513                 }
1514                 printk("\n");
1515         }
1516 }
1517
1518 void /*__init*/ print_local_APIC(void * dummy)
1519 {
1520         unsigned int v, ver, maxlvt;
1521
1522         if (apic_verbosity == APIC_QUIET)
1523                 return;
1524
1525         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1526                 smp_processor_id(), hard_smp_processor_id());
1527         v = apic_read(APIC_ID);
1528         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1529         v = apic_read(APIC_LVR);
1530         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1531         ver = GET_APIC_VERSION(v);
1532         maxlvt = lapic_get_maxlvt();
1533
1534         v = apic_read(APIC_TASKPRI);
1535         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1536
1537         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1538                 v = apic_read(APIC_ARBPRI);
1539                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1540                         v & APIC_ARBPRI_MASK);
1541                 v = apic_read(APIC_PROCPRI);
1542                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1543         }
1544
1545         v = apic_read(APIC_EOI);
1546         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1547         v = apic_read(APIC_RRR);
1548         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1549         v = apic_read(APIC_LDR);
1550         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1551         v = apic_read(APIC_DFR);
1552         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1553         v = apic_read(APIC_SPIV);
1554         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1555
1556         printk(KERN_DEBUG "... APIC ISR field:\n");
1557         print_APIC_bitfield(APIC_ISR);
1558         printk(KERN_DEBUG "... APIC TMR field:\n");
1559         print_APIC_bitfield(APIC_TMR);
1560         printk(KERN_DEBUG "... APIC IRR field:\n");
1561         print_APIC_bitfield(APIC_IRR);
1562
1563         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1564                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1565                         apic_write(APIC_ESR, 0);
1566                 v = apic_read(APIC_ESR);
1567                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1568         }
1569
1570         v = apic_read(APIC_ICR);
1571         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1572         v = apic_read(APIC_ICR2);
1573         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1574
1575         v = apic_read(APIC_LVTT);
1576         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1577
1578         if (maxlvt > 3) {                       /* PC is LVT#4. */
1579                 v = apic_read(APIC_LVTPC);
1580                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1581         }
1582         v = apic_read(APIC_LVT0);
1583         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1584         v = apic_read(APIC_LVT1);
1585         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1586
1587         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1588                 v = apic_read(APIC_LVTERR);
1589                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1590         }
1591
1592         v = apic_read(APIC_TMICT);
1593         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1594         v = apic_read(APIC_TMCCT);
1595         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1596         v = apic_read(APIC_TDCR);
1597         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1598         printk("\n");
1599 }
1600
1601 void print_all_local_APICs (void)
1602 {
1603         on_each_cpu(print_local_APIC, NULL, 1, 1);
1604 }
1605
1606 void /*__init*/ print_PIC(void)
1607 {
1608         unsigned int v;
1609         unsigned long flags;
1610
1611         if (apic_verbosity == APIC_QUIET)
1612                 return;
1613
1614         printk(KERN_DEBUG "\nprinting PIC contents\n");
1615
1616         spin_lock_irqsave(&i8259A_lock, flags);
1617
1618         v = inb(0xa1) << 8 | inb(0x21);
1619         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1620
1621         v = inb(0xa0) << 8 | inb(0x20);
1622         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1623
1624         outb(0x0b,0xa0);
1625         outb(0x0b,0x20);
1626         v = inb(0xa0) << 8 | inb(0x20);
1627         outb(0x0a,0xa0);
1628         outb(0x0a,0x20);
1629
1630         spin_unlock_irqrestore(&i8259A_lock, flags);
1631
1632         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1633
1634         v = inb(0x4d1) << 8 | inb(0x4d0);
1635         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1636 }
1637
1638 #endif  /*  0  */
1639
1640 static void __init enable_IO_APIC(void)
1641 {
1642         union IO_APIC_reg_01 reg_01;
1643         int i8259_apic, i8259_pin;
1644         int i, apic;
1645         unsigned long flags;
1646
1647         for (i = 0; i < PIN_MAP_SIZE; i++) {
1648                 irq_2_pin[i].pin = -1;
1649                 irq_2_pin[i].next = 0;
1650         }
1651         if (!pirqs_enabled)
1652                 for (i = 0; i < MAX_PIRQS; i++)
1653                         pirq_entries[i] = -1;
1654
1655         /*
1656          * The number of IO-APIC IRQ registers (== #pins):
1657          */
1658         for (apic = 0; apic < nr_ioapics; apic++) {
1659                 spin_lock_irqsave(&ioapic_lock, flags);
1660                 reg_01.raw = io_apic_read(apic, 1);
1661                 spin_unlock_irqrestore(&ioapic_lock, flags);
1662                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1663         }
1664         for(apic = 0; apic < nr_ioapics; apic++) {
1665                 int pin;
1666                 /* See if any of the pins is in ExtINT mode */
1667                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1668                         struct IO_APIC_route_entry entry;
1669                         entry = ioapic_read_entry(apic, pin);
1670
1671
1672                         /* If the interrupt line is enabled and in ExtInt mode
1673                          * I have found the pin where the i8259 is connected.
1674                          */
1675                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1676                                 ioapic_i8259.apic = apic;
1677                                 ioapic_i8259.pin  = pin;
1678                                 goto found_i8259;
1679                         }
1680                 }
1681         }
1682  found_i8259:
1683         /* Look to see what if the MP table has reported the ExtINT */
1684         /* If we could not find the appropriate pin by looking at the ioapic
1685          * the i8259 probably is not connected the ioapic but give the
1686          * mptable a chance anyway.
1687          */
1688         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1689         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1690         /* Trust the MP table if nothing is setup in the hardware */
1691         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1692                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1693                 ioapic_i8259.pin  = i8259_pin;
1694                 ioapic_i8259.apic = i8259_apic;
1695         }
1696         /* Complain if the MP table and the hardware disagree */
1697         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1698                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1699         {
1700                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1701         }
1702
1703         /*
1704          * Do not trust the IO-APIC being empty at bootup
1705          */
1706         clear_IO_APIC();
1707 }
1708
1709 /*
1710  * Not an __init, needed by the reboot code
1711  */
1712 void disable_IO_APIC(void)
1713 {
1714         /*
1715          * Clear the IO-APIC before rebooting:
1716          */
1717         clear_IO_APIC();
1718
1719         /*
1720          * If the i8259 is routed through an IOAPIC
1721          * Put that IOAPIC in virtual wire mode
1722          * so legacy interrupts can be delivered.
1723          */
1724         if (ioapic_i8259.pin != -1) {
1725                 struct IO_APIC_route_entry entry;
1726
1727                 memset(&entry, 0, sizeof(entry));
1728                 entry.mask            = 0; /* Enabled */
1729                 entry.trigger         = 0; /* Edge */
1730                 entry.irr             = 0;
1731                 entry.polarity        = 0; /* High */
1732                 entry.delivery_status = 0;
1733                 entry.dest_mode       = 0; /* Physical */
1734                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1735                 entry.vector          = 0;
1736                 entry.dest.physical.physical_dest =
1737                                         GET_APIC_ID(apic_read(APIC_ID));
1738
1739                 /*
1740                  * Add it to the IO-APIC irq-routing table:
1741                  */
1742                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1743         }
1744         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1745 }
1746
1747 /*
1748  * function to set the IO-APIC physical IDs based on the
1749  * values stored in the MPC table.
1750  *
1751  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1752  */
1753
1754 #ifndef CONFIG_X86_NUMAQ
1755 static void __init setup_ioapic_ids_from_mpc(void)
1756 {
1757         union IO_APIC_reg_00 reg_00;
1758         physid_mask_t phys_id_present_map;
1759         int apic;
1760         int i;
1761         unsigned char old_id;
1762         unsigned long flags;
1763
1764         /*
1765          * Don't check I/O APIC IDs for xAPIC systems.  They have
1766          * no meaning without the serial APIC bus.
1767          */
1768         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1769                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1770                 return;
1771         /*
1772          * This is broken; anything with a real cpu count has to
1773          * circumvent this idiocy regardless.
1774          */
1775         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1776
1777         /*
1778          * Set the IOAPIC ID to the value stored in the MPC table.
1779          */
1780         for (apic = 0; apic < nr_ioapics; apic++) {
1781
1782                 /* Read the register 0 value */
1783                 spin_lock_irqsave(&ioapic_lock, flags);
1784                 reg_00.raw = io_apic_read(apic, 0);
1785                 spin_unlock_irqrestore(&ioapic_lock, flags);
1786                 
1787                 old_id = mp_ioapics[apic].mpc_apicid;
1788
1789                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1790                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1791                                 apic, mp_ioapics[apic].mpc_apicid);
1792                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1793                                 reg_00.bits.ID);
1794                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1795                 }
1796
1797                 /*
1798                  * Sanity check, is the ID really free? Every APIC in a
1799                  * system must have a unique ID or we get lots of nice
1800                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1801                  */
1802                 if (check_apicid_used(phys_id_present_map,
1803                                         mp_ioapics[apic].mpc_apicid)) {
1804                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1805                                 apic, mp_ioapics[apic].mpc_apicid);
1806                         for (i = 0; i < get_physical_broadcast(); i++)
1807                                 if (!physid_isset(i, phys_id_present_map))
1808                                         break;
1809                         if (i >= get_physical_broadcast())
1810                                 panic("Max APIC ID exceeded!\n");
1811                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1812                                 i);
1813                         physid_set(i, phys_id_present_map);
1814                         mp_ioapics[apic].mpc_apicid = i;
1815                 } else {
1816                         physid_mask_t tmp;
1817                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1818                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1819                                         "phys_id_present_map\n",
1820                                         mp_ioapics[apic].mpc_apicid);
1821                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1822                 }
1823
1824
1825                 /*
1826                  * We need to adjust the IRQ routing table
1827                  * if the ID changed.
1828                  */
1829                 if (old_id != mp_ioapics[apic].mpc_apicid)
1830                         for (i = 0; i < mp_irq_entries; i++)
1831                                 if (mp_irqs[i].mpc_dstapic == old_id)
1832                                         mp_irqs[i].mpc_dstapic
1833                                                 = mp_ioapics[apic].mpc_apicid;
1834
1835                 /*
1836                  * Read the right value from the MPC table and
1837                  * write it into the ID register.
1838                  */
1839                 apic_printk(APIC_VERBOSE, KERN_INFO
1840                         "...changing IO-APIC physical APIC ID to %d ...",
1841                         mp_ioapics[apic].mpc_apicid);
1842
1843                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1844                 spin_lock_irqsave(&ioapic_lock, flags);
1845                 io_apic_write(apic, 0, reg_00.raw);
1846                 spin_unlock_irqrestore(&ioapic_lock, flags);
1847
1848                 /*
1849                  * Sanity check
1850                  */
1851                 spin_lock_irqsave(&ioapic_lock, flags);
1852                 reg_00.raw = io_apic_read(apic, 0);
1853                 spin_unlock_irqrestore(&ioapic_lock, flags);
1854                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1855                         printk("could not set ID!\n");
1856                 else
1857                         apic_printk(APIC_VERBOSE, " ok.\n");
1858         }
1859 }
1860 #else
1861 static void __init setup_ioapic_ids_from_mpc(void) { }
1862 #endif
1863
1864 int no_timer_check __initdata;
1865
1866 static int __init notimercheck(char *s)
1867 {
1868         no_timer_check = 1;
1869         return 1;
1870 }
1871 __setup("no_timer_check", notimercheck);
1872
1873 /*
1874  * There is a nasty bug in some older SMP boards, their mptable lies
1875  * about the timer IRQ. We do the following to work around the situation:
1876  *
1877  *      - timer IRQ defaults to IO-APIC IRQ
1878  *      - if this function detects that timer IRQs are defunct, then we fall
1879  *        back to ISA timer IRQs
1880  */
1881 static int __init timer_irq_works(void)
1882 {
1883         unsigned long t1 = jiffies;
1884         unsigned long flags;
1885
1886         if (no_timer_check)
1887                 return 1;
1888
1889         local_save_flags(flags);
1890         local_irq_enable();
1891         /* Let ten ticks pass... */
1892         mdelay((10 * 1000) / HZ);
1893         local_irq_restore(flags);
1894
1895         /*
1896          * Expect a few ticks at least, to be sure some possible
1897          * glue logic does not lock up after one or two first
1898          * ticks in a non-ExtINT mode.  Also the local APIC
1899          * might have cached one ExtINT interrupt.  Finally, at
1900          * least one tick may be lost due to delays.
1901          */
1902         if (time_after(jiffies, t1 + 4))
1903                 return 1;
1904
1905         return 0;
1906 }
1907
1908 /*
1909  * In the SMP+IOAPIC case it might happen that there are an unspecified
1910  * number of pending IRQ events unhandled. These cases are very rare,
1911  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1912  * better to do it this way as thus we do not have to be aware of
1913  * 'pending' interrupts in the IRQ path, except at this point.
1914  */
1915 /*
1916  * Edge triggered needs to resend any interrupt
1917  * that was delayed but this is now handled in the device
1918  * independent code.
1919  */
1920
1921 /*
1922  * Startup quirk:
1923  *
1924  * Starting up a edge-triggered IO-APIC interrupt is
1925  * nasty - we need to make sure that we get the edge.
1926  * If it is already asserted for some reason, we need
1927  * return 1 to indicate that is was pending.
1928  *
1929  * This is not complete - we should be able to fake
1930  * an edge even if it isn't on the 8259A...
1931  *
1932  * (We do this for level-triggered IRQs too - it cannot hurt.)
1933  */
1934 static unsigned int startup_ioapic_irq(unsigned int irq)
1935 {
1936         int was_pending = 0;
1937         unsigned long flags;
1938
1939         spin_lock_irqsave(&ioapic_lock, flags);
1940         if (irq < 16) {
1941                 disable_8259A_irq(irq);
1942                 if (i8259A_irq_pending(irq))
1943                         was_pending = 1;
1944         }
1945         __unmask_IO_APIC_irq(irq);
1946         spin_unlock_irqrestore(&ioapic_lock, flags);
1947
1948         return was_pending;
1949 }
1950
1951 static void ack_ioapic_irq(unsigned int irq)
1952 {
1953         move_native_irq(irq);
1954         ack_APIC_irq();
1955 }
1956
1957 static void ack_ioapic_quirk_irq(unsigned int irq)
1958 {
1959         unsigned long v;
1960         int i;
1961
1962         move_native_irq(irq);
1963 /*
1964  * It appears there is an erratum which affects at least version 0x11
1965  * of I/O APIC (that's the 82093AA and cores integrated into various
1966  * chipsets).  Under certain conditions a level-triggered interrupt is
1967  * erroneously delivered as edge-triggered one but the respective IRR
1968  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1969  * message but it will never arrive and further interrupts are blocked
1970  * from the source.  The exact reason is so far unknown, but the
1971  * phenomenon was observed when two consecutive interrupt requests
1972  * from a given source get delivered to the same CPU and the source is
1973  * temporarily disabled in between.
1974  *
1975  * A workaround is to simulate an EOI message manually.  We achieve it
1976  * by setting the trigger mode to edge and then to level when the edge
1977  * trigger mode gets detected in the TMR of a local APIC for a
1978  * level-triggered interrupt.  We mask the source for the time of the
1979  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1980  * The idea is from Manfred Spraul.  --macro
1981  */
1982         i = irq_vector[irq];
1983
1984         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1985
1986         ack_APIC_irq();
1987
1988         if (!(v & (1 << (i & 0x1f)))) {
1989                 atomic_inc(&irq_mis_count);
1990                 spin_lock(&ioapic_lock);
1991                 __mask_and_edge_IO_APIC_irq(irq);
1992                 __unmask_and_level_IO_APIC_irq(irq);
1993                 spin_unlock(&ioapic_lock);
1994         }
1995 }
1996
1997 static int ioapic_retrigger_irq(unsigned int irq)
1998 {
1999         send_IPI_self(irq_vector[irq]);
2000
2001         return 1;
2002 }
2003
2004 static struct irq_chip ioapic_chip __read_mostly = {
2005         .name           = "IO-APIC",
2006         .startup        = startup_ioapic_irq,
2007         .mask           = mask_IO_APIC_irq,
2008         .unmask         = unmask_IO_APIC_irq,
2009         .ack            = ack_ioapic_irq,
2010         .eoi            = ack_ioapic_quirk_irq,
2011 #ifdef CONFIG_SMP
2012         .set_affinity   = set_ioapic_affinity_irq,
2013 #endif
2014         .retrigger      = ioapic_retrigger_irq,
2015 };
2016
2017
2018 static inline void init_IO_APIC_traps(void)
2019 {
2020         int irq;
2021
2022         /*
2023          * NOTE! The local APIC isn't very good at handling
2024          * multiple interrupts at the same interrupt level.
2025          * As the interrupt level is determined by taking the
2026          * vector number and shifting that right by 4, we
2027          * want to spread these out a bit so that they don't
2028          * all fall in the same interrupt level.
2029          *
2030          * Also, we've got to be careful not to trash gate
2031          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2032          */
2033         for (irq = 0; irq < NR_IRQS ; irq++) {
2034                 int tmp = irq;
2035                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2036                         /*
2037                          * Hmm.. We don't have an entry for this,
2038                          * so default to an old-fashioned 8259
2039                          * interrupt if we can..
2040                          */
2041                         if (irq < 16)
2042                                 make_8259A_irq(irq);
2043                         else
2044                                 /* Strange. Oh, well.. */
2045                                 irq_desc[irq].chip = &no_irq_chip;
2046                 }
2047         }
2048 }
2049
2050 /*
2051  * The local APIC irq-chip implementation:
2052  */
2053
2054 static void ack_apic(unsigned int irq)
2055 {
2056         ack_APIC_irq();
2057 }
2058
2059 static void mask_lapic_irq (unsigned int irq)
2060 {
2061         unsigned long v;
2062
2063         v = apic_read(APIC_LVT0);
2064         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2065 }
2066
2067 static void unmask_lapic_irq (unsigned int irq)
2068 {
2069         unsigned long v;
2070
2071         v = apic_read(APIC_LVT0);
2072         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2073 }
2074
2075 static struct irq_chip lapic_chip __read_mostly = {
2076         .name           = "local-APIC-edge",
2077         .mask           = mask_lapic_irq,
2078         .unmask         = unmask_lapic_irq,
2079         .eoi            = ack_apic,
2080 };
2081
2082 static void __init setup_nmi(void)
2083 {
2084         /*
2085          * Dirty trick to enable the NMI watchdog ...
2086          * We put the 8259A master into AEOI mode and
2087          * unmask on all local APICs LVT0 as NMI.
2088          *
2089          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2090          * is from Maciej W. Rozycki - so we do not have to EOI from
2091          * the NMI handler or the timer interrupt.
2092          */ 
2093         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2094
2095         enable_NMI_through_LVT0();
2096
2097         apic_printk(APIC_VERBOSE, " done.\n");
2098 }
2099
2100 /*
2101  * This looks a bit hackish but it's about the only one way of sending
2102  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2103  * not support the ExtINT mode, unfortunately.  We need to send these
2104  * cycles as some i82489DX-based boards have glue logic that keeps the
2105  * 8259A interrupt line asserted until INTA.  --macro
2106  */
2107 static inline void unlock_ExtINT_logic(void)
2108 {
2109         int apic, pin, i;
2110         struct IO_APIC_route_entry entry0, entry1;
2111         unsigned char save_control, save_freq_select;
2112
2113         pin  = find_isa_irq_pin(8, mp_INT);
2114         if (pin == -1) {
2115                 WARN_ON_ONCE(1);
2116                 return;
2117         }
2118         apic = find_isa_irq_apic(8, mp_INT);
2119         if (apic == -1) {
2120                 WARN_ON_ONCE(1);
2121                 return;
2122         }
2123
2124         entry0 = ioapic_read_entry(apic, pin);
2125         clear_IO_APIC_pin(apic, pin);
2126
2127         memset(&entry1, 0, sizeof(entry1));
2128
2129         entry1.dest_mode = 0;                   /* physical delivery */
2130         entry1.mask = 0;                        /* unmask IRQ now */
2131         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2132         entry1.delivery_mode = dest_ExtINT;
2133         entry1.polarity = entry0.polarity;
2134         entry1.trigger = 0;
2135         entry1.vector = 0;
2136
2137         ioapic_write_entry(apic, pin, entry1);
2138
2139         save_control = CMOS_READ(RTC_CONTROL);
2140         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2141         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2142                    RTC_FREQ_SELECT);
2143         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2144
2145         i = 100;
2146         while (i-- > 0) {
2147                 mdelay(10);
2148                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2149                         i -= 10;
2150         }
2151
2152         CMOS_WRITE(save_control, RTC_CONTROL);
2153         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2154         clear_IO_APIC_pin(apic, pin);
2155
2156         ioapic_write_entry(apic, pin, entry0);
2157 }
2158
2159 int timer_uses_ioapic_pin_0;
2160
2161 /*
2162  * This code may look a bit paranoid, but it's supposed to cooperate with
2163  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2164  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2165  * fanatically on his truly buggy board.
2166  */
2167 static inline void __init check_timer(void)
2168 {
2169         int apic1, pin1, apic2, pin2;
2170         int vector;
2171         unsigned long flags;
2172
2173         local_irq_save(flags);
2174
2175         /*
2176          * get/set the timer IRQ vector:
2177          */
2178         disable_8259A_irq(0);
2179         vector = assign_irq_vector(0);
2180         set_intr_gate(vector, interrupt[0]);
2181
2182         /*
2183          * Subtle, code in do_timer_interrupt() expects an AEOI
2184          * mode for the 8259A whenever interrupts are routed
2185          * through I/O APICs.  Also IRQ0 has to be enabled in
2186          * the 8259A which implies the virtual wire has to be
2187          * disabled in the local APIC.
2188          */
2189         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2190         init_8259A(1);
2191         timer_ack = 1;
2192         if (timer_over_8254 > 0)
2193                 enable_8259A_irq(0);
2194
2195         pin1  = find_isa_irq_pin(0, mp_INT);
2196         apic1 = find_isa_irq_apic(0, mp_INT);
2197         pin2  = ioapic_i8259.pin;
2198         apic2 = ioapic_i8259.apic;
2199
2200         if (pin1 == 0)
2201                 timer_uses_ioapic_pin_0 = 1;
2202
2203         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2204                 vector, apic1, pin1, apic2, pin2);
2205
2206         if (pin1 != -1) {
2207                 /*
2208                  * Ok, does IRQ0 through the IOAPIC work?
2209                  */
2210                 unmask_IO_APIC_irq(0);
2211                 if (timer_irq_works()) {
2212                         if (nmi_watchdog == NMI_IO_APIC) {
2213                                 disable_8259A_irq(0);
2214                                 setup_nmi();
2215                                 enable_8259A_irq(0);
2216                         }
2217                         if (disable_timer_pin_1 > 0)
2218                                 clear_IO_APIC_pin(0, pin1);
2219                         goto out;
2220                 }
2221                 clear_IO_APIC_pin(apic1, pin1);
2222                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2223                                 "IO-APIC\n");
2224         }
2225
2226         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2227         if (pin2 != -1) {
2228                 printk("\n..... (found pin %d) ...", pin2);
2229                 /*
2230                  * legacy devices should be connected to IO APIC #0
2231                  */
2232                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2233                 if (timer_irq_works()) {
2234                         printk("works.\n");
2235                         if (pin1 != -1)
2236                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2237                         else
2238                                 add_pin_to_irq(0, apic2, pin2);
2239                         if (nmi_watchdog == NMI_IO_APIC) {
2240                                 setup_nmi();
2241                         }
2242                         goto out;
2243                 }
2244                 /*
2245                  * Cleanup, just in case ...
2246                  */
2247                 clear_IO_APIC_pin(apic2, pin2);
2248         }
2249         printk(" failed.\n");
2250
2251         if (nmi_watchdog == NMI_IO_APIC) {
2252                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2253                 nmi_watchdog = 0;
2254         }
2255
2256         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2257
2258         disable_8259A_irq(0);
2259         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2260                                       "fasteoi");
2261         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2262         enable_8259A_irq(0);
2263
2264         if (timer_irq_works()) {
2265                 printk(" works.\n");
2266                 goto out;
2267         }
2268         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2269         printk(" failed.\n");
2270
2271         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2272
2273         timer_ack = 0;
2274         init_8259A(0);
2275         make_8259A_irq(0);
2276         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2277
2278         unlock_ExtINT_logic();
2279
2280         if (timer_irq_works()) {
2281                 printk(" works.\n");
2282                 goto out;
2283         }
2284         printk(" failed :(.\n");
2285         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2286                 "report.  Then try booting with the 'noapic' option");
2287 out:
2288         local_irq_restore(flags);
2289 }
2290
2291 /*
2292  *
2293  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2294  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2295  *   Linux doesn't really care, as it's not actually used
2296  *   for any interrupt handling anyway.
2297  */
2298 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2299
2300 void __init setup_IO_APIC(void)
2301 {
2302         int i;
2303
2304         /* Reserve all the system vectors. */
2305         for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2306                 set_bit(i, used_vectors);
2307
2308         enable_IO_APIC();
2309
2310         if (acpi_ioapic)
2311                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2312         else
2313                 io_apic_irqs = ~PIC_IRQS;
2314
2315         printk("ENABLING IO-APIC IRQs\n");
2316
2317         /*
2318          * Set up IO-APIC IRQ routing.
2319          */
2320         if (!acpi_ioapic)
2321                 setup_ioapic_ids_from_mpc();
2322         sync_Arb_IDs();
2323         setup_IO_APIC_irqs();
2324         init_IO_APIC_traps();
2325         check_timer();
2326         if (!acpi_ioapic)
2327                 print_IO_APIC();
2328 }
2329
2330 static int __init setup_disable_8254_timer(char *s)
2331 {
2332         timer_over_8254 = -1;
2333         return 1;
2334 }
2335 static int __init setup_enable_8254_timer(char *s)
2336 {
2337         timer_over_8254 = 2;
2338         return 1;
2339 }
2340
2341 __setup("disable_8254_timer", setup_disable_8254_timer);
2342 __setup("enable_8254_timer", setup_enable_8254_timer);
2343
2344 /*
2345  *      Called after all the initialization is done. If we didnt find any
2346  *      APIC bugs then we can allow the modify fast path
2347  */
2348  
2349 static int __init io_apic_bug_finalize(void)
2350 {
2351         if(sis_apic_bug == -1)
2352                 sis_apic_bug = 0;
2353         return 0;
2354 }
2355
2356 late_initcall(io_apic_bug_finalize);
2357
2358 struct sysfs_ioapic_data {
2359         struct sys_device dev;
2360         struct IO_APIC_route_entry entry[0];
2361 };
2362 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2363
2364 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2365 {
2366         struct IO_APIC_route_entry *entry;
2367         struct sysfs_ioapic_data *data;
2368         int i;
2369         
2370         data = container_of(dev, struct sysfs_ioapic_data, dev);
2371         entry = data->entry;
2372         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2373                 entry[i] = ioapic_read_entry(dev->id, i);
2374
2375         return 0;
2376 }
2377
2378 static int ioapic_resume(struct sys_device *dev)
2379 {
2380         struct IO_APIC_route_entry *entry;
2381         struct sysfs_ioapic_data *data;
2382         unsigned long flags;
2383         union IO_APIC_reg_00 reg_00;
2384         int i;
2385         
2386         data = container_of(dev, struct sysfs_ioapic_data, dev);
2387         entry = data->entry;
2388
2389         spin_lock_irqsave(&ioapic_lock, flags);
2390         reg_00.raw = io_apic_read(dev->id, 0);
2391         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2392                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2393                 io_apic_write(dev->id, 0, reg_00.raw);
2394         }
2395         spin_unlock_irqrestore(&ioapic_lock, flags);
2396         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2397                 ioapic_write_entry(dev->id, i, entry[i]);
2398
2399         return 0;
2400 }
2401
2402 static struct sysdev_class ioapic_sysdev_class = {
2403         .name = "ioapic",
2404         .suspend = ioapic_suspend,
2405         .resume = ioapic_resume,
2406 };
2407
2408 static int __init ioapic_init_sysfs(void)
2409 {
2410         struct sys_device * dev;
2411         int i, size, error = 0;
2412
2413         error = sysdev_class_register(&ioapic_sysdev_class);
2414         if (error)
2415                 return error;
2416
2417         for (i = 0; i < nr_ioapics; i++ ) {
2418                 size = sizeof(struct sys_device) + nr_ioapic_registers[i] 
2419                         * sizeof(struct IO_APIC_route_entry);
2420                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2421                 if (!mp_ioapic_data[i]) {
2422                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2423                         continue;
2424                 }
2425                 memset(mp_ioapic_data[i], 0, size);
2426                 dev = &mp_ioapic_data[i]->dev;
2427                 dev->id = i; 
2428                 dev->cls = &ioapic_sysdev_class;
2429                 error = sysdev_register(dev);
2430                 if (error) {
2431                         kfree(mp_ioapic_data[i]);
2432                         mp_ioapic_data[i] = NULL;
2433                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2434                         continue;
2435                 }
2436         }
2437
2438         return 0;
2439 }
2440
2441 device_initcall(ioapic_init_sysfs);
2442
2443 /*
2444  * Dynamic irq allocate and deallocation
2445  */
2446 int create_irq(void)
2447 {
2448         /* Allocate an unused irq */
2449         int irq, new, vector = 0;
2450         unsigned long flags;
2451
2452         irq = -ENOSPC;
2453         spin_lock_irqsave(&vector_lock, flags);
2454         for (new = (NR_IRQS - 1); new >= 0; new--) {
2455                 if (platform_legacy_irq(new))
2456                         continue;
2457                 if (irq_vector[new] != 0)
2458                         continue;
2459                 vector = __assign_irq_vector(new);
2460                 if (likely(vector > 0))
2461                         irq = new;
2462                 break;
2463         }
2464         spin_unlock_irqrestore(&vector_lock, flags);
2465
2466         if (irq >= 0) {
2467                 set_intr_gate(vector, interrupt[irq]);
2468                 dynamic_irq_init(irq);
2469         }
2470         return irq;
2471 }
2472
2473 void destroy_irq(unsigned int irq)
2474 {
2475         unsigned long flags;
2476
2477         dynamic_irq_cleanup(irq);
2478
2479         spin_lock_irqsave(&vector_lock, flags);
2480         irq_vector[irq] = 0;
2481         spin_unlock_irqrestore(&vector_lock, flags);
2482 }
2483
2484 /*
2485  * MSI message composition
2486  */
2487 #ifdef CONFIG_PCI_MSI
2488 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2489 {
2490         int vector;
2491         unsigned dest;
2492
2493         vector = assign_irq_vector(irq);
2494         if (vector >= 0) {
2495                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2496
2497                 msg->address_hi = MSI_ADDR_BASE_HI;
2498                 msg->address_lo =
2499                         MSI_ADDR_BASE_LO |
2500                         ((INT_DEST_MODE == 0) ?
2501                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2502                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2503                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2504                                 MSI_ADDR_REDIRECTION_CPU:
2505                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2506                         MSI_ADDR_DEST_ID(dest);
2507
2508                 msg->data =
2509                         MSI_DATA_TRIGGER_EDGE |
2510                         MSI_DATA_LEVEL_ASSERT |
2511                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2512                                 MSI_DATA_DELIVERY_FIXED:
2513                                 MSI_DATA_DELIVERY_LOWPRI) |
2514                         MSI_DATA_VECTOR(vector);
2515         }
2516         return vector;
2517 }
2518
2519 #ifdef CONFIG_SMP
2520 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2521 {
2522         struct msi_msg msg;
2523         unsigned int dest;
2524         cpumask_t tmp;
2525         int vector;
2526
2527         cpus_and(tmp, mask, cpu_online_map);
2528         if (cpus_empty(tmp))
2529                 tmp = TARGET_CPUS;
2530
2531         vector = assign_irq_vector(irq);
2532         if (vector < 0)
2533                 return;
2534
2535         dest = cpu_mask_to_apicid(mask);
2536
2537         read_msi_msg(irq, &msg);
2538
2539         msg.data &= ~MSI_DATA_VECTOR_MASK;
2540         msg.data |= MSI_DATA_VECTOR(vector);
2541         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2542         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2543
2544         write_msi_msg(irq, &msg);
2545         irq_desc[irq].affinity = mask;
2546 }
2547 #endif /* CONFIG_SMP */
2548
2549 /*
2550  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2551  * which implement the MSI or MSI-X Capability Structure.
2552  */
2553 static struct irq_chip msi_chip = {
2554         .name           = "PCI-MSI",
2555         .unmask         = unmask_msi_irq,
2556         .mask           = mask_msi_irq,
2557         .ack            = ack_ioapic_irq,
2558 #ifdef CONFIG_SMP
2559         .set_affinity   = set_msi_irq_affinity,
2560 #endif
2561         .retrigger      = ioapic_retrigger_irq,
2562 };
2563
2564 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2565 {
2566         struct msi_msg msg;
2567         int irq, ret;
2568         irq = create_irq();
2569         if (irq < 0)
2570                 return irq;
2571
2572         ret = msi_compose_msg(dev, irq, &msg);
2573         if (ret < 0) {
2574                 destroy_irq(irq);
2575                 return ret;
2576         }
2577
2578         set_irq_msi(irq, desc);
2579         write_msi_msg(irq, &msg);
2580
2581         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2582                                       "edge");
2583
2584         return 0;
2585 }
2586
2587 void arch_teardown_msi_irq(unsigned int irq)
2588 {
2589         destroy_irq(irq);
2590 }
2591
2592 #endif /* CONFIG_PCI_MSI */
2593
2594 /*
2595  * Hypertransport interrupt support
2596  */
2597 #ifdef CONFIG_HT_IRQ
2598
2599 #ifdef CONFIG_SMP
2600
2601 static void target_ht_irq(unsigned int irq, unsigned int dest)
2602 {
2603         struct ht_irq_msg msg;
2604         fetch_ht_irq_msg(irq, &msg);
2605
2606         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2607         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2608
2609         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2610         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2611
2612         write_ht_irq_msg(irq, &msg);
2613 }
2614
2615 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2616 {
2617         unsigned int dest;
2618         cpumask_t tmp;
2619
2620         cpus_and(tmp, mask, cpu_online_map);
2621         if (cpus_empty(tmp))
2622                 tmp = TARGET_CPUS;
2623
2624         cpus_and(mask, tmp, CPU_MASK_ALL);
2625
2626         dest = cpu_mask_to_apicid(mask);
2627
2628         target_ht_irq(irq, dest);
2629         irq_desc[irq].affinity = mask;
2630 }
2631 #endif
2632
2633 static struct irq_chip ht_irq_chip = {
2634         .name           = "PCI-HT",
2635         .mask           = mask_ht_irq,
2636         .unmask         = unmask_ht_irq,
2637         .ack            = ack_ioapic_irq,
2638 #ifdef CONFIG_SMP
2639         .set_affinity   = set_ht_irq_affinity,
2640 #endif
2641         .retrigger      = ioapic_retrigger_irq,
2642 };
2643
2644 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2645 {
2646         int vector;
2647
2648         vector = assign_irq_vector(irq);
2649         if (vector >= 0) {
2650                 struct ht_irq_msg msg;
2651                 unsigned dest;
2652                 cpumask_t tmp;
2653
2654                 cpus_clear(tmp);
2655                 cpu_set(vector >> 8, tmp);
2656                 dest = cpu_mask_to_apicid(tmp);
2657
2658                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2659
2660                 msg.address_lo =
2661                         HT_IRQ_LOW_BASE |
2662                         HT_IRQ_LOW_DEST_ID(dest) |
2663                         HT_IRQ_LOW_VECTOR(vector) |
2664                         ((INT_DEST_MODE == 0) ?
2665                                 HT_IRQ_LOW_DM_PHYSICAL :
2666                                 HT_IRQ_LOW_DM_LOGICAL) |
2667                         HT_IRQ_LOW_RQEOI_EDGE |
2668                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2669                                 HT_IRQ_LOW_MT_FIXED :
2670                                 HT_IRQ_LOW_MT_ARBITRATED) |
2671                         HT_IRQ_LOW_IRQ_MASKED;
2672
2673                 write_ht_irq_msg(irq, &msg);
2674
2675                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2676                                               handle_edge_irq, "edge");
2677         }
2678         return vector;
2679 }
2680 #endif /* CONFIG_HT_IRQ */
2681
2682 /* --------------------------------------------------------------------------
2683                           ACPI-based IOAPIC Configuration
2684    -------------------------------------------------------------------------- */
2685
2686 #ifdef CONFIG_ACPI
2687
2688 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2689 {
2690         union IO_APIC_reg_00 reg_00;
2691         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2692         physid_mask_t tmp;
2693         unsigned long flags;
2694         int i = 0;
2695
2696         /*
2697          * The P4 platform supports up to 256 APIC IDs on two separate APIC 
2698          * buses (one for LAPICs, one for IOAPICs), where predecessors only 
2699          * supports up to 16 on one shared APIC bus.
2700          * 
2701          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2702          *      advantage of new APIC bus architecture.
2703          */
2704
2705         if (physids_empty(apic_id_map))
2706                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2707
2708         spin_lock_irqsave(&ioapic_lock, flags);
2709         reg_00.raw = io_apic_read(ioapic, 0);
2710         spin_unlock_irqrestore(&ioapic_lock, flags);
2711
2712         if (apic_id >= get_physical_broadcast()) {
2713                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2714                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2715                 apic_id = reg_00.bits.ID;
2716         }
2717
2718         /*
2719          * Every APIC in a system must have a unique ID or we get lots of nice 
2720          * 'stuck on smp_invalidate_needed IPI wait' messages.
2721          */
2722         if (check_apicid_used(apic_id_map, apic_id)) {
2723
2724                 for (i = 0; i < get_physical_broadcast(); i++) {
2725                         if (!check_apicid_used(apic_id_map, i))
2726                                 break;
2727                 }
2728
2729                 if (i == get_physical_broadcast())
2730                         panic("Max apic_id exceeded!\n");
2731
2732                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2733                         "trying %d\n", ioapic, apic_id, i);
2734
2735                 apic_id = i;
2736         } 
2737
2738         tmp = apicid_to_cpu_present(apic_id);
2739         physids_or(apic_id_map, apic_id_map, tmp);
2740
2741         if (reg_00.bits.ID != apic_id) {
2742                 reg_00.bits.ID = apic_id;
2743
2744                 spin_lock_irqsave(&ioapic_lock, flags);
2745                 io_apic_write(ioapic, 0, reg_00.raw);
2746                 reg_00.raw = io_apic_read(ioapic, 0);
2747                 spin_unlock_irqrestore(&ioapic_lock, flags);
2748
2749                 /* Sanity check */
2750                 if (reg_00.bits.ID != apic_id) {
2751                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2752                         return -1;
2753                 }
2754         }
2755
2756         apic_printk(APIC_VERBOSE, KERN_INFO
2757                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2758
2759         return apic_id;
2760 }
2761
2762
2763 int __init io_apic_get_version (int ioapic)
2764 {
2765         union IO_APIC_reg_01    reg_01;
2766         unsigned long flags;
2767
2768         spin_lock_irqsave(&ioapic_lock, flags);
2769         reg_01.raw = io_apic_read(ioapic, 1);
2770         spin_unlock_irqrestore(&ioapic_lock, flags);
2771
2772         return reg_01.bits.version;
2773 }
2774
2775
2776 int __init io_apic_get_redir_entries (int ioapic)
2777 {
2778         union IO_APIC_reg_01    reg_01;
2779         unsigned long flags;
2780
2781         spin_lock_irqsave(&ioapic_lock, flags);
2782         reg_01.raw = io_apic_read(ioapic, 1);
2783         spin_unlock_irqrestore(&ioapic_lock, flags);
2784
2785         return reg_01.bits.entries;
2786 }
2787
2788
2789 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2790 {
2791         struct IO_APIC_route_entry entry;
2792         unsigned long flags;
2793
2794         if (!IO_APIC_IRQ(irq)) {
2795                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2796                         ioapic);
2797                 return -EINVAL;
2798         }
2799
2800         /*
2801          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2802          * Note that we mask (disable) IRQs now -- these get enabled when the
2803          * corresponding device driver registers for this IRQ.
2804          */
2805
2806         memset(&entry,0,sizeof(entry));
2807
2808         entry.delivery_mode = INT_DELIVERY_MODE;
2809         entry.dest_mode = INT_DEST_MODE;
2810         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2811         entry.trigger = edge_level;
2812         entry.polarity = active_high_low;
2813         entry.mask  = 1;
2814
2815         /*
2816          * IRQs < 16 are already in the irq_2_pin[] map
2817          */
2818         if (irq >= 16)
2819                 add_pin_to_irq(irq, ioapic, pin);
2820
2821         entry.vector = assign_irq_vector(irq);
2822
2823         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2824                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2825                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2826                 edge_level, active_high_low);
2827
2828         ioapic_register_intr(irq, entry.vector, edge_level);
2829
2830         if (!ioapic && (irq < 16))
2831                 disable_8259A_irq(irq);
2832
2833         spin_lock_irqsave(&ioapic_lock, flags);
2834         __ioapic_write_entry(ioapic, pin, entry);
2835         spin_unlock_irqrestore(&ioapic_lock, flags);
2836
2837         return 0;
2838 }
2839
2840 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2841 {
2842         int i;
2843
2844         if (skip_ioapic_setup)
2845                 return -1;
2846
2847         for (i = 0; i < mp_irq_entries; i++)
2848                 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2849                     mp_irqs[i].mpc_srcbusirq == bus_irq)
2850                         break;
2851         if (i >= mp_irq_entries)
2852                 return -1;
2853
2854         *trigger = irq_trigger(i);
2855         *polarity = irq_polarity(i);
2856         return 0;
2857 }
2858
2859 #endif /* CONFIG_ACPI */
2860
2861 static int __init parse_disable_timer_pin_1(char *arg)
2862 {
2863         disable_timer_pin_1 = 1;
2864         return 0;
2865 }
2866 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2867
2868 static int __init parse_enable_timer_pin_1(char *arg)
2869 {
2870         disable_timer_pin_1 = -1;
2871         return 0;
2872 }
2873 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2874
2875 static int __init parse_noapic(char *arg)
2876 {
2877         /* disable IO-APIC */
2878         disable_ioapic_setup();
2879         return 0;
2880 }
2881 early_param("noapic", parse_noapic);