2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
49 #include <asm/proto.h>
52 #include <asm/timer.h>
53 #include <asm/i8259.h>
55 #include <asm/msidef.h>
56 #include <asm/hypertransport.h>
57 #include <asm/setup.h>
58 #include <asm/irq_remapping.h>
61 #include <mach_apic.h>
62 #include <mach_apicdef.h>
64 #define __apicdebuginit(type) static type __init
67 * Is the SiS APIC rmw bug present ?
68 * -1 = don't know, 0 = no, 1 = yes
70 int sis_apic_bug = -1;
72 static DEFINE_SPINLOCK(ioapic_lock);
73 static DEFINE_SPINLOCK(vector_lock);
77 * Rough estimation of how many shared IRQs there are, can
83 * # of IRQ routing registers
85 int nr_ioapic_registers[MAX_IO_APICS];
87 /* I/O APIC entries */
88 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
91 /* MP IRQ source entries */
92 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
94 /* # of MP IRQ source entries */
97 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
98 int mp_bus_id_to_type[MAX_MP_BUSSES];
101 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
103 int skip_ioapic_setup;
105 static int __init parse_noapic(char *arg)
107 /* disable IO-APIC */
108 disable_ioapic_setup();
111 early_param("noapic", parse_noapic);
117 struct irq_cfg *next;
118 struct irq_pin_list *irq_2_pin;
120 cpumask_t old_domain;
121 unsigned move_cleanup_count;
123 u8 move_in_progress : 1;
126 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
127 static struct irq_cfg irq_cfg_legacy[] __initdata = {
128 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
129 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
130 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
131 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
132 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
133 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
134 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
135 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
136 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
137 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
138 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
139 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
140 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
141 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
142 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
143 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
146 static struct irq_cfg irq_cfg_init = { .irq = -1U, };
147 /* need to be biger than size of irq_cfg_legacy */
148 static int nr_irq_cfg = 32;
150 static int __init parse_nr_irq_cfg(char *arg)
153 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
160 early_param("nr_irq_cfg", parse_nr_irq_cfg);
162 static void init_one_irq_cfg(struct irq_cfg *cfg)
164 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
167 static struct irq_cfg *irq_cfgx;
168 static struct irq_cfg *irq_cfgx_free;
169 static void __init init_work(void *data)
171 struct dyn_array *da = data;
178 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
180 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
181 for (i = legacy_count; i < *da->nr; i++)
182 init_one_irq_cfg(&cfg[i]);
184 for (i = 1; i < *da->nr; i++)
185 cfg[i-1].next = &cfg[i];
187 irq_cfgx_free = &irq_cfgx[legacy_count];
188 irq_cfgx[legacy_count - 1].next = NULL;
191 #define for_each_irq_cfg(cfg) \
192 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
194 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
196 static struct irq_cfg *irq_cfg(unsigned int irq)
211 static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
213 struct irq_cfg *cfg, *cfg_pri;
217 cfg_pri = cfg = irq_cfgx;
227 if (!irq_cfgx_free) {
229 unsigned long total_bytes;
231 * we run out of pre-allocate ones, allocate more
233 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
235 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
237 cfg = kzalloc(total_bytes, GFP_ATOMIC);
239 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
242 panic("please boot with nr_irq_cfg= %d\n", count * 2);
245 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
247 for (i = 0; i < nr_irq_cfg; i++)
248 init_one_irq_cfg(&cfg[i]);
250 for (i = 1; i < nr_irq_cfg; i++)
251 cfg[i-1].next = &cfg[i];
257 irq_cfgx_free = irq_cfgx_free->next;
264 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
266 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
268 /* dump the results */
271 unsigned long bytes = sizeof(struct irq_cfg);
273 printk(KERN_DEBUG "=========================== %d\n", irq);
274 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
275 for_each_irq_cfg(cfg) {
277 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
279 printk(KERN_DEBUG "===========================\n");
286 * This is performance-critical, we want to do it O(1)
288 * the indexing order of this array favors 1:1 mappings
289 * between pins and IRQs.
292 struct irq_pin_list {
294 struct irq_pin_list *next;
297 static struct irq_pin_list *irq_2_pin_head;
298 /* fill one page ? */
299 static int nr_irq_2_pin = 0x100;
300 static struct irq_pin_list *irq_2_pin_ptr;
301 static void __init irq_2_pin_init_work(void *data)
303 struct dyn_array *da = data;
304 struct irq_pin_list *pin;
309 for (i = 1; i < *da->nr; i++)
310 pin[i-1].next = &pin[i];
312 irq_2_pin_ptr = &pin[0];
314 DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
316 static struct irq_pin_list *get_one_free_irq_2_pin(void)
318 struct irq_pin_list *pin;
324 irq_2_pin_ptr = pin->next;
330 * we run out of pre-allocate ones, allocate more
332 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
335 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
338 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
339 nr_irq_2_pin, PAGE_SIZE, 0);
342 panic("can not get more irq_2_pin\n");
344 for (i = 1; i < nr_irq_2_pin; i++)
345 pin[i-1].next = &pin[i];
347 irq_2_pin_ptr = pin->next;
355 unsigned int unused[3];
359 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
361 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
362 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
365 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
367 struct io_apic __iomem *io_apic = io_apic_base(apic);
368 writel(reg, &io_apic->index);
369 return readl(&io_apic->data);
372 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
374 struct io_apic __iomem *io_apic = io_apic_base(apic);
375 writel(reg, &io_apic->index);
376 writel(value, &io_apic->data);
380 * Re-write a value: to be used for read-modify-write
381 * cycles where the read already set up the index register.
383 * Older SiS APIC requires we rewrite the index register
385 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
387 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
389 writel(reg, &io_apic->index);
390 writel(value, &io_apic->data);
394 static bool io_apic_level_ack_pending(unsigned int irq)
396 struct irq_pin_list *entry;
398 struct irq_cfg *cfg = irq_cfg(irq);
400 spin_lock_irqsave(&ioapic_lock, flags);
401 entry = cfg->irq_2_pin;
409 reg = io_apic_read(entry->apic, 0x10 + pin*2);
410 /* Is the remote IRR bit set? */
411 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
412 spin_unlock_irqrestore(&ioapic_lock, flags);
419 spin_unlock_irqrestore(&ioapic_lock, flags);
426 struct { u32 w1, w2; };
427 struct IO_APIC_route_entry entry;
430 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
432 union entry_union eu;
434 spin_lock_irqsave(&ioapic_lock, flags);
435 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
436 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
437 spin_unlock_irqrestore(&ioapic_lock, flags);
442 * When we write a new IO APIC routing entry, we need to write the high
443 * word first! If the mask bit in the low word is clear, we will enable
444 * the interrupt, and we need to make sure the entry is fully populated
445 * before that happens.
448 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
450 union entry_union eu;
452 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
453 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
456 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
459 spin_lock_irqsave(&ioapic_lock, flags);
460 __ioapic_write_entry(apic, pin, e);
461 spin_unlock_irqrestore(&ioapic_lock, flags);
465 * When we mask an IO APIC routing entry, we need to write the low
466 * word first, in order to set the mask bit before we change the
469 static void ioapic_mask_entry(int apic, int pin)
472 union entry_union eu = { .entry.mask = 1 };
474 spin_lock_irqsave(&ioapic_lock, flags);
475 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
476 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
477 spin_unlock_irqrestore(&ioapic_lock, flags);
481 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
485 struct irq_pin_list *entry;
488 entry = cfg->irq_2_pin;
497 io_apic_write(apic, 0x11 + pin*2, dest);
498 reg = io_apic_read(apic, 0x10 + pin*2);
499 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
501 io_apic_modify(apic, 0x10 + pin *2, reg);
508 static int assign_irq_vector(int irq, cpumask_t mask);
510 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
517 cpus_and(tmp, mask, cpu_online_map);
522 if (assign_irq_vector(irq, mask))
525 cpus_and(tmp, cfg->domain, mask);
526 dest = cpu_mask_to_apicid(tmp);
528 * Only the high 8 bits are valid.
530 dest = SET_APIC_LOGICAL_ID(dest);
532 spin_lock_irqsave(&ioapic_lock, flags);
533 __target_IO_APIC_irq(irq, dest, cfg->vector);
534 irq_to_desc(irq)->affinity = mask;
535 spin_unlock_irqrestore(&ioapic_lock, flags);
538 #endif /* CONFIG_SMP */
541 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
542 * shared ISA-space IRQs, so we have to support them. We are super
543 * fast in the common case, and fast for shared ISA-space IRQs.
545 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
548 struct irq_pin_list *entry;
550 /* first time to refer irq_cfg, so with new */
551 cfg = irq_cfg_alloc(irq);
552 entry = cfg->irq_2_pin;
554 entry = get_one_free_irq_2_pin();
555 cfg->irq_2_pin = entry;
558 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
562 while (entry->next) {
563 /* not again, please */
564 if (entry->apic == apic && entry->pin == pin)
570 entry->next = get_one_free_irq_2_pin();
574 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
578 * Reroute an IRQ to a different pin.
580 static void __init replace_pin_at_irq(unsigned int irq,
581 int oldapic, int oldpin,
582 int newapic, int newpin)
584 struct irq_cfg *cfg = irq_cfg(irq);
585 struct irq_pin_list *entry = cfg->irq_2_pin;
589 if (entry->apic == oldapic && entry->pin == oldpin) {
590 entry->apic = newapic;
593 /* every one is different, right? */
599 /* why? call replace before add? */
601 add_pin_to_irq(irq, newapic, newpin);
606 * Synchronize the IO-APIC and the CPU by doing
607 * a dummy read from the IO-APIC
609 static inline void io_apic_sync(unsigned int apic)
611 struct io_apic __iomem *io_apic = io_apic_base(apic);
612 readl(&io_apic->data);
615 #define __DO_ACTION(R, ACTION, FINAL) \
619 struct irq_cfg *cfg; \
620 struct irq_pin_list *entry; \
622 cfg = irq_cfg(irq); \
623 entry = cfg->irq_2_pin; \
629 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
631 io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
635 entry = entry->next; \
639 #define DO_ACTION(name,R,ACTION, FINAL) \
641 static void name##_IO_APIC_irq (unsigned int irq) \
642 __DO_ACTION(R, ACTION, FINAL)
645 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
648 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
652 static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
655 struct irq_pin_list *entry;
656 unsigned int pin, reg;
659 entry = cfg->irq_2_pin;
664 reg = io_apic_read(entry->apic, 0x10 + pin*2);
667 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
675 static void __mask_IO_APIC_irq(unsigned int irq)
677 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
681 static void __unmask_IO_APIC_irq(unsigned int irq)
683 __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
686 /* mask = 1, trigger = 0 */
687 static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
689 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
690 IO_APIC_REDIR_LEVEL_TRIGGER);
693 /* mask = 0, trigger = 1 */
694 static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
696 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
697 IO_APIC_REDIR_MASKED);
702 static void mask_IO_APIC_irq(unsigned int irq)
706 spin_lock_irqsave(&ioapic_lock, flags);
707 __mask_IO_APIC_irq(irq);
708 spin_unlock_irqrestore(&ioapic_lock, flags);
711 static void unmask_IO_APIC_irq(unsigned int irq)
715 spin_lock_irqsave(&ioapic_lock, flags);
716 __unmask_IO_APIC_irq(irq);
717 spin_unlock_irqrestore(&ioapic_lock, flags);
720 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
722 struct IO_APIC_route_entry entry;
724 /* Check delivery_mode to be sure we're not clearing an SMI pin */
725 entry = ioapic_read_entry(apic, pin);
726 if (entry.delivery_mode == dest_SMI)
730 * Disable it in the IO-APIC irq-routing table:
732 ioapic_mask_entry(apic, pin);
735 static void clear_IO_APIC(void)
739 for (apic = 0; apic < nr_ioapics; apic++)
740 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
741 clear_IO_APIC_pin(apic, pin);
745 void send_IPI_self(int vector)
752 apic_wait_icr_idle();
753 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
755 * Send the IPI. The write to APIC_ICR fires this off.
757 apic_write(APIC_ICR, cfg);
759 #endif /* !CONFIG_SMP */
763 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
764 * specific CPU-side IRQs.
768 static int pirq_entries [MAX_PIRQS];
769 static int pirqs_enabled;
771 static int __init ioapic_pirq_setup(char *str)
774 int ints[MAX_PIRQS+1];
776 get_options(str, ARRAY_SIZE(ints), ints);
778 for (i = 0; i < MAX_PIRQS; i++)
779 pirq_entries[i] = -1;
782 apic_printk(APIC_VERBOSE, KERN_INFO
783 "PIRQ redirection, working around broken MP-BIOS.\n");
785 if (ints[0] < MAX_PIRQS)
788 for (i = 0; i < max; i++) {
789 apic_printk(APIC_VERBOSE, KERN_DEBUG
790 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
792 * PIRQs are mapped upside down, usually.
794 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
799 __setup("pirq=", ioapic_pirq_setup);
802 * Find the IRQ entry number of a certain pin.
804 static int find_irq_entry(int apic, int pin, int type)
808 for (i = 0; i < mp_irq_entries; i++)
809 if (mp_irqs[i].mp_irqtype == type &&
810 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
811 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
812 mp_irqs[i].mp_dstirq == pin)
819 * Find the pin to which IRQ[irq] (ISA) is connected
821 static int __init find_isa_irq_pin(int irq, int type)
825 for (i = 0; i < mp_irq_entries; i++) {
826 int lbus = mp_irqs[i].mp_srcbus;
828 if (test_bit(lbus, mp_bus_not_pci) &&
829 (mp_irqs[i].mp_irqtype == type) &&
830 (mp_irqs[i].mp_srcbusirq == irq))
832 return mp_irqs[i].mp_dstirq;
837 static int __init find_isa_irq_apic(int irq, int type)
841 for (i = 0; i < mp_irq_entries; i++) {
842 int lbus = mp_irqs[i].mp_srcbus;
844 if (test_bit(lbus, mp_bus_not_pci) &&
845 (mp_irqs[i].mp_irqtype == type) &&
846 (mp_irqs[i].mp_srcbusirq == irq))
849 if (i < mp_irq_entries) {
851 for (apic = 0; apic < nr_ioapics; apic++) {
852 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
861 * Find a specific PCI IRQ entry.
862 * Not an __init, possibly needed by modules
864 static int pin_2_irq(int idx, int apic, int pin);
866 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
868 int apic, i, best_guess = -1;
870 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
871 "slot:%d, pin:%d.\n", bus, slot, pin);
872 if (test_bit(bus, mp_bus_not_pci)) {
873 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
876 for (i = 0; i < mp_irq_entries; i++) {
877 int lbus = mp_irqs[i].mp_srcbus;
879 for (apic = 0; apic < nr_ioapics; apic++)
880 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
881 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
884 if (!test_bit(lbus, mp_bus_not_pci) &&
885 !mp_irqs[i].mp_irqtype &&
887 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
888 int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq);
890 if (!(apic || IO_APIC_IRQ(irq)))
893 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
896 * Use the first all-but-pin matching entry as a
897 * best-guess fuzzy result for broken mptables.
905 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
907 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
909 * EISA Edge/Level control register, ELCR
911 static int EISA_ELCR(unsigned int irq)
914 unsigned int port = 0x4d0 + (irq >> 3);
915 return (inb(port) >> (irq & 7)) & 1;
917 apic_printk(APIC_VERBOSE, KERN_INFO
918 "Broken MPtable reports ISA irq %d\n", irq);
923 /* ISA interrupts are always polarity zero edge triggered,
924 * when listed as conforming in the MP table. */
926 #define default_ISA_trigger(idx) (0)
927 #define default_ISA_polarity(idx) (0)
929 /* EISA interrupts are always polarity zero and can be edge or level
930 * trigger depending on the ELCR value. If an interrupt is listed as
931 * EISA conforming in the MP table, that means its trigger type must
932 * be read in from the ELCR */
934 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
935 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
937 /* PCI interrupts are always polarity one level triggered,
938 * when listed as conforming in the MP table. */
940 #define default_PCI_trigger(idx) (1)
941 #define default_PCI_polarity(idx) (1)
943 /* MCA interrupts are always polarity zero level triggered,
944 * when listed as conforming in the MP table. */
946 #define default_MCA_trigger(idx) (1)
947 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
949 static int MPBIOS_polarity(int idx)
951 int bus = mp_irqs[idx].mp_srcbus;
955 * Determine IRQ line polarity (high active or low active):
957 switch (mp_irqs[idx].mp_irqflag & 3) {
958 case 0: /* conforms, ie. bus-type dependent polarity */
960 polarity = test_bit(bus, mp_bus_not_pci)?
961 default_ISA_polarity(idx):
962 default_PCI_polarity(idx);
965 case 1: /* high active */
970 case 2: /* reserved */
972 printk(KERN_WARNING "broken BIOS!!\n");
976 case 3: /* low active */
981 default: /* invalid */
983 printk(KERN_WARNING "broken BIOS!!\n");
991 static int MPBIOS_trigger(int idx)
993 int bus = mp_irqs[idx].mp_srcbus;
997 * Determine IRQ trigger mode (edge or level sensitive):
999 switch ((mp_irqs[idx].mp_irqflag>>2) & 3) {
1000 case 0: /* conforms, ie. bus-type dependent */
1002 trigger = test_bit(bus, mp_bus_not_pci)?
1003 default_ISA_trigger(idx):
1004 default_PCI_trigger(idx);
1005 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1006 switch (mp_bus_id_to_type[bus]) {
1007 case MP_BUS_ISA: /* ISA pin */
1009 /* set before the switch */
1012 case MP_BUS_EISA: /* EISA pin */
1014 trigger = default_EISA_trigger(idx);
1017 case MP_BUS_PCI: /* PCI pin */
1019 /* set before the switch */
1022 case MP_BUS_MCA: /* MCA pin */
1024 trigger = default_MCA_trigger(idx);
1029 printk(KERN_WARNING "broken BIOS!!\n");
1042 case 2: /* reserved */
1044 printk(KERN_WARNING "broken BIOS!!\n");
1053 default: /* invalid */
1055 printk(KERN_WARNING "broken BIOS!!\n");
1063 static inline int irq_polarity(int idx)
1065 return MPBIOS_polarity(idx);
1068 static inline int irq_trigger(int idx)
1070 return MPBIOS_trigger(idx);
1073 int (*ioapic_renumber_irq)(int ioapic, int irq);
1074 static int pin_2_irq(int idx, int apic, int pin)
1077 int bus = mp_irqs[idx].mp_srcbus;
1080 * Debugging check, we are in big trouble if this message pops up!
1082 if (mp_irqs[idx].mp_dstirq != pin)
1083 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1085 if (test_bit(bus, mp_bus_not_pci))
1086 irq = mp_irqs[idx].mp_srcbusirq;
1089 * PCI IRQs are mapped in order
1093 irq += nr_ioapic_registers[i++];
1097 * For MPS mode, so far only needed by ES7000 platform
1099 if (ioapic_renumber_irq)
1100 irq = ioapic_renumber_irq(apic, irq);
1104 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1106 if ((pin >= 16) && (pin <= 23)) {
1107 if (pirq_entries[pin-16] != -1) {
1108 if (!pirq_entries[pin-16]) {
1109 apic_printk(APIC_VERBOSE, KERN_DEBUG
1110 "disabling PIRQ%d\n", pin-16);
1112 irq = pirq_entries[pin-16];
1113 apic_printk(APIC_VERBOSE, KERN_DEBUG
1114 "using PIRQ%d -> IRQ %d\n",
1122 void lock_vector_lock(void)
1124 /* Used to the online set of cpus does not change
1125 * during assign_irq_vector.
1127 spin_lock(&vector_lock);
1130 void unlock_vector_lock(void)
1132 spin_unlock(&vector_lock);
1135 static int __assign_irq_vector(int irq, cpumask_t mask)
1138 * NOTE! The local APIC isn't very good at handling
1139 * multiple interrupts at the same interrupt level.
1140 * As the interrupt level is determined by taking the
1141 * vector number and shifting that right by 4, we
1142 * want to spread these out a bit so that they don't
1143 * all fall in the same interrupt level.
1145 * Also, we've got to be careful not to trash gate
1146 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1148 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1149 unsigned int old_vector;
1151 struct irq_cfg *cfg;
1155 /* Only try and allocate irqs on cpus that are present */
1156 cpus_and(mask, mask, cpu_online_map);
1158 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1161 old_vector = cfg->vector;
1164 cpus_and(tmp, cfg->domain, mask);
1165 if (!cpus_empty(tmp))
1169 for_each_cpu_mask_nr(cpu, mask) {
1170 cpumask_t domain, new_mask;
1174 domain = vector_allocation_domain(cpu);
1175 cpus_and(new_mask, domain, cpu_online_map);
1177 vector = current_vector;
1178 offset = current_offset;
1181 if (vector >= first_system_vector) {
1182 /* If we run out of vectors on large boxen, must share them. */
1183 offset = (offset + 1) % 8;
1184 vector = FIRST_DEVICE_VECTOR + offset;
1186 if (unlikely(current_vector == vector))
1188 #ifdef CONFIG_X86_64
1189 if (vector == IA32_SYSCALL_VECTOR)
1192 if (vector == SYSCALL_VECTOR)
1195 for_each_cpu_mask_nr(new_cpu, new_mask)
1196 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1199 current_vector = vector;
1200 current_offset = offset;
1202 cfg->move_in_progress = 1;
1203 cfg->old_domain = cfg->domain;
1205 printk(KERN_DEBUG "assign_irq_vector: irq %d vector %#x cpu ", irq, vector);
1206 for_each_cpu_mask_nr(new_cpu, new_mask) {
1207 per_cpu(vector_irq, new_cpu)[vector] = irq;
1208 printk(KERN_CONT " %d ", new_cpu);
1210 printk(KERN_CONT "\n");
1211 cfg->vector = vector;
1212 cfg->domain = domain;
1218 static int assign_irq_vector(int irq, cpumask_t mask)
1221 unsigned long flags;
1223 spin_lock_irqsave(&vector_lock, flags);
1224 err = __assign_irq_vector(irq, mask);
1225 spin_unlock_irqrestore(&vector_lock, flags);
1230 static void __clear_irq_vector(int irq)
1232 struct irq_cfg *cfg;
1237 BUG_ON(!cfg->vector);
1239 vector = cfg->vector;
1240 cpus_and(mask, cfg->domain, cpu_online_map);
1241 for_each_cpu_mask_nr(cpu, mask)
1242 per_cpu(vector_irq, cpu)[vector] = -1;
1245 cpus_clear(cfg->domain);
1248 void __setup_vector_irq(int cpu)
1250 /* Initialize vector_irq on a new cpu */
1251 /* This function must be called with vector_lock held */
1253 struct irq_cfg *cfg;
1255 /* Mark the inuse vectors */
1256 for_each_irq_cfg(cfg) {
1257 if (!cpu_isset(cpu, cfg->domain))
1259 vector = cfg->vector;
1261 per_cpu(vector_irq, cpu)[vector] = irq;
1263 /* Mark the free vectors */
1264 for (vector = 0; vector < NR_VECTORS; ++vector) {
1265 irq = per_cpu(vector_irq, cpu)[vector];
1270 if (!cpu_isset(cpu, cfg->domain))
1271 per_cpu(vector_irq, cpu)[vector] = -1;
1275 static struct irq_chip ioapic_chip;
1277 #define IOAPIC_AUTO -1
1278 #define IOAPIC_EDGE 0
1279 #define IOAPIC_LEVEL 1
1281 #ifdef CONFIG_X86_32
1282 static inline int IO_APIC_irq_trigger(int irq)
1286 for (apic = 0; apic < nr_ioapics; apic++) {
1287 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1288 idx = find_irq_entry(apic, pin, mp_INT);
1289 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1290 return irq_trigger(idx);
1294 * nonexistent IRQs are edge default
1299 static inline int IO_APIC_irq_trigger(int irq)
1305 static void ioapic_register_intr(int irq, unsigned long trigger)
1307 struct irq_desc *desc;
1309 /* first time to use this irq_desc */
1311 desc = irq_to_desc(irq);
1313 desc = irq_to_desc_alloc(irq);
1315 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1316 trigger == IOAPIC_LEVEL)
1317 desc->status |= IRQ_LEVEL;
1319 desc->status &= ~IRQ_LEVEL;
1321 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1322 trigger == IOAPIC_LEVEL)
1323 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1324 handle_fasteoi_irq, "fasteoi");
1326 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1327 handle_edge_irq, "edge");
1330 static int setup_ioapic_entry(int apic, int irq,
1331 struct IO_APIC_route_entry *entry,
1332 unsigned int destination, int trigger,
1333 int polarity, int vector)
1336 * add it to the IO-APIC irq-routing table:
1338 memset(entry,0,sizeof(*entry));
1340 entry->delivery_mode = INT_DELIVERY_MODE;
1341 entry->dest_mode = INT_DEST_MODE;
1342 entry->dest = destination;
1344 entry->mask = 0; /* enable IRQ */
1345 entry->trigger = trigger;
1346 entry->polarity = polarity;
1347 entry->vector = vector;
1349 /* Mask level triggered irqs.
1350 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1358 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1359 int trigger, int polarity)
1361 struct irq_cfg *cfg;
1362 struct IO_APIC_route_entry entry;
1365 if (!IO_APIC_IRQ(irq))
1371 if (assign_irq_vector(irq, mask))
1374 cpus_and(mask, cfg->domain, mask);
1376 apic_printk(APIC_VERBOSE,KERN_DEBUG
1377 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1378 "IRQ %d Mode:%i Active:%i)\n",
1379 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1380 irq, trigger, polarity);
1383 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1384 cpu_mask_to_apicid(mask), trigger, polarity,
1386 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1387 mp_ioapics[apic].mp_apicid, pin);
1388 __clear_irq_vector(irq);
1392 ioapic_register_intr(irq, trigger);
1394 disable_8259A_irq(irq);
1396 ioapic_write_entry(apic, pin, entry);
1399 static void __init setup_IO_APIC_irqs(void)
1401 int apic, pin, idx, irq, first_notcon = 1;
1403 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1405 for (apic = 0; apic < nr_ioapics; apic++) {
1406 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1408 idx = find_irq_entry(apic,pin,mp_INT);
1411 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1414 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1417 if (!first_notcon) {
1418 apic_printk(APIC_VERBOSE, " not connected.\n");
1422 irq = pin_2_irq(idx, apic, pin);
1424 if (multi_timer_check(apic, irq))
1427 add_pin_to_irq(irq, apic, pin);
1429 setup_IO_APIC_irq(apic, pin, irq,
1430 irq_trigger(idx), irq_polarity(idx));
1435 apic_printk(APIC_VERBOSE, " not connected.\n");
1439 * Set up the timer pin, possibly with the 8259A-master behind.
1441 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1444 struct IO_APIC_route_entry entry;
1446 memset(&entry, 0, sizeof(entry));
1449 * We use logical delivery to get the timer IRQ
1452 entry.dest_mode = INT_DEST_MODE;
1453 entry.mask = 1; /* mask IRQ now */
1454 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1455 entry.delivery_mode = INT_DELIVERY_MODE;
1458 entry.vector = vector;
1461 * The timer IRQ doesn't have to know that behind the
1462 * scene we may have a 8259A-master in AEOI mode ...
1464 ioapic_register_intr(0, IOAPIC_EDGE);
1467 * Add it to the IO-APIC irq-routing table:
1469 ioapic_write_entry(apic, pin, entry);
1473 __apicdebuginit(void) print_IO_APIC(void)
1476 union IO_APIC_reg_00 reg_00;
1477 union IO_APIC_reg_01 reg_01;
1478 union IO_APIC_reg_02 reg_02;
1479 union IO_APIC_reg_03 reg_03;
1480 unsigned long flags;
1481 struct irq_cfg *cfg;
1483 if (apic_verbosity == APIC_QUIET)
1486 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1487 for (i = 0; i < nr_ioapics; i++)
1488 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1489 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1492 * We are a bit conservative about what we expect. We have to
1493 * know about every hardware change ASAP.
1495 printk(KERN_INFO "testing the IO APIC.......................\n");
1497 for (apic = 0; apic < nr_ioapics; apic++) {
1499 spin_lock_irqsave(&ioapic_lock, flags);
1500 reg_00.raw = io_apic_read(apic, 0);
1501 reg_01.raw = io_apic_read(apic, 1);
1502 if (reg_01.bits.version >= 0x10)
1503 reg_02.raw = io_apic_read(apic, 2);
1504 if (reg_01.bits.version >= 0x20)
1505 reg_03.raw = io_apic_read(apic, 3);
1506 spin_unlock_irqrestore(&ioapic_lock, flags);
1508 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1509 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1510 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1511 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1512 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1514 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1515 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1517 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1518 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1521 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1522 * but the value of reg_02 is read as the previous read register
1523 * value, so ignore it if reg_02 == reg_01.
1525 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1526 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1527 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1531 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1532 * or reg_03, but the value of reg_0[23] is read as the previous read
1533 * register value, so ignore it if reg_03 == reg_0[12].
1535 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1536 reg_03.raw != reg_01.raw) {
1537 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1538 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1541 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1543 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1544 " Stat Dmod Deli Vect: \n");
1546 for (i = 0; i <= reg_01.bits.entries; i++) {
1547 struct IO_APIC_route_entry entry;
1549 entry = ioapic_read_entry(apic, i);
1551 printk(KERN_DEBUG " %02x %02X ", i, entry.dest);
1553 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1558 entry.delivery_status,
1560 entry.delivery_mode,
1565 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1566 for_each_irq_cfg(cfg) {
1567 struct irq_pin_list *entry = cfg->irq_2_pin;
1570 printk(KERN_DEBUG "IRQ%d ", i);
1572 printk("-> %d:%d", entry->apic, entry->pin);
1575 entry = entry->next;
1580 printk(KERN_INFO ".................................... done.\n");
1585 __apicdebuginit(void) print_APIC_bitfield(int base)
1590 if (apic_verbosity == APIC_QUIET)
1593 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1594 for (i = 0; i < 8; i++) {
1595 v = apic_read(base + i*0x10);
1596 for (j = 0; j < 32; j++) {
1606 __apicdebuginit(void) print_local_APIC(void *dummy)
1608 unsigned int v, ver, maxlvt;
1611 if (apic_verbosity == APIC_QUIET)
1614 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1615 smp_processor_id(), hard_smp_processor_id());
1616 v = apic_read(APIC_ID);
1617 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v,
1619 v = apic_read(APIC_LVR);
1620 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1621 ver = GET_APIC_VERSION(v);
1622 maxlvt = lapic_get_maxlvt();
1624 v = apic_read(APIC_TASKPRI);
1625 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1627 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1628 v = apic_read(APIC_ARBPRI);
1629 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1630 v & APIC_ARBPRI_MASK);
1631 v = apic_read(APIC_PROCPRI);
1632 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1635 v = apic_read(APIC_EOI);
1636 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1637 v = apic_read(APIC_RRR);
1638 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1639 v = apic_read(APIC_LDR);
1640 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1641 v = apic_read(APIC_DFR);
1642 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1643 v = apic_read(APIC_SPIV);
1644 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1646 printk(KERN_DEBUG "... APIC ISR field:\n");
1647 print_APIC_bitfield(APIC_ISR);
1648 printk(KERN_DEBUG "... APIC TMR field:\n");
1649 print_APIC_bitfield(APIC_TMR);
1650 printk(KERN_DEBUG "... APIC IRR field:\n");
1651 print_APIC_bitfield(APIC_IRR);
1653 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1654 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1655 apic_write(APIC_ESR, 0);
1656 v = apic_read(APIC_ESR);
1657 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1660 icr = apic_icr_read();
1661 printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
1662 printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
1664 v = apic_read(APIC_LVTT);
1665 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1667 if (maxlvt > 3) { /* PC is LVT#4. */
1668 v = apic_read(APIC_LVTPC);
1669 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1671 v = apic_read(APIC_LVT0);
1672 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1673 v = apic_read(APIC_LVT1);
1674 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1676 if (maxlvt > 2) { /* ERR is LVT#3. */
1677 v = apic_read(APIC_LVTERR);
1678 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1681 v = apic_read(APIC_TMICT);
1682 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1683 v = apic_read(APIC_TMCCT);
1684 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1685 v = apic_read(APIC_TDCR);
1686 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1690 __apicdebuginit(void) print_all_local_APICs(void)
1692 on_each_cpu(print_local_APIC, NULL, 1);
1695 __apicdebuginit(void) print_PIC(void)
1698 unsigned long flags;
1700 if (apic_verbosity == APIC_QUIET)
1703 printk(KERN_DEBUG "\nprinting PIC contents\n");
1705 spin_lock_irqsave(&i8259A_lock, flags);
1707 v = inb(0xa1) << 8 | inb(0x21);
1708 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1710 v = inb(0xa0) << 8 | inb(0x20);
1711 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1715 v = inb(0xa0) << 8 | inb(0x20);
1719 spin_unlock_irqrestore(&i8259A_lock, flags);
1721 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1723 v = inb(0x4d1) << 8 | inb(0x4d0);
1724 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1727 __apicdebuginit(int) print_all_ICs(void)
1730 print_all_local_APICs();
1736 fs_initcall(print_all_ICs);
1739 /* Where if anywhere is the i8259 connect in external int mode */
1740 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1742 static void __init enable_IO_APIC(void)
1744 union IO_APIC_reg_01 reg_01;
1745 int i8259_apic, i8259_pin;
1747 unsigned long flags;
1750 for (i = 0; i < MAX_PIRQS; i++)
1751 pirq_entries[i] = -1;
1754 * The number of IO-APIC IRQ registers (== #pins):
1756 for (apic = 0; apic < nr_ioapics; apic++) {
1757 spin_lock_irqsave(&ioapic_lock, flags);
1758 reg_01.raw = io_apic_read(apic, 1);
1759 spin_unlock_irqrestore(&ioapic_lock, flags);
1760 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1762 for (apic = 0; apic < nr_ioapics; apic++) {
1764 /* See if any of the pins is in ExtINT mode */
1765 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1766 struct IO_APIC_route_entry entry;
1767 entry = ioapic_read_entry(apic, pin);
1769 /* If the interrupt line is enabled and in ExtInt mode
1770 * I have found the pin where the i8259 is connected.
1772 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1773 ioapic_i8259.apic = apic;
1774 ioapic_i8259.pin = pin;
1780 /* Look to see what if the MP table has reported the ExtINT */
1781 /* If we could not find the appropriate pin by looking at the ioapic
1782 * the i8259 probably is not connected the ioapic but give the
1783 * mptable a chance anyway.
1785 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1786 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1787 /* Trust the MP table if nothing is setup in the hardware */
1788 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1789 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1790 ioapic_i8259.pin = i8259_pin;
1791 ioapic_i8259.apic = i8259_apic;
1793 /* Complain if the MP table and the hardware disagree */
1794 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1795 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1797 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1801 * Do not trust the IO-APIC being empty at bootup
1807 * Not an __init, needed by the reboot code
1809 void disable_IO_APIC(void)
1812 * Clear the IO-APIC before rebooting:
1817 * If the i8259 is routed through an IOAPIC
1818 * Put that IOAPIC in virtual wire mode
1819 * so legacy interrupts can be delivered.
1821 if (ioapic_i8259.pin != -1) {
1822 struct IO_APIC_route_entry entry;
1824 memset(&entry, 0, sizeof(entry));
1825 entry.mask = 0; /* Enabled */
1826 entry.trigger = 0; /* Edge */
1828 entry.polarity = 0; /* High */
1829 entry.delivery_status = 0;
1830 entry.dest_mode = 0; /* Physical */
1831 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1833 entry.dest = read_apic_id();
1836 * Add it to the IO-APIC irq-routing table:
1838 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1840 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1844 * function to set the IO-APIC physical IDs based on the
1845 * values stored in the MPC table.
1847 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1850 static void __init setup_ioapic_ids_from_mpc(void)
1852 union IO_APIC_reg_00 reg_00;
1853 physid_mask_t phys_id_present_map;
1856 unsigned char old_id;
1857 unsigned long flags;
1859 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1863 * Don't check I/O APIC IDs for xAPIC systems. They have
1864 * no meaning without the serial APIC bus.
1866 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1867 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1870 * This is broken; anything with a real cpu count has to
1871 * circumvent this idiocy regardless.
1873 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1876 * Set the IOAPIC ID to the value stored in the MPC table.
1878 for (apic = 0; apic < nr_ioapics; apic++) {
1880 /* Read the register 0 value */
1881 spin_lock_irqsave(&ioapic_lock, flags);
1882 reg_00.raw = io_apic_read(apic, 0);
1883 spin_unlock_irqrestore(&ioapic_lock, flags);
1885 old_id = mp_ioapics[apic].mp_apicid;
1887 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1888 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1889 apic, mp_ioapics[apic].mp_apicid);
1890 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1892 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1896 * Sanity check, is the ID really free? Every APIC in a
1897 * system must have a unique ID or we get lots of nice
1898 * 'stuck on smp_invalidate_needed IPI wait' messages.
1900 if (check_apicid_used(phys_id_present_map,
1901 mp_ioapics[apic].mp_apicid)) {
1902 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1903 apic, mp_ioapics[apic].mp_apicid);
1904 for (i = 0; i < get_physical_broadcast(); i++)
1905 if (!physid_isset(i, phys_id_present_map))
1907 if (i >= get_physical_broadcast())
1908 panic("Max APIC ID exceeded!\n");
1909 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1911 physid_set(i, phys_id_present_map);
1912 mp_ioapics[apic].mp_apicid = i;
1915 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1916 apic_printk(APIC_VERBOSE, "Setting %d in the "
1917 "phys_id_present_map\n",
1918 mp_ioapics[apic].mp_apicid);
1919 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1924 * We need to adjust the IRQ routing table
1925 * if the ID changed.
1927 if (old_id != mp_ioapics[apic].mp_apicid)
1928 for (i = 0; i < mp_irq_entries; i++)
1929 if (mp_irqs[i].mp_dstapic == old_id)
1930 mp_irqs[i].mp_dstapic
1931 = mp_ioapics[apic].mp_apicid;
1934 * Read the right value from the MPC table and
1935 * write it into the ID register.
1937 apic_printk(APIC_VERBOSE, KERN_INFO
1938 "...changing IO-APIC physical APIC ID to %d ...",
1939 mp_ioapics[apic].mp_apicid);
1941 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1942 spin_lock_irqsave(&ioapic_lock, flags);
1943 io_apic_write(apic, 0, reg_00.raw);
1944 spin_unlock_irqrestore(&ioapic_lock, flags);
1949 spin_lock_irqsave(&ioapic_lock, flags);
1950 reg_00.raw = io_apic_read(apic, 0);
1951 spin_unlock_irqrestore(&ioapic_lock, flags);
1952 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1953 printk("could not set ID!\n");
1955 apic_printk(APIC_VERBOSE, " ok.\n");
1959 int no_timer_check __initdata;
1961 static int __init notimercheck(char *s)
1966 __setup("no_timer_check", notimercheck);
1969 * There is a nasty bug in some older SMP boards, their mptable lies
1970 * about the timer IRQ. We do the following to work around the situation:
1972 * - timer IRQ defaults to IO-APIC IRQ
1973 * - if this function detects that timer IRQs are defunct, then we fall
1974 * back to ISA timer IRQs
1976 static int __init timer_irq_works(void)
1978 unsigned long t1 = jiffies;
1979 unsigned long flags;
1984 local_save_flags(flags);
1986 /* Let ten ticks pass... */
1987 mdelay((10 * 1000) / HZ);
1988 local_irq_restore(flags);
1991 * Expect a few ticks at least, to be sure some possible
1992 * glue logic does not lock up after one or two first
1993 * ticks in a non-ExtINT mode. Also the local APIC
1994 * might have cached one ExtINT interrupt. Finally, at
1995 * least one tick may be lost due to delays.
1997 if (time_after(jiffies, t1 + 4))
2004 * In the SMP+IOAPIC case it might happen that there are an unspecified
2005 * number of pending IRQ events unhandled. These cases are very rare,
2006 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2007 * better to do it this way as thus we do not have to be aware of
2008 * 'pending' interrupts in the IRQ path, except at this point.
2011 * Edge triggered needs to resend any interrupt
2012 * that was delayed but this is now handled in the device
2019 * Starting up a edge-triggered IO-APIC interrupt is
2020 * nasty - we need to make sure that we get the edge.
2021 * If it is already asserted for some reason, we need
2022 * return 1 to indicate that is was pending.
2024 * This is not complete - we should be able to fake
2025 * an edge even if it isn't on the 8259A...
2027 * (We do this for level-triggered IRQs too - it cannot hurt.)
2029 static unsigned int startup_ioapic_irq(unsigned int irq)
2031 int was_pending = 0;
2032 unsigned long flags;
2034 spin_lock_irqsave(&ioapic_lock, flags);
2036 disable_8259A_irq(irq);
2037 if (i8259A_irq_pending(irq))
2040 __unmask_IO_APIC_irq(irq);
2041 spin_unlock_irqrestore(&ioapic_lock, flags);
2046 static int ioapic_retrigger_irq(unsigned int irq)
2048 send_IPI_self(irq_cfg(irq)->vector);
2054 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2056 unsigned vector, me;
2060 me = smp_processor_id();
2061 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2063 struct irq_desc *desc;
2064 struct irq_cfg *cfg;
2065 irq = __get_cpu_var(vector_irq)[vector];
2067 desc = irq_to_desc(irq);
2072 spin_lock(&desc->lock);
2073 if (!cfg->move_cleanup_count)
2076 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2079 __get_cpu_var(vector_irq)[vector] = -1;
2080 cfg->move_cleanup_count--;
2082 spin_unlock(&desc->lock);
2088 static void irq_complete_move(unsigned int irq)
2090 struct irq_cfg *cfg = irq_cfg(irq);
2091 unsigned vector, me;
2093 if (likely(!cfg->move_in_progress))
2096 vector = ~get_irq_regs()->orig_ax;
2097 me = smp_processor_id();
2098 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2099 cpumask_t cleanup_mask;
2101 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2102 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2103 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2104 cfg->move_in_progress = 0;
2108 static inline void irq_complete_move(unsigned int irq) {}
2111 static void ack_apic_edge(unsigned int irq)
2113 irq_complete_move(irq);
2114 move_native_irq(irq);
2118 #ifdef CONFIG_X86_64
2119 static void ack_apic_level(unsigned int irq)
2121 int do_unmask_irq = 0;
2123 irq_complete_move(irq);
2124 #ifdef CONFIG_GENERIC_PENDING_IRQ
2125 /* If we are moving the irq we need to mask it */
2126 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2128 mask_IO_APIC_irq(irq);
2133 * We must acknowledge the irq before we move it or the acknowledge will
2134 * not propagate properly.
2138 /* Now we can move and renable the irq */
2139 if (unlikely(do_unmask_irq)) {
2140 /* Only migrate the irq if the ack has been received.
2142 * On rare occasions the broadcast level triggered ack gets
2143 * delayed going to ioapics, and if we reprogram the
2144 * vector while Remote IRR is still set the irq will never
2147 * To prevent this scenario we read the Remote IRR bit
2148 * of the ioapic. This has two effects.
2149 * - On any sane system the read of the ioapic will
2150 * flush writes (and acks) going to the ioapic from
2152 * - We get to see if the ACK has actually been delivered.
2154 * Based on failed experiments of reprogramming the
2155 * ioapic entry from outside of irq context starting
2156 * with masking the ioapic entry and then polling until
2157 * Remote IRR was clear before reprogramming the
2158 * ioapic I don't trust the Remote IRR bit to be
2159 * completey accurate.
2161 * However there appears to be no other way to plug
2162 * this race, so if the Remote IRR bit is not
2163 * accurate and is causing problems then it is a hardware bug
2164 * and you can go talk to the chipset vendor about it.
2166 if (!io_apic_level_ack_pending(irq))
2167 move_masked_irq(irq, desc);
2168 unmask_IO_APIC_irq(irq);
2172 atomic_t irq_mis_count;
2173 static void ack_apic_level(unsigned int irq)
2178 irq_complete_move(irq);
2179 move_native_irq(irq);
2181 * It appears there is an erratum which affects at least version 0x11
2182 * of I/O APIC (that's the 82093AA and cores integrated into various
2183 * chipsets). Under certain conditions a level-triggered interrupt is
2184 * erroneously delivered as edge-triggered one but the respective IRR
2185 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2186 * message but it will never arrive and further interrupts are blocked
2187 * from the source. The exact reason is so far unknown, but the
2188 * phenomenon was observed when two consecutive interrupt requests
2189 * from a given source get delivered to the same CPU and the source is
2190 * temporarily disabled in between.
2192 * A workaround is to simulate an EOI message manually. We achieve it
2193 * by setting the trigger mode to edge and then to level when the edge
2194 * trigger mode gets detected in the TMR of a local APIC for a
2195 * level-triggered interrupt. We mask the source for the time of the
2196 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2197 * The idea is from Manfred Spraul. --macro
2199 i = irq_cfg(irq)->vector;
2201 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2205 if (!(v & (1 << (i & 0x1f)))) {
2206 atomic_inc(&irq_mis_count);
2207 spin_lock(&ioapic_lock);
2208 __mask_and_edge_IO_APIC_irq(irq);
2209 __unmask_and_level_IO_APIC_irq(irq);
2210 spin_unlock(&ioapic_lock);
2215 static struct irq_chip ioapic_chip __read_mostly = {
2217 .startup = startup_ioapic_irq,
2218 .mask = mask_IO_APIC_irq,
2219 .unmask = unmask_IO_APIC_irq,
2220 .ack = ack_apic_edge,
2221 .eoi = ack_apic_level,
2223 .set_affinity = set_ioapic_affinity_irq,
2225 .retrigger = ioapic_retrigger_irq,
2229 static inline void init_IO_APIC_traps(void)
2232 struct irq_desc *desc;
2233 struct irq_cfg *cfg;
2236 * NOTE! The local APIC isn't very good at handling
2237 * multiple interrupts at the same interrupt level.
2238 * As the interrupt level is determined by taking the
2239 * vector number and shifting that right by 4, we
2240 * want to spread these out a bit so that they don't
2241 * all fall in the same interrupt level.
2243 * Also, we've got to be careful not to trash gate
2244 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2246 for_each_irq_cfg(cfg) {
2248 if (IO_APIC_IRQ(irq) && !cfg->vector) {
2250 * Hmm.. We don't have an entry for this,
2251 * so default to an old-fashioned 8259
2252 * interrupt if we can..
2255 make_8259A_irq(irq);
2257 desc = irq_to_desc(irq);
2258 /* Strange. Oh, well.. */
2259 desc->chip = &no_irq_chip;
2266 * The local APIC irq-chip implementation:
2269 static void mask_lapic_irq(unsigned int irq)
2273 v = apic_read(APIC_LVT0);
2274 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2277 static void unmask_lapic_irq(unsigned int irq)
2281 v = apic_read(APIC_LVT0);
2282 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2285 static void ack_lapic_irq(unsigned int irq)
2290 static struct irq_chip lapic_chip __read_mostly = {
2291 .name = "local-APIC",
2292 .mask = mask_lapic_irq,
2293 .unmask = unmask_lapic_irq,
2294 .ack = ack_lapic_irq,
2297 static void lapic_register_intr(int irq)
2299 struct irq_desc *desc;
2301 desc = irq_to_desc(irq);
2302 desc->status &= ~IRQ_LEVEL;
2303 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2307 static void __init setup_nmi(void)
2310 * Dirty trick to enable the NMI watchdog ...
2311 * We put the 8259A master into AEOI mode and
2312 * unmask on all local APICs LVT0 as NMI.
2314 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2315 * is from Maciej W. Rozycki - so we do not have to EOI from
2316 * the NMI handler or the timer interrupt.
2318 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2320 enable_NMI_through_LVT0();
2322 apic_printk(APIC_VERBOSE, " done.\n");
2326 * This looks a bit hackish but it's about the only one way of sending
2327 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2328 * not support the ExtINT mode, unfortunately. We need to send these
2329 * cycles as some i82489DX-based boards have glue logic that keeps the
2330 * 8259A interrupt line asserted until INTA. --macro
2332 static inline void __init unlock_ExtINT_logic(void)
2335 struct IO_APIC_route_entry entry0, entry1;
2336 unsigned char save_control, save_freq_select;
2338 pin = find_isa_irq_pin(8, mp_INT);
2343 apic = find_isa_irq_apic(8, mp_INT);
2349 entry0 = ioapic_read_entry(apic, pin);
2350 clear_IO_APIC_pin(apic, pin);
2352 memset(&entry1, 0, sizeof(entry1));
2354 entry1.dest_mode = 0; /* physical delivery */
2355 entry1.mask = 0; /* unmask IRQ now */
2356 entry1.dest = hard_smp_processor_id();
2357 entry1.delivery_mode = dest_ExtINT;
2358 entry1.polarity = entry0.polarity;
2362 ioapic_write_entry(apic, pin, entry1);
2364 save_control = CMOS_READ(RTC_CONTROL);
2365 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2366 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2368 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2373 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2377 CMOS_WRITE(save_control, RTC_CONTROL);
2378 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2379 clear_IO_APIC_pin(apic, pin);
2381 ioapic_write_entry(apic, pin, entry0);
2384 static int disable_timer_pin_1 __initdata;
2385 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2386 static int __init parse_disable_timer_pin_1(char *arg)
2388 disable_timer_pin_1 = 1;
2391 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2393 int timer_through_8259 __initdata;
2396 * This code may look a bit paranoid, but it's supposed to cooperate with
2397 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2398 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2399 * fanatically on his truly buggy board.
2401 static inline void __init check_timer(void)
2403 struct irq_cfg *cfg = irq_cfg(0);
2404 int apic1, pin1, apic2, pin2;
2405 unsigned long flags;
2409 local_irq_save(flags);
2411 ver = apic_read(APIC_LVR);
2412 ver = GET_APIC_VERSION(ver);
2415 * get/set the timer IRQ vector:
2417 disable_8259A_irq(0);
2418 assign_irq_vector(0, TARGET_CPUS);
2421 * As IRQ0 is to be enabled in the 8259A, the virtual
2422 * wire has to be disabled in the local APIC. Also
2423 * timer interrupts need to be acknowledged manually in
2424 * the 8259A for the i82489DX when using the NMI
2425 * watchdog as that APIC treats NMIs as level-triggered.
2426 * The AEOI mode will finish them in the 8259A
2429 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2431 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2433 pin1 = find_isa_irq_pin(0, mp_INT);
2434 apic1 = find_isa_irq_apic(0, mp_INT);
2435 pin2 = ioapic_i8259.pin;
2436 apic2 = ioapic_i8259.apic;
2438 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2439 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2440 cfg->vector, apic1, pin1, apic2, pin2);
2443 * Some BIOS writers are clueless and report the ExtINTA
2444 * I/O APIC input from the cascaded 8259A as the timer
2445 * interrupt input. So just in case, if only one pin
2446 * was found above, try it both directly and through the
2453 } else if (pin2 == -1) {
2460 * Ok, does IRQ0 through the IOAPIC work?
2463 add_pin_to_irq(0, apic1, pin1);
2464 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2466 unmask_IO_APIC_irq(0);
2467 if (timer_irq_works()) {
2468 if (nmi_watchdog == NMI_IO_APIC) {
2470 enable_8259A_irq(0);
2472 if (disable_timer_pin_1 > 0)
2473 clear_IO_APIC_pin(0, pin1);
2476 clear_IO_APIC_pin(apic1, pin1);
2478 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2479 "8254 timer not connected to IO-APIC\n");
2481 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2482 "(IRQ0) through the 8259A ...\n");
2483 apic_printk(APIC_QUIET, KERN_INFO
2484 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2486 * legacy devices should be connected to IO APIC #0
2488 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2489 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2490 unmask_IO_APIC_irq(0);
2491 enable_8259A_irq(0);
2492 if (timer_irq_works()) {
2493 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2494 timer_through_8259 = 1;
2495 if (nmi_watchdog == NMI_IO_APIC) {
2496 disable_8259A_irq(0);
2498 enable_8259A_irq(0);
2503 * Cleanup, just in case ...
2505 disable_8259A_irq(0);
2506 clear_IO_APIC_pin(apic2, pin2);
2507 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2510 if (nmi_watchdog == NMI_IO_APIC) {
2511 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2512 "through the IO-APIC - disabling NMI Watchdog!\n");
2513 nmi_watchdog = NMI_NONE;
2517 apic_printk(APIC_QUIET, KERN_INFO
2518 "...trying to set up timer as Virtual Wire IRQ...\n");
2520 lapic_register_intr(0);
2521 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2522 enable_8259A_irq(0);
2524 if (timer_irq_works()) {
2525 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2528 disable_8259A_irq(0);
2529 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2530 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2532 apic_printk(APIC_QUIET, KERN_INFO
2533 "...trying to set up timer as ExtINT IRQ...\n");
2537 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2539 unlock_ExtINT_logic();
2541 if (timer_irq_works()) {
2542 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2545 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2546 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2547 "report. Then try booting with the 'noapic' option.\n");
2549 local_irq_restore(flags);
2553 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2554 * to devices. However there may be an I/O APIC pin available for
2555 * this interrupt regardless. The pin may be left unconnected, but
2556 * typically it will be reused as an ExtINT cascade interrupt for
2557 * the master 8259A. In the MPS case such a pin will normally be
2558 * reported as an ExtINT interrupt in the MP table. With ACPI
2559 * there is no provision for ExtINT interrupts, and in the absence
2560 * of an override it would be treated as an ordinary ISA I/O APIC
2561 * interrupt, that is edge-triggered and unmasked by default. We
2562 * used to do this, but it caused problems on some systems because
2563 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2564 * the same ExtINT cascade interrupt to drive the local APIC of the
2565 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2566 * the I/O APIC in all cases now. No actual device should request
2567 * it anyway. --macro
2569 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2571 void __init setup_IO_APIC(void)
2575 io_apic_irqs = ~PIC_IRQS;
2577 printk("ENABLING IO-APIC IRQs\n");
2580 * Set up IO-APIC IRQ routing.
2583 setup_ioapic_ids_from_mpc();
2585 setup_IO_APIC_irqs();
2586 init_IO_APIC_traps();
2591 * Called after all the initialization is done. If we didnt find any
2592 * APIC bugs then we can allow the modify fast path
2595 static int __init io_apic_bug_finalize(void)
2597 if (sis_apic_bug == -1)
2602 late_initcall(io_apic_bug_finalize);
2604 struct sysfs_ioapic_data {
2605 struct sys_device dev;
2606 struct IO_APIC_route_entry entry[0];
2608 static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
2610 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2612 struct IO_APIC_route_entry *entry;
2613 struct sysfs_ioapic_data *data;
2616 data = container_of(dev, struct sysfs_ioapic_data, dev);
2617 entry = data->entry;
2618 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2619 entry[i] = ioapic_read_entry(dev->id, i);
2624 static int ioapic_resume(struct sys_device *dev)
2626 struct IO_APIC_route_entry *entry;
2627 struct sysfs_ioapic_data *data;
2628 unsigned long flags;
2629 union IO_APIC_reg_00 reg_00;
2632 data = container_of(dev, struct sysfs_ioapic_data, dev);
2633 entry = data->entry;
2635 spin_lock_irqsave(&ioapic_lock, flags);
2636 reg_00.raw = io_apic_read(dev->id, 0);
2637 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2638 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2639 io_apic_write(dev->id, 0, reg_00.raw);
2641 spin_unlock_irqrestore(&ioapic_lock, flags);
2642 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2643 ioapic_write_entry(dev->id, i, entry[i]);
2648 static struct sysdev_class ioapic_sysdev_class = {
2650 .suspend = ioapic_suspend,
2651 .resume = ioapic_resume,
2654 static int __init ioapic_init_sysfs(void)
2656 struct sys_device *dev;
2657 int i, size, error = 0;
2659 error = sysdev_class_register(&ioapic_sysdev_class);
2663 for (i = 0; i < nr_ioapics; i++) {
2664 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2665 * sizeof(struct IO_APIC_route_entry);
2666 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2667 if (!mp_ioapic_data[i]) {
2668 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2671 dev = &mp_ioapic_data[i]->dev;
2673 dev->cls = &ioapic_sysdev_class;
2674 error = sysdev_register(dev);
2676 kfree(mp_ioapic_data[i]);
2677 mp_ioapic_data[i] = NULL;
2678 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2686 device_initcall(ioapic_init_sysfs);
2689 * Dynamic irq allocate and deallocation
2691 unsigned int create_irq_nr(unsigned int irq_want)
2693 /* Allocate an unused irq */
2694 unsigned int irq, new;
2695 unsigned long flags;
2696 struct irq_cfg *cfg_new;
2698 #ifndef CONFIG_HAVE_SPARSE_IRQ
2699 /* only can use bus/dev/fn.. when per_cpu vector is used */
2700 irq_want = nr_irqs - 1;
2704 spin_lock_irqsave(&vector_lock, flags);
2705 for (new = (nr_irqs - 1); new > 0; new--) {
2706 if (platform_legacy_irq(new))
2708 cfg_new = irq_cfg(new);
2709 if (cfg_new && cfg_new->vector != 0)
2711 /* check if need to create one */
2713 cfg_new = irq_cfg_alloc(new);
2714 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
2718 spin_unlock_irqrestore(&vector_lock, flags);
2721 dynamic_irq_init(irq);
2726 int create_irq(void)
2728 return create_irq_nr(nr_irqs - 1);
2731 void destroy_irq(unsigned int irq)
2733 unsigned long flags;
2735 dynamic_irq_cleanup(irq);
2737 spin_lock_irqsave(&vector_lock, flags);
2738 __clear_irq_vector(irq);
2739 spin_unlock_irqrestore(&vector_lock, flags);
2743 * MSI message composition
2745 #ifdef CONFIG_PCI_MSI
2746 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2748 struct irq_cfg *cfg;
2754 err = assign_irq_vector(irq, tmp);
2759 cpus_and(tmp, cfg->domain, tmp);
2760 dest = cpu_mask_to_apicid(tmp);
2762 msg->address_hi = MSI_ADDR_BASE_HI;
2765 ((INT_DEST_MODE == 0) ?
2766 MSI_ADDR_DEST_MODE_PHYSICAL:
2767 MSI_ADDR_DEST_MODE_LOGICAL) |
2768 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2769 MSI_ADDR_REDIRECTION_CPU:
2770 MSI_ADDR_REDIRECTION_LOWPRI) |
2771 MSI_ADDR_DEST_ID(dest);
2774 MSI_DATA_TRIGGER_EDGE |
2775 MSI_DATA_LEVEL_ASSERT |
2776 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2777 MSI_DATA_DELIVERY_FIXED:
2778 MSI_DATA_DELIVERY_LOWPRI) |
2779 MSI_DATA_VECTOR(cfg->vector);
2785 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2787 struct irq_cfg *cfg;
2792 cpus_and(tmp, mask, cpu_online_map);
2793 if (cpus_empty(tmp))
2796 if (assign_irq_vector(irq, mask))
2800 cpus_and(tmp, cfg->domain, mask);
2801 dest = cpu_mask_to_apicid(tmp);
2803 read_msi_msg(irq, &msg);
2805 msg.data &= ~MSI_DATA_VECTOR_MASK;
2806 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2807 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2808 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2810 write_msi_msg(irq, &msg);
2811 irq_to_desc(irq)->affinity = mask;
2813 #endif /* CONFIG_SMP */
2816 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2817 * which implement the MSI or MSI-X Capability Structure.
2819 static struct irq_chip msi_chip = {
2821 .unmask = unmask_msi_irq,
2822 .mask = mask_msi_irq,
2823 .ack = ack_apic_edge,
2825 .set_affinity = set_msi_irq_affinity,
2827 .retrigger = ioapic_retrigger_irq,
2831 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
2836 ret = msi_compose_msg(dev, irq, &msg);
2840 set_irq_msi(irq, desc);
2841 write_msi_msg(irq, &msg);
2843 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2848 static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
2852 irq = dev->bus->number;
2860 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2864 unsigned int irq_want;
2866 irq_want = build_irq_for_pci_dev(dev) + 0x100;
2868 irq = create_irq_nr(irq_want);
2873 ret = setup_msi_irq(dev, desc, irq);
2882 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
2885 int ret, sub_handle;
2886 struct msi_desc *desc;
2887 unsigned int irq_want;
2889 irq_want = build_irq_for_pci_dev(dev) + 0x100;
2891 list_for_each_entry(desc, &dev->msi_list, list) {
2892 irq = create_irq_nr(irq_want--);
2895 ret = setup_msi_irq(dev, desc, irq);
2908 void arch_teardown_msi_irq(unsigned int irq)
2913 #endif /* CONFIG_PCI_MSI */
2916 * Hypertransport interrupt support
2918 #ifdef CONFIG_HT_IRQ
2922 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2924 struct ht_irq_msg msg;
2925 fetch_ht_irq_msg(irq, &msg);
2927 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2928 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2930 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2931 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2933 write_ht_irq_msg(irq, &msg);
2936 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2938 struct irq_cfg *cfg;
2942 cpus_and(tmp, mask, cpu_online_map);
2943 if (cpus_empty(tmp))
2946 if (assign_irq_vector(irq, mask))
2950 cpus_and(tmp, cfg->domain, mask);
2951 dest = cpu_mask_to_apicid(tmp);
2953 target_ht_irq(irq, dest, cfg->vector);
2954 irq_to_desc(irq)->affinity = mask;
2958 static struct irq_chip ht_irq_chip = {
2960 .mask = mask_ht_irq,
2961 .unmask = unmask_ht_irq,
2962 .ack = ack_apic_edge,
2964 .set_affinity = set_ht_irq_affinity,
2966 .retrigger = ioapic_retrigger_irq,
2969 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2971 struct irq_cfg *cfg;
2976 err = assign_irq_vector(irq, tmp);
2978 struct ht_irq_msg msg;
2982 cpus_and(tmp, cfg->domain, tmp);
2983 dest = cpu_mask_to_apicid(tmp);
2985 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2989 HT_IRQ_LOW_DEST_ID(dest) |
2990 HT_IRQ_LOW_VECTOR(cfg->vector) |
2991 ((INT_DEST_MODE == 0) ?
2992 HT_IRQ_LOW_DM_PHYSICAL :
2993 HT_IRQ_LOW_DM_LOGICAL) |
2994 HT_IRQ_LOW_RQEOI_EDGE |
2995 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2996 HT_IRQ_LOW_MT_FIXED :
2997 HT_IRQ_LOW_MT_ARBITRATED) |
2998 HT_IRQ_LOW_IRQ_MASKED;
3000 write_ht_irq_msg(irq, &msg);
3002 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3003 handle_edge_irq, "edge");
3007 #endif /* CONFIG_HT_IRQ */
3009 /* --------------------------------------------------------------------------
3010 ACPI-based IOAPIC Configuration
3011 -------------------------------------------------------------------------- */
3015 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3017 union IO_APIC_reg_00 reg_00;
3018 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3020 unsigned long flags;
3024 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3025 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3026 * supports up to 16 on one shared APIC bus.
3028 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3029 * advantage of new APIC bus architecture.
3032 if (physids_empty(apic_id_map))
3033 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3035 spin_lock_irqsave(&ioapic_lock, flags);
3036 reg_00.raw = io_apic_read(ioapic, 0);
3037 spin_unlock_irqrestore(&ioapic_lock, flags);
3039 if (apic_id >= get_physical_broadcast()) {
3040 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3041 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3042 apic_id = reg_00.bits.ID;
3046 * Every APIC in a system must have a unique ID or we get lots of nice
3047 * 'stuck on smp_invalidate_needed IPI wait' messages.
3049 if (check_apicid_used(apic_id_map, apic_id)) {
3051 for (i = 0; i < get_physical_broadcast(); i++) {
3052 if (!check_apicid_used(apic_id_map, i))
3056 if (i == get_physical_broadcast())
3057 panic("Max apic_id exceeded!\n");
3059 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3060 "trying %d\n", ioapic, apic_id, i);
3065 tmp = apicid_to_cpu_present(apic_id);
3066 physids_or(apic_id_map, apic_id_map, tmp);
3068 if (reg_00.bits.ID != apic_id) {
3069 reg_00.bits.ID = apic_id;
3071 spin_lock_irqsave(&ioapic_lock, flags);
3072 io_apic_write(ioapic, 0, reg_00.raw);
3073 reg_00.raw = io_apic_read(ioapic, 0);
3074 spin_unlock_irqrestore(&ioapic_lock, flags);
3077 if (reg_00.bits.ID != apic_id) {
3078 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3083 apic_printk(APIC_VERBOSE, KERN_INFO
3084 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3090 int __init io_apic_get_version(int ioapic)
3092 union IO_APIC_reg_01 reg_01;
3093 unsigned long flags;
3095 spin_lock_irqsave(&ioapic_lock, flags);
3096 reg_01.raw = io_apic_read(ioapic, 1);
3097 spin_unlock_irqrestore(&ioapic_lock, flags);
3099 return reg_01.bits.version;
3103 int __init io_apic_get_redir_entries(int ioapic)
3105 union IO_APIC_reg_01 reg_01;
3106 unsigned long flags;
3108 spin_lock_irqsave(&ioapic_lock, flags);
3109 reg_01.raw = io_apic_read(ioapic, 1);
3110 spin_unlock_irqrestore(&ioapic_lock, flags);
3112 return reg_01.bits.entries;
3116 int io_apic_set_pci_routing(int ioapic, int pin, int irq, int triggering, int polarity)
3118 if (!IO_APIC_IRQ(irq)) {
3119 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3125 * IRQs < 16 are already in the irq_2_pin[] map
3128 add_pin_to_irq(irq, ioapic, pin);
3130 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
3135 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3139 if (skip_ioapic_setup)
3142 for (i = 0; i < mp_irq_entries; i++)
3143 if (mp_irqs[i].mp_irqtype == mp_INT &&
3144 mp_irqs[i].mp_srcbusirq == bus_irq)
3146 if (i >= mp_irq_entries)
3149 *trigger = irq_trigger(i);
3150 *polarity = irq_polarity(i);
3154 #endif /* CONFIG_ACPI */
3157 * This function currently is only a helper for the i386 smp boot process where
3158 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3159 * so mask in all cases should simply be TARGET_CPUS
3162 void __init setup_ioapic_dest(void)
3164 int pin, ioapic, irq, irq_entry;
3165 struct irq_cfg *cfg;
3166 struct irq_desc *desc;
3168 if (skip_ioapic_setup == 1)
3171 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3172 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3173 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3174 if (irq_entry == -1)
3176 irq = pin_2_irq(irq_entry, ioapic, pin);
3178 /* setup_IO_APIC_irqs could fail to get vector for some device
3179 * when you have too many devices, because at that time only boot
3184 setup_IO_APIC_irq(ioapic, pin, irq,
3185 irq_trigger(irq_entry),
3186 irq_polarity(irq_entry));
3188 desc = irq_to_desc(irq);
3189 set_ioapic_affinity_irq(irq, TARGET_CPUS);
3197 void __init ioapic_init_mappings(void)
3199 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3202 for (i = 0; i < nr_ioapics; i++) {
3203 if (smp_found_config) {
3204 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3207 "WARNING: bogus zero IO-APIC "
3208 "address found in MPTABLE, "
3209 "disabling IO/APIC support!\n");
3210 smp_found_config = 0;
3211 skip_ioapic_setup = 1;
3212 goto fake_ioapic_page;
3216 ioapic_phys = (unsigned long)
3217 alloc_bootmem_pages(PAGE_SIZE);
3218 ioapic_phys = __pa(ioapic_phys);
3220 set_fixmap_nocache(idx, ioapic_phys);
3221 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
3222 __fix_to_virt(idx), ioapic_phys);