x86: use not_pci bitmap #4
[sfrench/cifs-2.6.git] / arch / x86 / kernel / io_apic_32.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h>      /* time_after() */
39
40 #include <asm/io.h>
41 #include <asm/smp.h>
42 #include <asm/desc.h>
43 #include <asm/timer.h>
44 #include <asm/i8259.h>
45 #include <asm/nmi.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
48
49 #include <mach_apic.h>
50 #include <mach_apicdef.h>
51
52 int (*ioapic_renumber_irq)(int ioapic, int irq);
53 atomic_t irq_mis_count;
54
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
57
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
60
61 int timer_over_8254 __initdata = 1;
62
63 /*
64  *      Is the SiS APIC rmw bug present ?
65  *      -1 = don't know, 0 = no, 1 = yes
66  */
67 int sis_apic_bug = -1;
68
69 /*
70  * # of IRQ routing registers
71  */
72 int nr_ioapic_registers[MAX_IO_APICS];
73
74 static int disable_timer_pin_1 __initdata;
75
76 /*
77  * Rough estimation of how many shared IRQs there are, can
78  * be changed anytime.
79  */
80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
82
83 /*
84  * This is performance-critical, we want to do it O(1)
85  *
86  * the indexing order of this array favors 1:1 mappings
87  * between pins and IRQs.
88  */
89
90 static struct irq_pin_list {
91         int apic, pin, next;
92 } irq_2_pin[PIN_MAP_SIZE];
93
94 struct io_apic {
95         unsigned int index;
96         unsigned int unused[3];
97         unsigned int data;
98 };
99
100 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
101 {
102         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
103                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
104 }
105
106 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
107 {
108         struct io_apic __iomem *io_apic = io_apic_base(apic);
109         writel(reg, &io_apic->index);
110         return readl(&io_apic->data);
111 }
112
113 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
114 {
115         struct io_apic __iomem *io_apic = io_apic_base(apic);
116         writel(reg, &io_apic->index);
117         writel(value, &io_apic->data);
118 }
119
120 /*
121  * Re-write a value: to be used for read-modify-write
122  * cycles where the read already set up the index register.
123  *
124  * Older SiS APIC requires we rewrite the index register
125  */
126 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
127 {
128         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
129         if (sis_apic_bug)
130                 writel(reg, &io_apic->index);
131         writel(value, &io_apic->data);
132 }
133
134 union entry_union {
135         struct { u32 w1, w2; };
136         struct IO_APIC_route_entry entry;
137 };
138
139 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
140 {
141         union entry_union eu;
142         unsigned long flags;
143         spin_lock_irqsave(&ioapic_lock, flags);
144         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
145         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
146         spin_unlock_irqrestore(&ioapic_lock, flags);
147         return eu.entry;
148 }
149
150 /*
151  * When we write a new IO APIC routing entry, we need to write the high
152  * word first! If the mask bit in the low word is clear, we will enable
153  * the interrupt, and we need to make sure the entry is fully populated
154  * before that happens.
155  */
156 static void
157 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
158 {
159         union entry_union eu;
160         eu.entry = e;
161         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
162         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
163 }
164
165 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
166 {
167         unsigned long flags;
168         spin_lock_irqsave(&ioapic_lock, flags);
169         __ioapic_write_entry(apic, pin, e);
170         spin_unlock_irqrestore(&ioapic_lock, flags);
171 }
172
173 /*
174  * When we mask an IO APIC routing entry, we need to write the low
175  * word first, in order to set the mask bit before we change the
176  * high bits!
177  */
178 static void ioapic_mask_entry(int apic, int pin)
179 {
180         unsigned long flags;
181         union entry_union eu = { .entry.mask = 1 };
182
183         spin_lock_irqsave(&ioapic_lock, flags);
184         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
185         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
186         spin_unlock_irqrestore(&ioapic_lock, flags);
187 }
188
189 /*
190  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
191  * shared ISA-space IRQs, so we have to support them. We are super
192  * fast in the common case, and fast for shared ISA-space IRQs.
193  */
194 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
195 {
196         static int first_free_entry = NR_IRQS;
197         struct irq_pin_list *entry = irq_2_pin + irq;
198
199         while (entry->next)
200                 entry = irq_2_pin + entry->next;
201
202         if (entry->pin != -1) {
203                 entry->next = first_free_entry;
204                 entry = irq_2_pin + entry->next;
205                 if (++first_free_entry >= PIN_MAP_SIZE)
206                         panic("io_apic.c: whoops");
207         }
208         entry->apic = apic;
209         entry->pin = pin;
210 }
211
212 /*
213  * Reroute an IRQ to a different pin.
214  */
215 static void __init replace_pin_at_irq(unsigned int irq,
216                                       int oldapic, int oldpin,
217                                       int newapic, int newpin)
218 {
219         struct irq_pin_list *entry = irq_2_pin + irq;
220
221         while (1) {
222                 if (entry->apic == oldapic && entry->pin == oldpin) {
223                         entry->apic = newapic;
224                         entry->pin = newpin;
225                 }
226                 if (!entry->next)
227                         break;
228                 entry = irq_2_pin + entry->next;
229         }
230 }
231
232 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
233 {
234         struct irq_pin_list *entry = irq_2_pin + irq;
235         unsigned int pin, reg;
236
237         for (;;) {
238                 pin = entry->pin;
239                 if (pin == -1)
240                         break;
241                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
242                 reg &= ~disable;
243                 reg |= enable;
244                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
245                 if (!entry->next)
246                         break;
247                 entry = irq_2_pin + entry->next;
248         }
249 }
250
251 /* mask = 1 */
252 static void __mask_IO_APIC_irq (unsigned int irq)
253 {
254         __modify_IO_APIC_irq(irq, 0x00010000, 0);
255 }
256
257 /* mask = 0 */
258 static void __unmask_IO_APIC_irq (unsigned int irq)
259 {
260         __modify_IO_APIC_irq(irq, 0, 0x00010000);
261 }
262
263 /* mask = 1, trigger = 0 */
264 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
265 {
266         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
267 }
268
269 /* mask = 0, trigger = 1 */
270 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
271 {
272         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
273 }
274
275 static void mask_IO_APIC_irq (unsigned int irq)
276 {
277         unsigned long flags;
278
279         spin_lock_irqsave(&ioapic_lock, flags);
280         __mask_IO_APIC_irq(irq);
281         spin_unlock_irqrestore(&ioapic_lock, flags);
282 }
283
284 static void unmask_IO_APIC_irq (unsigned int irq)
285 {
286         unsigned long flags;
287
288         spin_lock_irqsave(&ioapic_lock, flags);
289         __unmask_IO_APIC_irq(irq);
290         spin_unlock_irqrestore(&ioapic_lock, flags);
291 }
292
293 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
294 {
295         struct IO_APIC_route_entry entry;
296         
297         /* Check delivery_mode to be sure we're not clearing an SMI pin */
298         entry = ioapic_read_entry(apic, pin);
299         if (entry.delivery_mode == dest_SMI)
300                 return;
301
302         /*
303          * Disable it in the IO-APIC irq-routing table:
304          */
305         ioapic_mask_entry(apic, pin);
306 }
307
308 static void clear_IO_APIC (void)
309 {
310         int apic, pin;
311
312         for (apic = 0; apic < nr_ioapics; apic++)
313                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
314                         clear_IO_APIC_pin(apic, pin);
315 }
316
317 #ifdef CONFIG_SMP
318 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
319 {
320         unsigned long flags;
321         int pin;
322         struct irq_pin_list *entry = irq_2_pin + irq;
323         unsigned int apicid_value;
324         cpumask_t tmp;
325         
326         cpus_and(tmp, cpumask, cpu_online_map);
327         if (cpus_empty(tmp))
328                 tmp = TARGET_CPUS;
329
330         cpus_and(cpumask, tmp, CPU_MASK_ALL);
331
332         apicid_value = cpu_mask_to_apicid(cpumask);
333         /* Prepare to do the io_apic_write */
334         apicid_value = apicid_value << 24;
335         spin_lock_irqsave(&ioapic_lock, flags);
336         for (;;) {
337                 pin = entry->pin;
338                 if (pin == -1)
339                         break;
340                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
341                 if (!entry->next)
342                         break;
343                 entry = irq_2_pin + entry->next;
344         }
345         irq_desc[irq].affinity = cpumask;
346         spin_unlock_irqrestore(&ioapic_lock, flags);
347 }
348
349 #if defined(CONFIG_IRQBALANCE)
350 # include <asm/processor.h>     /* kernel_thread() */
351 # include <linux/kernel_stat.h> /* kstat */
352 # include <linux/slab.h>                /* kmalloc() */
353 # include <linux/timer.h>
354  
355 #define IRQBALANCE_CHECK_ARCH -999
356 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
357 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
358 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
359 #define BALANCED_IRQ_LESS_DELTA         (HZ)
360
361 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
362 static int physical_balance __read_mostly;
363 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
364
365 static struct irq_cpu_info {
366         unsigned long * last_irq;
367         unsigned long * irq_delta;
368         unsigned long irq;
369 } irq_cpu_data[NR_CPUS];
370
371 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
372 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
373 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
374
375 #define IDLE_ENOUGH(cpu,now) \
376         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
377
378 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
379
380 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
381
382 static cpumask_t balance_irq_affinity[NR_IRQS] = {
383         [0 ... NR_IRQS-1] = CPU_MASK_ALL
384 };
385
386 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
387 {
388         balance_irq_affinity[irq] = mask;
389 }
390
391 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
392                         unsigned long now, int direction)
393 {
394         int search_idle = 1;
395         int cpu = curr_cpu;
396
397         goto inside;
398
399         do {
400                 if (unlikely(cpu == curr_cpu))
401                         search_idle = 0;
402 inside:
403                 if (direction == 1) {
404                         cpu++;
405                         if (cpu >= NR_CPUS)
406                                 cpu = 0;
407                 } else {
408                         cpu--;
409                         if (cpu == -1)
410                                 cpu = NR_CPUS-1;
411                 }
412         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
413                         (search_idle && !IDLE_ENOUGH(cpu,now)));
414
415         return cpu;
416 }
417
418 static inline void balance_irq(int cpu, int irq)
419 {
420         unsigned long now = jiffies;
421         cpumask_t allowed_mask;
422         unsigned int new_cpu;
423                 
424         if (irqbalance_disabled)
425                 return; 
426
427         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
428         new_cpu = move(cpu, allowed_mask, now, 1);
429         if (cpu != new_cpu) {
430                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
431         }
432 }
433
434 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
435 {
436         int i, j;
437
438         for_each_online_cpu(i) {
439                 for (j = 0; j < NR_IRQS; j++) {
440                         if (!irq_desc[j].action)
441                                 continue;
442                         /* Is it a significant load ?  */
443                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
444                                                 useful_load_threshold)
445                                 continue;
446                         balance_irq(i, j);
447                 }
448         }
449         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
450                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
451         return;
452 }
453
454 static void do_irq_balance(void)
455 {
456         int i, j;
457         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
458         unsigned long move_this_load = 0;
459         int max_loaded = 0, min_loaded = 0;
460         int load;
461         unsigned long useful_load_threshold = balanced_irq_interval + 10;
462         int selected_irq;
463         int tmp_loaded, first_attempt = 1;
464         unsigned long tmp_cpu_irq;
465         unsigned long imbalance = 0;
466         cpumask_t allowed_mask, target_cpu_mask, tmp;
467
468         for_each_possible_cpu(i) {
469                 int package_index;
470                 CPU_IRQ(i) = 0;
471                 if (!cpu_online(i))
472                         continue;
473                 package_index = CPU_TO_PACKAGEINDEX(i);
474                 for (j = 0; j < NR_IRQS; j++) {
475                         unsigned long value_now, delta;
476                         /* Is this an active IRQ or balancing disabled ? */
477                         if (!irq_desc[j].action || irq_balancing_disabled(j))
478                                 continue;
479                         if ( package_index == i )
480                                 IRQ_DELTA(package_index,j) = 0;
481                         /* Determine the total count per processor per IRQ */
482                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
483
484                         /* Determine the activity per processor per IRQ */
485                         delta = value_now - LAST_CPU_IRQ(i,j);
486
487                         /* Update last_cpu_irq[][] for the next time */
488                         LAST_CPU_IRQ(i,j) = value_now;
489
490                         /* Ignore IRQs whose rate is less than the clock */
491                         if (delta < useful_load_threshold)
492                                 continue;
493                         /* update the load for the processor or package total */
494                         IRQ_DELTA(package_index,j) += delta;
495
496                         /* Keep track of the higher numbered sibling as well */
497                         if (i != package_index)
498                                 CPU_IRQ(i) += delta;
499                         /*
500                          * We have sibling A and sibling B in the package
501                          *
502                          * cpu_irq[A] = load for cpu A + load for cpu B
503                          * cpu_irq[B] = load for cpu B
504                          */
505                         CPU_IRQ(package_index) += delta;
506                 }
507         }
508         /* Find the least loaded processor package */
509         for_each_online_cpu(i) {
510                 if (i != CPU_TO_PACKAGEINDEX(i))
511                         continue;
512                 if (min_cpu_irq > CPU_IRQ(i)) {
513                         min_cpu_irq = CPU_IRQ(i);
514                         min_loaded = i;
515                 }
516         }
517         max_cpu_irq = ULONG_MAX;
518
519 tryanothercpu:
520         /* Look for heaviest loaded processor.
521          * We may come back to get the next heaviest loaded processor.
522          * Skip processors with trivial loads.
523          */
524         tmp_cpu_irq = 0;
525         tmp_loaded = -1;
526         for_each_online_cpu(i) {
527                 if (i != CPU_TO_PACKAGEINDEX(i))
528                         continue;
529                 if (max_cpu_irq <= CPU_IRQ(i)) 
530                         continue;
531                 if (tmp_cpu_irq < CPU_IRQ(i)) {
532                         tmp_cpu_irq = CPU_IRQ(i);
533                         tmp_loaded = i;
534                 }
535         }
536
537         if (tmp_loaded == -1) {
538          /* In the case of small number of heavy interrupt sources, 
539           * loading some of the cpus too much. We use Ingo's original 
540           * approach to rotate them around.
541           */
542                 if (!first_attempt && imbalance >= useful_load_threshold) {
543                         rotate_irqs_among_cpus(useful_load_threshold);
544                         return;
545                 }
546                 goto not_worth_the_effort;
547         }
548         
549         first_attempt = 0;              /* heaviest search */
550         max_cpu_irq = tmp_cpu_irq;      /* load */
551         max_loaded = tmp_loaded;        /* processor */
552         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
553         
554         /* if imbalance is less than approx 10% of max load, then
555          * observe diminishing returns action. - quit
556          */
557         if (imbalance < (max_cpu_irq >> 3))
558                 goto not_worth_the_effort;
559
560 tryanotherirq:
561         /* if we select an IRQ to move that can't go where we want, then
562          * see if there is another one to try.
563          */
564         move_this_load = 0;
565         selected_irq = -1;
566         for (j = 0; j < NR_IRQS; j++) {
567                 /* Is this an active IRQ? */
568                 if (!irq_desc[j].action)
569                         continue;
570                 if (imbalance <= IRQ_DELTA(max_loaded,j))
571                         continue;
572                 /* Try to find the IRQ that is closest to the imbalance
573                  * without going over.
574                  */
575                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
576                         move_this_load = IRQ_DELTA(max_loaded,j);
577                         selected_irq = j;
578                 }
579         }
580         if (selected_irq == -1) {
581                 goto tryanothercpu;
582         }
583
584         imbalance = move_this_load;
585         
586         /* For physical_balance case, we accumulated both load
587          * values in the one of the siblings cpu_irq[],
588          * to use the same code for physical and logical processors
589          * as much as possible. 
590          *
591          * NOTE: the cpu_irq[] array holds the sum of the load for
592          * sibling A and sibling B in the slot for the lowest numbered
593          * sibling (A), _AND_ the load for sibling B in the slot for
594          * the higher numbered sibling.
595          *
596          * We seek the least loaded sibling by making the comparison
597          * (A+B)/2 vs B
598          */
599         load = CPU_IRQ(min_loaded) >> 1;
600         for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
601                 if (load > CPU_IRQ(j)) {
602                         /* This won't change cpu_sibling_map[min_loaded] */
603                         load = CPU_IRQ(j);
604                         min_loaded = j;
605                 }
606         }
607
608         cpus_and(allowed_mask,
609                 cpu_online_map,
610                 balance_irq_affinity[selected_irq]);
611         target_cpu_mask = cpumask_of_cpu(min_loaded);
612         cpus_and(tmp, target_cpu_mask, allowed_mask);
613
614         if (!cpus_empty(tmp)) {
615                 /* mark for change destination */
616                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
617
618                 /* Since we made a change, come back sooner to 
619                  * check for more variation.
620                  */
621                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
622                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
623                 return;
624         }
625         goto tryanotherirq;
626
627 not_worth_the_effort:
628         /*
629          * if we did not find an IRQ to move, then adjust the time interval
630          * upward
631          */
632         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
633                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);       
634         return;
635 }
636
637 static int balanced_irq(void *unused)
638 {
639         int i;
640         unsigned long prev_balance_time = jiffies;
641         long time_remaining = balanced_irq_interval;
642
643         /* push everything to CPU 0 to give us a starting point.  */
644         for (i = 0 ; i < NR_IRQS ; i++) {
645                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
646                 set_pending_irq(i, cpumask_of_cpu(0));
647         }
648
649         set_freezable();
650         for ( ; ; ) {
651                 time_remaining = schedule_timeout_interruptible(time_remaining);
652                 try_to_freeze();
653                 if (time_after(jiffies,
654                                 prev_balance_time+balanced_irq_interval)) {
655                         preempt_disable();
656                         do_irq_balance();
657                         prev_balance_time = jiffies;
658                         time_remaining = balanced_irq_interval;
659                         preempt_enable();
660                 }
661         }
662         return 0;
663 }
664
665 static int __init balanced_irq_init(void)
666 {
667         int i;
668         struct cpuinfo_x86 *c;
669         cpumask_t tmp;
670
671         cpus_shift_right(tmp, cpu_online_map, 2);
672         c = &boot_cpu_data;
673         /* When not overwritten by the command line ask subarchitecture. */
674         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
675                 irqbalance_disabled = NO_BALANCE_IRQ;
676         if (irqbalance_disabled)
677                 return 0;
678         
679          /* disable irqbalance completely if there is only one processor online */
680         if (num_online_cpus() < 2) {
681                 irqbalance_disabled = 1;
682                 return 0;
683         }
684         /*
685          * Enable physical balance only if more than 1 physical processor
686          * is present
687          */
688         if (smp_num_siblings > 1 && !cpus_empty(tmp))
689                 physical_balance = 1;
690
691         for_each_online_cpu(i) {
692                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
693                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
694                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
695                         printk(KERN_ERR "balanced_irq_init: out of memory");
696                         goto failed;
697                 }
698                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
699                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
700         }
701         
702         printk(KERN_INFO "Starting balanced_irq\n");
703         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
704                 return 0;
705         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
706 failed:
707         for_each_possible_cpu(i) {
708                 kfree(irq_cpu_data[i].irq_delta);
709                 irq_cpu_data[i].irq_delta = NULL;
710                 kfree(irq_cpu_data[i].last_irq);
711                 irq_cpu_data[i].last_irq = NULL;
712         }
713         return 0;
714 }
715
716 int __devinit irqbalance_disable(char *str)
717 {
718         irqbalance_disabled = 1;
719         return 1;
720 }
721
722 __setup("noirqbalance", irqbalance_disable);
723
724 late_initcall(balanced_irq_init);
725 #endif /* CONFIG_IRQBALANCE */
726 #endif /* CONFIG_SMP */
727
728 #ifndef CONFIG_SMP
729 void send_IPI_self(int vector)
730 {
731         unsigned int cfg;
732
733         /*
734          * Wait for idle.
735          */
736         apic_wait_icr_idle();
737         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
738         /*
739          * Send the IPI. The write to APIC_ICR fires this off.
740          */
741         apic_write_around(APIC_ICR, cfg);
742 }
743 #endif /* !CONFIG_SMP */
744
745
746 /*
747  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
748  * specific CPU-side IRQs.
749  */
750
751 #define MAX_PIRQS 8
752 static int pirq_entries [MAX_PIRQS];
753 static int pirqs_enabled;
754 int skip_ioapic_setup;
755
756 static int __init ioapic_pirq_setup(char *str)
757 {
758         int i, max;
759         int ints[MAX_PIRQS+1];
760
761         get_options(str, ARRAY_SIZE(ints), ints);
762
763         for (i = 0; i < MAX_PIRQS; i++)
764                 pirq_entries[i] = -1;
765
766         pirqs_enabled = 1;
767         apic_printk(APIC_VERBOSE, KERN_INFO
768                         "PIRQ redirection, working around broken MP-BIOS.\n");
769         max = MAX_PIRQS;
770         if (ints[0] < MAX_PIRQS)
771                 max = ints[0];
772
773         for (i = 0; i < max; i++) {
774                 apic_printk(APIC_VERBOSE, KERN_DEBUG
775                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
776                 /*
777                  * PIRQs are mapped upside down, usually.
778                  */
779                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
780         }
781         return 1;
782 }
783
784 __setup("pirq=", ioapic_pirq_setup);
785
786 /*
787  * Find the IRQ entry number of a certain pin.
788  */
789 static int find_irq_entry(int apic, int pin, int type)
790 {
791         int i;
792
793         for (i = 0; i < mp_irq_entries; i++)
794                 if (mp_irqs[i].mpc_irqtype == type &&
795                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
796                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
797                     mp_irqs[i].mpc_dstirq == pin)
798                         return i;
799
800         return -1;
801 }
802
803 /*
804  * Find the pin to which IRQ[irq] (ISA) is connected
805  */
806 static int __init find_isa_irq_pin(int irq, int type)
807 {
808         int i;
809
810         for (i = 0; i < mp_irq_entries; i++) {
811                 int lbus = mp_irqs[i].mpc_srcbus;
812
813                 if (test_bit(lbus, mp_bus_not_pci) &&
814                     (mp_irqs[i].mpc_irqtype == type) &&
815                     (mp_irqs[i].mpc_srcbusirq == irq))
816
817                         return mp_irqs[i].mpc_dstirq;
818         }
819         return -1;
820 }
821
822 static int __init find_isa_irq_apic(int irq, int type)
823 {
824         int i;
825
826         for (i = 0; i < mp_irq_entries; i++) {
827                 int lbus = mp_irqs[i].mpc_srcbus;
828
829                 if (test_bit(lbus, mp_bus_not_pci) &&
830                     (mp_irqs[i].mpc_irqtype == type) &&
831                     (mp_irqs[i].mpc_srcbusirq == irq))
832                         break;
833         }
834         if (i < mp_irq_entries) {
835                 int apic;
836                 for(apic = 0; apic < nr_ioapics; apic++) {
837                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
838                                 return apic;
839                 }
840         }
841
842         return -1;
843 }
844
845 /*
846  * Find a specific PCI IRQ entry.
847  * Not an __init, possibly needed by modules
848  */
849 static int pin_2_irq(int idx, int apic, int pin);
850
851 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
852 {
853         int apic, i, best_guess = -1;
854
855         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
856                 "slot:%d, pin:%d.\n", bus, slot, pin);
857         if (mp_bus_id_to_pci_bus[bus] == -1) {
858                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
859                 return -1;
860         }
861         for (i = 0; i < mp_irq_entries; i++) {
862                 int lbus = mp_irqs[i].mpc_srcbus;
863
864                 for (apic = 0; apic < nr_ioapics; apic++)
865                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
866                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
867                                 break;
868
869                 if (!test_bit(lbus, mp_bus_not_pci) &&
870                     !mp_irqs[i].mpc_irqtype &&
871                     (bus == lbus) &&
872                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
873                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
874
875                         if (!(apic || IO_APIC_IRQ(irq)))
876                                 continue;
877
878                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
879                                 return irq;
880                         /*
881                          * Use the first all-but-pin matching entry as a
882                          * best-guess fuzzy result for broken mptables.
883                          */
884                         if (best_guess < 0)
885                                 best_guess = irq;
886                 }
887         }
888         return best_guess;
889 }
890 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
891
892 /*
893  * This function currently is only a helper for the i386 smp boot process where 
894  * we need to reprogram the ioredtbls to cater for the cpus which have come online
895  * so mask in all cases should simply be TARGET_CPUS
896  */
897 #ifdef CONFIG_SMP
898 void __init setup_ioapic_dest(void)
899 {
900         int pin, ioapic, irq, irq_entry;
901
902         if (skip_ioapic_setup == 1)
903                 return;
904
905         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
906                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
907                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
908                         if (irq_entry == -1)
909                                 continue;
910                         irq = pin_2_irq(irq_entry, ioapic, pin);
911                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
912                 }
913
914         }
915 }
916 #endif
917
918 /*
919  * EISA Edge/Level control register, ELCR
920  */
921 static int EISA_ELCR(unsigned int irq)
922 {
923         if (irq < 16) {
924                 unsigned int port = 0x4d0 + (irq >> 3);
925                 return (inb(port) >> (irq & 7)) & 1;
926         }
927         apic_printk(APIC_VERBOSE, KERN_INFO
928                         "Broken MPtable reports ISA irq %d\n", irq);
929         return 0;
930 }
931
932 /* ISA interrupts are always polarity zero edge triggered,
933  * when listed as conforming in the MP table. */
934
935 #define default_ISA_trigger(idx)        (0)
936 #define default_ISA_polarity(idx)       (0)
937
938 /* EISA interrupts are always polarity zero and can be edge or level
939  * trigger depending on the ELCR value.  If an interrupt is listed as
940  * EISA conforming in the MP table, that means its trigger type must
941  * be read in from the ELCR */
942
943 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
944 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
945
946 /* PCI interrupts are always polarity one level triggered,
947  * when listed as conforming in the MP table. */
948
949 #define default_PCI_trigger(idx)        (1)
950 #define default_PCI_polarity(idx)       (1)
951
952 /* MCA interrupts are always polarity zero level triggered,
953  * when listed as conforming in the MP table. */
954
955 #define default_MCA_trigger(idx)        (1)
956 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
957
958 static int MPBIOS_polarity(int idx)
959 {
960         int bus = mp_irqs[idx].mpc_srcbus;
961         int polarity;
962
963         /*
964          * Determine IRQ line polarity (high active or low active):
965          */
966         switch (mp_irqs[idx].mpc_irqflag & 3)
967         {
968                 case 0: /* conforms, ie. bus-type dependent polarity */
969                 {
970                         polarity = test_bit(bus, mp_bus_not_pci)?
971                                 default_ISA_polarity(idx):
972                                 default_PCI_polarity(idx);
973                         break;
974                 }
975                 case 1: /* high active */
976                 {
977                         polarity = 0;
978                         break;
979                 }
980                 case 2: /* reserved */
981                 {
982                         printk(KERN_WARNING "broken BIOS!!\n");
983                         polarity = 1;
984                         break;
985                 }
986                 case 3: /* low active */
987                 {
988                         polarity = 1;
989                         break;
990                 }
991                 default: /* invalid */
992                 {
993                         printk(KERN_WARNING "broken BIOS!!\n");
994                         polarity = 1;
995                         break;
996                 }
997         }
998         return polarity;
999 }
1000
1001 static int MPBIOS_trigger(int idx)
1002 {
1003         int bus = mp_irqs[idx].mpc_srcbus;
1004         int trigger;
1005
1006         /*
1007          * Determine IRQ trigger mode (edge or level sensitive):
1008          */
1009         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1010         {
1011                 case 0: /* conforms, ie. bus-type dependent */
1012                 {
1013                         switch (mp_bus_id_to_type[bus])
1014                         {
1015                                 case MP_BUS_ISA: /* ISA pin */
1016                                 {
1017                                         trigger = default_ISA_trigger(idx);
1018                                         break;
1019                                 }
1020                                 case MP_BUS_EISA: /* EISA pin */
1021                                 {
1022                                         trigger = default_EISA_trigger(idx);
1023                                         break;
1024                                 }
1025                                 case MP_BUS_PCI: /* PCI pin */
1026                                 {
1027                                         trigger = default_PCI_trigger(idx);
1028                                         break;
1029                                 }
1030                                 case MP_BUS_MCA: /* MCA pin */
1031                                 {
1032                                         trigger = default_MCA_trigger(idx);
1033                                         break;
1034                                 }
1035                                 default:
1036                                 {
1037                                         printk(KERN_WARNING "broken BIOS!!\n");
1038                                         trigger = 1;
1039                                         break;
1040                                 }
1041                         }
1042                         break;
1043                 }
1044                 case 1: /* edge */
1045                 {
1046                         trigger = 0;
1047                         break;
1048                 }
1049                 case 2: /* reserved */
1050                 {
1051                         printk(KERN_WARNING "broken BIOS!!\n");
1052                         trigger = 1;
1053                         break;
1054                 }
1055                 case 3: /* level */
1056                 {
1057                         trigger = 1;
1058                         break;
1059                 }
1060                 default: /* invalid */
1061                 {
1062                         printk(KERN_WARNING "broken BIOS!!\n");
1063                         trigger = 0;
1064                         break;
1065                 }
1066         }
1067         return trigger;
1068 }
1069
1070 static inline int irq_polarity(int idx)
1071 {
1072         return MPBIOS_polarity(idx);
1073 }
1074
1075 static inline int irq_trigger(int idx)
1076 {
1077         return MPBIOS_trigger(idx);
1078 }
1079
1080 static int pin_2_irq(int idx, int apic, int pin)
1081 {
1082         int irq, i;
1083         int bus = mp_irqs[idx].mpc_srcbus;
1084
1085         /*
1086          * Debugging check, we are in big trouble if this message pops up!
1087          */
1088         if (mp_irqs[idx].mpc_dstirq != pin)
1089                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1090
1091         switch (mp_bus_id_to_type[bus])
1092         {
1093                 case MP_BUS_ISA: /* ISA pin */
1094                 case MP_BUS_EISA:
1095                 case MP_BUS_MCA:
1096                 {
1097                         irq = mp_irqs[idx].mpc_srcbusirq;
1098                         break;
1099                 }
1100                 case MP_BUS_PCI: /* PCI pin */
1101                 {
1102                         /*
1103                          * PCI IRQs are mapped in order
1104                          */
1105                         i = irq = 0;
1106                         while (i < apic)
1107                                 irq += nr_ioapic_registers[i++];
1108                         irq += pin;
1109
1110                         /*
1111                          * For MPS mode, so far only needed by ES7000 platform
1112                          */
1113                         if (ioapic_renumber_irq)
1114                                 irq = ioapic_renumber_irq(apic, irq);
1115
1116                         break;
1117                 }
1118                 default:
1119                 {
1120                         printk(KERN_ERR "unknown bus type %d.\n",bus); 
1121                         irq = 0;
1122                         break;
1123                 }
1124         }
1125
1126         /*
1127          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1128          */
1129         if ((pin >= 16) && (pin <= 23)) {
1130                 if (pirq_entries[pin-16] != -1) {
1131                         if (!pirq_entries[pin-16]) {
1132                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1133                                                 "disabling PIRQ%d\n", pin-16);
1134                         } else {
1135                                 irq = pirq_entries[pin-16];
1136                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1137                                                 "using PIRQ%d -> IRQ %d\n",
1138                                                 pin-16, irq);
1139                         }
1140                 }
1141         }
1142         return irq;
1143 }
1144
1145 static inline int IO_APIC_irq_trigger(int irq)
1146 {
1147         int apic, idx, pin;
1148
1149         for (apic = 0; apic < nr_ioapics; apic++) {
1150                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1151                         idx = find_irq_entry(apic,pin,mp_INT);
1152                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1153                                 return irq_trigger(idx);
1154                 }
1155         }
1156         /*
1157          * nonexistent IRQs are edge default
1158          */
1159         return 0;
1160 }
1161
1162 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1163 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1164
1165 static int __assign_irq_vector(int irq)
1166 {
1167         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1168         int vector, offset;
1169
1170         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1171
1172         if (irq_vector[irq] > 0)
1173                 return irq_vector[irq];
1174
1175         vector = current_vector;
1176         offset = current_offset;
1177 next:
1178         vector += 8;
1179         if (vector >= FIRST_SYSTEM_VECTOR) {
1180                 offset = (offset + 1) % 8;
1181                 vector = FIRST_DEVICE_VECTOR + offset;
1182         }
1183         if (vector == current_vector)
1184                 return -ENOSPC;
1185         if (test_and_set_bit(vector, used_vectors))
1186                 goto next;
1187
1188         current_vector = vector;
1189         current_offset = offset;
1190         irq_vector[irq] = vector;
1191
1192         return vector;
1193 }
1194
1195 static int assign_irq_vector(int irq)
1196 {
1197         unsigned long flags;
1198         int vector;
1199
1200         spin_lock_irqsave(&vector_lock, flags);
1201         vector = __assign_irq_vector(irq);
1202         spin_unlock_irqrestore(&vector_lock, flags);
1203
1204         return vector;
1205 }
1206 static struct irq_chip ioapic_chip;
1207
1208 #define IOAPIC_AUTO     -1
1209 #define IOAPIC_EDGE     0
1210 #define IOAPIC_LEVEL    1
1211
1212 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1213 {
1214         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1215             trigger == IOAPIC_LEVEL) {
1216                 irq_desc[irq].status |= IRQ_LEVEL;
1217                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1218                                          handle_fasteoi_irq, "fasteoi");
1219         } else {
1220                 irq_desc[irq].status &= ~IRQ_LEVEL;
1221                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1222                                          handle_edge_irq, "edge");
1223         }
1224         set_intr_gate(vector, interrupt[irq]);
1225 }
1226
1227 static void __init setup_IO_APIC_irqs(void)
1228 {
1229         struct IO_APIC_route_entry entry;
1230         int apic, pin, idx, irq, first_notcon = 1, vector;
1231         unsigned long flags;
1232
1233         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1234
1235         for (apic = 0; apic < nr_ioapics; apic++) {
1236         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1237
1238                 /*
1239                  * add it to the IO-APIC irq-routing table:
1240                  */
1241                 memset(&entry,0,sizeof(entry));
1242
1243                 entry.delivery_mode = INT_DELIVERY_MODE;
1244                 entry.dest_mode = INT_DEST_MODE;
1245                 entry.mask = 0;                         /* enable IRQ */
1246                 entry.dest.logical.logical_dest = 
1247                                         cpu_mask_to_apicid(TARGET_CPUS);
1248
1249                 idx = find_irq_entry(apic,pin,mp_INT);
1250                 if (idx == -1) {
1251                         if (first_notcon) {
1252                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1253                                                 " IO-APIC (apicid-pin) %d-%d",
1254                                                 mp_ioapics[apic].mpc_apicid,
1255                                                 pin);
1256                                 first_notcon = 0;
1257                         } else
1258                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1259                                         mp_ioapics[apic].mpc_apicid, pin);
1260                         continue;
1261                 }
1262
1263                 if (!first_notcon) {
1264                         apic_printk(APIC_VERBOSE, " not connected.\n");
1265                         first_notcon = 1;
1266                 }
1267
1268                 entry.trigger = irq_trigger(idx);
1269                 entry.polarity = irq_polarity(idx);
1270
1271                 if (irq_trigger(idx)) {
1272                         entry.trigger = 1;
1273                         entry.mask = 1;
1274                 }
1275
1276                 irq = pin_2_irq(idx, apic, pin);
1277                 /*
1278                  * skip adding the timer int on secondary nodes, which causes
1279                  * a small but painful rift in the time-space continuum
1280                  */
1281                 if (multi_timer_check(apic, irq))
1282                         continue;
1283                 else
1284                         add_pin_to_irq(irq, apic, pin);
1285
1286                 if (!apic && !IO_APIC_IRQ(irq))
1287                         continue;
1288
1289                 if (IO_APIC_IRQ(irq)) {
1290                         vector = assign_irq_vector(irq);
1291                         entry.vector = vector;
1292                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1293                 
1294                         if (!apic && (irq < 16))
1295                                 disable_8259A_irq(irq);
1296                 }
1297                 spin_lock_irqsave(&ioapic_lock, flags);
1298                 __ioapic_write_entry(apic, pin, entry);
1299                 spin_unlock_irqrestore(&ioapic_lock, flags);
1300         }
1301         }
1302
1303         if (!first_notcon)
1304                 apic_printk(APIC_VERBOSE, " not connected.\n");
1305 }
1306
1307 /*
1308  * Set up the 8259A-master output pin:
1309  */
1310 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1311 {
1312         struct IO_APIC_route_entry entry;
1313
1314         memset(&entry,0,sizeof(entry));
1315
1316         disable_8259A_irq(0);
1317
1318         /* mask LVT0 */
1319         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1320
1321         /*
1322          * We use logical delivery to get the timer IRQ
1323          * to the first CPU.
1324          */
1325         entry.dest_mode = INT_DEST_MODE;
1326         entry.mask = 0;                                 /* unmask IRQ now */
1327         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1328         entry.delivery_mode = INT_DELIVERY_MODE;
1329         entry.polarity = 0;
1330         entry.trigger = 0;
1331         entry.vector = vector;
1332
1333         /*
1334          * The timer IRQ doesn't have to know that behind the
1335          * scene we have a 8259A-master in AEOI mode ...
1336          */
1337         irq_desc[0].chip = &ioapic_chip;
1338         set_irq_handler(0, handle_edge_irq);
1339
1340         /*
1341          * Add it to the IO-APIC irq-routing table:
1342          */
1343         ioapic_write_entry(apic, pin, entry);
1344
1345         enable_8259A_irq(0);
1346 }
1347
1348 void __init print_IO_APIC(void)
1349 {
1350         int apic, i;
1351         union IO_APIC_reg_00 reg_00;
1352         union IO_APIC_reg_01 reg_01;
1353         union IO_APIC_reg_02 reg_02;
1354         union IO_APIC_reg_03 reg_03;
1355         unsigned long flags;
1356
1357         if (apic_verbosity == APIC_QUIET)
1358                 return;
1359
1360         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1361         for (i = 0; i < nr_ioapics; i++)
1362                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1363                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1364
1365         /*
1366          * We are a bit conservative about what we expect.  We have to
1367          * know about every hardware change ASAP.
1368          */
1369         printk(KERN_INFO "testing the IO APIC.......................\n");
1370
1371         for (apic = 0; apic < nr_ioapics; apic++) {
1372
1373         spin_lock_irqsave(&ioapic_lock, flags);
1374         reg_00.raw = io_apic_read(apic, 0);
1375         reg_01.raw = io_apic_read(apic, 1);
1376         if (reg_01.bits.version >= 0x10)
1377                 reg_02.raw = io_apic_read(apic, 2);
1378         if (reg_01.bits.version >= 0x20)
1379                 reg_03.raw = io_apic_read(apic, 3);
1380         spin_unlock_irqrestore(&ioapic_lock, flags);
1381
1382         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1383         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1384         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1385         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1386         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1387
1388         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1389         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1390
1391         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1392         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1393
1394         /*
1395          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1396          * but the value of reg_02 is read as the previous read register
1397          * value, so ignore it if reg_02 == reg_01.
1398          */
1399         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1400                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1401                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1402         }
1403
1404         /*
1405          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1406          * or reg_03, but the value of reg_0[23] is read as the previous read
1407          * register value, so ignore it if reg_03 == reg_0[12].
1408          */
1409         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1410             reg_03.raw != reg_01.raw) {
1411                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1412                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1413         }
1414
1415         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1416
1417         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1418                           " Stat Dest Deli Vect:   \n");
1419
1420         for (i = 0; i <= reg_01.bits.entries; i++) {
1421                 struct IO_APIC_route_entry entry;
1422
1423                 entry = ioapic_read_entry(apic, i);
1424
1425                 printk(KERN_DEBUG " %02x %03X %02X  ",
1426                         i,
1427                         entry.dest.logical.logical_dest,
1428                         entry.dest.physical.physical_dest
1429                 );
1430
1431                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1432                         entry.mask,
1433                         entry.trigger,
1434                         entry.irr,
1435                         entry.polarity,
1436                         entry.delivery_status,
1437                         entry.dest_mode,
1438                         entry.delivery_mode,
1439                         entry.vector
1440                 );
1441         }
1442         }
1443         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1444         for (i = 0; i < NR_IRQS; i++) {
1445                 struct irq_pin_list *entry = irq_2_pin + i;
1446                 if (entry->pin < 0)
1447                         continue;
1448                 printk(KERN_DEBUG "IRQ%d ", i);
1449                 for (;;) {
1450                         printk("-> %d:%d", entry->apic, entry->pin);
1451                         if (!entry->next)
1452                                 break;
1453                         entry = irq_2_pin + entry->next;
1454                 }
1455                 printk("\n");
1456         }
1457
1458         printk(KERN_INFO ".................................... done.\n");
1459
1460         return;
1461 }
1462
1463 #if 0
1464
1465 static void print_APIC_bitfield (int base)
1466 {
1467         unsigned int v;
1468         int i, j;
1469
1470         if (apic_verbosity == APIC_QUIET)
1471                 return;
1472
1473         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1474         for (i = 0; i < 8; i++) {
1475                 v = apic_read(base + i*0x10);
1476                 for (j = 0; j < 32; j++) {
1477                         if (v & (1<<j))
1478                                 printk("1");
1479                         else
1480                                 printk("0");
1481                 }
1482                 printk("\n");
1483         }
1484 }
1485
1486 void /*__init*/ print_local_APIC(void * dummy)
1487 {
1488         unsigned int v, ver, maxlvt;
1489
1490         if (apic_verbosity == APIC_QUIET)
1491                 return;
1492
1493         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1494                 smp_processor_id(), hard_smp_processor_id());
1495         v = apic_read(APIC_ID);
1496         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1497         v = apic_read(APIC_LVR);
1498         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1499         ver = GET_APIC_VERSION(v);
1500         maxlvt = lapic_get_maxlvt();
1501
1502         v = apic_read(APIC_TASKPRI);
1503         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1504
1505         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1506                 v = apic_read(APIC_ARBPRI);
1507                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1508                         v & APIC_ARBPRI_MASK);
1509                 v = apic_read(APIC_PROCPRI);
1510                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1511         }
1512
1513         v = apic_read(APIC_EOI);
1514         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1515         v = apic_read(APIC_RRR);
1516         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1517         v = apic_read(APIC_LDR);
1518         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1519         v = apic_read(APIC_DFR);
1520         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1521         v = apic_read(APIC_SPIV);
1522         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1523
1524         printk(KERN_DEBUG "... APIC ISR field:\n");
1525         print_APIC_bitfield(APIC_ISR);
1526         printk(KERN_DEBUG "... APIC TMR field:\n");
1527         print_APIC_bitfield(APIC_TMR);
1528         printk(KERN_DEBUG "... APIC IRR field:\n");
1529         print_APIC_bitfield(APIC_IRR);
1530
1531         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1532                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1533                         apic_write(APIC_ESR, 0);
1534                 v = apic_read(APIC_ESR);
1535                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1536         }
1537
1538         v = apic_read(APIC_ICR);
1539         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1540         v = apic_read(APIC_ICR2);
1541         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1542
1543         v = apic_read(APIC_LVTT);
1544         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1545
1546         if (maxlvt > 3) {                       /* PC is LVT#4. */
1547                 v = apic_read(APIC_LVTPC);
1548                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1549         }
1550         v = apic_read(APIC_LVT0);
1551         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1552         v = apic_read(APIC_LVT1);
1553         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1554
1555         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1556                 v = apic_read(APIC_LVTERR);
1557                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1558         }
1559
1560         v = apic_read(APIC_TMICT);
1561         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1562         v = apic_read(APIC_TMCCT);
1563         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1564         v = apic_read(APIC_TDCR);
1565         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1566         printk("\n");
1567 }
1568
1569 void print_all_local_APICs (void)
1570 {
1571         on_each_cpu(print_local_APIC, NULL, 1, 1);
1572 }
1573
1574 void /*__init*/ print_PIC(void)
1575 {
1576         unsigned int v;
1577         unsigned long flags;
1578
1579         if (apic_verbosity == APIC_QUIET)
1580                 return;
1581
1582         printk(KERN_DEBUG "\nprinting PIC contents\n");
1583
1584         spin_lock_irqsave(&i8259A_lock, flags);
1585
1586         v = inb(0xa1) << 8 | inb(0x21);
1587         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1588
1589         v = inb(0xa0) << 8 | inb(0x20);
1590         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1591
1592         outb(0x0b,0xa0);
1593         outb(0x0b,0x20);
1594         v = inb(0xa0) << 8 | inb(0x20);
1595         outb(0x0a,0xa0);
1596         outb(0x0a,0x20);
1597
1598         spin_unlock_irqrestore(&i8259A_lock, flags);
1599
1600         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1601
1602         v = inb(0x4d1) << 8 | inb(0x4d0);
1603         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1604 }
1605
1606 #endif  /*  0  */
1607
1608 static void __init enable_IO_APIC(void)
1609 {
1610         union IO_APIC_reg_01 reg_01;
1611         int i8259_apic, i8259_pin;
1612         int i, apic;
1613         unsigned long flags;
1614
1615         for (i = 0; i < PIN_MAP_SIZE; i++) {
1616                 irq_2_pin[i].pin = -1;
1617                 irq_2_pin[i].next = 0;
1618         }
1619         if (!pirqs_enabled)
1620                 for (i = 0; i < MAX_PIRQS; i++)
1621                         pirq_entries[i] = -1;
1622
1623         /*
1624          * The number of IO-APIC IRQ registers (== #pins):
1625          */
1626         for (apic = 0; apic < nr_ioapics; apic++) {
1627                 spin_lock_irqsave(&ioapic_lock, flags);
1628                 reg_01.raw = io_apic_read(apic, 1);
1629                 spin_unlock_irqrestore(&ioapic_lock, flags);
1630                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1631         }
1632         for(apic = 0; apic < nr_ioapics; apic++) {
1633                 int pin;
1634                 /* See if any of the pins is in ExtINT mode */
1635                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1636                         struct IO_APIC_route_entry entry;
1637                         entry = ioapic_read_entry(apic, pin);
1638
1639
1640                         /* If the interrupt line is enabled and in ExtInt mode
1641                          * I have found the pin where the i8259 is connected.
1642                          */
1643                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1644                                 ioapic_i8259.apic = apic;
1645                                 ioapic_i8259.pin  = pin;
1646                                 goto found_i8259;
1647                         }
1648                 }
1649         }
1650  found_i8259:
1651         /* Look to see what if the MP table has reported the ExtINT */
1652         /* If we could not find the appropriate pin by looking at the ioapic
1653          * the i8259 probably is not connected the ioapic but give the
1654          * mptable a chance anyway.
1655          */
1656         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1657         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1658         /* Trust the MP table if nothing is setup in the hardware */
1659         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1660                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1661                 ioapic_i8259.pin  = i8259_pin;
1662                 ioapic_i8259.apic = i8259_apic;
1663         }
1664         /* Complain if the MP table and the hardware disagree */
1665         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1666                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1667         {
1668                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1669         }
1670
1671         /*
1672          * Do not trust the IO-APIC being empty at bootup
1673          */
1674         clear_IO_APIC();
1675 }
1676
1677 /*
1678  * Not an __init, needed by the reboot code
1679  */
1680 void disable_IO_APIC(void)
1681 {
1682         /*
1683          * Clear the IO-APIC before rebooting:
1684          */
1685         clear_IO_APIC();
1686
1687         /*
1688          * If the i8259 is routed through an IOAPIC
1689          * Put that IOAPIC in virtual wire mode
1690          * so legacy interrupts can be delivered.
1691          */
1692         if (ioapic_i8259.pin != -1) {
1693                 struct IO_APIC_route_entry entry;
1694
1695                 memset(&entry, 0, sizeof(entry));
1696                 entry.mask            = 0; /* Enabled */
1697                 entry.trigger         = 0; /* Edge */
1698                 entry.irr             = 0;
1699                 entry.polarity        = 0; /* High */
1700                 entry.delivery_status = 0;
1701                 entry.dest_mode       = 0; /* Physical */
1702                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1703                 entry.vector          = 0;
1704                 entry.dest.physical.physical_dest =
1705                                         GET_APIC_ID(apic_read(APIC_ID));
1706
1707                 /*
1708                  * Add it to the IO-APIC irq-routing table:
1709                  */
1710                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1711         }
1712         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1713 }
1714
1715 /*
1716  * function to set the IO-APIC physical IDs based on the
1717  * values stored in the MPC table.
1718  *
1719  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1720  */
1721
1722 #ifndef CONFIG_X86_NUMAQ
1723 static void __init setup_ioapic_ids_from_mpc(void)
1724 {
1725         union IO_APIC_reg_00 reg_00;
1726         physid_mask_t phys_id_present_map;
1727         int apic;
1728         int i;
1729         unsigned char old_id;
1730         unsigned long flags;
1731
1732         /*
1733          * Don't check I/O APIC IDs for xAPIC systems.  They have
1734          * no meaning without the serial APIC bus.
1735          */
1736         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1737                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1738                 return;
1739         /*
1740          * This is broken; anything with a real cpu count has to
1741          * circumvent this idiocy regardless.
1742          */
1743         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1744
1745         /*
1746          * Set the IOAPIC ID to the value stored in the MPC table.
1747          */
1748         for (apic = 0; apic < nr_ioapics; apic++) {
1749
1750                 /* Read the register 0 value */
1751                 spin_lock_irqsave(&ioapic_lock, flags);
1752                 reg_00.raw = io_apic_read(apic, 0);
1753                 spin_unlock_irqrestore(&ioapic_lock, flags);
1754                 
1755                 old_id = mp_ioapics[apic].mpc_apicid;
1756
1757                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1758                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1759                                 apic, mp_ioapics[apic].mpc_apicid);
1760                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1761                                 reg_00.bits.ID);
1762                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1763                 }
1764
1765                 /*
1766                  * Sanity check, is the ID really free? Every APIC in a
1767                  * system must have a unique ID or we get lots of nice
1768                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1769                  */
1770                 if (check_apicid_used(phys_id_present_map,
1771                                         mp_ioapics[apic].mpc_apicid)) {
1772                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1773                                 apic, mp_ioapics[apic].mpc_apicid);
1774                         for (i = 0; i < get_physical_broadcast(); i++)
1775                                 if (!physid_isset(i, phys_id_present_map))
1776                                         break;
1777                         if (i >= get_physical_broadcast())
1778                                 panic("Max APIC ID exceeded!\n");
1779                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1780                                 i);
1781                         physid_set(i, phys_id_present_map);
1782                         mp_ioapics[apic].mpc_apicid = i;
1783                 } else {
1784                         physid_mask_t tmp;
1785                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1786                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1787                                         "phys_id_present_map\n",
1788                                         mp_ioapics[apic].mpc_apicid);
1789                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1790                 }
1791
1792
1793                 /*
1794                  * We need to adjust the IRQ routing table
1795                  * if the ID changed.
1796                  */
1797                 if (old_id != mp_ioapics[apic].mpc_apicid)
1798                         for (i = 0; i < mp_irq_entries; i++)
1799                                 if (mp_irqs[i].mpc_dstapic == old_id)
1800                                         mp_irqs[i].mpc_dstapic
1801                                                 = mp_ioapics[apic].mpc_apicid;
1802
1803                 /*
1804                  * Read the right value from the MPC table and
1805                  * write it into the ID register.
1806                  */
1807                 apic_printk(APIC_VERBOSE, KERN_INFO
1808                         "...changing IO-APIC physical APIC ID to %d ...",
1809                         mp_ioapics[apic].mpc_apicid);
1810
1811                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1812                 spin_lock_irqsave(&ioapic_lock, flags);
1813                 io_apic_write(apic, 0, reg_00.raw);
1814                 spin_unlock_irqrestore(&ioapic_lock, flags);
1815
1816                 /*
1817                  * Sanity check
1818                  */
1819                 spin_lock_irqsave(&ioapic_lock, flags);
1820                 reg_00.raw = io_apic_read(apic, 0);
1821                 spin_unlock_irqrestore(&ioapic_lock, flags);
1822                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1823                         printk("could not set ID!\n");
1824                 else
1825                         apic_printk(APIC_VERBOSE, " ok.\n");
1826         }
1827 }
1828 #else
1829 static void __init setup_ioapic_ids_from_mpc(void) { }
1830 #endif
1831
1832 int no_timer_check __initdata;
1833
1834 static int __init notimercheck(char *s)
1835 {
1836         no_timer_check = 1;
1837         return 1;
1838 }
1839 __setup("no_timer_check", notimercheck);
1840
1841 /*
1842  * There is a nasty bug in some older SMP boards, their mptable lies
1843  * about the timer IRQ. We do the following to work around the situation:
1844  *
1845  *      - timer IRQ defaults to IO-APIC IRQ
1846  *      - if this function detects that timer IRQs are defunct, then we fall
1847  *        back to ISA timer IRQs
1848  */
1849 static int __init timer_irq_works(void)
1850 {
1851         unsigned long t1 = jiffies;
1852         unsigned long flags;
1853
1854         if (no_timer_check)
1855                 return 1;
1856
1857         local_save_flags(flags);
1858         local_irq_enable();
1859         /* Let ten ticks pass... */
1860         mdelay((10 * 1000) / HZ);
1861         local_irq_restore(flags);
1862
1863         /*
1864          * Expect a few ticks at least, to be sure some possible
1865          * glue logic does not lock up after one or two first
1866          * ticks in a non-ExtINT mode.  Also the local APIC
1867          * might have cached one ExtINT interrupt.  Finally, at
1868          * least one tick may be lost due to delays.
1869          */
1870         if (time_after(jiffies, t1 + 4))
1871                 return 1;
1872
1873         return 0;
1874 }
1875
1876 /*
1877  * In the SMP+IOAPIC case it might happen that there are an unspecified
1878  * number of pending IRQ events unhandled. These cases are very rare,
1879  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1880  * better to do it this way as thus we do not have to be aware of
1881  * 'pending' interrupts in the IRQ path, except at this point.
1882  */
1883 /*
1884  * Edge triggered needs to resend any interrupt
1885  * that was delayed but this is now handled in the device
1886  * independent code.
1887  */
1888
1889 /*
1890  * Startup quirk:
1891  *
1892  * Starting up a edge-triggered IO-APIC interrupt is
1893  * nasty - we need to make sure that we get the edge.
1894  * If it is already asserted for some reason, we need
1895  * return 1 to indicate that is was pending.
1896  *
1897  * This is not complete - we should be able to fake
1898  * an edge even if it isn't on the 8259A...
1899  *
1900  * (We do this for level-triggered IRQs too - it cannot hurt.)
1901  */
1902 static unsigned int startup_ioapic_irq(unsigned int irq)
1903 {
1904         int was_pending = 0;
1905         unsigned long flags;
1906
1907         spin_lock_irqsave(&ioapic_lock, flags);
1908         if (irq < 16) {
1909                 disable_8259A_irq(irq);
1910                 if (i8259A_irq_pending(irq))
1911                         was_pending = 1;
1912         }
1913         __unmask_IO_APIC_irq(irq);
1914         spin_unlock_irqrestore(&ioapic_lock, flags);
1915
1916         return was_pending;
1917 }
1918
1919 static void ack_ioapic_irq(unsigned int irq)
1920 {
1921         move_native_irq(irq);
1922         ack_APIC_irq();
1923 }
1924
1925 static void ack_ioapic_quirk_irq(unsigned int irq)
1926 {
1927         unsigned long v;
1928         int i;
1929
1930         move_native_irq(irq);
1931 /*
1932  * It appears there is an erratum which affects at least version 0x11
1933  * of I/O APIC (that's the 82093AA and cores integrated into various
1934  * chipsets).  Under certain conditions a level-triggered interrupt is
1935  * erroneously delivered as edge-triggered one but the respective IRR
1936  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1937  * message but it will never arrive and further interrupts are blocked
1938  * from the source.  The exact reason is so far unknown, but the
1939  * phenomenon was observed when two consecutive interrupt requests
1940  * from a given source get delivered to the same CPU and the source is
1941  * temporarily disabled in between.
1942  *
1943  * A workaround is to simulate an EOI message manually.  We achieve it
1944  * by setting the trigger mode to edge and then to level when the edge
1945  * trigger mode gets detected in the TMR of a local APIC for a
1946  * level-triggered interrupt.  We mask the source for the time of the
1947  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1948  * The idea is from Manfred Spraul.  --macro
1949  */
1950         i = irq_vector[irq];
1951
1952         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1953
1954         ack_APIC_irq();
1955
1956         if (!(v & (1 << (i & 0x1f)))) {
1957                 atomic_inc(&irq_mis_count);
1958                 spin_lock(&ioapic_lock);
1959                 __mask_and_edge_IO_APIC_irq(irq);
1960                 __unmask_and_level_IO_APIC_irq(irq);
1961                 spin_unlock(&ioapic_lock);
1962         }
1963 }
1964
1965 static int ioapic_retrigger_irq(unsigned int irq)
1966 {
1967         send_IPI_self(irq_vector[irq]);
1968
1969         return 1;
1970 }
1971
1972 static struct irq_chip ioapic_chip __read_mostly = {
1973         .name           = "IO-APIC",
1974         .startup        = startup_ioapic_irq,
1975         .mask           = mask_IO_APIC_irq,
1976         .unmask         = unmask_IO_APIC_irq,
1977         .ack            = ack_ioapic_irq,
1978         .eoi            = ack_ioapic_quirk_irq,
1979 #ifdef CONFIG_SMP
1980         .set_affinity   = set_ioapic_affinity_irq,
1981 #endif
1982         .retrigger      = ioapic_retrigger_irq,
1983 };
1984
1985
1986 static inline void init_IO_APIC_traps(void)
1987 {
1988         int irq;
1989
1990         /*
1991          * NOTE! The local APIC isn't very good at handling
1992          * multiple interrupts at the same interrupt level.
1993          * As the interrupt level is determined by taking the
1994          * vector number and shifting that right by 4, we
1995          * want to spread these out a bit so that they don't
1996          * all fall in the same interrupt level.
1997          *
1998          * Also, we've got to be careful not to trash gate
1999          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2000          */
2001         for (irq = 0; irq < NR_IRQS ; irq++) {
2002                 int tmp = irq;
2003                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2004                         /*
2005                          * Hmm.. We don't have an entry for this,
2006                          * so default to an old-fashioned 8259
2007                          * interrupt if we can..
2008                          */
2009                         if (irq < 16)
2010                                 make_8259A_irq(irq);
2011                         else
2012                                 /* Strange. Oh, well.. */
2013                                 irq_desc[irq].chip = &no_irq_chip;
2014                 }
2015         }
2016 }
2017
2018 /*
2019  * The local APIC irq-chip implementation:
2020  */
2021
2022 static void ack_apic(unsigned int irq)
2023 {
2024         ack_APIC_irq();
2025 }
2026
2027 static void mask_lapic_irq (unsigned int irq)
2028 {
2029         unsigned long v;
2030
2031         v = apic_read(APIC_LVT0);
2032         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2033 }
2034
2035 static void unmask_lapic_irq (unsigned int irq)
2036 {
2037         unsigned long v;
2038
2039         v = apic_read(APIC_LVT0);
2040         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2041 }
2042
2043 static struct irq_chip lapic_chip __read_mostly = {
2044         .name           = "local-APIC-edge",
2045         .mask           = mask_lapic_irq,
2046         .unmask         = unmask_lapic_irq,
2047         .eoi            = ack_apic,
2048 };
2049
2050 static void __init setup_nmi(void)
2051 {
2052         /*
2053          * Dirty trick to enable the NMI watchdog ...
2054          * We put the 8259A master into AEOI mode and
2055          * unmask on all local APICs LVT0 as NMI.
2056          *
2057          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2058          * is from Maciej W. Rozycki - so we do not have to EOI from
2059          * the NMI handler or the timer interrupt.
2060          */ 
2061         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2062
2063         enable_NMI_through_LVT0();
2064
2065         apic_printk(APIC_VERBOSE, " done.\n");
2066 }
2067
2068 /*
2069  * This looks a bit hackish but it's about the only one way of sending
2070  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2071  * not support the ExtINT mode, unfortunately.  We need to send these
2072  * cycles as some i82489DX-based boards have glue logic that keeps the
2073  * 8259A interrupt line asserted until INTA.  --macro
2074  */
2075 static inline void unlock_ExtINT_logic(void)
2076 {
2077         int apic, pin, i;
2078         struct IO_APIC_route_entry entry0, entry1;
2079         unsigned char save_control, save_freq_select;
2080
2081         pin  = find_isa_irq_pin(8, mp_INT);
2082         if (pin == -1) {
2083                 WARN_ON_ONCE(1);
2084                 return;
2085         }
2086         apic = find_isa_irq_apic(8, mp_INT);
2087         if (apic == -1) {
2088                 WARN_ON_ONCE(1);
2089                 return;
2090         }
2091
2092         entry0 = ioapic_read_entry(apic, pin);
2093         clear_IO_APIC_pin(apic, pin);
2094
2095         memset(&entry1, 0, sizeof(entry1));
2096
2097         entry1.dest_mode = 0;                   /* physical delivery */
2098         entry1.mask = 0;                        /* unmask IRQ now */
2099         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2100         entry1.delivery_mode = dest_ExtINT;
2101         entry1.polarity = entry0.polarity;
2102         entry1.trigger = 0;
2103         entry1.vector = 0;
2104
2105         ioapic_write_entry(apic, pin, entry1);
2106
2107         save_control = CMOS_READ(RTC_CONTROL);
2108         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2109         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2110                    RTC_FREQ_SELECT);
2111         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2112
2113         i = 100;
2114         while (i-- > 0) {
2115                 mdelay(10);
2116                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2117                         i -= 10;
2118         }
2119
2120         CMOS_WRITE(save_control, RTC_CONTROL);
2121         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2122         clear_IO_APIC_pin(apic, pin);
2123
2124         ioapic_write_entry(apic, pin, entry0);
2125 }
2126
2127 int timer_uses_ioapic_pin_0;
2128
2129 /*
2130  * This code may look a bit paranoid, but it's supposed to cooperate with
2131  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2132  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2133  * fanatically on his truly buggy board.
2134  */
2135 static inline void __init check_timer(void)
2136 {
2137         int apic1, pin1, apic2, pin2;
2138         int vector;
2139         unsigned long flags;
2140
2141         local_irq_save(flags);
2142
2143         /*
2144          * get/set the timer IRQ vector:
2145          */
2146         disable_8259A_irq(0);
2147         vector = assign_irq_vector(0);
2148         set_intr_gate(vector, interrupt[0]);
2149
2150         /*
2151          * Subtle, code in do_timer_interrupt() expects an AEOI
2152          * mode for the 8259A whenever interrupts are routed
2153          * through I/O APICs.  Also IRQ0 has to be enabled in
2154          * the 8259A which implies the virtual wire has to be
2155          * disabled in the local APIC.
2156          */
2157         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2158         init_8259A(1);
2159         timer_ack = 1;
2160         if (timer_over_8254 > 0)
2161                 enable_8259A_irq(0);
2162
2163         pin1  = find_isa_irq_pin(0, mp_INT);
2164         apic1 = find_isa_irq_apic(0, mp_INT);
2165         pin2  = ioapic_i8259.pin;
2166         apic2 = ioapic_i8259.apic;
2167
2168         if (pin1 == 0)
2169                 timer_uses_ioapic_pin_0 = 1;
2170
2171         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2172                 vector, apic1, pin1, apic2, pin2);
2173
2174         if (pin1 != -1) {
2175                 /*
2176                  * Ok, does IRQ0 through the IOAPIC work?
2177                  */
2178                 unmask_IO_APIC_irq(0);
2179                 if (timer_irq_works()) {
2180                         if (nmi_watchdog == NMI_IO_APIC) {
2181                                 disable_8259A_irq(0);
2182                                 setup_nmi();
2183                                 enable_8259A_irq(0);
2184                         }
2185                         if (disable_timer_pin_1 > 0)
2186                                 clear_IO_APIC_pin(0, pin1);
2187                         goto out;
2188                 }
2189                 clear_IO_APIC_pin(apic1, pin1);
2190                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2191                                 "IO-APIC\n");
2192         }
2193
2194         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2195         if (pin2 != -1) {
2196                 printk("\n..... (found pin %d) ...", pin2);
2197                 /*
2198                  * legacy devices should be connected to IO APIC #0
2199                  */
2200                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2201                 if (timer_irq_works()) {
2202                         printk("works.\n");
2203                         if (pin1 != -1)
2204                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2205                         else
2206                                 add_pin_to_irq(0, apic2, pin2);
2207                         if (nmi_watchdog == NMI_IO_APIC) {
2208                                 setup_nmi();
2209                         }
2210                         goto out;
2211                 }
2212                 /*
2213                  * Cleanup, just in case ...
2214                  */
2215                 clear_IO_APIC_pin(apic2, pin2);
2216         }
2217         printk(" failed.\n");
2218
2219         if (nmi_watchdog == NMI_IO_APIC) {
2220                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2221                 nmi_watchdog = 0;
2222         }
2223
2224         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2225
2226         disable_8259A_irq(0);
2227         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2228                                       "fasteoi");
2229         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2230         enable_8259A_irq(0);
2231
2232         if (timer_irq_works()) {
2233                 printk(" works.\n");
2234                 goto out;
2235         }
2236         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2237         printk(" failed.\n");
2238
2239         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2240
2241         timer_ack = 0;
2242         init_8259A(0);
2243         make_8259A_irq(0);
2244         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2245
2246         unlock_ExtINT_logic();
2247
2248         if (timer_irq_works()) {
2249                 printk(" works.\n");
2250                 goto out;
2251         }
2252         printk(" failed :(.\n");
2253         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2254                 "report.  Then try booting with the 'noapic' option");
2255 out:
2256         local_irq_restore(flags);
2257 }
2258
2259 /*
2260  *
2261  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2262  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2263  *   Linux doesn't really care, as it's not actually used
2264  *   for any interrupt handling anyway.
2265  */
2266 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2267
2268 void __init setup_IO_APIC(void)
2269 {
2270         int i;
2271
2272         /* Reserve all the system vectors. */
2273         for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2274                 set_bit(i, used_vectors);
2275
2276         enable_IO_APIC();
2277
2278         if (acpi_ioapic)
2279                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2280         else
2281                 io_apic_irqs = ~PIC_IRQS;
2282
2283         printk("ENABLING IO-APIC IRQs\n");
2284
2285         /*
2286          * Set up IO-APIC IRQ routing.
2287          */
2288         if (!acpi_ioapic)
2289                 setup_ioapic_ids_from_mpc();
2290         sync_Arb_IDs();
2291         setup_IO_APIC_irqs();
2292         init_IO_APIC_traps();
2293         check_timer();
2294         if (!acpi_ioapic)
2295                 print_IO_APIC();
2296 }
2297
2298 static int __init setup_disable_8254_timer(char *s)
2299 {
2300         timer_over_8254 = -1;
2301         return 1;
2302 }
2303 static int __init setup_enable_8254_timer(char *s)
2304 {
2305         timer_over_8254 = 2;
2306         return 1;
2307 }
2308
2309 __setup("disable_8254_timer", setup_disable_8254_timer);
2310 __setup("enable_8254_timer", setup_enable_8254_timer);
2311
2312 /*
2313  *      Called after all the initialization is done. If we didnt find any
2314  *      APIC bugs then we can allow the modify fast path
2315  */
2316  
2317 static int __init io_apic_bug_finalize(void)
2318 {
2319         if(sis_apic_bug == -1)
2320                 sis_apic_bug = 0;
2321         return 0;
2322 }
2323
2324 late_initcall(io_apic_bug_finalize);
2325
2326 struct sysfs_ioapic_data {
2327         struct sys_device dev;
2328         struct IO_APIC_route_entry entry[0];
2329 };
2330 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2331
2332 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2333 {
2334         struct IO_APIC_route_entry *entry;
2335         struct sysfs_ioapic_data *data;
2336         int i;
2337         
2338         data = container_of(dev, struct sysfs_ioapic_data, dev);
2339         entry = data->entry;
2340         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2341                 entry[i] = ioapic_read_entry(dev->id, i);
2342
2343         return 0;
2344 }
2345
2346 static int ioapic_resume(struct sys_device *dev)
2347 {
2348         struct IO_APIC_route_entry *entry;
2349         struct sysfs_ioapic_data *data;
2350         unsigned long flags;
2351         union IO_APIC_reg_00 reg_00;
2352         int i;
2353         
2354         data = container_of(dev, struct sysfs_ioapic_data, dev);
2355         entry = data->entry;
2356
2357         spin_lock_irqsave(&ioapic_lock, flags);
2358         reg_00.raw = io_apic_read(dev->id, 0);
2359         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2360                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2361                 io_apic_write(dev->id, 0, reg_00.raw);
2362         }
2363         spin_unlock_irqrestore(&ioapic_lock, flags);
2364         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2365                 ioapic_write_entry(dev->id, i, entry[i]);
2366
2367         return 0;
2368 }
2369
2370 static struct sysdev_class ioapic_sysdev_class = {
2371         .name = "ioapic",
2372         .suspend = ioapic_suspend,
2373         .resume = ioapic_resume,
2374 };
2375
2376 static int __init ioapic_init_sysfs(void)
2377 {
2378         struct sys_device * dev;
2379         int i, size, error = 0;
2380
2381         error = sysdev_class_register(&ioapic_sysdev_class);
2382         if (error)
2383                 return error;
2384
2385         for (i = 0; i < nr_ioapics; i++ ) {
2386                 size = sizeof(struct sys_device) + nr_ioapic_registers[i] 
2387                         * sizeof(struct IO_APIC_route_entry);
2388                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2389                 if (!mp_ioapic_data[i]) {
2390                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2391                         continue;
2392                 }
2393                 memset(mp_ioapic_data[i], 0, size);
2394                 dev = &mp_ioapic_data[i]->dev;
2395                 dev->id = i; 
2396                 dev->cls = &ioapic_sysdev_class;
2397                 error = sysdev_register(dev);
2398                 if (error) {
2399                         kfree(mp_ioapic_data[i]);
2400                         mp_ioapic_data[i] = NULL;
2401                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2402                         continue;
2403                 }
2404         }
2405
2406         return 0;
2407 }
2408
2409 device_initcall(ioapic_init_sysfs);
2410
2411 /*
2412  * Dynamic irq allocate and deallocation
2413  */
2414 int create_irq(void)
2415 {
2416         /* Allocate an unused irq */
2417         int irq, new, vector = 0;
2418         unsigned long flags;
2419
2420         irq = -ENOSPC;
2421         spin_lock_irqsave(&vector_lock, flags);
2422         for (new = (NR_IRQS - 1); new >= 0; new--) {
2423                 if (platform_legacy_irq(new))
2424                         continue;
2425                 if (irq_vector[new] != 0)
2426                         continue;
2427                 vector = __assign_irq_vector(new);
2428                 if (likely(vector > 0))
2429                         irq = new;
2430                 break;
2431         }
2432         spin_unlock_irqrestore(&vector_lock, flags);
2433
2434         if (irq >= 0) {
2435                 set_intr_gate(vector, interrupt[irq]);
2436                 dynamic_irq_init(irq);
2437         }
2438         return irq;
2439 }
2440
2441 void destroy_irq(unsigned int irq)
2442 {
2443         unsigned long flags;
2444
2445         dynamic_irq_cleanup(irq);
2446
2447         spin_lock_irqsave(&vector_lock, flags);
2448         irq_vector[irq] = 0;
2449         spin_unlock_irqrestore(&vector_lock, flags);
2450 }
2451
2452 /*
2453  * MSI message composition
2454  */
2455 #ifdef CONFIG_PCI_MSI
2456 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2457 {
2458         int vector;
2459         unsigned dest;
2460
2461         vector = assign_irq_vector(irq);
2462         if (vector >= 0) {
2463                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2464
2465                 msg->address_hi = MSI_ADDR_BASE_HI;
2466                 msg->address_lo =
2467                         MSI_ADDR_BASE_LO |
2468                         ((INT_DEST_MODE == 0) ?
2469                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2470                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2471                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2472                                 MSI_ADDR_REDIRECTION_CPU:
2473                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2474                         MSI_ADDR_DEST_ID(dest);
2475
2476                 msg->data =
2477                         MSI_DATA_TRIGGER_EDGE |
2478                         MSI_DATA_LEVEL_ASSERT |
2479                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2480                                 MSI_DATA_DELIVERY_FIXED:
2481                                 MSI_DATA_DELIVERY_LOWPRI) |
2482                         MSI_DATA_VECTOR(vector);
2483         }
2484         return vector;
2485 }
2486
2487 #ifdef CONFIG_SMP
2488 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2489 {
2490         struct msi_msg msg;
2491         unsigned int dest;
2492         cpumask_t tmp;
2493         int vector;
2494
2495         cpus_and(tmp, mask, cpu_online_map);
2496         if (cpus_empty(tmp))
2497                 tmp = TARGET_CPUS;
2498
2499         vector = assign_irq_vector(irq);
2500         if (vector < 0)
2501                 return;
2502
2503         dest = cpu_mask_to_apicid(mask);
2504
2505         read_msi_msg(irq, &msg);
2506
2507         msg.data &= ~MSI_DATA_VECTOR_MASK;
2508         msg.data |= MSI_DATA_VECTOR(vector);
2509         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2510         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2511
2512         write_msi_msg(irq, &msg);
2513         irq_desc[irq].affinity = mask;
2514 }
2515 #endif /* CONFIG_SMP */
2516
2517 /*
2518  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2519  * which implement the MSI or MSI-X Capability Structure.
2520  */
2521 static struct irq_chip msi_chip = {
2522         .name           = "PCI-MSI",
2523         .unmask         = unmask_msi_irq,
2524         .mask           = mask_msi_irq,
2525         .ack            = ack_ioapic_irq,
2526 #ifdef CONFIG_SMP
2527         .set_affinity   = set_msi_irq_affinity,
2528 #endif
2529         .retrigger      = ioapic_retrigger_irq,
2530 };
2531
2532 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2533 {
2534         struct msi_msg msg;
2535         int irq, ret;
2536         irq = create_irq();
2537         if (irq < 0)
2538                 return irq;
2539
2540         ret = msi_compose_msg(dev, irq, &msg);
2541         if (ret < 0) {
2542                 destroy_irq(irq);
2543                 return ret;
2544         }
2545
2546         set_irq_msi(irq, desc);
2547         write_msi_msg(irq, &msg);
2548
2549         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2550                                       "edge");
2551
2552         return 0;
2553 }
2554
2555 void arch_teardown_msi_irq(unsigned int irq)
2556 {
2557         destroy_irq(irq);
2558 }
2559
2560 #endif /* CONFIG_PCI_MSI */
2561
2562 /*
2563  * Hypertransport interrupt support
2564  */
2565 #ifdef CONFIG_HT_IRQ
2566
2567 #ifdef CONFIG_SMP
2568
2569 static void target_ht_irq(unsigned int irq, unsigned int dest)
2570 {
2571         struct ht_irq_msg msg;
2572         fetch_ht_irq_msg(irq, &msg);
2573
2574         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2575         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2576
2577         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2578         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2579
2580         write_ht_irq_msg(irq, &msg);
2581 }
2582
2583 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2584 {
2585         unsigned int dest;
2586         cpumask_t tmp;
2587
2588         cpus_and(tmp, mask, cpu_online_map);
2589         if (cpus_empty(tmp))
2590                 tmp = TARGET_CPUS;
2591
2592         cpus_and(mask, tmp, CPU_MASK_ALL);
2593
2594         dest = cpu_mask_to_apicid(mask);
2595
2596         target_ht_irq(irq, dest);
2597         irq_desc[irq].affinity = mask;
2598 }
2599 #endif
2600
2601 static struct irq_chip ht_irq_chip = {
2602         .name           = "PCI-HT",
2603         .mask           = mask_ht_irq,
2604         .unmask         = unmask_ht_irq,
2605         .ack            = ack_ioapic_irq,
2606 #ifdef CONFIG_SMP
2607         .set_affinity   = set_ht_irq_affinity,
2608 #endif
2609         .retrigger      = ioapic_retrigger_irq,
2610 };
2611
2612 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2613 {
2614         int vector;
2615
2616         vector = assign_irq_vector(irq);
2617         if (vector >= 0) {
2618                 struct ht_irq_msg msg;
2619                 unsigned dest;
2620                 cpumask_t tmp;
2621
2622                 cpus_clear(tmp);
2623                 cpu_set(vector >> 8, tmp);
2624                 dest = cpu_mask_to_apicid(tmp);
2625
2626                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2627
2628                 msg.address_lo =
2629                         HT_IRQ_LOW_BASE |
2630                         HT_IRQ_LOW_DEST_ID(dest) |
2631                         HT_IRQ_LOW_VECTOR(vector) |
2632                         ((INT_DEST_MODE == 0) ?
2633                                 HT_IRQ_LOW_DM_PHYSICAL :
2634                                 HT_IRQ_LOW_DM_LOGICAL) |
2635                         HT_IRQ_LOW_RQEOI_EDGE |
2636                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2637                                 HT_IRQ_LOW_MT_FIXED :
2638                                 HT_IRQ_LOW_MT_ARBITRATED) |
2639                         HT_IRQ_LOW_IRQ_MASKED;
2640
2641                 write_ht_irq_msg(irq, &msg);
2642
2643                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2644                                               handle_edge_irq, "edge");
2645         }
2646         return vector;
2647 }
2648 #endif /* CONFIG_HT_IRQ */
2649
2650 /* --------------------------------------------------------------------------
2651                           ACPI-based IOAPIC Configuration
2652    -------------------------------------------------------------------------- */
2653
2654 #ifdef CONFIG_ACPI
2655
2656 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2657 {
2658         union IO_APIC_reg_00 reg_00;
2659         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2660         physid_mask_t tmp;
2661         unsigned long flags;
2662         int i = 0;
2663
2664         /*
2665          * The P4 platform supports up to 256 APIC IDs on two separate APIC 
2666          * buses (one for LAPICs, one for IOAPICs), where predecessors only 
2667          * supports up to 16 on one shared APIC bus.
2668          * 
2669          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2670          *      advantage of new APIC bus architecture.
2671          */
2672
2673         if (physids_empty(apic_id_map))
2674                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2675
2676         spin_lock_irqsave(&ioapic_lock, flags);
2677         reg_00.raw = io_apic_read(ioapic, 0);
2678         spin_unlock_irqrestore(&ioapic_lock, flags);
2679
2680         if (apic_id >= get_physical_broadcast()) {
2681                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2682                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2683                 apic_id = reg_00.bits.ID;
2684         }
2685
2686         /*
2687          * Every APIC in a system must have a unique ID or we get lots of nice 
2688          * 'stuck on smp_invalidate_needed IPI wait' messages.
2689          */
2690         if (check_apicid_used(apic_id_map, apic_id)) {
2691
2692                 for (i = 0; i < get_physical_broadcast(); i++) {
2693                         if (!check_apicid_used(apic_id_map, i))
2694                                 break;
2695                 }
2696
2697                 if (i == get_physical_broadcast())
2698                         panic("Max apic_id exceeded!\n");
2699
2700                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2701                         "trying %d\n", ioapic, apic_id, i);
2702
2703                 apic_id = i;
2704         } 
2705
2706         tmp = apicid_to_cpu_present(apic_id);
2707         physids_or(apic_id_map, apic_id_map, tmp);
2708
2709         if (reg_00.bits.ID != apic_id) {
2710                 reg_00.bits.ID = apic_id;
2711
2712                 spin_lock_irqsave(&ioapic_lock, flags);
2713                 io_apic_write(ioapic, 0, reg_00.raw);
2714                 reg_00.raw = io_apic_read(ioapic, 0);
2715                 spin_unlock_irqrestore(&ioapic_lock, flags);
2716
2717                 /* Sanity check */
2718                 if (reg_00.bits.ID != apic_id) {
2719                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2720                         return -1;
2721                 }
2722         }
2723
2724         apic_printk(APIC_VERBOSE, KERN_INFO
2725                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2726
2727         return apic_id;
2728 }
2729
2730
2731 int __init io_apic_get_version (int ioapic)
2732 {
2733         union IO_APIC_reg_01    reg_01;
2734         unsigned long flags;
2735
2736         spin_lock_irqsave(&ioapic_lock, flags);
2737         reg_01.raw = io_apic_read(ioapic, 1);
2738         spin_unlock_irqrestore(&ioapic_lock, flags);
2739
2740         return reg_01.bits.version;
2741 }
2742
2743
2744 int __init io_apic_get_redir_entries (int ioapic)
2745 {
2746         union IO_APIC_reg_01    reg_01;
2747         unsigned long flags;
2748
2749         spin_lock_irqsave(&ioapic_lock, flags);
2750         reg_01.raw = io_apic_read(ioapic, 1);
2751         spin_unlock_irqrestore(&ioapic_lock, flags);
2752
2753         return reg_01.bits.entries;
2754 }
2755
2756
2757 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2758 {
2759         struct IO_APIC_route_entry entry;
2760         unsigned long flags;
2761
2762         if (!IO_APIC_IRQ(irq)) {
2763                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2764                         ioapic);
2765                 return -EINVAL;
2766         }
2767
2768         /*
2769          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2770          * Note that we mask (disable) IRQs now -- these get enabled when the
2771          * corresponding device driver registers for this IRQ.
2772          */
2773
2774         memset(&entry,0,sizeof(entry));
2775
2776         entry.delivery_mode = INT_DELIVERY_MODE;
2777         entry.dest_mode = INT_DEST_MODE;
2778         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2779         entry.trigger = edge_level;
2780         entry.polarity = active_high_low;
2781         entry.mask  = 1;
2782
2783         /*
2784          * IRQs < 16 are already in the irq_2_pin[] map
2785          */
2786         if (irq >= 16)
2787                 add_pin_to_irq(irq, ioapic, pin);
2788
2789         entry.vector = assign_irq_vector(irq);
2790
2791         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2792                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2793                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2794                 edge_level, active_high_low);
2795
2796         ioapic_register_intr(irq, entry.vector, edge_level);
2797
2798         if (!ioapic && (irq < 16))
2799                 disable_8259A_irq(irq);
2800
2801         spin_lock_irqsave(&ioapic_lock, flags);
2802         __ioapic_write_entry(ioapic, pin, entry);
2803         spin_unlock_irqrestore(&ioapic_lock, flags);
2804
2805         return 0;
2806 }
2807
2808 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2809 {
2810         int i;
2811
2812         if (skip_ioapic_setup)
2813                 return -1;
2814
2815         for (i = 0; i < mp_irq_entries; i++)
2816                 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2817                     mp_irqs[i].mpc_srcbusirq == bus_irq)
2818                         break;
2819         if (i >= mp_irq_entries)
2820                 return -1;
2821
2822         *trigger = irq_trigger(i);
2823         *polarity = irq_polarity(i);
2824         return 0;
2825 }
2826
2827 #endif /* CONFIG_ACPI */
2828
2829 static int __init parse_disable_timer_pin_1(char *arg)
2830 {
2831         disable_timer_pin_1 = 1;
2832         return 0;
2833 }
2834 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2835
2836 static int __init parse_enable_timer_pin_1(char *arg)
2837 {
2838         disable_timer_pin_1 = -1;
2839         return 0;
2840 }
2841 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2842
2843 static int __init parse_noapic(char *arg)
2844 {
2845         /* disable IO-APIC */
2846         disable_ioapic_setup();
2847         return 0;
2848 }
2849 early_param("noapic", parse_noapic);