arch/x86/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/export.h>
   5 #include <linux/delay.h>
   6 #include <linux/errno.h>
   7 #include <linux/i8253.h>
   8 #include <linux/slab.h>
   9 #include <linux/hpet.h>
  10 #include <linux/init.h>
  11 #include <linux/cpu.h>
  12 #include <linux/pm.h>
  13 #include <linux/io.h>
  14
  15 #include <asm/fixmap.h>
  16 #include <asm/hpet.h>
  17 #include <asm/time.h>
  18
  19 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
  20
  21 /* FSEC = 10^-15
  22    NSEC = 10^-9 */
  23 #define FSEC_PER_NSEC                   1000000L
  24
  25 #define HPET_DEV_USED_BIT               2
  26 #define HPET_DEV_USED                   (1 << HPET_DEV_USED_BIT)
  27 #define HPET_DEV_VALID                  0x8
  28 #define HPET_DEV_FSB_CAP                0x1000
  29 #define HPET_DEV_PERI_CAP               0x2000
  30
  31 #define HPET_MIN_CYCLES                 128
  32 #define HPET_MIN_PROG_DELTA             (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
  33
  34 /*
  35  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  36  */
  37 unsigned long                           hpet_address;
  38 u8                                      hpet_blockid; /* OS timer block num */
  39 u8                                      hpet_msi_disable;
  40
  41 #ifdef CONFIG_PCI_MSI
  42 static unsigned long                    hpet_num_timers;
  43 #endif
  44 static void __iomem                     *hpet_virt_address;
  45
  46 struct hpet_dev {
  47         struct clock_event_device       evt;
  48         unsigned int                    num;
  49         int                             cpu;
  50         unsigned int                    irq;
  51         unsigned int                    flags;
  52         char                            name[10];
  53 };
  54
  55 inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
  56 {
  57         return container_of(evtdev, struct hpet_dev, evt);
  58 }
  59
  60 inline unsigned int hpet_readl(unsigned int a)
  61 {
  62         return readl(hpet_virt_address + a);
  63 }
  64
  65 static inline void hpet_writel(unsigned int d, unsigned int a)
  66 {
  67         writel(d, hpet_virt_address + a);
  68 }
  69
  70 #ifdef CONFIG_X86_64
  71 #include <asm/pgtable.h>
  72 #endif
  73
  74 static inline void hpet_set_mapping(void)
  75 {
  76         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
  77 #ifdef CONFIG_X86_64
  78         __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
  79 #endif
  80 }
  81
  82 static inline void hpet_clear_mapping(void)
  83 {
  84         iounmap(hpet_virt_address);
  85         hpet_virt_address = NULL;
  86 }
  87
  88 /*
  89  * HPET command line enable / disable
  90  */
  91 static int boot_hpet_disable;
  92 int hpet_force_user;
  93 static int hpet_verbose;
  94
  95 static int __init hpet_setup(char *str)
  96 {
  97         while (str) {
  98                 char *next = strchr(str, ',');
  99
 100                 if (next)
 101                         *next++ = 0;
 102                 if (!strncmp("disable", str, 7))
 103                         boot_hpet_disable = 1;
 104                 if (!strncmp("force", str, 5))
 105                         hpet_force_user = 1;
 106                 if (!strncmp("verbose", str, 7))
 107                         hpet_verbose = 1;
 108                 str = next;
 109         }
 110         return 1;
 111 }
 112 __setup("hpet=", hpet_setup);
 113
 114 static int __init disable_hpet(char *str)
 115 {
 116         boot_hpet_disable = 1;
 117         return 1;
 118 }
 119 __setup("nohpet", disable_hpet);
 120
 121 static inline int is_hpet_capable(void)
 122 {
 123         return !boot_hpet_disable && hpet_address;
 124 }
 125
 126 /*
 127  * HPET timer interrupt enable / disable
 128  */
 129 static int hpet_legacy_int_enabled;
 130
 131 /**
 132  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 133  */
 134 int is_hpet_enabled(void)
 135 {
 136         return is_hpet_capable() && hpet_legacy_int_enabled;
 137 }
 138 EXPORT_SYMBOL_GPL(is_hpet_enabled);
 139
 140 static void _hpet_print_config(const char *function, int line)
 141 {
 142         u32 i, timers, l, h;
 143         printk(KERN_INFO "hpet: %s(%d):\n", function, line);
 144         l = hpet_readl(HPET_ID);
 145         h = hpet_readl(HPET_PERIOD);
 146         timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 147         printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
 148         l = hpet_readl(HPET_CFG);
 149         h = hpet_readl(HPET_STATUS);
 150         printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
 151         l = hpet_readl(HPET_COUNTER);
 152         h = hpet_readl(HPET_COUNTER+4);
 153         printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
 154
 155         for (i = 0; i < timers; i++) {
 156                 l = hpet_readl(HPET_Tn_CFG(i));
 157                 h = hpet_readl(HPET_Tn_CFG(i)+4);
 158                 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
 159                        i, l, h);
 160                 l = hpet_readl(HPET_Tn_CMP(i));
 161                 h = hpet_readl(HPET_Tn_CMP(i)+4);
 162                 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
 163                        i, l, h);
 164                 l = hpet_readl(HPET_Tn_ROUTE(i));
 165                 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
 166                 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
 167                        i, l, h);
 168         }
 169 }
 170
 171 #define hpet_print_config()                                     \
 172 do {                                                            \
 173         if (hpet_verbose)                                       \
 174                 _hpet_print_config(__FUNCTION__, __LINE__);     \
 175 } while (0)
 176
 177 /*
 178  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 179  * timer 0 and timer 1 in case of RTC emulation.
 180  */
 181 #ifdef CONFIG_HPET
 182
 183 static void hpet_reserve_msi_timers(struct hpet_data *hd);
 184
 185 static void hpet_reserve_platform_timers(unsigned int id)
 186 {
 187         struct hpet __iomem *hpet = hpet_virt_address;
 188         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
 189         unsigned int nrtimers, i;
 190         struct hpet_data hd;
 191
 192         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 193
 194         memset(&hd, 0, sizeof(hd));
 195         hd.hd_phys_address      = hpet_address;
 196         hd.hd_address           = hpet;
 197         hd.hd_nirqs             = nrtimers;
 198         hpet_reserve_timer(&hd, 0);
 199
 200 #ifdef CONFIG_HPET_EMULATE_RTC
 201         hpet_reserve_timer(&hd, 1);
 202 #endif
 203
 204         /*
 205          * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
 206          * is wrong for i8259!) not the output IRQ.  Many BIOS writers
 207          * don't bother configuring *any* comparator interrupts.
 208          */
 209         hd.hd_irq[0] = HPET_LEGACY_8254;
 210         hd.hd_irq[1] = HPET_LEGACY_RTC;
 211
 212         for (i = 2; i < nrtimers; timer++, i++) {
 213                 hd.hd_irq[i] = (readl(&timer->hpet_config) &
 214                         Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
 215         }
 216
 217         hpet_reserve_msi_timers(&hd);
 218
 219         hpet_alloc(&hd);
 220
 221 }
 222 #else
 223 static void hpet_reserve_platform_timers(unsigned int id) { }
 224 #endif
 225
 226 /*
 227  * Common hpet info
 228  */
 229 static unsigned long hpet_freq;
 230
 231 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 232                           struct clock_event_device *evt);
 233 static int hpet_legacy_next_event(unsigned long delta,
 234                            struct clock_event_device *evt);
 235
 236 /*
 237  * The hpet clock event device
 238  */
 239 static struct clock_event_device hpet_clockevent = {
 240         .name           = "hpet",
 241         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 242         .set_mode       = hpet_legacy_set_mode,
 243         .set_next_event = hpet_legacy_next_event,
 244         .irq            = 0,
 245         .rating         = 50,
 246 };
 247
 248 static void hpet_stop_counter(void)
 249 {
 250         unsigned long cfg = hpet_readl(HPET_CFG);
 251         cfg &= ~HPET_CFG_ENABLE;
 252         hpet_writel(cfg, HPET_CFG);
 253 }
 254
 255 static void hpet_reset_counter(void)
 256 {
 257         hpet_writel(0, HPET_COUNTER);
 258         hpet_writel(0, HPET_COUNTER + 4);
 259 }
 260
 261 static void hpet_start_counter(void)
 262 {
 263         unsigned int cfg = hpet_readl(HPET_CFG);
 264         cfg |= HPET_CFG_ENABLE;
 265         hpet_writel(cfg, HPET_CFG);
 266 }
 267
 268 static void hpet_restart_counter(void)
 269 {
 270         hpet_stop_counter();
 271         hpet_reset_counter();
 272         hpet_start_counter();
 273 }
 274
 275 static void hpet_resume_device(void)
 276 {
 277         force_hpet_resume();
 278 }
 279
 280 static void hpet_resume_counter(struct clocksource *cs)
 281 {
 282         hpet_resume_device();
 283         hpet_restart_counter();
 284 }
 285
 286 static void hpet_enable_legacy_int(void)
 287 {
 288         unsigned int cfg = hpet_readl(HPET_CFG);
 289
 290         cfg |= HPET_CFG_LEGACY;
 291         hpet_writel(cfg, HPET_CFG);
 292         hpet_legacy_int_enabled = 1;
 293 }
 294
 295 static void hpet_legacy_clockevent_register(void)
 296 {
 297         /* Start HPET legacy interrupts */
 298         hpet_enable_legacy_int();
 299
 300         /*
 301          * Start hpet with the boot cpu mask and make it
 302          * global after the IO_APIC has been initialized.
 303          */
 304         hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
 305         clockevents_config_and_register(&hpet_clockevent, hpet_freq,
 306                                         HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
 307         global_clock_event = &hpet_clockevent;
 308         printk(KERN_DEBUG "hpet clockevent registered\n");
 309 }
 310
 311 static int hpet_setup_msi_irq(unsigned int irq);
 312
 313 static void hpet_set_mode(enum clock_event_mode mode,
 314                           struct clock_event_device *evt, int timer)
 315 {
 316         unsigned int cfg, cmp, now;
 317         uint64_t delta;
 318
 319         switch (mode) {
 320         case CLOCK_EVT_MODE_PERIODIC:
 321                 hpet_stop_counter();
 322                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
 323                 delta >>= evt->shift;
 324                 now = hpet_readl(HPET_COUNTER);
 325                 cmp = now + (unsigned int) delta;
 326                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 327                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
 328                        HPET_TN_SETVAL | HPET_TN_32BIT;
 329                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 330                 hpet_writel(cmp, HPET_Tn_CMP(timer));
 331                 udelay(1);
 332                 /*
 333                  * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
 334                  * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
 335                  * bit is automatically cleared after the first write.
 336                  * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
 337                  * Publication # 24674)
 338                  */
 339                 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
 340                 hpet_start_counter();
 341                 hpet_print_config();
 342                 break;
 343
 344         case CLOCK_EVT_MODE_ONESHOT:
 345                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 346                 cfg &= ~HPET_TN_PERIODIC;
 347                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 348                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 349                 break;
 350
 351         case CLOCK_EVT_MODE_UNUSED:
 352         case CLOCK_EVT_MODE_SHUTDOWN:
 353                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 354                 cfg &= ~HPET_TN_ENABLE;
 355                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 356                 break;
 357
 358         case CLOCK_EVT_MODE_RESUME:
 359                 if (timer == 0) {
 360                         hpet_enable_legacy_int();
 361                 } else {
 362                         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 363                         hpet_setup_msi_irq(hdev->irq);
 364                         disable_irq(hdev->irq);
 365                         irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
 366                         enable_irq(hdev->irq);
 367                 }
 368                 hpet_print_config();
 369                 break;
 370         }
 371 }
 372
 373 static int hpet_next_event(unsigned long delta,
 374                            struct clock_event_device *evt, int timer)
 375 {
 376         u32 cnt;
 377         s32 res;
 378
 379         cnt = hpet_readl(HPET_COUNTER);
 380         cnt += (u32) delta;
 381         hpet_writel(cnt, HPET_Tn_CMP(timer));
 382
 383         /*
 384          * HPETs are a complete disaster. The compare register is
 385          * based on a equal comparison and neither provides a less
 386          * than or equal functionality (which would require to take
 387          * the wraparound into account) nor a simple count down event
 388          * mode. Further the write to the comparator register is
 389          * delayed internally up to two HPET clock cycles in certain
 390          * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
 391          * longer delays. We worked around that by reading back the
 392          * compare register, but that required another workaround for
 393          * ICH9,10 chips where the first readout after write can
 394          * return the old stale value. We already had a minimum
 395          * programming delta of 5us enforced, but a NMI or SMI hitting
 396          * between the counter readout and the comparator write can
 397          * move us behind that point easily. Now instead of reading
 398          * the compare register back several times, we make the ETIME
 399          * decision based on the following: Return ETIME if the
 400          * counter value after the write is less than HPET_MIN_CYCLES
 401          * away from the event or if the counter is already ahead of
 402          * the event. The minimum programming delta for the generic
 403          * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
 404          */
 405         res = (s32)(cnt - hpet_readl(HPET_COUNTER));
 406
 407         return res < HPET_MIN_CYCLES ? -ETIME : 0;
 408 }
 409
 410 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 411                         struct clock_event_device *evt)
 412 {
 413         hpet_set_mode(mode, evt, 0);
 414 }
 415
 416 static int hpet_legacy_next_event(unsigned long delta,
 417                         struct clock_event_device *evt)
 418 {
 419         return hpet_next_event(delta, evt, 0);
 420 }
 421
 422 /*
 423  * HPET MSI Support
 424  */
 425 #ifdef CONFIG_PCI_MSI
 426
 427 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
 428 static struct hpet_dev  *hpet_devs;
 429
 430 void hpet_msi_unmask(struct irq_data *data)
 431 {
 432         struct hpet_dev *hdev = data->handler_data;
 433         unsigned int cfg;
 434
 435         /* unmask it */
 436         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 437         cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
 438         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 439 }
 440
 441 void hpet_msi_mask(struct irq_data *data)
 442 {
 443         struct hpet_dev *hdev = data->handler_data;
 444         unsigned int cfg;
 445
 446         /* mask it */
 447         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 448         cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
 449         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 450 }
 451
 452 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
 453 {
 454         hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
 455         hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
 456 }
 457
 458 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
 459 {
 460         msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
 461         msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
 462         msg->address_hi = 0;
 463 }
 464
 465 static void hpet_msi_set_mode(enum clock_event_mode mode,
 466                                 struct clock_event_device *evt)
 467 {
 468         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 469         hpet_set_mode(mode, evt, hdev->num);
 470 }
 471
 472 static int hpet_msi_next_event(unsigned long delta,
 473                                 struct clock_event_device *evt)
 474 {
 475         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 476         return hpet_next_event(delta, evt, hdev->num);
 477 }
 478
 479 static int hpet_setup_msi_irq(unsigned int irq)
 480 {
 481         if (x86_msi.setup_hpet_msi(irq, hpet_blockid)) {
 482                 destroy_irq(irq);
 483                 return -EINVAL;
 484         }
 485         return 0;
 486 }
 487
 488 static int hpet_assign_irq(struct hpet_dev *dev)
 489 {
 490         unsigned int irq;
 491
 492         irq = create_irq_nr(0, -1);
 493         if (!irq)
 494                 return -EINVAL;
 495
 496         irq_set_handler_data(irq, dev);
 497
 498         if (hpet_setup_msi_irq(irq))
 499                 return -EINVAL;
 500
 501         dev->irq = irq;
 502         return 0;
 503 }
 504
 505 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
 506 {
 507         struct hpet_dev *dev = (struct hpet_dev *)data;
 508         struct clock_event_device *hevt = &dev->evt;
 509
 510         if (!hevt->event_handler) {
 511                 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
 512                                 dev->num);
 513                 return IRQ_HANDLED;
 514         }
 515
 516         hevt->event_handler(hevt);
 517         return IRQ_HANDLED;
 518 }
 519
 520 static int hpet_setup_irq(struct hpet_dev *dev)
 521 {
 522
 523         if (request_irq(dev->irq, hpet_interrupt_handler,
 524                         IRQF_TIMER | IRQF_NOBALANCING,
 525                         dev->name, dev))
 526                 return -1;
 527
 528         disable_irq(dev->irq);
 529         irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
 530         enable_irq(dev->irq);
 531
 532         printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
 533                          dev->name, dev->irq);
 534
 535         return 0;
 536 }
 537
 538 /* This should be called in specific @cpu */
 539 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
 540 {
 541         struct clock_event_device *evt = &hdev->evt;
 542
 543         WARN_ON(cpu != smp_processor_id());
 544         if (!(hdev->flags & HPET_DEV_VALID))
 545                 return;
 546
 547         if (hpet_setup_msi_irq(hdev->irq))
 548                 return;
 549
 550         hdev->cpu = cpu;
 551         per_cpu(cpu_hpet_dev, cpu) = hdev;
 552         evt->name = hdev->name;
 553         hpet_setup_irq(hdev);
 554         evt->irq = hdev->irq;
 555
 556         evt->rating = 110;
 557         evt->features = CLOCK_EVT_FEAT_ONESHOT;
 558         if (hdev->flags & HPET_DEV_PERI_CAP)
 559                 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
 560
 561         evt->set_mode = hpet_msi_set_mode;
 562         evt->set_next_event = hpet_msi_next_event;
 563         evt->cpumask = cpumask_of(hdev->cpu);
 564
 565         clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
 566                                         0x7FFFFFFF);
 567 }
 568
 569 #ifdef CONFIG_HPET
 570 /* Reserve at least one timer for userspace (/dev/hpet) */
 571 #define RESERVE_TIMERS 1
 572 #else
 573 #define RESERVE_TIMERS 0
 574 #endif
 575
 576 static void hpet_msi_capability_lookup(unsigned int start_timer)
 577 {
 578         unsigned int id;
 579         unsigned int num_timers;
 580         unsigned int num_timers_used = 0;
 581         int i;
 582
 583         if (hpet_msi_disable)
 584                 return;
 585
 586         if (boot_cpu_has(X86_FEATURE_ARAT))
 587                 return;
 588         id = hpet_readl(HPET_ID);
 589
 590         num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 591         num_timers++; /* Value read out starts from 0 */
 592         hpet_print_config();
 593
 594         hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
 595         if (!hpet_devs)
 596                 return;
 597
 598         hpet_num_timers = num_timers;
 599
 600         for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
 601                 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
 602                 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
 603
 604                 /* Only consider HPET timer with MSI support */
 605                 if (!(cfg & HPET_TN_FSB_CAP))
 606                         continue;
 607
 608                 hdev->flags = 0;
 609                 if (cfg & HPET_TN_PERIODIC_CAP)
 610                         hdev->flags |= HPET_DEV_PERI_CAP;
 611                 hdev->num = i;
 612
 613                 sprintf(hdev->name, "hpet%d", i);
 614                 if (hpet_assign_irq(hdev))
 615                         continue;
 616
 617                 hdev->flags |= HPET_DEV_FSB_CAP;
 618                 hdev->flags |= HPET_DEV_VALID;
 619                 num_timers_used++;
 620                 if (num_timers_used == num_possible_cpus())
 621                         break;
 622         }
 623
 624         printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
 625                 num_timers, num_timers_used);
 626 }
 627
 628 #ifdef CONFIG_HPET
 629 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 630 {
 631         int i;
 632
 633         if (!hpet_devs)
 634                 return;
 635
 636         for (i = 0; i < hpet_num_timers; i++) {
 637                 struct hpet_dev *hdev = &hpet_devs[i];
 638
 639                 if (!(hdev->flags & HPET_DEV_VALID))
 640                         continue;
 641
 642                 hd->hd_irq[hdev->num] = hdev->irq;
 643                 hpet_reserve_timer(hd, hdev->num);
 644         }
 645 }
 646 #endif
 647
 648 static struct hpet_dev *hpet_get_unused_timer(void)
 649 {
 650         int i;
 651
 652         if (!hpet_devs)
 653                 return NULL;
 654
 655         for (i = 0; i < hpet_num_timers; i++) {
 656                 struct hpet_dev *hdev = &hpet_devs[i];
 657
 658                 if (!(hdev->flags & HPET_DEV_VALID))
 659                         continue;
 660                 if (test_and_set_bit(HPET_DEV_USED_BIT,
 661                         (unsigned long *)&hdev->flags))
 662                         continue;
 663                 return hdev;
 664         }
 665         return NULL;
 666 }
 667
 668 struct hpet_work_struct {
 669         struct delayed_work work;
 670         struct completion complete;
 671 };
 672
 673 static void hpet_work(struct work_struct *w)
 674 {
 675         struct hpet_dev *hdev;
 676         int cpu = smp_processor_id();
 677         struct hpet_work_struct *hpet_work;
 678
 679         hpet_work = container_of(w, struct hpet_work_struct, work.work);
 680
 681         hdev = hpet_get_unused_timer();
 682         if (hdev)
 683                 init_one_hpet_msi_clockevent(hdev, cpu);
 684
 685         complete(&hpet_work->complete);
 686 }
 687
 688 static int hpet_cpuhp_notify(struct notifier_block *n,
 689                 unsigned long action, void *hcpu)
 690 {
 691         unsigned long cpu = (unsigned long)hcpu;
 692         struct hpet_work_struct work;
 693         struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
 694
 695         switch (action & 0xf) {
 696         case CPU_ONLINE:
 697                 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
 698                 init_completion(&work.complete);
 699                 /* FIXME: add schedule_work_on() */
 700                 schedule_delayed_work_on(cpu, &work.work, 0);
 701                 wait_for_completion(&work.complete);
 702                 destroy_delayed_work_on_stack(&work.work);
 703                 break;
 704         case CPU_DEAD:
 705                 if (hdev) {
 706                         free_irq(hdev->irq, hdev);
 707                         hdev->flags &= ~HPET_DEV_USED;
 708                         per_cpu(cpu_hpet_dev, cpu) = NULL;
 709                 }
 710                 break;
 711         }
 712         return NOTIFY_OK;
 713 }
 714 #else
 715
 716 static int hpet_setup_msi_irq(unsigned int irq)
 717 {
 718         return 0;
 719 }
 720 static void hpet_msi_capability_lookup(unsigned int start_timer)
 721 {
 722         return;
 723 }
 724
 725 #ifdef CONFIG_HPET
 726 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 727 {
 728         return;
 729 }
 730 #endif
 731
 732 static int hpet_cpuhp_notify(struct notifier_block *n,
 733                 unsigned long action, void *hcpu)
 734 {
 735         return NOTIFY_OK;
 736 }
 737
 738 #endif
 739
 740 /*
 741  * Clock source related code
 742  */
 743 static cycle_t read_hpet(struct clocksource *cs)
 744 {
 745         return (cycle_t)hpet_readl(HPET_COUNTER);
 746 }
 747
 748 static struct clocksource clocksource_hpet = {
 749         .name           = "hpet",
 750         .rating         = 250,
 751         .read           = read_hpet,
 752         .mask           = HPET_MASK,
 753         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 754         .resume         = hpet_resume_counter,
 755 #ifdef CONFIG_X86_64
 756         .archdata       = { .vclock_mode = VCLOCK_HPET },
 757 #endif
 758 };
 759
 760 static int hpet_clocksource_register(void)
 761 {
 762         u64 start, now;
 763         cycle_t t1;
 764
 765         /* Start the counter */
 766         hpet_restart_counter();
 767
 768         /* Verify whether hpet counter works */
 769         t1 = hpet_readl(HPET_COUNTER);
 770         rdtscll(start);
 771
 772         /*
 773          * We don't know the TSC frequency yet, but waiting for
 774          * 200000 TSC cycles is safe:
 775          * 4 GHz == 50us
 776          * 1 GHz == 200us
 777          */
 778         do {
 779                 rep_nop();
 780                 rdtscll(now);
 781         } while ((now - start) < 200000UL);
 782
 783         if (t1 == hpet_readl(HPET_COUNTER)) {
 784                 printk(KERN_WARNING
 785                        "HPET counter not counting. HPET disabled\n");
 786                 return -ENODEV;
 787         }
 788
 789         clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
 790         return 0;
 791 }
 792
 793 static u32 *hpet_boot_cfg;
 794
 795 /**
 796  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
 797  */
 798 int __init hpet_enable(void)
 799 {
 800         u32 hpet_period, cfg, id;
 801         u64 freq;
 802         unsigned int i, last;
 803
 804         if (!is_hpet_capable())
 805                 return 0;
 806
 807         hpet_set_mapping();
 808
 809         /*
 810          * Read the period and check for a sane value:
 811          */
 812         hpet_period = hpet_readl(HPET_PERIOD);
 813
 814         /*
 815          * AMD SB700 based systems with spread spectrum enabled use a
 816          * SMM based HPET emulation to provide proper frequency
 817          * setting. The SMM code is initialized with the first HPET
 818          * register access and takes some time to complete. During
 819          * this time the config register reads 0xffffffff. We check
 820          * for max. 1000 loops whether the config register reads a non
 821          * 0xffffffff value to make sure that HPET is up and running
 822          * before we go further. A counting loop is safe, as the HPET
 823          * access takes thousands of CPU cycles. On non SB700 based
 824          * machines this check is only done once and has no side
 825          * effects.
 826          */
 827         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
 828                 if (i == 1000) {
 829                         printk(KERN_WARNING
 830                                "HPET config register value = 0xFFFFFFFF. "
 831                                "Disabling HPET\n");
 832                         goto out_nohpet;
 833                 }
 834         }
 835
 836         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 837                 goto out_nohpet;
 838
 839         /*
 840          * The period is a femto seconds value. Convert it to a
 841          * frequency.
 842          */
 843         freq = FSEC_PER_SEC;
 844         do_div(freq, hpet_period);
 845         hpet_freq = freq;
 846
 847         /*
 848          * Read the HPET ID register to retrieve the IRQ routing
 849          * information and the number of channels
 850          */
 851         id = hpet_readl(HPET_ID);
 852         hpet_print_config();
 853
 854         last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
 855
 856 #ifdef CONFIG_HPET_EMULATE_RTC
 857         /*
 858          * The legacy routing mode needs at least two channels, tick timer
 859          * and the rtc emulation channel.
 860          */
 861         if (!last)
 862                 goto out_nohpet;
 863 #endif
 864
 865         cfg = hpet_readl(HPET_CFG);
 866         hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
 867                                 GFP_KERNEL);
 868         if (hpet_boot_cfg)
 869                 *hpet_boot_cfg = cfg;
 870         else
 871                 pr_warn("HPET initial state will not be saved\n");
 872         cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
 873         hpet_writel(cfg, HPET_CFG);
 874         if (cfg)
 875                 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
 876                         cfg);
 877
 878         for (i = 0; i <= last; ++i) {
 879                 cfg = hpet_readl(HPET_Tn_CFG(i));
 880                 if (hpet_boot_cfg)
 881                         hpet_boot_cfg[i + 1] = cfg;
 882                 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
 883                 hpet_writel(cfg, HPET_Tn_CFG(i));
 884                 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
 885                          | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
 886                          | HPET_TN_FSB | HPET_TN_FSB_CAP);
 887                 if (cfg)
 888                         pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
 889                                 cfg, i);
 890         }
 891         hpet_print_config();
 892
 893         if (hpet_clocksource_register())
 894                 goto out_nohpet;
 895
 896         if (id & HPET_ID_LEGSUP) {
 897                 hpet_legacy_clockevent_register();
 898                 return 1;
 899         }
 900         return 0;
 901
 902 out_nohpet:
 903         hpet_clear_mapping();
 904         hpet_address = 0;
 905         return 0;
 906 }
 907
 908 /*
 909  * Needs to be late, as the reserve_timer code calls kalloc !
 910  *
 911  * Not a problem on i386 as hpet_enable is called from late_time_init,
 912  * but on x86_64 it is necessary !
 913  */
 914 static __init int hpet_late_init(void)
 915 {
 916         int cpu;
 917
 918         if (boot_hpet_disable)
 919                 return -ENODEV;
 920
 921         if (!hpet_address) {
 922                 if (!force_hpet_address)
 923                         return -ENODEV;
 924
 925                 hpet_address = force_hpet_address;
 926                 hpet_enable();
 927         }
 928
 929         if (!hpet_virt_address)
 930                 return -ENODEV;
 931
 932         if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
 933                 hpet_msi_capability_lookup(2);
 934         else
 935                 hpet_msi_capability_lookup(0);
 936
 937         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
 938         hpet_print_config();
 939
 940         if (hpet_msi_disable)
 941                 return 0;
 942
 943         if (boot_cpu_has(X86_FEATURE_ARAT))
 944                 return 0;
 945
 946         for_each_online_cpu(cpu) {
 947                 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
 948         }
 949
 950         /* This notifier should be called after workqueue is ready */
 951         hotcpu_notifier(hpet_cpuhp_notify, -20);
 952
 953         return 0;
 954 }
 955 fs_initcall(hpet_late_init);
 956
 957 void hpet_disable(void)
 958 {
 959         if (is_hpet_capable() && hpet_virt_address) {
 960                 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
 961
 962                 if (hpet_boot_cfg)
 963                         cfg = *hpet_boot_cfg;
 964                 else if (hpet_legacy_int_enabled) {
 965                         cfg &= ~HPET_CFG_LEGACY;
 966                         hpet_legacy_int_enabled = 0;
 967                 }
 968                 cfg &= ~HPET_CFG_ENABLE;
 969                 hpet_writel(cfg, HPET_CFG);
 970
 971                 if (!hpet_boot_cfg)
 972                         return;
 973
 974                 id = hpet_readl(HPET_ID);
 975                 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 976
 977                 for (id = 0; id <= last; ++id)
 978                         hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
 979
 980                 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
 981                         hpet_writel(*hpet_boot_cfg, HPET_CFG);
 982         }
 983 }
 984
 985 #ifdef CONFIG_HPET_EMULATE_RTC
 986
 987 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 988  * is enabled, we support RTC interrupt functionality in software.
 989  * RTC has 3 kinds of interrupts:
 990  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 991  *    is updated
 992  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 993  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 994  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 995  * (1) and (2) above are implemented using polling at a frequency of
 996  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 997  * overhead. (DEFAULT_RTC_INT_FREQ)
 998  * For (3), we use interrupts at 64Hz or user specified periodic
 999  * frequency, whichever is higher.
1000  */
1001 #include <linux/mc146818rtc.h>
1002 #include <linux/rtc.h>
1003 #include <asm/rtc.h>
1004
1005 #define DEFAULT_RTC_INT_FREQ    64
1006 #define DEFAULT_RTC_SHIFT       6
1007 #define RTC_NUM_INTS            1
1008
1009 static unsigned long hpet_rtc_flags;
1010 static int hpet_prev_update_sec;
1011 static struct rtc_time hpet_alarm_time;
1012 static unsigned long hpet_pie_count;
1013 static u32 hpet_t1_cmp;
1014 static u32 hpet_default_delta;
1015 static u32 hpet_pie_delta;
1016 static unsigned long hpet_pie_limit;
1017
1018 static rtc_irq_handler irq_handler;
1019
1020 /*
1021  * Check that the hpet counter c1 is ahead of the c2
1022  */
1023 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1024 {
1025         return (s32)(c2 - c1) < 0;
1026 }
1027
1028 /*
1029  * Registers a IRQ handler.
1030  */
1031 int hpet_register_irq_handler(rtc_irq_handler handler)
1032 {
1033         if (!is_hpet_enabled())
1034                 return -ENODEV;
1035         if (irq_handler)
1036                 return -EBUSY;
1037
1038         irq_handler = handler;
1039
1040         return 0;
1041 }
1042 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1043
1044 /*
1045  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1046  * and does cleanup.
1047  */
1048 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1049 {
1050         if (!is_hpet_enabled())
1051                 return;
1052
1053         irq_handler = NULL;
1054         hpet_rtc_flags = 0;
1055 }
1056 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1057
1058 /*
1059  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1060  * is not supported by all HPET implementations for timer 1.
1061  *
1062  * hpet_rtc_timer_init() is called when the rtc is initialized.
1063  */
1064 int hpet_rtc_timer_init(void)
1065 {
1066         unsigned int cfg, cnt, delta;
1067         unsigned long flags;
1068
1069         if (!is_hpet_enabled())
1070                 return 0;
1071
1072         if (!hpet_default_delta) {
1073                 uint64_t clc;
1074
1075                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1076                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1077                 hpet_default_delta = clc;
1078         }
1079
1080         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1081                 delta = hpet_default_delta;
1082         else
1083                 delta = hpet_pie_delta;
1084
1085         local_irq_save(flags);
1086
1087         cnt = delta + hpet_readl(HPET_COUNTER);
1088         hpet_writel(cnt, HPET_T1_CMP);
1089         hpet_t1_cmp = cnt;
1090
1091         cfg = hpet_readl(HPET_T1_CFG);
1092         cfg &= ~HPET_TN_PERIODIC;
1093         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1094         hpet_writel(cfg, HPET_T1_CFG);
1095
1096         local_irq_restore(flags);
1097
1098         return 1;
1099 }
1100 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1101
1102 static void hpet_disable_rtc_channel(void)
1103 {
1104         unsigned long cfg;
1105         cfg = hpet_readl(HPET_T1_CFG);
1106         cfg &= ~HPET_TN_ENABLE;
1107         hpet_writel(cfg, HPET_T1_CFG);
1108 }
1109
1110 /*
1111  * The functions below are called from rtc driver.
1112  * Return 0 if HPET is not being used.
1113  * Otherwise do the necessary changes and return 1.
1114  */
1115 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1116 {
1117         if (!is_hpet_enabled())
1118                 return 0;
1119
1120         hpet_rtc_flags &= ~bit_mask;
1121         if (unlikely(!hpet_rtc_flags))
1122                 hpet_disable_rtc_channel();
1123
1124         return 1;
1125 }
1126 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1127
1128 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1129 {
1130         unsigned long oldbits = hpet_rtc_flags;
1131
1132         if (!is_hpet_enabled())
1133                 return 0;
1134
1135         hpet_rtc_flags |= bit_mask;
1136
1137         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1138                 hpet_prev_update_sec = -1;
1139
1140         if (!oldbits)
1141                 hpet_rtc_timer_init();
1142
1143         return 1;
1144 }
1145 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1146
1147 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1148                         unsigned char sec)
1149 {
1150         if (!is_hpet_enabled())
1151                 return 0;
1152
1153         hpet_alarm_time.tm_hour = hrs;
1154         hpet_alarm_time.tm_min = min;
1155         hpet_alarm_time.tm_sec = sec;
1156
1157         return 1;
1158 }
1159 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1160
1161 int hpet_set_periodic_freq(unsigned long freq)
1162 {
1163         uint64_t clc;
1164
1165         if (!is_hpet_enabled())
1166                 return 0;
1167
1168         if (freq <= DEFAULT_RTC_INT_FREQ)
1169                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1170         else {
1171                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1172                 do_div(clc, freq);
1173                 clc >>= hpet_clockevent.shift;
1174                 hpet_pie_delta = clc;
1175                 hpet_pie_limit = 0;
1176         }
1177         return 1;
1178 }
1179 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1180
1181 int hpet_rtc_dropped_irq(void)
1182 {
1183         return is_hpet_enabled();
1184 }
1185 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1186
1187 static void hpet_rtc_timer_reinit(void)
1188 {
1189         unsigned int delta;
1190         int lost_ints = -1;
1191
1192         if (unlikely(!hpet_rtc_flags))
1193                 hpet_disable_rtc_channel();
1194
1195         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1196                 delta = hpet_default_delta;
1197         else
1198                 delta = hpet_pie_delta;
1199
1200         /*
1201          * Increment the comparator value until we are ahead of the
1202          * current count.
1203          */
1204         do {
1205                 hpet_t1_cmp += delta;
1206                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1207                 lost_ints++;
1208         } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1209
1210         if (lost_ints) {
1211                 if (hpet_rtc_flags & RTC_PIE)
1212                         hpet_pie_count += lost_ints;
1213                 if (printk_ratelimit())
1214                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1215                                 lost_ints);
1216         }
1217 }
1218
1219 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1220 {
1221         struct rtc_time curr_time;
1222         unsigned long rtc_int_flag = 0;
1223
1224         hpet_rtc_timer_reinit();
1225         memset(&curr_time, 0, sizeof(struct rtc_time));
1226
1227         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1228                 get_rtc_time(&curr_time);
1229
1230         if (hpet_rtc_flags & RTC_UIE &&
1231             curr_time.tm_sec != hpet_prev_update_sec) {
1232                 if (hpet_prev_update_sec >= 0)
1233                         rtc_int_flag = RTC_UF;
1234                 hpet_prev_update_sec = curr_time.tm_sec;
1235         }
1236
1237         if (hpet_rtc_flags & RTC_PIE &&
1238             ++hpet_pie_count >= hpet_pie_limit) {
1239                 rtc_int_flag |= RTC_PF;
1240                 hpet_pie_count = 0;
1241         }
1242
1243         if (hpet_rtc_flags & RTC_AIE &&
1244             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1245             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1246             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1247                         rtc_int_flag |= RTC_AF;
1248
1249         if (rtc_int_flag) {
1250                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1251                 if (irq_handler)
1252                         irq_handler(rtc_int_flag, dev_id);
1253         }
1254         return IRQ_HANDLED;
1255 }
1256 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1257 #endif