1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
5 #include <linux/export.h>
6 #include <linux/delay.h>
7 #include <linux/errno.h>
8 #include <linux/i8253.h>
9 #include <linux/slab.h>
10 #include <linux/hpet.h>
11 #include <linux/init.h>
12 #include <linux/cpu.h>
16 #include <asm/cpufeature.h>
17 #include <asm/irqdomain.h>
18 #include <asm/fixmap.h>
22 #define HPET_MASK CLOCKSOURCE_MASK(32)
24 #define HPET_DEV_USED_BIT 2
25 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
26 #define HPET_DEV_VALID 0x8
27 #define HPET_DEV_FSB_CAP 0x1000
28 #define HPET_DEV_PERI_CAP 0x2000
30 #define HPET_MIN_CYCLES 128
31 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
34 * HPET address is set in acpi/boot.c, when an ACPI entry exists
36 unsigned long hpet_address;
37 u8 hpet_blockid; /* OS timer block num */
38 bool hpet_msi_disable;
41 static unsigned int hpet_num_timers;
43 static void __iomem *hpet_virt_address;
46 struct clock_event_device evt;
54 static inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
56 return container_of(evtdev, struct hpet_dev, evt);
59 inline unsigned int hpet_readl(unsigned int a)
61 return readl(hpet_virt_address + a);
64 static inline void hpet_writel(unsigned int d, unsigned int a)
66 writel(d, hpet_virt_address + a);
70 #include <asm/pgtable.h>
73 static inline void hpet_set_mapping(void)
75 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
78 static inline void hpet_clear_mapping(void)
80 iounmap(hpet_virt_address);
81 hpet_virt_address = NULL;
85 * HPET command line enable / disable
87 bool boot_hpet_disable;
89 static bool hpet_verbose;
91 static int __init hpet_setup(char *str)
94 char *next = strchr(str, ',');
98 if (!strncmp("disable", str, 7))
99 boot_hpet_disable = true;
100 if (!strncmp("force", str, 5))
101 hpet_force_user = true;
102 if (!strncmp("verbose", str, 7))
108 __setup("hpet=", hpet_setup);
110 static int __init disable_hpet(char *str)
112 boot_hpet_disable = true;
115 __setup("nohpet", disable_hpet);
117 static inline int is_hpet_capable(void)
119 return !boot_hpet_disable && hpet_address;
123 * HPET timer interrupt enable / disable
125 static bool hpet_legacy_int_enabled;
128 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
130 int is_hpet_enabled(void)
132 return is_hpet_capable() && hpet_legacy_int_enabled;
134 EXPORT_SYMBOL_GPL(is_hpet_enabled);
136 static void _hpet_print_config(const char *function, int line)
139 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
140 l = hpet_readl(HPET_ID);
141 h = hpet_readl(HPET_PERIOD);
142 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
143 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
144 l = hpet_readl(HPET_CFG);
145 h = hpet_readl(HPET_STATUS);
146 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
147 l = hpet_readl(HPET_COUNTER);
148 h = hpet_readl(HPET_COUNTER+4);
149 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
151 for (i = 0; i < timers; i++) {
152 l = hpet_readl(HPET_Tn_CFG(i));
153 h = hpet_readl(HPET_Tn_CFG(i)+4);
154 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
156 l = hpet_readl(HPET_Tn_CMP(i));
157 h = hpet_readl(HPET_Tn_CMP(i)+4);
158 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
160 l = hpet_readl(HPET_Tn_ROUTE(i));
161 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
162 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
167 #define hpet_print_config() \
170 _hpet_print_config(__func__, __LINE__); \
174 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
175 * timer 0 and timer 1 in case of RTC emulation.
179 static void hpet_reserve_msi_timers(struct hpet_data *hd);
181 static void hpet_reserve_platform_timers(unsigned int id)
183 struct hpet __iomem *hpet = hpet_virt_address;
184 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
185 unsigned int nrtimers, i;
188 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
190 memset(&hd, 0, sizeof(hd));
191 hd.hd_phys_address = hpet_address;
192 hd.hd_address = hpet;
193 hd.hd_nirqs = nrtimers;
194 hpet_reserve_timer(&hd, 0);
196 #ifdef CONFIG_HPET_EMULATE_RTC
197 hpet_reserve_timer(&hd, 1);
201 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
202 * is wrong for i8259!) not the output IRQ. Many BIOS writers
203 * don't bother configuring *any* comparator interrupts.
205 hd.hd_irq[0] = HPET_LEGACY_8254;
206 hd.hd_irq[1] = HPET_LEGACY_RTC;
208 for (i = 2; i < nrtimers; timer++, i++) {
209 hd.hd_irq[i] = (readl(&timer->hpet_config) &
210 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
213 hpet_reserve_msi_timers(&hd);
219 static void hpet_reserve_platform_timers(unsigned int id) { }
225 static unsigned long hpet_freq;
227 static struct clock_event_device hpet_clockevent;
229 static void hpet_stop_counter(void)
231 u32 cfg = hpet_readl(HPET_CFG);
232 cfg &= ~HPET_CFG_ENABLE;
233 hpet_writel(cfg, HPET_CFG);
236 static void hpet_reset_counter(void)
238 hpet_writel(0, HPET_COUNTER);
239 hpet_writel(0, HPET_COUNTER + 4);
242 static void hpet_start_counter(void)
244 unsigned int cfg = hpet_readl(HPET_CFG);
245 cfg |= HPET_CFG_ENABLE;
246 hpet_writel(cfg, HPET_CFG);
249 static void hpet_restart_counter(void)
252 hpet_reset_counter();
253 hpet_start_counter();
256 static void hpet_resume_device(void)
261 static void hpet_resume_counter(struct clocksource *cs)
263 hpet_resume_device();
264 hpet_restart_counter();
267 static void hpet_enable_legacy_int(void)
269 unsigned int cfg = hpet_readl(HPET_CFG);
271 cfg |= HPET_CFG_LEGACY;
272 hpet_writel(cfg, HPET_CFG);
273 hpet_legacy_int_enabled = true;
276 static void hpet_legacy_clockevent_register(void)
278 /* Start HPET legacy interrupts */
279 hpet_enable_legacy_int();
282 * Start hpet with the boot cpu mask and make it
283 * global after the IO_APIC has been initialized.
285 hpet_clockevent.cpumask = cpumask_of(boot_cpu_data.cpu_index);
286 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
287 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
288 global_clock_event = &hpet_clockevent;
289 printk(KERN_DEBUG "hpet clockevent registered\n");
292 static int hpet_set_periodic(struct clock_event_device *evt, int timer)
294 unsigned int cfg, cmp, now;
298 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
299 delta >>= evt->shift;
300 now = hpet_readl(HPET_COUNTER);
301 cmp = now + (unsigned int)delta;
302 cfg = hpet_readl(HPET_Tn_CFG(timer));
303 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
305 hpet_writel(cfg, HPET_Tn_CFG(timer));
306 hpet_writel(cmp, HPET_Tn_CMP(timer));
309 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
310 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
311 * bit is automatically cleared after the first write.
312 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
313 * Publication # 24674)
315 hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer));
316 hpet_start_counter();
322 static int hpet_set_oneshot(struct clock_event_device *evt, int timer)
326 cfg = hpet_readl(HPET_Tn_CFG(timer));
327 cfg &= ~HPET_TN_PERIODIC;
328 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
329 hpet_writel(cfg, HPET_Tn_CFG(timer));
334 static int hpet_shutdown(struct clock_event_device *evt, int timer)
338 cfg = hpet_readl(HPET_Tn_CFG(timer));
339 cfg &= ~HPET_TN_ENABLE;
340 hpet_writel(cfg, HPET_Tn_CFG(timer));
345 static int hpet_resume(struct clock_event_device *evt)
347 hpet_enable_legacy_int();
352 static int hpet_next_event(unsigned long delta,
353 struct clock_event_device *evt, int timer)
358 cnt = hpet_readl(HPET_COUNTER);
360 hpet_writel(cnt, HPET_Tn_CMP(timer));
363 * HPETs are a complete disaster. The compare register is
364 * based on a equal comparison and neither provides a less
365 * than or equal functionality (which would require to take
366 * the wraparound into account) nor a simple count down event
367 * mode. Further the write to the comparator register is
368 * delayed internally up to two HPET clock cycles in certain
369 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
370 * longer delays. We worked around that by reading back the
371 * compare register, but that required another workaround for
372 * ICH9,10 chips where the first readout after write can
373 * return the old stale value. We already had a minimum
374 * programming delta of 5us enforced, but a NMI or SMI hitting
375 * between the counter readout and the comparator write can
376 * move us behind that point easily. Now instead of reading
377 * the compare register back several times, we make the ETIME
378 * decision based on the following: Return ETIME if the
379 * counter value after the write is less than HPET_MIN_CYCLES
380 * away from the event or if the counter is already ahead of
381 * the event. The minimum programming delta for the generic
382 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
384 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
386 return res < HPET_MIN_CYCLES ? -ETIME : 0;
389 static int hpet_legacy_shutdown(struct clock_event_device *evt)
391 return hpet_shutdown(evt, 0);
394 static int hpet_legacy_set_oneshot(struct clock_event_device *evt)
396 return hpet_set_oneshot(evt, 0);
399 static int hpet_legacy_set_periodic(struct clock_event_device *evt)
401 return hpet_set_periodic(evt, 0);
404 static int hpet_legacy_resume(struct clock_event_device *evt)
406 return hpet_resume(evt);
409 static int hpet_legacy_next_event(unsigned long delta,
410 struct clock_event_device *evt)
412 return hpet_next_event(delta, evt, 0);
416 * The hpet clock event device
418 static struct clock_event_device hpet_clockevent = {
420 .features = CLOCK_EVT_FEAT_PERIODIC |
421 CLOCK_EVT_FEAT_ONESHOT,
422 .set_state_periodic = hpet_legacy_set_periodic,
423 .set_state_oneshot = hpet_legacy_set_oneshot,
424 .set_state_shutdown = hpet_legacy_shutdown,
425 .tick_resume = hpet_legacy_resume,
426 .set_next_event = hpet_legacy_next_event,
434 #ifdef CONFIG_PCI_MSI
436 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
437 static struct hpet_dev *hpet_devs;
438 static struct irq_domain *hpet_domain;
440 void hpet_msi_unmask(struct irq_data *data)
442 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
446 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
447 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
448 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
451 void hpet_msi_mask(struct irq_data *data)
453 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
457 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
458 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
459 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
462 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
464 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
465 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
468 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
470 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
471 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
475 static int hpet_msi_shutdown(struct clock_event_device *evt)
477 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
479 return hpet_shutdown(evt, hdev->num);
482 static int hpet_msi_set_oneshot(struct clock_event_device *evt)
484 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
486 return hpet_set_oneshot(evt, hdev->num);
489 static int hpet_msi_set_periodic(struct clock_event_device *evt)
491 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
493 return hpet_set_periodic(evt, hdev->num);
496 static int hpet_msi_resume(struct clock_event_device *evt)
498 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
499 struct irq_data *data = irq_get_irq_data(hdev->irq);
502 /* Restore the MSI msg and unmask the interrupt */
503 irq_chip_compose_msi_msg(data, &msg);
504 hpet_msi_write(hdev, &msg);
505 hpet_msi_unmask(data);
509 static int hpet_msi_next_event(unsigned long delta,
510 struct clock_event_device *evt)
512 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
513 return hpet_next_event(delta, evt, hdev->num);
516 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
518 struct hpet_dev *dev = (struct hpet_dev *)data;
519 struct clock_event_device *hevt = &dev->evt;
521 if (!hevt->event_handler) {
522 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
527 hevt->event_handler(hevt);
531 static int hpet_setup_irq(struct hpet_dev *dev)
534 if (request_irq(dev->irq, hpet_interrupt_handler,
535 IRQF_TIMER | IRQF_NOBALANCING,
539 disable_irq(dev->irq);
540 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
541 enable_irq(dev->irq);
543 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
544 dev->name, dev->irq);
549 /* This should be called in specific @cpu */
550 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
552 struct clock_event_device *evt = &hdev->evt;
554 WARN_ON(cpu != smp_processor_id());
555 if (!(hdev->flags & HPET_DEV_VALID))
559 per_cpu(cpu_hpet_dev, cpu) = hdev;
560 evt->name = hdev->name;
561 hpet_setup_irq(hdev);
562 evt->irq = hdev->irq;
565 evt->features = CLOCK_EVT_FEAT_ONESHOT;
566 if (hdev->flags & HPET_DEV_PERI_CAP) {
567 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
568 evt->set_state_periodic = hpet_msi_set_periodic;
571 evt->set_state_shutdown = hpet_msi_shutdown;
572 evt->set_state_oneshot = hpet_msi_set_oneshot;
573 evt->tick_resume = hpet_msi_resume;
574 evt->set_next_event = hpet_msi_next_event;
575 evt->cpumask = cpumask_of(hdev->cpu);
577 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
582 /* Reserve at least one timer for userspace (/dev/hpet) */
583 #define RESERVE_TIMERS 1
585 #define RESERVE_TIMERS 0
588 static void hpet_msi_capability_lookup(unsigned int start_timer)
591 unsigned int num_timers;
592 unsigned int num_timers_used = 0;
595 if (hpet_msi_disable)
598 if (boot_cpu_has(X86_FEATURE_ARAT))
600 id = hpet_readl(HPET_ID);
602 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
603 num_timers++; /* Value read out starts from 0 */
606 hpet_domain = hpet_create_irq_domain(hpet_blockid);
610 hpet_devs = kcalloc(num_timers, sizeof(struct hpet_dev), GFP_KERNEL);
614 hpet_num_timers = num_timers;
616 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
617 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
618 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
620 /* Only consider HPET timer with MSI support */
621 if (!(cfg & HPET_TN_FSB_CAP))
625 if (cfg & HPET_TN_PERIODIC_CAP)
626 hdev->flags |= HPET_DEV_PERI_CAP;
627 sprintf(hdev->name, "hpet%d", i);
630 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num);
635 hdev->flags |= HPET_DEV_FSB_CAP;
636 hdev->flags |= HPET_DEV_VALID;
638 if (num_timers_used == num_possible_cpus())
642 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
643 num_timers, num_timers_used);
647 static void hpet_reserve_msi_timers(struct hpet_data *hd)
654 for (i = 0; i < hpet_num_timers; i++) {
655 struct hpet_dev *hdev = &hpet_devs[i];
657 if (!(hdev->flags & HPET_DEV_VALID))
660 hd->hd_irq[hdev->num] = hdev->irq;
661 hpet_reserve_timer(hd, hdev->num);
666 static struct hpet_dev *hpet_get_unused_timer(void)
673 for (i = 0; i < hpet_num_timers; i++) {
674 struct hpet_dev *hdev = &hpet_devs[i];
676 if (!(hdev->flags & HPET_DEV_VALID))
678 if (test_and_set_bit(HPET_DEV_USED_BIT,
679 (unsigned long *)&hdev->flags))
686 struct hpet_work_struct {
687 struct delayed_work work;
688 struct completion complete;
691 static void hpet_work(struct work_struct *w)
693 struct hpet_dev *hdev;
694 int cpu = smp_processor_id();
695 struct hpet_work_struct *hpet_work;
697 hpet_work = container_of(w, struct hpet_work_struct, work.work);
699 hdev = hpet_get_unused_timer();
701 init_one_hpet_msi_clockevent(hdev, cpu);
703 complete(&hpet_work->complete);
706 static int hpet_cpuhp_online(unsigned int cpu)
708 struct hpet_work_struct work;
710 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
711 init_completion(&work.complete);
712 /* FIXME: add schedule_work_on() */
713 schedule_delayed_work_on(cpu, &work.work, 0);
714 wait_for_completion(&work.complete);
715 destroy_delayed_work_on_stack(&work.work);
719 static int hpet_cpuhp_dead(unsigned int cpu)
721 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
725 free_irq(hdev->irq, hdev);
726 hdev->flags &= ~HPET_DEV_USED;
727 per_cpu(cpu_hpet_dev, cpu) = NULL;
732 static void hpet_msi_capability_lookup(unsigned int start_timer)
738 static void hpet_reserve_msi_timers(struct hpet_data *hd)
744 #define hpet_cpuhp_online NULL
745 #define hpet_cpuhp_dead NULL
750 * Clock source related code
752 #if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
754 * Reading the HPET counter is a very slow operation. If a large number of
755 * CPUs are trying to access the HPET counter simultaneously, it can cause
756 * massive delay and slow down system performance dramatically. This may
757 * happen when HPET is the default clock source instead of TSC. For a
758 * really large system with hundreds of CPUs, the slowdown may be so
759 * severe that it may actually crash the system because of a NMI watchdog
760 * soft lockup, for example.
762 * If multiple CPUs are trying to access the HPET counter at the same time,
763 * we don't actually need to read the counter multiple times. Instead, the
764 * other CPUs can use the counter value read by the first CPU in the group.
766 * This special feature is only enabled on x86-64 systems. It is unlikely
767 * that 32-bit x86 systems will have enough CPUs to require this feature
768 * with its associated locking overhead. And we also need 64-bit atomic
771 * The lock and the hpet value are stored together and can be read in a
772 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t
773 * is 32 bits in size.
777 arch_spinlock_t lock;
783 static union hpet_lock hpet __cacheline_aligned = {
784 { .lock = __ARCH_SPIN_LOCK_UNLOCKED, },
787 static u64 read_hpet(struct clocksource *cs)
790 union hpet_lock old, new;
792 BUILD_BUG_ON(sizeof(union hpet_lock) != 8);
795 * Read HPET directly if in NMI.
798 return (u64)hpet_readl(HPET_COUNTER);
801 * Read the current state of the lock and HPET value atomically.
803 old.lockval = READ_ONCE(hpet.lockval);
805 if (arch_spin_is_locked(&old.lock))
808 local_irq_save(flags);
809 if (arch_spin_trylock(&hpet.lock)) {
810 new.value = hpet_readl(HPET_COUNTER);
812 * Use WRITE_ONCE() to prevent store tearing.
814 WRITE_ONCE(hpet.value, new.value);
815 arch_spin_unlock(&hpet.lock);
816 local_irq_restore(flags);
817 return (u64)new.value;
819 local_irq_restore(flags);
825 * Wait until the HPET value change or the lock is free to indicate
826 * its value is up-to-date.
828 * It is possible that old.value has already contained the latest
829 * HPET value while the lock holder was in the process of releasing
830 * the lock. Checking for lock state change will enable us to return
831 * the value immediately instead of waiting for the next HPET reader
836 new.lockval = READ_ONCE(hpet.lockval);
837 } while ((new.value == old.value) && arch_spin_is_locked(&new.lock));
839 return (u64)new.value;
845 static u64 read_hpet(struct clocksource *cs)
847 return (u64)hpet_readl(HPET_COUNTER);
851 static struct clocksource clocksource_hpet = {
856 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
857 .resume = hpet_resume_counter,
860 static int hpet_clocksource_register(void)
865 /* Start the counter */
866 hpet_restart_counter();
868 /* Verify whether hpet counter works */
869 t1 = hpet_readl(HPET_COUNTER);
873 * We don't know the TSC frequency yet, but waiting for
874 * 200000 TSC cycles is safe:
881 } while ((now - start) < 200000UL);
883 if (t1 == hpet_readl(HPET_COUNTER)) {
885 "HPET counter not counting. HPET disabled\n");
889 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
893 static u32 *hpet_boot_cfg;
896 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
898 int __init hpet_enable(void)
900 u32 hpet_period, cfg, id;
902 unsigned int i, last;
904 if (!is_hpet_capable())
910 * Read the period and check for a sane value:
912 hpet_period = hpet_readl(HPET_PERIOD);
915 * AMD SB700 based systems with spread spectrum enabled use a
916 * SMM based HPET emulation to provide proper frequency
917 * setting. The SMM code is initialized with the first HPET
918 * register access and takes some time to complete. During
919 * this time the config register reads 0xffffffff. We check
920 * for max. 1000 loops whether the config register reads a non
921 * 0xffffffff value to make sure that HPET is up and running
922 * before we go further. A counting loop is safe, as the HPET
923 * access takes thousands of CPU cycles. On non SB700 based
924 * machines this check is only done once and has no side
927 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
930 "HPET config register value = 0xFFFFFFFF. "
936 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
940 * The period is a femto seconds value. Convert it to a
944 do_div(freq, hpet_period);
948 * Read the HPET ID register to retrieve the IRQ routing
949 * information and the number of channels
951 id = hpet_readl(HPET_ID);
954 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
956 #ifdef CONFIG_HPET_EMULATE_RTC
958 * The legacy routing mode needs at least two channels, tick timer
959 * and the rtc emulation channel.
965 cfg = hpet_readl(HPET_CFG);
966 hpet_boot_cfg = kmalloc_array(last + 2, sizeof(*hpet_boot_cfg),
969 *hpet_boot_cfg = cfg;
971 pr_warn("HPET initial state will not be saved\n");
972 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
973 hpet_writel(cfg, HPET_CFG);
975 pr_warn("Unrecognized bits %#x set in global cfg\n", cfg);
977 for (i = 0; i <= last; ++i) {
978 cfg = hpet_readl(HPET_Tn_CFG(i));
980 hpet_boot_cfg[i + 1] = cfg;
981 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
982 hpet_writel(cfg, HPET_Tn_CFG(i));
983 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
984 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
985 | HPET_TN_FSB | HPET_TN_FSB_CAP);
987 pr_warn("Unrecognized bits %#x set in cfg#%u\n",
992 if (hpet_clocksource_register())
995 if (id & HPET_ID_LEGSUP) {
996 hpet_legacy_clockevent_register();
1002 hpet_clear_mapping();
1008 * Needs to be late, as the reserve_timer code calls kalloc !
1010 * Not a problem on i386 as hpet_enable is called from late_time_init,
1011 * but on x86_64 it is necessary !
1013 static __init int hpet_late_init(void)
1017 if (boot_hpet_disable)
1020 if (!hpet_address) {
1021 if (!force_hpet_address)
1024 hpet_address = force_hpet_address;
1028 if (!hpet_virt_address)
1031 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
1032 hpet_msi_capability_lookup(2);
1034 hpet_msi_capability_lookup(0);
1036 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
1037 hpet_print_config();
1039 if (hpet_msi_disable)
1042 if (boot_cpu_has(X86_FEATURE_ARAT))
1045 /* This notifier should be called after workqueue is ready */
1046 ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online",
1047 hpet_cpuhp_online, NULL);
1050 ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL,
1057 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE);
1060 fs_initcall(hpet_late_init);
1062 void hpet_disable(void)
1064 if (is_hpet_capable() && hpet_virt_address) {
1065 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
1068 cfg = *hpet_boot_cfg;
1069 else if (hpet_legacy_int_enabled) {
1070 cfg &= ~HPET_CFG_LEGACY;
1071 hpet_legacy_int_enabled = false;
1073 cfg &= ~HPET_CFG_ENABLE;
1074 hpet_writel(cfg, HPET_CFG);
1079 id = hpet_readl(HPET_ID);
1080 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
1082 for (id = 0; id <= last; ++id)
1083 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
1085 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
1086 hpet_writel(*hpet_boot_cfg, HPET_CFG);
1090 #ifdef CONFIG_HPET_EMULATE_RTC
1092 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1093 * is enabled, we support RTC interrupt functionality in software.
1094 * RTC has 3 kinds of interrupts:
1095 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1097 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1098 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1099 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1100 * (1) and (2) above are implemented using polling at a frequency of
1101 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1102 * overhead. (DEFAULT_RTC_INT_FREQ)
1103 * For (3), we use interrupts at 64Hz or user specified periodic
1104 * frequency, whichever is higher.
1106 #include <linux/mc146818rtc.h>
1107 #include <linux/rtc.h>
1109 #define DEFAULT_RTC_INT_FREQ 64
1110 #define DEFAULT_RTC_SHIFT 6
1111 #define RTC_NUM_INTS 1
1113 static unsigned long hpet_rtc_flags;
1114 static int hpet_prev_update_sec;
1115 static struct rtc_time hpet_alarm_time;
1116 static unsigned long hpet_pie_count;
1117 static u32 hpet_t1_cmp;
1118 static u32 hpet_default_delta;
1119 static u32 hpet_pie_delta;
1120 static unsigned long hpet_pie_limit;
1122 static rtc_irq_handler irq_handler;
1125 * Check that the hpet counter c1 is ahead of the c2
1127 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1129 return (s32)(c2 - c1) < 0;
1133 * Registers a IRQ handler.
1135 int hpet_register_irq_handler(rtc_irq_handler handler)
1137 if (!is_hpet_enabled())
1142 irq_handler = handler;
1146 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1149 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1152 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1154 if (!is_hpet_enabled())
1160 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1163 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1164 * is not supported by all HPET implementations for timer 1.
1166 * hpet_rtc_timer_init() is called when the rtc is initialized.
1168 int hpet_rtc_timer_init(void)
1170 unsigned int cfg, cnt, delta;
1171 unsigned long flags;
1173 if (!is_hpet_enabled())
1176 if (!hpet_default_delta) {
1179 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1180 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1181 hpet_default_delta = clc;
1184 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1185 delta = hpet_default_delta;
1187 delta = hpet_pie_delta;
1189 local_irq_save(flags);
1191 cnt = delta + hpet_readl(HPET_COUNTER);
1192 hpet_writel(cnt, HPET_T1_CMP);
1195 cfg = hpet_readl(HPET_T1_CFG);
1196 cfg &= ~HPET_TN_PERIODIC;
1197 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1198 hpet_writel(cfg, HPET_T1_CFG);
1200 local_irq_restore(flags);
1204 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1206 static void hpet_disable_rtc_channel(void)
1208 u32 cfg = hpet_readl(HPET_T1_CFG);
1209 cfg &= ~HPET_TN_ENABLE;
1210 hpet_writel(cfg, HPET_T1_CFG);
1214 * The functions below are called from rtc driver.
1215 * Return 0 if HPET is not being used.
1216 * Otherwise do the necessary changes and return 1.
1218 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1220 if (!is_hpet_enabled())
1223 hpet_rtc_flags &= ~bit_mask;
1224 if (unlikely(!hpet_rtc_flags))
1225 hpet_disable_rtc_channel();
1229 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1231 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1233 unsigned long oldbits = hpet_rtc_flags;
1235 if (!is_hpet_enabled())
1238 hpet_rtc_flags |= bit_mask;
1240 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1241 hpet_prev_update_sec = -1;
1244 hpet_rtc_timer_init();
1248 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1250 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1253 if (!is_hpet_enabled())
1256 hpet_alarm_time.tm_hour = hrs;
1257 hpet_alarm_time.tm_min = min;
1258 hpet_alarm_time.tm_sec = sec;
1262 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1264 int hpet_set_periodic_freq(unsigned long freq)
1268 if (!is_hpet_enabled())
1271 if (freq <= DEFAULT_RTC_INT_FREQ)
1272 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1274 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1276 clc >>= hpet_clockevent.shift;
1277 hpet_pie_delta = clc;
1282 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1284 int hpet_rtc_dropped_irq(void)
1286 return is_hpet_enabled();
1288 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1290 static void hpet_rtc_timer_reinit(void)
1295 if (unlikely(!hpet_rtc_flags))
1296 hpet_disable_rtc_channel();
1298 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1299 delta = hpet_default_delta;
1301 delta = hpet_pie_delta;
1304 * Increment the comparator value until we are ahead of the
1308 hpet_t1_cmp += delta;
1309 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1311 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1314 if (hpet_rtc_flags & RTC_PIE)
1315 hpet_pie_count += lost_ints;
1316 if (printk_ratelimit())
1317 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1322 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1324 struct rtc_time curr_time;
1325 unsigned long rtc_int_flag = 0;
1327 hpet_rtc_timer_reinit();
1328 memset(&curr_time, 0, sizeof(struct rtc_time));
1330 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1331 mc146818_get_time(&curr_time);
1333 if (hpet_rtc_flags & RTC_UIE &&
1334 curr_time.tm_sec != hpet_prev_update_sec) {
1335 if (hpet_prev_update_sec >= 0)
1336 rtc_int_flag = RTC_UF;
1337 hpet_prev_update_sec = curr_time.tm_sec;
1340 if (hpet_rtc_flags & RTC_PIE &&
1341 ++hpet_pie_count >= hpet_pie_limit) {
1342 rtc_int_flag |= RTC_PF;
1346 if (hpet_rtc_flags & RTC_AIE &&
1347 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1348 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1349 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1350 rtc_int_flag |= RTC_AF;
1353 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1355 irq_handler(rtc_int_flag, dev_id);
1359 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);