Merge branch 'timers-for-linus-hpet' of git://git.kernel.org/pub/scm/linux/kernel...
[sfrench/cifs-2.6.git] / arch / x86 / kernel / hpet.c
1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/sysdev.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/hpet.h>
8 #include <linux/init.h>
9 #include <linux/cpu.h>
10 #include <linux/pm.h>
11 #include <linux/io.h>
12
13 #include <asm/fixmap.h>
14 #include <asm/i8253.h>
15 #include <asm/hpet.h>
16
17 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
18 #define HPET_SHIFT                      22
19
20 /* FSEC = 10^-15
21    NSEC = 10^-9 */
22 #define FSEC_PER_NSEC                   1000000L
23
24 #define HPET_DEV_USED_BIT               2
25 #define HPET_DEV_USED                   (1 << HPET_DEV_USED_BIT)
26 #define HPET_DEV_VALID                  0x8
27 #define HPET_DEV_FSB_CAP                0x1000
28 #define HPET_DEV_PERI_CAP               0x2000
29
30 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
31
32 /*
33  * HPET address is set in acpi/boot.c, when an ACPI entry exists
34  */
35 unsigned long                           hpet_address;
36 u8                                      hpet_blockid; /* OS timer block num */
37 #ifdef CONFIG_PCI_MSI
38 static unsigned long                    hpet_num_timers;
39 #endif
40 static void __iomem                     *hpet_virt_address;
41
42 struct hpet_dev {
43         struct clock_event_device       evt;
44         unsigned int                    num;
45         int                             cpu;
46         unsigned int                    irq;
47         unsigned int                    flags;
48         char                            name[10];
49 };
50
51 inline unsigned int hpet_readl(unsigned int a)
52 {
53         return readl(hpet_virt_address + a);
54 }
55
56 static inline void hpet_writel(unsigned int d, unsigned int a)
57 {
58         writel(d, hpet_virt_address + a);
59 }
60
61 #ifdef CONFIG_X86_64
62 #include <asm/pgtable.h>
63 #endif
64
65 static inline void hpet_set_mapping(void)
66 {
67         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
68 #ifdef CONFIG_X86_64
69         __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
70 #endif
71 }
72
73 static inline void hpet_clear_mapping(void)
74 {
75         iounmap(hpet_virt_address);
76         hpet_virt_address = NULL;
77 }
78
79 /*
80  * HPET command line enable / disable
81  */
82 static int boot_hpet_disable;
83 int hpet_force_user;
84 static int hpet_verbose;
85
86 static int __init hpet_setup(char *str)
87 {
88         if (str) {
89                 if (!strncmp("disable", str, 7))
90                         boot_hpet_disable = 1;
91                 if (!strncmp("force", str, 5))
92                         hpet_force_user = 1;
93                 if (!strncmp("verbose", str, 7))
94                         hpet_verbose = 1;
95         }
96         return 1;
97 }
98 __setup("hpet=", hpet_setup);
99
100 static int __init disable_hpet(char *str)
101 {
102         boot_hpet_disable = 1;
103         return 1;
104 }
105 __setup("nohpet", disable_hpet);
106
107 static inline int is_hpet_capable(void)
108 {
109         return !boot_hpet_disable && hpet_address;
110 }
111
112 /*
113  * HPET timer interrupt enable / disable
114  */
115 static int hpet_legacy_int_enabled;
116
117 /**
118  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
119  */
120 int is_hpet_enabled(void)
121 {
122         return is_hpet_capable() && hpet_legacy_int_enabled;
123 }
124 EXPORT_SYMBOL_GPL(is_hpet_enabled);
125
126 static void _hpet_print_config(const char *function, int line)
127 {
128         u32 i, timers, l, h;
129         printk(KERN_INFO "hpet: %s(%d):\n", function, line);
130         l = hpet_readl(HPET_ID);
131         h = hpet_readl(HPET_PERIOD);
132         timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
133         printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
134         l = hpet_readl(HPET_CFG);
135         h = hpet_readl(HPET_STATUS);
136         printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
137         l = hpet_readl(HPET_COUNTER);
138         h = hpet_readl(HPET_COUNTER+4);
139         printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
140
141         for (i = 0; i < timers; i++) {
142                 l = hpet_readl(HPET_Tn_CFG(i));
143                 h = hpet_readl(HPET_Tn_CFG(i)+4);
144                 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
145                        i, l, h);
146                 l = hpet_readl(HPET_Tn_CMP(i));
147                 h = hpet_readl(HPET_Tn_CMP(i)+4);
148                 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
149                        i, l, h);
150                 l = hpet_readl(HPET_Tn_ROUTE(i));
151                 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
152                 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
153                        i, l, h);
154         }
155 }
156
157 #define hpet_print_config()                                     \
158 do {                                                            \
159         if (hpet_verbose)                                       \
160                 _hpet_print_config(__FUNCTION__, __LINE__);     \
161 } while (0)
162
163 /*
164  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
165  * timer 0 and timer 1 in case of RTC emulation.
166  */
167 #ifdef CONFIG_HPET
168
169 static void hpet_reserve_msi_timers(struct hpet_data *hd);
170
171 static void hpet_reserve_platform_timers(unsigned int id)
172 {
173         struct hpet __iomem *hpet = hpet_virt_address;
174         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
175         unsigned int nrtimers, i;
176         struct hpet_data hd;
177
178         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
179
180         memset(&hd, 0, sizeof(hd));
181         hd.hd_phys_address      = hpet_address;
182         hd.hd_address           = hpet;
183         hd.hd_nirqs             = nrtimers;
184         hpet_reserve_timer(&hd, 0);
185
186 #ifdef CONFIG_HPET_EMULATE_RTC
187         hpet_reserve_timer(&hd, 1);
188 #endif
189
190         /*
191          * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
192          * is wrong for i8259!) not the output IRQ.  Many BIOS writers
193          * don't bother configuring *any* comparator interrupts.
194          */
195         hd.hd_irq[0] = HPET_LEGACY_8254;
196         hd.hd_irq[1] = HPET_LEGACY_RTC;
197
198         for (i = 2; i < nrtimers; timer++, i++) {
199                 hd.hd_irq[i] = (readl(&timer->hpet_config) &
200                         Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
201         }
202
203         hpet_reserve_msi_timers(&hd);
204
205         hpet_alloc(&hd);
206
207 }
208 #else
209 static void hpet_reserve_platform_timers(unsigned int id) { }
210 #endif
211
212 /*
213  * Common hpet info
214  */
215 static unsigned long hpet_period;
216
217 static void hpet_legacy_set_mode(enum clock_event_mode mode,
218                           struct clock_event_device *evt);
219 static int hpet_legacy_next_event(unsigned long delta,
220                            struct clock_event_device *evt);
221
222 /*
223  * The hpet clock event device
224  */
225 static struct clock_event_device hpet_clockevent = {
226         .name           = "hpet",
227         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
228         .set_mode       = hpet_legacy_set_mode,
229         .set_next_event = hpet_legacy_next_event,
230         .shift          = 32,
231         .irq            = 0,
232         .rating         = 50,
233 };
234
235 static void hpet_stop_counter(void)
236 {
237         unsigned long cfg = hpet_readl(HPET_CFG);
238         cfg &= ~HPET_CFG_ENABLE;
239         hpet_writel(cfg, HPET_CFG);
240 }
241
242 static void hpet_reset_counter(void)
243 {
244         hpet_writel(0, HPET_COUNTER);
245         hpet_writel(0, HPET_COUNTER + 4);
246 }
247
248 static void hpet_start_counter(void)
249 {
250         unsigned int cfg = hpet_readl(HPET_CFG);
251         cfg |= HPET_CFG_ENABLE;
252         hpet_writel(cfg, HPET_CFG);
253 }
254
255 static void hpet_restart_counter(void)
256 {
257         hpet_stop_counter();
258         hpet_reset_counter();
259         hpet_start_counter();
260 }
261
262 static void hpet_resume_device(void)
263 {
264         force_hpet_resume();
265 }
266
267 static void hpet_resume_counter(void)
268 {
269         hpet_resume_device();
270         hpet_restart_counter();
271 }
272
273 static void hpet_enable_legacy_int(void)
274 {
275         unsigned int cfg = hpet_readl(HPET_CFG);
276
277         cfg |= HPET_CFG_LEGACY;
278         hpet_writel(cfg, HPET_CFG);
279         hpet_legacy_int_enabled = 1;
280 }
281
282 static void hpet_legacy_clockevent_register(void)
283 {
284         /* Start HPET legacy interrupts */
285         hpet_enable_legacy_int();
286
287         /*
288          * The mult factor is defined as (include/linux/clockchips.h)
289          *  mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
290          * hpet_period is in units of femtoseconds (per cycle), so
291          *  mult/2^shift = cyc/ns = 10^6/hpet_period
292          *  mult = (10^6 * 2^shift)/hpet_period
293          *  mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
294          */
295         hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
296                                       hpet_period, hpet_clockevent.shift);
297         /* Calculate the min / max delta */
298         hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
299                                                            &hpet_clockevent);
300         /* 5 usec minimum reprogramming delta. */
301         hpet_clockevent.min_delta_ns = 5000;
302
303         /*
304          * Start hpet with the boot cpu mask and make it
305          * global after the IO_APIC has been initialized.
306          */
307         hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
308         clockevents_register_device(&hpet_clockevent);
309         global_clock_event = &hpet_clockevent;
310         printk(KERN_DEBUG "hpet clockevent registered\n");
311 }
312
313 static int hpet_setup_msi_irq(unsigned int irq);
314
315 static void hpet_set_mode(enum clock_event_mode mode,
316                           struct clock_event_device *evt, int timer)
317 {
318         unsigned int cfg, cmp, now;
319         uint64_t delta;
320
321         switch (mode) {
322         case CLOCK_EVT_MODE_PERIODIC:
323                 hpet_stop_counter();
324                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
325                 delta >>= evt->shift;
326                 now = hpet_readl(HPET_COUNTER);
327                 cmp = now + (unsigned int) delta;
328                 cfg = hpet_readl(HPET_Tn_CFG(timer));
329                 /* Make sure we use edge triggered interrupts */
330                 cfg &= ~HPET_TN_LEVEL;
331                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
332                        HPET_TN_SETVAL | HPET_TN_32BIT;
333                 hpet_writel(cfg, HPET_Tn_CFG(timer));
334                 hpet_writel(cmp, HPET_Tn_CMP(timer));
335                 udelay(1);
336                 /*
337                  * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
338                  * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
339                  * bit is automatically cleared after the first write.
340                  * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
341                  * Publication # 24674)
342                  */
343                 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
344                 hpet_start_counter();
345                 hpet_print_config();
346                 break;
347
348         case CLOCK_EVT_MODE_ONESHOT:
349                 cfg = hpet_readl(HPET_Tn_CFG(timer));
350                 cfg &= ~HPET_TN_PERIODIC;
351                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
352                 hpet_writel(cfg, HPET_Tn_CFG(timer));
353                 break;
354
355         case CLOCK_EVT_MODE_UNUSED:
356         case CLOCK_EVT_MODE_SHUTDOWN:
357                 cfg = hpet_readl(HPET_Tn_CFG(timer));
358                 cfg &= ~HPET_TN_ENABLE;
359                 hpet_writel(cfg, HPET_Tn_CFG(timer));
360                 break;
361
362         case CLOCK_EVT_MODE_RESUME:
363                 if (timer == 0) {
364                         hpet_enable_legacy_int();
365                 } else {
366                         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
367                         hpet_setup_msi_irq(hdev->irq);
368                         disable_irq(hdev->irq);
369                         irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
370                         enable_irq(hdev->irq);
371                 }
372                 hpet_print_config();
373                 break;
374         }
375 }
376
377 static int hpet_next_event(unsigned long delta,
378                            struct clock_event_device *evt, int timer)
379 {
380         u32 cnt;
381
382         cnt = hpet_readl(HPET_COUNTER);
383         cnt += (u32) delta;
384         hpet_writel(cnt, HPET_Tn_CMP(timer));
385
386         /*
387          * We need to read back the CMP register on certain HPET
388          * implementations (ATI chipsets) which seem to delay the
389          * transfer of the compare register into the internal compare
390          * logic. With small deltas this might actually be too late as
391          * the counter could already be higher than the compare value
392          * at that point and we would wait for the next hpet interrupt
393          * forever. We found out that reading the CMP register back
394          * forces the transfer so we can rely on the comparison with
395          * the counter register below. If the read back from the
396          * compare register does not match the value we programmed
397          * then we might have a real hardware problem. We can not do
398          * much about it here, but at least alert the user/admin with
399          * a prominent warning.
400          */
401         WARN_ONCE(hpet_readl(HPET_Tn_CMP(timer)) != cnt,
402                   KERN_WARNING "hpet: compare register read back failed.\n");
403
404         return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
405 }
406
407 static void hpet_legacy_set_mode(enum clock_event_mode mode,
408                         struct clock_event_device *evt)
409 {
410         hpet_set_mode(mode, evt, 0);
411 }
412
413 static int hpet_legacy_next_event(unsigned long delta,
414                         struct clock_event_device *evt)
415 {
416         return hpet_next_event(delta, evt, 0);
417 }
418
419 /*
420  * HPET MSI Support
421  */
422 #ifdef CONFIG_PCI_MSI
423
424 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
425 static struct hpet_dev  *hpet_devs;
426
427 void hpet_msi_unmask(unsigned int irq)
428 {
429         struct hpet_dev *hdev = get_irq_data(irq);
430         unsigned int cfg;
431
432         /* unmask it */
433         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
434         cfg |= HPET_TN_FSB;
435         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
436 }
437
438 void hpet_msi_mask(unsigned int irq)
439 {
440         unsigned int cfg;
441         struct hpet_dev *hdev = get_irq_data(irq);
442
443         /* mask it */
444         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
445         cfg &= ~HPET_TN_FSB;
446         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
447 }
448
449 void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
450 {
451         struct hpet_dev *hdev = get_irq_data(irq);
452
453         hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
454         hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
455 }
456
457 void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
458 {
459         struct hpet_dev *hdev = get_irq_data(irq);
460
461         msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
462         msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
463         msg->address_hi = 0;
464 }
465
466 static void hpet_msi_set_mode(enum clock_event_mode mode,
467                                 struct clock_event_device *evt)
468 {
469         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
470         hpet_set_mode(mode, evt, hdev->num);
471 }
472
473 static int hpet_msi_next_event(unsigned long delta,
474                                 struct clock_event_device *evt)
475 {
476         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
477         return hpet_next_event(delta, evt, hdev->num);
478 }
479
480 static int hpet_setup_msi_irq(unsigned int irq)
481 {
482         if (arch_setup_hpet_msi(irq, hpet_blockid)) {
483                 destroy_irq(irq);
484                 return -EINVAL;
485         }
486         return 0;
487 }
488
489 static int hpet_assign_irq(struct hpet_dev *dev)
490 {
491         unsigned int irq;
492
493         irq = create_irq();
494         if (!irq)
495                 return -EINVAL;
496
497         set_irq_data(irq, dev);
498
499         if (hpet_setup_msi_irq(irq))
500                 return -EINVAL;
501
502         dev->irq = irq;
503         return 0;
504 }
505
506 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
507 {
508         struct hpet_dev *dev = (struct hpet_dev *)data;
509         struct clock_event_device *hevt = &dev->evt;
510
511         if (!hevt->event_handler) {
512                 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
513                                 dev->num);
514                 return IRQ_HANDLED;
515         }
516
517         hevt->event_handler(hevt);
518         return IRQ_HANDLED;
519 }
520
521 static int hpet_setup_irq(struct hpet_dev *dev)
522 {
523
524         if (request_irq(dev->irq, hpet_interrupt_handler,
525                         IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
526                         dev->name, dev))
527                 return -1;
528
529         disable_irq(dev->irq);
530         irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
531         enable_irq(dev->irq);
532
533         printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
534                          dev->name, dev->irq);
535
536         return 0;
537 }
538
539 /* This should be called in specific @cpu */
540 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
541 {
542         struct clock_event_device *evt = &hdev->evt;
543         uint64_t hpet_freq;
544
545         WARN_ON(cpu != smp_processor_id());
546         if (!(hdev->flags & HPET_DEV_VALID))
547                 return;
548
549         if (hpet_setup_msi_irq(hdev->irq))
550                 return;
551
552         hdev->cpu = cpu;
553         per_cpu(cpu_hpet_dev, cpu) = hdev;
554         evt->name = hdev->name;
555         hpet_setup_irq(hdev);
556         evt->irq = hdev->irq;
557
558         evt->rating = 110;
559         evt->features = CLOCK_EVT_FEAT_ONESHOT;
560         if (hdev->flags & HPET_DEV_PERI_CAP)
561                 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
562
563         evt->set_mode = hpet_msi_set_mode;
564         evt->set_next_event = hpet_msi_next_event;
565         evt->shift = 32;
566
567         /*
568          * The period is a femto seconds value. We need to calculate the
569          * scaled math multiplication factor for nanosecond to hpet tick
570          * conversion.
571          */
572         hpet_freq = 1000000000000000ULL;
573         do_div(hpet_freq, hpet_period);
574         evt->mult = div_sc((unsigned long) hpet_freq,
575                                       NSEC_PER_SEC, evt->shift);
576         /* Calculate the max delta */
577         evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
578         /* 5 usec minimum reprogramming delta. */
579         evt->min_delta_ns = 5000;
580
581         evt->cpumask = cpumask_of(hdev->cpu);
582         clockevents_register_device(evt);
583 }
584
585 #ifdef CONFIG_HPET
586 /* Reserve at least one timer for userspace (/dev/hpet) */
587 #define RESERVE_TIMERS 1
588 #else
589 #define RESERVE_TIMERS 0
590 #endif
591
592 static void hpet_msi_capability_lookup(unsigned int start_timer)
593 {
594         unsigned int id;
595         unsigned int num_timers;
596         unsigned int num_timers_used = 0;
597         int i;
598
599         if (boot_cpu_has(X86_FEATURE_ARAT))
600                 return;
601         id = hpet_readl(HPET_ID);
602
603         num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
604         num_timers++; /* Value read out starts from 0 */
605         hpet_print_config();
606
607         hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
608         if (!hpet_devs)
609                 return;
610
611         hpet_num_timers = num_timers;
612
613         for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
614                 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
615                 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
616
617                 /* Only consider HPET timer with MSI support */
618                 if (!(cfg & HPET_TN_FSB_CAP))
619                         continue;
620
621                 hdev->flags = 0;
622                 if (cfg & HPET_TN_PERIODIC_CAP)
623                         hdev->flags |= HPET_DEV_PERI_CAP;
624                 hdev->num = i;
625
626                 sprintf(hdev->name, "hpet%d", i);
627                 if (hpet_assign_irq(hdev))
628                         continue;
629
630                 hdev->flags |= HPET_DEV_FSB_CAP;
631                 hdev->flags |= HPET_DEV_VALID;
632                 num_timers_used++;
633                 if (num_timers_used == num_possible_cpus())
634                         break;
635         }
636
637         printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
638                 num_timers, num_timers_used);
639 }
640
641 #ifdef CONFIG_HPET
642 static void hpet_reserve_msi_timers(struct hpet_data *hd)
643 {
644         int i;
645
646         if (!hpet_devs)
647                 return;
648
649         for (i = 0; i < hpet_num_timers; i++) {
650                 struct hpet_dev *hdev = &hpet_devs[i];
651
652                 if (!(hdev->flags & HPET_DEV_VALID))
653                         continue;
654
655                 hd->hd_irq[hdev->num] = hdev->irq;
656                 hpet_reserve_timer(hd, hdev->num);
657         }
658 }
659 #endif
660
661 static struct hpet_dev *hpet_get_unused_timer(void)
662 {
663         int i;
664
665         if (!hpet_devs)
666                 return NULL;
667
668         for (i = 0; i < hpet_num_timers; i++) {
669                 struct hpet_dev *hdev = &hpet_devs[i];
670
671                 if (!(hdev->flags & HPET_DEV_VALID))
672                         continue;
673                 if (test_and_set_bit(HPET_DEV_USED_BIT,
674                         (unsigned long *)&hdev->flags))
675                         continue;
676                 return hdev;
677         }
678         return NULL;
679 }
680
681 struct hpet_work_struct {
682         struct delayed_work work;
683         struct completion complete;
684 };
685
686 static void hpet_work(struct work_struct *w)
687 {
688         struct hpet_dev *hdev;
689         int cpu = smp_processor_id();
690         struct hpet_work_struct *hpet_work;
691
692         hpet_work = container_of(w, struct hpet_work_struct, work.work);
693
694         hdev = hpet_get_unused_timer();
695         if (hdev)
696                 init_one_hpet_msi_clockevent(hdev, cpu);
697
698         complete(&hpet_work->complete);
699 }
700
701 static int hpet_cpuhp_notify(struct notifier_block *n,
702                 unsigned long action, void *hcpu)
703 {
704         unsigned long cpu = (unsigned long)hcpu;
705         struct hpet_work_struct work;
706         struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
707
708         switch (action & 0xf) {
709         case CPU_ONLINE:
710                 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work);
711                 init_completion(&work.complete);
712                 /* FIXME: add schedule_work_on() */
713                 schedule_delayed_work_on(cpu, &work.work, 0);
714                 wait_for_completion(&work.complete);
715                 destroy_timer_on_stack(&work.work.timer);
716                 break;
717         case CPU_DEAD:
718                 if (hdev) {
719                         free_irq(hdev->irq, hdev);
720                         hdev->flags &= ~HPET_DEV_USED;
721                         per_cpu(cpu_hpet_dev, cpu) = NULL;
722                 }
723                 break;
724         }
725         return NOTIFY_OK;
726 }
727 #else
728
729 static int hpet_setup_msi_irq(unsigned int irq)
730 {
731         return 0;
732 }
733 static void hpet_msi_capability_lookup(unsigned int start_timer)
734 {
735         return;
736 }
737
738 #ifdef CONFIG_HPET
739 static void hpet_reserve_msi_timers(struct hpet_data *hd)
740 {
741         return;
742 }
743 #endif
744
745 static int hpet_cpuhp_notify(struct notifier_block *n,
746                 unsigned long action, void *hcpu)
747 {
748         return NOTIFY_OK;
749 }
750
751 #endif
752
753 /*
754  * Clock source related code
755  */
756 static cycle_t read_hpet(struct clocksource *cs)
757 {
758         return (cycle_t)hpet_readl(HPET_COUNTER);
759 }
760
761 #ifdef CONFIG_X86_64
762 static cycle_t __vsyscall_fn vread_hpet(void)
763 {
764         return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
765 }
766 #endif
767
768 static struct clocksource clocksource_hpet = {
769         .name           = "hpet",
770         .rating         = 250,
771         .read           = read_hpet,
772         .mask           = HPET_MASK,
773         .shift          = HPET_SHIFT,
774         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
775         .resume         = hpet_resume_counter,
776 #ifdef CONFIG_X86_64
777         .vread          = vread_hpet,
778 #endif
779 };
780
781 static int hpet_clocksource_register(void)
782 {
783         u64 start, now;
784         cycle_t t1;
785
786         /* Start the counter */
787         hpet_restart_counter();
788
789         /* Verify whether hpet counter works */
790         t1 = hpet_readl(HPET_COUNTER);
791         rdtscll(start);
792
793         /*
794          * We don't know the TSC frequency yet, but waiting for
795          * 200000 TSC cycles is safe:
796          * 4 GHz == 50us
797          * 1 GHz == 200us
798          */
799         do {
800                 rep_nop();
801                 rdtscll(now);
802         } while ((now - start) < 200000UL);
803
804         if (t1 == hpet_readl(HPET_COUNTER)) {
805                 printk(KERN_WARNING
806                        "HPET counter not counting. HPET disabled\n");
807                 return -ENODEV;
808         }
809
810         /*
811          * The definition of mult is (include/linux/clocksource.h)
812          * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
813          * so we first need to convert hpet_period to ns/cyc units:
814          *  mult/2^shift = ns/cyc = hpet_period/10^6
815          *  mult = (hpet_period * 2^shift)/10^6
816          *  mult = (hpet_period << shift)/FSEC_PER_NSEC
817          */
818         clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
819
820         clocksource_register(&clocksource_hpet);
821
822         return 0;
823 }
824
825 /**
826  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
827  */
828 int __init hpet_enable(void)
829 {
830         unsigned int id;
831         int i;
832
833         if (!is_hpet_capable())
834                 return 0;
835
836         hpet_set_mapping();
837
838         /*
839          * Read the period and check for a sane value:
840          */
841         hpet_period = hpet_readl(HPET_PERIOD);
842
843         /*
844          * AMD SB700 based systems with spread spectrum enabled use a
845          * SMM based HPET emulation to provide proper frequency
846          * setting. The SMM code is initialized with the first HPET
847          * register access and takes some time to complete. During
848          * this time the config register reads 0xffffffff. We check
849          * for max. 1000 loops whether the config register reads a non
850          * 0xffffffff value to make sure that HPET is up and running
851          * before we go further. A counting loop is safe, as the HPET
852          * access takes thousands of CPU cycles. On non SB700 based
853          * machines this check is only done once and has no side
854          * effects.
855          */
856         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
857                 if (i == 1000) {
858                         printk(KERN_WARNING
859                                "HPET config register value = 0xFFFFFFFF. "
860                                "Disabling HPET\n");
861                         goto out_nohpet;
862                 }
863         }
864
865         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
866                 goto out_nohpet;
867
868         /*
869          * Read the HPET ID register to retrieve the IRQ routing
870          * information and the number of channels
871          */
872         id = hpet_readl(HPET_ID);
873         hpet_print_config();
874
875 #ifdef CONFIG_HPET_EMULATE_RTC
876         /*
877          * The legacy routing mode needs at least two channels, tick timer
878          * and the rtc emulation channel.
879          */
880         if (!(id & HPET_ID_NUMBER))
881                 goto out_nohpet;
882 #endif
883
884         if (hpet_clocksource_register())
885                 goto out_nohpet;
886
887         if (id & HPET_ID_LEGSUP) {
888                 hpet_legacy_clockevent_register();
889                 return 1;
890         }
891         return 0;
892
893 out_nohpet:
894         hpet_clear_mapping();
895         hpet_address = 0;
896         return 0;
897 }
898
899 /*
900  * Needs to be late, as the reserve_timer code calls kalloc !
901  *
902  * Not a problem on i386 as hpet_enable is called from late_time_init,
903  * but on x86_64 it is necessary !
904  */
905 static __init int hpet_late_init(void)
906 {
907         int cpu;
908
909         if (boot_hpet_disable)
910                 return -ENODEV;
911
912         if (!hpet_address) {
913                 if (!force_hpet_address)
914                         return -ENODEV;
915
916                 hpet_address = force_hpet_address;
917                 hpet_enable();
918         }
919
920         if (!hpet_virt_address)
921                 return -ENODEV;
922
923         if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
924                 hpet_msi_capability_lookup(2);
925         else
926                 hpet_msi_capability_lookup(0);
927
928         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
929         hpet_print_config();
930
931         if (boot_cpu_has(X86_FEATURE_ARAT))
932                 return 0;
933
934         for_each_online_cpu(cpu) {
935                 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
936         }
937
938         /* This notifier should be called after workqueue is ready */
939         hotcpu_notifier(hpet_cpuhp_notify, -20);
940
941         return 0;
942 }
943 fs_initcall(hpet_late_init);
944
945 void hpet_disable(void)
946 {
947         if (is_hpet_capable()) {
948                 unsigned int cfg = hpet_readl(HPET_CFG);
949
950                 if (hpet_legacy_int_enabled) {
951                         cfg &= ~HPET_CFG_LEGACY;
952                         hpet_legacy_int_enabled = 0;
953                 }
954                 cfg &= ~HPET_CFG_ENABLE;
955                 hpet_writel(cfg, HPET_CFG);
956         }
957 }
958
959 #ifdef CONFIG_HPET_EMULATE_RTC
960
961 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
962  * is enabled, we support RTC interrupt functionality in software.
963  * RTC has 3 kinds of interrupts:
964  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
965  *    is updated
966  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
967  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
968  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
969  * (1) and (2) above are implemented using polling at a frequency of
970  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
971  * overhead. (DEFAULT_RTC_INT_FREQ)
972  * For (3), we use interrupts at 64Hz or user specified periodic
973  * frequency, whichever is higher.
974  */
975 #include <linux/mc146818rtc.h>
976 #include <linux/rtc.h>
977 #include <asm/rtc.h>
978
979 #define DEFAULT_RTC_INT_FREQ    64
980 #define DEFAULT_RTC_SHIFT       6
981 #define RTC_NUM_INTS            1
982
983 static unsigned long hpet_rtc_flags;
984 static int hpet_prev_update_sec;
985 static struct rtc_time hpet_alarm_time;
986 static unsigned long hpet_pie_count;
987 static u32 hpet_t1_cmp;
988 static u32 hpet_default_delta;
989 static u32 hpet_pie_delta;
990 static unsigned long hpet_pie_limit;
991
992 static rtc_irq_handler irq_handler;
993
994 /*
995  * Check that the hpet counter c1 is ahead of the c2
996  */
997 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
998 {
999         return (s32)(c2 - c1) < 0;
1000 }
1001
1002 /*
1003  * Registers a IRQ handler.
1004  */
1005 int hpet_register_irq_handler(rtc_irq_handler handler)
1006 {
1007         if (!is_hpet_enabled())
1008                 return -ENODEV;
1009         if (irq_handler)
1010                 return -EBUSY;
1011
1012         irq_handler = handler;
1013
1014         return 0;
1015 }
1016 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1017
1018 /*
1019  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1020  * and does cleanup.
1021  */
1022 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1023 {
1024         if (!is_hpet_enabled())
1025                 return;
1026
1027         irq_handler = NULL;
1028         hpet_rtc_flags = 0;
1029 }
1030 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1031
1032 /*
1033  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1034  * is not supported by all HPET implementations for timer 1.
1035  *
1036  * hpet_rtc_timer_init() is called when the rtc is initialized.
1037  */
1038 int hpet_rtc_timer_init(void)
1039 {
1040         unsigned int cfg, cnt, delta;
1041         unsigned long flags;
1042
1043         if (!is_hpet_enabled())
1044                 return 0;
1045
1046         if (!hpet_default_delta) {
1047                 uint64_t clc;
1048
1049                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1050                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1051                 hpet_default_delta = clc;
1052         }
1053
1054         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1055                 delta = hpet_default_delta;
1056         else
1057                 delta = hpet_pie_delta;
1058
1059         local_irq_save(flags);
1060
1061         cnt = delta + hpet_readl(HPET_COUNTER);
1062         hpet_writel(cnt, HPET_T1_CMP);
1063         hpet_t1_cmp = cnt;
1064
1065         cfg = hpet_readl(HPET_T1_CFG);
1066         cfg &= ~HPET_TN_PERIODIC;
1067         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1068         hpet_writel(cfg, HPET_T1_CFG);
1069
1070         local_irq_restore(flags);
1071
1072         return 1;
1073 }
1074 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1075
1076 /*
1077  * The functions below are called from rtc driver.
1078  * Return 0 if HPET is not being used.
1079  * Otherwise do the necessary changes and return 1.
1080  */
1081 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1082 {
1083         if (!is_hpet_enabled())
1084                 return 0;
1085
1086         hpet_rtc_flags &= ~bit_mask;
1087         return 1;
1088 }
1089 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1090
1091 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1092 {
1093         unsigned long oldbits = hpet_rtc_flags;
1094
1095         if (!is_hpet_enabled())
1096                 return 0;
1097
1098         hpet_rtc_flags |= bit_mask;
1099
1100         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1101                 hpet_prev_update_sec = -1;
1102
1103         if (!oldbits)
1104                 hpet_rtc_timer_init();
1105
1106         return 1;
1107 }
1108 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1109
1110 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1111                         unsigned char sec)
1112 {
1113         if (!is_hpet_enabled())
1114                 return 0;
1115
1116         hpet_alarm_time.tm_hour = hrs;
1117         hpet_alarm_time.tm_min = min;
1118         hpet_alarm_time.tm_sec = sec;
1119
1120         return 1;
1121 }
1122 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1123
1124 int hpet_set_periodic_freq(unsigned long freq)
1125 {
1126         uint64_t clc;
1127
1128         if (!is_hpet_enabled())
1129                 return 0;
1130
1131         if (freq <= DEFAULT_RTC_INT_FREQ)
1132                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1133         else {
1134                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1135                 do_div(clc, freq);
1136                 clc >>= hpet_clockevent.shift;
1137                 hpet_pie_delta = clc;
1138         }
1139         return 1;
1140 }
1141 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1142
1143 int hpet_rtc_dropped_irq(void)
1144 {
1145         return is_hpet_enabled();
1146 }
1147 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1148
1149 static void hpet_rtc_timer_reinit(void)
1150 {
1151         unsigned int cfg, delta;
1152         int lost_ints = -1;
1153
1154         if (unlikely(!hpet_rtc_flags)) {
1155                 cfg = hpet_readl(HPET_T1_CFG);
1156                 cfg &= ~HPET_TN_ENABLE;
1157                 hpet_writel(cfg, HPET_T1_CFG);
1158                 return;
1159         }
1160
1161         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1162                 delta = hpet_default_delta;
1163         else
1164                 delta = hpet_pie_delta;
1165
1166         /*
1167          * Increment the comparator value until we are ahead of the
1168          * current count.
1169          */
1170         do {
1171                 hpet_t1_cmp += delta;
1172                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1173                 lost_ints++;
1174         } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1175
1176         if (lost_ints) {
1177                 if (hpet_rtc_flags & RTC_PIE)
1178                         hpet_pie_count += lost_ints;
1179                 if (printk_ratelimit())
1180                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1181                                 lost_ints);
1182         }
1183 }
1184
1185 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1186 {
1187         struct rtc_time curr_time;
1188         unsigned long rtc_int_flag = 0;
1189
1190         hpet_rtc_timer_reinit();
1191         memset(&curr_time, 0, sizeof(struct rtc_time));
1192
1193         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1194                 get_rtc_time(&curr_time);
1195
1196         if (hpet_rtc_flags & RTC_UIE &&
1197             curr_time.tm_sec != hpet_prev_update_sec) {
1198                 if (hpet_prev_update_sec >= 0)
1199                         rtc_int_flag = RTC_UF;
1200                 hpet_prev_update_sec = curr_time.tm_sec;
1201         }
1202
1203         if (hpet_rtc_flags & RTC_PIE &&
1204             ++hpet_pie_count >= hpet_pie_limit) {
1205                 rtc_int_flag |= RTC_PF;
1206                 hpet_pie_count = 0;
1207         }
1208
1209         if (hpet_rtc_flags & RTC_AIE &&
1210             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1211             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1212             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1213                         rtc_int_flag |= RTC_AF;
1214
1215         if (rtc_int_flag) {
1216                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1217                 if (irq_handler)
1218                         irq_handler(rtc_int_flag, dev_id);
1219         }
1220         return IRQ_HANDLED;
1221 }
1222 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1223 #endif