Merge branch 'x86-vdso-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[sfrench/cifs-2.6.git] / arch / x86 / kernel / hpet.c
1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/export.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/i8253.h>
8 #include <linux/slab.h>
9 #include <linux/hpet.h>
10 #include <linux/init.h>
11 #include <linux/cpu.h>
12 #include <linux/pm.h>
13 #include <linux/io.h>
14
15 #include <asm/fixmap.h>
16 #include <asm/hpet.h>
17 #include <asm/time.h>
18
19 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
20
21 /* FSEC = 10^-15
22    NSEC = 10^-9 */
23 #define FSEC_PER_NSEC                   1000000L
24
25 #define HPET_DEV_USED_BIT               2
26 #define HPET_DEV_USED                   (1 << HPET_DEV_USED_BIT)
27 #define HPET_DEV_VALID                  0x8
28 #define HPET_DEV_FSB_CAP                0x1000
29 #define HPET_DEV_PERI_CAP               0x2000
30
31 #define HPET_MIN_CYCLES                 128
32 #define HPET_MIN_PROG_DELTA             (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
33
34 /*
35  * HPET address is set in acpi/boot.c, when an ACPI entry exists
36  */
37 unsigned long                           hpet_address;
38 u8                                      hpet_blockid; /* OS timer block num */
39 u8                                      hpet_msi_disable;
40
41 #ifdef CONFIG_PCI_MSI
42 static unsigned long                    hpet_num_timers;
43 #endif
44 static void __iomem                     *hpet_virt_address;
45
46 struct hpet_dev {
47         struct clock_event_device       evt;
48         unsigned int                    num;
49         int                             cpu;
50         unsigned int                    irq;
51         unsigned int                    flags;
52         char                            name[10];
53 };
54
55 inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
56 {
57         return container_of(evtdev, struct hpet_dev, evt);
58 }
59
60 inline unsigned int hpet_readl(unsigned int a)
61 {
62         return readl(hpet_virt_address + a);
63 }
64
65 static inline void hpet_writel(unsigned int d, unsigned int a)
66 {
67         writel(d, hpet_virt_address + a);
68 }
69
70 #ifdef CONFIG_X86_64
71 #include <asm/pgtable.h>
72 #endif
73
74 static inline void hpet_set_mapping(void)
75 {
76         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
77 #ifdef CONFIG_X86_64
78         __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
79 #endif
80 }
81
82 static inline void hpet_clear_mapping(void)
83 {
84         iounmap(hpet_virt_address);
85         hpet_virt_address = NULL;
86 }
87
88 /*
89  * HPET command line enable / disable
90  */
91 static int boot_hpet_disable;
92 int hpet_force_user;
93 static int hpet_verbose;
94
95 static int __init hpet_setup(char *str)
96 {
97         while (str) {
98                 char *next = strchr(str, ',');
99
100                 if (next)
101                         *next++ = 0;
102                 if (!strncmp("disable", str, 7))
103                         boot_hpet_disable = 1;
104                 if (!strncmp("force", str, 5))
105                         hpet_force_user = 1;
106                 if (!strncmp("verbose", str, 7))
107                         hpet_verbose = 1;
108                 str = next;
109         }
110         return 1;
111 }
112 __setup("hpet=", hpet_setup);
113
114 static int __init disable_hpet(char *str)
115 {
116         boot_hpet_disable = 1;
117         return 1;
118 }
119 __setup("nohpet", disable_hpet);
120
121 static inline int is_hpet_capable(void)
122 {
123         return !boot_hpet_disable && hpet_address;
124 }
125
126 /*
127  * HPET timer interrupt enable / disable
128  */
129 static int hpet_legacy_int_enabled;
130
131 /**
132  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
133  */
134 int is_hpet_enabled(void)
135 {
136         return is_hpet_capable() && hpet_legacy_int_enabled;
137 }
138 EXPORT_SYMBOL_GPL(is_hpet_enabled);
139
140 static void _hpet_print_config(const char *function, int line)
141 {
142         u32 i, timers, l, h;
143         printk(KERN_INFO "hpet: %s(%d):\n", function, line);
144         l = hpet_readl(HPET_ID);
145         h = hpet_readl(HPET_PERIOD);
146         timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
147         printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
148         l = hpet_readl(HPET_CFG);
149         h = hpet_readl(HPET_STATUS);
150         printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
151         l = hpet_readl(HPET_COUNTER);
152         h = hpet_readl(HPET_COUNTER+4);
153         printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
154
155         for (i = 0; i < timers; i++) {
156                 l = hpet_readl(HPET_Tn_CFG(i));
157                 h = hpet_readl(HPET_Tn_CFG(i)+4);
158                 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
159                        i, l, h);
160                 l = hpet_readl(HPET_Tn_CMP(i));
161                 h = hpet_readl(HPET_Tn_CMP(i)+4);
162                 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
163                        i, l, h);
164                 l = hpet_readl(HPET_Tn_ROUTE(i));
165                 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
166                 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
167                        i, l, h);
168         }
169 }
170
171 #define hpet_print_config()                                     \
172 do {                                                            \
173         if (hpet_verbose)                                       \
174                 _hpet_print_config(__FUNCTION__, __LINE__);     \
175 } while (0)
176
177 /*
178  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
179  * timer 0 and timer 1 in case of RTC emulation.
180  */
181 #ifdef CONFIG_HPET
182
183 static void hpet_reserve_msi_timers(struct hpet_data *hd);
184
185 static void hpet_reserve_platform_timers(unsigned int id)
186 {
187         struct hpet __iomem *hpet = hpet_virt_address;
188         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
189         unsigned int nrtimers, i;
190         struct hpet_data hd;
191
192         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
193
194         memset(&hd, 0, sizeof(hd));
195         hd.hd_phys_address      = hpet_address;
196         hd.hd_address           = hpet;
197         hd.hd_nirqs             = nrtimers;
198         hpet_reserve_timer(&hd, 0);
199
200 #ifdef CONFIG_HPET_EMULATE_RTC
201         hpet_reserve_timer(&hd, 1);
202 #endif
203
204         /*
205          * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
206          * is wrong for i8259!) not the output IRQ.  Many BIOS writers
207          * don't bother configuring *any* comparator interrupts.
208          */
209         hd.hd_irq[0] = HPET_LEGACY_8254;
210         hd.hd_irq[1] = HPET_LEGACY_RTC;
211
212         for (i = 2; i < nrtimers; timer++, i++) {
213                 hd.hd_irq[i] = (readl(&timer->hpet_config) &
214                         Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
215         }
216
217         hpet_reserve_msi_timers(&hd);
218
219         hpet_alloc(&hd);
220
221 }
222 #else
223 static void hpet_reserve_platform_timers(unsigned int id) { }
224 #endif
225
226 /*
227  * Common hpet info
228  */
229 static unsigned long hpet_freq;
230
231 static void hpet_legacy_set_mode(enum clock_event_mode mode,
232                           struct clock_event_device *evt);
233 static int hpet_legacy_next_event(unsigned long delta,
234                            struct clock_event_device *evt);
235
236 /*
237  * The hpet clock event device
238  */
239 static struct clock_event_device hpet_clockevent = {
240         .name           = "hpet",
241         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
242         .set_mode       = hpet_legacy_set_mode,
243         .set_next_event = hpet_legacy_next_event,
244         .irq            = 0,
245         .rating         = 50,
246 };
247
248 static void hpet_stop_counter(void)
249 {
250         unsigned long cfg = hpet_readl(HPET_CFG);
251         cfg &= ~HPET_CFG_ENABLE;
252         hpet_writel(cfg, HPET_CFG);
253 }
254
255 static void hpet_reset_counter(void)
256 {
257         hpet_writel(0, HPET_COUNTER);
258         hpet_writel(0, HPET_COUNTER + 4);
259 }
260
261 static void hpet_start_counter(void)
262 {
263         unsigned int cfg = hpet_readl(HPET_CFG);
264         cfg |= HPET_CFG_ENABLE;
265         hpet_writel(cfg, HPET_CFG);
266 }
267
268 static void hpet_restart_counter(void)
269 {
270         hpet_stop_counter();
271         hpet_reset_counter();
272         hpet_start_counter();
273 }
274
275 static void hpet_resume_device(void)
276 {
277         force_hpet_resume();
278 }
279
280 static void hpet_resume_counter(struct clocksource *cs)
281 {
282         hpet_resume_device();
283         hpet_restart_counter();
284 }
285
286 static void hpet_enable_legacy_int(void)
287 {
288         unsigned int cfg = hpet_readl(HPET_CFG);
289
290         cfg |= HPET_CFG_LEGACY;
291         hpet_writel(cfg, HPET_CFG);
292         hpet_legacy_int_enabled = 1;
293 }
294
295 static void hpet_legacy_clockevent_register(void)
296 {
297         /* Start HPET legacy interrupts */
298         hpet_enable_legacy_int();
299
300         /*
301          * Start hpet with the boot cpu mask and make it
302          * global after the IO_APIC has been initialized.
303          */
304         hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
305         clockevents_config_and_register(&hpet_clockevent, hpet_freq,
306                                         HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
307         global_clock_event = &hpet_clockevent;
308         printk(KERN_DEBUG "hpet clockevent registered\n");
309 }
310
311 static int hpet_setup_msi_irq(unsigned int irq);
312
313 static void hpet_set_mode(enum clock_event_mode mode,
314                           struct clock_event_device *evt, int timer)
315 {
316         unsigned int cfg, cmp, now;
317         uint64_t delta;
318
319         switch (mode) {
320         case CLOCK_EVT_MODE_PERIODIC:
321                 hpet_stop_counter();
322                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
323                 delta >>= evt->shift;
324                 now = hpet_readl(HPET_COUNTER);
325                 cmp = now + (unsigned int) delta;
326                 cfg = hpet_readl(HPET_Tn_CFG(timer));
327                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
328                        HPET_TN_SETVAL | HPET_TN_32BIT;
329                 hpet_writel(cfg, HPET_Tn_CFG(timer));
330                 hpet_writel(cmp, HPET_Tn_CMP(timer));
331                 udelay(1);
332                 /*
333                  * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
334                  * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
335                  * bit is automatically cleared after the first write.
336                  * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
337                  * Publication # 24674)
338                  */
339                 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
340                 hpet_start_counter();
341                 hpet_print_config();
342                 break;
343
344         case CLOCK_EVT_MODE_ONESHOT:
345                 cfg = hpet_readl(HPET_Tn_CFG(timer));
346                 cfg &= ~HPET_TN_PERIODIC;
347                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
348                 hpet_writel(cfg, HPET_Tn_CFG(timer));
349                 break;
350
351         case CLOCK_EVT_MODE_UNUSED:
352         case CLOCK_EVT_MODE_SHUTDOWN:
353                 cfg = hpet_readl(HPET_Tn_CFG(timer));
354                 cfg &= ~HPET_TN_ENABLE;
355                 hpet_writel(cfg, HPET_Tn_CFG(timer));
356                 break;
357
358         case CLOCK_EVT_MODE_RESUME:
359                 if (timer == 0) {
360                         hpet_enable_legacy_int();
361                 } else {
362                         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
363                         hpet_setup_msi_irq(hdev->irq);
364                         disable_irq(hdev->irq);
365                         irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
366                         enable_irq(hdev->irq);
367                 }
368                 hpet_print_config();
369                 break;
370         }
371 }
372
373 static int hpet_next_event(unsigned long delta,
374                            struct clock_event_device *evt, int timer)
375 {
376         u32 cnt;
377         s32 res;
378
379         cnt = hpet_readl(HPET_COUNTER);
380         cnt += (u32) delta;
381         hpet_writel(cnt, HPET_Tn_CMP(timer));
382
383         /*
384          * HPETs are a complete disaster. The compare register is
385          * based on a equal comparison and neither provides a less
386          * than or equal functionality (which would require to take
387          * the wraparound into account) nor a simple count down event
388          * mode. Further the write to the comparator register is
389          * delayed internally up to two HPET clock cycles in certain
390          * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
391          * longer delays. We worked around that by reading back the
392          * compare register, but that required another workaround for
393          * ICH9,10 chips where the first readout after write can
394          * return the old stale value. We already had a minimum
395          * programming delta of 5us enforced, but a NMI or SMI hitting
396          * between the counter readout and the comparator write can
397          * move us behind that point easily. Now instead of reading
398          * the compare register back several times, we make the ETIME
399          * decision based on the following: Return ETIME if the
400          * counter value after the write is less than HPET_MIN_CYCLES
401          * away from the event or if the counter is already ahead of
402          * the event. The minimum programming delta for the generic
403          * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
404          */
405         res = (s32)(cnt - hpet_readl(HPET_COUNTER));
406
407         return res < HPET_MIN_CYCLES ? -ETIME : 0;
408 }
409
410 static void hpet_legacy_set_mode(enum clock_event_mode mode,
411                         struct clock_event_device *evt)
412 {
413         hpet_set_mode(mode, evt, 0);
414 }
415
416 static int hpet_legacy_next_event(unsigned long delta,
417                         struct clock_event_device *evt)
418 {
419         return hpet_next_event(delta, evt, 0);
420 }
421
422 /*
423  * HPET MSI Support
424  */
425 #ifdef CONFIG_PCI_MSI
426
427 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
428 static struct hpet_dev  *hpet_devs;
429
430 void hpet_msi_unmask(struct irq_data *data)
431 {
432         struct hpet_dev *hdev = data->handler_data;
433         unsigned int cfg;
434
435         /* unmask it */
436         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
437         cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
438         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
439 }
440
441 void hpet_msi_mask(struct irq_data *data)
442 {
443         struct hpet_dev *hdev = data->handler_data;
444         unsigned int cfg;
445
446         /* mask it */
447         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
448         cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
449         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
450 }
451
452 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
453 {
454         hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
455         hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
456 }
457
458 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
459 {
460         msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
461         msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
462         msg->address_hi = 0;
463 }
464
465 static void hpet_msi_set_mode(enum clock_event_mode mode,
466                                 struct clock_event_device *evt)
467 {
468         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
469         hpet_set_mode(mode, evt, hdev->num);
470 }
471
472 static int hpet_msi_next_event(unsigned long delta,
473                                 struct clock_event_device *evt)
474 {
475         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
476         return hpet_next_event(delta, evt, hdev->num);
477 }
478
479 static int hpet_setup_msi_irq(unsigned int irq)
480 {
481         if (x86_msi.setup_hpet_msi(irq, hpet_blockid)) {
482                 destroy_irq(irq);
483                 return -EINVAL;
484         }
485         return 0;
486 }
487
488 static int hpet_assign_irq(struct hpet_dev *dev)
489 {
490         unsigned int irq;
491
492         irq = create_irq_nr(0, -1);
493         if (!irq)
494                 return -EINVAL;
495
496         irq_set_handler_data(irq, dev);
497
498         if (hpet_setup_msi_irq(irq))
499                 return -EINVAL;
500
501         dev->irq = irq;
502         return 0;
503 }
504
505 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
506 {
507         struct hpet_dev *dev = (struct hpet_dev *)data;
508         struct clock_event_device *hevt = &dev->evt;
509
510         if (!hevt->event_handler) {
511                 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
512                                 dev->num);
513                 return IRQ_HANDLED;
514         }
515
516         hevt->event_handler(hevt);
517         return IRQ_HANDLED;
518 }
519
520 static int hpet_setup_irq(struct hpet_dev *dev)
521 {
522
523         if (request_irq(dev->irq, hpet_interrupt_handler,
524                         IRQF_TIMER | IRQF_NOBALANCING,
525                         dev->name, dev))
526                 return -1;
527
528         disable_irq(dev->irq);
529         irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
530         enable_irq(dev->irq);
531
532         printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
533                          dev->name, dev->irq);
534
535         return 0;
536 }
537
538 /* This should be called in specific @cpu */
539 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
540 {
541         struct clock_event_device *evt = &hdev->evt;
542
543         WARN_ON(cpu != smp_processor_id());
544         if (!(hdev->flags & HPET_DEV_VALID))
545                 return;
546
547         if (hpet_setup_msi_irq(hdev->irq))
548                 return;
549
550         hdev->cpu = cpu;
551         per_cpu(cpu_hpet_dev, cpu) = hdev;
552         evt->name = hdev->name;
553         hpet_setup_irq(hdev);
554         evt->irq = hdev->irq;
555
556         evt->rating = 110;
557         evt->features = CLOCK_EVT_FEAT_ONESHOT;
558         if (hdev->flags & HPET_DEV_PERI_CAP)
559                 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
560
561         evt->set_mode = hpet_msi_set_mode;
562         evt->set_next_event = hpet_msi_next_event;
563         evt->cpumask = cpumask_of(hdev->cpu);
564
565         clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
566                                         0x7FFFFFFF);
567 }
568
569 #ifdef CONFIG_HPET
570 /* Reserve at least one timer for userspace (/dev/hpet) */
571 #define RESERVE_TIMERS 1
572 #else
573 #define RESERVE_TIMERS 0
574 #endif
575
576 static void hpet_msi_capability_lookup(unsigned int start_timer)
577 {
578         unsigned int id;
579         unsigned int num_timers;
580         unsigned int num_timers_used = 0;
581         int i;
582
583         if (hpet_msi_disable)
584                 return;
585
586         if (boot_cpu_has(X86_FEATURE_ARAT))
587                 return;
588         id = hpet_readl(HPET_ID);
589
590         num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
591         num_timers++; /* Value read out starts from 0 */
592         hpet_print_config();
593
594         hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
595         if (!hpet_devs)
596                 return;
597
598         hpet_num_timers = num_timers;
599
600         for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
601                 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
602                 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
603
604                 /* Only consider HPET timer with MSI support */
605                 if (!(cfg & HPET_TN_FSB_CAP))
606                         continue;
607
608                 hdev->flags = 0;
609                 if (cfg & HPET_TN_PERIODIC_CAP)
610                         hdev->flags |= HPET_DEV_PERI_CAP;
611                 hdev->num = i;
612
613                 sprintf(hdev->name, "hpet%d", i);
614                 if (hpet_assign_irq(hdev))
615                         continue;
616
617                 hdev->flags |= HPET_DEV_FSB_CAP;
618                 hdev->flags |= HPET_DEV_VALID;
619                 num_timers_used++;
620                 if (num_timers_used == num_possible_cpus())
621                         break;
622         }
623
624         printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
625                 num_timers, num_timers_used);
626 }
627
628 #ifdef CONFIG_HPET
629 static void hpet_reserve_msi_timers(struct hpet_data *hd)
630 {
631         int i;
632
633         if (!hpet_devs)
634                 return;
635
636         for (i = 0; i < hpet_num_timers; i++) {
637                 struct hpet_dev *hdev = &hpet_devs[i];
638
639                 if (!(hdev->flags & HPET_DEV_VALID))
640                         continue;
641
642                 hd->hd_irq[hdev->num] = hdev->irq;
643                 hpet_reserve_timer(hd, hdev->num);
644         }
645 }
646 #endif
647
648 static struct hpet_dev *hpet_get_unused_timer(void)
649 {
650         int i;
651
652         if (!hpet_devs)
653                 return NULL;
654
655         for (i = 0; i < hpet_num_timers; i++) {
656                 struct hpet_dev *hdev = &hpet_devs[i];
657
658                 if (!(hdev->flags & HPET_DEV_VALID))
659                         continue;
660                 if (test_and_set_bit(HPET_DEV_USED_BIT,
661                         (unsigned long *)&hdev->flags))
662                         continue;
663                 return hdev;
664         }
665         return NULL;
666 }
667
668 struct hpet_work_struct {
669         struct delayed_work work;
670         struct completion complete;
671 };
672
673 static void hpet_work(struct work_struct *w)
674 {
675         struct hpet_dev *hdev;
676         int cpu = smp_processor_id();
677         struct hpet_work_struct *hpet_work;
678
679         hpet_work = container_of(w, struct hpet_work_struct, work.work);
680
681         hdev = hpet_get_unused_timer();
682         if (hdev)
683                 init_one_hpet_msi_clockevent(hdev, cpu);
684
685         complete(&hpet_work->complete);
686 }
687
688 static int hpet_cpuhp_notify(struct notifier_block *n,
689                 unsigned long action, void *hcpu)
690 {
691         unsigned long cpu = (unsigned long)hcpu;
692         struct hpet_work_struct work;
693         struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
694
695         switch (action & 0xf) {
696         case CPU_ONLINE:
697                 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
698                 init_completion(&work.complete);
699                 /* FIXME: add schedule_work_on() */
700                 schedule_delayed_work_on(cpu, &work.work, 0);
701                 wait_for_completion(&work.complete);
702                 destroy_delayed_work_on_stack(&work.work);
703                 break;
704         case CPU_DEAD:
705                 if (hdev) {
706                         free_irq(hdev->irq, hdev);
707                         hdev->flags &= ~HPET_DEV_USED;
708                         per_cpu(cpu_hpet_dev, cpu) = NULL;
709                 }
710                 break;
711         }
712         return NOTIFY_OK;
713 }
714 #else
715
716 static int hpet_setup_msi_irq(unsigned int irq)
717 {
718         return 0;
719 }
720 static void hpet_msi_capability_lookup(unsigned int start_timer)
721 {
722         return;
723 }
724
725 #ifdef CONFIG_HPET
726 static void hpet_reserve_msi_timers(struct hpet_data *hd)
727 {
728         return;
729 }
730 #endif
731
732 static int hpet_cpuhp_notify(struct notifier_block *n,
733                 unsigned long action, void *hcpu)
734 {
735         return NOTIFY_OK;
736 }
737
738 #endif
739
740 /*
741  * Clock source related code
742  */
743 static cycle_t read_hpet(struct clocksource *cs)
744 {
745         return (cycle_t)hpet_readl(HPET_COUNTER);
746 }
747
748 static struct clocksource clocksource_hpet = {
749         .name           = "hpet",
750         .rating         = 250,
751         .read           = read_hpet,
752         .mask           = HPET_MASK,
753         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
754         .resume         = hpet_resume_counter,
755         .archdata       = { .vclock_mode = VCLOCK_HPET },
756 };
757
758 static int hpet_clocksource_register(void)
759 {
760         u64 start, now;
761         cycle_t t1;
762
763         /* Start the counter */
764         hpet_restart_counter();
765
766         /* Verify whether hpet counter works */
767         t1 = hpet_readl(HPET_COUNTER);
768         rdtscll(start);
769
770         /*
771          * We don't know the TSC frequency yet, but waiting for
772          * 200000 TSC cycles is safe:
773          * 4 GHz == 50us
774          * 1 GHz == 200us
775          */
776         do {
777                 rep_nop();
778                 rdtscll(now);
779         } while ((now - start) < 200000UL);
780
781         if (t1 == hpet_readl(HPET_COUNTER)) {
782                 printk(KERN_WARNING
783                        "HPET counter not counting. HPET disabled\n");
784                 return -ENODEV;
785         }
786
787         clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
788         return 0;
789 }
790
791 static u32 *hpet_boot_cfg;
792
793 /**
794  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
795  */
796 int __init hpet_enable(void)
797 {
798         u32 hpet_period, cfg, id;
799         u64 freq;
800         unsigned int i, last;
801
802         if (!is_hpet_capable())
803                 return 0;
804
805         hpet_set_mapping();
806
807         /*
808          * Read the period and check for a sane value:
809          */
810         hpet_period = hpet_readl(HPET_PERIOD);
811
812         /*
813          * AMD SB700 based systems with spread spectrum enabled use a
814          * SMM based HPET emulation to provide proper frequency
815          * setting. The SMM code is initialized with the first HPET
816          * register access and takes some time to complete. During
817          * this time the config register reads 0xffffffff. We check
818          * for max. 1000 loops whether the config register reads a non
819          * 0xffffffff value to make sure that HPET is up and running
820          * before we go further. A counting loop is safe, as the HPET
821          * access takes thousands of CPU cycles. On non SB700 based
822          * machines this check is only done once and has no side
823          * effects.
824          */
825         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
826                 if (i == 1000) {
827                         printk(KERN_WARNING
828                                "HPET config register value = 0xFFFFFFFF. "
829                                "Disabling HPET\n");
830                         goto out_nohpet;
831                 }
832         }
833
834         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
835                 goto out_nohpet;
836
837         /*
838          * The period is a femto seconds value. Convert it to a
839          * frequency.
840          */
841         freq = FSEC_PER_SEC;
842         do_div(freq, hpet_period);
843         hpet_freq = freq;
844
845         /*
846          * Read the HPET ID register to retrieve the IRQ routing
847          * information and the number of channels
848          */
849         id = hpet_readl(HPET_ID);
850         hpet_print_config();
851
852         last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
853
854 #ifdef CONFIG_HPET_EMULATE_RTC
855         /*
856          * The legacy routing mode needs at least two channels, tick timer
857          * and the rtc emulation channel.
858          */
859         if (!last)
860                 goto out_nohpet;
861 #endif
862
863         cfg = hpet_readl(HPET_CFG);
864         hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
865                                 GFP_KERNEL);
866         if (hpet_boot_cfg)
867                 *hpet_boot_cfg = cfg;
868         else
869                 pr_warn("HPET initial state will not be saved\n");
870         cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
871         hpet_writel(cfg, HPET_CFG);
872         if (cfg)
873                 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
874                         cfg);
875
876         for (i = 0; i <= last; ++i) {
877                 cfg = hpet_readl(HPET_Tn_CFG(i));
878                 if (hpet_boot_cfg)
879                         hpet_boot_cfg[i + 1] = cfg;
880                 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
881                 hpet_writel(cfg, HPET_Tn_CFG(i));
882                 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
883                          | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
884                          | HPET_TN_FSB | HPET_TN_FSB_CAP);
885                 if (cfg)
886                         pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
887                                 cfg, i);
888         }
889         hpet_print_config();
890
891         if (hpet_clocksource_register())
892                 goto out_nohpet;
893
894         if (id & HPET_ID_LEGSUP) {
895                 hpet_legacy_clockevent_register();
896                 return 1;
897         }
898         return 0;
899
900 out_nohpet:
901         hpet_clear_mapping();
902         hpet_address = 0;
903         return 0;
904 }
905
906 /*
907  * Needs to be late, as the reserve_timer code calls kalloc !
908  *
909  * Not a problem on i386 as hpet_enable is called from late_time_init,
910  * but on x86_64 it is necessary !
911  */
912 static __init int hpet_late_init(void)
913 {
914         int cpu;
915
916         if (boot_hpet_disable)
917                 return -ENODEV;
918
919         if (!hpet_address) {
920                 if (!force_hpet_address)
921                         return -ENODEV;
922
923                 hpet_address = force_hpet_address;
924                 hpet_enable();
925         }
926
927         if (!hpet_virt_address)
928                 return -ENODEV;
929
930         if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
931                 hpet_msi_capability_lookup(2);
932         else
933                 hpet_msi_capability_lookup(0);
934
935         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
936         hpet_print_config();
937
938         if (hpet_msi_disable)
939                 return 0;
940
941         if (boot_cpu_has(X86_FEATURE_ARAT))
942                 return 0;
943
944         for_each_online_cpu(cpu) {
945                 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
946         }
947
948         /* This notifier should be called after workqueue is ready */
949         hotcpu_notifier(hpet_cpuhp_notify, -20);
950
951         return 0;
952 }
953 fs_initcall(hpet_late_init);
954
955 void hpet_disable(void)
956 {
957         if (is_hpet_capable() && hpet_virt_address) {
958                 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
959
960                 if (hpet_boot_cfg)
961                         cfg = *hpet_boot_cfg;
962                 else if (hpet_legacy_int_enabled) {
963                         cfg &= ~HPET_CFG_LEGACY;
964                         hpet_legacy_int_enabled = 0;
965                 }
966                 cfg &= ~HPET_CFG_ENABLE;
967                 hpet_writel(cfg, HPET_CFG);
968
969                 if (!hpet_boot_cfg)
970                         return;
971
972                 id = hpet_readl(HPET_ID);
973                 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
974
975                 for (id = 0; id <= last; ++id)
976                         hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
977
978                 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
979                         hpet_writel(*hpet_boot_cfg, HPET_CFG);
980         }
981 }
982
983 #ifdef CONFIG_HPET_EMULATE_RTC
984
985 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
986  * is enabled, we support RTC interrupt functionality in software.
987  * RTC has 3 kinds of interrupts:
988  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
989  *    is updated
990  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
991  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
992  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
993  * (1) and (2) above are implemented using polling at a frequency of
994  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
995  * overhead. (DEFAULT_RTC_INT_FREQ)
996  * For (3), we use interrupts at 64Hz or user specified periodic
997  * frequency, whichever is higher.
998  */
999 #include <linux/mc146818rtc.h>
1000 #include <linux/rtc.h>
1001 #include <asm/rtc.h>
1002
1003 #define DEFAULT_RTC_INT_FREQ    64
1004 #define DEFAULT_RTC_SHIFT       6
1005 #define RTC_NUM_INTS            1
1006
1007 static unsigned long hpet_rtc_flags;
1008 static int hpet_prev_update_sec;
1009 static struct rtc_time hpet_alarm_time;
1010 static unsigned long hpet_pie_count;
1011 static u32 hpet_t1_cmp;
1012 static u32 hpet_default_delta;
1013 static u32 hpet_pie_delta;
1014 static unsigned long hpet_pie_limit;
1015
1016 static rtc_irq_handler irq_handler;
1017
1018 /*
1019  * Check that the hpet counter c1 is ahead of the c2
1020  */
1021 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1022 {
1023         return (s32)(c2 - c1) < 0;
1024 }
1025
1026 /*
1027  * Registers a IRQ handler.
1028  */
1029 int hpet_register_irq_handler(rtc_irq_handler handler)
1030 {
1031         if (!is_hpet_enabled())
1032                 return -ENODEV;
1033         if (irq_handler)
1034                 return -EBUSY;
1035
1036         irq_handler = handler;
1037
1038         return 0;
1039 }
1040 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1041
1042 /*
1043  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1044  * and does cleanup.
1045  */
1046 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1047 {
1048         if (!is_hpet_enabled())
1049                 return;
1050
1051         irq_handler = NULL;
1052         hpet_rtc_flags = 0;
1053 }
1054 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1055
1056 /*
1057  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1058  * is not supported by all HPET implementations for timer 1.
1059  *
1060  * hpet_rtc_timer_init() is called when the rtc is initialized.
1061  */
1062 int hpet_rtc_timer_init(void)
1063 {
1064         unsigned int cfg, cnt, delta;
1065         unsigned long flags;
1066
1067         if (!is_hpet_enabled())
1068                 return 0;
1069
1070         if (!hpet_default_delta) {
1071                 uint64_t clc;
1072
1073                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1074                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1075                 hpet_default_delta = clc;
1076         }
1077
1078         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1079                 delta = hpet_default_delta;
1080         else
1081                 delta = hpet_pie_delta;
1082
1083         local_irq_save(flags);
1084
1085         cnt = delta + hpet_readl(HPET_COUNTER);
1086         hpet_writel(cnt, HPET_T1_CMP);
1087         hpet_t1_cmp = cnt;
1088
1089         cfg = hpet_readl(HPET_T1_CFG);
1090         cfg &= ~HPET_TN_PERIODIC;
1091         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1092         hpet_writel(cfg, HPET_T1_CFG);
1093
1094         local_irq_restore(flags);
1095
1096         return 1;
1097 }
1098 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1099
1100 static void hpet_disable_rtc_channel(void)
1101 {
1102         unsigned long cfg;
1103         cfg = hpet_readl(HPET_T1_CFG);
1104         cfg &= ~HPET_TN_ENABLE;
1105         hpet_writel(cfg, HPET_T1_CFG);
1106 }
1107
1108 /*
1109  * The functions below are called from rtc driver.
1110  * Return 0 if HPET is not being used.
1111  * Otherwise do the necessary changes and return 1.
1112  */
1113 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1114 {
1115         if (!is_hpet_enabled())
1116                 return 0;
1117
1118         hpet_rtc_flags &= ~bit_mask;
1119         if (unlikely(!hpet_rtc_flags))
1120                 hpet_disable_rtc_channel();
1121
1122         return 1;
1123 }
1124 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1125
1126 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1127 {
1128         unsigned long oldbits = hpet_rtc_flags;
1129
1130         if (!is_hpet_enabled())
1131                 return 0;
1132
1133         hpet_rtc_flags |= bit_mask;
1134
1135         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1136                 hpet_prev_update_sec = -1;
1137
1138         if (!oldbits)
1139                 hpet_rtc_timer_init();
1140
1141         return 1;
1142 }
1143 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1144
1145 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1146                         unsigned char sec)
1147 {
1148         if (!is_hpet_enabled())
1149                 return 0;
1150
1151         hpet_alarm_time.tm_hour = hrs;
1152         hpet_alarm_time.tm_min = min;
1153         hpet_alarm_time.tm_sec = sec;
1154
1155         return 1;
1156 }
1157 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1158
1159 int hpet_set_periodic_freq(unsigned long freq)
1160 {
1161         uint64_t clc;
1162
1163         if (!is_hpet_enabled())
1164                 return 0;
1165
1166         if (freq <= DEFAULT_RTC_INT_FREQ)
1167                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1168         else {
1169                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1170                 do_div(clc, freq);
1171                 clc >>= hpet_clockevent.shift;
1172                 hpet_pie_delta = clc;
1173                 hpet_pie_limit = 0;
1174         }
1175         return 1;
1176 }
1177 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1178
1179 int hpet_rtc_dropped_irq(void)
1180 {
1181         return is_hpet_enabled();
1182 }
1183 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1184
1185 static void hpet_rtc_timer_reinit(void)
1186 {
1187         unsigned int delta;
1188         int lost_ints = -1;
1189
1190         if (unlikely(!hpet_rtc_flags))
1191                 hpet_disable_rtc_channel();
1192
1193         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1194                 delta = hpet_default_delta;
1195         else
1196                 delta = hpet_pie_delta;
1197
1198         /*
1199          * Increment the comparator value until we are ahead of the
1200          * current count.
1201          */
1202         do {
1203                 hpet_t1_cmp += delta;
1204                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1205                 lost_ints++;
1206         } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1207
1208         if (lost_ints) {
1209                 if (hpet_rtc_flags & RTC_PIE)
1210                         hpet_pie_count += lost_ints;
1211                 if (printk_ratelimit())
1212                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1213                                 lost_ints);
1214         }
1215 }
1216
1217 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1218 {
1219         struct rtc_time curr_time;
1220         unsigned long rtc_int_flag = 0;
1221
1222         hpet_rtc_timer_reinit();
1223         memset(&curr_time, 0, sizeof(struct rtc_time));
1224
1225         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1226                 get_rtc_time(&curr_time);
1227
1228         if (hpet_rtc_flags & RTC_UIE &&
1229             curr_time.tm_sec != hpet_prev_update_sec) {
1230                 if (hpet_prev_update_sec >= 0)
1231                         rtc_int_flag = RTC_UF;
1232                 hpet_prev_update_sec = curr_time.tm_sec;
1233         }
1234
1235         if (hpet_rtc_flags & RTC_PIE &&
1236             ++hpet_pie_count >= hpet_pie_limit) {
1237                 rtc_int_flag |= RTC_PF;
1238                 hpet_pie_count = 0;
1239         }
1240
1241         if (hpet_rtc_flags & RTC_AIE &&
1242             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1243             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1244             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1245                         rtc_int_flag |= RTC_AF;
1246
1247         if (rtc_int_flag) {
1248                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1249                 if (irq_handler)
1250                         irq_handler(rtc_int_flag, dev_id);
1251         }
1252         return IRQ_HANDLED;
1253 }
1254 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1255 #endif