arch/x86/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/sysdev.h>
   5 #include <linux/delay.h>
   6 #include <linux/errno.h>
   7 #include <linux/slab.h>
   8 #include <linux/hpet.h>
   9 #include <linux/init.h>
  10 #include <linux/cpu.h>
  11 #include <linux/pm.h>
  12 #include <linux/io.h>
  13
  14 #include <asm/fixmap.h>
  15 #include <asm/i8253.h>
  16 #include <asm/hpet.h>
  17
  18 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
  19 #define HPET_SHIFT                      22
  20
  21 /* FSEC = 10^-15
  22    NSEC = 10^-9 */
  23 #define FSEC_PER_NSEC                   1000000L
  24
  25 #define HPET_DEV_USED_BIT               2
  26 #define HPET_DEV_USED                   (1 << HPET_DEV_USED_BIT)
  27 #define HPET_DEV_VALID                  0x8
  28 #define HPET_DEV_FSB_CAP                0x1000
  29 #define HPET_DEV_PERI_CAP               0x2000
  30
  31 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
  32
  33 /*
  34  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  35  */
  36 unsigned long                           hpet_address;
  37 u8                                      hpet_blockid; /* OS timer block num */
  38 u8                                      hpet_msi_disable;
  39
  40 #ifdef CONFIG_PCI_MSI
  41 static unsigned long                    hpet_num_timers;
  42 #endif
  43 static void __iomem                     *hpet_virt_address;
  44
  45 struct hpet_dev {
  46         struct clock_event_device       evt;
  47         unsigned int                    num;
  48         int                             cpu;
  49         unsigned int                    irq;
  50         unsigned int                    flags;
  51         char                            name[10];
  52 };
  53
  54 inline unsigned int hpet_readl(unsigned int a)
  55 {
  56         return readl(hpet_virt_address + a);
  57 }
  58
  59 static inline void hpet_writel(unsigned int d, unsigned int a)
  60 {
  61         writel(d, hpet_virt_address + a);
  62 }
  63
  64 #ifdef CONFIG_X86_64
  65 #include <asm/pgtable.h>
  66 #endif
  67
  68 static inline void hpet_set_mapping(void)
  69 {
  70         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
  71 #ifdef CONFIG_X86_64
  72         __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
  73 #endif
  74 }
  75
  76 static inline void hpet_clear_mapping(void)
  77 {
  78         iounmap(hpet_virt_address);
  79         hpet_virt_address = NULL;
  80 }
  81
  82 /*
  83  * HPET command line enable / disable
  84  */
  85 static int boot_hpet_disable;
  86 int hpet_force_user;
  87 static int hpet_verbose;
  88
  89 static int __init hpet_setup(char *str)
  90 {
  91         if (str) {
  92                 if (!strncmp("disable", str, 7))
  93                         boot_hpet_disable = 1;
  94                 if (!strncmp("force", str, 5))
  95                         hpet_force_user = 1;
  96                 if (!strncmp("verbose", str, 7))
  97                         hpet_verbose = 1;
  98         }
  99         return 1;
 100 }
 101 __setup("hpet=", hpet_setup);
 102
 103 static int __init disable_hpet(char *str)
 104 {
 105         boot_hpet_disable = 1;
 106         return 1;
 107 }
 108 __setup("nohpet", disable_hpet);
 109
 110 static inline int is_hpet_capable(void)
 111 {
 112         return !boot_hpet_disable && hpet_address;
 113 }
 114
 115 /*
 116  * HPET timer interrupt enable / disable
 117  */
 118 static int hpet_legacy_int_enabled;
 119
 120 /**
 121  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 122  */
 123 int is_hpet_enabled(void)
 124 {
 125         return is_hpet_capable() && hpet_legacy_int_enabled;
 126 }
 127 EXPORT_SYMBOL_GPL(is_hpet_enabled);
 128
 129 static void _hpet_print_config(const char *function, int line)
 130 {
 131         u32 i, timers, l, h;
 132         printk(KERN_INFO "hpet: %s(%d):\n", function, line);
 133         l = hpet_readl(HPET_ID);
 134         h = hpet_readl(HPET_PERIOD);
 135         timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 136         printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
 137         l = hpet_readl(HPET_CFG);
 138         h = hpet_readl(HPET_STATUS);
 139         printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
 140         l = hpet_readl(HPET_COUNTER);
 141         h = hpet_readl(HPET_COUNTER+4);
 142         printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
 143
 144         for (i = 0; i < timers; i++) {
 145                 l = hpet_readl(HPET_Tn_CFG(i));
 146                 h = hpet_readl(HPET_Tn_CFG(i)+4);
 147                 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
 148                        i, l, h);
 149                 l = hpet_readl(HPET_Tn_CMP(i));
 150                 h = hpet_readl(HPET_Tn_CMP(i)+4);
 151                 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
 152                        i, l, h);
 153                 l = hpet_readl(HPET_Tn_ROUTE(i));
 154                 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
 155                 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
 156                        i, l, h);
 157         }
 158 }
 159
 160 #define hpet_print_config()                                     \
 161 do {                                                            \
 162         if (hpet_verbose)                                       \
 163                 _hpet_print_config(__FUNCTION__, __LINE__);     \
 164 } while (0)
 165
 166 /*
 167  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 168  * timer 0 and timer 1 in case of RTC emulation.
 169  */
 170 #ifdef CONFIG_HPET
 171
 172 static void hpet_reserve_msi_timers(struct hpet_data *hd);
 173
 174 static void hpet_reserve_platform_timers(unsigned int id)
 175 {
 176         struct hpet __iomem *hpet = hpet_virt_address;
 177         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
 178         unsigned int nrtimers, i;
 179         struct hpet_data hd;
 180
 181         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 182
 183         memset(&hd, 0, sizeof(hd));
 184         hd.hd_phys_address      = hpet_address;
 185         hd.hd_address           = hpet;
 186         hd.hd_nirqs             = nrtimers;
 187         hpet_reserve_timer(&hd, 0);
 188
 189 #ifdef CONFIG_HPET_EMULATE_RTC
 190         hpet_reserve_timer(&hd, 1);
 191 #endif
 192
 193         /*
 194          * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
 195          * is wrong for i8259!) not the output IRQ.  Many BIOS writers
 196          * don't bother configuring *any* comparator interrupts.
 197          */
 198         hd.hd_irq[0] = HPET_LEGACY_8254;
 199         hd.hd_irq[1] = HPET_LEGACY_RTC;
 200
 201         for (i = 2; i < nrtimers; timer++, i++) {
 202                 hd.hd_irq[i] = (readl(&timer->hpet_config) &
 203                         Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
 204         }
 205
 206         hpet_reserve_msi_timers(&hd);
 207
 208         hpet_alloc(&hd);
 209
 210 }
 211 #else
 212 static void hpet_reserve_platform_timers(unsigned int id) { }
 213 #endif
 214
 215 /*
 216  * Common hpet info
 217  */
 218 static unsigned long hpet_period;
 219
 220 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 221                           struct clock_event_device *evt);
 222 static int hpet_legacy_next_event(unsigned long delta,
 223                            struct clock_event_device *evt);
 224
 225 /*
 226  * The hpet clock event device
 227  */
 228 static struct clock_event_device hpet_clockevent = {
 229         .name           = "hpet",
 230         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 231         .set_mode       = hpet_legacy_set_mode,
 232         .set_next_event = hpet_legacy_next_event,
 233         .shift          = 32,
 234         .irq            = 0,
 235         .rating         = 50,
 236 };
 237
 238 static void hpet_stop_counter(void)
 239 {
 240         unsigned long cfg = hpet_readl(HPET_CFG);
 241         cfg &= ~HPET_CFG_ENABLE;
 242         hpet_writel(cfg, HPET_CFG);
 243 }
 244
 245 static void hpet_reset_counter(void)
 246 {
 247         hpet_writel(0, HPET_COUNTER);
 248         hpet_writel(0, HPET_COUNTER + 4);
 249 }
 250
 251 static void hpet_start_counter(void)
 252 {
 253         unsigned int cfg = hpet_readl(HPET_CFG);
 254         cfg |= HPET_CFG_ENABLE;
 255         hpet_writel(cfg, HPET_CFG);
 256 }
 257
 258 static void hpet_restart_counter(void)
 259 {
 260         hpet_stop_counter();
 261         hpet_reset_counter();
 262         hpet_start_counter();
 263 }
 264
 265 static void hpet_resume_device(void)
 266 {
 267         force_hpet_resume();
 268 }
 269
 270 static void hpet_resume_counter(struct clocksource *cs)
 271 {
 272         hpet_resume_device();
 273         hpet_restart_counter();
 274 }
 275
 276 static void hpet_enable_legacy_int(void)
 277 {
 278         unsigned int cfg = hpet_readl(HPET_CFG);
 279
 280         cfg |= HPET_CFG_LEGACY;
 281         hpet_writel(cfg, HPET_CFG);
 282         hpet_legacy_int_enabled = 1;
 283 }
 284
 285 static void hpet_legacy_clockevent_register(void)
 286 {
 287         /* Start HPET legacy interrupts */
 288         hpet_enable_legacy_int();
 289
 290         /*
 291          * The mult factor is defined as (include/linux/clockchips.h)
 292          *  mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
 293          * hpet_period is in units of femtoseconds (per cycle), so
 294          *  mult/2^shift = cyc/ns = 10^6/hpet_period
 295          *  mult = (10^6 * 2^shift)/hpet_period
 296          *  mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
 297          */
 298         hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
 299                                       hpet_period, hpet_clockevent.shift);
 300         /* Calculate the min / max delta */
 301         hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
 302                                                            &hpet_clockevent);
 303         /* 5 usec minimum reprogramming delta. */
 304         hpet_clockevent.min_delta_ns = 5000;
 305
 306         /*
 307          * Start hpet with the boot cpu mask and make it
 308          * global after the IO_APIC has been initialized.
 309          */
 310         hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
 311         clockevents_register_device(&hpet_clockevent);
 312         global_clock_event = &hpet_clockevent;
 313         printk(KERN_DEBUG "hpet clockevent registered\n");
 314 }
 315
 316 static int hpet_setup_msi_irq(unsigned int irq);
 317
 318 static void hpet_set_mode(enum clock_event_mode mode,
 319                           struct clock_event_device *evt, int timer)
 320 {
 321         unsigned int cfg, cmp, now;
 322         uint64_t delta;
 323
 324         switch (mode) {
 325         case CLOCK_EVT_MODE_PERIODIC:
 326                 hpet_stop_counter();
 327                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
 328                 delta >>= evt->shift;
 329                 now = hpet_readl(HPET_COUNTER);
 330                 cmp = now + (unsigned int) delta;
 331                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 332                 /* Make sure we use edge triggered interrupts */
 333                 cfg &= ~HPET_TN_LEVEL;
 334                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
 335                        HPET_TN_SETVAL | HPET_TN_32BIT;
 336                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 337                 hpet_writel(cmp, HPET_Tn_CMP(timer));
 338                 udelay(1);
 339                 /*
 340                  * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
 341                  * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
 342                  * bit is automatically cleared after the first write.
 343                  * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
 344                  * Publication # 24674)
 345                  */
 346                 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
 347                 hpet_start_counter();
 348                 hpet_print_config();
 349                 break;
 350
 351         case CLOCK_EVT_MODE_ONESHOT:
 352                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 353                 cfg &= ~HPET_TN_PERIODIC;
 354                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 355                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 356                 break;
 357
 358         case CLOCK_EVT_MODE_UNUSED:
 359         case CLOCK_EVT_MODE_SHUTDOWN:
 360                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 361                 cfg &= ~HPET_TN_ENABLE;
 362                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 363                 break;
 364
 365         case CLOCK_EVT_MODE_RESUME:
 366                 if (timer == 0) {
 367                         hpet_enable_legacy_int();
 368                 } else {
 369                         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 370                         hpet_setup_msi_irq(hdev->irq);
 371                         disable_irq(hdev->irq);
 372                         irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
 373                         enable_irq(hdev->irq);
 374                 }
 375                 hpet_print_config();
 376                 break;
 377         }
 378 }
 379
 380 static int hpet_next_event(unsigned long delta,
 381                            struct clock_event_device *evt, int timer)
 382 {
 383         u32 cnt;
 384
 385         cnt = hpet_readl(HPET_COUNTER);
 386         cnt += (u32) delta;
 387         hpet_writel(cnt, HPET_Tn_CMP(timer));
 388
 389         /*
 390          * We need to read back the CMP register on certain HPET
 391          * implementations (ATI chipsets) which seem to delay the
 392          * transfer of the compare register into the internal compare
 393          * logic. With small deltas this might actually be too late as
 394          * the counter could already be higher than the compare value
 395          * at that point and we would wait for the next hpet interrupt
 396          * forever. We found out that reading the CMP register back
 397          * forces the transfer so we can rely on the comparison with
 398          * the counter register below. If the read back from the
 399          * compare register does not match the value we programmed
 400          * then we might have a real hardware problem. We can not do
 401          * much about it here, but at least alert the user/admin with
 402          * a prominent warning.
 403          * An erratum on some chipsets (ICH9,..), results in comparator read
 404          * immediately following a write returning old value. Workaround
 405          * for this is to read this value second time, when first
 406          * read returns old value.
 407          */
 408         if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) {
 409                 WARN_ONCE(hpet_readl(HPET_Tn_CMP(timer)) != cnt,
 410                   KERN_WARNING "hpet: compare register read back failed.\n");
 411         }
 412
 413         return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
 414 }
 415
 416 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 417                         struct clock_event_device *evt)
 418 {
 419         hpet_set_mode(mode, evt, 0);
 420 }
 421
 422 static int hpet_legacy_next_event(unsigned long delta,
 423                         struct clock_event_device *evt)
 424 {
 425         return hpet_next_event(delta, evt, 0);
 426 }
 427
 428 /*
 429  * HPET MSI Support
 430  */
 431 #ifdef CONFIG_PCI_MSI
 432
 433 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
 434 static struct hpet_dev  *hpet_devs;
 435
 436 void hpet_msi_unmask(unsigned int irq)
 437 {
 438         struct hpet_dev *hdev = get_irq_data(irq);
 439         unsigned int cfg;
 440
 441         /* unmask it */
 442         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 443         cfg |= HPET_TN_FSB;
 444         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 445 }
 446
 447 void hpet_msi_mask(unsigned int irq)
 448 {
 449         unsigned int cfg;
 450         struct hpet_dev *hdev = get_irq_data(irq);
 451
 452         /* mask it */
 453         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 454         cfg &= ~HPET_TN_FSB;
 455         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 456 }
 457
 458 void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
 459 {
 460         struct hpet_dev *hdev = get_irq_data(irq);
 461
 462         hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
 463         hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
 464 }
 465
 466 void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
 467 {
 468         struct hpet_dev *hdev = get_irq_data(irq);
 469
 470         msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
 471         msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
 472         msg->address_hi = 0;
 473 }
 474
 475 static void hpet_msi_set_mode(enum clock_event_mode mode,
 476                                 struct clock_event_device *evt)
 477 {
 478         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 479         hpet_set_mode(mode, evt, hdev->num);
 480 }
 481
 482 static int hpet_msi_next_event(unsigned long delta,
 483                                 struct clock_event_device *evt)
 484 {
 485         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 486         return hpet_next_event(delta, evt, hdev->num);
 487 }
 488
 489 static int hpet_setup_msi_irq(unsigned int irq)
 490 {
 491         if (arch_setup_hpet_msi(irq, hpet_blockid)) {
 492                 destroy_irq(irq);
 493                 return -EINVAL;
 494         }
 495         return 0;
 496 }
 497
 498 static int hpet_assign_irq(struct hpet_dev *dev)
 499 {
 500         unsigned int irq;
 501
 502         irq = create_irq();
 503         if (!irq)
 504                 return -EINVAL;
 505
 506         set_irq_data(irq, dev);
 507
 508         if (hpet_setup_msi_irq(irq))
 509                 return -EINVAL;
 510
 511         dev->irq = irq;
 512         return 0;
 513 }
 514
 515 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
 516 {
 517         struct hpet_dev *dev = (struct hpet_dev *)data;
 518         struct clock_event_device *hevt = &dev->evt;
 519
 520         if (!hevt->event_handler) {
 521                 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
 522                                 dev->num);
 523                 return IRQ_HANDLED;
 524         }
 525
 526         hevt->event_handler(hevt);
 527         return IRQ_HANDLED;
 528 }
 529
 530 static int hpet_setup_irq(struct hpet_dev *dev)
 531 {
 532
 533         if (request_irq(dev->irq, hpet_interrupt_handler,
 534                         IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
 535                         dev->name, dev))
 536                 return -1;
 537
 538         disable_irq(dev->irq);
 539         irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
 540         enable_irq(dev->irq);
 541
 542         printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
 543                          dev->name, dev->irq);
 544
 545         return 0;
 546 }
 547
 548 /* This should be called in specific @cpu */
 549 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
 550 {
 551         struct clock_event_device *evt = &hdev->evt;
 552         uint64_t hpet_freq;
 553
 554         WARN_ON(cpu != smp_processor_id());
 555         if (!(hdev->flags & HPET_DEV_VALID))
 556                 return;
 557
 558         if (hpet_setup_msi_irq(hdev->irq))
 559                 return;
 560
 561         hdev->cpu = cpu;
 562         per_cpu(cpu_hpet_dev, cpu) = hdev;
 563         evt->name = hdev->name;
 564         hpet_setup_irq(hdev);
 565         evt->irq = hdev->irq;
 566
 567         evt->rating = 110;
 568         evt->features = CLOCK_EVT_FEAT_ONESHOT;
 569         if (hdev->flags & HPET_DEV_PERI_CAP)
 570                 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
 571
 572         evt->set_mode = hpet_msi_set_mode;
 573         evt->set_next_event = hpet_msi_next_event;
 574         evt->shift = 32;
 575
 576         /*
 577          * The period is a femto seconds value. We need to calculate the
 578          * scaled math multiplication factor for nanosecond to hpet tick
 579          * conversion.
 580          */
 581         hpet_freq = 1000000000000000ULL;
 582         do_div(hpet_freq, hpet_period);
 583         evt->mult = div_sc((unsigned long) hpet_freq,
 584                                       NSEC_PER_SEC, evt->shift);
 585         /* Calculate the max delta */
 586         evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
 587         /* 5 usec minimum reprogramming delta. */
 588         evt->min_delta_ns = 5000;
 589
 590         evt->cpumask = cpumask_of(hdev->cpu);
 591         clockevents_register_device(evt);
 592 }
 593
 594 #ifdef CONFIG_HPET
 595 /* Reserve at least one timer for userspace (/dev/hpet) */
 596 #define RESERVE_TIMERS 1
 597 #else
 598 #define RESERVE_TIMERS 0
 599 #endif
 600
 601 static void hpet_msi_capability_lookup(unsigned int start_timer)
 602 {
 603         unsigned int id;
 604         unsigned int num_timers;
 605         unsigned int num_timers_used = 0;
 606         int i;
 607
 608         if (hpet_msi_disable)
 609                 return;
 610
 611         if (boot_cpu_has(X86_FEATURE_ARAT))
 612                 return;
 613         id = hpet_readl(HPET_ID);
 614
 615         num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 616         num_timers++; /* Value read out starts from 0 */
 617         hpet_print_config();
 618
 619         hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
 620         if (!hpet_devs)
 621                 return;
 622
 623         hpet_num_timers = num_timers;
 624
 625         for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
 626                 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
 627                 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
 628
 629                 /* Only consider HPET timer with MSI support */
 630                 if (!(cfg & HPET_TN_FSB_CAP))
 631                         continue;
 632
 633                 hdev->flags = 0;
 634                 if (cfg & HPET_TN_PERIODIC_CAP)
 635                         hdev->flags |= HPET_DEV_PERI_CAP;
 636                 hdev->num = i;
 637
 638                 sprintf(hdev->name, "hpet%d", i);
 639                 if (hpet_assign_irq(hdev))
 640                         continue;
 641
 642                 hdev->flags |= HPET_DEV_FSB_CAP;
 643                 hdev->flags |= HPET_DEV_VALID;
 644                 num_timers_used++;
 645                 if (num_timers_used == num_possible_cpus())
 646                         break;
 647         }
 648
 649         printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
 650                 num_timers, num_timers_used);
 651 }
 652
 653 #ifdef CONFIG_HPET
 654 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 655 {
 656         int i;
 657
 658         if (!hpet_devs)
 659                 return;
 660
 661         for (i = 0; i < hpet_num_timers; i++) {
 662                 struct hpet_dev *hdev = &hpet_devs[i];
 663
 664                 if (!(hdev->flags & HPET_DEV_VALID))
 665                         continue;
 666
 667                 hd->hd_irq[hdev->num] = hdev->irq;
 668                 hpet_reserve_timer(hd, hdev->num);
 669         }
 670 }
 671 #endif
 672
 673 static struct hpet_dev *hpet_get_unused_timer(void)
 674 {
 675         int i;
 676
 677         if (!hpet_devs)
 678                 return NULL;
 679
 680         for (i = 0; i < hpet_num_timers; i++) {
 681                 struct hpet_dev *hdev = &hpet_devs[i];
 682
 683                 if (!(hdev->flags & HPET_DEV_VALID))
 684                         continue;
 685                 if (test_and_set_bit(HPET_DEV_USED_BIT,
 686                         (unsigned long *)&hdev->flags))
 687                         continue;
 688                 return hdev;
 689         }
 690         return NULL;
 691 }
 692
 693 struct hpet_work_struct {
 694         struct delayed_work work;
 695         struct completion complete;
 696 };
 697
 698 static void hpet_work(struct work_struct *w)
 699 {
 700         struct hpet_dev *hdev;
 701         int cpu = smp_processor_id();
 702         struct hpet_work_struct *hpet_work;
 703
 704         hpet_work = container_of(w, struct hpet_work_struct, work.work);
 705
 706         hdev = hpet_get_unused_timer();
 707         if (hdev)
 708                 init_one_hpet_msi_clockevent(hdev, cpu);
 709
 710         complete(&hpet_work->complete);
 711 }
 712
 713 static int hpet_cpuhp_notify(struct notifier_block *n,
 714                 unsigned long action, void *hcpu)
 715 {
 716         unsigned long cpu = (unsigned long)hcpu;
 717         struct hpet_work_struct work;
 718         struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
 719
 720         switch (action & 0xf) {
 721         case CPU_ONLINE:
 722                 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work);
 723                 init_completion(&work.complete);
 724                 /* FIXME: add schedule_work_on() */
 725                 schedule_delayed_work_on(cpu, &work.work, 0);
 726                 wait_for_completion(&work.complete);
 727                 destroy_timer_on_stack(&work.work.timer);
 728                 break;
 729         case CPU_DEAD:
 730                 if (hdev) {
 731                         free_irq(hdev->irq, hdev);
 732                         hdev->flags &= ~HPET_DEV_USED;
 733                         per_cpu(cpu_hpet_dev, cpu) = NULL;
 734                 }
 735                 break;
 736         }
 737         return NOTIFY_OK;
 738 }
 739 #else
 740
 741 static int hpet_setup_msi_irq(unsigned int irq)
 742 {
 743         return 0;
 744 }
 745 static void hpet_msi_capability_lookup(unsigned int start_timer)
 746 {
 747         return;
 748 }
 749
 750 #ifdef CONFIG_HPET
 751 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 752 {
 753         return;
 754 }
 755 #endif
 756
 757 static int hpet_cpuhp_notify(struct notifier_block *n,
 758                 unsigned long action, void *hcpu)
 759 {
 760         return NOTIFY_OK;
 761 }
 762
 763 #endif
 764
 765 /*
 766  * Clock source related code
 767  */
 768 static cycle_t read_hpet(struct clocksource *cs)
 769 {
 770         return (cycle_t)hpet_readl(HPET_COUNTER);
 771 }
 772
 773 #ifdef CONFIG_X86_64
 774 static cycle_t __vsyscall_fn vread_hpet(void)
 775 {
 776         return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
 777 }
 778 #endif
 779
 780 static struct clocksource clocksource_hpet = {
 781         .name           = "hpet",
 782         .rating         = 250,
 783         .read           = read_hpet,
 784         .mask           = HPET_MASK,
 785         .shift          = HPET_SHIFT,
 786         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 787         .resume         = hpet_resume_counter,
 788 #ifdef CONFIG_X86_64
 789         .vread          = vread_hpet,
 790 #endif
 791 };
 792
 793 static int hpet_clocksource_register(void)
 794 {
 795         u64 start, now;
 796         cycle_t t1;
 797
 798         /* Start the counter */
 799         hpet_restart_counter();
 800
 801         /* Verify whether hpet counter works */
 802         t1 = hpet_readl(HPET_COUNTER);
 803         rdtscll(start);
 804
 805         /*
 806          * We don't know the TSC frequency yet, but waiting for
 807          * 200000 TSC cycles is safe:
 808          * 4 GHz == 50us
 809          * 1 GHz == 200us
 810          */
 811         do {
 812                 rep_nop();
 813                 rdtscll(now);
 814         } while ((now - start) < 200000UL);
 815
 816         if (t1 == hpet_readl(HPET_COUNTER)) {
 817                 printk(KERN_WARNING
 818                        "HPET counter not counting. HPET disabled\n");
 819                 return -ENODEV;
 820         }
 821
 822         /*
 823          * The definition of mult is (include/linux/clocksource.h)
 824          * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
 825          * so we first need to convert hpet_period to ns/cyc units:
 826          *  mult/2^shift = ns/cyc = hpet_period/10^6
 827          *  mult = (hpet_period * 2^shift)/10^6
 828          *  mult = (hpet_period << shift)/FSEC_PER_NSEC
 829          */
 830         clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
 831
 832         clocksource_register(&clocksource_hpet);
 833
 834         return 0;
 835 }
 836
 837 /**
 838  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
 839  */
 840 int __init hpet_enable(void)
 841 {
 842         unsigned int id;
 843         int i;
 844
 845         if (!is_hpet_capable())
 846                 return 0;
 847
 848         hpet_set_mapping();
 849
 850         /*
 851          * Read the period and check for a sane value:
 852          */
 853         hpet_period = hpet_readl(HPET_PERIOD);
 854
 855         /*
 856          * AMD SB700 based systems with spread spectrum enabled use a
 857          * SMM based HPET emulation to provide proper frequency
 858          * setting. The SMM code is initialized with the first HPET
 859          * register access and takes some time to complete. During
 860          * this time the config register reads 0xffffffff. We check
 861          * for max. 1000 loops whether the config register reads a non
 862          * 0xffffffff value to make sure that HPET is up and running
 863          * before we go further. A counting loop is safe, as the HPET
 864          * access takes thousands of CPU cycles. On non SB700 based
 865          * machines this check is only done once and has no side
 866          * effects.
 867          */
 868         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
 869                 if (i == 1000) {
 870                         printk(KERN_WARNING
 871                                "HPET config register value = 0xFFFFFFFF. "
 872                                "Disabling HPET\n");
 873                         goto out_nohpet;
 874                 }
 875         }
 876
 877         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 878                 goto out_nohpet;
 879
 880         /*
 881          * Read the HPET ID register to retrieve the IRQ routing
 882          * information and the number of channels
 883          */
 884         id = hpet_readl(HPET_ID);
 885         hpet_print_config();
 886
 887 #ifdef CONFIG_HPET_EMULATE_RTC
 888         /*
 889          * The legacy routing mode needs at least two channels, tick timer
 890          * and the rtc emulation channel.
 891          */
 892         if (!(id & HPET_ID_NUMBER))
 893                 goto out_nohpet;
 894 #endif
 895
 896         if (hpet_clocksource_register())
 897                 goto out_nohpet;
 898
 899         if (id & HPET_ID_LEGSUP) {
 900                 hpet_legacy_clockevent_register();
 901                 return 1;
 902         }
 903         return 0;
 904
 905 out_nohpet:
 906         hpet_clear_mapping();
 907         hpet_address = 0;
 908         return 0;
 909 }
 910
 911 /*
 912  * Needs to be late, as the reserve_timer code calls kalloc !
 913  *
 914  * Not a problem on i386 as hpet_enable is called from late_time_init,
 915  * but on x86_64 it is necessary !
 916  */
 917 static __init int hpet_late_init(void)
 918 {
 919         int cpu;
 920
 921         if (boot_hpet_disable)
 922                 return -ENODEV;
 923
 924         if (!hpet_address) {
 925                 if (!force_hpet_address)
 926                         return -ENODEV;
 927
 928                 hpet_address = force_hpet_address;
 929                 hpet_enable();
 930         }
 931
 932         if (!hpet_virt_address)
 933                 return -ENODEV;
 934
 935         if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
 936                 hpet_msi_capability_lookup(2);
 937         else
 938                 hpet_msi_capability_lookup(0);
 939
 940         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
 941         hpet_print_config();
 942
 943         if (hpet_msi_disable)
 944                 return 0;
 945
 946         if (boot_cpu_has(X86_FEATURE_ARAT))
 947                 return 0;
 948
 949         for_each_online_cpu(cpu) {
 950                 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
 951         }
 952
 953         /* This notifier should be called after workqueue is ready */
 954         hotcpu_notifier(hpet_cpuhp_notify, -20);
 955
 956         return 0;
 957 }
 958 fs_initcall(hpet_late_init);
 959
 960 void hpet_disable(void)
 961 {
 962         if (is_hpet_capable()) {
 963                 unsigned int cfg = hpet_readl(HPET_CFG);
 964
 965                 if (hpet_legacy_int_enabled) {
 966                         cfg &= ~HPET_CFG_LEGACY;
 967                         hpet_legacy_int_enabled = 0;
 968                 }
 969                 cfg &= ~HPET_CFG_ENABLE;
 970                 hpet_writel(cfg, HPET_CFG);
 971         }
 972 }
 973
 974 #ifdef CONFIG_HPET_EMULATE_RTC
 975
 976 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 977  * is enabled, we support RTC interrupt functionality in software.
 978  * RTC has 3 kinds of interrupts:
 979  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 980  *    is updated
 981  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 982  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 983  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 984  * (1) and (2) above are implemented using polling at a frequency of
 985  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 986  * overhead. (DEFAULT_RTC_INT_FREQ)
 987  * For (3), we use interrupts at 64Hz or user specified periodic
 988  * frequency, whichever is higher.
 989  */
 990 #include <linux/mc146818rtc.h>
 991 #include <linux/rtc.h>
 992 #include <asm/rtc.h>
 993
 994 #define DEFAULT_RTC_INT_FREQ    64
 995 #define DEFAULT_RTC_SHIFT       6
 996 #define RTC_NUM_INTS            1
 997
 998 static unsigned long hpet_rtc_flags;
 999 static int hpet_prev_update_sec;
1000 static struct rtc_time hpet_alarm_time;
1001 static unsigned long hpet_pie_count;
1002 static u32 hpet_t1_cmp;
1003 static u32 hpet_default_delta;
1004 static u32 hpet_pie_delta;
1005 static unsigned long hpet_pie_limit;
1006
1007 static rtc_irq_handler irq_handler;
1008
1009 /*
1010  * Check that the hpet counter c1 is ahead of the c2
1011  */
1012 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1013 {
1014         return (s32)(c2 - c1) < 0;
1015 }
1016
1017 /*
1018  * Registers a IRQ handler.
1019  */
1020 int hpet_register_irq_handler(rtc_irq_handler handler)
1021 {
1022         if (!is_hpet_enabled())
1023                 return -ENODEV;
1024         if (irq_handler)
1025                 return -EBUSY;
1026
1027         irq_handler = handler;
1028
1029         return 0;
1030 }
1031 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1032
1033 /*
1034  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1035  * and does cleanup.
1036  */
1037 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1038 {
1039         if (!is_hpet_enabled())
1040                 return;
1041
1042         irq_handler = NULL;
1043         hpet_rtc_flags = 0;
1044 }
1045 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1046
1047 /*
1048  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1049  * is not supported by all HPET implementations for timer 1.
1050  *
1051  * hpet_rtc_timer_init() is called when the rtc is initialized.
1052  */
1053 int hpet_rtc_timer_init(void)
1054 {
1055         unsigned int cfg, cnt, delta;
1056         unsigned long flags;
1057
1058         if (!is_hpet_enabled())
1059                 return 0;
1060
1061         if (!hpet_default_delta) {
1062                 uint64_t clc;
1063
1064                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1065                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1066                 hpet_default_delta = clc;
1067         }
1068
1069         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1070                 delta = hpet_default_delta;
1071         else
1072                 delta = hpet_pie_delta;
1073
1074         local_irq_save(flags);
1075
1076         cnt = delta + hpet_readl(HPET_COUNTER);
1077         hpet_writel(cnt, HPET_T1_CMP);
1078         hpet_t1_cmp = cnt;
1079
1080         cfg = hpet_readl(HPET_T1_CFG);
1081         cfg &= ~HPET_TN_PERIODIC;
1082         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1083         hpet_writel(cfg, HPET_T1_CFG);
1084
1085         local_irq_restore(flags);
1086
1087         return 1;
1088 }
1089 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1090
1091 /*
1092  * The functions below are called from rtc driver.
1093  * Return 0 if HPET is not being used.
1094  * Otherwise do the necessary changes and return 1.
1095  */
1096 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1097 {
1098         if (!is_hpet_enabled())
1099                 return 0;
1100
1101         hpet_rtc_flags &= ~bit_mask;
1102         return 1;
1103 }
1104 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1105
1106 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1107 {
1108         unsigned long oldbits = hpet_rtc_flags;
1109
1110         if (!is_hpet_enabled())
1111                 return 0;
1112
1113         hpet_rtc_flags |= bit_mask;
1114
1115         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1116                 hpet_prev_update_sec = -1;
1117
1118         if (!oldbits)
1119                 hpet_rtc_timer_init();
1120
1121         return 1;
1122 }
1123 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1124
1125 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1126                         unsigned char sec)
1127 {
1128         if (!is_hpet_enabled())
1129                 return 0;
1130
1131         hpet_alarm_time.tm_hour = hrs;
1132         hpet_alarm_time.tm_min = min;
1133         hpet_alarm_time.tm_sec = sec;
1134
1135         return 1;
1136 }
1137 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1138
1139 int hpet_set_periodic_freq(unsigned long freq)
1140 {
1141         uint64_t clc;
1142
1143         if (!is_hpet_enabled())
1144                 return 0;
1145
1146         if (freq <= DEFAULT_RTC_INT_FREQ)
1147                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1148         else {
1149                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1150                 do_div(clc, freq);
1151                 clc >>= hpet_clockevent.shift;
1152                 hpet_pie_delta = clc;
1153                 hpet_pie_limit = 0;
1154         }
1155         return 1;
1156 }
1157 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1158
1159 int hpet_rtc_dropped_irq(void)
1160 {
1161         return is_hpet_enabled();
1162 }
1163 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1164
1165 static void hpet_rtc_timer_reinit(void)
1166 {
1167         unsigned int cfg, delta;
1168         int lost_ints = -1;
1169
1170         if (unlikely(!hpet_rtc_flags)) {
1171                 cfg = hpet_readl(HPET_T1_CFG);
1172                 cfg &= ~HPET_TN_ENABLE;
1173                 hpet_writel(cfg, HPET_T1_CFG);
1174                 return;
1175         }
1176
1177         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1178                 delta = hpet_default_delta;
1179         else
1180                 delta = hpet_pie_delta;
1181
1182         /*
1183          * Increment the comparator value until we are ahead of the
1184          * current count.
1185          */
1186         do {
1187                 hpet_t1_cmp += delta;
1188                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1189                 lost_ints++;
1190         } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1191
1192         if (lost_ints) {
1193                 if (hpet_rtc_flags & RTC_PIE)
1194                         hpet_pie_count += lost_ints;
1195                 if (printk_ratelimit())
1196                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1197                                 lost_ints);
1198         }
1199 }
1200
1201 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1202 {
1203         struct rtc_time curr_time;
1204         unsigned long rtc_int_flag = 0;
1205
1206         hpet_rtc_timer_reinit();
1207         memset(&curr_time, 0, sizeof(struct rtc_time));
1208
1209         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1210                 get_rtc_time(&curr_time);
1211
1212         if (hpet_rtc_flags & RTC_UIE &&
1213             curr_time.tm_sec != hpet_prev_update_sec) {
1214                 if (hpet_prev_update_sec >= 0)
1215                         rtc_int_flag = RTC_UF;
1216                 hpet_prev_update_sec = curr_time.tm_sec;
1217         }
1218
1219         if (hpet_rtc_flags & RTC_PIE &&
1220             ++hpet_pie_count >= hpet_pie_limit) {
1221                 rtc_int_flag |= RTC_PF;
1222                 hpet_pie_count = 0;
1223         }
1224
1225         if (hpet_rtc_flags & RTC_AIE &&
1226             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1227             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1228             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1229                         rtc_int_flag |= RTC_AF;
1230
1231         if (rtc_int_flag) {
1232                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1233                 if (irq_handler)
1234                         irq_handler(rtc_int_flag, dev_id);
1235         }
1236         return IRQ_HANDLED;
1237 }
1238 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1239 #endif