arch/x86/kernel/cpu/perf_event_intel_uncore.c

   1 #include "perf_event_intel_uncore.h"
   2
   3 static struct intel_uncore_type *empty_uncore[] = { NULL, };
   4 struct intel_uncore_type **uncore_msr_uncores = empty_uncore;
   5 struct intel_uncore_type **uncore_pci_uncores = empty_uncore;
   6
   7 static bool pcidrv_registered;
   8 struct pci_driver *uncore_pci_driver;
   9 /* pci bus to socket mapping */
  10 int uncore_pcibus_to_physid[256] = { [0 ... 255] = -1, };
  11 struct pci_dev *uncore_extra_pci_dev[UNCORE_SOCKET_MAX][UNCORE_EXTRA_PCI_DEV_MAX];
  12
  13 static DEFINE_RAW_SPINLOCK(uncore_box_lock);
  14 /* mask of cpus that collect uncore events */
  15 static cpumask_t uncore_cpu_mask;
  16
  17 /* constraint for the fixed counter */
  18 static struct event_constraint uncore_constraint_fixed =
  19         EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL);
  20 struct event_constraint uncore_constraint_empty =
  21         EVENT_CONSTRAINT(0, 0, 0);
  22
  23 ssize_t uncore_event_show(struct kobject *kobj,
  24                           struct kobj_attribute *attr, char *buf)
  25 {
  26         struct uncore_event_desc *event =
  27                 container_of(attr, struct uncore_event_desc, attr);
  28         return sprintf(buf, "%s", event->config);
  29 }
  30
  31 struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
  32 {
  33         return container_of(event->pmu, struct intel_uncore_pmu, pmu);
  34 }
  35
  36 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
  37 {
  38         struct intel_uncore_box *box;
  39
  40         box = *per_cpu_ptr(pmu->box, cpu);
  41         if (box)
  42                 return box;
  43
  44         raw_spin_lock(&uncore_box_lock);
  45         /* Recheck in lock to handle races. */
  46         if (*per_cpu_ptr(pmu->box, cpu))
  47                 goto out;
  48         list_for_each_entry(box, &pmu->box_list, list) {
  49                 if (box->phys_id == topology_physical_package_id(cpu)) {
  50                         atomic_inc(&box->refcnt);
  51                         *per_cpu_ptr(pmu->box, cpu) = box;
  52                         break;
  53                 }
  54         }
  55 out:
  56         raw_spin_unlock(&uncore_box_lock);
  57
  58         return *per_cpu_ptr(pmu->box, cpu);
  59 }
  60
  61 struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
  62 {
  63         /*
  64          * perf core schedules event on the basis of cpu, uncore events are
  65          * collected by one of the cpus inside a physical package.
  66          */
  67         return uncore_pmu_to_box(uncore_event_to_pmu(event), smp_processor_id());
  68 }
  69
  70 u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
  71 {
  72         u64 count;
  73
  74         rdmsrl(event->hw.event_base, count);
  75
  76         return count;
  77 }
  78
  79 /*
  80  * generic get constraint function for shared match/mask registers.
  81  */
  82 struct event_constraint *
  83 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
  84 {
  85         struct intel_uncore_extra_reg *er;
  86         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
  87         struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
  88         unsigned long flags;
  89         bool ok = false;
  90
  91         /*
  92          * reg->alloc can be set due to existing state, so for fake box we
  93          * need to ignore this, otherwise we might fail to allocate proper
  94          * fake state for this extra reg constraint.
  95          */
  96         if (reg1->idx == EXTRA_REG_NONE ||
  97             (!uncore_box_is_fake(box) && reg1->alloc))
  98                 return NULL;
  99
 100         er = &box->shared_regs[reg1->idx];
 101         raw_spin_lock_irqsave(&er->lock, flags);
 102         if (!atomic_read(&er->ref) ||
 103             (er->config1 == reg1->config && er->config2 == reg2->config)) {
 104                 atomic_inc(&er->ref);
 105                 er->config1 = reg1->config;
 106                 er->config2 = reg2->config;
 107                 ok = true;
 108         }
 109         raw_spin_unlock_irqrestore(&er->lock, flags);
 110
 111         if (ok) {
 112                 if (!uncore_box_is_fake(box))
 113                         reg1->alloc = 1;
 114                 return NULL;
 115         }
 116
 117         return &uncore_constraint_empty;
 118 }
 119
 120 void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
 121 {
 122         struct intel_uncore_extra_reg *er;
 123         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
 124
 125         /*
 126          * Only put constraint if extra reg was actually allocated. Also
 127          * takes care of event which do not use an extra shared reg.
 128          *
 129          * Also, if this is a fake box we shouldn't touch any event state
 130          * (reg->alloc) and we don't care about leaving inconsistent box
 131          * state either since it will be thrown out.
 132          */
 133         if (uncore_box_is_fake(box) || !reg1->alloc)
 134                 return;
 135
 136         er = &box->shared_regs[reg1->idx];
 137         atomic_dec(&er->ref);
 138         reg1->alloc = 0;
 139 }
 140
 141 u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx)
 142 {
 143         struct intel_uncore_extra_reg *er;
 144         unsigned long flags;
 145         u64 config;
 146
 147         er = &box->shared_regs[idx];
 148
 149         raw_spin_lock_irqsave(&er->lock, flags);
 150         config = er->config;
 151         raw_spin_unlock_irqrestore(&er->lock, flags);
 152
 153         return config;
 154 }
 155
 156 static void uncore_assign_hw_event(struct intel_uncore_box *box, struct perf_event *event, int idx)
 157 {
 158         struct hw_perf_event *hwc = &event->hw;
 159
 160         hwc->idx = idx;
 161         hwc->last_tag = ++box->tags[idx];
 162
 163         if (hwc->idx == UNCORE_PMC_IDX_FIXED) {
 164                 hwc->event_base = uncore_fixed_ctr(box);
 165                 hwc->config_base = uncore_fixed_ctl(box);
 166                 return;
 167         }
 168
 169         hwc->config_base = uncore_event_ctl(box, hwc->idx);
 170         hwc->event_base  = uncore_perf_ctr(box, hwc->idx);
 171 }
 172
 173 void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event)
 174 {
 175         u64 prev_count, new_count, delta;
 176         int shift;
 177
 178         if (event->hw.idx >= UNCORE_PMC_IDX_FIXED)
 179                 shift = 64 - uncore_fixed_ctr_bits(box);
 180         else
 181                 shift = 64 - uncore_perf_ctr_bits(box);
 182
 183         /* the hrtimer might modify the previous event value */
 184 again:
 185         prev_count = local64_read(&event->hw.prev_count);
 186         new_count = uncore_read_counter(box, event);
 187         if (local64_xchg(&event->hw.prev_count, new_count) != prev_count)
 188                 goto again;
 189
 190         delta = (new_count << shift) - (prev_count << shift);
 191         delta >>= shift;
 192
 193         local64_add(delta, &event->count);
 194 }
 195
 196 /*
 197  * The overflow interrupt is unavailable for SandyBridge-EP, is broken
 198  * for SandyBridge. So we use hrtimer to periodically poll the counter
 199  * to avoid overflow.
 200  */
 201 static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer)
 202 {
 203         struct intel_uncore_box *box;
 204         struct perf_event *event;
 205         unsigned long flags;
 206         int bit;
 207
 208         box = container_of(hrtimer, struct intel_uncore_box, hrtimer);
 209         if (!box->n_active || box->cpu != smp_processor_id())
 210                 return HRTIMER_NORESTART;
 211         /*
 212          * disable local interrupt to prevent uncore_pmu_event_start/stop
 213          * to interrupt the update process
 214          */
 215         local_irq_save(flags);
 216
 217         /*
 218          * handle boxes with an active event list as opposed to active
 219          * counters
 220          */
 221         list_for_each_entry(event, &box->active_list, active_entry) {
 222                 uncore_perf_event_update(box, event);
 223         }
 224
 225         for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX)
 226                 uncore_perf_event_update(box, box->events[bit]);
 227
 228         local_irq_restore(flags);
 229
 230         hrtimer_forward_now(hrtimer, ns_to_ktime(box->hrtimer_duration));
 231         return HRTIMER_RESTART;
 232 }
 233
 234 void uncore_pmu_start_hrtimer(struct intel_uncore_box *box)
 235 {
 236         __hrtimer_start_range_ns(&box->hrtimer,
 237                         ns_to_ktime(box->hrtimer_duration), 0,
 238                         HRTIMER_MODE_REL_PINNED, 0);
 239 }
 240
 241 void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box)
 242 {
 243         hrtimer_cancel(&box->hrtimer);
 244 }
 245
 246 static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
 247 {
 248         hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 249         box->hrtimer.function = uncore_pmu_hrtimer;
 250 }
 251
 252 static struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type, int node)
 253 {
 254         struct intel_uncore_box *box;
 255         int i, size;
 256
 257         size = sizeof(*box) + type->num_shared_regs * sizeof(struct intel_uncore_extra_reg);
 258
 259         box = kzalloc_node(size, GFP_KERNEL, node);
 260         if (!box)
 261                 return NULL;
 262
 263         for (i = 0; i < type->num_shared_regs; i++)
 264                 raw_spin_lock_init(&box->shared_regs[i].lock);
 265
 266         uncore_pmu_init_hrtimer(box);
 267         atomic_set(&box->refcnt, 1);
 268         box->cpu = -1;
 269         box->phys_id = -1;
 270
 271         /* set default hrtimer timeout */
 272         box->hrtimer_duration = UNCORE_PMU_HRTIMER_INTERVAL;
 273
 274         INIT_LIST_HEAD(&box->active_list);
 275
 276         return box;
 277 }
 278
 279 /*
 280  * Using uncore_pmu_event_init pmu event_init callback
 281  * as a detection point for uncore events.
 282  */
 283 static int uncore_pmu_event_init(struct perf_event *event);
 284
 285 static bool is_uncore_event(struct perf_event *event)
 286 {
 287         return event->pmu->event_init == uncore_pmu_event_init;
 288 }
 289
 290 static int
 291 uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader, bool dogrp)
 292 {
 293         struct perf_event *event;
 294         int n, max_count;
 295
 296         max_count = box->pmu->type->num_counters;
 297         if (box->pmu->type->fixed_ctl)
 298                 max_count++;
 299
 300         if (box->n_events >= max_count)
 301                 return -EINVAL;
 302
 303         n = box->n_events;
 304
 305         if (is_uncore_event(leader)) {
 306                 box->event_list[n] = leader;
 307                 n++;
 308         }
 309
 310         if (!dogrp)
 311                 return n;
 312
 313         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 314                 if (!is_uncore_event(event) ||
 315                     event->state <= PERF_EVENT_STATE_OFF)
 316                         continue;
 317
 318                 if (n >= max_count)
 319                         return -EINVAL;
 320
 321                 box->event_list[n] = event;
 322                 n++;
 323         }
 324         return n;
 325 }
 326
 327 static struct event_constraint *
 328 uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
 329 {
 330         struct intel_uncore_type *type = box->pmu->type;
 331         struct event_constraint *c;
 332
 333         if (type->ops->get_constraint) {
 334                 c = type->ops->get_constraint(box, event);
 335                 if (c)
 336                         return c;
 337         }
 338
 339         if (event->attr.config == UNCORE_FIXED_EVENT)
 340                 return &uncore_constraint_fixed;
 341
 342         if (type->constraints) {
 343                 for_each_event_constraint(c, type->constraints) {
 344                         if ((event->hw.config & c->cmask) == c->code)
 345                                 return c;
 346                 }
 347         }
 348
 349         return &type->unconstrainted;
 350 }
 351
 352 static void uncore_put_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
 353 {
 354         if (box->pmu->type->ops->put_constraint)
 355                 box->pmu->type->ops->put_constraint(box, event);
 356 }
 357
 358 static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n)
 359 {
 360         unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
 361         struct event_constraint *c;
 362         int i, wmin, wmax, ret = 0;
 363         struct hw_perf_event *hwc;
 364
 365         bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);
 366
 367         for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 368                 c = uncore_get_event_constraint(box, box->event_list[i]);
 369                 box->event_constraint[i] = c;
 370                 wmin = min(wmin, c->weight);
 371                 wmax = max(wmax, c->weight);
 372         }
 373
 374         /* fastpath, try to reuse previous register */
 375         for (i = 0; i < n; i++) {
 376                 hwc = &box->event_list[i]->hw;
 377                 c = box->event_constraint[i];
 378
 379                 /* never assigned */
 380                 if (hwc->idx == -1)
 381                         break;
 382
 383                 /* constraint still honored */
 384                 if (!test_bit(hwc->idx, c->idxmsk))
 385                         break;
 386
 387                 /* not already used */
 388                 if (test_bit(hwc->idx, used_mask))
 389                         break;
 390
 391                 __set_bit(hwc->idx, used_mask);
 392                 if (assign)
 393                         assign[i] = hwc->idx;
 394         }
 395         /* slow path */
 396         if (i != n)
 397                 ret = perf_assign_events(box->event_constraint, n,
 398                                          wmin, wmax, n, assign);
 399
 400         if (!assign || ret) {
 401                 for (i = 0; i < n; i++)
 402                         uncore_put_event_constraint(box, box->event_list[i]);
 403         }
 404         return ret ? -EINVAL : 0;
 405 }
 406
 407 static void uncore_pmu_event_start(struct perf_event *event, int flags)
 408 {
 409         struct intel_uncore_box *box = uncore_event_to_box(event);
 410         int idx = event->hw.idx;
 411
 412         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
 413                 return;
 414
 415         if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
 416                 return;
 417
 418         event->hw.state = 0;
 419         box->events[idx] = event;
 420         box->n_active++;
 421         __set_bit(idx, box->active_mask);
 422
 423         local64_set(&event->hw.prev_count, uncore_read_counter(box, event));
 424         uncore_enable_event(box, event);
 425
 426         if (box->n_active == 1) {
 427                 uncore_enable_box(box);
 428                 uncore_pmu_start_hrtimer(box);
 429         }
 430 }
 431
 432 static void uncore_pmu_event_stop(struct perf_event *event, int flags)
 433 {
 434         struct intel_uncore_box *box = uncore_event_to_box(event);
 435         struct hw_perf_event *hwc = &event->hw;
 436
 437         if (__test_and_clear_bit(hwc->idx, box->active_mask)) {
 438                 uncore_disable_event(box, event);
 439                 box->n_active--;
 440                 box->events[hwc->idx] = NULL;
 441                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
 442                 hwc->state |= PERF_HES_STOPPED;
 443
 444                 if (box->n_active == 0) {
 445                         uncore_disable_box(box);
 446                         uncore_pmu_cancel_hrtimer(box);
 447                 }
 448         }
 449
 450         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
 451                 /*
 452                  * Drain the remaining delta count out of a event
 453                  * that we are disabling:
 454                  */
 455                 uncore_perf_event_update(box, event);
 456                 hwc->state |= PERF_HES_UPTODATE;
 457         }
 458 }
 459
 460 static int uncore_pmu_event_add(struct perf_event *event, int flags)
 461 {
 462         struct intel_uncore_box *box = uncore_event_to_box(event);
 463         struct hw_perf_event *hwc = &event->hw;
 464         int assign[UNCORE_PMC_IDX_MAX];
 465         int i, n, ret;
 466
 467         if (!box)
 468                 return -ENODEV;
 469
 470         ret = n = uncore_collect_events(box, event, false);
 471         if (ret < 0)
 472                 return ret;
 473
 474         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 475         if (!(flags & PERF_EF_START))
 476                 hwc->state |= PERF_HES_ARCH;
 477
 478         ret = uncore_assign_events(box, assign, n);
 479         if (ret)
 480                 return ret;
 481
 482         /* save events moving to new counters */
 483         for (i = 0; i < box->n_events; i++) {
 484                 event = box->event_list[i];
 485                 hwc = &event->hw;
 486
 487                 if (hwc->idx == assign[i] &&
 488                         hwc->last_tag == box->tags[assign[i]])
 489                         continue;
 490                 /*
 491                  * Ensure we don't accidentally enable a stopped
 492                  * counter simply because we rescheduled.
 493                  */
 494                 if (hwc->state & PERF_HES_STOPPED)
 495                         hwc->state |= PERF_HES_ARCH;
 496
 497                 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
 498         }
 499
 500         /* reprogram moved events into new counters */
 501         for (i = 0; i < n; i++) {
 502                 event = box->event_list[i];
 503                 hwc = &event->hw;
 504
 505                 if (hwc->idx != assign[i] ||
 506                         hwc->last_tag != box->tags[assign[i]])
 507                         uncore_assign_hw_event(box, event, assign[i]);
 508                 else if (i < box->n_events)
 509                         continue;
 510
 511                 if (hwc->state & PERF_HES_ARCH)
 512                         continue;
 513
 514                 uncore_pmu_event_start(event, 0);
 515         }
 516         box->n_events = n;
 517
 518         return 0;
 519 }
 520
 521 static void uncore_pmu_event_del(struct perf_event *event, int flags)
 522 {
 523         struct intel_uncore_box *box = uncore_event_to_box(event);
 524         int i;
 525
 526         uncore_pmu_event_stop(event, PERF_EF_UPDATE);
 527
 528         for (i = 0; i < box->n_events; i++) {
 529                 if (event == box->event_list[i]) {
 530                         uncore_put_event_constraint(box, event);
 531
 532                         while (++i < box->n_events)
 533                                 box->event_list[i - 1] = box->event_list[i];
 534
 535                         --box->n_events;
 536                         break;
 537                 }
 538         }
 539
 540         event->hw.idx = -1;
 541         event->hw.last_tag = ~0ULL;
 542 }
 543
 544 void uncore_pmu_event_read(struct perf_event *event)
 545 {
 546         struct intel_uncore_box *box = uncore_event_to_box(event);
 547         uncore_perf_event_update(box, event);
 548 }
 549
 550 /*
 551  * validation ensures the group can be loaded onto the
 552  * PMU if it was the only group available.
 553  */
 554 static int uncore_validate_group(struct intel_uncore_pmu *pmu,
 555                                 struct perf_event *event)
 556 {
 557         struct perf_event *leader = event->group_leader;
 558         struct intel_uncore_box *fake_box;
 559         int ret = -EINVAL, n;
 560
 561         fake_box = uncore_alloc_box(pmu->type, NUMA_NO_NODE);
 562         if (!fake_box)
 563                 return -ENOMEM;
 564
 565         fake_box->pmu = pmu;
 566         /*
 567          * the event is not yet connected with its
 568          * siblings therefore we must first collect
 569          * existing siblings, then add the new event
 570          * before we can simulate the scheduling
 571          */
 572         n = uncore_collect_events(fake_box, leader, true);
 573         if (n < 0)
 574                 goto out;
 575
 576         fake_box->n_events = n;
 577         n = uncore_collect_events(fake_box, event, false);
 578         if (n < 0)
 579                 goto out;
 580
 581         fake_box->n_events = n;
 582
 583         ret = uncore_assign_events(fake_box, NULL, n);
 584 out:
 585         kfree(fake_box);
 586         return ret;
 587 }
 588
 589 static int uncore_pmu_event_init(struct perf_event *event)
 590 {
 591         struct intel_uncore_pmu *pmu;
 592         struct intel_uncore_box *box;
 593         struct hw_perf_event *hwc = &event->hw;
 594         int ret;
 595
 596         if (event->attr.type != event->pmu->type)
 597                 return -ENOENT;
 598
 599         pmu = uncore_event_to_pmu(event);
 600         /* no device found for this pmu */
 601         if (pmu->func_id < 0)
 602                 return -ENOENT;
 603
 604         /*
 605          * Uncore PMU does measure at all privilege level all the time.
 606          * So it doesn't make sense to specify any exclude bits.
 607          */
 608         if (event->attr.exclude_user || event->attr.exclude_kernel ||
 609                         event->attr.exclude_hv || event->attr.exclude_idle)
 610                 return -EINVAL;
 611
 612         /* Sampling not supported yet */
 613         if (hwc->sample_period)
 614                 return -EINVAL;
 615
 616         /*
 617          * Place all uncore events for a particular physical package
 618          * onto a single cpu
 619          */
 620         if (event->cpu < 0)
 621                 return -EINVAL;
 622         box = uncore_pmu_to_box(pmu, event->cpu);
 623         if (!box || box->cpu < 0)
 624                 return -EINVAL;
 625         event->cpu = box->cpu;
 626
 627         event->hw.idx = -1;
 628         event->hw.last_tag = ~0ULL;
 629         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 630         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 631
 632         if (event->attr.config == UNCORE_FIXED_EVENT) {
 633                 /* no fixed counter */
 634                 if (!pmu->type->fixed_ctl)
 635                         return -EINVAL;
 636                 /*
 637                  * if there is only one fixed counter, only the first pmu
 638                  * can access the fixed counter
 639                  */
 640                 if (pmu->type->single_fixed && pmu->pmu_idx > 0)
 641                         return -EINVAL;
 642
 643                 /* fixed counters have event field hardcoded to zero */
 644                 hwc->config = 0ULL;
 645         } else {
 646                 hwc->config = event->attr.config & pmu->type->event_mask;
 647                 if (pmu->type->ops->hw_config) {
 648                         ret = pmu->type->ops->hw_config(box, event);
 649                         if (ret)
 650                                 return ret;
 651                 }
 652         }
 653
 654         if (event->group_leader != event)
 655                 ret = uncore_validate_group(pmu, event);
 656         else
 657                 ret = 0;
 658
 659         return ret;
 660 }
 661
 662 static ssize_t uncore_get_attr_cpumask(struct device *dev,
 663                                 struct device_attribute *attr, char *buf)
 664 {
 665         return cpumap_print_to_pagebuf(true, buf, &uncore_cpu_mask);
 666 }
 667
 668 static DEVICE_ATTR(cpumask, S_IRUGO, uncore_get_attr_cpumask, NULL);
 669
 670 static struct attribute *uncore_pmu_attrs[] = {
 671         &dev_attr_cpumask.attr,
 672         NULL,
 673 };
 674
 675 static struct attribute_group uncore_pmu_attr_group = {
 676         .attrs = uncore_pmu_attrs,
 677 };
 678
 679 static int uncore_pmu_register(struct intel_uncore_pmu *pmu)
 680 {
 681         int ret;
 682
 683         if (!pmu->type->pmu) {
 684                 pmu->pmu = (struct pmu) {
 685                         .attr_groups    = pmu->type->attr_groups,
 686                         .task_ctx_nr    = perf_invalid_context,
 687                         .event_init     = uncore_pmu_event_init,
 688                         .add            = uncore_pmu_event_add,
 689                         .del            = uncore_pmu_event_del,
 690                         .start          = uncore_pmu_event_start,
 691                         .stop           = uncore_pmu_event_stop,
 692                         .read           = uncore_pmu_event_read,
 693                 };
 694         } else {
 695                 pmu->pmu = *pmu->type->pmu;
 696                 pmu->pmu.attr_groups = pmu->type->attr_groups;
 697         }
 698
 699         if (pmu->type->num_boxes == 1) {
 700                 if (strlen(pmu->type->name) > 0)
 701                         sprintf(pmu->name, "uncore_%s", pmu->type->name);
 702                 else
 703                         sprintf(pmu->name, "uncore");
 704         } else {
 705                 sprintf(pmu->name, "uncore_%s_%d", pmu->type->name,
 706                         pmu->pmu_idx);
 707         }
 708
 709         ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
 710         return ret;
 711 }
 712
 713 static void __init uncore_type_exit(struct intel_uncore_type *type)
 714 {
 715         int i;
 716
 717         for (i = 0; i < type->num_boxes; i++)
 718                 free_percpu(type->pmus[i].box);
 719         kfree(type->pmus);
 720         type->pmus = NULL;
 721         kfree(type->events_group);
 722         type->events_group = NULL;
 723 }
 724
 725 static void __init uncore_types_exit(struct intel_uncore_type **types)
 726 {
 727         int i;
 728         for (i = 0; types[i]; i++)
 729                 uncore_type_exit(types[i]);
 730 }
 731
 732 static int __init uncore_type_init(struct intel_uncore_type *type)
 733 {
 734         struct intel_uncore_pmu *pmus;
 735         struct attribute_group *attr_group;
 736         struct attribute **attrs;
 737         int i, j;
 738
 739         pmus = kzalloc(sizeof(*pmus) * type->num_boxes, GFP_KERNEL);
 740         if (!pmus)
 741                 return -ENOMEM;
 742
 743         type->pmus = pmus;
 744
 745         type->unconstrainted = (struct event_constraint)
 746                 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
 747                                 0, type->num_counters, 0, 0);
 748
 749         for (i = 0; i < type->num_boxes; i++) {
 750                 pmus[i].func_id = -1;
 751                 pmus[i].pmu_idx = i;
 752                 pmus[i].type = type;
 753                 INIT_LIST_HEAD(&pmus[i].box_list);
 754                 pmus[i].box = alloc_percpu(struct intel_uncore_box *);
 755                 if (!pmus[i].box)
 756                         goto fail;
 757         }
 758
 759         if (type->event_descs) {
 760                 i = 0;
 761                 while (type->event_descs[i].attr.attr.name)
 762                         i++;
 763
 764                 attr_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
 765                                         sizeof(*attr_group), GFP_KERNEL);
 766                 if (!attr_group)
 767                         goto fail;
 768
 769                 attrs = (struct attribute **)(attr_group + 1);
 770                 attr_group->name = "events";
 771                 attr_group->attrs = attrs;
 772
 773                 for (j = 0; j < i; j++)
 774                         attrs[j] = &type->event_descs[j].attr.attr;
 775
 776                 type->events_group = attr_group;
 777         }
 778
 779         type->pmu_group = &uncore_pmu_attr_group;
 780         return 0;
 781 fail:
 782         uncore_type_exit(type);
 783         return -ENOMEM;
 784 }
 785
 786 static int __init uncore_types_init(struct intel_uncore_type **types)
 787 {
 788         int i, ret;
 789
 790         for (i = 0; types[i]; i++) {
 791                 ret = uncore_type_init(types[i]);
 792                 if (ret)
 793                         goto fail;
 794         }
 795         return 0;
 796 fail:
 797         while (--i >= 0)
 798                 uncore_type_exit(types[i]);
 799         return ret;
 800 }
 801
 802 /*
 803  * add a pci uncore device
 804  */
 805 static int uncore_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 806 {
 807         struct intel_uncore_pmu *pmu;
 808         struct intel_uncore_box *box;
 809         struct intel_uncore_type *type;
 810         int phys_id;
 811         bool first_box = false;
 812
 813         phys_id = uncore_pcibus_to_physid[pdev->bus->number];
 814         if (phys_id < 0)
 815                 return -ENODEV;
 816
 817         if (UNCORE_PCI_DEV_TYPE(id->driver_data) == UNCORE_EXTRA_PCI_DEV) {
 818                 int idx = UNCORE_PCI_DEV_IDX(id->driver_data);
 819                 uncore_extra_pci_dev[phys_id][idx] = pdev;
 820                 pci_set_drvdata(pdev, NULL);
 821                 return 0;
 822         }
 823
 824         type = uncore_pci_uncores[UNCORE_PCI_DEV_TYPE(id->driver_data)];
 825         box = uncore_alloc_box(type, NUMA_NO_NODE);
 826         if (!box)
 827                 return -ENOMEM;
 828
 829         /*
 830          * for performance monitoring unit with multiple boxes,
 831          * each box has a different function id.
 832          */
 833         pmu = &type->pmus[UNCORE_PCI_DEV_IDX(id->driver_data)];
 834         if (pmu->func_id < 0)
 835                 pmu->func_id = pdev->devfn;
 836         else
 837                 WARN_ON_ONCE(pmu->func_id != pdev->devfn);
 838
 839         box->phys_id = phys_id;
 840         box->pci_dev = pdev;
 841         box->pmu = pmu;
 842         pci_set_drvdata(pdev, box);
 843
 844         raw_spin_lock(&uncore_box_lock);
 845         if (list_empty(&pmu->box_list))
 846                 first_box = true;
 847         list_add_tail(&box->list, &pmu->box_list);
 848         raw_spin_unlock(&uncore_box_lock);
 849
 850         if (first_box)
 851                 uncore_pmu_register(pmu);
 852         return 0;
 853 }
 854
 855 static void uncore_pci_remove(struct pci_dev *pdev)
 856 {
 857         struct intel_uncore_box *box = pci_get_drvdata(pdev);
 858         struct intel_uncore_pmu *pmu;
 859         int i, cpu, phys_id = uncore_pcibus_to_physid[pdev->bus->number];
 860         bool last_box = false;
 861
 862         box = pci_get_drvdata(pdev);
 863         if (!box) {
 864                 for (i = 0; i < UNCORE_EXTRA_PCI_DEV_MAX; i++) {
 865                         if (uncore_extra_pci_dev[phys_id][i] == pdev) {
 866                                 uncore_extra_pci_dev[phys_id][i] = NULL;
 867                                 break;
 868                         }
 869                 }
 870                 WARN_ON_ONCE(i >= UNCORE_EXTRA_PCI_DEV_MAX);
 871                 return;
 872         }
 873
 874         pmu = box->pmu;
 875         if (WARN_ON_ONCE(phys_id != box->phys_id))
 876                 return;
 877
 878         pci_set_drvdata(pdev, NULL);
 879
 880         raw_spin_lock(&uncore_box_lock);
 881         list_del(&box->list);
 882         if (list_empty(&pmu->box_list))
 883                 last_box = true;
 884         raw_spin_unlock(&uncore_box_lock);
 885
 886         for_each_possible_cpu(cpu) {
 887                 if (*per_cpu_ptr(pmu->box, cpu) == box) {
 888                         *per_cpu_ptr(pmu->box, cpu) = NULL;
 889                         atomic_dec(&box->refcnt);
 890                 }
 891         }
 892
 893         WARN_ON_ONCE(atomic_read(&box->refcnt) != 1);
 894         kfree(box);
 895
 896         if (last_box)
 897                 perf_pmu_unregister(&pmu->pmu);
 898 }
 899
 900 static int __init uncore_pci_init(void)
 901 {
 902         int ret;
 903
 904         switch (boot_cpu_data.x86_model) {
 905         case 45: /* Sandy Bridge-EP */
 906                 ret = snbep_uncore_pci_init();
 907                 break;
 908         case 62: /* Ivy Bridge-EP */
 909                 ret = ivbep_uncore_pci_init();
 910                 break;
 911         case 63: /* Haswell-EP */
 912                 ret = hswep_uncore_pci_init();
 913                 break;
 914         case 42: /* Sandy Bridge */
 915                 ret = snb_uncore_pci_init();
 916                 break;
 917         case 58: /* Ivy Bridge */
 918                 ret = ivb_uncore_pci_init();
 919                 break;
 920         case 60: /* Haswell */
 921         case 69: /* Haswell Celeron */
 922                 ret = hsw_uncore_pci_init();
 923                 break;
 924         default:
 925                 return 0;
 926         }
 927
 928         if (ret)
 929                 return ret;
 930
 931         ret = uncore_types_init(uncore_pci_uncores);
 932         if (ret)
 933                 return ret;
 934
 935         uncore_pci_driver->probe = uncore_pci_probe;
 936         uncore_pci_driver->remove = uncore_pci_remove;
 937
 938         ret = pci_register_driver(uncore_pci_driver);
 939         if (ret == 0)
 940                 pcidrv_registered = true;
 941         else
 942                 uncore_types_exit(uncore_pci_uncores);
 943
 944         return ret;
 945 }
 946
 947 static void __init uncore_pci_exit(void)
 948 {
 949         if (pcidrv_registered) {
 950                 pcidrv_registered = false;
 951                 pci_unregister_driver(uncore_pci_driver);
 952                 uncore_types_exit(uncore_pci_uncores);
 953         }
 954 }
 955
 956 /* CPU hot plug/unplug are serialized by cpu_add_remove_lock mutex */
 957 static LIST_HEAD(boxes_to_free);
 958
 959 static void uncore_kfree_boxes(void)
 960 {
 961         struct intel_uncore_box *box;
 962
 963         while (!list_empty(&boxes_to_free)) {
 964                 box = list_entry(boxes_to_free.next,
 965                                  struct intel_uncore_box, list);
 966                 list_del(&box->list);
 967                 kfree(box);
 968         }
 969 }
 970
 971 static void uncore_cpu_dying(int cpu)
 972 {
 973         struct intel_uncore_type *type;
 974         struct intel_uncore_pmu *pmu;
 975         struct intel_uncore_box *box;
 976         int i, j;
 977
 978         for (i = 0; uncore_msr_uncores[i]; i++) {
 979                 type = uncore_msr_uncores[i];
 980                 for (j = 0; j < type->num_boxes; j++) {
 981                         pmu = &type->pmus[j];
 982                         box = *per_cpu_ptr(pmu->box, cpu);
 983                         *per_cpu_ptr(pmu->box, cpu) = NULL;
 984                         if (box && atomic_dec_and_test(&box->refcnt))
 985                                 list_add(&box->list, &boxes_to_free);
 986                 }
 987         }
 988 }
 989
 990 static int uncore_cpu_starting(int cpu)
 991 {
 992         struct intel_uncore_type *type;
 993         struct intel_uncore_pmu *pmu;
 994         struct intel_uncore_box *box, *exist;
 995         int i, j, k, phys_id;
 996
 997         phys_id = topology_physical_package_id(cpu);
 998
 999         for (i = 0; uncore_msr_uncores[i]; i++) {
1000                 type = uncore_msr_uncores[i];
1001                 for (j = 0; j < type->num_boxes; j++) {
1002                         pmu = &type->pmus[j];
1003                         box = *per_cpu_ptr(pmu->box, cpu);
1004                         /* called by uncore_cpu_init? */
1005                         if (box && box->phys_id >= 0)
1006                                 continue;
1007
1008                         for_each_online_cpu(k) {
1009                                 exist = *per_cpu_ptr(pmu->box, k);
1010                                 if (exist && exist->phys_id == phys_id) {
1011                                         atomic_inc(&exist->refcnt);
1012                                         *per_cpu_ptr(pmu->box, cpu) = exist;
1013                                         if (box) {
1014                                                 list_add(&box->list,
1015                                                          &boxes_to_free);
1016                                                 box = NULL;
1017                                         }
1018                                         break;
1019                                 }
1020                         }
1021
1022                         if (box)
1023                                 box->phys_id = phys_id;
1024                 }
1025         }
1026         return 0;
1027 }
1028
1029 static int uncore_cpu_prepare(int cpu, int phys_id)
1030 {
1031         struct intel_uncore_type *type;
1032         struct intel_uncore_pmu *pmu;
1033         struct intel_uncore_box *box;
1034         int i, j;
1035
1036         for (i = 0; uncore_msr_uncores[i]; i++) {
1037                 type = uncore_msr_uncores[i];
1038                 for (j = 0; j < type->num_boxes; j++) {
1039                         pmu = &type->pmus[j];
1040                         if (pmu->func_id < 0)
1041                                 pmu->func_id = j;
1042
1043                         box = uncore_alloc_box(type, cpu_to_node(cpu));
1044                         if (!box)
1045                                 return -ENOMEM;
1046
1047                         box->pmu = pmu;
1048                         box->phys_id = phys_id;
1049                         *per_cpu_ptr(pmu->box, cpu) = box;
1050                 }
1051         }
1052         return 0;
1053 }
1054
1055 static void
1056 uncore_change_context(struct intel_uncore_type **uncores, int old_cpu, int new_cpu)
1057 {
1058         struct intel_uncore_type *type;
1059         struct intel_uncore_pmu *pmu;
1060         struct intel_uncore_box *box;
1061         int i, j;
1062
1063         for (i = 0; uncores[i]; i++) {
1064                 type = uncores[i];
1065                 for (j = 0; j < type->num_boxes; j++) {
1066                         pmu = &type->pmus[j];
1067                         if (old_cpu < 0)
1068                                 box = uncore_pmu_to_box(pmu, new_cpu);
1069                         else
1070                                 box = uncore_pmu_to_box(pmu, old_cpu);
1071                         if (!box)
1072                                 continue;
1073
1074                         if (old_cpu < 0) {
1075                                 WARN_ON_ONCE(box->cpu != -1);
1076                                 box->cpu = new_cpu;
1077                                 continue;
1078                         }
1079
1080                         WARN_ON_ONCE(box->cpu != old_cpu);
1081                         if (new_cpu >= 0) {
1082                                 uncore_pmu_cancel_hrtimer(box);
1083                                 perf_pmu_migrate_context(&pmu->pmu,
1084                                                 old_cpu, new_cpu);
1085                                 box->cpu = new_cpu;
1086                         } else {
1087                                 box->cpu = -1;
1088                         }
1089                 }
1090         }
1091 }
1092
1093 static void uncore_event_exit_cpu(int cpu)
1094 {
1095         int i, phys_id, target;
1096
1097         /* if exiting cpu is used for collecting uncore events */
1098         if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask))
1099                 return;
1100
1101         /* find a new cpu to collect uncore events */
1102         phys_id = topology_physical_package_id(cpu);
1103         target = -1;
1104         for_each_online_cpu(i) {
1105                 if (i == cpu)
1106                         continue;
1107                 if (phys_id == topology_physical_package_id(i)) {
1108                         target = i;
1109                         break;
1110                 }
1111         }
1112
1113         /* migrate uncore events to the new cpu */
1114         if (target >= 0)
1115                 cpumask_set_cpu(target, &uncore_cpu_mask);
1116
1117         uncore_change_context(uncore_msr_uncores, cpu, target);
1118         uncore_change_context(uncore_pci_uncores, cpu, target);
1119 }
1120
1121 static void uncore_event_init_cpu(int cpu)
1122 {
1123         int i, phys_id;
1124
1125         phys_id = topology_physical_package_id(cpu);
1126         for_each_cpu(i, &uncore_cpu_mask) {
1127                 if (phys_id == topology_physical_package_id(i))
1128                         return;
1129         }
1130
1131         cpumask_set_cpu(cpu, &uncore_cpu_mask);
1132
1133         uncore_change_context(uncore_msr_uncores, -1, cpu);
1134         uncore_change_context(uncore_pci_uncores, -1, cpu);
1135 }
1136
1137 static int uncore_cpu_notifier(struct notifier_block *self,
1138                                unsigned long action, void *hcpu)
1139 {
1140         unsigned int cpu = (long)hcpu;
1141
1142         /* allocate/free data structure for uncore box */
1143         switch (action & ~CPU_TASKS_FROZEN) {
1144         case CPU_UP_PREPARE:
1145                 uncore_cpu_prepare(cpu, -1);
1146                 break;
1147         case CPU_STARTING:
1148                 uncore_cpu_starting(cpu);
1149                 break;
1150         case CPU_UP_CANCELED:
1151         case CPU_DYING:
1152                 uncore_cpu_dying(cpu);
1153                 break;
1154         case CPU_ONLINE:
1155         case CPU_DEAD:
1156                 uncore_kfree_boxes();
1157                 break;
1158         default:
1159                 break;
1160         }
1161
1162         /* select the cpu that collects uncore events */
1163         switch (action & ~CPU_TASKS_FROZEN) {
1164         case CPU_DOWN_FAILED:
1165         case CPU_STARTING:
1166                 uncore_event_init_cpu(cpu);
1167                 break;
1168         case CPU_DOWN_PREPARE:
1169                 uncore_event_exit_cpu(cpu);
1170                 break;
1171         default:
1172                 break;
1173         }
1174
1175         return NOTIFY_OK;
1176 }
1177
1178 static struct notifier_block uncore_cpu_nb = {
1179         .notifier_call  = uncore_cpu_notifier,
1180         /*
1181          * to migrate uncore events, our notifier should be executed
1182          * before perf core's notifier.
1183          */
1184         .priority       = CPU_PRI_PERF + 1,
1185 };
1186
1187 static void __init uncore_cpu_setup(void *dummy)
1188 {
1189         uncore_cpu_starting(smp_processor_id());
1190 }
1191
1192 static int __init uncore_cpu_init(void)
1193 {
1194         int ret;
1195
1196         switch (boot_cpu_data.x86_model) {
1197         case 26: /* Nehalem */
1198         case 30:
1199         case 37: /* Westmere */
1200         case 44:
1201                 nhm_uncore_cpu_init();
1202                 break;
1203         case 42: /* Sandy Bridge */
1204         case 58: /* Ivy Bridge */
1205                 snb_uncore_cpu_init();
1206                 break;
1207         case 45: /* Sandy Bridge-EP */
1208                 snbep_uncore_cpu_init();
1209                 break;
1210         case 46: /* Nehalem-EX */
1211         case 47: /* Westmere-EX aka. Xeon E7 */
1212                 nhmex_uncore_cpu_init();
1213                 break;
1214         case 62: /* Ivy Bridge-EP */
1215                 ivbep_uncore_cpu_init();
1216                 break;
1217         case 63: /* Haswell-EP */
1218                 hswep_uncore_cpu_init();
1219                 break;
1220         default:
1221                 return 0;
1222         }
1223
1224         ret = uncore_types_init(uncore_msr_uncores);
1225         if (ret)
1226                 return ret;
1227
1228         return 0;
1229 }
1230
1231 static int __init uncore_pmus_register(void)
1232 {
1233         struct intel_uncore_pmu *pmu;
1234         struct intel_uncore_type *type;
1235         int i, j;
1236
1237         for (i = 0; uncore_msr_uncores[i]; i++) {
1238                 type = uncore_msr_uncores[i];
1239                 for (j = 0; j < type->num_boxes; j++) {
1240                         pmu = &type->pmus[j];
1241                         uncore_pmu_register(pmu);
1242                 }
1243         }
1244
1245         return 0;
1246 }
1247
1248 static void __init uncore_cpumask_init(void)
1249 {
1250         int cpu;
1251
1252         /*
1253          * ony invoke once from msr or pci init code
1254          */
1255         if (!cpumask_empty(&uncore_cpu_mask))
1256                 return;
1257
1258         cpu_notifier_register_begin();
1259
1260         for_each_online_cpu(cpu) {
1261                 int i, phys_id = topology_physical_package_id(cpu);
1262
1263                 for_each_cpu(i, &uncore_cpu_mask) {
1264                         if (phys_id == topology_physical_package_id(i)) {
1265                                 phys_id = -1;
1266                                 break;
1267                         }
1268                 }
1269                 if (phys_id < 0)
1270                         continue;
1271
1272                 uncore_cpu_prepare(cpu, phys_id);
1273                 uncore_event_init_cpu(cpu);
1274         }
1275         on_each_cpu(uncore_cpu_setup, NULL, 1);
1276
1277         __register_cpu_notifier(&uncore_cpu_nb);
1278
1279         cpu_notifier_register_done();
1280 }
1281
1282
1283 static int __init intel_uncore_init(void)
1284 {
1285         int ret;
1286
1287         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
1288                 return -ENODEV;
1289
1290         if (cpu_has_hypervisor)
1291                 return -ENODEV;
1292
1293         ret = uncore_pci_init();
1294         if (ret)
1295                 goto fail;
1296         ret = uncore_cpu_init();
1297         if (ret) {
1298                 uncore_pci_exit();
1299                 goto fail;
1300         }
1301         uncore_cpumask_init();
1302
1303         uncore_pmus_register();
1304         return 0;
1305 fail:
1306         return ret;
1307 }
1308 device_initcall(intel_uncore_init);