arch/x86/kernel/cpu/perf_event_intel_uncore.c

   1 #include "perf_event_intel_uncore.h"
   2
   3 static struct intel_uncore_type *empty_uncore[] = { NULL, };
   4 struct intel_uncore_type **uncore_msr_uncores = empty_uncore;
   5 struct intel_uncore_type **uncore_pci_uncores = empty_uncore;
   6
   7 static bool pcidrv_registered;
   8 struct pci_driver *uncore_pci_driver;
   9 /* pci bus to socket mapping */
  10 int uncore_pcibus_to_physid[256] = { [0 ... 255] = -1, };
  11 struct pci_dev *uncore_extra_pci_dev[UNCORE_SOCKET_MAX][UNCORE_EXTRA_PCI_DEV_MAX];
  12
  13 static DEFINE_RAW_SPINLOCK(uncore_box_lock);
  14 /* mask of cpus that collect uncore events */
  15 static cpumask_t uncore_cpu_mask;
  16
  17 /* constraint for the fixed counter */
  18 static struct event_constraint uncore_constraint_fixed =
  19         EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL);
  20 struct event_constraint uncore_constraint_empty =
  21         EVENT_CONSTRAINT(0, 0, 0);
  22
  23 ssize_t uncore_event_show(struct kobject *kobj,
  24                           struct kobj_attribute *attr, char *buf)
  25 {
  26         struct uncore_event_desc *event =
  27                 container_of(attr, struct uncore_event_desc, attr);
  28         return sprintf(buf, "%s", event->config);
  29 }
  30
  31 struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
  32 {
  33         return container_of(event->pmu, struct intel_uncore_pmu, pmu);
  34 }
  35
  36 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
  37 {
  38         struct intel_uncore_box *box;
  39
  40         box = *per_cpu_ptr(pmu->box, cpu);
  41         if (box)
  42                 return box;
  43
  44         raw_spin_lock(&uncore_box_lock);
  45         /* Recheck in lock to handle races. */
  46         if (*per_cpu_ptr(pmu->box, cpu))
  47                 goto out;
  48         list_for_each_entry(box, &pmu->box_list, list) {
  49                 if (box->phys_id == topology_physical_package_id(cpu)) {
  50                         atomic_inc(&box->refcnt);
  51                         *per_cpu_ptr(pmu->box, cpu) = box;
  52                         break;
  53                 }
  54         }
  55 out:
  56         raw_spin_unlock(&uncore_box_lock);
  57
  58         return *per_cpu_ptr(pmu->box, cpu);
  59 }
  60
  61 struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
  62 {
  63         /*
  64          * perf core schedules event on the basis of cpu, uncore events are
  65          * collected by one of the cpus inside a physical package.
  66          */
  67         return uncore_pmu_to_box(uncore_event_to_pmu(event), smp_processor_id());
  68 }
  69
  70 u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
  71 {
  72         u64 count;
  73
  74         rdmsrl(event->hw.event_base, count);
  75
  76         return count;
  77 }
  78
  79 /*
  80  * generic get constraint function for shared match/mask registers.
  81  */
  82 struct event_constraint *
  83 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
  84 {
  85         struct intel_uncore_extra_reg *er;
  86         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
  87         struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
  88         unsigned long flags;
  89         bool ok = false;
  90
  91         /*
  92          * reg->alloc can be set due to existing state, so for fake box we
  93          * need to ignore this, otherwise we might fail to allocate proper
  94          * fake state for this extra reg constraint.
  95          */
  96         if (reg1->idx == EXTRA_REG_NONE ||
  97             (!uncore_box_is_fake(box) && reg1->alloc))
  98                 return NULL;
  99
 100         er = &box->shared_regs[reg1->idx];
 101         raw_spin_lock_irqsave(&er->lock, flags);
 102         if (!atomic_read(&er->ref) ||
 103             (er->config1 == reg1->config && er->config2 == reg2->config)) {
 104                 atomic_inc(&er->ref);
 105                 er->config1 = reg1->config;
 106                 er->config2 = reg2->config;
 107                 ok = true;
 108         }
 109         raw_spin_unlock_irqrestore(&er->lock, flags);
 110
 111         if (ok) {
 112                 if (!uncore_box_is_fake(box))
 113                         reg1->alloc = 1;
 114                 return NULL;
 115         }
 116
 117         return &uncore_constraint_empty;
 118 }
 119
 120 void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
 121 {
 122         struct intel_uncore_extra_reg *er;
 123         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
 124
 125         /*
 126          * Only put constraint if extra reg was actually allocated. Also
 127          * takes care of event which do not use an extra shared reg.
 128          *
 129          * Also, if this is a fake box we shouldn't touch any event state
 130          * (reg->alloc) and we don't care about leaving inconsistent box
 131          * state either since it will be thrown out.
 132          */
 133         if (uncore_box_is_fake(box) || !reg1->alloc)
 134                 return;
 135
 136         er = &box->shared_regs[reg1->idx];
 137         atomic_dec(&er->ref);
 138         reg1->alloc = 0;
 139 }
 140
 141 u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx)
 142 {
 143         struct intel_uncore_extra_reg *er;
 144         unsigned long flags;
 145         u64 config;
 146
 147         er = &box->shared_regs[idx];
 148
 149         raw_spin_lock_irqsave(&er->lock, flags);
 150         config = er->config;
 151         raw_spin_unlock_irqrestore(&er->lock, flags);
 152
 153         return config;
 154 }
 155
 156 static void uncore_assign_hw_event(struct intel_uncore_box *box, struct perf_event *event, int idx)
 157 {
 158         struct hw_perf_event *hwc = &event->hw;
 159
 160         hwc->idx = idx;
 161         hwc->last_tag = ++box->tags[idx];
 162
 163         if (hwc->idx == UNCORE_PMC_IDX_FIXED) {
 164                 hwc->event_base = uncore_fixed_ctr(box);
 165                 hwc->config_base = uncore_fixed_ctl(box);
 166                 return;
 167         }
 168
 169         hwc->config_base = uncore_event_ctl(box, hwc->idx);
 170         hwc->event_base  = uncore_perf_ctr(box, hwc->idx);
 171 }
 172
 173 void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event)
 174 {
 175         u64 prev_count, new_count, delta;
 176         int shift;
 177
 178         if (event->hw.idx >= UNCORE_PMC_IDX_FIXED)
 179                 shift = 64 - uncore_fixed_ctr_bits(box);
 180         else
 181                 shift = 64 - uncore_perf_ctr_bits(box);
 182
 183         /* the hrtimer might modify the previous event value */
 184 again:
 185         prev_count = local64_read(&event->hw.prev_count);
 186         new_count = uncore_read_counter(box, event);
 187         if (local64_xchg(&event->hw.prev_count, new_count) != prev_count)
 188                 goto again;
 189
 190         delta = (new_count << shift) - (prev_count << shift);
 191         delta >>= shift;
 192
 193         local64_add(delta, &event->count);
 194 }
 195
 196 /*
 197  * The overflow interrupt is unavailable for SandyBridge-EP, is broken
 198  * for SandyBridge. So we use hrtimer to periodically poll the counter
 199  * to avoid overflow.
 200  */
 201 static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer)
 202 {
 203         struct intel_uncore_box *box;
 204         struct perf_event *event;
 205         unsigned long flags;
 206         int bit;
 207
 208         box = container_of(hrtimer, struct intel_uncore_box, hrtimer);
 209         if (!box->n_active || box->cpu != smp_processor_id())
 210                 return HRTIMER_NORESTART;
 211         /*
 212          * disable local interrupt to prevent uncore_pmu_event_start/stop
 213          * to interrupt the update process
 214          */
 215         local_irq_save(flags);
 216
 217         /*
 218          * handle boxes with an active event list as opposed to active
 219          * counters
 220          */
 221         list_for_each_entry(event, &box->active_list, active_entry) {
 222                 uncore_perf_event_update(box, event);
 223         }
 224
 225         for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX)
 226                 uncore_perf_event_update(box, box->events[bit]);
 227
 228         local_irq_restore(flags);
 229
 230         hrtimer_forward_now(hrtimer, ns_to_ktime(box->hrtimer_duration));
 231         return HRTIMER_RESTART;
 232 }
 233
 234 void uncore_pmu_start_hrtimer(struct intel_uncore_box *box)
 235 {
 236         __hrtimer_start_range_ns(&box->hrtimer,
 237                         ns_to_ktime(box->hrtimer_duration), 0,
 238                         HRTIMER_MODE_REL_PINNED, 0);
 239 }
 240
 241 void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box)
 242 {
 243         hrtimer_cancel(&box->hrtimer);
 244 }
 245
 246 static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
 247 {
 248         hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 249         box->hrtimer.function = uncore_pmu_hrtimer;
 250 }
 251
 252 static struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type, int node)
 253 {
 254         struct intel_uncore_box *box;
 255         int i, size;
 256
 257         size = sizeof(*box) + type->num_shared_regs * sizeof(struct intel_uncore_extra_reg);
 258
 259         box = kzalloc_node(size, GFP_KERNEL, node);
 260         if (!box)
 261                 return NULL;
 262
 263         for (i = 0; i < type->num_shared_regs; i++)
 264                 raw_spin_lock_init(&box->shared_regs[i].lock);
 265
 266         uncore_pmu_init_hrtimer(box);
 267         atomic_set(&box->refcnt, 1);
 268         box->cpu = -1;
 269         box->phys_id = -1;
 270
 271         /* set default hrtimer timeout */
 272         box->hrtimer_duration = UNCORE_PMU_HRTIMER_INTERVAL;
 273
 274         INIT_LIST_HEAD(&box->active_list);
 275
 276         return box;
 277 }
 278
 279 /*
 280  * Using uncore_pmu_event_init pmu event_init callback
 281  * as a detection point for uncore events.
 282  */
 283 static int uncore_pmu_event_init(struct perf_event *event);
 284
 285 static bool is_uncore_event(struct perf_event *event)
 286 {
 287         return event->pmu->event_init == uncore_pmu_event_init;
 288 }
 289
 290 static int
 291 uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader, bool dogrp)
 292 {
 293         struct perf_event *event;
 294         int n, max_count;
 295
 296         max_count = box->pmu->type->num_counters;
 297         if (box->pmu->type->fixed_ctl)
 298                 max_count++;
 299
 300         if (box->n_events >= max_count)
 301                 return -EINVAL;
 302
 303         n = box->n_events;
 304
 305         if (is_uncore_event(leader)) {
 306                 box->event_list[n] = leader;
 307                 n++;
 308         }
 309
 310         if (!dogrp)
 311                 return n;
 312
 313         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 314                 if (!is_uncore_event(event) ||
 315                     event->state <= PERF_EVENT_STATE_OFF)
 316                         continue;
 317
 318                 if (n >= max_count)
 319                         return -EINVAL;
 320
 321                 box->event_list[n] = event;
 322                 n++;
 323         }
 324         return n;
 325 }
 326
 327 static struct event_constraint *
 328 uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
 329 {
 330         struct intel_uncore_type *type = box->pmu->type;
 331         struct event_constraint *c;
 332
 333         if (type->ops->get_constraint) {
 334                 c = type->ops->get_constraint(box, event);
 335                 if (c)
 336                         return c;
 337         }
 338
 339         if (event->attr.config == UNCORE_FIXED_EVENT)
 340                 return &uncore_constraint_fixed;
 341
 342         if (type->constraints) {
 343                 for_each_event_constraint(c, type->constraints) {
 344                         if ((event->hw.config & c->cmask) == c->code)
 345                                 return c;
 346                 }
 347         }
 348
 349         return &type->unconstrainted;
 350 }
 351
 352 static void uncore_put_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
 353 {
 354         if (box->pmu->type->ops->put_constraint)
 355                 box->pmu->type->ops->put_constraint(box, event);
 356 }
 357
 358 static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n)
 359 {
 360         unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
 361         struct event_constraint *c;
 362         int i, wmin, wmax, ret = 0;
 363         struct hw_perf_event *hwc;
 364
 365         bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);
 366
 367         for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 368                 hwc = &box->event_list[i]->hw;
 369                 c = uncore_get_event_constraint(box, box->event_list[i]);
 370                 hwc->constraint = c;
 371                 wmin = min(wmin, c->weight);
 372                 wmax = max(wmax, c->weight);
 373         }
 374
 375         /* fastpath, try to reuse previous register */
 376         for (i = 0; i < n; i++) {
 377                 hwc = &box->event_list[i]->hw;
 378                 c = hwc->constraint;
 379
 380                 /* never assigned */
 381                 if (hwc->idx == -1)
 382                         break;
 383
 384                 /* constraint still honored */
 385                 if (!test_bit(hwc->idx, c->idxmsk))
 386                         break;
 387
 388                 /* not already used */
 389                 if (test_bit(hwc->idx, used_mask))
 390                         break;
 391
 392                 __set_bit(hwc->idx, used_mask);
 393                 if (assign)
 394                         assign[i] = hwc->idx;
 395         }
 396         /* slow path */
 397         if (i != n)
 398                 ret = perf_assign_events(box->event_list, n,
 399                                          wmin, wmax, assign);
 400
 401         if (!assign || ret) {
 402                 for (i = 0; i < n; i++)
 403                         uncore_put_event_constraint(box, box->event_list[i]);
 404         }
 405         return ret ? -EINVAL : 0;
 406 }
 407
 408 static void uncore_pmu_event_start(struct perf_event *event, int flags)
 409 {
 410         struct intel_uncore_box *box = uncore_event_to_box(event);
 411         int idx = event->hw.idx;
 412
 413         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
 414                 return;
 415
 416         if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
 417                 return;
 418
 419         event->hw.state = 0;
 420         box->events[idx] = event;
 421         box->n_active++;
 422         __set_bit(idx, box->active_mask);
 423
 424         local64_set(&event->hw.prev_count, uncore_read_counter(box, event));
 425         uncore_enable_event(box, event);
 426
 427         if (box->n_active == 1) {
 428                 uncore_enable_box(box);
 429                 uncore_pmu_start_hrtimer(box);
 430         }
 431 }
 432
 433 static void uncore_pmu_event_stop(struct perf_event *event, int flags)
 434 {
 435         struct intel_uncore_box *box = uncore_event_to_box(event);
 436         struct hw_perf_event *hwc = &event->hw;
 437
 438         if (__test_and_clear_bit(hwc->idx, box->active_mask)) {
 439                 uncore_disable_event(box, event);
 440                 box->n_active--;
 441                 box->events[hwc->idx] = NULL;
 442                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
 443                 hwc->state |= PERF_HES_STOPPED;
 444
 445                 if (box->n_active == 0) {
 446                         uncore_disable_box(box);
 447                         uncore_pmu_cancel_hrtimer(box);
 448                 }
 449         }
 450
 451         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
 452                 /*
 453                  * Drain the remaining delta count out of a event
 454                  * that we are disabling:
 455                  */
 456                 uncore_perf_event_update(box, event);
 457                 hwc->state |= PERF_HES_UPTODATE;
 458         }
 459 }
 460
 461 static int uncore_pmu_event_add(struct perf_event *event, int flags)
 462 {
 463         struct intel_uncore_box *box = uncore_event_to_box(event);
 464         struct hw_perf_event *hwc = &event->hw;
 465         int assign[UNCORE_PMC_IDX_MAX];
 466         int i, n, ret;
 467
 468         if (!box)
 469                 return -ENODEV;
 470
 471         ret = n = uncore_collect_events(box, event, false);
 472         if (ret < 0)
 473                 return ret;
 474
 475         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 476         if (!(flags & PERF_EF_START))
 477                 hwc->state |= PERF_HES_ARCH;
 478
 479         ret = uncore_assign_events(box, assign, n);
 480         if (ret)
 481                 return ret;
 482
 483         /* save events moving to new counters */
 484         for (i = 0; i < box->n_events; i++) {
 485                 event = box->event_list[i];
 486                 hwc = &event->hw;
 487
 488                 if (hwc->idx == assign[i] &&
 489                         hwc->last_tag == box->tags[assign[i]])
 490                         continue;
 491                 /*
 492                  * Ensure we don't accidentally enable a stopped
 493                  * counter simply because we rescheduled.
 494                  */
 495                 if (hwc->state & PERF_HES_STOPPED)
 496                         hwc->state |= PERF_HES_ARCH;
 497
 498                 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
 499         }
 500
 501         /* reprogram moved events into new counters */
 502         for (i = 0; i < n; i++) {
 503                 event = box->event_list[i];
 504                 hwc = &event->hw;
 505
 506                 if (hwc->idx != assign[i] ||
 507                         hwc->last_tag != box->tags[assign[i]])
 508                         uncore_assign_hw_event(box, event, assign[i]);
 509                 else if (i < box->n_events)
 510                         continue;
 511
 512                 if (hwc->state & PERF_HES_ARCH)
 513                         continue;
 514
 515                 uncore_pmu_event_start(event, 0);
 516         }
 517         box->n_events = n;
 518
 519         return 0;
 520 }
 521
 522 static void uncore_pmu_event_del(struct perf_event *event, int flags)
 523 {
 524         struct intel_uncore_box *box = uncore_event_to_box(event);
 525         int i;
 526
 527         uncore_pmu_event_stop(event, PERF_EF_UPDATE);
 528
 529         for (i = 0; i < box->n_events; i++) {
 530                 if (event == box->event_list[i]) {
 531                         uncore_put_event_constraint(box, event);
 532
 533                         while (++i < box->n_events)
 534                                 box->event_list[i - 1] = box->event_list[i];
 535
 536                         --box->n_events;
 537                         break;
 538                 }
 539         }
 540
 541         event->hw.idx = -1;
 542         event->hw.last_tag = ~0ULL;
 543 }
 544
 545 void uncore_pmu_event_read(struct perf_event *event)
 546 {
 547         struct intel_uncore_box *box = uncore_event_to_box(event);
 548         uncore_perf_event_update(box, event);
 549 }
 550
 551 /*
 552  * validation ensures the group can be loaded onto the
 553  * PMU if it was the only group available.
 554  */
 555 static int uncore_validate_group(struct intel_uncore_pmu *pmu,
 556                                 struct perf_event *event)
 557 {
 558         struct perf_event *leader = event->group_leader;
 559         struct intel_uncore_box *fake_box;
 560         int ret = -EINVAL, n;
 561
 562         fake_box = uncore_alloc_box(pmu->type, NUMA_NO_NODE);
 563         if (!fake_box)
 564                 return -ENOMEM;
 565
 566         fake_box->pmu = pmu;
 567         /*
 568          * the event is not yet connected with its
 569          * siblings therefore we must first collect
 570          * existing siblings, then add the new event
 571          * before we can simulate the scheduling
 572          */
 573         n = uncore_collect_events(fake_box, leader, true);
 574         if (n < 0)
 575                 goto out;
 576
 577         fake_box->n_events = n;
 578         n = uncore_collect_events(fake_box, event, false);
 579         if (n < 0)
 580                 goto out;
 581
 582         fake_box->n_events = n;
 583
 584         ret = uncore_assign_events(fake_box, NULL, n);
 585 out:
 586         kfree(fake_box);
 587         return ret;
 588 }
 589
 590 static int uncore_pmu_event_init(struct perf_event *event)
 591 {
 592         struct intel_uncore_pmu *pmu;
 593         struct intel_uncore_box *box;
 594         struct hw_perf_event *hwc = &event->hw;
 595         int ret;
 596
 597         if (event->attr.type != event->pmu->type)
 598                 return -ENOENT;
 599
 600         pmu = uncore_event_to_pmu(event);
 601         /* no device found for this pmu */
 602         if (pmu->func_id < 0)
 603                 return -ENOENT;
 604
 605         /*
 606          * Uncore PMU does measure at all privilege level all the time.
 607          * So it doesn't make sense to specify any exclude bits.
 608          */
 609         if (event->attr.exclude_user || event->attr.exclude_kernel ||
 610                         event->attr.exclude_hv || event->attr.exclude_idle)
 611                 return -EINVAL;
 612
 613         /* Sampling not supported yet */
 614         if (hwc->sample_period)
 615                 return -EINVAL;
 616
 617         /*
 618          * Place all uncore events for a particular physical package
 619          * onto a single cpu
 620          */
 621         if (event->cpu < 0)
 622                 return -EINVAL;
 623         box = uncore_pmu_to_box(pmu, event->cpu);
 624         if (!box || box->cpu < 0)
 625                 return -EINVAL;
 626         event->cpu = box->cpu;
 627
 628         event->hw.idx = -1;
 629         event->hw.last_tag = ~0ULL;
 630         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 631         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 632
 633         if (event->attr.config == UNCORE_FIXED_EVENT) {
 634                 /* no fixed counter */
 635                 if (!pmu->type->fixed_ctl)
 636                         return -EINVAL;
 637                 /*
 638                  * if there is only one fixed counter, only the first pmu
 639                  * can access the fixed counter
 640                  */
 641                 if (pmu->type->single_fixed && pmu->pmu_idx > 0)
 642                         return -EINVAL;
 643
 644                 /* fixed counters have event field hardcoded to zero */
 645                 hwc->config = 0ULL;
 646         } else {
 647                 hwc->config = event->attr.config & pmu->type->event_mask;
 648                 if (pmu->type->ops->hw_config) {
 649                         ret = pmu->type->ops->hw_config(box, event);
 650                         if (ret)
 651                                 return ret;
 652                 }
 653         }
 654
 655         if (event->group_leader != event)
 656                 ret = uncore_validate_group(pmu, event);
 657         else
 658                 ret = 0;
 659
 660         return ret;
 661 }
 662
 663 static ssize_t uncore_get_attr_cpumask(struct device *dev,
 664                                 struct device_attribute *attr, char *buf)
 665 {
 666         return cpumap_print_to_pagebuf(true, buf, &uncore_cpu_mask);
 667 }
 668
 669 static DEVICE_ATTR(cpumask, S_IRUGO, uncore_get_attr_cpumask, NULL);
 670
 671 static struct attribute *uncore_pmu_attrs[] = {
 672         &dev_attr_cpumask.attr,
 673         NULL,
 674 };
 675
 676 static struct attribute_group uncore_pmu_attr_group = {
 677         .attrs = uncore_pmu_attrs,
 678 };
 679
 680 static int uncore_pmu_register(struct intel_uncore_pmu *pmu)
 681 {
 682         int ret;
 683
 684         if (!pmu->type->pmu) {
 685                 pmu->pmu = (struct pmu) {
 686                         .attr_groups    = pmu->type->attr_groups,
 687                         .task_ctx_nr    = perf_invalid_context,
 688                         .event_init     = uncore_pmu_event_init,
 689                         .add            = uncore_pmu_event_add,
 690                         .del            = uncore_pmu_event_del,
 691                         .start          = uncore_pmu_event_start,
 692                         .stop           = uncore_pmu_event_stop,
 693                         .read           = uncore_pmu_event_read,
 694                 };
 695         } else {
 696                 pmu->pmu = *pmu->type->pmu;
 697                 pmu->pmu.attr_groups = pmu->type->attr_groups;
 698         }
 699
 700         if (pmu->type->num_boxes == 1) {
 701                 if (strlen(pmu->type->name) > 0)
 702                         sprintf(pmu->name, "uncore_%s", pmu->type->name);
 703                 else
 704                         sprintf(pmu->name, "uncore");
 705         } else {
 706                 sprintf(pmu->name, "uncore_%s_%d", pmu->type->name,
 707                         pmu->pmu_idx);
 708         }
 709
 710         ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
 711         return ret;
 712 }
 713
 714 static void __init uncore_type_exit(struct intel_uncore_type *type)
 715 {
 716         int i;
 717
 718         for (i = 0; i < type->num_boxes; i++)
 719                 free_percpu(type->pmus[i].box);
 720         kfree(type->pmus);
 721         type->pmus = NULL;
 722         kfree(type->events_group);
 723         type->events_group = NULL;
 724 }
 725
 726 static void __init uncore_types_exit(struct intel_uncore_type **types)
 727 {
 728         int i;
 729         for (i = 0; types[i]; i++)
 730                 uncore_type_exit(types[i]);
 731 }
 732
 733 static int __init uncore_type_init(struct intel_uncore_type *type)
 734 {
 735         struct intel_uncore_pmu *pmus;
 736         struct attribute_group *attr_group;
 737         struct attribute **attrs;
 738         int i, j;
 739
 740         pmus = kzalloc(sizeof(*pmus) * type->num_boxes, GFP_KERNEL);
 741         if (!pmus)
 742                 return -ENOMEM;
 743
 744         type->pmus = pmus;
 745
 746         type->unconstrainted = (struct event_constraint)
 747                 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
 748                                 0, type->num_counters, 0, 0);
 749
 750         for (i = 0; i < type->num_boxes; i++) {
 751                 pmus[i].func_id = -1;
 752                 pmus[i].pmu_idx = i;
 753                 pmus[i].type = type;
 754                 INIT_LIST_HEAD(&pmus[i].box_list);
 755                 pmus[i].box = alloc_percpu(struct intel_uncore_box *);
 756                 if (!pmus[i].box)
 757                         goto fail;
 758         }
 759
 760         if (type->event_descs) {
 761                 i = 0;
 762                 while (type->event_descs[i].attr.attr.name)
 763                         i++;
 764
 765                 attr_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
 766                                         sizeof(*attr_group), GFP_KERNEL);
 767                 if (!attr_group)
 768                         goto fail;
 769
 770                 attrs = (struct attribute **)(attr_group + 1);
 771                 attr_group->name = "events";
 772                 attr_group->attrs = attrs;
 773
 774                 for (j = 0; j < i; j++)
 775                         attrs[j] = &type->event_descs[j].attr.attr;
 776
 777                 type->events_group = attr_group;
 778         }
 779
 780         type->pmu_group = &uncore_pmu_attr_group;
 781         return 0;
 782 fail:
 783         uncore_type_exit(type);
 784         return -ENOMEM;
 785 }
 786
 787 static int __init uncore_types_init(struct intel_uncore_type **types)
 788 {
 789         int i, ret;
 790
 791         for (i = 0; types[i]; i++) {
 792                 ret = uncore_type_init(types[i]);
 793                 if (ret)
 794                         goto fail;
 795         }
 796         return 0;
 797 fail:
 798         while (--i >= 0)
 799                 uncore_type_exit(types[i]);
 800         return ret;
 801 }
 802
 803 /*
 804  * add a pci uncore device
 805  */
 806 static int uncore_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 807 {
 808         struct intel_uncore_pmu *pmu;
 809         struct intel_uncore_box *box;
 810         struct intel_uncore_type *type;
 811         int phys_id;
 812         bool first_box = false;
 813
 814         phys_id = uncore_pcibus_to_physid[pdev->bus->number];
 815         if (phys_id < 0)
 816                 return -ENODEV;
 817
 818         if (UNCORE_PCI_DEV_TYPE(id->driver_data) == UNCORE_EXTRA_PCI_DEV) {
 819                 int idx = UNCORE_PCI_DEV_IDX(id->driver_data);
 820                 uncore_extra_pci_dev[phys_id][idx] = pdev;
 821                 pci_set_drvdata(pdev, NULL);
 822                 return 0;
 823         }
 824
 825         type = uncore_pci_uncores[UNCORE_PCI_DEV_TYPE(id->driver_data)];
 826         box = uncore_alloc_box(type, NUMA_NO_NODE);
 827         if (!box)
 828                 return -ENOMEM;
 829
 830         /*
 831          * for performance monitoring unit with multiple boxes,
 832          * each box has a different function id.
 833          */
 834         pmu = &type->pmus[UNCORE_PCI_DEV_IDX(id->driver_data)];
 835         if (pmu->func_id < 0)
 836                 pmu->func_id = pdev->devfn;
 837         else
 838                 WARN_ON_ONCE(pmu->func_id != pdev->devfn);
 839
 840         box->phys_id = phys_id;
 841         box->pci_dev = pdev;
 842         box->pmu = pmu;
 843         pci_set_drvdata(pdev, box);
 844
 845         raw_spin_lock(&uncore_box_lock);
 846         if (list_empty(&pmu->box_list))
 847                 first_box = true;
 848         list_add_tail(&box->list, &pmu->box_list);
 849         raw_spin_unlock(&uncore_box_lock);
 850
 851         if (first_box)
 852                 uncore_pmu_register(pmu);
 853         return 0;
 854 }
 855
 856 static void uncore_pci_remove(struct pci_dev *pdev)
 857 {
 858         struct intel_uncore_box *box = pci_get_drvdata(pdev);
 859         struct intel_uncore_pmu *pmu;
 860         int i, cpu, phys_id = uncore_pcibus_to_physid[pdev->bus->number];
 861         bool last_box = false;
 862
 863         box = pci_get_drvdata(pdev);
 864         if (!box) {
 865                 for (i = 0; i < UNCORE_EXTRA_PCI_DEV_MAX; i++) {
 866                         if (uncore_extra_pci_dev[phys_id][i] == pdev) {
 867                                 uncore_extra_pci_dev[phys_id][i] = NULL;
 868                                 break;
 869                         }
 870                 }
 871                 WARN_ON_ONCE(i >= UNCORE_EXTRA_PCI_DEV_MAX);
 872                 return;
 873         }
 874
 875         pmu = box->pmu;
 876         if (WARN_ON_ONCE(phys_id != box->phys_id))
 877                 return;
 878
 879         pci_set_drvdata(pdev, NULL);
 880
 881         raw_spin_lock(&uncore_box_lock);
 882         list_del(&box->list);
 883         if (list_empty(&pmu->box_list))
 884                 last_box = true;
 885         raw_spin_unlock(&uncore_box_lock);
 886
 887         for_each_possible_cpu(cpu) {
 888                 if (*per_cpu_ptr(pmu->box, cpu) == box) {
 889                         *per_cpu_ptr(pmu->box, cpu) = NULL;
 890                         atomic_dec(&box->refcnt);
 891                 }
 892         }
 893
 894         WARN_ON_ONCE(atomic_read(&box->refcnt) != 1);
 895         kfree(box);
 896
 897         if (last_box)
 898                 perf_pmu_unregister(&pmu->pmu);
 899 }
 900
 901 static int __init uncore_pci_init(void)
 902 {
 903         int ret;
 904
 905         switch (boot_cpu_data.x86_model) {
 906         case 45: /* Sandy Bridge-EP */
 907                 ret = snbep_uncore_pci_init();
 908                 break;
 909         case 62: /* Ivy Bridge-EP */
 910                 ret = ivbep_uncore_pci_init();
 911                 break;
 912         case 63: /* Haswell-EP */
 913                 ret = hswep_uncore_pci_init();
 914                 break;
 915         case 42: /* Sandy Bridge */
 916                 ret = snb_uncore_pci_init();
 917                 break;
 918         case 58: /* Ivy Bridge */
 919                 ret = ivb_uncore_pci_init();
 920                 break;
 921         case 60: /* Haswell */
 922         case 69: /* Haswell Celeron */
 923                 ret = hsw_uncore_pci_init();
 924                 break;
 925         default:
 926                 return 0;
 927         }
 928
 929         if (ret)
 930                 return ret;
 931
 932         ret = uncore_types_init(uncore_pci_uncores);
 933         if (ret)
 934                 return ret;
 935
 936         uncore_pci_driver->probe = uncore_pci_probe;
 937         uncore_pci_driver->remove = uncore_pci_remove;
 938
 939         ret = pci_register_driver(uncore_pci_driver);
 940         if (ret == 0)
 941                 pcidrv_registered = true;
 942         else
 943                 uncore_types_exit(uncore_pci_uncores);
 944
 945         return ret;
 946 }
 947
 948 static void __init uncore_pci_exit(void)
 949 {
 950         if (pcidrv_registered) {
 951                 pcidrv_registered = false;
 952                 pci_unregister_driver(uncore_pci_driver);
 953                 uncore_types_exit(uncore_pci_uncores);
 954         }
 955 }
 956
 957 /* CPU hot plug/unplug are serialized by cpu_add_remove_lock mutex */
 958 static LIST_HEAD(boxes_to_free);
 959
 960 static void uncore_kfree_boxes(void)
 961 {
 962         struct intel_uncore_box *box;
 963
 964         while (!list_empty(&boxes_to_free)) {
 965                 box = list_entry(boxes_to_free.next,
 966                                  struct intel_uncore_box, list);
 967                 list_del(&box->list);
 968                 kfree(box);
 969         }
 970 }
 971
 972 static void uncore_cpu_dying(int cpu)
 973 {
 974         struct intel_uncore_type *type;
 975         struct intel_uncore_pmu *pmu;
 976         struct intel_uncore_box *box;
 977         int i, j;
 978
 979         for (i = 0; uncore_msr_uncores[i]; i++) {
 980                 type = uncore_msr_uncores[i];
 981                 for (j = 0; j < type->num_boxes; j++) {
 982                         pmu = &type->pmus[j];
 983                         box = *per_cpu_ptr(pmu->box, cpu);
 984                         *per_cpu_ptr(pmu->box, cpu) = NULL;
 985                         if (box && atomic_dec_and_test(&box->refcnt))
 986                                 list_add(&box->list, &boxes_to_free);
 987                 }
 988         }
 989 }
 990
 991 static int uncore_cpu_starting(int cpu)
 992 {
 993         struct intel_uncore_type *type;
 994         struct intel_uncore_pmu *pmu;
 995         struct intel_uncore_box *box, *exist;
 996         int i, j, k, phys_id;
 997
 998         phys_id = topology_physical_package_id(cpu);
 999
1000         for (i = 0; uncore_msr_uncores[i]; i++) {
1001                 type = uncore_msr_uncores[i];
1002                 for (j = 0; j < type->num_boxes; j++) {
1003                         pmu = &type->pmus[j];
1004                         box = *per_cpu_ptr(pmu->box, cpu);
1005                         /* called by uncore_cpu_init? */
1006                         if (box && box->phys_id >= 0)
1007                                 continue;
1008
1009                         for_each_online_cpu(k) {
1010                                 exist = *per_cpu_ptr(pmu->box, k);
1011                                 if (exist && exist->phys_id == phys_id) {
1012                                         atomic_inc(&exist->refcnt);
1013                                         *per_cpu_ptr(pmu->box, cpu) = exist;
1014                                         if (box) {
1015                                                 list_add(&box->list,
1016                                                          &boxes_to_free);
1017                                                 box = NULL;
1018                                         }
1019                                         break;
1020                                 }
1021                         }
1022
1023                         if (box)
1024                                 box->phys_id = phys_id;
1025                 }
1026         }
1027         return 0;
1028 }
1029
1030 static int uncore_cpu_prepare(int cpu, int phys_id)
1031 {
1032         struct intel_uncore_type *type;
1033         struct intel_uncore_pmu *pmu;
1034         struct intel_uncore_box *box;
1035         int i, j;
1036
1037         for (i = 0; uncore_msr_uncores[i]; i++) {
1038                 type = uncore_msr_uncores[i];
1039                 for (j = 0; j < type->num_boxes; j++) {
1040                         pmu = &type->pmus[j];
1041                         if (pmu->func_id < 0)
1042                                 pmu->func_id = j;
1043
1044                         box = uncore_alloc_box(type, cpu_to_node(cpu));
1045                         if (!box)
1046                                 return -ENOMEM;
1047
1048                         box->pmu = pmu;
1049                         box->phys_id = phys_id;
1050                         *per_cpu_ptr(pmu->box, cpu) = box;
1051                 }
1052         }
1053         return 0;
1054 }
1055
1056 static void
1057 uncore_change_context(struct intel_uncore_type **uncores, int old_cpu, int new_cpu)
1058 {
1059         struct intel_uncore_type *type;
1060         struct intel_uncore_pmu *pmu;
1061         struct intel_uncore_box *box;
1062         int i, j;
1063
1064         for (i = 0; uncores[i]; i++) {
1065                 type = uncores[i];
1066                 for (j = 0; j < type->num_boxes; j++) {
1067                         pmu = &type->pmus[j];
1068                         if (old_cpu < 0)
1069                                 box = uncore_pmu_to_box(pmu, new_cpu);
1070                         else
1071                                 box = uncore_pmu_to_box(pmu, old_cpu);
1072                         if (!box)
1073                                 continue;
1074
1075                         if (old_cpu < 0) {
1076                                 WARN_ON_ONCE(box->cpu != -1);
1077                                 box->cpu = new_cpu;
1078                                 continue;
1079                         }
1080
1081                         WARN_ON_ONCE(box->cpu != old_cpu);
1082                         if (new_cpu >= 0) {
1083                                 uncore_pmu_cancel_hrtimer(box);
1084                                 perf_pmu_migrate_context(&pmu->pmu,
1085                                                 old_cpu, new_cpu);
1086                                 box->cpu = new_cpu;
1087                         } else {
1088                                 box->cpu = -1;
1089                         }
1090                 }
1091         }
1092 }
1093
1094 static void uncore_event_exit_cpu(int cpu)
1095 {
1096         int i, phys_id, target;
1097
1098         /* if exiting cpu is used for collecting uncore events */
1099         if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask))
1100                 return;
1101
1102         /* find a new cpu to collect uncore events */
1103         phys_id = topology_physical_package_id(cpu);
1104         target = -1;
1105         for_each_online_cpu(i) {
1106                 if (i == cpu)
1107                         continue;
1108                 if (phys_id == topology_physical_package_id(i)) {
1109                         target = i;
1110                         break;
1111                 }
1112         }
1113
1114         /* migrate uncore events to the new cpu */
1115         if (target >= 0)
1116                 cpumask_set_cpu(target, &uncore_cpu_mask);
1117
1118         uncore_change_context(uncore_msr_uncores, cpu, target);
1119         uncore_change_context(uncore_pci_uncores, cpu, target);
1120 }
1121
1122 static void uncore_event_init_cpu(int cpu)
1123 {
1124         int i, phys_id;
1125
1126         phys_id = topology_physical_package_id(cpu);
1127         for_each_cpu(i, &uncore_cpu_mask) {
1128                 if (phys_id == topology_physical_package_id(i))
1129                         return;
1130         }
1131
1132         cpumask_set_cpu(cpu, &uncore_cpu_mask);
1133
1134         uncore_change_context(uncore_msr_uncores, -1, cpu);
1135         uncore_change_context(uncore_pci_uncores, -1, cpu);
1136 }
1137
1138 static int uncore_cpu_notifier(struct notifier_block *self,
1139                                unsigned long action, void *hcpu)
1140 {
1141         unsigned int cpu = (long)hcpu;
1142
1143         /* allocate/free data structure for uncore box */
1144         switch (action & ~CPU_TASKS_FROZEN) {
1145         case CPU_UP_PREPARE:
1146                 uncore_cpu_prepare(cpu, -1);
1147                 break;
1148         case CPU_STARTING:
1149                 uncore_cpu_starting(cpu);
1150                 break;
1151         case CPU_UP_CANCELED:
1152         case CPU_DYING:
1153                 uncore_cpu_dying(cpu);
1154                 break;
1155         case CPU_ONLINE:
1156         case CPU_DEAD:
1157                 uncore_kfree_boxes();
1158                 break;
1159         default:
1160                 break;
1161         }
1162
1163         /* select the cpu that collects uncore events */
1164         switch (action & ~CPU_TASKS_FROZEN) {
1165         case CPU_DOWN_FAILED:
1166         case CPU_STARTING:
1167                 uncore_event_init_cpu(cpu);
1168                 break;
1169         case CPU_DOWN_PREPARE:
1170                 uncore_event_exit_cpu(cpu);
1171                 break;
1172         default:
1173                 break;
1174         }
1175
1176         return NOTIFY_OK;
1177 }
1178
1179 static struct notifier_block uncore_cpu_nb = {
1180         .notifier_call  = uncore_cpu_notifier,
1181         /*
1182          * to migrate uncore events, our notifier should be executed
1183          * before perf core's notifier.
1184          */
1185         .priority       = CPU_PRI_PERF + 1,
1186 };
1187
1188 static void __init uncore_cpu_setup(void *dummy)
1189 {
1190         uncore_cpu_starting(smp_processor_id());
1191 }
1192
1193 static int __init uncore_cpu_init(void)
1194 {
1195         int ret;
1196
1197         switch (boot_cpu_data.x86_model) {
1198         case 26: /* Nehalem */
1199         case 30:
1200         case 37: /* Westmere */
1201         case 44:
1202                 nhm_uncore_cpu_init();
1203                 break;
1204         case 42: /* Sandy Bridge */
1205         case 58: /* Ivy Bridge */
1206                 snb_uncore_cpu_init();
1207                 break;
1208         case 45: /* Sandy Bridge-EP */
1209                 snbep_uncore_cpu_init();
1210                 break;
1211         case 46: /* Nehalem-EX */
1212         case 47: /* Westmere-EX aka. Xeon E7 */
1213                 nhmex_uncore_cpu_init();
1214                 break;
1215         case 62: /* Ivy Bridge-EP */
1216                 ivbep_uncore_cpu_init();
1217                 break;
1218         case 63: /* Haswell-EP */
1219                 hswep_uncore_cpu_init();
1220                 break;
1221         default:
1222                 return 0;
1223         }
1224
1225         ret = uncore_types_init(uncore_msr_uncores);
1226         if (ret)
1227                 return ret;
1228
1229         return 0;
1230 }
1231
1232 static int __init uncore_pmus_register(void)
1233 {
1234         struct intel_uncore_pmu *pmu;
1235         struct intel_uncore_type *type;
1236         int i, j;
1237
1238         for (i = 0; uncore_msr_uncores[i]; i++) {
1239                 type = uncore_msr_uncores[i];
1240                 for (j = 0; j < type->num_boxes; j++) {
1241                         pmu = &type->pmus[j];
1242                         uncore_pmu_register(pmu);
1243                 }
1244         }
1245
1246         return 0;
1247 }
1248
1249 static void __init uncore_cpumask_init(void)
1250 {
1251         int cpu;
1252
1253         /*
1254          * ony invoke once from msr or pci init code
1255          */
1256         if (!cpumask_empty(&uncore_cpu_mask))
1257                 return;
1258
1259         cpu_notifier_register_begin();
1260
1261         for_each_online_cpu(cpu) {
1262                 int i, phys_id = topology_physical_package_id(cpu);
1263
1264                 for_each_cpu(i, &uncore_cpu_mask) {
1265                         if (phys_id == topology_physical_package_id(i)) {
1266                                 phys_id = -1;
1267                                 break;
1268                         }
1269                 }
1270                 if (phys_id < 0)
1271                         continue;
1272
1273                 uncore_cpu_prepare(cpu, phys_id);
1274                 uncore_event_init_cpu(cpu);
1275         }
1276         on_each_cpu(uncore_cpu_setup, NULL, 1);
1277
1278         __register_cpu_notifier(&uncore_cpu_nb);
1279
1280         cpu_notifier_register_done();
1281 }
1282
1283
1284 static int __init intel_uncore_init(void)
1285 {
1286         int ret;
1287
1288         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
1289                 return -ENODEV;
1290
1291         if (cpu_has_hypervisor)
1292                 return -ENODEV;
1293
1294         ret = uncore_pci_init();
1295         if (ret)
1296                 goto fail;
1297         ret = uncore_cpu_init();
1298         if (ret) {
1299                 uncore_pci_exit();
1300                 goto fail;
1301         }
1302         uncore_cpumask_init();
1303
1304         uncore_pmus_register();
1305         return 0;
1306 fail:
1307         return ret;
1308 }
1309 device_initcall(intel_uncore_init);