x86: coding style fixes to arch/x86/kernel/cpu/mtrr/state.c
[sfrench/cifs-2.6.git] / arch / x86 / kernel / cpu / mtrr / state.c
1 #include <linux/mm.h>
2 #include <linux/init.h>
3 #include <asm/io.h>
4 #include <asm/mtrr.h>
5 #include <asm/msr.h>
6 #include <asm/processor-cyrix.h>
7 #include <asm/processor-flags.h>
8 #include "mtrr.h"
9
10
11 /*  Put the processor into a state where MTRRs can be safely set  */
12 void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
13 {
14         unsigned int cr0;
15
16         /*  Disable interrupts locally  */
17         local_irq_save(ctxt->flags);
18
19         if (use_intel() || is_cpu(CYRIX)) {
20
21                 /*  Save value of CR4 and clear Page Global Enable (bit 7)  */
22                 if (cpu_has_pge) {
23                         ctxt->cr4val = read_cr4();
24                         write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
25                 }
26
27                 /*
28                  * Disable and flush caches. Note that wbinvd flushes the TLBs
29                  * as a side-effect
30                  */
31                 cr0 = read_cr0() | X86_CR0_CD;
32                 wbinvd();
33                 write_cr0(cr0);
34                 wbinvd();
35
36                 if (use_intel())
37                         /*  Save MTRR state */
38                         rdmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
39                 else
40                         /* Cyrix ARRs - everything else were excluded at the top */
41                         ctxt->ccr3 = getCx86(CX86_CCR3);
42         }
43 }
44
45 void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
46 {
47         if (use_intel())
48                 /*  Disable MTRRs, and set the default type to uncached  */
49                 mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL,
50                       ctxt->deftype_hi);
51         else if (is_cpu(CYRIX))
52                 /* Cyrix ARRs - everything else were excluded at the top */
53                 setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
54 }
55
56 /*  Restore the processor after a set_mtrr_prepare  */
57 void set_mtrr_done(struct set_mtrr_context *ctxt)
58 {
59         if (use_intel() || is_cpu(CYRIX)) {
60
61                 /*  Flush caches and TLBs  */
62                 wbinvd();
63
64                 /*  Restore MTRRdefType  */
65                 if (use_intel())
66                         /* Intel (P6) standard MTRRs */
67                         mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
68                 else
69                         /* Cyrix ARRs - everything else was excluded at the top */
70                         setCx86(CX86_CCR3, ctxt->ccr3);
71
72                 /*  Enable caches  */
73                 write_cr0(read_cr0() & 0xbfffffff);
74
75                 /*  Restore value of CR4  */
76                 if (cpu_has_pge)
77                         write_cr4(ctxt->cr4val);
78         }
79         /*  Re-enable interrupts locally (if enabled previously)  */
80         local_irq_restore(ctxt->flags);
81 }
82