arch/x86/kernel/cpu/mcheck/mce_amd.c

   1 /*
   2  *  (c) 2005-2016 Advanced Micro Devices, Inc.
   3  *  Your use of this code is subject to the terms and conditions of the
   4  *  GNU general public license version 2. See "COPYING" or
   5  *  http://www.gnu.org/licenses/gpl.html
   6  *
   7  *  Written by Jacob Shin - AMD, Inc.
   8  *  Maintained by: Borislav Petkov <bp@alien8.de>
   9  *
  10  *  All MC4_MISCi registers are shared between cores on a node.
  11  */
  12 #include <linux/interrupt.h>
  13 #include <linux/notifier.h>
  14 #include <linux/kobject.h>
  15 #include <linux/percpu.h>
  16 #include <linux/errno.h>
  17 #include <linux/sched.h>
  18 #include <linux/sysfs.h>
  19 #include <linux/slab.h>
  20 #include <linux/init.h>
  21 #include <linux/cpu.h>
  22 #include <linux/smp.h>
  23 #include <linux/string.h>
  24
  25 #include <asm/amd_nb.h>
  26 #include <asm/apic.h>
  27 #include <asm/mce.h>
  28 #include <asm/msr.h>
  29 #include <asm/trace/irq_vectors.h>
  30
  31 #include "mce-internal.h"
  32
  33 #define NR_BLOCKS         5
  34 #define THRESHOLD_MAX     0xFFF
  35 #define INT_TYPE_APIC     0x00020000
  36 #define MASK_VALID_HI     0x80000000
  37 #define MASK_CNTP_HI      0x40000000
  38 #define MASK_LOCKED_HI    0x20000000
  39 #define MASK_LVTOFF_HI    0x00F00000
  40 #define MASK_COUNT_EN_HI  0x00080000
  41 #define MASK_INT_TYPE_HI  0x00060000
  42 #define MASK_OVERFLOW_HI  0x00010000
  43 #define MASK_ERR_COUNT_HI 0x00000FFF
  44 #define MASK_BLKPTR_LO    0xFF000000
  45 #define MCG_XBLK_ADDR     0xC0000400
  46
  47 /* Deferred error settings */
  48 #define MSR_CU_DEF_ERR          0xC0000410
  49 #define MASK_DEF_LVTOFF         0x000000F0
  50 #define MASK_DEF_INT_TYPE       0x00000006
  51 #define DEF_LVT_OFF             0x2
  52 #define DEF_INT_TYPE_APIC       0x2
  53
  54 /* Scalable MCA: */
  55
  56 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
  57 #define SMCA_THR_LVT_OFF        0xF000
  58
  59 static bool thresholding_en;
  60
  61 static const char * const th_names[] = {
  62         "load_store",
  63         "insn_fetch",
  64         "combined_unit",
  65         "decode_unit",
  66         "northbridge",
  67         "execution_unit",
  68 };
  69
  70 static const char * const smca_umc_block_names[] = {
  71         "dram_ecc",
  72         "misc_umc"
  73 };
  74
  75 struct smca_bank_name {
  76         const char *name;       /* Short name for sysfs */
  77         const char *long_name;  /* Long name for pretty-printing */
  78 };
  79
  80 static struct smca_bank_name smca_names[] = {
  81         [SMCA_LS]       = { "load_store",       "Load Store Unit" },
  82         [SMCA_IF]       = { "insn_fetch",       "Instruction Fetch Unit" },
  83         [SMCA_L2_CACHE] = { "l2_cache",         "L2 Cache" },
  84         [SMCA_DE]       = { "decode_unit",      "Decode Unit" },
  85         [SMCA_EX]       = { "execution_unit",   "Execution Unit" },
  86         [SMCA_FP]       = { "floating_point",   "Floating Point Unit" },
  87         [SMCA_L3_CACHE] = { "l3_cache",         "L3 Cache" },
  88         [SMCA_CS]       = { "coherent_slave",   "Coherent Slave" },
  89         [SMCA_PIE]      = { "pie",              "Power, Interrupts, etc." },
  90         [SMCA_UMC]      = { "umc",              "Unified Memory Controller" },
  91         [SMCA_PB]       = { "param_block",      "Parameter Block" },
  92         [SMCA_PSP]      = { "psp",              "Platform Security Processor" },
  93         [SMCA_SMU]      = { "smu",              "System Management Unit" },
  94 };
  95
  96 const char *smca_get_name(enum smca_bank_types t)
  97 {
  98         if (t >= N_SMCA_BANK_TYPES)
  99                 return NULL;
 100
 101         return smca_names[t].name;
 102 }
 103
 104 const char *smca_get_long_name(enum smca_bank_types t)
 105 {
 106         if (t >= N_SMCA_BANK_TYPES)
 107                 return NULL;
 108
 109         return smca_names[t].long_name;
 110 }
 111 EXPORT_SYMBOL_GPL(smca_get_long_name);
 112
 113 static struct smca_hwid smca_hwid_mcatypes[] = {
 114         /* { bank_type, hwid_mcatype, xec_bitmap } */
 115
 116         /* ZN Core (HWID=0xB0) MCA types */
 117         { SMCA_LS,       HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF },
 118         { SMCA_IF,       HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
 119         { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF },
 120         { SMCA_DE,       HWID_MCATYPE(0xB0, 0x3), 0x1FF },
 121         /* HWID 0xB0 MCATYPE 0x4 is Reserved */
 122         { SMCA_EX,       HWID_MCATYPE(0xB0, 0x5), 0x7FF },
 123         { SMCA_FP,       HWID_MCATYPE(0xB0, 0x6), 0x7F },
 124         { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF },
 125
 126         /* Data Fabric MCA types */
 127         { SMCA_CS,       HWID_MCATYPE(0x2E, 0x0), 0x1FF },
 128         { SMCA_PIE,      HWID_MCATYPE(0x2E, 0x1), 0xF },
 129
 130         /* Unified Memory Controller MCA type */
 131         { SMCA_UMC,      HWID_MCATYPE(0x96, 0x0), 0x3F },
 132
 133         /* Parameter Block MCA type */
 134         { SMCA_PB,       HWID_MCATYPE(0x05, 0x0), 0x1 },
 135
 136         /* Platform Security Processor MCA type */
 137         { SMCA_PSP,      HWID_MCATYPE(0xFF, 0x0), 0x1 },
 138
 139         /* System Management Unit MCA type */
 140         { SMCA_SMU,      HWID_MCATYPE(0x01, 0x0), 0x1 },
 141 };
 142
 143 struct smca_bank smca_banks[MAX_NR_BANKS];
 144 EXPORT_SYMBOL_GPL(smca_banks);
 145
 146 /*
 147  * In SMCA enabled processors, we can have multiple banks for a given IP type.
 148  * So to define a unique name for each bank, we use a temp c-string to append
 149  * the MCA_IPID[InstanceId] to type's name in get_name().
 150  *
 151  * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
 152  * is greater than 8 plus 1 (for underscore) plus length of longest type name.
 153  */
 154 #define MAX_MCATYPE_NAME_LEN    30
 155 static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
 156
 157 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
 158 static DEFINE_PER_CPU(unsigned int, bank_map);  /* see which banks are on */
 159
 160 static void amd_threshold_interrupt(void);
 161 static void amd_deferred_error_interrupt(void);
 162
 163 static void default_deferred_error_interrupt(void)
 164 {
 165         pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
 166 }
 167 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
 168
 169 static void smca_configure(unsigned int bank, unsigned int cpu)
 170 {
 171         unsigned int i, hwid_mcatype;
 172         struct smca_hwid *s_hwid;
 173         u32 high, low;
 174         u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
 175
 176         /* Set appropriate bits in MCA_CONFIG */
 177         if (!rdmsr_safe(smca_config, &low, &high)) {
 178                 /*
 179                  * OS is required to set the MCAX bit to acknowledge that it is
 180                  * now using the new MSR ranges and new registers under each
 181                  * bank. It also means that the OS will configure deferred
 182                  * errors in the new MCx_CONFIG register. If the bit is not set,
 183                  * uncorrectable errors will cause a system panic.
 184                  *
 185                  * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
 186                  */
 187                 high |= BIT(0);
 188
 189                 /*
 190                  * SMCA sets the Deferred Error Interrupt type per bank.
 191                  *
 192                  * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
 193                  * if the DeferredIntType bit field is available.
 194                  *
 195                  * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
 196                  * high portion of the MSR). OS should set this to 0x1 to enable
 197                  * APIC based interrupt. First, check that no interrupt has been
 198                  * set.
 199                  */
 200                 if ((low & BIT(5)) && !((high >> 5) & 0x3))
 201                         high |= BIT(5);
 202
 203                 wrmsr(smca_config, low, high);
 204         }
 205
 206         /* Return early if this bank was already initialized. */
 207         if (smca_banks[bank].hwid)
 208                 return;
 209
 210         if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
 211                 pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
 212                 return;
 213         }
 214
 215         hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
 216                                     (high & MCI_IPID_MCATYPE) >> 16);
 217
 218         for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
 219                 s_hwid = &smca_hwid_mcatypes[i];
 220                 if (hwid_mcatype == s_hwid->hwid_mcatype) {
 221                         smca_banks[bank].hwid = s_hwid;
 222                         smca_banks[bank].id = low;
 223                         smca_banks[bank].sysfs_id = s_hwid->count++;
 224                         break;
 225                 }
 226         }
 227 }
 228
 229 struct thresh_restart {
 230         struct threshold_block  *b;
 231         int                     reset;
 232         int                     set_lvt_off;
 233         int                     lvt_off;
 234         u16                     old_limit;
 235 };
 236
 237 static inline bool is_shared_bank(int bank)
 238 {
 239         /*
 240          * Scalable MCA provides for only one core to have access to the MSRs of
 241          * a shared bank.
 242          */
 243         if (mce_flags.smca)
 244                 return false;
 245
 246         /* Bank 4 is for northbridge reporting and is thus shared */
 247         return (bank == 4);
 248 }
 249
 250 static const char *bank4_names(const struct threshold_block *b)
 251 {
 252         switch (b->address) {
 253         /* MSR4_MISC0 */
 254         case 0x00000413:
 255                 return "dram";
 256
 257         case 0xc0000408:
 258                 return "ht_links";
 259
 260         case 0xc0000409:
 261                 return "l3_cache";
 262
 263         default:
 264                 WARN(1, "Funny MSR: 0x%08x\n", b->address);
 265                 return "";
 266         }
 267 };
 268
 269
 270 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
 271 {
 272         /*
 273          * bank 4 supports APIC LVT interrupts implicitly since forever.
 274          */
 275         if (bank == 4)
 276                 return true;
 277
 278         /*
 279          * IntP: interrupt present; if this bit is set, the thresholding
 280          * bank can generate APIC LVT interrupts
 281          */
 282         return msr_high_bits & BIT(28);
 283 }
 284
 285 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
 286 {
 287         int msr = (hi & MASK_LVTOFF_HI) >> 20;
 288
 289         if (apic < 0) {
 290                 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
 291                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
 292                        b->bank, b->block, b->address, hi, lo);
 293                 return 0;
 294         }
 295
 296         if (apic != msr) {
 297                 /*
 298                  * On SMCA CPUs, LVT offset is programmed at a different MSR, and
 299                  * the BIOS provides the value. The original field where LVT offset
 300                  * was set is reserved. Return early here:
 301                  */
 302                 if (mce_flags.smca)
 303                         return 0;
 304
 305                 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
 306                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
 307                        b->cpu, apic, b->bank, b->block, b->address, hi, lo);
 308                 return 0;
 309         }
 310
 311         return 1;
 312 };
 313
 314 /* Reprogram MCx_MISC MSR behind this threshold bank. */
 315 static void threshold_restart_bank(void *_tr)
 316 {
 317         struct thresh_restart *tr = _tr;
 318         u32 hi, lo;
 319
 320         rdmsr(tr->b->address, lo, hi);
 321
 322         if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
 323                 tr->reset = 1;  /* limit cannot be lower than err count */
 324
 325         if (tr->reset) {                /* reset err count and overflow bit */
 326                 hi =
 327                     (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
 328                     (THRESHOLD_MAX - tr->b->threshold_limit);
 329         } else if (tr->old_limit) {     /* change limit w/o reset */
 330                 int new_count = (hi & THRESHOLD_MAX) +
 331                     (tr->old_limit - tr->b->threshold_limit);
 332
 333                 hi = (hi & ~MASK_ERR_COUNT_HI) |
 334                     (new_count & THRESHOLD_MAX);
 335         }
 336
 337         /* clear IntType */
 338         hi &= ~MASK_INT_TYPE_HI;
 339
 340         if (!tr->b->interrupt_capable)
 341                 goto done;
 342
 343         if (tr->set_lvt_off) {
 344                 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
 345                         /* set new lvt offset */
 346                         hi &= ~MASK_LVTOFF_HI;
 347                         hi |= tr->lvt_off << 20;
 348                 }
 349         }
 350
 351         if (tr->b->interrupt_enable)
 352                 hi |= INT_TYPE_APIC;
 353
 354  done:
 355
 356         hi |= MASK_COUNT_EN_HI;
 357         wrmsr(tr->b->address, lo, hi);
 358 }
 359
 360 static void mce_threshold_block_init(struct threshold_block *b, int offset)
 361 {
 362         struct thresh_restart tr = {
 363                 .b                      = b,
 364                 .set_lvt_off            = 1,
 365                 .lvt_off                = offset,
 366         };
 367
 368         b->threshold_limit              = THRESHOLD_MAX;
 369         threshold_restart_bank(&tr);
 370 };
 371
 372 static int setup_APIC_mce_threshold(int reserved, int new)
 373 {
 374         if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
 375                                               APIC_EILVT_MSG_FIX, 0))
 376                 return new;
 377
 378         return reserved;
 379 }
 380
 381 static int setup_APIC_deferred_error(int reserved, int new)
 382 {
 383         if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,
 384                                               APIC_EILVT_MSG_FIX, 0))
 385                 return new;
 386
 387         return reserved;
 388 }
 389
 390 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 391 {
 392         u32 low = 0, high = 0;
 393         int def_offset = -1, def_new;
 394
 395         if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
 396                 return;
 397
 398         def_new = (low & MASK_DEF_LVTOFF) >> 4;
 399         if (!(low & MASK_DEF_LVTOFF)) {
 400                 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
 401                 def_new = DEF_LVT_OFF;
 402                 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
 403         }
 404
 405         def_offset = setup_APIC_deferred_error(def_offset, def_new);
 406         if ((def_offset == def_new) &&
 407             (deferred_error_int_vector != amd_deferred_error_interrupt))
 408                 deferred_error_int_vector = amd_deferred_error_interrupt;
 409
 410         low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
 411         wrmsr(MSR_CU_DEF_ERR, low, high);
 412 }
 413
 414 static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high,
 415                              unsigned int bank, unsigned int block)
 416 {
 417         u32 addr = 0, offset = 0;
 418
 419         if (mce_flags.smca) {
 420                 if (!block) {
 421                         addr = MSR_AMD64_SMCA_MCx_MISC(bank);
 422                 } else {
 423                         /*
 424                          * For SMCA enabled processors, BLKPTR field of the
 425                          * first MISC register (MCx_MISC0) indicates presence of
 426                          * additional MISC register set (MISC1-4).
 427                          */
 428                         u32 low, high;
 429
 430                         if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
 431                                 return addr;
 432
 433                         if (!(low & MCI_CONFIG_MCAX))
 434                                 return addr;
 435
 436                         if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
 437                             (low & MASK_BLKPTR_LO))
 438                                 addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
 439                 }
 440                 return addr;
 441         }
 442
 443         /* Fall back to method we used for older processors: */
 444         switch (block) {
 445         case 0:
 446                 addr = msr_ops.misc(bank);
 447                 break;
 448         case 1:
 449                 offset = ((low & MASK_BLKPTR_LO) >> 21);
 450                 if (offset)
 451                         addr = MCG_XBLK_ADDR + offset;
 452                 break;
 453         default:
 454                 addr = ++current_addr;
 455         }
 456         return addr;
 457 }
 458
 459 static int
 460 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 461                         int offset, u32 misc_high)
 462 {
 463         unsigned int cpu = smp_processor_id();
 464         u32 smca_low, smca_high;
 465         struct threshold_block b;
 466         int new;
 467
 468         if (!block)
 469                 per_cpu(bank_map, cpu) |= (1 << bank);
 470
 471         memset(&b, 0, sizeof(b));
 472         b.cpu                   = cpu;
 473         b.bank                  = bank;
 474         b.block                 = block;
 475         b.address               = addr;
 476         b.interrupt_capable     = lvt_interrupt_supported(bank, misc_high);
 477
 478         if (!b.interrupt_capable)
 479                 goto done;
 480
 481         b.interrupt_enable = 1;
 482
 483         if (!mce_flags.smca) {
 484                 new = (misc_high & MASK_LVTOFF_HI) >> 20;
 485                 goto set_offset;
 486         }
 487
 488         /* Gather LVT offset for thresholding: */
 489         if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
 490                 goto out;
 491
 492         new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
 493
 494 set_offset:
 495         offset = setup_APIC_mce_threshold(offset, new);
 496
 497         if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt))
 498                 mce_threshold_vector = amd_threshold_interrupt;
 499
 500 done:
 501         mce_threshold_block_init(&b, offset);
 502
 503 out:
 504         return offset;
 505 }
 506
 507 /* cpu init entry point, called from mce.c with preempt off */
 508 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 509 {
 510         u32 low = 0, high = 0, address = 0;
 511         unsigned int bank, block, cpu = smp_processor_id();
 512         int offset = -1;
 513
 514         for (bank = 0; bank < mca_cfg.banks; ++bank) {
 515                 if (mce_flags.smca)
 516                         smca_configure(bank, cpu);
 517
 518                 for (block = 0; block < NR_BLOCKS; ++block) {
 519                         address = get_block_address(cpu, address, low, high, bank, block);
 520                         if (!address)
 521                                 break;
 522
 523                         if (rdmsr_safe(address, &low, &high))
 524                                 break;
 525
 526                         if (!(high & MASK_VALID_HI))
 527                                 continue;
 528
 529                         if (!(high & MASK_CNTP_HI)  ||
 530                              (high & MASK_LOCKED_HI))
 531                                 continue;
 532
 533                         offset = prepare_threshold_block(bank, block, address, offset, high);
 534                 }
 535         }
 536
 537         if (mce_flags.succor)
 538                 deferred_error_interrupt_enable(c);
 539 }
 540
 541 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
 542 {
 543         u64 dram_base_addr, dram_limit_addr, dram_hole_base;
 544         /* We start from the normalized address */
 545         u64 ret_addr = norm_addr;
 546
 547         u32 tmp;
 548
 549         u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
 550         u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
 551         u8 intlv_addr_sel, intlv_addr_bit;
 552         u8 num_intlv_bits, hashed_bit;
 553         u8 lgcy_mmio_hole_en, base = 0;
 554         u8 cs_mask, cs_id = 0;
 555         bool hash_enabled = false;
 556
 557         /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
 558         if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
 559                 goto out_err;
 560
 561         /* Remove HiAddrOffset from normalized address, if enabled: */
 562         if (tmp & BIT(0)) {
 563                 u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
 564
 565                 if (norm_addr >= hi_addr_offset) {
 566                         ret_addr -= hi_addr_offset;
 567                         base = 1;
 568                 }
 569         }
 570
 571         /* Read D18F0x110 (DramBaseAddress). */
 572         if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp))
 573                 goto out_err;
 574
 575         /* Check if address range is valid. */
 576         if (!(tmp & BIT(0))) {
 577                 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
 578                         __func__, tmp);
 579                 goto out_err;
 580         }
 581
 582         lgcy_mmio_hole_en = tmp & BIT(1);
 583         intlv_num_chan    = (tmp >> 4) & 0xF;
 584         intlv_addr_sel    = (tmp >> 8) & 0x7;
 585         dram_base_addr    = (tmp & GENMASK_ULL(31, 12)) << 16;
 586
 587         /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
 588         if (intlv_addr_sel > 3) {
 589                 pr_err("%s: Invalid interleave address select %d.\n",
 590                         __func__, intlv_addr_sel);
 591                 goto out_err;
 592         }
 593
 594         /* Read D18F0x114 (DramLimitAddress). */
 595         if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
 596                 goto out_err;
 597
 598         intlv_num_sockets = (tmp >> 8) & 0x1;
 599         intlv_num_dies    = (tmp >> 10) & 0x3;
 600         dram_limit_addr   = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
 601
 602         intlv_addr_bit = intlv_addr_sel + 8;
 603
 604         /* Re-use intlv_num_chan by setting it equal to log2(#channels) */
 605         switch (intlv_num_chan) {
 606         case 0: intlv_num_chan = 0; break;
 607         case 1: intlv_num_chan = 1; break;
 608         case 3: intlv_num_chan = 2; break;
 609         case 5: intlv_num_chan = 3; break;
 610         case 7: intlv_num_chan = 4; break;
 611
 612         case 8: intlv_num_chan = 1;
 613                 hash_enabled = true;
 614                 break;
 615         default:
 616                 pr_err("%s: Invalid number of interleaved channels %d.\n",
 617                         __func__, intlv_num_chan);
 618                 goto out_err;
 619         }
 620
 621         num_intlv_bits = intlv_num_chan;
 622
 623         if (intlv_num_dies > 2) {
 624                 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
 625                         __func__, intlv_num_dies);
 626                 goto out_err;
 627         }
 628
 629         num_intlv_bits += intlv_num_dies;
 630
 631         /* Add a bit if sockets are interleaved. */
 632         num_intlv_bits += intlv_num_sockets;
 633
 634         /* Assert num_intlv_bits <= 4 */
 635         if (num_intlv_bits > 4) {
 636                 pr_err("%s: Invalid interleave bits %d.\n",
 637                         __func__, num_intlv_bits);
 638                 goto out_err;
 639         }
 640
 641         if (num_intlv_bits > 0) {
 642                 u64 temp_addr_x, temp_addr_i, temp_addr_y;
 643                 u8 die_id_bit, sock_id_bit, cs_fabric_id;
 644
 645                 /*
 646                  * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
 647                  * This is the fabric id for this coherent slave. Use
 648                  * umc/channel# as instance id of the coherent slave
 649                  * for FICAA.
 650                  */
 651                 if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
 652                         goto out_err;
 653
 654                 cs_fabric_id = (tmp >> 8) & 0xFF;
 655                 die_id_bit   = 0;
 656
 657                 /* If interleaved over more than 1 channel: */
 658                 if (intlv_num_chan) {
 659                         die_id_bit = intlv_num_chan;
 660                         cs_mask    = (1 << die_id_bit) - 1;
 661                         cs_id      = cs_fabric_id & cs_mask;
 662                 }
 663
 664                 sock_id_bit = die_id_bit;
 665
 666                 /* Read D18F1x208 (SystemFabricIdMask). */
 667                 if (intlv_num_dies || intlv_num_sockets)
 668                         if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp))
 669                                 goto out_err;
 670
 671                 /* If interleaved over more than 1 die. */
 672                 if (intlv_num_dies) {
 673                         sock_id_bit  = die_id_bit + intlv_num_dies;
 674                         die_id_shift = (tmp >> 24) & 0xF;
 675                         die_id_mask  = (tmp >> 8) & 0xFF;
 676
 677                         cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
 678                 }
 679
 680                 /* If interleaved over more than 1 socket. */
 681                 if (intlv_num_sockets) {
 682                         socket_id_shift = (tmp >> 28) & 0xF;
 683                         socket_id_mask  = (tmp >> 16) & 0xFF;
 684
 685                         cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
 686                 }
 687
 688                 /*
 689                  * The pre-interleaved address consists of XXXXXXIIIYYYYY
 690                  * where III is the ID for this CS, and XXXXXXYYYYY are the
 691                  * address bits from the post-interleaved address.
 692                  * "num_intlv_bits" has been calculated to tell us how many "I"
 693                  * bits there are. "intlv_addr_bit" tells us how many "Y" bits
 694                  * there are (where "I" starts).
 695                  */
 696                 temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0);
 697                 temp_addr_i = (cs_id << intlv_addr_bit);
 698                 temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
 699                 ret_addr    = temp_addr_x | temp_addr_i | temp_addr_y;
 700         }
 701
 702         /* Add dram base address */
 703         ret_addr += dram_base_addr;
 704
 705         /* If legacy MMIO hole enabled */
 706         if (lgcy_mmio_hole_en) {
 707                 if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp))
 708                         goto out_err;
 709
 710                 dram_hole_base = tmp & GENMASK(31, 24);
 711                 if (ret_addr >= dram_hole_base)
 712                         ret_addr += (BIT_ULL(32) - dram_hole_base);
 713         }
 714
 715         if (hash_enabled) {
 716                 /* Save some parentheses and grab ls-bit at the end. */
 717                 hashed_bit =    (ret_addr >> 12) ^
 718                                 (ret_addr >> 18) ^
 719                                 (ret_addr >> 21) ^
 720                                 (ret_addr >> 30) ^
 721                                 cs_id;
 722
 723                 hashed_bit &= BIT(0);
 724
 725                 if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0)))
 726                         ret_addr ^= BIT(intlv_addr_bit);
 727         }
 728
 729         /* Is calculated system address is above DRAM limit address? */
 730         if (ret_addr > dram_limit_addr)
 731                 goto out_err;
 732
 733         *sys_addr = ret_addr;
 734         return 0;
 735
 736 out_err:
 737         return -EINVAL;
 738 }
 739 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr);
 740
 741 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
 742 {
 743         struct mce m;
 744
 745         mce_setup(&m);
 746
 747         m.status = status;
 748         m.misc   = misc;
 749         m.bank   = bank;
 750         m.tsc    = rdtsc();
 751
 752         if (m.status & MCI_STATUS_ADDRV) {
 753                 m.addr = addr;
 754
 755                 /*
 756                  * Extract [55:<lsb>] where lsb is the least significant
 757                  * *valid* bit of the address bits.
 758                  */
 759                 if (mce_flags.smca) {
 760                         u8 lsb = (m.addr >> 56) & 0x3f;
 761
 762                         m.addr &= GENMASK_ULL(55, lsb);
 763                 }
 764         }
 765
 766         if (mce_flags.smca) {
 767                 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);
 768
 769                 if (m.status & MCI_STATUS_SYNDV)
 770                         rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);
 771         }
 772
 773         mce_log(&m);
 774 }
 775
 776 asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(void)
 777 {
 778         entering_irq();
 779         trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
 780         inc_irq_stat(irq_deferred_error_count);
 781         deferred_error_int_vector();
 782         trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
 783         exiting_ack_irq();
 784 }
 785
 786 /*
 787  * Returns true if the logged error is deferred. False, otherwise.
 788  */
 789 static inline bool
 790 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
 791 {
 792         u64 status, addr = 0;
 793
 794         rdmsrl(msr_stat, status);
 795         if (!(status & MCI_STATUS_VAL))
 796                 return false;
 797
 798         if (status & MCI_STATUS_ADDRV)
 799                 rdmsrl(msr_addr, addr);
 800
 801         __log_error(bank, status, addr, misc);
 802
 803         wrmsrl(msr_stat, 0);
 804
 805         return status & MCI_STATUS_DEFERRED;
 806 }
 807
 808 /*
 809  * We have three scenarios for checking for Deferred errors:
 810  *
 811  * 1) Non-SMCA systems check MCA_STATUS and log error if found.
 812  * 2) SMCA systems check MCA_STATUS. If error is found then log it and also
 813  *    clear MCA_DESTAT.
 814  * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
 815  *    log it.
 816  */
 817 static void log_error_deferred(unsigned int bank)
 818 {
 819         bool defrd;
 820
 821         defrd = _log_error_bank(bank, msr_ops.status(bank),
 822                                         msr_ops.addr(bank), 0);
 823
 824         if (!mce_flags.smca)
 825                 return;
 826
 827         /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */
 828         if (defrd) {
 829                 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
 830                 return;
 831         }
 832
 833         /*
 834          * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
 835          * for a valid error.
 836          */
 837         _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),
 838                               MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);
 839 }
 840
 841 /* APIC interrupt handler for deferred errors */
 842 static void amd_deferred_error_interrupt(void)
 843 {
 844         unsigned int bank;
 845
 846         for (bank = 0; bank < mca_cfg.banks; ++bank)
 847                 log_error_deferred(bank);
 848 }
 849
 850 static void log_error_thresholding(unsigned int bank, u64 misc)
 851 {
 852         _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc);
 853 }
 854
 855 static void log_and_reset_block(struct threshold_block *block)
 856 {
 857         struct thresh_restart tr;
 858         u32 low = 0, high = 0;
 859
 860         if (!block)
 861                 return;
 862
 863         if (rdmsr_safe(block->address, &low, &high))
 864                 return;
 865
 866         if (!(high & MASK_OVERFLOW_HI))
 867                 return;
 868
 869         /* Log the MCE which caused the threshold event. */
 870         log_error_thresholding(block->bank, ((u64)high << 32) | low);
 871
 872         /* Reset threshold block after logging error. */
 873         memset(&tr, 0, sizeof(tr));
 874         tr.b = block;
 875         threshold_restart_bank(&tr);
 876 }
 877
 878 /*
 879  * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
 880  * goes off when error_count reaches threshold_limit.
 881  */
 882 static void amd_threshold_interrupt(void)
 883 {
 884         struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL;
 885         unsigned int bank, cpu = smp_processor_id();
 886
 887         for (bank = 0; bank < mca_cfg.banks; ++bank) {
 888                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
 889                         continue;
 890
 891                 first_block = per_cpu(threshold_banks, cpu)[bank]->blocks;
 892                 if (!first_block)
 893                         continue;
 894
 895                 /*
 896                  * The first block is also the head of the list. Check it first
 897                  * before iterating over the rest.
 898                  */
 899                 log_and_reset_block(first_block);
 900                 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj)
 901                         log_and_reset_block(block);
 902         }
 903 }
 904
 905 /*
 906  * Sysfs Interface
 907  */
 908
 909 struct threshold_attr {
 910         struct attribute attr;
 911         ssize_t (*show) (struct threshold_block *, char *);
 912         ssize_t (*store) (struct threshold_block *, const char *, size_t count);
 913 };
 914
 915 #define SHOW_FIELDS(name)                                               \
 916 static ssize_t show_ ## name(struct threshold_block *b, char *buf)      \
 917 {                                                                       \
 918         return sprintf(buf, "%lu\n", (unsigned long) b->name);          \
 919 }
 920 SHOW_FIELDS(interrupt_enable)
 921 SHOW_FIELDS(threshold_limit)
 922
 923 static ssize_t
 924 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
 925 {
 926         struct thresh_restart tr;
 927         unsigned long new;
 928
 929         if (!b->interrupt_capable)
 930                 return -EINVAL;
 931
 932         if (kstrtoul(buf, 0, &new) < 0)
 933                 return -EINVAL;
 934
 935         b->interrupt_enable = !!new;
 936
 937         memset(&tr, 0, sizeof(tr));
 938         tr.b            = b;
 939
 940         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 941
 942         return size;
 943 }
 944
 945 static ssize_t
 946 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
 947 {
 948         struct thresh_restart tr;
 949         unsigned long new;
 950
 951         if (kstrtoul(buf, 0, &new) < 0)
 952                 return -EINVAL;
 953
 954         if (new > THRESHOLD_MAX)
 955                 new = THRESHOLD_MAX;
 956         if (new < 1)
 957                 new = 1;
 958
 959         memset(&tr, 0, sizeof(tr));
 960         tr.old_limit = b->threshold_limit;
 961         b->threshold_limit = new;
 962         tr.b = b;
 963
 964         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 965
 966         return size;
 967 }
 968
 969 static ssize_t show_error_count(struct threshold_block *b, char *buf)
 970 {
 971         u32 lo, hi;
 972
 973         rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
 974
 975         return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
 976                                      (THRESHOLD_MAX - b->threshold_limit)));
 977 }
 978
 979 static struct threshold_attr error_count = {
 980         .attr = {.name = __stringify(error_count), .mode = 0444 },
 981         .show = show_error_count,
 982 };
 983
 984 #define RW_ATTR(val)                                                    \
 985 static struct threshold_attr val = {                                    \
 986         .attr   = {.name = __stringify(val), .mode = 0644 },            \
 987         .show   = show_## val,                                          \
 988         .store  = store_## val,                                         \
 989 };
 990
 991 RW_ATTR(interrupt_enable);
 992 RW_ATTR(threshold_limit);
 993
 994 static struct attribute *default_attrs[] = {
 995         &threshold_limit.attr,
 996         &error_count.attr,
 997         NULL,   /* possibly interrupt_enable if supported, see below */
 998         NULL,
 999 };
1000
1001 #define to_block(k)     container_of(k, struct threshold_block, kobj)
1002 #define to_attr(a)      container_of(a, struct threshold_attr, attr)
1003
1004 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1005 {
1006         struct threshold_block *b = to_block(kobj);
1007         struct threshold_attr *a = to_attr(attr);
1008         ssize_t ret;
1009
1010         ret = a->show ? a->show(b, buf) : -EIO;
1011
1012         return ret;
1013 }
1014
1015 static ssize_t store(struct kobject *kobj, struct attribute *attr,
1016                      const char *buf, size_t count)
1017 {
1018         struct threshold_block *b = to_block(kobj);
1019         struct threshold_attr *a = to_attr(attr);
1020         ssize_t ret;
1021
1022         ret = a->store ? a->store(b, buf, count) : -EIO;
1023
1024         return ret;
1025 }
1026
1027 static const struct sysfs_ops threshold_ops = {
1028         .show                   = show,
1029         .store                  = store,
1030 };
1031
1032 static struct kobj_type threshold_ktype = {
1033         .sysfs_ops              = &threshold_ops,
1034         .default_attrs          = default_attrs,
1035 };
1036
1037 static const char *get_name(unsigned int bank, struct threshold_block *b)
1038 {
1039         unsigned int bank_type;
1040
1041         if (!mce_flags.smca) {
1042                 if (b && bank == 4)
1043                         return bank4_names(b);
1044
1045                 return th_names[bank];
1046         }
1047
1048         if (!smca_banks[bank].hwid)
1049                 return NULL;
1050
1051         bank_type = smca_banks[bank].hwid->bank_type;
1052
1053         if (b && bank_type == SMCA_UMC) {
1054                 if (b->block < ARRAY_SIZE(smca_umc_block_names))
1055                         return smca_umc_block_names[b->block];
1056                 return NULL;
1057         }
1058
1059         if (smca_banks[bank].hwid->count == 1)
1060                 return smca_get_name(bank_type);
1061
1062         snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
1063                  "%s_%x", smca_get_name(bank_type),
1064                           smca_banks[bank].sysfs_id);
1065         return buf_mcatype;
1066 }
1067
1068 static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
1069                                      unsigned int block, u32 address)
1070 {
1071         struct threshold_block *b = NULL;
1072         u32 low, high;
1073         int err;
1074
1075         if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
1076                 return 0;
1077
1078         if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
1079                 return 0;
1080
1081         if (!(high & MASK_VALID_HI)) {
1082                 if (block)
1083                         goto recurse;
1084                 else
1085                         return 0;
1086         }
1087
1088         if (!(high & MASK_CNTP_HI)  ||
1089              (high & MASK_LOCKED_HI))
1090                 goto recurse;
1091
1092         b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
1093         if (!b)
1094                 return -ENOMEM;
1095
1096         b->block                = block;
1097         b->bank                 = bank;
1098         b->cpu                  = cpu;
1099         b->address              = address;
1100         b->interrupt_enable     = 0;
1101         b->interrupt_capable    = lvt_interrupt_supported(bank, high);
1102         b->threshold_limit      = THRESHOLD_MAX;
1103
1104         if (b->interrupt_capable) {
1105                 threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
1106                 b->interrupt_enable = 1;
1107         } else {
1108                 threshold_ktype.default_attrs[2] = NULL;
1109         }
1110
1111         INIT_LIST_HEAD(&b->miscj);
1112
1113         if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
1114                 list_add(&b->miscj,
1115                          &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
1116         } else {
1117                 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
1118         }
1119
1120         err = kobject_init_and_add(&b->kobj, &threshold_ktype,
1121                                    per_cpu(threshold_banks, cpu)[bank]->kobj,
1122                                    get_name(bank, b));
1123         if (err)
1124                 goto out_free;
1125 recurse:
1126         address = get_block_address(cpu, address, low, high, bank, ++block);
1127         if (!address)
1128                 return 0;
1129
1130         err = allocate_threshold_blocks(cpu, bank, block, address);
1131         if (err)
1132                 goto out_free;
1133
1134         if (b)
1135                 kobject_uevent(&b->kobj, KOBJ_ADD);
1136
1137         return err;
1138
1139 out_free:
1140         if (b) {
1141                 kobject_put(&b->kobj);
1142                 list_del(&b->miscj);
1143                 kfree(b);
1144         }
1145         return err;
1146 }
1147
1148 static int __threshold_add_blocks(struct threshold_bank *b)
1149 {
1150         struct list_head *head = &b->blocks->miscj;
1151         struct threshold_block *pos = NULL;
1152         struct threshold_block *tmp = NULL;
1153         int err = 0;
1154
1155         err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
1156         if (err)
1157                 return err;
1158
1159         list_for_each_entry_safe(pos, tmp, head, miscj) {
1160
1161                 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
1162                 if (err) {
1163                         list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
1164                                 kobject_del(&pos->kobj);
1165
1166                         return err;
1167                 }
1168         }
1169         return err;
1170 }
1171
1172 static int threshold_create_bank(unsigned int cpu, unsigned int bank)
1173 {
1174         struct device *dev = per_cpu(mce_device, cpu);
1175         struct amd_northbridge *nb = NULL;
1176         struct threshold_bank *b = NULL;
1177         const char *name = get_name(bank, NULL);
1178         int err = 0;
1179
1180         if (!dev)
1181                 return -ENODEV;
1182
1183         if (is_shared_bank(bank)) {
1184                 nb = node_to_amd_nb(amd_get_nb_id(cpu));
1185
1186                 /* threshold descriptor already initialized on this node? */
1187                 if (nb && nb->bank4) {
1188                         /* yes, use it */
1189                         b = nb->bank4;
1190                         err = kobject_add(b->kobj, &dev->kobj, name);
1191                         if (err)
1192                                 goto out;
1193
1194                         per_cpu(threshold_banks, cpu)[bank] = b;
1195                         refcount_inc(&b->cpus);
1196
1197                         err = __threshold_add_blocks(b);
1198
1199                         goto out;
1200                 }
1201         }
1202
1203         b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
1204         if (!b) {
1205                 err = -ENOMEM;
1206                 goto out;
1207         }
1208
1209         b->kobj = kobject_create_and_add(name, &dev->kobj);
1210         if (!b->kobj) {
1211                 err = -EINVAL;
1212                 goto out_free;
1213         }
1214
1215         per_cpu(threshold_banks, cpu)[bank] = b;
1216
1217         if (is_shared_bank(bank)) {
1218                 refcount_set(&b->cpus, 1);
1219
1220                 /* nb is already initialized, see above */
1221                 if (nb) {
1222                         WARN_ON(nb->bank4);
1223                         nb->bank4 = b;
1224                 }
1225         }
1226
1227         err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank));
1228         if (!err)
1229                 goto out;
1230
1231  out_free:
1232         kfree(b);
1233
1234  out:
1235         return err;
1236 }
1237
1238 static void deallocate_threshold_block(unsigned int cpu,
1239                                                  unsigned int bank)
1240 {
1241         struct threshold_block *pos = NULL;
1242         struct threshold_block *tmp = NULL;
1243         struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
1244
1245         if (!head)
1246                 return;
1247
1248         list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
1249                 kobject_put(&pos->kobj);
1250                 list_del(&pos->miscj);
1251                 kfree(pos);
1252         }
1253
1254         kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
1255         per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
1256 }
1257
1258 static void __threshold_remove_blocks(struct threshold_bank *b)
1259 {
1260         struct threshold_block *pos = NULL;
1261         struct threshold_block *tmp = NULL;
1262
1263         kobject_del(b->kobj);
1264
1265         list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
1266                 kobject_del(&pos->kobj);
1267 }
1268
1269 static void threshold_remove_bank(unsigned int cpu, int bank)
1270 {
1271         struct amd_northbridge *nb;
1272         struct threshold_bank *b;
1273
1274         b = per_cpu(threshold_banks, cpu)[bank];
1275         if (!b)
1276                 return;
1277
1278         if (!b->blocks)
1279                 goto free_out;
1280
1281         if (is_shared_bank(bank)) {
1282                 if (!refcount_dec_and_test(&b->cpus)) {
1283                         __threshold_remove_blocks(b);
1284                         per_cpu(threshold_banks, cpu)[bank] = NULL;
1285                         return;
1286                 } else {
1287                         /*
1288                          * the last CPU on this node using the shared bank is
1289                          * going away, remove that bank now.
1290                          */
1291                         nb = node_to_amd_nb(amd_get_nb_id(cpu));
1292                         nb->bank4 = NULL;
1293                 }
1294         }
1295
1296         deallocate_threshold_block(cpu, bank);
1297
1298 free_out:
1299         kobject_del(b->kobj);
1300         kobject_put(b->kobj);
1301         kfree(b);
1302         per_cpu(threshold_banks, cpu)[bank] = NULL;
1303 }
1304
1305 int mce_threshold_remove_device(unsigned int cpu)
1306 {
1307         unsigned int bank;
1308
1309         if (!thresholding_en)
1310                 return 0;
1311
1312         for (bank = 0; bank < mca_cfg.banks; ++bank) {
1313                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1314                         continue;
1315                 threshold_remove_bank(cpu, bank);
1316         }
1317         kfree(per_cpu(threshold_banks, cpu));
1318         per_cpu(threshold_banks, cpu) = NULL;
1319         return 0;
1320 }
1321
1322 /* create dir/files for all valid threshold banks */
1323 int mce_threshold_create_device(unsigned int cpu)
1324 {
1325         unsigned int bank;
1326         struct threshold_bank **bp;
1327         int err = 0;
1328
1329         if (!thresholding_en)
1330                 return 0;
1331
1332         bp = per_cpu(threshold_banks, cpu);
1333         if (bp)
1334                 return 0;
1335
1336         bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks,
1337                      GFP_KERNEL);
1338         if (!bp)
1339                 return -ENOMEM;
1340
1341         per_cpu(threshold_banks, cpu) = bp;
1342
1343         for (bank = 0; bank < mca_cfg.banks; ++bank) {
1344                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1345                         continue;
1346                 err = threshold_create_bank(cpu, bank);
1347                 if (err)
1348                         goto err;
1349         }
1350         return err;
1351 err:
1352         mce_threshold_remove_device(cpu);
1353         return err;
1354 }
1355
1356 static __init int threshold_init_device(void)
1357 {
1358         unsigned lcpu = 0;
1359
1360         if (mce_threshold_vector == amd_threshold_interrupt)
1361                 thresholding_en = true;
1362
1363         /* to hit CPUs online before the notifier is up */
1364         for_each_online_cpu(lcpu) {
1365                 int err = mce_threshold_create_device(lcpu);
1366
1367                 if (err)
1368                         return err;
1369         }
1370
1371         return 0;
1372 }
1373 /*
1374  * there are 3 funcs which need to be _initcalled in a logic sequence:
1375  * 1. xen_late_init_mcelog
1376  * 2. mcheck_init_device
1377  * 3. threshold_init_device
1378  *
1379  * xen_late_init_mcelog must register xen_mce_chrdev_device before
1380  * native mce_chrdev_device registration if running under xen platform;
1381  *
1382  * mcheck_init_device should be inited before threshold_init_device to
1383  * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
1384  *
1385  * so we use following _initcalls
1386  * 1. device_initcall(xen_late_init_mcelog);
1387  * 2. device_initcall_sync(mcheck_init_device);
1388  * 3. late_initcall(threshold_init_device);
1389  *
1390  * when running under xen, the initcall order is 1,2,3;
1391  * on baremetal, we skip 1 and we do only 2 and 3.
1392  */
1393 late_initcall(threshold_init_device);