2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/thread_info.h>
14 #include <linux/capability.h>
15 #include <linux/miscdevice.h>
16 #include <linux/ratelimit.h>
17 #include <linux/kallsyms.h>
18 #include <linux/rcupdate.h>
19 #include <linux/kobject.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kernel.h>
23 #include <linux/percpu.h>
24 #include <linux/string.h>
25 #include <linux/device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/delay.h>
28 #include <linux/ctype.h>
29 #include <linux/sched.h>
30 #include <linux/sysfs.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/kmod.h>
35 #include <linux/poll.h>
36 #include <linux/nmi.h>
37 #include <linux/cpu.h>
38 #include <linux/ras.h>
39 #include <linux/smp.h>
42 #include <linux/debugfs.h>
43 #include <linux/irq_work.h>
44 #include <linux/export.h>
45 #include <linux/jump_label.h>
47 #include <asm/intel-family.h>
48 #include <asm/processor.h>
49 #include <asm/traps.h>
50 #include <asm/tlbflush.h>
53 #include <asm/reboot.h>
54 #include <asm/set_memory.h>
56 #include "mce-internal.h"
58 static DEFINE_MUTEX(mce_log_mutex);
60 #define CREATE_TRACE_POINTS
61 #include <trace/events/mce.h>
63 #define SPINUNIT 100 /* 100ns */
65 DEFINE_PER_CPU(unsigned, mce_exception_count);
67 struct mce_bank *mce_banks __read_mostly;
68 struct mce_vendor_flags mce_flags __read_mostly;
70 struct mca_config mca_cfg __read_mostly = {
74 * 0: always panic on uncorrected errors, log corrected errors
75 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
76 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
77 * 3: never panic or SIGBUS, log all errors (for testing only)
83 static DEFINE_PER_CPU(struct mce, mces_seen);
84 static unsigned long mce_need_notify;
85 static int cpu_missing;
88 * MCA banks polled by the period polling timer for corrected events.
89 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
91 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
92 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
96 * MCA banks controlled through firmware first for corrected errors.
97 * This is a global list of banks for which we won't enable CMCI and we
98 * won't poll. Firmware controls these banks and is responsible for
99 * reporting corrected errors through GHES. Uncorrected/recoverable
100 * errors are still notified through a machine check.
102 mce_banks_t mce_banks_ce_disabled;
104 static struct work_struct mce_work;
105 static struct irq_work mce_irq_work;
107 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
110 * CPU/chipset specific EDAC code can register a notifier call here to print
111 * MCE errors in a human-readable form.
113 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
115 /* Do initial initialization of a struct mce */
116 void mce_setup(struct mce *m)
118 memset(m, 0, sizeof(struct mce));
119 m->cpu = m->extcpu = smp_processor_id();
120 /* We hope get_seconds stays lockless */
121 m->time = get_seconds();
122 m->cpuvendor = boot_cpu_data.x86_vendor;
123 m->cpuid = cpuid_eax(1);
124 m->socketid = cpu_data(m->extcpu).phys_proc_id;
125 m->apicid = cpu_data(m->extcpu).initial_apicid;
126 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
128 if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
129 rdmsrl(MSR_PPIN, m->ppin);
132 DEFINE_PER_CPU(struct mce, injectm);
133 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
135 void mce_log(struct mce *m)
137 if (!mce_gen_pool_add(m))
138 irq_work_queue(&mce_irq_work);
141 void mce_inject_log(struct mce *m)
143 mutex_lock(&mce_log_mutex);
145 mutex_unlock(&mce_log_mutex);
147 EXPORT_SYMBOL_GPL(mce_inject_log);
149 static struct notifier_block mce_srao_nb;
152 * We run the default notifier if we have only the SRAO, the first and the
153 * default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS
154 * notifiers registered on the chain.
156 #define NUM_DEFAULT_NOTIFIERS 3
157 static atomic_t num_notifiers;
159 void mce_register_decode_chain(struct notifier_block *nb)
161 if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC))
164 atomic_inc(&num_notifiers);
166 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
168 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
170 void mce_unregister_decode_chain(struct notifier_block *nb)
172 atomic_dec(&num_notifiers);
174 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
176 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
178 static inline u32 ctl_reg(int bank)
180 return MSR_IA32_MCx_CTL(bank);
183 static inline u32 status_reg(int bank)
185 return MSR_IA32_MCx_STATUS(bank);
188 static inline u32 addr_reg(int bank)
190 return MSR_IA32_MCx_ADDR(bank);
193 static inline u32 misc_reg(int bank)
195 return MSR_IA32_MCx_MISC(bank);
198 static inline u32 smca_ctl_reg(int bank)
200 return MSR_AMD64_SMCA_MCx_CTL(bank);
203 static inline u32 smca_status_reg(int bank)
205 return MSR_AMD64_SMCA_MCx_STATUS(bank);
208 static inline u32 smca_addr_reg(int bank)
210 return MSR_AMD64_SMCA_MCx_ADDR(bank);
213 static inline u32 smca_misc_reg(int bank)
215 return MSR_AMD64_SMCA_MCx_MISC(bank);
218 struct mca_msr_regs msr_ops = {
220 .status = status_reg,
225 static void __print_mce(struct mce *m)
227 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
229 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
230 m->mcgstatus, m->bank, m->status);
233 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
234 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
237 if (m->cs == __KERNEL_CS)
238 print_symbol("{%s}", m->ip);
242 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
244 pr_cont("ADDR %llx ", m->addr);
246 pr_cont("MISC %llx ", m->misc);
248 if (mce_flags.smca) {
250 pr_cont("SYND %llx ", m->synd);
252 pr_cont("IPID %llx ", m->ipid);
257 * Note this output is parsed by external tools and old fields
258 * should not be changed.
260 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
261 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
262 cpu_data(m->extcpu).microcode);
265 static void print_mce(struct mce *m)
268 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
271 #define PANIC_TIMEOUT 5 /* 5 seconds */
273 static atomic_t mce_panicked;
275 static int fake_panic;
276 static atomic_t mce_fake_panicked;
278 /* Panic in progress. Enable interrupts and wait for final IPI */
279 static void wait_for_panic(void)
281 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
285 while (timeout-- > 0)
287 if (panic_timeout == 0)
288 panic_timeout = mca_cfg.panic_timeout;
289 panic("Panicing machine check CPU died");
292 static void mce_panic(const char *msg, struct mce *final, char *exp)
295 struct llist_node *pending;
296 struct mce_evt_llist *l;
300 * Make sure only one CPU runs in machine check panic
302 if (atomic_inc_return(&mce_panicked) > 1)
309 /* Don't log too much for fake panic */
310 if (atomic_inc_return(&mce_fake_panicked) > 1)
313 pending = mce_gen_pool_prepare_records();
314 /* First print corrected ones that are still unlogged */
315 llist_for_each_entry(l, pending, llnode) {
316 struct mce *m = &l->mce;
317 if (!(m->status & MCI_STATUS_UC)) {
320 apei_err = apei_write_mce(m);
323 /* Now print uncorrected but with the final one last */
324 llist_for_each_entry(l, pending, llnode) {
325 struct mce *m = &l->mce;
326 if (!(m->status & MCI_STATUS_UC))
328 if (!final || mce_cmp(m, final)) {
331 apei_err = apei_write_mce(m);
337 apei_err = apei_write_mce(final);
340 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
342 pr_emerg(HW_ERR "Machine check: %s\n", exp);
344 if (panic_timeout == 0)
345 panic_timeout = mca_cfg.panic_timeout;
348 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
351 /* Support code for software error injection */
353 static int msr_to_offset(u32 msr)
355 unsigned bank = __this_cpu_read(injectm.bank);
357 if (msr == mca_cfg.rip_msr)
358 return offsetof(struct mce, ip);
359 if (msr == msr_ops.status(bank))
360 return offsetof(struct mce, status);
361 if (msr == msr_ops.addr(bank))
362 return offsetof(struct mce, addr);
363 if (msr == msr_ops.misc(bank))
364 return offsetof(struct mce, misc);
365 if (msr == MSR_IA32_MCG_STATUS)
366 return offsetof(struct mce, mcgstatus);
370 /* MSR access wrappers used for error injection */
371 static u64 mce_rdmsrl(u32 msr)
375 if (__this_cpu_read(injectm.finished)) {
376 int offset = msr_to_offset(msr);
380 return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
383 if (rdmsrl_safe(msr, &v)) {
384 WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr);
386 * Return zero in case the access faulted. This should
387 * not happen normally but can happen if the CPU does
388 * something weird, or if the code is buggy.
396 static void mce_wrmsrl(u32 msr, u64 v)
398 if (__this_cpu_read(injectm.finished)) {
399 int offset = msr_to_offset(msr);
402 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
409 * Collect all global (w.r.t. this processor) status about this machine
410 * check into our "mce" struct so that we can use it later to assess
411 * the severity of the problem as we read per-bank specific details.
413 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
417 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
420 * Get the address of the instruction at the time of
421 * the machine check error.
423 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
428 * When in VM86 mode make the cs look like ring 3
429 * always. This is a lie, but it's better than passing
430 * the additional vm86 bit around everywhere.
432 if (v8086_mode(regs))
435 /* Use accurate RIP reporting if available. */
437 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
441 int mce_available(struct cpuinfo_x86 *c)
443 if (mca_cfg.disabled)
445 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
448 static void mce_schedule_work(void)
450 if (!mce_gen_pool_empty())
451 schedule_work(&mce_work);
454 static void mce_irq_work_cb(struct irq_work *entry)
459 static void mce_report_event(struct pt_regs *regs)
461 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
464 * Triggering the work queue here is just an insurance
465 * policy in case the syscall exit notify handler
466 * doesn't run soon enough or ends up running on the
467 * wrong CPU (can happen when audit sleeps)
473 irq_work_queue(&mce_irq_work);
477 * Check if the address reported by the CPU is in a format we can parse.
478 * It would be possible to add code for most other cases, but all would
479 * be somewhat complicated (e.g. segment offset would require an instruction
480 * parser). So only support physical addresses up to page granuality for now.
482 static int mce_usable_address(struct mce *m)
484 if (!(m->status & MCI_STATUS_ADDRV))
487 /* Checks after this one are Intel-specific: */
488 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
491 if (!(m->status & MCI_STATUS_MISCV))
494 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
497 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
503 bool mce_is_memory_error(struct mce *m)
505 if (m->cpuvendor == X86_VENDOR_AMD) {
506 /* ErrCodeExt[20:16] */
507 u8 xec = (m->status >> 16) & 0x1f;
509 return (xec == 0x0 || xec == 0x8);
510 } else if (m->cpuvendor == X86_VENDOR_INTEL) {
512 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
514 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
515 * indicating a memory error. Bit 8 is used for indicating a
516 * cache hierarchy error. The combination of bit 2 and bit 3
517 * is used for indicating a `generic' cache hierarchy error
518 * But we can't just blindly check the above bits, because if
519 * bit 11 is set, then it is a bus/interconnect error - and
520 * either way the above bits just gives more detail on what
521 * bus/interconnect error happened. Note that bit 12 can be
522 * ignored, as it's the "filter" bit.
524 return (m->status & 0xef80) == BIT(7) ||
525 (m->status & 0xef00) == BIT(8) ||
526 (m->status & 0xeffc) == 0xc;
531 EXPORT_SYMBOL_GPL(mce_is_memory_error);
533 static bool cec_add_mce(struct mce *m)
538 /* We eat only correctable DRAM errors with usable addresses. */
539 if (mce_is_memory_error(m) &&
540 !(m->status & MCI_STATUS_UC) &&
541 mce_usable_address(m))
542 if (!cec_add_elem(m->addr >> PAGE_SHIFT))
548 static int mce_first_notifier(struct notifier_block *nb, unsigned long val,
551 struct mce *m = (struct mce *)data;
559 /* Emit the trace record: */
562 set_bit(0, &mce_need_notify);
569 static struct notifier_block first_nb = {
570 .notifier_call = mce_first_notifier,
571 .priority = MCE_PRIO_FIRST,
574 static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
577 struct mce *mce = (struct mce *)data;
583 if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) {
584 pfn = mce->addr >> PAGE_SHIFT;
585 memory_failure(pfn, MCE_VECTOR, 0);
590 static struct notifier_block mce_srao_nb = {
591 .notifier_call = srao_decode_notifier,
592 .priority = MCE_PRIO_SRAO,
595 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
598 struct mce *m = (struct mce *)data;
603 if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS)
611 static struct notifier_block mce_default_nb = {
612 .notifier_call = mce_default_notifier,
613 /* lowest prio, we want it to run last. */
614 .priority = MCE_PRIO_LOWEST,
618 * Read ADDR and MISC registers.
620 static void mce_read_aux(struct mce *m, int i)
622 if (m->status & MCI_STATUS_MISCV)
623 m->misc = mce_rdmsrl(msr_ops.misc(i));
625 if (m->status & MCI_STATUS_ADDRV) {
626 m->addr = mce_rdmsrl(msr_ops.addr(i));
629 * Mask the reported address by the reported granularity.
631 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
632 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
638 * Extract [55:<lsb>] where lsb is the least significant
639 * *valid* bit of the address bits.
641 if (mce_flags.smca) {
642 u8 lsb = (m->addr >> 56) & 0x3f;
644 m->addr &= GENMASK_ULL(55, lsb);
648 if (mce_flags.smca) {
649 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
651 if (m->status & MCI_STATUS_SYNDV)
652 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
656 DEFINE_PER_CPU(unsigned, mce_poll_count);
659 * Poll for corrected events or events that happened before reset.
660 * Those are just logged through /dev/mcelog.
662 * This is executed in standard interrupt context.
664 * Note: spec recommends to panic for fatal unsignalled
665 * errors here. However this would be quite problematic --
666 * we would need to reimplement the Monarch handling and
667 * it would mess up the exclusion between exception handler
668 * and poll hander -- * so we skip this for now.
669 * These cases should not happen anyways, or only when the CPU
670 * is already totally * confused. In this case it's likely it will
671 * not fully execute the machine check handler either.
673 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
675 bool error_seen = false;
679 this_cpu_inc(mce_poll_count);
681 mce_gather_info(&m, NULL);
683 if (flags & MCP_TIMESTAMP)
686 for (i = 0; i < mca_cfg.banks; i++) {
687 if (!mce_banks[i].ctl || !test_bit(i, *b))
695 m.status = mce_rdmsrl(msr_ops.status(i));
696 if (!(m.status & MCI_STATUS_VAL))
700 * Uncorrected or signalled events are handled by the exception
701 * handler when it is enabled, so don't process those here.
703 * TBD do the same check for MCI_STATUS_EN here?
705 if (!(flags & MCP_UC) &&
706 (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC)))
713 m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
716 * Don't get the IP here because it's unlikely to
717 * have anything to do with the actual error location.
719 if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce)
721 else if (mce_usable_address(&m)) {
723 * Although we skipped logging this, we still want
724 * to take action. Add to the pool so the registered
725 * notifiers will see it.
727 if (!mce_gen_pool_add(&m))
732 * Clear state for this bank.
734 mce_wrmsrl(msr_ops.status(i), 0);
738 * Don't clear MCG_STATUS here because it's only defined for
746 EXPORT_SYMBOL_GPL(machine_check_poll);
749 * Do a quick check if any of the events requires a panic.
750 * This decides if we keep the events around or clear them.
752 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
753 struct pt_regs *regs)
758 for (i = 0; i < mca_cfg.banks; i++) {
759 m->status = mce_rdmsrl(msr_ops.status(i));
760 if (m->status & MCI_STATUS_VAL) {
761 __set_bit(i, validp);
762 if (quirk_no_way_out)
763 quirk_no_way_out(i, m, regs);
766 if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
775 * Variable to establish order between CPUs while scanning.
776 * Each CPU spins initially until executing is equal its number.
778 static atomic_t mce_executing;
781 * Defines order of CPUs on entry. First CPU becomes Monarch.
783 static atomic_t mce_callin;
786 * Check if a timeout waiting for other CPUs happened.
788 static int mce_timed_out(u64 *t, const char *msg)
791 * The others already did panic for some reason.
792 * Bail out like in a timeout.
793 * rmb() to tell the compiler that system_state
794 * might have been modified by someone else.
797 if (atomic_read(&mce_panicked))
799 if (!mca_cfg.monarch_timeout)
801 if ((s64)*t < SPINUNIT) {
802 if (mca_cfg.tolerant <= 1)
803 mce_panic(msg, NULL, NULL);
809 touch_nmi_watchdog();
814 * The Monarch's reign. The Monarch is the CPU who entered
815 * the machine check handler first. It waits for the others to
816 * raise the exception too and then grades them. When any
817 * error is fatal panic. Only then let the others continue.
819 * The other CPUs entering the MCE handler will be controlled by the
820 * Monarch. They are called Subjects.
822 * This way we prevent any potential data corruption in a unrecoverable case
823 * and also makes sure always all CPU's errors are examined.
825 * Also this detects the case of a machine check event coming from outer
826 * space (not detected by any CPUs) In this case some external agent wants
827 * us to shut down, so panic too.
829 * The other CPUs might still decide to panic if the handler happens
830 * in a unrecoverable place, but in this case the system is in a semi-stable
831 * state and won't corrupt anything by itself. It's ok to let the others
832 * continue for a bit first.
834 * All the spin loops have timeouts; when a timeout happens a CPU
835 * typically elects itself to be Monarch.
837 static void mce_reign(void)
840 struct mce *m = NULL;
841 int global_worst = 0;
846 * This CPU is the Monarch and the other CPUs have run
847 * through their handlers.
848 * Grade the severity of the errors of all the CPUs.
850 for_each_possible_cpu(cpu) {
851 int severity = mce_severity(&per_cpu(mces_seen, cpu),
854 if (severity > global_worst) {
856 global_worst = severity;
857 m = &per_cpu(mces_seen, cpu);
862 * Cannot recover? Panic here then.
863 * This dumps all the mces in the log buffer and stops the
866 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
867 mce_panic("Fatal machine check", m, msg);
870 * For UC somewhere we let the CPU who detects it handle it.
871 * Also must let continue the others, otherwise the handling
872 * CPU could deadlock on a lock.
876 * No machine check event found. Must be some external
877 * source or one CPU is hung. Panic.
879 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
880 mce_panic("Fatal machine check from unknown source", NULL, NULL);
883 * Now clear all the mces_seen so that they don't reappear on
886 for_each_possible_cpu(cpu)
887 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
890 static atomic_t global_nwo;
893 * Start of Monarch synchronization. This waits until all CPUs have
894 * entered the exception handler and then determines if any of them
895 * saw a fatal event that requires panic. Then it executes them
896 * in the entry order.
897 * TBD double check parallel CPU hotunplug
899 static int mce_start(int *no_way_out)
902 int cpus = num_online_cpus();
903 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
908 atomic_add(*no_way_out, &global_nwo);
910 * Rely on the implied barrier below, such that global_nwo
911 * is updated before mce_callin.
913 order = atomic_inc_return(&mce_callin);
918 while (atomic_read(&mce_callin) != cpus) {
919 if (mce_timed_out(&timeout,
920 "Timeout: Not all CPUs entered broadcast exception handler")) {
921 atomic_set(&global_nwo, 0);
928 * mce_callin should be read before global_nwo
934 * Monarch: Starts executing now, the others wait.
936 atomic_set(&mce_executing, 1);
939 * Subject: Now start the scanning loop one by one in
940 * the original callin order.
941 * This way when there are any shared banks it will be
942 * only seen by one CPU before cleared, avoiding duplicates.
944 while (atomic_read(&mce_executing) < order) {
945 if (mce_timed_out(&timeout,
946 "Timeout: Subject CPUs unable to finish machine check processing")) {
947 atomic_set(&global_nwo, 0);
955 * Cache the global no_way_out state.
957 *no_way_out = atomic_read(&global_nwo);
963 * Synchronize between CPUs after main scanning loop.
964 * This invokes the bulk of the Monarch processing.
966 static int mce_end(int order)
969 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
977 * Allow others to run.
979 atomic_inc(&mce_executing);
982 /* CHECKME: Can this race with a parallel hotplug? */
983 int cpus = num_online_cpus();
986 * Monarch: Wait for everyone to go through their scanning
989 while (atomic_read(&mce_executing) <= cpus) {
990 if (mce_timed_out(&timeout,
991 "Timeout: Monarch CPU unable to finish machine check processing"))
1001 * Subject: Wait for Monarch to finish.
1003 while (atomic_read(&mce_executing) != 0) {
1004 if (mce_timed_out(&timeout,
1005 "Timeout: Monarch CPU did not finish machine check processing"))
1011 * Don't reset anything. That's done by the Monarch.
1017 * Reset all global state.
1020 atomic_set(&global_nwo, 0);
1021 atomic_set(&mce_callin, 0);
1025 * Let others run again.
1027 atomic_set(&mce_executing, 0);
1031 static void mce_clear_state(unsigned long *toclear)
1035 for (i = 0; i < mca_cfg.banks; i++) {
1036 if (test_bit(i, toclear))
1037 mce_wrmsrl(msr_ops.status(i), 0);
1041 static int do_memory_failure(struct mce *m)
1043 int flags = MF_ACTION_REQUIRED;
1046 pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr);
1047 if (!(m->mcgstatus & MCG_STATUS_RIPV))
1048 flags |= MF_MUST_KILL;
1049 ret = memory_failure(m->addr >> PAGE_SHIFT, MCE_VECTOR, flags);
1051 pr_err("Memory error not recovered");
1055 #if defined(arch_unmap_kpfn) && defined(CONFIG_MEMORY_FAILURE)
1057 void arch_unmap_kpfn(unsigned long pfn)
1059 unsigned long decoy_addr;
1062 * Unmap this page from the kernel 1:1 mappings to make sure
1063 * we don't log more errors because of speculative access to
1065 * We would like to just call:
1066 * set_memory_np((unsigned long)pfn_to_kaddr(pfn), 1);
1067 * but doing that would radically increase the odds of a
1068 * speculative access to the posion page because we'd have
1069 * the virtual address of the kernel 1:1 mapping sitting
1070 * around in registers.
1071 * Instead we get tricky. We create a non-canonical address
1072 * that looks just like the one we want, but has bit 63 flipped.
1073 * This relies on set_memory_np() not checking whether we passed
1078 * Build time check to see if we have a spare virtual bit. Don't want
1079 * to leave this until run time because most developers don't have a
1080 * system that can exercise this code path. This will only become a
1081 * problem if/when we move beyond 5-level page tables.
1083 * Hard code "9" here because cpp doesn't grok ilog2(PTRS_PER_PGD)
1085 #if PGDIR_SHIFT + 9 < 63
1086 decoy_addr = (pfn << PAGE_SHIFT) + (PAGE_OFFSET ^ BIT(63));
1088 #error "no unused virtual bit available"
1091 if (set_memory_np(decoy_addr, 1))
1092 pr_warn("Could not invalidate pfn=0x%lx from 1:1 map\n", pfn);
1098 * The actual machine check handler. This only handles real
1099 * exceptions when something got corrupted coming in through int 18.
1101 * This is executed in NMI context not subject to normal locking rules. This
1102 * implies that most kernel services cannot be safely used. Don't even
1103 * think about putting a printk in there!
1105 * On Intel systems this is entered on all CPUs in parallel through
1106 * MCE broadcast. However some CPUs might be broken beyond repair,
1107 * so be always careful when synchronizing with others.
1109 void do_machine_check(struct pt_regs *regs, long error_code)
1111 struct mca_config *cfg = &mca_cfg;
1112 struct mce m, *final;
1118 * Establish sequential order between the CPUs entering the machine
1123 * If no_way_out gets set, there is no safe way to recover from this
1124 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway.
1128 * If kill_it gets set, there might be a way to recover from this
1132 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1133 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1134 char *msg = "Unknown";
1137 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1141 int cpu = smp_processor_id();
1144 * Cases where we avoid rendezvous handler timeout:
1145 * 1) If this CPU is offline.
1147 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1148 * skip those CPUs which remain looping in the 1st kernel - see
1149 * crash_nmi_callback().
1151 * Note: there still is a small window between kexec-ing and the new,
1152 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1153 * might not get handled properly.
1155 if (cpu_is_offline(cpu) ||
1156 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1159 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
1160 if (mcgstatus & MCG_STATUS_RIPV) {
1161 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1168 this_cpu_inc(mce_exception_count);
1173 mce_gather_info(&m, regs);
1176 final = this_cpu_ptr(&mces_seen);
1179 memset(valid_banks, 0, sizeof(valid_banks));
1180 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1185 * When no restart IP might need to kill or panic.
1186 * Assume the worst for now, but if we find the
1187 * severity is MCE_AR_SEVERITY we have other options.
1189 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1193 * Check if this MCE is signaled to only this logical processor,
1196 if (m.cpuvendor == X86_VENDOR_INTEL)
1197 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1200 * Go through all banks in exclusion of the other CPUs. This way we
1201 * don't report duplicated events on shared banks because the first one
1202 * to see it will clear it. If this is a Local MCE, then no need to
1203 * perform rendezvous.
1206 order = mce_start(&no_way_out);
1208 for (i = 0; i < cfg->banks; i++) {
1209 __clear_bit(i, toclear);
1210 if (!test_bit(i, valid_banks))
1212 if (!mce_banks[i].ctl)
1219 m.status = mce_rdmsrl(msr_ops.status(i));
1220 if ((m.status & MCI_STATUS_VAL) == 0)
1224 * Non uncorrected or non signaled errors are handled by
1225 * machine_check_poll. Leave them alone, unless this panics.
1227 if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1232 * Set taint even when machine check was not enabled.
1234 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1236 severity = mce_severity(&m, cfg->tolerant, NULL, true);
1239 * When machine check was for corrected/deferred handler don't
1240 * touch, unless we're panicing.
1242 if ((severity == MCE_KEEP_SEVERITY ||
1243 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1245 __set_bit(i, toclear);
1246 if (severity == MCE_NO_SEVERITY) {
1248 * Machine check event was not enabled. Clear, but
1254 mce_read_aux(&m, i);
1256 /* assuming valid severity level != 0 */
1257 m.severity = severity;
1261 if (severity > worst) {
1267 /* mce_clear_state will clear *final, save locally for use later */
1271 mce_clear_state(toclear);
1274 * Do most of the synchronization with other CPUs.
1275 * When there's any problem use only local no_way_out state.
1278 if (mce_end(order) < 0)
1279 no_way_out = worst >= MCE_PANIC_SEVERITY;
1282 * Local MCE skipped calling mce_reign()
1283 * If we found a fatal error, we need to panic here.
1285 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
1286 mce_panic("Machine check from unknown source",
1291 * If tolerant is at an insane level we drop requests to kill
1292 * processes and continue even when there is no way out.
1294 if (cfg->tolerant == 3)
1296 else if (no_way_out)
1297 mce_panic("Fatal machine check on current CPU", &m, msg);
1300 mce_report_event(regs);
1301 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1305 if (worst != MCE_AR_SEVERITY && !kill_it)
1308 /* Fault was in user mode and we need to take some action */
1309 if ((m.cs & 3) == 3) {
1310 ist_begin_non_atomic(regs);
1313 if (kill_it || do_memory_failure(&m))
1314 force_sig(SIGBUS, current);
1315 local_irq_disable();
1316 ist_end_non_atomic();
1318 if (!fixup_exception(regs, X86_TRAP_MC))
1319 mce_panic("Failed kernel mode recovery", &m, NULL);
1325 EXPORT_SYMBOL_GPL(do_machine_check);
1327 #ifndef CONFIG_MEMORY_FAILURE
1328 int memory_failure(unsigned long pfn, int vector, int flags)
1330 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1331 BUG_ON(flags & MF_ACTION_REQUIRED);
1332 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1333 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1341 * Periodic polling timer for "silent" machine check errors. If the
1342 * poller finds an MCE, poll 2x faster. When the poller finds no more
1343 * errors, poll 2x slower (up to check_interval seconds).
1345 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1347 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1348 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1350 static unsigned long mce_adjust_timer_default(unsigned long interval)
1355 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1357 static void __start_timer(struct timer_list *t, unsigned long interval)
1359 unsigned long when = jiffies + interval;
1360 unsigned long flags;
1362 local_irq_save(flags);
1364 if (!timer_pending(t) || time_before(when, t->expires))
1365 mod_timer(t, round_jiffies(when));
1367 local_irq_restore(flags);
1370 static void mce_timer_fn(unsigned long data)
1372 struct timer_list *t = this_cpu_ptr(&mce_timer);
1373 int cpu = smp_processor_id();
1376 WARN_ON(cpu != data);
1378 iv = __this_cpu_read(mce_next_interval);
1380 if (mce_available(this_cpu_ptr(&cpu_info))) {
1381 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1383 if (mce_intel_cmci_poll()) {
1384 iv = mce_adjust_timer(iv);
1390 * Alert userspace if needed. If we logged an MCE, reduce the polling
1391 * interval, otherwise increase the polling interval.
1393 if (mce_notify_irq())
1394 iv = max(iv / 2, (unsigned long) HZ/100);
1396 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1399 __this_cpu_write(mce_next_interval, iv);
1400 __start_timer(t, iv);
1404 * Ensure that the timer is firing in @interval from now.
1406 void mce_timer_kick(unsigned long interval)
1408 struct timer_list *t = this_cpu_ptr(&mce_timer);
1409 unsigned long iv = __this_cpu_read(mce_next_interval);
1411 __start_timer(t, interval);
1414 __this_cpu_write(mce_next_interval, interval);
1417 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1418 static void mce_timer_delete_all(void)
1422 for_each_online_cpu(cpu)
1423 del_timer_sync(&per_cpu(mce_timer, cpu));
1427 * Notify the user(s) about new machine check events.
1428 * Can be called from interrupt context, but not from machine check/NMI
1431 int mce_notify_irq(void)
1433 /* Not more than two messages every minute */
1434 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1436 if (test_and_clear_bit(0, &mce_need_notify)) {
1439 if (__ratelimit(&ratelimit))
1440 pr_info(HW_ERR "Machine check events logged\n");
1446 EXPORT_SYMBOL_GPL(mce_notify_irq);
1448 static int __mcheck_cpu_mce_banks_init(void)
1451 u8 num_banks = mca_cfg.banks;
1453 mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL);
1457 for (i = 0; i < num_banks; i++) {
1458 struct mce_bank *b = &mce_banks[i];
1467 * Initialize Machine Checks for a CPU.
1469 static int __mcheck_cpu_cap_init(void)
1474 rdmsrl(MSR_IA32_MCG_CAP, cap);
1476 b = cap & MCG_BANKCNT_MASK;
1478 pr_info("CPU supports %d MCE banks\n", b);
1480 if (b > MAX_NR_BANKS) {
1481 pr_warn("Using only %u machine check banks out of %u\n",
1486 /* Don't support asymmetric configurations today */
1487 WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks);
1491 int err = __mcheck_cpu_mce_banks_init();
1497 /* Use accurate RIP reporting if available. */
1498 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1499 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1501 if (cap & MCG_SER_P)
1507 static void __mcheck_cpu_init_generic(void)
1509 enum mcp_flags m_fl = 0;
1510 mce_banks_t all_banks;
1513 if (!mca_cfg.bootlog)
1517 * Log the machine checks left over from the previous reset.
1519 bitmap_fill(all_banks, MAX_NR_BANKS);
1520 machine_check_poll(MCP_UC | m_fl, &all_banks);
1522 cr4_set_bits(X86_CR4_MCE);
1524 rdmsrl(MSR_IA32_MCG_CAP, cap);
1525 if (cap & MCG_CTL_P)
1526 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1529 static void __mcheck_cpu_init_clear_banks(void)
1533 for (i = 0; i < mca_cfg.banks; i++) {
1534 struct mce_bank *b = &mce_banks[i];
1538 wrmsrl(msr_ops.ctl(i), b->ctl);
1539 wrmsrl(msr_ops.status(i), 0);
1544 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1545 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1546 * Vol 3B Table 15-20). But this confuses both the code that determines
1547 * whether the machine check occurred in kernel or user mode, and also
1548 * the severity assessment code. Pretend that EIPV was set, and take the
1549 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1551 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1555 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1557 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1558 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1559 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1561 (MCI_STATUS_UC|MCI_STATUS_EN|
1562 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1563 MCI_STATUS_AR|MCACOD_INSTR))
1566 m->mcgstatus |= MCG_STATUS_EIPV;
1571 /* Add per CPU specific workarounds here */
1572 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1574 struct mca_config *cfg = &mca_cfg;
1576 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1577 pr_info("unknown CPU type - not enabling MCE support\n");
1581 /* This should be disabled by the BIOS, but isn't always */
1582 if (c->x86_vendor == X86_VENDOR_AMD) {
1583 if (c->x86 == 15 && cfg->banks > 4) {
1585 * disable GART TBL walk error reporting, which
1586 * trips off incorrectly with the IOMMU & 3ware
1589 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1591 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1593 * Lots of broken BIOS around that don't clear them
1594 * by default and leave crap in there. Don't log:
1599 * Various K7s with broken bank 0 around. Always disable
1602 if (c->x86 == 6 && cfg->banks > 0)
1603 mce_banks[0].ctl = 0;
1606 * overflow_recov is supported for F15h Models 00h-0fh
1607 * even though we don't have a CPUID bit for it.
1609 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1610 mce_flags.overflow_recov = 1;
1613 * Turn off MC4_MISC thresholding banks on those models since
1614 * they're not supported there.
1616 if (c->x86 == 0x15 &&
1617 (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
1622 0x00000413, /* MC4_MISC0 */
1623 0xc0000408, /* MC4_MISC1 */
1626 rdmsrl(MSR_K7_HWCR, hwcr);
1628 /* McStatusWrEn has to be set */
1629 need_toggle = !(hwcr & BIT(18));
1632 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
1634 /* Clear CntP bit safely */
1635 for (i = 0; i < ARRAY_SIZE(msrs); i++)
1636 msr_clear_bit(msrs[i], 62);
1638 /* restore old settings */
1640 wrmsrl(MSR_K7_HWCR, hwcr);
1644 if (c->x86_vendor == X86_VENDOR_INTEL) {
1646 * SDM documents that on family 6 bank 0 should not be written
1647 * because it aliases to another special BIOS controlled
1649 * But it's not aliased anymore on model 0x1a+
1650 * Don't ignore bank 0 completely because there could be a
1651 * valid event later, merely don't write CTL0.
1654 if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0)
1655 mce_banks[0].init = 0;
1658 * All newer Intel systems support MCE broadcasting. Enable
1659 * synchronization with a one second timeout.
1661 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1662 cfg->monarch_timeout < 0)
1663 cfg->monarch_timeout = USEC_PER_SEC;
1666 * There are also broken BIOSes on some Pentium M and
1669 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1672 if (c->x86 == 6 && c->x86_model == 45)
1673 quirk_no_way_out = quirk_sandybridge_ifu;
1675 if (cfg->monarch_timeout < 0)
1676 cfg->monarch_timeout = 0;
1677 if (cfg->bootlog != 0)
1678 cfg->panic_timeout = 30;
1683 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1688 switch (c->x86_vendor) {
1689 case X86_VENDOR_INTEL:
1690 intel_p5_mcheck_init(c);
1693 case X86_VENDOR_CENTAUR:
1694 winchip_mcheck_init(c);
1705 * Init basic CPU features needed for early decoding of MCEs.
1707 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1709 if (c->x86_vendor == X86_VENDOR_AMD) {
1710 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1711 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1712 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1714 if (mce_flags.smca) {
1715 msr_ops.ctl = smca_ctl_reg;
1716 msr_ops.status = smca_status_reg;
1717 msr_ops.addr = smca_addr_reg;
1718 msr_ops.misc = smca_misc_reg;
1723 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1725 switch (c->x86_vendor) {
1726 case X86_VENDOR_INTEL:
1727 mce_intel_feature_init(c);
1728 mce_adjust_timer = cmci_intel_adjust_timer;
1731 case X86_VENDOR_AMD: {
1732 mce_amd_feature_init(c);
1741 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1743 switch (c->x86_vendor) {
1744 case X86_VENDOR_INTEL:
1745 mce_intel_feature_clear(c);
1752 static void mce_start_timer(struct timer_list *t)
1754 unsigned long iv = check_interval * HZ;
1756 if (mca_cfg.ignore_ce || !iv)
1759 this_cpu_write(mce_next_interval, iv);
1760 __start_timer(t, iv);
1763 static void __mcheck_cpu_setup_timer(void)
1765 struct timer_list *t = this_cpu_ptr(&mce_timer);
1766 unsigned int cpu = smp_processor_id();
1768 setup_pinned_timer(t, mce_timer_fn, cpu);
1771 static void __mcheck_cpu_init_timer(void)
1773 struct timer_list *t = this_cpu_ptr(&mce_timer);
1774 unsigned int cpu = smp_processor_id();
1776 setup_pinned_timer(t, mce_timer_fn, cpu);
1780 /* Handle unconfigured int18 (should never happen) */
1781 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1783 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1784 smp_processor_id());
1787 /* Call the installed machine check handler for this CPU setup. */
1788 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1789 unexpected_machine_check;
1792 * Called for each booted CPU to set up machine checks.
1793 * Must be called with preempt off:
1795 void mcheck_cpu_init(struct cpuinfo_x86 *c)
1797 if (mca_cfg.disabled)
1800 if (__mcheck_cpu_ancient_init(c))
1803 if (!mce_available(c))
1806 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1807 mca_cfg.disabled = true;
1811 if (mce_gen_pool_init()) {
1812 mca_cfg.disabled = true;
1813 pr_emerg("Couldn't allocate MCE records pool!\n");
1817 machine_check_vector = do_machine_check;
1819 __mcheck_cpu_init_early(c);
1820 __mcheck_cpu_init_generic();
1821 __mcheck_cpu_init_vendor(c);
1822 __mcheck_cpu_init_clear_banks();
1823 __mcheck_cpu_setup_timer();
1827 * Called for each booted CPU to clear some machine checks opt-ins
1829 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
1831 if (mca_cfg.disabled)
1834 if (!mce_available(c))
1838 * Possibly to clear general settings generic to x86
1839 * __mcheck_cpu_clear_generic(c);
1841 __mcheck_cpu_clear_vendor(c);
1845 static void __mce_disable_bank(void *arg)
1847 int bank = *((int *)arg);
1848 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
1849 cmci_disable_bank(bank);
1852 void mce_disable_bank(int bank)
1854 if (bank >= mca_cfg.banks) {
1856 "Ignoring request to disable invalid MCA bank %d.\n",
1860 set_bit(bank, mce_banks_ce_disabled);
1861 on_each_cpu(__mce_disable_bank, &bank, 1);
1865 * mce=off Disables machine check
1866 * mce=no_cmci Disables CMCI
1867 * mce=no_lmce Disables LMCE
1868 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1869 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1870 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1871 * monarchtimeout is how long to wait for other CPUs on machine
1872 * check, or 0 to not wait
1873 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
1875 * mce=nobootlog Don't log MCEs from before booting.
1876 * mce=bios_cmci_threshold Don't program the CMCI threshold
1877 * mce=recovery force enable memcpy_mcsafe()
1879 static int __init mcheck_enable(char *str)
1881 struct mca_config *cfg = &mca_cfg;
1889 if (!strcmp(str, "off"))
1890 cfg->disabled = true;
1891 else if (!strcmp(str, "no_cmci"))
1892 cfg->cmci_disabled = true;
1893 else if (!strcmp(str, "no_lmce"))
1894 cfg->lmce_disabled = true;
1895 else if (!strcmp(str, "dont_log_ce"))
1896 cfg->dont_log_ce = true;
1897 else if (!strcmp(str, "ignore_ce"))
1898 cfg->ignore_ce = true;
1899 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1900 cfg->bootlog = (str[0] == 'b');
1901 else if (!strcmp(str, "bios_cmci_threshold"))
1902 cfg->bios_cmci_threshold = true;
1903 else if (!strcmp(str, "recovery"))
1904 cfg->recovery = true;
1905 else if (isdigit(str[0])) {
1906 if (get_option(&str, &cfg->tolerant) == 2)
1907 get_option(&str, &(cfg->monarch_timeout));
1909 pr_info("mce argument %s ignored. Please use /sys\n", str);
1914 __setup("mce", mcheck_enable);
1916 int __init mcheck_init(void)
1918 mcheck_intel_therm_init();
1919 mce_register_decode_chain(&first_nb);
1920 mce_register_decode_chain(&mce_srao_nb);
1921 mce_register_decode_chain(&mce_default_nb);
1922 mcheck_vendor_init_severity();
1924 INIT_WORK(&mce_work, mce_gen_pool_process);
1925 init_irq_work(&mce_irq_work, mce_irq_work_cb);
1931 * mce_syscore: PM support
1935 * Disable machine checks on suspend and shutdown. We can't really handle
1938 static void mce_disable_error_reporting(void)
1942 for (i = 0; i < mca_cfg.banks; i++) {
1943 struct mce_bank *b = &mce_banks[i];
1946 wrmsrl(msr_ops.ctl(i), 0);
1951 static void vendor_disable_error_reporting(void)
1954 * Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
1955 * Disabling them for just a single offlined CPU is bad, since it will
1956 * inhibit reporting for all shared resources on the socket like the
1957 * last level cache (LLC), the integrated memory controller (iMC), etc.
1959 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
1960 boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1963 mce_disable_error_reporting();
1966 static int mce_syscore_suspend(void)
1968 vendor_disable_error_reporting();
1972 static void mce_syscore_shutdown(void)
1974 vendor_disable_error_reporting();
1978 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1979 * Only one CPU is active at this time, the others get re-added later using
1982 static void mce_syscore_resume(void)
1984 __mcheck_cpu_init_generic();
1985 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
1986 __mcheck_cpu_init_clear_banks();
1989 static struct syscore_ops mce_syscore_ops = {
1990 .suspend = mce_syscore_suspend,
1991 .shutdown = mce_syscore_shutdown,
1992 .resume = mce_syscore_resume,
1996 * mce_device: Sysfs support
1999 static void mce_cpu_restart(void *data)
2001 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2003 __mcheck_cpu_init_generic();
2004 __mcheck_cpu_init_clear_banks();
2005 __mcheck_cpu_init_timer();
2008 /* Reinit MCEs after user configuration changes */
2009 static void mce_restart(void)
2011 mce_timer_delete_all();
2012 on_each_cpu(mce_cpu_restart, NULL, 1);
2015 /* Toggle features for corrected errors */
2016 static void mce_disable_cmci(void *data)
2018 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2023 static void mce_enable_ce(void *all)
2025 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2030 __mcheck_cpu_init_timer();
2033 static struct bus_type mce_subsys = {
2034 .name = "machinecheck",
2035 .dev_name = "machinecheck",
2038 DEFINE_PER_CPU(struct device *, mce_device);
2040 static inline struct mce_bank *attr_to_bank(struct device_attribute *attr)
2042 return container_of(attr, struct mce_bank, attr);
2045 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2048 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
2051 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2052 const char *buf, size_t size)
2056 if (kstrtou64(buf, 0, &new) < 0)
2059 attr_to_bank(attr)->ctl = new;
2065 static ssize_t set_ignore_ce(struct device *s,
2066 struct device_attribute *attr,
2067 const char *buf, size_t size)
2071 if (kstrtou64(buf, 0, &new) < 0)
2074 if (mca_cfg.ignore_ce ^ !!new) {
2076 /* disable ce features */
2077 mce_timer_delete_all();
2078 on_each_cpu(mce_disable_cmci, NULL, 1);
2079 mca_cfg.ignore_ce = true;
2081 /* enable ce features */
2082 mca_cfg.ignore_ce = false;
2083 on_each_cpu(mce_enable_ce, (void *)1, 1);
2089 static ssize_t set_cmci_disabled(struct device *s,
2090 struct device_attribute *attr,
2091 const char *buf, size_t size)
2095 if (kstrtou64(buf, 0, &new) < 0)
2098 if (mca_cfg.cmci_disabled ^ !!new) {
2101 on_each_cpu(mce_disable_cmci, NULL, 1);
2102 mca_cfg.cmci_disabled = true;
2105 mca_cfg.cmci_disabled = false;
2106 on_each_cpu(mce_enable_ce, NULL, 1);
2112 static ssize_t store_int_with_restart(struct device *s,
2113 struct device_attribute *attr,
2114 const char *buf, size_t size)
2116 ssize_t ret = device_store_int(s, attr, buf, size);
2121 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2122 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2123 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2125 static struct dev_ext_attribute dev_attr_check_interval = {
2126 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2130 static struct dev_ext_attribute dev_attr_ignore_ce = {
2131 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2135 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2136 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2137 &mca_cfg.cmci_disabled
2140 static struct device_attribute *mce_device_attrs[] = {
2141 &dev_attr_tolerant.attr,
2142 &dev_attr_check_interval.attr,
2143 #ifdef CONFIG_X86_MCELOG_LEGACY
2146 &dev_attr_monarch_timeout.attr,
2147 &dev_attr_dont_log_ce.attr,
2148 &dev_attr_ignore_ce.attr,
2149 &dev_attr_cmci_disabled.attr,
2153 static cpumask_var_t mce_device_initialized;
2155 static void mce_device_release(struct device *dev)
2160 /* Per cpu device init. All of the cpus still share the same ctrl bank: */
2161 static int mce_device_create(unsigned int cpu)
2167 if (!mce_available(&boot_cpu_data))
2170 dev = per_cpu(mce_device, cpu);
2174 dev = kzalloc(sizeof *dev, GFP_KERNEL);
2178 dev->bus = &mce_subsys;
2179 dev->release = &mce_device_release;
2181 err = device_register(dev);
2187 for (i = 0; mce_device_attrs[i]; i++) {
2188 err = device_create_file(dev, mce_device_attrs[i]);
2192 for (j = 0; j < mca_cfg.banks; j++) {
2193 err = device_create_file(dev, &mce_banks[j].attr);
2197 cpumask_set_cpu(cpu, mce_device_initialized);
2198 per_cpu(mce_device, cpu) = dev;
2203 device_remove_file(dev, &mce_banks[j].attr);
2206 device_remove_file(dev, mce_device_attrs[i]);
2208 device_unregister(dev);
2213 static void mce_device_remove(unsigned int cpu)
2215 struct device *dev = per_cpu(mce_device, cpu);
2218 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2221 for (i = 0; mce_device_attrs[i]; i++)
2222 device_remove_file(dev, mce_device_attrs[i]);
2224 for (i = 0; i < mca_cfg.banks; i++)
2225 device_remove_file(dev, &mce_banks[i].attr);
2227 device_unregister(dev);
2228 cpumask_clear_cpu(cpu, mce_device_initialized);
2229 per_cpu(mce_device, cpu) = NULL;
2232 /* Make sure there are no machine checks on offlined CPUs. */
2233 static void mce_disable_cpu(void)
2235 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2238 if (!cpuhp_tasks_frozen)
2241 vendor_disable_error_reporting();
2244 static void mce_reenable_cpu(void)
2248 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2251 if (!cpuhp_tasks_frozen)
2253 for (i = 0; i < mca_cfg.banks; i++) {
2254 struct mce_bank *b = &mce_banks[i];
2257 wrmsrl(msr_ops.ctl(i), b->ctl);
2261 static int mce_cpu_dead(unsigned int cpu)
2263 mce_intel_hcpu_update(cpu);
2265 /* intentionally ignoring frozen here */
2266 if (!cpuhp_tasks_frozen)
2271 static int mce_cpu_online(unsigned int cpu)
2273 struct timer_list *t = this_cpu_ptr(&mce_timer);
2276 mce_device_create(cpu);
2278 ret = mce_threshold_create_device(cpu);
2280 mce_device_remove(cpu);
2288 static int mce_cpu_pre_down(unsigned int cpu)
2290 struct timer_list *t = this_cpu_ptr(&mce_timer);
2294 mce_threshold_remove_device(cpu);
2295 mce_device_remove(cpu);
2299 static __init void mce_init_banks(void)
2303 for (i = 0; i < mca_cfg.banks; i++) {
2304 struct mce_bank *b = &mce_banks[i];
2305 struct device_attribute *a = &b->attr;
2307 sysfs_attr_init(&a->attr);
2308 a->attr.name = b->attrname;
2309 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2311 a->attr.mode = 0644;
2312 a->show = show_bank;
2313 a->store = set_bank;
2317 static __init int mcheck_init_device(void)
2321 if (!mce_available(&boot_cpu_data)) {
2326 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2333 err = subsys_system_register(&mce_subsys, NULL);
2337 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2342 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2343 mce_cpu_online, mce_cpu_pre_down);
2345 goto err_out_online;
2347 register_syscore_ops(&mce_syscore_ops);
2352 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2355 free_cpumask_var(mce_device_initialized);
2358 pr_err("Unable to init MCE device (rc: %d)\n", err);
2362 device_initcall_sync(mcheck_init_device);
2365 * Old style boot options parsing. Only for compatibility.
2367 static int __init mcheck_disable(char *str)
2369 mca_cfg.disabled = true;
2372 __setup("nomce", mcheck_disable);
2374 #ifdef CONFIG_DEBUG_FS
2375 struct dentry *mce_get_debugfs_dir(void)
2377 static struct dentry *dmce;
2380 dmce = debugfs_create_dir("mce", NULL);
2385 static void mce_reset(void)
2388 atomic_set(&mce_fake_panicked, 0);
2389 atomic_set(&mce_executing, 0);
2390 atomic_set(&mce_callin, 0);
2391 atomic_set(&global_nwo, 0);
2394 static int fake_panic_get(void *data, u64 *val)
2400 static int fake_panic_set(void *data, u64 val)
2407 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2408 fake_panic_set, "%llu\n");
2410 static int __init mcheck_debugfs_init(void)
2412 struct dentry *dmce, *ffake_panic;
2414 dmce = mce_get_debugfs_dir();
2417 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2425 static int __init mcheck_debugfs_init(void) { return -EINVAL; }
2428 DEFINE_STATIC_KEY_FALSE(mcsafe_key);
2429 EXPORT_SYMBOL_GPL(mcsafe_key);
2431 static int __init mcheck_late_init(void)
2433 if (mca_cfg.recovery)
2434 static_branch_inc(&mcsafe_key);
2436 mcheck_debugfs_init();
2440 * Flush out everything that has been logged during early boot, now that
2441 * everything has been initialized (workqueues, decoders, ...).
2443 mce_schedule_work();
2447 late_initcall(mcheck_late_init);