Merge branches 'x86/apic', 'x86/cleanups' and 'x86/mm' into x86/core
[sfrench/cifs-2.6.git] / arch / x86 / kernel / cpu / intel.c
1 #include <linux/init.h>
2 #include <linux/kernel.h>
3
4 #include <linux/string.h>
5 #include <linux/bitops.h>
6 #include <linux/smp.h>
7 #include <linux/thread_info.h>
8 #include <linux/module.h>
9
10 #include <asm/processor.h>
11 #include <asm/pgtable.h>
12 #include <asm/msr.h>
13 #include <asm/uaccess.h>
14 #include <asm/ds.h>
15 #include <asm/bugs.h>
16 #include <asm/cpu.h>
17
18 #ifdef CONFIG_X86_64
19 #include <asm/topology.h>
20 #include <asm/numa_64.h>
21 #endif
22
23 #include "cpu.h"
24
25 #ifdef CONFIG_X86_LOCAL_APIC
26 #include <asm/mpspec.h>
27 #include <asm/apic.h>
28 #endif
29
30 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
31 {
32         /* Unmask CPUID levels if masked: */
33         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
34                 u64 misc_enable;
35
36                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
37
38                 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
39                         misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
40                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
41                         c->cpuid_level = cpuid_eax(0);
42                 }
43         }
44
45         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
46                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
47                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
48
49 #ifdef CONFIG_X86_64
50         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
51 #else
52         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
53         if (c->x86 == 15 && c->x86_cache_alignment == 64)
54                 c->x86_cache_alignment = 128;
55 #endif
56
57         /* CPUID workaround for 0F33/0F34 CPU */
58         if (c->x86 == 0xF && c->x86_model == 0x3
59             && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
60                 c->x86_phys_bits = 36;
61
62         /*
63          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
64          * with P/T states and does not stop in deep C-states
65          */
66         if (c->x86_power & (1 << 8)) {
67                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
68                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
69         }
70
71         /*
72          * There is a known erratum on Pentium III and Core Solo
73          * and Core Duo CPUs.
74          * " Page with PAT set to WC while associated MTRR is UC
75          *   may consolidate to UC "
76          * Because of this erratum, it is better to stick with
77          * setting WC in MTRR rather than using PAT on these CPUs.
78          *
79          * Enable PAT WC only on P4, Core 2 or later CPUs.
80          */
81         if (c->x86 == 6 && c->x86_model < 15)
82                 clear_cpu_cap(c, X86_FEATURE_PAT);
83 }
84
85 #ifdef CONFIG_X86_32
86 /*
87  *      Early probe support logic for ppro memory erratum #50
88  *
89  *      This is called before we do cpu ident work
90  */
91
92 int __cpuinit ppro_with_ram_bug(void)
93 {
94         /* Uses data from early_cpu_detect now */
95         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
96             boot_cpu_data.x86 == 6 &&
97             boot_cpu_data.x86_model == 1 &&
98             boot_cpu_data.x86_mask < 8) {
99                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
100                 return 1;
101         }
102         return 0;
103 }
104
105 #ifdef CONFIG_X86_F00F_BUG
106 static void __cpuinit trap_init_f00f_bug(void)
107 {
108         __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
109
110         /*
111          * Update the IDT descriptor and reload the IDT so that
112          * it uses the read-only mapped virtual address.
113          */
114         idt_descr.address = fix_to_virt(FIX_F00F_IDT);
115         load_idt(&idt_descr);
116 }
117 #endif
118
119 static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
120 {
121 #ifdef CONFIG_SMP
122         /* calling is from identify_secondary_cpu() ? */
123         if (c->cpu_index == boot_cpu_id)
124                 return;
125
126         /*
127          * Mask B, Pentium, but not Pentium MMX
128          */
129         if (c->x86 == 5 &&
130             c->x86_mask >= 1 && c->x86_mask <= 4 &&
131             c->x86_model <= 3) {
132                 /*
133                  * Remember we have B step Pentia with bugs
134                  */
135                 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
136                                     "with B stepping processors.\n");
137         }
138 #endif
139 }
140
141 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
142 {
143         unsigned long lo, hi;
144
145 #ifdef CONFIG_X86_F00F_BUG
146         /*
147          * All current models of Pentium and Pentium with MMX technology CPUs
148          * have the F0 0F bug, which lets nonprivileged users lock up the system.
149          * Note that the workaround only should be initialized once...
150          */
151         c->f00f_bug = 0;
152         if (!paravirt_enabled() && c->x86 == 5) {
153                 static int f00f_workaround_enabled;
154
155                 c->f00f_bug = 1;
156                 if (!f00f_workaround_enabled) {
157                         trap_init_f00f_bug();
158                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
159                         f00f_workaround_enabled = 1;
160                 }
161         }
162 #endif
163
164         /*
165          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
166          * model 3 mask 3
167          */
168         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
169                 clear_cpu_cap(c, X86_FEATURE_SEP);
170
171         /*
172          * P4 Xeon errata 037 workaround.
173          * Hardware prefetcher may cause stale data to be loaded into the cache.
174          */
175         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
176                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
177                 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
178                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
179                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
180                         lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
181                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
182                 }
183         }
184
185         /*
186          * See if we have a good local APIC by checking for buggy Pentia,
187          * i.e. all B steppings and the C2 stepping of P54C when using their
188          * integrated APIC (see 11AP erratum in "Pentium Processor
189          * Specification Update").
190          */
191         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
192             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
193                 set_cpu_cap(c, X86_FEATURE_11AP);
194
195
196 #ifdef CONFIG_X86_INTEL_USERCOPY
197         /*
198          * Set up the preferred alignment for movsl bulk memory moves
199          */
200         switch (c->x86) {
201         case 4:         /* 486: untested */
202                 break;
203         case 5:         /* Old Pentia: untested */
204                 break;
205         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
206                 movsl_mask.mask = 7;
207                 break;
208         case 15:        /* P4 is OK down to 8-byte alignment */
209                 movsl_mask.mask = 7;
210                 break;
211         }
212 #endif
213
214 #ifdef CONFIG_X86_NUMAQ
215         numaq_tsc_disable();
216 #endif
217
218         intel_smp_check(c);
219 }
220 #else
221 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
222 {
223 }
224 #endif
225
226 static void __cpuinit srat_detect_node(void)
227 {
228 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
229         unsigned node;
230         int cpu = smp_processor_id();
231         int apicid = hard_smp_processor_id();
232
233         /* Don't do the funky fallback heuristics the AMD version employs
234            for now. */
235         node = apicid_to_node[apicid];
236         if (node == NUMA_NO_NODE || !node_online(node))
237                 node = first_node(node_online_map);
238         numa_set_node(cpu, node);
239
240         printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
241 #endif
242 }
243
244 /*
245  * find out the number of processor cores on the die
246  */
247 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
248 {
249         unsigned int eax, ebx, ecx, edx;
250
251         if (c->cpuid_level < 4)
252                 return 1;
253
254         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
255         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
256         if (eax & 0x1f)
257                 return ((eax >> 26) + 1);
258         else
259                 return 1;
260 }
261
262 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
263 {
264         /* Intel VMX MSR indicated features */
265 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
266 #define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
267 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
268 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
269 #define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
270 #define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
271
272         u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
273
274         clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
275         clear_cpu_cap(c, X86_FEATURE_VNMI);
276         clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
277         clear_cpu_cap(c, X86_FEATURE_EPT);
278         clear_cpu_cap(c, X86_FEATURE_VPID);
279
280         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
281         msr_ctl = vmx_msr_high | vmx_msr_low;
282         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
283                 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
284         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
285                 set_cpu_cap(c, X86_FEATURE_VNMI);
286         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
287                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
288                       vmx_msr_low, vmx_msr_high);
289                 msr_ctl2 = vmx_msr_high | vmx_msr_low;
290                 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
291                     (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
292                         set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
293                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
294                         set_cpu_cap(c, X86_FEATURE_EPT);
295                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
296                         set_cpu_cap(c, X86_FEATURE_VPID);
297         }
298 }
299
300 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
301 {
302         unsigned int l2 = 0;
303
304         early_init_intel(c);
305
306         intel_workarounds(c);
307
308         /*
309          * Detect the extended topology information if available. This
310          * will reinitialise the initial_apicid which will be used
311          * in init_intel_cacheinfo()
312          */
313         detect_extended_topology(c);
314
315         l2 = init_intel_cacheinfo(c);
316         if (c->cpuid_level > 9) {
317                 unsigned eax = cpuid_eax(10);
318                 /* Check for version and the number of counters */
319                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
320                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
321         }
322
323         if (cpu_has_xmm2)
324                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
325         if (cpu_has_ds) {
326                 unsigned int l1;
327                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
328                 if (!(l1 & (1<<11)))
329                         set_cpu_cap(c, X86_FEATURE_BTS);
330                 if (!(l1 & (1<<12)))
331                         set_cpu_cap(c, X86_FEATURE_PEBS);
332                 ds_init_intel(c);
333         }
334
335         if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
336                 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
337
338 #ifdef CONFIG_X86_64
339         if (c->x86 == 15)
340                 c->x86_cache_alignment = c->x86_clflush_size * 2;
341         if (c->x86 == 6)
342                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
343 #else
344         /*
345          * Names for the Pentium II/Celeron processors
346          * detectable only by also checking the cache size.
347          * Dixon is NOT a Celeron.
348          */
349         if (c->x86 == 6) {
350                 char *p = NULL;
351
352                 switch (c->x86_model) {
353                 case 5:
354                         if (c->x86_mask == 0) {
355                                 if (l2 == 0)
356                                         p = "Celeron (Covington)";
357                                 else if (l2 == 256)
358                                         p = "Mobile Pentium II (Dixon)";
359                         }
360                         break;
361
362                 case 6:
363                         if (l2 == 128)
364                                 p = "Celeron (Mendocino)";
365                         else if (c->x86_mask == 0 || c->x86_mask == 5)
366                                 p = "Celeron-A";
367                         break;
368
369                 case 8:
370                         if (l2 == 128)
371                                 p = "Celeron (Coppermine)";
372                         break;
373                 }
374
375                 if (p)
376                         strcpy(c->x86_model_id, p);
377         }
378
379         if (c->x86 == 15)
380                 set_cpu_cap(c, X86_FEATURE_P4);
381         if (c->x86 == 6)
382                 set_cpu_cap(c, X86_FEATURE_P3);
383 #endif
384
385         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
386                 /*
387                  * let's use the legacy cpuid vector 0x1 and 0x4 for topology
388                  * detection.
389                  */
390                 c->x86_max_cores = intel_num_cpu_cores(c);
391 #ifdef CONFIG_X86_32
392                 detect_ht(c);
393 #endif
394         }
395
396         /* Work around errata */
397         srat_detect_node();
398
399         if (cpu_has(c, X86_FEATURE_VMX))
400                 detect_vmx_virtcap(c);
401 }
402
403 #ifdef CONFIG_X86_32
404 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
405 {
406         /*
407          * Intel PIII Tualatin. This comes in two flavours.
408          * One has 256kb of cache, the other 512. We have no way
409          * to determine which, so we use a boottime override
410          * for the 512kb model, and assume 256 otherwise.
411          */
412         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
413                 size = 256;
414         return size;
415 }
416 #endif
417
418 static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
419         .c_vendor       = "Intel",
420         .c_ident        = { "GenuineIntel" },
421 #ifdef CONFIG_X86_32
422         .c_models = {
423                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
424                   {
425                           [0] = "486 DX-25/33",
426                           [1] = "486 DX-50",
427                           [2] = "486 SX",
428                           [3] = "486 DX/2",
429                           [4] = "486 SL",
430                           [5] = "486 SX/2",
431                           [7] = "486 DX/2-WB",
432                           [8] = "486 DX/4",
433                           [9] = "486 DX/4-WB"
434                   }
435                 },
436                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
437                   {
438                           [0] = "Pentium 60/66 A-step",
439                           [1] = "Pentium 60/66",
440                           [2] = "Pentium 75 - 200",
441                           [3] = "OverDrive PODP5V83",
442                           [4] = "Pentium MMX",
443                           [7] = "Mobile Pentium 75 - 200",
444                           [8] = "Mobile Pentium MMX"
445                   }
446                 },
447                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
448                   {
449                           [0] = "Pentium Pro A-step",
450                           [1] = "Pentium Pro",
451                           [3] = "Pentium II (Klamath)",
452                           [4] = "Pentium II (Deschutes)",
453                           [5] = "Pentium II (Deschutes)",
454                           [6] = "Mobile Pentium II",
455                           [7] = "Pentium III (Katmai)",
456                           [8] = "Pentium III (Coppermine)",
457                           [10] = "Pentium III (Cascades)",
458                           [11] = "Pentium III (Tualatin)",
459                   }
460                 },
461                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
462                   {
463                           [0] = "Pentium 4 (Unknown)",
464                           [1] = "Pentium 4 (Willamette)",
465                           [2] = "Pentium 4 (Northwood)",
466                           [4] = "Pentium 4 (Foster)",
467                           [5] = "Pentium 4 (Foster)",
468                   }
469                 },
470         },
471         .c_size_cache   = intel_size_cache,
472 #endif
473         .c_early_init   = early_init_intel,
474         .c_init         = init_intel,
475         .c_x86_vendor   = X86_VENDOR_INTEL,
476 };
477
478 cpu_dev_register(intel_cpu_dev);
479