arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/cpu.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23
  24 #include <asm/uv/uv_mmrs.h>
  25 #include <asm/uv/uv_hub.h>
  26 #include <asm/current.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/uv/bios.h>
  29 #include <asm/uv/uv.h>
  30 #include <asm/apic.h>
  31 #include <asm/ipi.h>
  32 #include <asm/smp.h>
  33 #include <asm/x86_init.h>
  34
  35 DEFINE_PER_CPU(int, x2apic_extra_bits);
  36
  37 static enum uv_system_type uv_system_type;
  38 static u64 gru_start_paddr, gru_end_paddr;
  39
  40 static inline bool is_GRU_range(u64 start, u64 end)
  41 {
  42         return start >= gru_start_paddr && end <= gru_end_paddr;
  43 }
  44
  45 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  46 {
  47         return is_ISA_range(start, end) || is_GRU_range(start, end);
  48 }
  49
  50 static int early_get_nodeid(void)
  51 {
  52         union uvh_node_id_u node_id;
  53         unsigned long *mmr;
  54
  55         mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr));
  56         node_id.v = *mmr;
  57         early_iounmap(mmr, sizeof(*mmr));
  58         return node_id.s.node_id;
  59 }
  60
  61 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  62 {
  63         if (!strcmp(oem_id, "SGI")) {
  64                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
  65                 if (!strcmp(oem_table_id, "UVL"))
  66                         uv_system_type = UV_LEGACY_APIC;
  67                 else if (!strcmp(oem_table_id, "UVX"))
  68                         uv_system_type = UV_X2APIC;
  69                 else if (!strcmp(oem_table_id, "UVH")) {
  70                         __get_cpu_var(x2apic_extra_bits) =
  71                                 early_get_nodeid() << (UV_APIC_PNODE_SHIFT - 1);
  72                         uv_system_type = UV_NON_UNIQUE_APIC;
  73                         return 1;
  74                 }
  75         }
  76         return 0;
  77 }
  78
  79 enum uv_system_type get_uv_system_type(void)
  80 {
  81         return uv_system_type;
  82 }
  83
  84 int is_uv_system(void)
  85 {
  86         return uv_system_type != UV_NONE;
  87 }
  88 EXPORT_SYMBOL_GPL(is_uv_system);
  89
  90 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  91 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  92
  93 struct uv_blade_info *uv_blade_info;
  94 EXPORT_SYMBOL_GPL(uv_blade_info);
  95
  96 short *uv_node_to_blade;
  97 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  98
  99 short *uv_cpu_to_blade;
 100 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
 101
 102 short uv_possible_blades;
 103 EXPORT_SYMBOL_GPL(uv_possible_blades);
 104
 105 unsigned long sn_rtc_cycles_per_second;
 106 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 107
 108 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
 109
 110 static const struct cpumask *uv_target_cpus(void)
 111 {
 112         return cpumask_of(0);
 113 }
 114
 115 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
 116 {
 117         cpumask_clear(retmask);
 118         cpumask_set_cpu(cpu, retmask);
 119 }
 120
 121 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 122 {
 123 #ifdef CONFIG_SMP
 124         unsigned long val;
 125         int pnode;
 126
 127         pnode = uv_apicid_to_pnode(phys_apicid);
 128         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 129             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 130             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 131             APIC_DM_INIT;
 132         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 133         mdelay(10);
 134
 135         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 136             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 137             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 138             APIC_DM_STARTUP;
 139         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 140
 141         atomic_set(&init_deasserted, 1);
 142 #endif
 143         return 0;
 144 }
 145
 146 static void uv_send_IPI_one(int cpu, int vector)
 147 {
 148         unsigned long apicid;
 149         int pnode;
 150
 151         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 152         pnode = uv_apicid_to_pnode(apicid);
 153         uv_hub_send_ipi(pnode, apicid, vector);
 154 }
 155
 156 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 157 {
 158         unsigned int cpu;
 159
 160         for_each_cpu(cpu, mask)
 161                 uv_send_IPI_one(cpu, vector);
 162 }
 163
 164 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 165 {
 166         unsigned int this_cpu = smp_processor_id();
 167         unsigned int cpu;
 168
 169         for_each_cpu(cpu, mask) {
 170                 if (cpu != this_cpu)
 171                         uv_send_IPI_one(cpu, vector);
 172         }
 173 }
 174
 175 static void uv_send_IPI_allbutself(int vector)
 176 {
 177         unsigned int this_cpu = smp_processor_id();
 178         unsigned int cpu;
 179
 180         for_each_online_cpu(cpu) {
 181                 if (cpu != this_cpu)
 182                         uv_send_IPI_one(cpu, vector);
 183         }
 184 }
 185
 186 static void uv_send_IPI_all(int vector)
 187 {
 188         uv_send_IPI_mask(cpu_online_mask, vector);
 189 }
 190
 191 static int uv_apic_id_registered(void)
 192 {
 193         return 1;
 194 }
 195
 196 static void uv_init_apic_ldr(void)
 197 {
 198 }
 199
 200 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 201 {
 202         /*
 203          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 204          * May as well be the first.
 205          */
 206         int cpu = cpumask_first(cpumask);
 207
 208         if ((unsigned)cpu < nr_cpu_ids)
 209                 return per_cpu(x86_cpu_to_apicid, cpu);
 210         else
 211                 return BAD_APICID;
 212 }
 213
 214 static unsigned int
 215 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 216                           const struct cpumask *andmask)
 217 {
 218         int cpu;
 219
 220         /*
 221          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 222          * May as well be the first.
 223          */
 224         for_each_cpu_and(cpu, cpumask, andmask) {
 225                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 226                         break;
 227         }
 228         if (cpu < nr_cpu_ids)
 229                 return per_cpu(x86_cpu_to_apicid, cpu);
 230
 231         return BAD_APICID;
 232 }
 233
 234 static unsigned int x2apic_get_apic_id(unsigned long x)
 235 {
 236         unsigned int id;
 237
 238         WARN_ON(preemptible() && num_online_cpus() > 1);
 239         id = x | __get_cpu_var(x2apic_extra_bits);
 240
 241         return id;
 242 }
 243
 244 static unsigned long set_apic_id(unsigned int id)
 245 {
 246         unsigned long x;
 247
 248         /* maskout x2apic_extra_bits ? */
 249         x = id;
 250         return x;
 251 }
 252
 253 static unsigned int uv_read_apic_id(void)
 254 {
 255
 256         return x2apic_get_apic_id(apic_read(APIC_ID));
 257 }
 258
 259 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 260 {
 261         return uv_read_apic_id() >> index_msb;
 262 }
 263
 264 static void uv_send_IPI_self(int vector)
 265 {
 266         apic_write(APIC_SELF_IPI, vector);
 267 }
 268
 269 struct apic __refdata apic_x2apic_uv_x = {
 270
 271         .name                           = "UV large system",
 272         .probe                          = NULL,
 273         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 274         .apic_id_registered             = uv_apic_id_registered,
 275
 276         .irq_delivery_mode              = dest_Fixed,
 277         .irq_dest_mode                  = 0, /* physical */
 278
 279         .target_cpus                    = uv_target_cpus,
 280         .disable_esr                    = 0,
 281         .dest_logical                   = APIC_DEST_LOGICAL,
 282         .check_apicid_used              = NULL,
 283         .check_apicid_present           = NULL,
 284
 285         .vector_allocation_domain       = uv_vector_allocation_domain,
 286         .init_apic_ldr                  = uv_init_apic_ldr,
 287
 288         .ioapic_phys_id_map             = NULL,
 289         .setup_apic_routing             = NULL,
 290         .multi_timer_check              = NULL,
 291         .apicid_to_node                 = NULL,
 292         .cpu_to_logical_apicid          = NULL,
 293         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 294         .apicid_to_cpu_present          = NULL,
 295         .setup_portio_remap             = NULL,
 296         .check_phys_apicid_present      = default_check_phys_apicid_present,
 297         .enable_apic_mode               = NULL,
 298         .phys_pkg_id                    = uv_phys_pkg_id,
 299         .mps_oem_check                  = NULL,
 300
 301         .get_apic_id                    = x2apic_get_apic_id,
 302         .set_apic_id                    = set_apic_id,
 303         .apic_id_mask                   = 0xFFFFFFFFu,
 304
 305         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
 306         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 307
 308         .send_IPI_mask                  = uv_send_IPI_mask,
 309         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 310         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 311         .send_IPI_all                   = uv_send_IPI_all,
 312         .send_IPI_self                  = uv_send_IPI_self,
 313
 314         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 315         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 316         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 317         .wait_for_init_deassert         = NULL,
 318         .smp_callin_clear_local_apic    = NULL,
 319         .inquire_remote_apic            = NULL,
 320
 321         .read                           = native_apic_msr_read,
 322         .write                          = native_apic_msr_write,
 323         .icr_read                       = native_x2apic_icr_read,
 324         .icr_write                      = native_x2apic_icr_write,
 325         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 326         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 327 };
 328
 329 static __cpuinit void set_x2apic_extra_bits(int pnode)
 330 {
 331         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 332 }
 333
 334 /*
 335  * Called on boot cpu.
 336  */
 337 static __init int boot_pnode_to_blade(int pnode)
 338 {
 339         int blade;
 340
 341         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 342                 if (pnode == uv_blade_info[blade].pnode)
 343                         return blade;
 344         BUG();
 345 }
 346
 347 struct redir_addr {
 348         unsigned long redirect;
 349         unsigned long alias;
 350 };
 351
 352 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 353
 354 static __initdata struct redir_addr redir_addrs[] = {
 355         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 356         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 357         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 358 };
 359
 360 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 361 {
 362         union uvh_si_alias0_overlay_config_u alias;
 363         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 364         int i;
 365
 366         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 367                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 368                 if (alias.s.enable && alias.s.base == 0) {
 369                         *size = (1UL << alias.s.m_alias);
 370                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 371                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 372                         return;
 373                 }
 374         }
 375         *base = *size = 0;
 376 }
 377
 378 enum map_type {map_wb, map_uc};
 379
 380 static __init void map_high(char *id, unsigned long base, int shift,
 381                             int max_pnode, enum map_type map_type)
 382 {
 383         unsigned long bytes, paddr;
 384
 385         paddr = base << shift;
 386         bytes = (1UL << shift) * (max_pnode + 1);
 387         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 388                                                 paddr + bytes);
 389         if (map_type == map_uc)
 390                 init_extra_mapping_uc(paddr, bytes);
 391         else
 392                 init_extra_mapping_wb(paddr, bytes);
 393
 394 }
 395 static __init void map_gru_high(int max_pnode)
 396 {
 397         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 398         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 399
 400         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 401         if (gru.s.enable) {
 402                 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
 403                 gru_start_paddr = ((u64)gru.s.base << shift);
 404                 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 405
 406         }
 407 }
 408
 409 static __init void map_mmr_high(int max_pnode)
 410 {
 411         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 412         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 413
 414         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 415         if (mmr.s.enable)
 416                 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
 417 }
 418
 419 static __init void map_mmioh_high(int max_pnode)
 420 {
 421         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 422         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 423
 424         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 425         if (mmioh.s.enable)
 426                 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
 427 }
 428
 429 static __init void map_low_mmrs(void)
 430 {
 431         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 432         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 433 }
 434
 435 static __init void uv_rtc_init(void)
 436 {
 437         long status;
 438         u64 ticks_per_sec;
 439
 440         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 441                                         &ticks_per_sec);
 442         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 443                 printk(KERN_WARNING
 444                         "unable to determine platform RTC clock frequency, "
 445                         "guessing.\n");
 446                 /* BIOS gives wrong value for clock freq. so guess */
 447                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 448         } else
 449                 sn_rtc_cycles_per_second = ticks_per_sec;
 450 }
 451
 452 /*
 453  * percpu heartbeat timer
 454  */
 455 static void uv_heartbeat(unsigned long ignored)
 456 {
 457         struct timer_list *timer = &uv_hub_info->scir.timer;
 458         unsigned char bits = uv_hub_info->scir.state;
 459
 460         /* flip heartbeat bit */
 461         bits ^= SCIR_CPU_HEARTBEAT;
 462
 463         /* is this cpu idle? */
 464         if (idle_cpu(raw_smp_processor_id()))
 465                 bits &= ~SCIR_CPU_ACTIVITY;
 466         else
 467                 bits |= SCIR_CPU_ACTIVITY;
 468
 469         /* update system controller interface reg */
 470         uv_set_scir_bits(bits);
 471
 472         /* enable next timer period */
 473         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 474 }
 475
 476 static void __cpuinit uv_heartbeat_enable(int cpu)
 477 {
 478         if (!uv_cpu_hub_info(cpu)->scir.enabled) {
 479                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 480
 481                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 482                 setup_timer(timer, uv_heartbeat, cpu);
 483                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 484                 add_timer_on(timer, cpu);
 485                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 486         }
 487
 488         /* check boot cpu */
 489         if (!uv_cpu_hub_info(0)->scir.enabled)
 490                 uv_heartbeat_enable(0);
 491 }
 492
 493 #ifdef CONFIG_HOTPLUG_CPU
 494 static void __cpuinit uv_heartbeat_disable(int cpu)
 495 {
 496         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 497                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 498                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 499         }
 500         uv_set_cpu_scir_bits(cpu, 0xff);
 501 }
 502
 503 /*
 504  * cpu hotplug notifier
 505  */
 506 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 507                                        unsigned long action, void *hcpu)
 508 {
 509         long cpu = (long)hcpu;
 510
 511         switch (action) {
 512         case CPU_ONLINE:
 513                 uv_heartbeat_enable(cpu);
 514                 break;
 515         case CPU_DOWN_PREPARE:
 516                 uv_heartbeat_disable(cpu);
 517                 break;
 518         default:
 519                 break;
 520         }
 521         return NOTIFY_OK;
 522 }
 523
 524 static __init void uv_scir_register_cpu_notifier(void)
 525 {
 526         hotcpu_notifier(uv_scir_cpu_notify, 0);
 527 }
 528
 529 #else /* !CONFIG_HOTPLUG_CPU */
 530
 531 static __init void uv_scir_register_cpu_notifier(void)
 532 {
 533 }
 534
 535 static __init int uv_init_heartbeat(void)
 536 {
 537         int cpu;
 538
 539         if (is_uv_system())
 540                 for_each_online_cpu(cpu)
 541                         uv_heartbeat_enable(cpu);
 542         return 0;
 543 }
 544
 545 late_initcall(uv_init_heartbeat);
 546
 547 #endif /* !CONFIG_HOTPLUG_CPU */
 548
 549 /*
 550  * Called on each cpu to initialize the per_cpu UV data area.
 551  * FIXME: hotplug not supported yet
 552  */
 553 void __cpuinit uv_cpu_init(void)
 554 {
 555         /* CPU 0 initilization will be done via uv_system_init. */
 556         if (!uv_blade_info)
 557                 return;
 558
 559         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 560
 561         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 562                 set_x2apic_extra_bits(uv_hub_info->pnode);
 563 }
 564
 565
 566 void __init uv_system_init(void)
 567 {
 568         union uvh_si_addr_map_config_u m_n_config;
 569         union uvh_node_id_u node_id;
 570         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 571         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 572         int gnode_extra, max_pnode = 0;
 573         unsigned long mmr_base, present, paddr;
 574         unsigned short pnode_mask;
 575
 576         map_low_mmrs();
 577
 578         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 579         m_val = m_n_config.s.m_skt;
 580         n_val = m_n_config.s.n_skt;
 581         mmr_base =
 582             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 583             ~UV_MMR_ENABLE;
 584         pnode_mask = (1 << n_val) - 1;
 585         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 586         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
 587         gnode_upper = ((unsigned long)gnode_extra  << m_val);
 588         printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
 589                         n_val, m_val, gnode_upper, gnode_extra);
 590
 591         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 592
 593         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 594                 uv_possible_blades +=
 595                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 596         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 597
 598         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 599         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 600         BUG_ON(!uv_blade_info);
 601         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 602                 uv_blade_info[blade].memory_nid = -1;
 603
 604         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 605
 606         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 607         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 608         BUG_ON(!uv_node_to_blade);
 609         memset(uv_node_to_blade, 255, bytes);
 610
 611         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 612         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 613         BUG_ON(!uv_cpu_to_blade);
 614         memset(uv_cpu_to_blade, 255, bytes);
 615
 616         blade = 0;
 617         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 618                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 619                 for (j = 0; j < 64; j++) {
 620                         if (!test_bit(j, &present))
 621                                 continue;
 622                         uv_blade_info[blade].pnode = (i * 64 + j);
 623                         uv_blade_info[blade].nr_possible_cpus = 0;
 624                         uv_blade_info[blade].nr_online_cpus = 0;
 625                         blade++;
 626                 }
 627         }
 628
 629         uv_bios_init();
 630         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
 631                             &sn_coherency_id, &sn_region_size);
 632         uv_rtc_init();
 633
 634         for_each_present_cpu(cpu) {
 635                 nid = cpu_to_node(cpu);
 636                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 637                 blade = boot_pnode_to_blade(pnode);
 638                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 639                 uv_blade_info[blade].nr_possible_cpus++;
 640
 641                 /* Any node on the blade, else will contain -1. */
 642                 uv_blade_info[blade].memory_nid = nid;
 643
 644                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 645                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 646                 uv_cpu_hub_info(cpu)->m_val = m_val;
 647                 uv_cpu_hub_info(cpu)->n_val = n_val;
 648                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 649                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 650                 uv_cpu_hub_info(cpu)->pnode = pnode;
 651                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
 652                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 653                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 654                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 655                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 656                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 657                 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;
 658                 uv_node_to_blade[nid] = blade;
 659                 uv_cpu_to_blade[cpu] = blade;
 660                 max_pnode = max(pnode, max_pnode);
 661
 662                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
 663                         "lcpu %d, blade %d\n",
 664                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 665                         lcpu, blade);
 666         }
 667
 668         /* Add blade/pnode info for nodes without cpus */
 669         for_each_online_node(nid) {
 670                 if (uv_node_to_blade[nid] >= 0)
 671                         continue;
 672                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
 673                 paddr = uv_soc_phys_ram_to_gpa(paddr);
 674                 pnode = (paddr >> m_val) & pnode_mask;
 675                 blade = boot_pnode_to_blade(pnode);
 676                 uv_node_to_blade[nid] = blade;
 677                 max_pnode = max(pnode, max_pnode);
 678         }
 679
 680         map_gru_high(max_pnode);
 681         map_mmr_high(max_pnode);
 682         map_mmioh_high(max_pnode);
 683
 684         uv_cpu_init();
 685         uv_scir_register_cpu_notifier();
 686         proc_mkdir("sgi_uv", NULL);
 687 }