x86, UV: uv_irq.c: Fix all sparse warnings
[sfrench/cifs-2.6.git] / arch / x86 / kernel / apic / x2apic_uv_x.c
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * SGI UV APIC functions (note: not an Intel compatible APIC)
7  *
8  * Copyright (C) 2007-2009 Silicon Graphics, Inc. All rights reserved.
9  */
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/cpu.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/pci.h>
24 #include <linux/kdebug.h>
25
26 #include <asm/uv/uv_mmrs.h>
27 #include <asm/uv/uv_hub.h>
28 #include <asm/current.h>
29 #include <asm/pgtable.h>
30 #include <asm/uv/bios.h>
31 #include <asm/uv/uv.h>
32 #include <asm/apic.h>
33 #include <asm/ipi.h>
34 #include <asm/smp.h>
35 #include <asm/x86_init.h>
36
37 DEFINE_PER_CPU(int, x2apic_extra_bits);
38
39 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
40
41 static enum uv_system_type uv_system_type;
42 static u64 gru_start_paddr, gru_end_paddr;
43 int uv_min_hub_revision_id;
44 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
45 static DEFINE_SPINLOCK(uv_nmi_lock);
46
47 static inline bool is_GRU_range(u64 start, u64 end)
48 {
49         return start >= gru_start_paddr && end <= gru_end_paddr;
50 }
51
52 static bool uv_is_untracked_pat_range(u64 start, u64 end)
53 {
54         return is_ISA_range(start, end) || is_GRU_range(start, end);
55 }
56
57 static int early_get_nodeid(void)
58 {
59         union uvh_node_id_u node_id;
60         unsigned long *mmr;
61
62         mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr));
63         node_id.v = *mmr;
64         early_iounmap(mmr, sizeof(*mmr));
65
66         /* Currently, all blades have same revision number */
67         uv_min_hub_revision_id = node_id.s.revision;
68
69         return node_id.s.node_id;
70 }
71
72 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
73 {
74         int nodeid;
75
76         if (!strcmp(oem_id, "SGI")) {
77                 nodeid = early_get_nodeid();
78                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
79                 x86_platform.nmi_init = uv_nmi_init;
80                 if (!strcmp(oem_table_id, "UVL"))
81                         uv_system_type = UV_LEGACY_APIC;
82                 else if (!strcmp(oem_table_id, "UVX"))
83                         uv_system_type = UV_X2APIC;
84                 else if (!strcmp(oem_table_id, "UVH")) {
85                         __get_cpu_var(x2apic_extra_bits) =
86                                 nodeid << (UV_APIC_PNODE_SHIFT - 1);
87                         uv_system_type = UV_NON_UNIQUE_APIC;
88                         return 1;
89                 }
90         }
91         return 0;
92 }
93
94 enum uv_system_type get_uv_system_type(void)
95 {
96         return uv_system_type;
97 }
98
99 int is_uv_system(void)
100 {
101         return uv_system_type != UV_NONE;
102 }
103 EXPORT_SYMBOL_GPL(is_uv_system);
104
105 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
106 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
107
108 struct uv_blade_info *uv_blade_info;
109 EXPORT_SYMBOL_GPL(uv_blade_info);
110
111 short *uv_node_to_blade;
112 EXPORT_SYMBOL_GPL(uv_node_to_blade);
113
114 short *uv_cpu_to_blade;
115 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
116
117 short uv_possible_blades;
118 EXPORT_SYMBOL_GPL(uv_possible_blades);
119
120 unsigned long sn_rtc_cycles_per_second;
121 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
122
123 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
124
125 static const struct cpumask *uv_target_cpus(void)
126 {
127         return cpumask_of(0);
128 }
129
130 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
131 {
132         cpumask_clear(retmask);
133         cpumask_set_cpu(cpu, retmask);
134 }
135
136 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
137 {
138 #ifdef CONFIG_SMP
139         unsigned long val;
140         int pnode;
141
142         pnode = uv_apicid_to_pnode(phys_apicid);
143         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
144             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
145             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
146             APIC_DM_INIT;
147         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
148         mdelay(10);
149
150         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
151             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
152             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
153             APIC_DM_STARTUP;
154         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
155
156         atomic_set(&init_deasserted, 1);
157 #endif
158         return 0;
159 }
160
161 static void uv_send_IPI_one(int cpu, int vector)
162 {
163         unsigned long apicid;
164         int pnode;
165
166         apicid = per_cpu(x86_cpu_to_apicid, cpu);
167         pnode = uv_apicid_to_pnode(apicid);
168         uv_hub_send_ipi(pnode, apicid, vector);
169 }
170
171 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
172 {
173         unsigned int cpu;
174
175         for_each_cpu(cpu, mask)
176                 uv_send_IPI_one(cpu, vector);
177 }
178
179 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
180 {
181         unsigned int this_cpu = smp_processor_id();
182         unsigned int cpu;
183
184         for_each_cpu(cpu, mask) {
185                 if (cpu != this_cpu)
186                         uv_send_IPI_one(cpu, vector);
187         }
188 }
189
190 static void uv_send_IPI_allbutself(int vector)
191 {
192         unsigned int this_cpu = smp_processor_id();
193         unsigned int cpu;
194
195         for_each_online_cpu(cpu) {
196                 if (cpu != this_cpu)
197                         uv_send_IPI_one(cpu, vector);
198         }
199 }
200
201 static void uv_send_IPI_all(int vector)
202 {
203         uv_send_IPI_mask(cpu_online_mask, vector);
204 }
205
206 static int uv_apic_id_registered(void)
207 {
208         return 1;
209 }
210
211 static void uv_init_apic_ldr(void)
212 {
213 }
214
215 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
216 {
217         /*
218          * We're using fixed IRQ delivery, can only return one phys APIC ID.
219          * May as well be the first.
220          */
221         int cpu = cpumask_first(cpumask);
222
223         if ((unsigned)cpu < nr_cpu_ids)
224                 return per_cpu(x86_cpu_to_apicid, cpu);
225         else
226                 return BAD_APICID;
227 }
228
229 static unsigned int
230 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
231                           const struct cpumask *andmask)
232 {
233         int cpu;
234
235         /*
236          * We're using fixed IRQ delivery, can only return one phys APIC ID.
237          * May as well be the first.
238          */
239         for_each_cpu_and(cpu, cpumask, andmask) {
240                 if (cpumask_test_cpu(cpu, cpu_online_mask))
241                         break;
242         }
243         return per_cpu(x86_cpu_to_apicid, cpu);
244 }
245
246 static unsigned int x2apic_get_apic_id(unsigned long x)
247 {
248         unsigned int id;
249
250         WARN_ON(preemptible() && num_online_cpus() > 1);
251         id = x | __get_cpu_var(x2apic_extra_bits);
252
253         return id;
254 }
255
256 static unsigned long set_apic_id(unsigned int id)
257 {
258         unsigned long x;
259
260         /* maskout x2apic_extra_bits ? */
261         x = id;
262         return x;
263 }
264
265 static unsigned int uv_read_apic_id(void)
266 {
267
268         return x2apic_get_apic_id(apic_read(APIC_ID));
269 }
270
271 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
272 {
273         return uv_read_apic_id() >> index_msb;
274 }
275
276 static void uv_send_IPI_self(int vector)
277 {
278         apic_write(APIC_SELF_IPI, vector);
279 }
280
281 struct apic __refdata apic_x2apic_uv_x = {
282
283         .name                           = "UV large system",
284         .probe                          = NULL,
285         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
286         .apic_id_registered             = uv_apic_id_registered,
287
288         .irq_delivery_mode              = dest_Fixed,
289         .irq_dest_mode                  = 0, /* physical */
290
291         .target_cpus                    = uv_target_cpus,
292         .disable_esr                    = 0,
293         .dest_logical                   = APIC_DEST_LOGICAL,
294         .check_apicid_used              = NULL,
295         .check_apicid_present           = NULL,
296
297         .vector_allocation_domain       = uv_vector_allocation_domain,
298         .init_apic_ldr                  = uv_init_apic_ldr,
299
300         .ioapic_phys_id_map             = NULL,
301         .setup_apic_routing             = NULL,
302         .multi_timer_check              = NULL,
303         .apicid_to_node                 = NULL,
304         .cpu_to_logical_apicid          = NULL,
305         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
306         .apicid_to_cpu_present          = NULL,
307         .setup_portio_remap             = NULL,
308         .check_phys_apicid_present      = default_check_phys_apicid_present,
309         .enable_apic_mode               = NULL,
310         .phys_pkg_id                    = uv_phys_pkg_id,
311         .mps_oem_check                  = NULL,
312
313         .get_apic_id                    = x2apic_get_apic_id,
314         .set_apic_id                    = set_apic_id,
315         .apic_id_mask                   = 0xFFFFFFFFu,
316
317         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
318         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
319
320         .send_IPI_mask                  = uv_send_IPI_mask,
321         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
322         .send_IPI_allbutself            = uv_send_IPI_allbutself,
323         .send_IPI_all                   = uv_send_IPI_all,
324         .send_IPI_self                  = uv_send_IPI_self,
325
326         .wakeup_secondary_cpu           = uv_wakeup_secondary,
327         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
328         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
329         .wait_for_init_deassert         = NULL,
330         .smp_callin_clear_local_apic    = NULL,
331         .inquire_remote_apic            = NULL,
332
333         .read                           = native_apic_msr_read,
334         .write                          = native_apic_msr_write,
335         .icr_read                       = native_x2apic_icr_read,
336         .icr_write                      = native_x2apic_icr_write,
337         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
338         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
339 };
340
341 static __cpuinit void set_x2apic_extra_bits(int pnode)
342 {
343         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
344 }
345
346 /*
347  * Called on boot cpu.
348  */
349 static __init int boot_pnode_to_blade(int pnode)
350 {
351         int blade;
352
353         for (blade = 0; blade < uv_num_possible_blades(); blade++)
354                 if (pnode == uv_blade_info[blade].pnode)
355                         return blade;
356         BUG();
357 }
358
359 struct redir_addr {
360         unsigned long redirect;
361         unsigned long alias;
362 };
363
364 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
365
366 static __initdata struct redir_addr redir_addrs[] = {
367         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
368         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
369         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
370 };
371
372 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
373 {
374         union uvh_si_alias0_overlay_config_u alias;
375         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
376         int i;
377
378         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
379                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
380                 if (alias.s.enable && alias.s.base == 0) {
381                         *size = (1UL << alias.s.m_alias);
382                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
383                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
384                         return;
385                 }
386         }
387         *base = *size = 0;
388 }
389
390 enum map_type {map_wb, map_uc};
391
392 static __init void map_high(char *id, unsigned long base, int pshift,
393                         int bshift, int max_pnode, enum map_type map_type)
394 {
395         unsigned long bytes, paddr;
396
397         paddr = base << pshift;
398         bytes = (1UL << bshift) * (max_pnode + 1);
399         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
400                                                 paddr + bytes);
401         if (map_type == map_uc)
402                 init_extra_mapping_uc(paddr, bytes);
403         else
404                 init_extra_mapping_wb(paddr, bytes);
405
406 }
407 static __init void map_gru_high(int max_pnode)
408 {
409         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
410         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
411
412         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
413         if (gru.s.enable) {
414                 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
415                 gru_start_paddr = ((u64)gru.s.base << shift);
416                 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
417
418         }
419 }
420
421 static __init void map_mmr_high(int max_pnode)
422 {
423         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
424         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
425
426         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
427         if (mmr.s.enable)
428                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
429 }
430
431 static __init void map_mmioh_high(int max_pnode)
432 {
433         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
434         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
435
436         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
437         if (mmioh.s.enable)
438                 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
439                         max_pnode, map_uc);
440 }
441
442 static __init void map_low_mmrs(void)
443 {
444         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
445         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
446 }
447
448 static __init void uv_rtc_init(void)
449 {
450         long status;
451         u64 ticks_per_sec;
452
453         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
454                                         &ticks_per_sec);
455         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
456                 printk(KERN_WARNING
457                         "unable to determine platform RTC clock frequency, "
458                         "guessing.\n");
459                 /* BIOS gives wrong value for clock freq. so guess */
460                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
461         } else
462                 sn_rtc_cycles_per_second = ticks_per_sec;
463 }
464
465 /*
466  * percpu heartbeat timer
467  */
468 static void uv_heartbeat(unsigned long ignored)
469 {
470         struct timer_list *timer = &uv_hub_info->scir.timer;
471         unsigned char bits = uv_hub_info->scir.state;
472
473         /* flip heartbeat bit */
474         bits ^= SCIR_CPU_HEARTBEAT;
475
476         /* is this cpu idle? */
477         if (idle_cpu(raw_smp_processor_id()))
478                 bits &= ~SCIR_CPU_ACTIVITY;
479         else
480                 bits |= SCIR_CPU_ACTIVITY;
481
482         /* update system controller interface reg */
483         uv_set_scir_bits(bits);
484
485         /* enable next timer period */
486         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
487 }
488
489 static void __cpuinit uv_heartbeat_enable(int cpu)
490 {
491         while (!uv_cpu_hub_info(cpu)->scir.enabled) {
492                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
493
494                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
495                 setup_timer(timer, uv_heartbeat, cpu);
496                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
497                 add_timer_on(timer, cpu);
498                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
499
500                 /* also ensure that boot cpu is enabled */
501                 cpu = 0;
502         }
503 }
504
505 #ifdef CONFIG_HOTPLUG_CPU
506 static void __cpuinit uv_heartbeat_disable(int cpu)
507 {
508         if (uv_cpu_hub_info(cpu)->scir.enabled) {
509                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
510                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
511         }
512         uv_set_cpu_scir_bits(cpu, 0xff);
513 }
514
515 /*
516  * cpu hotplug notifier
517  */
518 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
519                                        unsigned long action, void *hcpu)
520 {
521         long cpu = (long)hcpu;
522
523         switch (action) {
524         case CPU_ONLINE:
525                 uv_heartbeat_enable(cpu);
526                 break;
527         case CPU_DOWN_PREPARE:
528                 uv_heartbeat_disable(cpu);
529                 break;
530         default:
531                 break;
532         }
533         return NOTIFY_OK;
534 }
535
536 static __init void uv_scir_register_cpu_notifier(void)
537 {
538         hotcpu_notifier(uv_scir_cpu_notify, 0);
539 }
540
541 #else /* !CONFIG_HOTPLUG_CPU */
542
543 static __init void uv_scir_register_cpu_notifier(void)
544 {
545 }
546
547 static __init int uv_init_heartbeat(void)
548 {
549         int cpu;
550
551         if (is_uv_system())
552                 for_each_online_cpu(cpu)
553                         uv_heartbeat_enable(cpu);
554         return 0;
555 }
556
557 late_initcall(uv_init_heartbeat);
558
559 #endif /* !CONFIG_HOTPLUG_CPU */
560
561 /* Direct Legacy VGA I/O traffic to designated IOH */
562 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
563                       unsigned int command_bits, bool change_bridge)
564 {
565         int domain, bus, rc;
566
567         PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n",
568                         pdev->devfn, decode, command_bits, change_bridge);
569
570         if (!change_bridge)
571                 return 0;
572
573         if ((command_bits & PCI_COMMAND_IO) == 0)
574                 return 0;
575
576         domain = pci_domain_nr(pdev->bus);
577         bus = pdev->bus->number;
578
579         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
580         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
581
582         return rc;
583 }
584
585 /*
586  * Called on each cpu to initialize the per_cpu UV data area.
587  * FIXME: hotplug not supported yet
588  */
589 void __cpuinit uv_cpu_init(void)
590 {
591         /* CPU 0 initilization will be done via uv_system_init. */
592         if (!uv_blade_info)
593                 return;
594
595         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
596
597         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
598                 set_x2apic_extra_bits(uv_hub_info->pnode);
599 }
600
601 /*
602  * When NMI is received, print a stack trace.
603  */
604 int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
605 {
606         if (reason != DIE_NMI_IPI)
607                 return NOTIFY_OK;
608         /*
609          * Use a lock so only one cpu prints at a time
610          * to prevent intermixed output.
611          */
612         spin_lock(&uv_nmi_lock);
613         pr_info("NMI stack dump cpu %u:\n", smp_processor_id());
614         dump_stack();
615         spin_unlock(&uv_nmi_lock);
616
617         return NOTIFY_STOP;
618 }
619
620 static struct notifier_block uv_dump_stack_nmi_nb = {
621         .notifier_call  = uv_handle_nmi
622 };
623
624 void uv_register_nmi_notifier(void)
625 {
626         if (register_die_notifier(&uv_dump_stack_nmi_nb))
627                 printk(KERN_WARNING "UV NMI handler failed to register\n");
628 }
629
630 void uv_nmi_init(void)
631 {
632         unsigned int value;
633
634         /*
635          * Unmask NMI on all cpus
636          */
637         value = apic_read(APIC_LVT1) | APIC_DM_NMI;
638         value &= ~APIC_LVT_MASKED;
639         apic_write(APIC_LVT1, value);
640 }
641
642 void __init uv_system_init(void)
643 {
644         union uvh_si_addr_map_config_u m_n_config;
645         union uvh_node_id_u node_id;
646         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
647         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
648         int gnode_extra, max_pnode = 0;
649         unsigned long mmr_base, present, paddr;
650         unsigned short pnode_mask;
651
652         map_low_mmrs();
653
654         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
655         m_val = m_n_config.s.m_skt;
656         n_val = m_n_config.s.n_skt;
657         mmr_base =
658             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
659             ~UV_MMR_ENABLE;
660         pnode_mask = (1 << n_val) - 1;
661         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
662         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
663         gnode_upper = ((unsigned long)gnode_extra  << m_val);
664         printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
665                         n_val, m_val, gnode_upper, gnode_extra);
666
667         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
668
669         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
670                 uv_possible_blades +=
671                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
672         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
673
674         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
675         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
676         BUG_ON(!uv_blade_info);
677         for (blade = 0; blade < uv_num_possible_blades(); blade++)
678                 uv_blade_info[blade].memory_nid = -1;
679
680         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
681
682         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
683         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
684         BUG_ON(!uv_node_to_blade);
685         memset(uv_node_to_blade, 255, bytes);
686
687         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
688         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
689         BUG_ON(!uv_cpu_to_blade);
690         memset(uv_cpu_to_blade, 255, bytes);
691
692         blade = 0;
693         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
694                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
695                 for (j = 0; j < 64; j++) {
696                         if (!test_bit(j, &present))
697                                 continue;
698                         uv_blade_info[blade].pnode = (i * 64 + j);
699                         uv_blade_info[blade].nr_possible_cpus = 0;
700                         uv_blade_info[blade].nr_online_cpus = 0;
701                         blade++;
702                 }
703         }
704
705         uv_bios_init();
706         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
707                             &sn_region_size, &system_serial_number);
708         uv_rtc_init();
709
710         for_each_present_cpu(cpu) {
711                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
712
713                 nid = cpu_to_node(cpu);
714                 pnode = uv_apicid_to_pnode(apicid);
715                 blade = boot_pnode_to_blade(pnode);
716                 lcpu = uv_blade_info[blade].nr_possible_cpus;
717                 uv_blade_info[blade].nr_possible_cpus++;
718
719                 /* Any node on the blade, else will contain -1. */
720                 uv_blade_info[blade].memory_nid = nid;
721
722                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
723                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
724                 uv_cpu_hub_info(cpu)->m_val = m_val;
725                 uv_cpu_hub_info(cpu)->n_val = n_val;
726                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
727                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
728                 uv_cpu_hub_info(cpu)->pnode = pnode;
729                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
730                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
731                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
732                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
733                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
734                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
735                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
736                 uv_node_to_blade[nid] = blade;
737                 uv_cpu_to_blade[cpu] = blade;
738                 max_pnode = max(pnode, max_pnode);
739         }
740
741         /* Add blade/pnode info for nodes without cpus */
742         for_each_online_node(nid) {
743                 if (uv_node_to_blade[nid] >= 0)
744                         continue;
745                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
746                 paddr = uv_soc_phys_ram_to_gpa(paddr);
747                 pnode = (paddr >> m_val) & pnode_mask;
748                 blade = boot_pnode_to_blade(pnode);
749                 uv_node_to_blade[nid] = blade;
750                 max_pnode = max(pnode, max_pnode);
751         }
752
753         map_gru_high(max_pnode);
754         map_mmr_high(max_pnode);
755         map_mmioh_high(max_pnode);
756
757         uv_cpu_init();
758         uv_scir_register_cpu_notifier();
759         uv_register_nmi_notifier();
760         proc_mkdir("sgi_uv", NULL);
761
762         /* register Legacy VGA I/O redirection handler */
763         pci_register_set_vga_state(uv_set_vga_state);
764 }