Merge branch 'acpica' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux...
[sfrench/cifs-2.6.git] / arch / x86 / kernel / acpi / cstate.c
1 /*
2  * Copyright (C) 2005 Intel Corporation
3  *      Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
4  *      - Added _PDC for SMP C-states on Intel CPUs
5  */
6
7 #include <linux/kernel.h>
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/acpi.h>
11 #include <linux/cpu.h>
12 #include <linux/sched.h>
13
14 #include <acpi/processor.h>
15 #include <asm/acpi.h>
16
17 /*
18  * Initialize bm_flags based on the CPU cache properties
19  * On SMP it depends on cache configuration
20  * - When cache is not shared among all CPUs, we flush cache
21  *   before entering C3.
22  * - When cache is shared among all CPUs, we use bm_check
23  *   mechanism as in UP case
24  *
25  * This routine is called only after all the CPUs are online
26  */
27 void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
28                                         unsigned int cpu)
29 {
30         struct cpuinfo_x86 *c = &cpu_data(cpu);
31
32         flags->bm_check = 0;
33         if (num_online_cpus() == 1)
34                 flags->bm_check = 1;
35         else if (c->x86_vendor == X86_VENDOR_INTEL) {
36                 /*
37                  * Today all MP CPUs that support C3 share cache.
38                  * And caches should not be flushed by software while
39                  * entering C3 type state.
40                  */
41                 flags->bm_check = 1;
42         }
43
44         /*
45          * On all recent Intel platforms, ARB_DISABLE is a nop.
46          * So, set bm_control to zero to indicate that ARB_DISABLE
47          * is not required while entering C3 type state on
48          * P4, Core and beyond CPUs
49          */
50         if (c->x86_vendor == X86_VENDOR_INTEL &&
51             (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
52                         flags->bm_control = 0;
53 }
54 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
55
56 /* The code below handles cstate entry with monitor-mwait pair on Intel*/
57
58 struct cstate_entry {
59         struct {
60                 unsigned int eax;
61                 unsigned int ecx;
62         } states[ACPI_PROCESSOR_MAX_POWER];
63 };
64 static struct cstate_entry *cpu_cstate_entry;   /* per CPU ptr */
65
66 static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
67
68 #define MWAIT_SUBSTATE_MASK     (0xf)
69 #define MWAIT_CSTATE_MASK       (0xf)
70 #define MWAIT_SUBSTATE_SIZE     (4)
71
72 #define CPUID_MWAIT_LEAF (5)
73 #define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1)
74 #define CPUID5_ECX_INTERRUPT_BREAK      (0x2)
75
76 #define MWAIT_ECX_INTERRUPT_BREAK       (0x1)
77
78 #define NATIVE_CSTATE_BEYOND_HALT       (2)
79
80 static long acpi_processor_ffh_cstate_probe_cpu(void *_cx)
81 {
82         struct acpi_processor_cx *cx = _cx;
83         long retval;
84         unsigned int eax, ebx, ecx, edx;
85         unsigned int edx_part;
86         unsigned int cstate_type; /* C-state type and not ACPI C-state type */
87         unsigned int num_cstate_subtype;
88
89         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
90
91         /* Check whether this particular cx_type (in CST) is supported or not */
92         cstate_type = ((cx->address >> MWAIT_SUBSTATE_SIZE) &
93                         MWAIT_CSTATE_MASK) + 1;
94         edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE);
95         num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
96
97         retval = 0;
98         if (num_cstate_subtype < (cx->address & MWAIT_SUBSTATE_MASK)) {
99                 retval = -1;
100                 goto out;
101         }
102
103         /* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */
104         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
105             !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) {
106                 retval = -1;
107                 goto out;
108         }
109
110         if (!mwait_supported[cstate_type]) {
111                 mwait_supported[cstate_type] = 1;
112                 printk(KERN_DEBUG
113                         "Monitor-Mwait will be used to enter C-%d "
114                         "state\n", cx->type);
115         }
116         snprintf(cx->desc,
117                         ACPI_CX_DESC_LEN, "ACPI FFH INTEL MWAIT 0x%x",
118                         cx->address);
119 out:
120         return retval;
121 }
122
123 int acpi_processor_ffh_cstate_probe(unsigned int cpu,
124                 struct acpi_processor_cx *cx, struct acpi_power_register *reg)
125 {
126         struct cstate_entry *percpu_entry;
127         struct cpuinfo_x86 *c = &cpu_data(cpu);
128         long retval;
129
130         if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF)
131                 return -1;
132
133         if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
134                 return -1;
135
136         percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
137         percpu_entry->states[cx->index].eax = 0;
138         percpu_entry->states[cx->index].ecx = 0;
139
140         /* Make sure we are running on right CPU */
141
142         retval = work_on_cpu(cpu, acpi_processor_ffh_cstate_probe_cpu, cx);
143         if (retval == 0) {
144                 /* Use the hint in CST */
145                 percpu_entry->states[cx->index].eax = cx->address;
146                 percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
147         }
148         return retval;
149 }
150 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
151
152 void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx)
153 {
154         unsigned int cpu = smp_processor_id();
155         struct cstate_entry *percpu_entry;
156
157         percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
158         mwait_idle_with_hints(percpu_entry->states[cx->index].eax,
159                               percpu_entry->states[cx->index].ecx);
160 }
161 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter);
162
163 static int __init ffh_cstate_init(void)
164 {
165         struct cpuinfo_x86 *c = &boot_cpu_data;
166         if (c->x86_vendor != X86_VENDOR_INTEL)
167                 return -1;
168
169         cpu_cstate_entry = alloc_percpu(struct cstate_entry);
170         return 0;
171 }
172
173 static void __exit ffh_cstate_exit(void)
174 {
175         free_percpu(cpu_cstate_entry);
176         cpu_cstate_entry = NULL;
177 }
178
179 arch_initcall(ffh_cstate_init);
180 __exitcall(ffh_cstate_exit);