perf/x86/intel/uncore: Support CoffeeLake 8th CBOX
[sfrench/cifs-2.6.git] / arch / x86 / events / intel / uncore.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <linux/slab.h>
3 #include <linux/pci.h>
4 #include <asm/apicdef.h>
5
6 #include <linux/perf_event.h>
7 #include "../perf_event.h"
8
9 #define UNCORE_PMU_NAME_LEN             32
10 #define UNCORE_PMU_HRTIMER_INTERVAL     (60LL * NSEC_PER_SEC)
11 #define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)
12
13 #define UNCORE_FIXED_EVENT              0xff
14 #define UNCORE_PMC_IDX_MAX_GENERIC      8
15 #define UNCORE_PMC_IDX_MAX_FIXED        1
16 #define UNCORE_PMC_IDX_MAX_FREERUNNING  1
17 #define UNCORE_PMC_IDX_FIXED            UNCORE_PMC_IDX_MAX_GENERIC
18 #define UNCORE_PMC_IDX_FREERUNNING      (UNCORE_PMC_IDX_FIXED + \
19                                         UNCORE_PMC_IDX_MAX_FIXED)
20 #define UNCORE_PMC_IDX_MAX              (UNCORE_PMC_IDX_FREERUNNING + \
21                                         UNCORE_PMC_IDX_MAX_FREERUNNING)
22
23 #define UNCORE_PCI_DEV_FULL_DATA(dev, func, type, idx)  \
24                 ((dev << 24) | (func << 16) | (type << 8) | idx)
25 #define UNCORE_PCI_DEV_DATA(type, idx)  ((type << 8) | idx)
26 #define UNCORE_PCI_DEV_DEV(data)        ((data >> 24) & 0xff)
27 #define UNCORE_PCI_DEV_FUNC(data)       ((data >> 16) & 0xff)
28 #define UNCORE_PCI_DEV_TYPE(data)       ((data >> 8) & 0xff)
29 #define UNCORE_PCI_DEV_IDX(data)        (data & 0xff)
30 #define UNCORE_EXTRA_PCI_DEV            0xff
31 #define UNCORE_EXTRA_PCI_DEV_MAX        4
32
33 #define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
34
35 struct pci_extra_dev {
36         struct pci_dev *dev[UNCORE_EXTRA_PCI_DEV_MAX];
37 };
38
39 struct intel_uncore_ops;
40 struct intel_uncore_pmu;
41 struct intel_uncore_box;
42 struct uncore_event_desc;
43 struct freerunning_counters;
44
45 struct intel_uncore_type {
46         const char *name;
47         int num_counters;
48         int num_boxes;
49         int perf_ctr_bits;
50         int fixed_ctr_bits;
51         int num_freerunning_types;
52         unsigned perf_ctr;
53         unsigned event_ctl;
54         unsigned event_mask;
55         unsigned event_mask_ext;
56         unsigned fixed_ctr;
57         unsigned fixed_ctl;
58         unsigned box_ctl;
59         unsigned msr_offset;
60         unsigned num_shared_regs:8;
61         unsigned single_fixed:1;
62         unsigned pair_ctr_ctl:1;
63         unsigned *msr_offsets;
64         struct event_constraint unconstrainted;
65         struct event_constraint *constraints;
66         struct intel_uncore_pmu *pmus;
67         struct intel_uncore_ops *ops;
68         struct uncore_event_desc *event_descs;
69         struct freerunning_counters *freerunning;
70         const struct attribute_group *attr_groups[4];
71         struct pmu *pmu; /* for custom pmu ops */
72 };
73
74 #define pmu_group attr_groups[0]
75 #define format_group attr_groups[1]
76 #define events_group attr_groups[2]
77
78 struct intel_uncore_ops {
79         void (*init_box)(struct intel_uncore_box *);
80         void (*exit_box)(struct intel_uncore_box *);
81         void (*disable_box)(struct intel_uncore_box *);
82         void (*enable_box)(struct intel_uncore_box *);
83         void (*disable_event)(struct intel_uncore_box *, struct perf_event *);
84         void (*enable_event)(struct intel_uncore_box *, struct perf_event *);
85         u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
86         int (*hw_config)(struct intel_uncore_box *, struct perf_event *);
87         struct event_constraint *(*get_constraint)(struct intel_uncore_box *,
88                                                    struct perf_event *);
89         void (*put_constraint)(struct intel_uncore_box *, struct perf_event *);
90 };
91
92 struct intel_uncore_pmu {
93         struct pmu                      pmu;
94         char                            name[UNCORE_PMU_NAME_LEN];
95         int                             pmu_idx;
96         int                             func_id;
97         bool                            registered;
98         atomic_t                        activeboxes;
99         struct intel_uncore_type        *type;
100         struct intel_uncore_box         **boxes;
101 };
102
103 struct intel_uncore_extra_reg {
104         raw_spinlock_t lock;
105         u64 config, config1, config2;
106         atomic_t ref;
107 };
108
109 struct intel_uncore_box {
110         int pci_phys_id;
111         int pkgid;      /* Logical package ID */
112         int n_active;   /* number of active events */
113         int n_events;
114         int cpu;        /* cpu to collect events */
115         unsigned long flags;
116         atomic_t refcnt;
117         struct perf_event *events[UNCORE_PMC_IDX_MAX];
118         struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
119         struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
120         unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
121         u64 tags[UNCORE_PMC_IDX_MAX];
122         struct pci_dev *pci_dev;
123         struct intel_uncore_pmu *pmu;
124         u64 hrtimer_duration; /* hrtimer timeout for this box */
125         struct hrtimer hrtimer;
126         struct list_head list;
127         struct list_head active_list;
128         void *io_addr;
129         struct intel_uncore_extra_reg shared_regs[0];
130 };
131
132 /* CFL uncore 8th cbox MSRs */
133 #define CFL_UNC_CBO_7_PERFEVTSEL0               0xf70
134 #define CFL_UNC_CBO_7_PER_CTR0                  0xf76
135
136 #define UNCORE_BOX_FLAG_INITIATED               0
137 /* event config registers are 8-byte apart */
138 #define UNCORE_BOX_FLAG_CTL_OFFS8               1
139 /* CFL 8th CBOX has different MSR space */
140 #define UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS      2
141
142 struct uncore_event_desc {
143         struct kobj_attribute attr;
144         const char *config;
145 };
146
147 struct freerunning_counters {
148         unsigned int counter_base;
149         unsigned int counter_offset;
150         unsigned int box_offset;
151         unsigned int num_counters;
152         unsigned int bits;
153 };
154
155 struct pci2phy_map {
156         struct list_head list;
157         int segment;
158         int pbus_to_physid[256];
159 };
160
161 struct pci2phy_map *__find_pci2phy_map(int segment);
162
163 ssize_t uncore_event_show(struct kobject *kobj,
164                           struct kobj_attribute *attr, char *buf);
165
166 #define INTEL_UNCORE_EVENT_DESC(_name, _config)                 \
167 {                                                               \
168         .attr   = __ATTR(_name, 0444, uncore_event_show, NULL), \
169         .config = _config,                                      \
170 }
171
172 #define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format)                 \
173 static ssize_t __uncore_##_var##_show(struct kobject *kobj,             \
174                                 struct kobj_attribute *attr,            \
175                                 char *page)                             \
176 {                                                                       \
177         BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE);                     \
178         return sprintf(page, _format "\n");                             \
179 }                                                                       \
180 static struct kobj_attribute format_attr_##_var =                       \
181         __ATTR(_name, 0444, __uncore_##_var##_show, NULL)
182
183 static inline bool uncore_pmc_fixed(int idx)
184 {
185         return idx == UNCORE_PMC_IDX_FIXED;
186 }
187
188 static inline bool uncore_pmc_freerunning(int idx)
189 {
190         return idx == UNCORE_PMC_IDX_FREERUNNING;
191 }
192
193 static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
194 {
195         return box->pmu->type->box_ctl;
196 }
197
198 static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
199 {
200         return box->pmu->type->fixed_ctl;
201 }
202
203 static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
204 {
205         return box->pmu->type->fixed_ctr;
206 }
207
208 static inline
209 unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
210 {
211         if (test_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags))
212                 return idx * 8 + box->pmu->type->event_ctl;
213
214         return idx * 4 + box->pmu->type->event_ctl;
215 }
216
217 static inline
218 unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
219 {
220         return idx * 8 + box->pmu->type->perf_ctr;
221 }
222
223 static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
224 {
225         struct intel_uncore_pmu *pmu = box->pmu;
226         return pmu->type->msr_offsets ?
227                 pmu->type->msr_offsets[pmu->pmu_idx] :
228                 pmu->type->msr_offset * pmu->pmu_idx;
229 }
230
231 static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
232 {
233         if (!box->pmu->type->box_ctl)
234                 return 0;
235         return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
236 }
237
238 static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
239 {
240         if (!box->pmu->type->fixed_ctl)
241                 return 0;
242         return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
243 }
244
245 static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
246 {
247         return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
248 }
249
250
251 /*
252  * In the uncore document, there is no event-code assigned to free running
253  * counters. Some events need to be defined to indicate the free running
254  * counters. The events are encoded as event-code + umask-code.
255  *
256  * The event-code for all free running counters is 0xff, which is the same as
257  * the fixed counters.
258  *
259  * The umask-code is used to distinguish a fixed counter and a free running
260  * counter, and different types of free running counters.
261  * - For fixed counters, the umask-code is 0x0X.
262  *   X indicates the index of the fixed counter, which starts from 0.
263  * - For free running counters, the umask-code uses the rest of the space.
264  *   It would bare the format of 0xXY.
265  *   X stands for the type of free running counters, which starts from 1.
266  *   Y stands for the index of free running counters of same type, which
267  *   starts from 0.
268  *
269  * For example, there are three types of IIO free running counters on Skylake
270  * server, IO CLOCKS counters, BANDWIDTH counters and UTILIZATION counters.
271  * The event-code for all the free running counters is 0xff.
272  * 'ioclk' is the first counter of IO CLOCKS. IO CLOCKS is the first type,
273  * which umask-code starts from 0x10.
274  * So 'ioclk' is encoded as event=0xff,umask=0x10
275  * 'bw_in_port2' is the third counter of BANDWIDTH counters. BANDWIDTH is
276  * the second type, which umask-code starts from 0x20.
277  * So 'bw_in_port2' is encoded as event=0xff,umask=0x22
278  */
279 static inline unsigned int uncore_freerunning_idx(u64 config)
280 {
281         return ((config >> 8) & 0xf);
282 }
283
284 #define UNCORE_FREERUNNING_UMASK_START          0x10
285
286 static inline unsigned int uncore_freerunning_type(u64 config)
287 {
288         return ((((config >> 8) - UNCORE_FREERUNNING_UMASK_START) >> 4) & 0xf);
289 }
290
291 static inline
292 unsigned int uncore_freerunning_counter(struct intel_uncore_box *box,
293                                         struct perf_event *event)
294 {
295         unsigned int type = uncore_freerunning_type(event->attr.config);
296         unsigned int idx = uncore_freerunning_idx(event->attr.config);
297         struct intel_uncore_pmu *pmu = box->pmu;
298
299         return pmu->type->freerunning[type].counter_base +
300                pmu->type->freerunning[type].counter_offset * idx +
301                pmu->type->freerunning[type].box_offset * pmu->pmu_idx;
302 }
303
304 static inline
305 unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
306 {
307         if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) {
308                 return CFL_UNC_CBO_7_PERFEVTSEL0 +
309                        (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx);
310         } else {
311                 return box->pmu->type->event_ctl +
312                        (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
313                        uncore_msr_box_offset(box);
314         }
315 }
316
317 static inline
318 unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
319 {
320         if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) {
321                 return CFL_UNC_CBO_7_PER_CTR0 +
322                        (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx);
323         } else {
324                 return box->pmu->type->perf_ctr +
325                        (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
326                        uncore_msr_box_offset(box);
327         }
328 }
329
330 static inline
331 unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
332 {
333         if (box->pci_dev)
334                 return uncore_pci_fixed_ctl(box);
335         else
336                 return uncore_msr_fixed_ctl(box);
337 }
338
339 static inline
340 unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
341 {
342         if (box->pci_dev)
343                 return uncore_pci_fixed_ctr(box);
344         else
345                 return uncore_msr_fixed_ctr(box);
346 }
347
348 static inline
349 unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
350 {
351         if (box->pci_dev)
352                 return uncore_pci_event_ctl(box, idx);
353         else
354                 return uncore_msr_event_ctl(box, idx);
355 }
356
357 static inline
358 unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
359 {
360         if (box->pci_dev)
361                 return uncore_pci_perf_ctr(box, idx);
362         else
363                 return uncore_msr_perf_ctr(box, idx);
364 }
365
366 static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
367 {
368         return box->pmu->type->perf_ctr_bits;
369 }
370
371 static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
372 {
373         return box->pmu->type->fixed_ctr_bits;
374 }
375
376 static inline
377 unsigned int uncore_freerunning_bits(struct intel_uncore_box *box,
378                                      struct perf_event *event)
379 {
380         unsigned int type = uncore_freerunning_type(event->attr.config);
381
382         return box->pmu->type->freerunning[type].bits;
383 }
384
385 static inline int uncore_num_freerunning(struct intel_uncore_box *box,
386                                          struct perf_event *event)
387 {
388         unsigned int type = uncore_freerunning_type(event->attr.config);
389
390         return box->pmu->type->freerunning[type].num_counters;
391 }
392
393 static inline int uncore_num_freerunning_types(struct intel_uncore_box *box,
394                                                struct perf_event *event)
395 {
396         return box->pmu->type->num_freerunning_types;
397 }
398
399 static inline bool check_valid_freerunning_event(struct intel_uncore_box *box,
400                                                  struct perf_event *event)
401 {
402         unsigned int type = uncore_freerunning_type(event->attr.config);
403         unsigned int idx = uncore_freerunning_idx(event->attr.config);
404
405         return (type < uncore_num_freerunning_types(box, event)) &&
406                (idx < uncore_num_freerunning(box, event));
407 }
408
409 static inline int uncore_num_counters(struct intel_uncore_box *box)
410 {
411         return box->pmu->type->num_counters;
412 }
413
414 static inline bool is_freerunning_event(struct perf_event *event)
415 {
416         u64 cfg = event->attr.config;
417
418         return ((cfg & UNCORE_FIXED_EVENT) == UNCORE_FIXED_EVENT) &&
419                (((cfg >> 8) & 0xff) >= UNCORE_FREERUNNING_UMASK_START);
420 }
421
422 static inline void uncore_disable_box(struct intel_uncore_box *box)
423 {
424         if (box->pmu->type->ops->disable_box)
425                 box->pmu->type->ops->disable_box(box);
426 }
427
428 static inline void uncore_enable_box(struct intel_uncore_box *box)
429 {
430         if (box->pmu->type->ops->enable_box)
431                 box->pmu->type->ops->enable_box(box);
432 }
433
434 static inline void uncore_disable_event(struct intel_uncore_box *box,
435                                 struct perf_event *event)
436 {
437         box->pmu->type->ops->disable_event(box, event);
438 }
439
440 static inline void uncore_enable_event(struct intel_uncore_box *box,
441                                 struct perf_event *event)
442 {
443         box->pmu->type->ops->enable_event(box, event);
444 }
445
446 static inline u64 uncore_read_counter(struct intel_uncore_box *box,
447                                 struct perf_event *event)
448 {
449         return box->pmu->type->ops->read_counter(box, event);
450 }
451
452 static inline void uncore_box_init(struct intel_uncore_box *box)
453 {
454         if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
455                 if (box->pmu->type->ops->init_box)
456                         box->pmu->type->ops->init_box(box);
457         }
458 }
459
460 static inline void uncore_box_exit(struct intel_uncore_box *box)
461 {
462         if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
463                 if (box->pmu->type->ops->exit_box)
464                         box->pmu->type->ops->exit_box(box);
465         }
466 }
467
468 static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
469 {
470         return (box->pkgid < 0);
471 }
472
473 static inline struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
474 {
475         return container_of(event->pmu, struct intel_uncore_pmu, pmu);
476 }
477
478 static inline struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
479 {
480         return event->pmu_private;
481 }
482
483 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu);
484 u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event);
485 void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
486 void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
487 void uncore_pmu_event_start(struct perf_event *event, int flags);
488 void uncore_pmu_event_stop(struct perf_event *event, int flags);
489 int uncore_pmu_event_add(struct perf_event *event, int flags);
490 void uncore_pmu_event_del(struct perf_event *event, int flags);
491 void uncore_pmu_event_read(struct perf_event *event);
492 void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event);
493 struct event_constraint *
494 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event);
495 void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event);
496 u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);
497
498 extern struct intel_uncore_type **uncore_msr_uncores;
499 extern struct intel_uncore_type **uncore_pci_uncores;
500 extern struct pci_driver *uncore_pci_driver;
501 extern raw_spinlock_t pci2phy_map_lock;
502 extern struct list_head pci2phy_map_head;
503 extern struct pci_extra_dev *uncore_extra_pci_dev;
504 extern struct event_constraint uncore_constraint_empty;
505
506 /* uncore_snb.c */
507 int snb_uncore_pci_init(void);
508 int ivb_uncore_pci_init(void);
509 int hsw_uncore_pci_init(void);
510 int bdw_uncore_pci_init(void);
511 int skl_uncore_pci_init(void);
512 void snb_uncore_cpu_init(void);
513 void nhm_uncore_cpu_init(void);
514 void skl_uncore_cpu_init(void);
515 int snb_pci2phy_map_init(int devid);
516
517 /* uncore_snbep.c */
518 int snbep_uncore_pci_init(void);
519 void snbep_uncore_cpu_init(void);
520 int ivbep_uncore_pci_init(void);
521 void ivbep_uncore_cpu_init(void);
522 int hswep_uncore_pci_init(void);
523 void hswep_uncore_cpu_init(void);
524 int bdx_uncore_pci_init(void);
525 void bdx_uncore_cpu_init(void);
526 int knl_uncore_pci_init(void);
527 void knl_uncore_cpu_init(void);
528 int skx_uncore_pci_init(void);
529 void skx_uncore_cpu_init(void);
530
531 /* uncore_nhmex.c */
532 void nhmex_uncore_cpu_init(void);