1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86_64/entry.S
5 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
9 * entry.S contains the system-call and fault low-level handling routines.
11 * Some of this is documented in Documentation/x86/entry_64.txt
13 * A note on terminology:
14 * - iret frame: Architecture defined interrupt frame from SS to RIP
15 * at the top of the kernel process stack.
18 * - ENTRY/END: Define functions in the symbol table.
19 * - TRACE_IRQ_*: Trace hardirq state for lock debugging.
20 * - idtentry: Define exception entry points.
22 #include <linux/linkage.h>
23 #include <asm/segment.h>
24 #include <asm/cache.h>
25 #include <asm/errno.h>
26 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/thread_info.h>
30 #include <asm/hw_irq.h>
31 #include <asm/page_types.h>
32 #include <asm/irqflags.h>
33 #include <asm/paravirt.h>
34 #include <asm/percpu.h>
37 #include <asm/pgtable_types.h>
38 #include <asm/export.h>
39 #include <asm/frame.h>
40 #include <asm/nospec-branch.h>
41 #include <linux/err.h>
46 .section .entry.text, "ax"
48 #ifdef CONFIG_PARAVIRT
49 ENTRY(native_usergs_sysret64)
53 END(native_usergs_sysret64)
54 #endif /* CONFIG_PARAVIRT */
56 .macro TRACE_IRQS_FLAGS flags:req
57 #ifdef CONFIG_TRACE_IRQFLAGS
58 bt $9, \flags /* interrupts off? */
65 .macro TRACE_IRQS_IRETQ
66 TRACE_IRQS_FLAGS EFLAGS(%rsp)
70 * When dynamic function tracer is enabled it will add a breakpoint
71 * to all locations that it is about to modify, sync CPUs, update
72 * all the code, sync CPUs, then remove the breakpoints. In this time
73 * if lockdep is enabled, it might jump back into the debug handler
74 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF).
76 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to
77 * make sure the stack pointer does not get reset back to the top
78 * of the debug stack, and instead just reuses the current stack.
80 #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS)
82 .macro TRACE_IRQS_OFF_DEBUG
83 call debug_stack_set_zero
85 call debug_stack_reset
88 .macro TRACE_IRQS_ON_DEBUG
89 call debug_stack_set_zero
91 call debug_stack_reset
94 .macro TRACE_IRQS_IRETQ_DEBUG
95 bt $9, EFLAGS(%rsp) /* interrupts off? */
102 # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF
103 # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON
104 # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ
108 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
110 * This is the only entry point used for 64-bit system calls. The
111 * hardware interface is reasonably well designed and the register to
112 * argument mapping Linux uses fits well with the registers that are
113 * available when SYSCALL is used.
115 * SYSCALL instructions can be found inlined in libc implementations as
116 * well as some other programs and libraries. There are also a handful
117 * of SYSCALL instructions in the vDSO used, for example, as a
118 * clock_gettimeofday fallback.
120 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
121 * then loads new ss, cs, and rip from previously programmed MSRs.
122 * rflags gets masked by a value from another MSR (so CLD and CLAC
123 * are not needed). SYSCALL does not save anything on the stack
124 * and does not change rsp.
126 * Registers on entry:
127 * rax system call number
129 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
133 * r10 arg3 (needs to be moved to rcx to conform to C ABI)
136 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
138 * Only called from user space.
140 * When user can change pt_regs->foo always force IRET. That is because
141 * it deals with uncanonical addresses better. SYSRET has trouble
142 * with them due to bugs in both AMD and Intel CPUs.
145 .pushsection .entry_trampoline, "ax"
148 * The code in here gets remapped into cpu_entry_area's trampoline. This means
149 * that the assembler and linker have the wrong idea as to where this code
150 * lives (and, in fact, it's mapped more than once, so it's not even at a
151 * fixed address). So we can't reference any symbols outside the entry
152 * trampoline and expect it to work.
154 * Instead, we carefully abuse %rip-relative addressing.
155 * _entry_trampoline(%rip) refers to the start of the remapped) entry
156 * trampoline. We can thus find cpu_entry_area with this macro:
159 #define CPU_ENTRY_AREA \
160 _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip)
162 /* The top word of the SYSENTER stack is hot and is usable as scratch space. */
163 #define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \
164 SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA
166 ENTRY(entry_SYSCALL_64_trampoline)
170 /* Stash the user RSP. */
171 movq %rsp, RSP_SCRATCH
173 /* Note: using %rsp as a scratch reg. */
174 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
176 /* Load the top of the task stack into RSP */
177 movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp
179 /* Start building the simulated IRET frame. */
180 pushq $__USER_DS /* pt_regs->ss */
181 pushq RSP_SCRATCH /* pt_regs->sp */
182 pushq %r11 /* pt_regs->flags */
183 pushq $__USER_CS /* pt_regs->cs */
184 pushq %rcx /* pt_regs->ip */
187 * x86 lacks a near absolute jump, and we can't jump to the real
188 * entry text with a relative jump. We could push the target
189 * address and then use retq, but this destroys the pipeline on
190 * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead,
191 * spill RDI and restore it in a second-stage trampoline.
194 movq $entry_SYSCALL_64_stage2, %rdi
196 END(entry_SYSCALL_64_trampoline)
200 ENTRY(entry_SYSCALL_64_stage2)
203 jmp entry_SYSCALL_64_after_hwframe
204 END(entry_SYSCALL_64_stage2)
206 ENTRY(entry_SYSCALL_64)
209 * Interrupts are off on entry.
210 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON,
211 * it is too small to ever cause noticeable irq latency.
216 * This path is only taken when PAGE_TABLE_ISOLATION is disabled so it
217 * is not required to switch CR3.
219 movq %rsp, PER_CPU_VAR(rsp_scratch)
220 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
222 /* Construct struct pt_regs on stack */
223 pushq $__USER_DS /* pt_regs->ss */
224 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */
225 pushq %r11 /* pt_regs->flags */
226 pushq $__USER_CS /* pt_regs->cs */
227 pushq %rcx /* pt_regs->ip */
228 GLOBAL(entry_SYSCALL_64_after_hwframe)
229 pushq %rax /* pt_regs->orig_ax */
230 pushq %rdi /* pt_regs->di */
231 pushq %rsi /* pt_regs->si */
232 pushq %rdx /* pt_regs->dx */
233 pushq %rcx /* pt_regs->cx */
234 pushq $-ENOSYS /* pt_regs->ax */
235 pushq %r8 /* pt_regs->r8 */
236 pushq %r9 /* pt_regs->r9 */
237 pushq %r10 /* pt_regs->r10 */
239 * Clear extra registers that a speculation attack might
240 * otherwise want to exploit. Interleave XOR with PUSH
241 * for better uop scheduling:
243 xorq %r10, %r10 /* nospec r10 */
244 pushq %r11 /* pt_regs->r11 */
245 xorq %r11, %r11 /* nospec r11 */
246 pushq %rbx /* pt_regs->rbx */
247 xorl %ebx, %ebx /* nospec rbx */
248 pushq %rbp /* pt_regs->rbp */
249 xorl %ebp, %ebp /* nospec rbp */
250 pushq %r12 /* pt_regs->r12 */
251 xorq %r12, %r12 /* nospec r12 */
252 pushq %r13 /* pt_regs->r13 */
253 xorq %r13, %r13 /* nospec r13 */
254 pushq %r14 /* pt_regs->r14 */
255 xorq %r14, %r14 /* nospec r14 */
256 pushq %r15 /* pt_regs->r15 */
257 xorq %r15, %r15 /* nospec r15 */
264 call do_syscall_64 /* returns with IRQs disabled */
266 TRACE_IRQS_IRETQ /* we're about to change IF */
269 * Try to use SYSRET instead of IRET if we're returning to
270 * a completely clean 64-bit userspace context. If we're not,
271 * go to the slow exit path.
276 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */
277 jne swapgs_restore_regs_and_return_to_usermode
280 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
281 * in kernel space. This essentially lets the user take over
282 * the kernel, since userspace controls RSP.
284 * If width of "canonical tail" ever becomes variable, this will need
285 * to be updated to remain correct on both old and new CPUs.
287 * Change top bits to match most significant bit (47th or 56th bit
288 * depending on paging mode) in the address.
290 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
291 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
293 /* If this changed %rcx, it was not canonical */
295 jne swapgs_restore_regs_and_return_to_usermode
297 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
298 jne swapgs_restore_regs_and_return_to_usermode
301 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
302 jne swapgs_restore_regs_and_return_to_usermode
305 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
306 * restore RF properly. If the slowpath sets it for whatever reason, we
307 * need to restore it correctly.
309 * SYSRET can restore TF, but unlike IRET, restoring TF results in a
310 * trap from userspace immediately after SYSRET. This would cause an
311 * infinite loop whenever #DB happens with register state that satisfies
312 * the opportunistic SYSRET conditions. For example, single-stepping
315 * movq $stuck_here, %rcx
320 * would never get past 'stuck_here'.
322 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
323 jnz swapgs_restore_regs_and_return_to_usermode
325 /* nothing to check for RSP */
327 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
328 jne swapgs_restore_regs_and_return_to_usermode
331 * We win! This label is here just for ease of understanding
332 * perf profiles. Nothing jumps here.
334 syscall_return_via_sysret:
335 /* rcx and r11 are already restored (see code above) */
338 popq %rsi /* skip r11 */
343 popq %rsi /* skip rcx */
348 * Now all regs are restored except RSP and RDI.
349 * Save old stack pointer and switch to trampoline stack.
352 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
354 pushq RSP-RDI(%rdi) /* RSP */
355 pushq (%rdi) /* RDI */
358 * We are on the trampoline stack. All regs except RDI are live.
359 * We can do future final exit work right here.
361 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
366 END(entry_SYSCALL_64)
372 ENTRY(__switch_to_asm)
375 * Save callee-saved registers
376 * This must match the order in inactive_task_frame
386 movq %rsp, TASK_threadsp(%rdi)
387 movq TASK_threadsp(%rsi), %rsp
389 #ifdef CONFIG_CC_STACKPROTECTOR
390 movq TASK_stack_canary(%rsi), %rbx
391 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset
394 #ifdef CONFIG_RETPOLINE
396 * When switching from a shallower to a deeper call stack
397 * the RSB may either underflow or use entries populated
398 * with userspace addresses. On CPUs where those concerns
399 * exist, overwrite the RSB with entries which capture
400 * speculative execution to prevent attack.
403 FILL_RETURN_BUFFER RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
406 /* restore callee-saved registers */
418 * A newly forked process directly context switches into this address.
420 * rax: prev task we switched from
421 * rbx: kernel thread func (NULL for user thread)
422 * r12: kernel thread arg
427 call schedule_tail /* rdi: 'prev' task parameter */
429 testq %rbx, %rbx /* from kernel_thread? */
430 jnz 1f /* kernel threads are uncommon */
435 call syscall_return_slowpath /* returns with IRQs disabled */
436 TRACE_IRQS_ON /* user mode is traced as IRQS on */
437 jmp swapgs_restore_regs_and_return_to_usermode
444 * A kernel thread is allowed to return here after successfully
445 * calling do_execve(). Exit to userspace to complete the execve()
453 * Build the entry stubs with some assembler magic.
454 * We pack 1 stub into every 8-byte block.
457 ENTRY(irq_entries_start)
458 vector=FIRST_EXTERNAL_VECTOR
459 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
460 UNWIND_HINT_IRET_REGS
461 pushq $(~vector+0x80) /* Note: always in signed byte range */
466 END(irq_entries_start)
468 .macro DEBUG_ENTRY_ASSERT_IRQS_OFF
469 #ifdef CONFIG_DEBUG_ENTRY
472 testl $X86_EFLAGS_IF, %eax
481 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers
482 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone.
483 * Requires kernel GSBASE.
485 * The invariant is that, if irq_count != -1, then the IRQ stack is in use.
487 .macro ENTER_IRQ_STACK regs=1 old_rsp
488 DEBUG_ENTRY_ASSERT_IRQS_OFF
492 UNWIND_HINT_REGS base=\old_rsp
495 incl PER_CPU_VAR(irq_count)
496 jnz .Lirq_stack_push_old_rsp_\@
499 * Right now, if we just incremented irq_count to zero, we've
500 * claimed the IRQ stack but we haven't switched to it yet.
502 * If anything is added that can interrupt us here without using IST,
503 * it must be *extremely* careful to limit its stack usage. This
504 * could include kprobes and a hypothetical future IST-less #DB
507 * The OOPS unwinder relies on the word at the top of the IRQ
508 * stack linking back to the previous RSP for the entire time we're
509 * on the IRQ stack. For this to work reliably, we need to write
510 * it before we actually move ourselves to the IRQ stack.
513 movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8)
514 movq PER_CPU_VAR(irq_stack_ptr), %rsp
516 #ifdef CONFIG_DEBUG_ENTRY
518 * If the first movq above becomes wrong due to IRQ stack layout
519 * changes, the only way we'll notice is if we try to unwind right
520 * here. Assert that we set up the stack right to catch this type
523 cmpq -8(%rsp), \old_rsp
524 je .Lirq_stack_okay\@
529 .Lirq_stack_push_old_rsp_\@:
533 UNWIND_HINT_REGS indirect=1
538 * Undoes ENTER_IRQ_STACK.
540 .macro LEAVE_IRQ_STACK regs=1
541 DEBUG_ENTRY_ASSERT_IRQS_OFF
542 /* We need to be off the IRQ stack before decrementing irq_count. */
550 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming
551 * the irq stack but we're not on it.
554 decl PER_CPU_VAR(irq_count)
558 * Interrupt entry/exit.
560 * Interrupt entry points save only callee clobbered registers in fast path.
562 * Entry runs with interrupts off.
565 /* 0(%rsp): ~(interrupt number) */
566 .macro interrupt func
569 testb $3, CS-ORIG_RAX(%rsp)
572 call switch_to_thread_stack
575 ALLOC_PT_GPREGS_ON_STACK
584 * IRQ from user mode.
586 * We need to tell lockdep that IRQs are off. We can't do this until
587 * we fix gsbase, and we should do it before enter_from_user_mode
588 * (which can take locks). Since TRACE_IRQS_OFF idempotent,
589 * the simplest way to handle it is to just call it twice if
590 * we enter from user mode. There's no reason to optimize this since
591 * TRACE_IRQS_OFF is a no-op if lockdep is off.
595 CALL_enter_from_user_mode
598 ENTER_IRQ_STACK old_rsp=%rdi
599 /* We entered an interrupt context - irqs are off: */
602 call \func /* rdi points to pt_regs */
606 * The interrupt stubs push (~vector+0x80) onto the stack and
607 * then jump to common_interrupt.
609 .p2align CONFIG_X86_L1_CACHE_SHIFT
612 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */
614 /* 0(%rsp): old RSP */
616 DISABLE_INTERRUPTS(CLBR_ANY)
624 /* Interrupt came from user space */
627 call prepare_exit_to_usermode
630 GLOBAL(swapgs_restore_regs_and_return_to_usermode)
631 #ifdef CONFIG_DEBUG_ENTRY
632 /* Assert that pt_regs indicates user mode. */
649 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
650 * Save old stack pointer and switch to trampoline stack.
653 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
655 /* Copy the IRET frame to the trampoline stack. */
656 pushq 6*8(%rdi) /* SS */
657 pushq 5*8(%rdi) /* RSP */
658 pushq 4*8(%rdi) /* EFLAGS */
659 pushq 3*8(%rdi) /* CS */
660 pushq 2*8(%rdi) /* RIP */
662 /* Push user RDI on the trampoline stack. */
666 * We are on the trampoline stack. All regs except RDI are live.
667 * We can do future final exit work right here.
670 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
678 /* Returning to kernel space */
680 #ifdef CONFIG_PREEMPT
681 /* Interrupts are off */
682 /* Check if we need preemption */
683 bt $9, EFLAGS(%rsp) /* were interrupts off? */
685 0: cmpl $0, PER_CPU_VAR(__preempt_count)
687 call preempt_schedule_irq
692 * The iretq could re-enable interrupts:
696 GLOBAL(restore_regs_and_return_to_kernel)
697 #ifdef CONFIG_DEBUG_ENTRY
698 /* Assert that pt_regs indicates kernel mode. */
706 addq $8, %rsp /* skip regs->orig_ax */
710 UNWIND_HINT_IRET_REGS
712 * Are we returning to a stack segment from the LDT? Note: in
713 * 64-bit mode SS:RSP on the exception stack is always valid.
715 #ifdef CONFIG_X86_ESPFIX64
716 testb $4, (SS-RIP)(%rsp)
717 jnz native_irq_return_ldt
720 .global native_irq_return_iret
721 native_irq_return_iret:
723 * This may fault. Non-paranoid faults on return to userspace are
724 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
725 * Double-faults due to espfix64 are handled in do_double_fault.
726 * Other faults here are fatal.
730 #ifdef CONFIG_X86_ESPFIX64
731 native_irq_return_ldt:
733 * We are running with user GSBASE. All GPRs contain their user
734 * values. We have a percpu ESPFIX stack that is eight slots
735 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
736 * of the ESPFIX stack.
738 * We clobber RAX and RDI in this code. We stash RDI on the
739 * normal stack and RAX on the ESPFIX stack.
741 * The ESPFIX stack layout we set up looks like this:
743 * --- top of ESPFIX stack ---
748 * RIP <-- RSP points here when we're done
749 * RAX <-- espfix_waddr points here
750 * --- bottom of ESPFIX stack ---
753 pushq %rdi /* Stash user RDI */
754 SWAPGS /* to kernel GS */
755 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
757 movq PER_CPU_VAR(espfix_waddr), %rdi
758 movq %rax, (0*8)(%rdi) /* user RAX */
759 movq (1*8)(%rsp), %rax /* user RIP */
760 movq %rax, (1*8)(%rdi)
761 movq (2*8)(%rsp), %rax /* user CS */
762 movq %rax, (2*8)(%rdi)
763 movq (3*8)(%rsp), %rax /* user RFLAGS */
764 movq %rax, (3*8)(%rdi)
765 movq (5*8)(%rsp), %rax /* user SS */
766 movq %rax, (5*8)(%rdi)
767 movq (4*8)(%rsp), %rax /* user RSP */
768 movq %rax, (4*8)(%rdi)
769 /* Now RAX == RSP. */
771 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
774 * espfix_stack[31:16] == 0. The page tables are set up such that
775 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
776 * espfix_waddr for any X. That is, there are 65536 RO aliases of
777 * the same page. Set up RSP so that RSP[31:16] contains the
778 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
779 * still points to an RO alias of the ESPFIX stack.
781 orq PER_CPU_VAR(espfix_stack), %rax
783 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
784 SWAPGS /* to user GS */
785 popq %rdi /* Restore user RDI */
788 UNWIND_HINT_IRET_REGS offset=8
791 * At this point, we cannot write to the stack any more, but we can
794 popq %rax /* Restore user RAX */
797 * RSP now points to an ordinary IRET frame, except that the page
798 * is read-only and RSP[31:16] are preloaded with the userspace
799 * values. We can now IRET back to userspace.
801 jmp native_irq_return_iret
803 END(common_interrupt)
808 .macro apicinterrupt3 num sym do_sym
810 UNWIND_HINT_IRET_REGS
819 /* Make sure APIC interrupt handlers end up in the irqentry section: */
820 #define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax"
821 #define POP_SECTION_IRQENTRY .popsection
823 .macro apicinterrupt num sym do_sym
824 PUSH_SECTION_IRQENTRY
825 apicinterrupt3 \num \sym \do_sym
830 apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt
831 apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt
835 apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt
838 apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt
839 apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi
841 #ifdef CONFIG_HAVE_KVM
842 apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi
843 apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi
844 apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi
847 #ifdef CONFIG_X86_MCE_THRESHOLD
848 apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt
851 #ifdef CONFIG_X86_MCE_AMD
852 apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt
855 #ifdef CONFIG_X86_THERMAL_VECTOR
856 apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt
860 apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt
861 apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt
862 apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt
865 apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt
866 apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt
868 #ifdef CONFIG_IRQ_WORK
869 apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt
873 * Exception entry points.
875 #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8)
878 * Switch to the thread stack. This is called with the IRET frame and
879 * orig_ax on the stack. (That is, RDI..R12 are not on the stack and
880 * space has not been allocated for them.)
882 ENTRY(switch_to_thread_stack)
886 /* Need to switch before accessing the thread stack. */
887 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
889 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
890 UNWIND_HINT sp_offset=16 sp_reg=ORC_REG_DI
892 pushq 7*8(%rdi) /* regs->ss */
893 pushq 6*8(%rdi) /* regs->rsp */
894 pushq 5*8(%rdi) /* regs->eflags */
895 pushq 4*8(%rdi) /* regs->cs */
896 pushq 3*8(%rdi) /* regs->ip */
897 pushq 2*8(%rdi) /* regs->orig_ax */
898 pushq 8(%rdi) /* return address */
903 END(switch_to_thread_stack)
905 .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1
907 UNWIND_HINT_IRET_REGS offset=\has_error_code*8
910 .if \shift_ist != -1 && \paranoid == 0
911 .error "using shift_ist requires paranoid=1"
916 .if \has_error_code == 0
917 pushq $-1 /* ORIG_RAX: no syscall to restart */
920 ALLOC_PT_GPREGS_ON_STACK
923 testb $3, CS(%rsp) /* If coming from userspace, switch stacks */
924 jnz .Lfrom_usermode_switch_stack_\@
933 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */
937 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */
943 movq %rsp, %rdi /* pt_regs pointer */
946 movq ORIG_RAX(%rsp), %rsi /* get error code */
947 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
949 xorl %esi, %esi /* no error code */
953 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
959 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
962 /* these procedures expect "no swapgs" flag in ebx */
971 * Entry from userspace. Switch stacks and treat it
972 * as a normal entry. This means that paranoid handlers
973 * run in real process context if user_mode(regs).
975 .Lfrom_usermode_switch_stack_\@:
978 movq %rsp, %rdi /* pt_regs pointer */
981 movq ORIG_RAX(%rsp), %rsi /* get error code */
982 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
984 xorl %esi, %esi /* no error code */
989 jmp error_exit /* %ebx: no swapgs flag */
994 idtentry divide_error do_divide_error has_error_code=0
995 idtentry overflow do_overflow has_error_code=0
996 idtentry bounds do_bounds has_error_code=0
997 idtentry invalid_op do_invalid_op has_error_code=0
998 idtentry device_not_available do_device_not_available has_error_code=0
999 idtentry double_fault do_double_fault has_error_code=1 paranoid=2
1000 idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
1001 idtentry invalid_TSS do_invalid_TSS has_error_code=1
1002 idtentry segment_not_present do_segment_not_present has_error_code=1
1003 idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0
1004 idtentry coprocessor_error do_coprocessor_error has_error_code=0
1005 idtentry alignment_check do_alignment_check has_error_code=1
1006 idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0
1010 * Reload gs selector with exception handling
1013 ENTRY(native_load_gs_index)
1016 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI)
1021 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
1023 TRACE_IRQS_FLAGS (%rsp)
1027 ENDPROC(native_load_gs_index)
1028 EXPORT_SYMBOL(native_load_gs_index)
1030 _ASM_EXTABLE(.Lgs_change, bad_gs)
1031 .section .fixup, "ax"
1032 /* running with kernelgs */
1034 SWAPGS /* switch back to user gs */
1036 /* This can't be a string because the preprocessor needs to see it. */
1037 movl $__USER_DS, %eax
1040 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
1046 /* Call softirq on interrupt stack. Interrupts are off. */
1047 ENTRY(do_softirq_own_stack)
1050 ENTER_IRQ_STACK regs=0 old_rsp=%r11
1052 LEAVE_IRQ_STACK regs=0
1055 ENDPROC(do_softirq_own_stack)
1058 idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0
1061 * A note on the "critical region" in our callback handler.
1062 * We want to avoid stacking callback handlers due to events occurring
1063 * during handling of the last event. To do this, we keep events disabled
1064 * until we've done all processing. HOWEVER, we must enable events before
1065 * popping the stack frame (can't be done atomically) and so it would still
1066 * be possible to get enough handler activations to overflow the stack.
1067 * Although unlikely, bugs of that kind are hard to track down, so we'd
1068 * like to avoid the possibility.
1069 * So, on entry to the handler we detect whether we interrupted an
1070 * existing activation in its critical region -- if so, we pop the current
1071 * activation and restart the handler using the previous one.
1073 ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */
1076 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
1077 * see the correct pointer to the pt_regs
1080 movq %rdi, %rsp /* we don't return, adjust the stack frame */
1083 ENTER_IRQ_STACK old_rsp=%r10
1084 call xen_evtchn_do_upcall
1087 #ifndef CONFIG_PREEMPT
1088 call xen_maybe_preempt_hcall
1091 END(xen_do_hypervisor_callback)
1094 * Hypervisor uses this for application faults while it executes.
1095 * We get here for two reasons:
1096 * 1. Fault while reloading DS, ES, FS or GS
1097 * 2. Fault while executing IRET
1098 * Category 1 we do not need to fix up as Xen has already reloaded all segment
1099 * registers that could be reloaded and zeroed the others.
1100 * Category 2 we fix up by killing the current process. We cannot use the
1101 * normal Linux return path in this case because if we use the IRET hypercall
1102 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
1103 * We distinguish between categories by comparing each saved segment register
1104 * with its current contents: any discrepancy means we in category 1.
1106 ENTRY(xen_failsafe_callback)
1109 cmpw %cx, 0x10(%rsp)
1112 cmpw %cx, 0x18(%rsp)
1115 cmpw %cx, 0x20(%rsp)
1118 cmpw %cx, 0x28(%rsp)
1120 /* All segments match their saved values => Category 2 (Bad IRET). */
1125 UNWIND_HINT_IRET_REGS offset=8
1126 jmp general_protection
1127 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
1131 UNWIND_HINT_IRET_REGS
1132 pushq $-1 /* orig_ax = -1 => not a system call */
1133 ALLOC_PT_GPREGS_ON_STACK
1136 ENCODE_FRAME_POINTER
1138 END(xen_failsafe_callback)
1140 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1141 xen_hvm_callback_vector xen_evtchn_do_upcall
1143 #endif /* CONFIG_XEN */
1145 #if IS_ENABLED(CONFIG_HYPERV)
1146 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1147 hyperv_callback_vector hyperv_vector_handler
1148 #endif /* CONFIG_HYPERV */
1150 idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
1151 idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
1152 idtentry stack_segment do_stack_segment has_error_code=1
1155 idtentry xennmi do_nmi has_error_code=0
1156 idtentry xendebug do_debug has_error_code=0
1157 idtentry xenint3 do_int3 has_error_code=0
1160 idtentry general_protection do_general_protection has_error_code=1
1161 idtentry page_fault do_page_fault has_error_code=1
1163 #ifdef CONFIG_KVM_GUEST
1164 idtentry async_page_fault do_async_page_fault has_error_code=1
1167 #ifdef CONFIG_X86_MCE
1168 idtentry machine_check do_mce has_error_code=0 paranoid=1
1172 * Save all registers in pt_regs, and switch gs if needed.
1173 * Use slow, but surefire "are we in kernel?" check.
1174 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise
1176 ENTRY(paranoid_entry)
1181 ENCODE_FRAME_POINTER 8
1183 movl $MSR_GS_BASE, %ecx
1186 js 1f /* negative -> in kernel */
1191 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
1197 * "Paranoid" exit path from exception stack. This is invoked
1198 * only on return from non-NMI IST interrupts that came
1199 * from kernel space.
1201 * We may be returning to very strange contexts (e.g. very early
1202 * in syscall entry), so checking for preemption here would
1203 * be complicated. Fortunately, we there's no good reason
1204 * to try to handle preemption here.
1206 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it)
1208 ENTRY(paranoid_exit)
1210 DISABLE_INTERRUPTS(CLBR_ANY)
1211 TRACE_IRQS_OFF_DEBUG
1212 testl %ebx, %ebx /* swapgs needed? */
1213 jnz .Lparanoid_exit_no_swapgs
1215 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1217 jmp .Lparanoid_exit_restore
1218 .Lparanoid_exit_no_swapgs:
1219 TRACE_IRQS_IRETQ_DEBUG
1220 .Lparanoid_exit_restore:
1221 jmp restore_regs_and_return_to_kernel
1225 * Save all registers in pt_regs, and switch gs if needed.
1226 * Return: EBX=0: came from user mode; EBX=1: otherwise
1233 ENCODE_FRAME_POINTER 8
1234 testb $3, CS+8(%rsp)
1235 jz .Lerror_kernelspace
1238 * We entered from user mode or we're pretending to have entered
1239 * from user mode due to an IRET fault.
1242 /* We have user CR3. Change to kernel CR3. */
1243 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1245 .Lerror_entry_from_usermode_after_swapgs:
1246 /* Put us onto the real thread stack. */
1247 popq %r12 /* save return addr in %12 */
1248 movq %rsp, %rdi /* arg0 = pt_regs pointer */
1250 movq %rax, %rsp /* switch stack */
1251 ENCODE_FRAME_POINTER
1255 * We need to tell lockdep that IRQs are off. We can't do this until
1256 * we fix gsbase, and we should do it before enter_from_user_mode
1257 * (which can take locks).
1260 CALL_enter_from_user_mode
1268 * There are two places in the kernel that can potentially fault with
1269 * usergs. Handle them here. B stepping K8s sometimes report a
1270 * truncated RIP for IRET exceptions returning to compat mode. Check
1271 * for these here too.
1273 .Lerror_kernelspace:
1275 leaq native_irq_return_iret(%rip), %rcx
1276 cmpq %rcx, RIP+8(%rsp)
1278 movl %ecx, %eax /* zero extend */
1279 cmpq %rax, RIP+8(%rsp)
1281 cmpq $.Lgs_change, RIP+8(%rsp)
1282 jne .Lerror_entry_done
1285 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
1286 * gsbase and proceed. We'll fix up the exception and land in
1287 * .Lgs_change's error handler with kernel gsbase.
1290 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1291 jmp .Lerror_entry_done
1294 /* Fix truncated RIP */
1295 movq %rcx, RIP+8(%rsp)
1300 * We came from an IRET to user mode, so we have user
1301 * gsbase and CR3. Switch to kernel gsbase and CR3:
1304 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1307 * Pretend that the exception came from user mode: set up pt_regs
1308 * as if we faulted immediately after IRET and clear EBX so that
1309 * error_exit knows that we will be returning to user mode.
1315 jmp .Lerror_entry_from_usermode_after_swapgs
1320 * On entry, EBX is a "return to kernel mode" flag:
1321 * 1: already in kernel mode, don't need SWAPGS
1322 * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode
1326 DISABLE_INTERRUPTS(CLBR_ANY)
1334 * Runs on exception stack. Xen PV does not go through this path at all,
1335 * so we can use real assembly here.
1338 * %r14: Used to save/restore the CR3 of the interrupted context
1339 * when PAGE_TABLE_ISOLATION is in use. Do not clobber.
1342 UNWIND_HINT_IRET_REGS
1345 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1346 * the iretq it performs will take us out of NMI context.
1347 * This means that we can have nested NMIs where the next
1348 * NMI is using the top of the stack of the previous NMI. We
1349 * can't let it execute because the nested NMI will corrupt the
1350 * stack of the previous NMI. NMI handlers are not re-entrant
1353 * To handle this case we do the following:
1354 * Check the a special location on the stack that contains
1355 * a variable that is set when NMIs are executing.
1356 * The interrupted task's stack is also checked to see if it
1358 * If the variable is not set and the stack is not the NMI
1360 * o Set the special variable on the stack
1361 * o Copy the interrupt frame into an "outermost" location on the
1363 * o Copy the interrupt frame into an "iret" location on the stack
1364 * o Continue processing the NMI
1365 * If the variable is set or the previous stack is the NMI stack:
1366 * o Modify the "iret" location to jump to the repeat_nmi
1367 * o return back to the first NMI
1369 * Now on exit of the first NMI, we first clear the stack variable
1370 * The NMI stack will tell any nested NMIs at that point that it is
1371 * nested. Then we pop the stack normally with iret, and if there was
1372 * a nested NMI that updated the copy interrupt stack frame, a
1373 * jump will be made to the repeat_nmi code that will handle the second
1376 * However, espfix prevents us from directly returning to userspace
1377 * with a single IRET instruction. Similarly, IRET to user mode
1378 * can fault. We therefore handle NMIs from user space like
1379 * other IST entries.
1384 /* Use %rdx as our temp variable throughout */
1387 testb $3, CS-RIP+8(%rsp)
1388 jz .Lnmi_from_kernel
1391 * NMI from user mode. We need to run on the thread stack, but we
1392 * can't go through the normal entry paths: NMIs are masked, and
1393 * we don't want to enable interrupts, because then we'll end
1394 * up in an awkward situation in which IRQs are on but NMIs
1397 * We also must not push anything to the stack before switching
1398 * stacks lest we corrupt the "NMI executing" variable.
1403 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
1405 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
1406 UNWIND_HINT_IRET_REGS base=%rdx offset=8
1407 pushq 5*8(%rdx) /* pt_regs->ss */
1408 pushq 4*8(%rdx) /* pt_regs->rsp */
1409 pushq 3*8(%rdx) /* pt_regs->flags */
1410 pushq 2*8(%rdx) /* pt_regs->cs */
1411 pushq 1*8(%rdx) /* pt_regs->rip */
1412 UNWIND_HINT_IRET_REGS
1413 pushq $-1 /* pt_regs->orig_ax */
1414 pushq %rdi /* pt_regs->di */
1415 pushq %rsi /* pt_regs->si */
1416 pushq (%rdx) /* pt_regs->dx */
1417 pushq %rcx /* pt_regs->cx */
1418 pushq %rax /* pt_regs->ax */
1419 pushq %r8 /* pt_regs->r8 */
1420 pushq %r9 /* pt_regs->r9 */
1421 pushq %r10 /* pt_regs->r10 */
1422 pushq %r11 /* pt_regs->r11 */
1423 pushq %rbx /* pt_regs->rbx */
1424 pushq %rbp /* pt_regs->rbp */
1425 pushq %r12 /* pt_regs->r12 */
1426 pushq %r13 /* pt_regs->r13 */
1427 pushq %r14 /* pt_regs->r14 */
1428 pushq %r15 /* pt_regs->r15 */
1431 ENCODE_FRAME_POINTER
1434 * At this point we no longer need to worry about stack damage
1435 * due to nesting -- we're on the normal thread stack and we're
1436 * done with the NMI stack.
1444 * Return back to user mode. We must *not* do the normal exit
1445 * work, because we don't want to enable interrupts.
1447 jmp swapgs_restore_regs_and_return_to_usermode
1451 * Here's what our stack frame will look like:
1452 * +---------------------------------------------------------+
1454 * | original Return RSP |
1455 * | original RFLAGS |
1458 * +---------------------------------------------------------+
1459 * | temp storage for rdx |
1460 * +---------------------------------------------------------+
1461 * | "NMI executing" variable |
1462 * +---------------------------------------------------------+
1463 * | iret SS } Copied from "outermost" frame |
1464 * | iret Return RSP } on each loop iteration; overwritten |
1465 * | iret RFLAGS } by a nested NMI to force another |
1466 * | iret CS } iteration if needed. |
1468 * +---------------------------------------------------------+
1469 * | outermost SS } initialized in first_nmi; |
1470 * | outermost Return RSP } will not be changed before |
1471 * | outermost RFLAGS } NMI processing is done. |
1472 * | outermost CS } Copied to "iret" frame on each |
1473 * | outermost RIP } iteration. |
1474 * +---------------------------------------------------------+
1476 * +---------------------------------------------------------+
1478 * The "original" frame is used by hardware. Before re-enabling
1479 * NMIs, we need to be done with it, and we need to leave enough
1480 * space for the asm code here.
1482 * We return by executing IRET while RSP points to the "iret" frame.
1483 * That will either return for real or it will loop back into NMI
1486 * The "outermost" frame is copied to the "iret" frame on each
1487 * iteration of the loop, so each iteration starts with the "iret"
1488 * frame pointing to the final return target.
1492 * Determine whether we're a nested NMI.
1494 * If we interrupted kernel code between repeat_nmi and
1495 * end_repeat_nmi, then we are a nested NMI. We must not
1496 * modify the "iret" frame because it's being written by
1497 * the outer NMI. That's okay; the outer NMI handler is
1498 * about to about to call do_nmi anyway, so we can just
1499 * resume the outer NMI.
1502 movq $repeat_nmi, %rdx
1505 movq $end_repeat_nmi, %rdx
1511 * Now check "NMI executing". If it's set, then we're nested.
1512 * This will not detect if we interrupted an outer NMI just
1519 * Now test if the previous stack was an NMI stack. This covers
1520 * the case where we interrupt an outer NMI after it clears
1521 * "NMI executing" but before IRET. We need to be careful, though:
1522 * there is one case in which RSP could point to the NMI stack
1523 * despite there being no NMI active: naughty userspace controls
1524 * RSP at the very beginning of the SYSCALL targets. We can
1525 * pull a fast one on naughty userspace, though: we program
1526 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1527 * if it controls the kernel's RSP. We set DF before we clear
1531 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1532 cmpq %rdx, 4*8(%rsp)
1533 /* If the stack pointer is above the NMI stack, this is a normal NMI */
1536 subq $EXCEPTION_STKSZ, %rdx
1537 cmpq %rdx, 4*8(%rsp)
1538 /* If it is below the NMI stack, it is a normal NMI */
1541 /* Ah, it is within the NMI stack. */
1543 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1544 jz first_nmi /* RSP was user controlled. */
1546 /* This is a nested NMI. */
1550 * Modify the "iret" frame to point to repeat_nmi, forcing another
1551 * iteration of NMI handling.
1554 leaq -10*8(%rsp), %rdx
1561 /* Put stack back */
1567 /* We are returning to kernel mode, so this cannot result in a fault. */
1574 /* Make room for "NMI executing". */
1577 /* Leave room for the "iret" frame */
1580 /* Copy the "original" frame to the "outermost" frame */
1584 UNWIND_HINT_IRET_REGS
1586 /* Everything up to here is safe from nested NMIs */
1588 #ifdef CONFIG_DEBUG_ENTRY
1590 * For ease of testing, unmask NMIs right away. Disabled by
1591 * default because IRET is very expensive.
1594 pushq %rsp /* RSP (minus 8 because of the previous push) */
1595 addq $8, (%rsp) /* Fix up RSP */
1597 pushq $__KERNEL_CS /* CS */
1599 iretq /* continues at repeat_nmi below */
1600 UNWIND_HINT_IRET_REGS
1606 * If there was a nested NMI, the first NMI's iret will return
1607 * here. But NMIs are still enabled and we can take another
1608 * nested NMI. The nested NMI checks the interrupted RIP to see
1609 * if it is between repeat_nmi and end_repeat_nmi, and if so
1610 * it will just return, as we are about to repeat an NMI anyway.
1611 * This makes it safe to copy to the stack frame that a nested
1614 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
1615 * we're repeating an NMI, gsbase has the same value that it had on
1616 * the first iteration. paranoid_entry will load the kernel
1617 * gsbase if needed before we call do_nmi. "NMI executing"
1620 movq $1, 10*8(%rsp) /* Set "NMI executing". */
1623 * Copy the "outermost" frame to the "iret" frame. NMIs that nest
1624 * here must not modify the "iret" frame while we're writing to
1625 * it or it will end up containing garbage.
1635 * Everything below this point can be preempted by a nested NMI.
1636 * If this happens, then the inner NMI will change the "iret"
1637 * frame to point back to repeat_nmi.
1639 pushq $-1 /* ORIG_RAX: no syscall to restart */
1640 ALLOC_PT_GPREGS_ON_STACK
1643 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
1644 * as we should not be calling schedule in NMI context.
1645 * Even with normal interrupts enabled. An NMI should not be
1646 * setting NEED_RESCHED or anything that normal interrupts and
1647 * exceptions might do.
1652 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */
1657 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
1659 testl %ebx, %ebx /* swapgs needed? */
1668 * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
1669 * at the "iret" frame.
1674 * Clear "NMI executing". Set DF first so that we can easily
1675 * distinguish the remaining code between here and IRET from
1676 * the SYSCALL entry and exit paths.
1678 * We arguably should just inspect RIP instead, but I (Andy) wrote
1679 * this code when I had the misapprehension that Xen PV supported
1680 * NMIs, and Xen PV would break that approach.
1683 movq $0, 5*8(%rsp) /* clear "NMI executing" */
1686 * iretq reads the "iret" frame and exits the NMI stack in a
1687 * single instruction. We are returning to kernel mode, so this
1688 * cannot result in a fault. Similarly, we don't need to worry
1689 * about espfix64 on the way back to kernel mode.
1694 ENTRY(ignore_sysret)
1700 ENTRY(rewind_stack_do_exit)
1702 /* Prevent any naive code from trying to unwind to our caller. */
1705 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax
1706 leaq -PTREGS_SIZE(%rax), %rsp
1707 UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE
1710 END(rewind_stack_do_exit)