arch/sparc64/mm/init.c

   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/sched.h>
  12 #include <linux/string.h>
  13 #include <linux/init.h>
  14 #include <linux/bootmem.h>
  15 #include <linux/mm.h>
  16 #include <linux/hugetlb.h>
  17 #include <linux/slab.h>
  18 #include <linux/initrd.h>
  19 #include <linux/swap.h>
  20 #include <linux/pagemap.h>
  21 #include <linux/fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/kprobes.h>
  24 #include <linux/cache.h>
  25 #include <linux/sort.h>
  26
  27 #include <asm/head.h>
  28 #include <asm/system.h>
  29 #include <asm/page.h>
  30 #include <asm/pgalloc.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/oplib.h>
  33 #include <asm/iommu.h>
  34 #include <asm/io.h>
  35 #include <asm/uaccess.h>
  36 #include <asm/mmu_context.h>
  37 #include <asm/tlbflush.h>
  38 #include <asm/dma.h>
  39 #include <asm/starfire.h>
  40 #include <asm/tlb.h>
  41 #include <asm/spitfire.h>
  42 #include <asm/sections.h>
  43 #include <asm/tsb.h>
  44 #include <asm/hypervisor.h>
  45
  46 extern void device_scan(void);
  47
  48 #define MAX_PHYS_ADDRESS        (1UL << 42UL)
  49 #define KPTE_BITMAP_CHUNK_SZ    (256UL * 1024UL * 1024UL)
  50 #define KPTE_BITMAP_BYTES       \
  51         ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
  52
  53 unsigned long kern_linear_pte_xor[2] __read_mostly;
  54
  55 /* A bitmap, one bit for every 256MB of physical memory.  If the bit
  56  * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
  57  * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
  58  */
  59 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
  60
  61 /* A special kernel TSB for 4MB and 256MB linear mappings.  */
  62 struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  63
  64 #define MAX_BANKS       32
  65
  66 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
  67 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
  68 static int pavail_ents __initdata;
  69 static int pavail_rescan_ents __initdata;
  70
  71 static int cmp_p64(const void *a, const void *b)
  72 {
  73         const struct linux_prom64_registers *x = a, *y = b;
  74
  75         if (x->phys_addr > y->phys_addr)
  76                 return 1;
  77         if (x->phys_addr < y->phys_addr)
  78                 return -1;
  79         return 0;
  80 }
  81
  82 static void __init read_obp_memory(const char *property,
  83                                    struct linux_prom64_registers *regs,
  84                                    int *num_ents)
  85 {
  86         int node = prom_finddevice("/memory");
  87         int prop_size = prom_getproplen(node, property);
  88         int ents, ret, i;
  89
  90         ents = prop_size / sizeof(struct linux_prom64_registers);
  91         if (ents > MAX_BANKS) {
  92                 prom_printf("The machine has more %s property entries than "
  93                             "this kernel can support (%d).\n",
  94                             property, MAX_BANKS);
  95                 prom_halt();
  96         }
  97
  98         ret = prom_getproperty(node, property, (char *) regs, prop_size);
  99         if (ret == -1) {
 100                 prom_printf("Couldn't get %s property from /memory.\n");
 101                 prom_halt();
 102         }
 103
 104         *num_ents = ents;
 105
 106         /* Sanitize what we got from the firmware, by page aligning
 107          * everything.
 108          */
 109         for (i = 0; i < ents; i++) {
 110                 unsigned long base, size;
 111
 112                 base = regs[i].phys_addr;
 113                 size = regs[i].reg_size;
 114
 115                 size &= PAGE_MASK;
 116                 if (base & ~PAGE_MASK) {
 117                         unsigned long new_base = PAGE_ALIGN(base);
 118
 119                         size -= new_base - base;
 120                         if ((long) size < 0L)
 121                                 size = 0UL;
 122                         base = new_base;
 123                 }
 124                 regs[i].phys_addr = base;
 125                 regs[i].reg_size = size;
 126         }
 127         sort(regs, ents, sizeof(struct linux_prom64_registers),
 128              cmp_p64, NULL);
 129 }
 130
 131 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
 132
 133 /* Kernel physical address base and size in bytes.  */
 134 unsigned long kern_base __read_mostly;
 135 unsigned long kern_size __read_mostly;
 136
 137 /* get_new_mmu_context() uses "cache + 1".  */
 138 DEFINE_SPINLOCK(ctx_alloc_lock);
 139 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 140 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
 141 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
 142
 143 /* References to special section boundaries */
 144 extern char  _start[], _end[];
 145
 146 /* Initial ramdisk setup */
 147 extern unsigned long sparc_ramdisk_image64;
 148 extern unsigned int sparc_ramdisk_image;
 149 extern unsigned int sparc_ramdisk_size;
 150
 151 struct page *mem_map_zero __read_mostly;
 152
 153 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 154
 155 unsigned long sparc64_kern_pri_context __read_mostly;
 156 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 157 unsigned long sparc64_kern_sec_context __read_mostly;
 158
 159 int bigkernel = 0;
 160
 161 kmem_cache_t *pgtable_cache __read_mostly;
 162
 163 static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
 164 {
 165         clear_page(addr);
 166 }
 167
 168 extern void tsb_cache_init(void);
 169
 170 void pgtable_cache_init(void)
 171 {
 172         pgtable_cache = kmem_cache_create("pgtable_cache",
 173                                           PAGE_SIZE, PAGE_SIZE,
 174                                           SLAB_HWCACHE_ALIGN |
 175                                           SLAB_MUST_HWCACHE_ALIGN,
 176                                           zero_ctor,
 177                                           NULL);
 178         if (!pgtable_cache) {
 179                 prom_printf("Could not create pgtable_cache\n");
 180                 prom_halt();
 181         }
 182         tsb_cache_init();
 183 }
 184
 185 #ifdef CONFIG_DEBUG_DCFLUSH
 186 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 187 #ifdef CONFIG_SMP
 188 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 189 #endif
 190 #endif
 191
 192 inline void flush_dcache_page_impl(struct page *page)
 193 {
 194         BUG_ON(tlb_type == hypervisor);
 195 #ifdef CONFIG_DEBUG_DCFLUSH
 196         atomic_inc(&dcpage_flushes);
 197 #endif
 198
 199 #ifdef DCACHE_ALIASING_POSSIBLE
 200         __flush_dcache_page(page_address(page),
 201                             ((tlb_type == spitfire) &&
 202                              page_mapping(page) != NULL));
 203 #else
 204         if (page_mapping(page) != NULL &&
 205             tlb_type == spitfire)
 206                 __flush_icache_page(__pa(page_address(page)));
 207 #endif
 208 }
 209
 210 #define PG_dcache_dirty         PG_arch_1
 211 #define PG_dcache_cpu_shift     24UL
 212 #define PG_dcache_cpu_mask      (256UL - 1UL)
 213
 214 #if NR_CPUS > 256
 215 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
 216 #endif
 217
 218 #define dcache_dirty_cpu(page) \
 219         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 220
 221 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
 222 {
 223         unsigned long mask = this_cpu;
 224         unsigned long non_cpu_bits;
 225
 226         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 227         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 228
 229         __asm__ __volatile__("1:\n\t"
 230                              "ldx       [%2], %%g7\n\t"
 231                              "and       %%g7, %1, %%g1\n\t"
 232                              "or        %%g1, %0, %%g1\n\t"
 233                              "casx      [%2], %%g7, %%g1\n\t"
 234                              "cmp       %%g7, %%g1\n\t"
 235                              "membar    #StoreLoad | #StoreStore\n\t"
 236                              "bne,pn    %%xcc, 1b\n\t"
 237                              " nop"
 238                              : /* no outputs */
 239                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 240                              : "g1", "g7");
 241 }
 242
 243 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 244 {
 245         unsigned long mask = (1UL << PG_dcache_dirty);
 246
 247         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 248                              "1:\n\t"
 249                              "ldx       [%2], %%g7\n\t"
 250                              "srlx      %%g7, %4, %%g1\n\t"
 251                              "and       %%g1, %3, %%g1\n\t"
 252                              "cmp       %%g1, %0\n\t"
 253                              "bne,pn    %%icc, 2f\n\t"
 254                              " andn     %%g7, %1, %%g1\n\t"
 255                              "casx      [%2], %%g7, %%g1\n\t"
 256                              "cmp       %%g7, %%g1\n\t"
 257                              "membar    #StoreLoad | #StoreStore\n\t"
 258                              "bne,pn    %%xcc, 1b\n\t"
 259                              " nop\n"
 260                              "2:"
 261                              : /* no outputs */
 262                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 263                                "i" (PG_dcache_cpu_mask),
 264                                "i" (PG_dcache_cpu_shift)
 265                              : "g1", "g7");
 266 }
 267
 268 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 269 {
 270         unsigned long tsb_addr = (unsigned long) ent;
 271
 272         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
 273                 tsb_addr = __pa(tsb_addr);
 274
 275         __tsb_insert(tsb_addr, tag, pte);
 276 }
 277
 278 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
 279 unsigned long _PAGE_SZBITS __read_mostly;
 280
 281 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 282 {
 283         struct mm_struct *mm;
 284         struct tsb *tsb;
 285         unsigned long tag, flags;
 286         unsigned long tsb_index, tsb_hash_shift;
 287
 288         if (tlb_type != hypervisor) {
 289                 unsigned long pfn = pte_pfn(pte);
 290                 unsigned long pg_flags;
 291                 struct page *page;
 292
 293                 if (pfn_valid(pfn) &&
 294                     (page = pfn_to_page(pfn), page_mapping(page)) &&
 295                     ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 296                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 297                                    PG_dcache_cpu_mask);
 298                         int this_cpu = get_cpu();
 299
 300                         /* This is just to optimize away some function calls
 301                          * in the SMP case.
 302                          */
 303                         if (cpu == this_cpu)
 304                                 flush_dcache_page_impl(page);
 305                         else
 306                                 smp_flush_dcache_page_impl(page, cpu);
 307
 308                         clear_dcache_dirty_cpu(page, cpu);
 309
 310                         put_cpu();
 311                 }
 312         }
 313
 314         mm = vma->vm_mm;
 315
 316         tsb_index = MM_TSB_BASE;
 317         tsb_hash_shift = PAGE_SHIFT;
 318
 319         spin_lock_irqsave(&mm->context.lock, flags);
 320
 321 #ifdef CONFIG_HUGETLB_PAGE
 322         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
 323                 if ((tlb_type == hypervisor &&
 324                      (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
 325                     (tlb_type != hypervisor &&
 326                      (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
 327                         tsb_index = MM_TSB_HUGE;
 328                         tsb_hash_shift = HPAGE_SHIFT;
 329                 }
 330         }
 331 #endif
 332
 333         tsb = mm->context.tsb_block[tsb_index].tsb;
 334         tsb += ((address >> tsb_hash_shift) &
 335                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
 336         tag = (address >> 22UL);
 337         tsb_insert(tsb, tag, pte_val(pte));
 338
 339         spin_unlock_irqrestore(&mm->context.lock, flags);
 340 }
 341
 342 void flush_dcache_page(struct page *page)
 343 {
 344         struct address_space *mapping;
 345         int this_cpu;
 346
 347         if (tlb_type == hypervisor)
 348                 return;
 349
 350         /* Do not bother with the expensive D-cache flush if it
 351          * is merely the zero page.  The 'bigcore' testcase in GDB
 352          * causes this case to run millions of times.
 353          */
 354         if (page == ZERO_PAGE(0))
 355                 return;
 356
 357         this_cpu = get_cpu();
 358
 359         mapping = page_mapping(page);
 360         if (mapping && !mapping_mapped(mapping)) {
 361                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 362                 if (dirty) {
 363                         int dirty_cpu = dcache_dirty_cpu(page);
 364
 365                         if (dirty_cpu == this_cpu)
 366                                 goto out;
 367                         smp_flush_dcache_page_impl(page, dirty_cpu);
 368                 }
 369                 set_dcache_dirty(page, this_cpu);
 370         } else {
 371                 /* We could delay the flush for the !page_mapping
 372                  * case too.  But that case is for exec env/arg
 373                  * pages and those are %99 certainly going to get
 374                  * faulted into the tlb (and thus flushed) anyways.
 375                  */
 376                 flush_dcache_page_impl(page);
 377         }
 378
 379 out:
 380         put_cpu();
 381 }
 382
 383 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 384 {
 385         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 386         if (tlb_type == spitfire) {
 387                 unsigned long kaddr;
 388
 389                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
 390                         __flush_icache_page(__get_phys(kaddr));
 391         }
 392 }
 393
 394 void show_mem(void)
 395 {
 396         printk("Mem-info:\n");
 397         show_free_areas();
 398         printk("Free swap:       %6ldkB\n",
 399                nr_swap_pages << (PAGE_SHIFT-10));
 400         printk("%ld pages of RAM\n", num_physpages);
 401         printk("%d free pages\n", nr_free_pages());
 402 }
 403
 404 void mmu_info(struct seq_file *m)
 405 {
 406         if (tlb_type == cheetah)
 407                 seq_printf(m, "MMU Type\t: Cheetah\n");
 408         else if (tlb_type == cheetah_plus)
 409                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 410         else if (tlb_type == spitfire)
 411                 seq_printf(m, "MMU Type\t: Spitfire\n");
 412         else if (tlb_type == hypervisor)
 413                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 414         else
 415                 seq_printf(m, "MMU Type\t: ???\n");
 416
 417 #ifdef CONFIG_DEBUG_DCFLUSH
 418         seq_printf(m, "DCPageFlushes\t: %d\n",
 419                    atomic_read(&dcpage_flushes));
 420 #ifdef CONFIG_SMP
 421         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 422                    atomic_read(&dcpage_flushes_xcall));
 423 #endif /* CONFIG_SMP */
 424 #endif /* CONFIG_DEBUG_DCFLUSH */
 425 }
 426
 427 struct linux_prom_translation {
 428         unsigned long virt;
 429         unsigned long size;
 430         unsigned long data;
 431 };
 432
 433 /* Exported for kernel TLB miss handling in ktlb.S */
 434 struct linux_prom_translation prom_trans[512] __read_mostly;
 435 unsigned int prom_trans_ents __read_mostly;
 436
 437 /* Exported for SMP bootup purposes. */
 438 unsigned long kern_locked_tte_data;
 439
 440 /* The obp translations are saved based on 8k pagesize, since obp can
 441  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 442  * HI_OBP_ADDRESS range are handled in ktlb.S.
 443  */
 444 static inline int in_obp_range(unsigned long vaddr)
 445 {
 446         return (vaddr >= LOW_OBP_ADDRESS &&
 447                 vaddr < HI_OBP_ADDRESS);
 448 }
 449
 450 static int cmp_ptrans(const void *a, const void *b)
 451 {
 452         const struct linux_prom_translation *x = a, *y = b;
 453
 454         if (x->virt > y->virt)
 455                 return 1;
 456         if (x->virt < y->virt)
 457                 return -1;
 458         return 0;
 459 }
 460
 461 /* Read OBP translations property into 'prom_trans[]'.  */
 462 static void __init read_obp_translations(void)
 463 {
 464         int n, node, ents, first, last, i;
 465
 466         node = prom_finddevice("/virtual-memory");
 467         n = prom_getproplen(node, "translations");
 468         if (unlikely(n == 0 || n == -1)) {
 469                 prom_printf("prom_mappings: Couldn't get size.\n");
 470                 prom_halt();
 471         }
 472         if (unlikely(n > sizeof(prom_trans))) {
 473                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
 474                 prom_halt();
 475         }
 476
 477         if ((n = prom_getproperty(node, "translations",
 478                                   (char *)&prom_trans[0],
 479                                   sizeof(prom_trans))) == -1) {
 480                 prom_printf("prom_mappings: Couldn't get property.\n");
 481                 prom_halt();
 482         }
 483
 484         n = n / sizeof(struct linux_prom_translation);
 485
 486         ents = n;
 487
 488         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 489              cmp_ptrans, NULL);
 490
 491         /* Now kick out all the non-OBP entries.  */
 492         for (i = 0; i < ents; i++) {
 493                 if (in_obp_range(prom_trans[i].virt))
 494                         break;
 495         }
 496         first = i;
 497         for (; i < ents; i++) {
 498                 if (!in_obp_range(prom_trans[i].virt))
 499                         break;
 500         }
 501         last = i;
 502
 503         for (i = 0; i < (last - first); i++) {
 504                 struct linux_prom_translation *src = &prom_trans[i + first];
 505                 struct linux_prom_translation *dest = &prom_trans[i];
 506
 507                 *dest = *src;
 508         }
 509         for (; i < ents; i++) {
 510                 struct linux_prom_translation *dest = &prom_trans[i];
 511                 dest->virt = dest->size = dest->data = 0x0UL;
 512         }
 513
 514         prom_trans_ents = last - first;
 515
 516         if (tlb_type == spitfire) {
 517                 /* Clear diag TTE bits. */
 518                 for (i = 0; i < prom_trans_ents; i++)
 519                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 520         }
 521 }
 522
 523 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 524                                        unsigned long pte,
 525                                        unsigned long mmu)
 526 {
 527         register unsigned long func asm("%o5");
 528         register unsigned long arg0 asm("%o0");
 529         register unsigned long arg1 asm("%o1");
 530         register unsigned long arg2 asm("%o2");
 531         register unsigned long arg3 asm("%o3");
 532
 533         func = HV_FAST_MMU_MAP_PERM_ADDR;
 534         arg0 = vaddr;
 535         arg1 = 0;
 536         arg2 = pte;
 537         arg3 = mmu;
 538         __asm__ __volatile__("ta        0x80"
 539                              : "=&r" (func), "=&r" (arg0),
 540                                "=&r" (arg1), "=&r" (arg2),
 541                                "=&r" (arg3)
 542                              : "0" (func), "1" (arg0), "2" (arg1),
 543                                "3" (arg2), "4" (arg3));
 544         if (arg0 != 0) {
 545                 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
 546                             "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
 547                 prom_halt();
 548         }
 549 }
 550
 551 static unsigned long kern_large_tte(unsigned long paddr);
 552
 553 static void __init remap_kernel(void)
 554 {
 555         unsigned long phys_page, tte_vaddr, tte_data;
 556         int tlb_ent = sparc64_highest_locked_tlbent();
 557
 558         tte_vaddr = (unsigned long) KERNBASE;
 559         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
 560         tte_data = kern_large_tte(phys_page);
 561
 562         kern_locked_tte_data = tte_data;
 563
 564         /* Now lock us into the TLBs via Hypervisor or OBP. */
 565         if (tlb_type == hypervisor) {
 566                 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 567                 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 568                 if (bigkernel) {
 569                         tte_vaddr += 0x400000;
 570                         tte_data += 0x400000;
 571                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 572                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 573                 }
 574         } else {
 575                 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
 576                 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
 577                 if (bigkernel) {
 578                         tlb_ent -= 1;
 579                         prom_dtlb_load(tlb_ent,
 580                                        tte_data + 0x400000,
 581                                        tte_vaddr + 0x400000);
 582                         prom_itlb_load(tlb_ent,
 583                                        tte_data + 0x400000,
 584                                        tte_vaddr + 0x400000);
 585                 }
 586                 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
 587         }
 588         if (tlb_type == cheetah_plus) {
 589                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 590                                             CTX_CHEETAH_PLUS_NUC);
 591                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 592                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 593         }
 594 }
 595
 596
 597 static void __init inherit_prom_mappings(void)
 598 {
 599         read_obp_translations();
 600
 601         /* Now fixup OBP's idea about where we really are mapped. */
 602         prom_printf("Remapping the kernel... ");
 603         remap_kernel();
 604         prom_printf("done.\n");
 605 }
 606
 607 void prom_world(int enter)
 608 {
 609         if (!enter)
 610                 set_fs((mm_segment_t) { get_thread_current_ds() });
 611
 612         __asm__ __volatile__("flushw");
 613 }
 614
 615 #ifdef DCACHE_ALIASING_POSSIBLE
 616 void __flush_dcache_range(unsigned long start, unsigned long end)
 617 {
 618         unsigned long va;
 619
 620         if (tlb_type == spitfire) {
 621                 int n = 0;
 622
 623                 for (va = start; va < end; va += 32) {
 624                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 625                         if (++n >= 512)
 626                                 break;
 627                 }
 628         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 629                 start = __pa(start);
 630                 end = __pa(end);
 631                 for (va = start; va < end; va += 32)
 632                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 633                                              "membar #Sync"
 634                                              : /* no outputs */
 635                                              : "r" (va),
 636                                                "i" (ASI_DCACHE_INVALIDATE));
 637         }
 638 }
 639 #endif /* DCACHE_ALIASING_POSSIBLE */
 640
 641 /* Caller does TLB context flushing on local CPU if necessary.
 642  * The caller also ensures that CTX_VALID(mm->context) is false.
 643  *
 644  * We must be careful about boundary cases so that we never
 645  * let the user have CTX 0 (nucleus) or we ever use a CTX
 646  * version of zero (and thus NO_CONTEXT would not be caught
 647  * by version mis-match tests in mmu_context.h).
 648  *
 649  * Always invoked with interrupts disabled.
 650  */
 651 void get_new_mmu_context(struct mm_struct *mm)
 652 {
 653         unsigned long ctx, new_ctx;
 654         unsigned long orig_pgsz_bits;
 655         unsigned long flags;
 656         int new_version;
 657
 658         spin_lock_irqsave(&ctx_alloc_lock, flags);
 659         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 660         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 661         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 662         new_version = 0;
 663         if (new_ctx >= (1 << CTX_NR_BITS)) {
 664                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 665                 if (new_ctx >= ctx) {
 666                         int i;
 667                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 668                                 CTX_FIRST_VERSION;
 669                         if (new_ctx == 1)
 670                                 new_ctx = CTX_FIRST_VERSION;
 671
 672                         /* Don't call memset, for 16 entries that's just
 673                          * plain silly...
 674                          */
 675                         mmu_context_bmap[0] = 3;
 676                         mmu_context_bmap[1] = 0;
 677                         mmu_context_bmap[2] = 0;
 678                         mmu_context_bmap[3] = 0;
 679                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 680                                 mmu_context_bmap[i + 0] = 0;
 681                                 mmu_context_bmap[i + 1] = 0;
 682                                 mmu_context_bmap[i + 2] = 0;
 683                                 mmu_context_bmap[i + 3] = 0;
 684                         }
 685                         new_version = 1;
 686                         goto out;
 687                 }
 688         }
 689         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 690         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 691 out:
 692         tlb_context_cache = new_ctx;
 693         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 694         spin_unlock_irqrestore(&ctx_alloc_lock, flags);
 695
 696         if (unlikely(new_version))
 697                 smp_new_mmu_context_version();
 698 }
 699
 700 void sparc_ultra_dump_itlb(void)
 701 {
 702         int slot;
 703
 704         if (tlb_type == spitfire) {
 705                 printk ("Contents of itlb: ");
 706                 for (slot = 0; slot < 14; slot++) printk ("    ");
 707                 printk ("%2x:%016lx,%016lx\n",
 708                         0,
 709                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
 710                 for (slot = 1; slot < 64; slot+=3) {
 711                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 712                                 slot,
 713                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
 714                                 slot+1,
 715                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
 716                                 slot+2,
 717                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
 718                 }
 719         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 720                 printk ("Contents of itlb0:\n");
 721                 for (slot = 0; slot < 16; slot+=2) {
 722                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 723                                 slot,
 724                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
 725                                 slot+1,
 726                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
 727                 }
 728                 printk ("Contents of itlb2:\n");
 729                 for (slot = 0; slot < 128; slot+=2) {
 730                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 731                                 slot,
 732                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
 733                                 slot+1,
 734                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
 735                 }
 736         }
 737 }
 738
 739 void sparc_ultra_dump_dtlb(void)
 740 {
 741         int slot;
 742
 743         if (tlb_type == spitfire) {
 744                 printk ("Contents of dtlb: ");
 745                 for (slot = 0; slot < 14; slot++) printk ("    ");
 746                 printk ("%2x:%016lx,%016lx\n", 0,
 747                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
 748                 for (slot = 1; slot < 64; slot+=3) {
 749                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 750                                 slot,
 751                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
 752                                 slot+1,
 753                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
 754                                 slot+2,
 755                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
 756                 }
 757         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 758                 printk ("Contents of dtlb0:\n");
 759                 for (slot = 0; slot < 16; slot+=2) {
 760                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 761                                 slot,
 762                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
 763                                 slot+1,
 764                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
 765                 }
 766                 printk ("Contents of dtlb2:\n");
 767                 for (slot = 0; slot < 512; slot+=2) {
 768                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 769                                 slot,
 770                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
 771                                 slot+1,
 772                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
 773                 }
 774                 if (tlb_type == cheetah_plus) {
 775                         printk ("Contents of dtlb3:\n");
 776                         for (slot = 0; slot < 512; slot+=2) {
 777                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 778                                         slot,
 779                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
 780                                         slot+1,
 781                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
 782                         }
 783                 }
 784         }
 785 }
 786
 787 extern unsigned long cmdline_memory_size;
 788
 789 /* Find a free area for the bootmem map, avoiding the kernel image
 790  * and the initial ramdisk.
 791  */
 792 static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
 793                                                unsigned long end_pfn)
 794 {
 795         unsigned long avoid_start, avoid_end, bootmap_size;
 796         int i;
 797
 798         bootmap_size = ((end_pfn - start_pfn) + 7) / 8;
 799         bootmap_size = ALIGN(bootmap_size, sizeof(long));
 800
 801         avoid_start = avoid_end = 0;
 802 #ifdef CONFIG_BLK_DEV_INITRD
 803         avoid_start = initrd_start;
 804         avoid_end = PAGE_ALIGN(initrd_end);
 805 #endif
 806
 807 #ifdef CONFIG_DEBUG_BOOTMEM
 808         prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
 809                     kern_base, PAGE_ALIGN(kern_base + kern_size),
 810                     avoid_start, avoid_end);
 811 #endif
 812         for (i = 0; i < pavail_ents; i++) {
 813                 unsigned long start, end;
 814
 815                 start = pavail[i].phys_addr;
 816                 end = start + pavail[i].reg_size;
 817
 818                 while (start < end) {
 819                         if (start >= kern_base &&
 820                             start < PAGE_ALIGN(kern_base + kern_size)) {
 821                                 start = PAGE_ALIGN(kern_base + kern_size);
 822                                 continue;
 823                         }
 824                         if (start >= avoid_start && start < avoid_end) {
 825                                 start = avoid_end;
 826                                 continue;
 827                         }
 828
 829                         if ((end - start) < bootmap_size)
 830                                 break;
 831
 832                         if (start < kern_base &&
 833                             (start + bootmap_size) > kern_base) {
 834                                 start = PAGE_ALIGN(kern_base + kern_size);
 835                                 continue;
 836                         }
 837
 838                         if (start < avoid_start &&
 839                             (start + bootmap_size) > avoid_start) {
 840                                 start = avoid_end;
 841                                 continue;
 842                         }
 843
 844                         /* OK, it doesn't overlap anything, use it.  */
 845 #ifdef CONFIG_DEBUG_BOOTMEM
 846                         prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
 847                                     start >> PAGE_SHIFT, start);
 848 #endif
 849                         return start >> PAGE_SHIFT;
 850                 }
 851         }
 852
 853         prom_printf("Cannot find free area for bootmap, aborting.\n");
 854         prom_halt();
 855 }
 856
 857 static unsigned long __init bootmem_init(unsigned long *pages_avail,
 858                                          unsigned long phys_base)
 859 {
 860         unsigned long bootmap_size, end_pfn;
 861         unsigned long end_of_phys_memory = 0UL;
 862         unsigned long bootmap_pfn, bytes_avail, size;
 863         int i;
 864
 865 #ifdef CONFIG_DEBUG_BOOTMEM
 866         prom_printf("bootmem_init: Scan pavail, ");
 867 #endif
 868
 869         bytes_avail = 0UL;
 870         for (i = 0; i < pavail_ents; i++) {
 871                 end_of_phys_memory = pavail[i].phys_addr +
 872                         pavail[i].reg_size;
 873                 bytes_avail += pavail[i].reg_size;
 874                 if (cmdline_memory_size) {
 875                         if (bytes_avail > cmdline_memory_size) {
 876                                 unsigned long slack = bytes_avail - cmdline_memory_size;
 877
 878                                 bytes_avail -= slack;
 879                                 end_of_phys_memory -= slack;
 880
 881                                 pavail[i].reg_size -= slack;
 882                                 if ((long)pavail[i].reg_size <= 0L) {
 883                                         pavail[i].phys_addr = 0xdeadbeefUL;
 884                                         pavail[i].reg_size = 0UL;
 885                                         pavail_ents = i;
 886                                 } else {
 887                                         pavail[i+1].reg_size = 0Ul;
 888                                         pavail[i+1].phys_addr = 0xdeadbeefUL;
 889                                         pavail_ents = i + 1;
 890                                 }
 891                                 break;
 892                         }
 893                 }
 894         }
 895
 896         *pages_avail = bytes_avail >> PAGE_SHIFT;
 897
 898         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
 899
 900 #ifdef CONFIG_BLK_DEV_INITRD
 901         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
 902         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 903                 unsigned long ramdisk_image = sparc_ramdisk_image ?
 904                         sparc_ramdisk_image : sparc_ramdisk_image64;
 905                 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
 906                         ramdisk_image -= KERNBASE;
 907                 initrd_start = ramdisk_image + phys_base;
 908                 initrd_end = initrd_start + sparc_ramdisk_size;
 909                 if (initrd_end > end_of_phys_memory) {
 910                         printk(KERN_CRIT "initrd extends beyond end of memory "
 911                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
 912                                initrd_end, end_of_phys_memory);
 913                         initrd_start = 0;
 914                         initrd_end = 0;
 915                 }
 916         }
 917 #endif
 918         /* Initialize the boot-time allocator. */
 919         max_pfn = max_low_pfn = end_pfn;
 920         min_low_pfn = (phys_base >> PAGE_SHIFT);
 921
 922         bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
 923
 924 #ifdef CONFIG_DEBUG_BOOTMEM
 925         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
 926                     min_low_pfn, bootmap_pfn, max_low_pfn);
 927 #endif
 928         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
 929                                          min_low_pfn, end_pfn);
 930
 931         /* Now register the available physical memory with the
 932          * allocator.
 933          */
 934         for (i = 0; i < pavail_ents; i++) {
 935 #ifdef CONFIG_DEBUG_BOOTMEM
 936                 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
 937                             i, pavail[i].phys_addr, pavail[i].reg_size);
 938 #endif
 939                 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
 940         }
 941
 942 #ifdef CONFIG_BLK_DEV_INITRD
 943         if (initrd_start) {
 944                 size = initrd_end - initrd_start;
 945
 946                 /* Resert the initrd image area. */
 947 #ifdef CONFIG_DEBUG_BOOTMEM
 948                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
 949                         initrd_start, initrd_end);
 950 #endif
 951                 reserve_bootmem(initrd_start, size);
 952                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
 953
 954                 initrd_start += PAGE_OFFSET;
 955                 initrd_end += PAGE_OFFSET;
 956         }
 957 #endif
 958         /* Reserve the kernel text/data/bss. */
 959 #ifdef CONFIG_DEBUG_BOOTMEM
 960         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
 961 #endif
 962         reserve_bootmem(kern_base, kern_size);
 963         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
 964
 965         /* Reserve the bootmem map.   We do not account for it
 966          * in pages_avail because we will release that memory
 967          * in free_all_bootmem.
 968          */
 969         size = bootmap_size;
 970 #ifdef CONFIG_DEBUG_BOOTMEM
 971         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
 972                     (bootmap_pfn << PAGE_SHIFT), size);
 973 #endif
 974         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
 975         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
 976
 977         for (i = 0; i < pavail_ents; i++) {
 978                 unsigned long start_pfn, end_pfn;
 979
 980                 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
 981                 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
 982 #ifdef CONFIG_DEBUG_BOOTMEM
 983                 prom_printf("memory_present(0, %lx, %lx)\n",
 984                             start_pfn, end_pfn);
 985 #endif
 986                 memory_present(0, start_pfn, end_pfn);
 987         }
 988
 989         sparse_init();
 990
 991         return end_pfn;
 992 }
 993
 994 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
 995 static int pall_ents __initdata;
 996
 997 #ifdef CONFIG_DEBUG_PAGEALLOC
 998 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
 999 {
1000         unsigned long vstart = PAGE_OFFSET + pstart;
1001         unsigned long vend = PAGE_OFFSET + pend;
1002         unsigned long alloc_bytes = 0UL;
1003
1004         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1005                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1006                             vstart, vend);
1007                 prom_halt();
1008         }
1009
1010         while (vstart < vend) {
1011                 unsigned long this_end, paddr = __pa(vstart);
1012                 pgd_t *pgd = pgd_offset_k(vstart);
1013                 pud_t *pud;
1014                 pmd_t *pmd;
1015                 pte_t *pte;
1016
1017                 pud = pud_offset(pgd, vstart);
1018                 if (pud_none(*pud)) {
1019                         pmd_t *new;
1020
1021                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1022                         alloc_bytes += PAGE_SIZE;
1023                         pud_populate(&init_mm, pud, new);
1024                 }
1025
1026                 pmd = pmd_offset(pud, vstart);
1027                 if (!pmd_present(*pmd)) {
1028                         pte_t *new;
1029
1030                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1031                         alloc_bytes += PAGE_SIZE;
1032                         pmd_populate_kernel(&init_mm, pmd, new);
1033                 }
1034
1035                 pte = pte_offset_kernel(pmd, vstart);
1036                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1037                 if (this_end > vend)
1038                         this_end = vend;
1039
1040                 while (vstart < this_end) {
1041                         pte_val(*pte) = (paddr | pgprot_val(prot));
1042
1043                         vstart += PAGE_SIZE;
1044                         paddr += PAGE_SIZE;
1045                         pte++;
1046                 }
1047         }
1048
1049         return alloc_bytes;
1050 }
1051
1052 extern unsigned int kvmap_linear_patch[1];
1053 #endif /* CONFIG_DEBUG_PAGEALLOC */
1054
1055 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1056 {
1057         const unsigned long shift_256MB = 28;
1058         const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1059         const unsigned long size_256MB = (1UL << shift_256MB);
1060
1061         while (start < end) {
1062                 long remains;
1063
1064                 remains = end - start;
1065                 if (remains < size_256MB)
1066                         break;
1067
1068                 if (start & mask_256MB) {
1069                         start = (start + size_256MB) & ~mask_256MB;
1070                         continue;
1071                 }
1072
1073                 while (remains >= size_256MB) {
1074                         unsigned long index = start >> shift_256MB;
1075
1076                         __set_bit(index, kpte_linear_bitmap);
1077
1078                         start += size_256MB;
1079                         remains -= size_256MB;
1080                 }
1081         }
1082 }
1083
1084 static void __init kernel_physical_mapping_init(void)
1085 {
1086         unsigned long i;
1087 #ifdef CONFIG_DEBUG_PAGEALLOC
1088         unsigned long mem_alloced = 0UL;
1089 #endif
1090
1091         read_obp_memory("reg", &pall[0], &pall_ents);
1092
1093         for (i = 0; i < pall_ents; i++) {
1094                 unsigned long phys_start, phys_end;
1095
1096                 phys_start = pall[i].phys_addr;
1097                 phys_end = phys_start + pall[i].reg_size;
1098
1099                 mark_kpte_bitmap(phys_start, phys_end);
1100
1101 #ifdef CONFIG_DEBUG_PAGEALLOC
1102                 mem_alloced += kernel_map_range(phys_start, phys_end,
1103                                                 PAGE_KERNEL);
1104 #endif
1105         }
1106
1107 #ifdef CONFIG_DEBUG_PAGEALLOC
1108         printk("Allocated %ld bytes for kernel page tables.\n",
1109                mem_alloced);
1110
1111         kvmap_linear_patch[0] = 0x01000000; /* nop */
1112         flushi(&kvmap_linear_patch[0]);
1113
1114         __flush_tlb_all();
1115 #endif
1116 }
1117
1118 #ifdef CONFIG_DEBUG_PAGEALLOC
1119 void kernel_map_pages(struct page *page, int numpages, int enable)
1120 {
1121         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1122         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1123
1124         kernel_map_range(phys_start, phys_end,
1125                          (enable ? PAGE_KERNEL : __pgprot(0)));
1126
1127         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1128                                PAGE_OFFSET + phys_end);
1129
1130         /* we should perform an IPI and flush all tlbs,
1131          * but that can deadlock->flush only current cpu.
1132          */
1133         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1134                                  PAGE_OFFSET + phys_end);
1135 }
1136 #endif
1137
1138 unsigned long __init find_ecache_flush_span(unsigned long size)
1139 {
1140         int i;
1141
1142         for (i = 0; i < pavail_ents; i++) {
1143                 if (pavail[i].reg_size >= size)
1144                         return pavail[i].phys_addr;
1145         }
1146
1147         return ~0UL;
1148 }
1149
1150 static void __init tsb_phys_patch(void)
1151 {
1152         struct tsb_ldquad_phys_patch_entry *pquad;
1153         struct tsb_phys_patch_entry *p;
1154
1155         pquad = &__tsb_ldquad_phys_patch;
1156         while (pquad < &__tsb_ldquad_phys_patch_end) {
1157                 unsigned long addr = pquad->addr;
1158
1159                 if (tlb_type == hypervisor)
1160                         *(unsigned int *) addr = pquad->sun4v_insn;
1161                 else
1162                         *(unsigned int *) addr = pquad->sun4u_insn;
1163                 wmb();
1164                 __asm__ __volatile__("flush     %0"
1165                                      : /* no outputs */
1166                                      : "r" (addr));
1167
1168                 pquad++;
1169         }
1170
1171         p = &__tsb_phys_patch;
1172         while (p < &__tsb_phys_patch_end) {
1173                 unsigned long addr = p->addr;
1174
1175                 *(unsigned int *) addr = p->insn;
1176                 wmb();
1177                 __asm__ __volatile__("flush     %0"
1178                                      : /* no outputs */
1179                                      : "r" (addr));
1180
1181                 p++;
1182         }
1183 }
1184
1185 /* Don't mark as init, we give this to the Hypervisor.  */
1186 static struct hv_tsb_descr ktsb_descr[2];
1187 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1188
1189 static void __init sun4v_ktsb_init(void)
1190 {
1191         unsigned long ktsb_pa;
1192
1193         /* First KTSB for PAGE_SIZE mappings.  */
1194         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1195
1196         switch (PAGE_SIZE) {
1197         case 8 * 1024:
1198         default:
1199                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1200                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1201                 break;
1202
1203         case 64 * 1024:
1204                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1205                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1206                 break;
1207
1208         case 512 * 1024:
1209                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1210                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1211                 break;
1212
1213         case 4 * 1024 * 1024:
1214                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1215                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1216                 break;
1217         };
1218
1219         ktsb_descr[0].assoc = 1;
1220         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1221         ktsb_descr[0].ctx_idx = 0;
1222         ktsb_descr[0].tsb_base = ktsb_pa;
1223         ktsb_descr[0].resv = 0;
1224
1225         /* Second KTSB for 4MB/256MB mappings.  */
1226         ktsb_pa = (kern_base +
1227                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1228
1229         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1230         ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1231                                    HV_PGSZ_MASK_256MB);
1232         ktsb_descr[1].assoc = 1;
1233         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1234         ktsb_descr[1].ctx_idx = 0;
1235         ktsb_descr[1].tsb_base = ktsb_pa;
1236         ktsb_descr[1].resv = 0;
1237 }
1238
1239 void __cpuinit sun4v_ktsb_register(void)
1240 {
1241         register unsigned long func asm("%o5");
1242         register unsigned long arg0 asm("%o0");
1243         register unsigned long arg1 asm("%o1");
1244         unsigned long pa;
1245
1246         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1247
1248         func = HV_FAST_MMU_TSB_CTX0;
1249         arg0 = 2;
1250         arg1 = pa;
1251         __asm__ __volatile__("ta        %6"
1252                              : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1253                              : "0" (func), "1" (arg0), "2" (arg1),
1254                                "i" (HV_FAST_TRAP));
1255 }
1256
1257 /* paging_init() sets up the page tables */
1258
1259 extern void cheetah_ecache_flush_init(void);
1260 extern void sun4v_patch_tlb_handlers(void);
1261
1262 static unsigned long last_valid_pfn;
1263 pgd_t swapper_pg_dir[2048];
1264
1265 static void sun4u_pgprot_init(void);
1266 static void sun4v_pgprot_init(void);
1267
1268 void __init paging_init(void)
1269 {
1270         unsigned long end_pfn, pages_avail, shift, phys_base;
1271         unsigned long real_end, i;
1272
1273         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1274         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1275
1276         /* Invalidate both kernel TSBs.  */
1277         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1278         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1279
1280         if (tlb_type == hypervisor)
1281                 sun4v_pgprot_init();
1282         else
1283                 sun4u_pgprot_init();
1284
1285         if (tlb_type == cheetah_plus ||
1286             tlb_type == hypervisor)
1287                 tsb_phys_patch();
1288
1289         if (tlb_type == hypervisor) {
1290                 sun4v_patch_tlb_handlers();
1291                 sun4v_ktsb_init();
1292         }
1293
1294         /* Find available physical memory... */
1295         read_obp_memory("available", &pavail[0], &pavail_ents);
1296
1297         phys_base = 0xffffffffffffffffUL;
1298         for (i = 0; i < pavail_ents; i++)
1299                 phys_base = min(phys_base, pavail[i].phys_addr);
1300
1301         set_bit(0, mmu_context_bmap);
1302
1303         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1304
1305         real_end = (unsigned long)_end;
1306         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1307                 bigkernel = 1;
1308         if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1309                 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1310                 prom_halt();
1311         }
1312
1313         /* Set kernel pgd to upper alias so physical page computations
1314          * work.
1315          */
1316         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1317
1318         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1319
1320         /* Now can init the kernel/bad page tables. */
1321         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1322                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1323
1324         inherit_prom_mappings();
1325
1326         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1327         setup_tba();
1328
1329         __flush_tlb_all();
1330
1331         if (tlb_type == hypervisor)
1332                 sun4v_ktsb_register();
1333
1334         /* Setup bootmem... */
1335         pages_avail = 0;
1336         last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1337
1338         max_mapnr = last_valid_pfn;
1339
1340         kernel_physical_mapping_init();
1341
1342         {
1343                 unsigned long zones_size[MAX_NR_ZONES];
1344                 unsigned long zholes_size[MAX_NR_ZONES];
1345                 int znum;
1346
1347                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1348                         zones_size[znum] = zholes_size[znum] = 0;
1349
1350                 zones_size[ZONE_DMA] = end_pfn;
1351                 zholes_size[ZONE_DMA] = end_pfn - pages_avail;
1352
1353                 free_area_init_node(0, &contig_page_data, zones_size,
1354                                     __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1355                                     zholes_size);
1356         }
1357
1358         device_scan();
1359 }
1360
1361 static void __init taint_real_pages(void)
1362 {
1363         int i;
1364
1365         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1366
1367         /* Find changes discovered in the physmem available rescan and
1368          * reserve the lost portions in the bootmem maps.
1369          */
1370         for (i = 0; i < pavail_ents; i++) {
1371                 unsigned long old_start, old_end;
1372
1373                 old_start = pavail[i].phys_addr;
1374                 old_end = old_start +
1375                         pavail[i].reg_size;
1376                 while (old_start < old_end) {
1377                         int n;
1378
1379                         for (n = 0; pavail_rescan_ents; n++) {
1380                                 unsigned long new_start, new_end;
1381
1382                                 new_start = pavail_rescan[n].phys_addr;
1383                                 new_end = new_start +
1384                                         pavail_rescan[n].reg_size;
1385
1386                                 if (new_start <= old_start &&
1387                                     new_end >= (old_start + PAGE_SIZE)) {
1388                                         set_bit(old_start >> 22,
1389                                                 sparc64_valid_addr_bitmap);
1390                                         goto do_next_page;
1391                                 }
1392                         }
1393                         reserve_bootmem(old_start, PAGE_SIZE);
1394
1395                 do_next_page:
1396                         old_start += PAGE_SIZE;
1397                 }
1398         }
1399 }
1400
1401 void __init mem_init(void)
1402 {
1403         unsigned long codepages, datapages, initpages;
1404         unsigned long addr, last;
1405         int i;
1406
1407         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1408         i += 1;
1409         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1410         if (sparc64_valid_addr_bitmap == NULL) {
1411                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1412                 prom_halt();
1413         }
1414         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1415
1416         addr = PAGE_OFFSET + kern_base;
1417         last = PAGE_ALIGN(kern_size) + addr;
1418         while (addr < last) {
1419                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1420                 addr += PAGE_SIZE;
1421         }
1422
1423         taint_real_pages();
1424
1425         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1426
1427 #ifdef CONFIG_DEBUG_BOOTMEM
1428         prom_printf("mem_init: Calling free_all_bootmem().\n");
1429 #endif
1430         totalram_pages = num_physpages = free_all_bootmem() - 1;
1431
1432         /*
1433          * Set up the zero page, mark it reserved, so that page count
1434          * is not manipulated when freeing the page from user ptes.
1435          */
1436         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1437         if (mem_map_zero == NULL) {
1438                 prom_printf("paging_init: Cannot alloc zero page.\n");
1439                 prom_halt();
1440         }
1441         SetPageReserved(mem_map_zero);
1442
1443         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1444         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1445         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1446         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1447         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1448         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1449
1450         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1451                nr_free_pages() << (PAGE_SHIFT-10),
1452                codepages << (PAGE_SHIFT-10),
1453                datapages << (PAGE_SHIFT-10),
1454                initpages << (PAGE_SHIFT-10),
1455                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1456
1457         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1458                 cheetah_ecache_flush_init();
1459 }
1460
1461 void free_initmem(void)
1462 {
1463         unsigned long addr, initend;
1464
1465         /*
1466          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1467          */
1468         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1469         initend = (unsigned long)(__init_end) & PAGE_MASK;
1470         for (; addr < initend; addr += PAGE_SIZE) {
1471                 unsigned long page;
1472                 struct page *p;
1473
1474                 page = (addr +
1475                         ((unsigned long) __va(kern_base)) -
1476                         ((unsigned long) KERNBASE));
1477                 memset((void *)addr, 0xcc, PAGE_SIZE);
1478                 p = virt_to_page(page);
1479
1480                 ClearPageReserved(p);
1481                 init_page_count(p);
1482                 __free_page(p);
1483                 num_physpages++;
1484                 totalram_pages++;
1485         }
1486 }
1487
1488 #ifdef CONFIG_BLK_DEV_INITRD
1489 void free_initrd_mem(unsigned long start, unsigned long end)
1490 {
1491         if (start < end)
1492                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1493         for (; start < end; start += PAGE_SIZE) {
1494                 struct page *p = virt_to_page(start);
1495
1496                 ClearPageReserved(p);
1497                 init_page_count(p);
1498                 __free_page(p);
1499                 num_physpages++;
1500                 totalram_pages++;
1501         }
1502 }
1503 #endif
1504
1505 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
1506 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
1507 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1508 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1509 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1510 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1511
1512 pgprot_t PAGE_KERNEL __read_mostly;
1513 EXPORT_SYMBOL(PAGE_KERNEL);
1514
1515 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1516 pgprot_t PAGE_COPY __read_mostly;
1517
1518 pgprot_t PAGE_SHARED __read_mostly;
1519 EXPORT_SYMBOL(PAGE_SHARED);
1520
1521 pgprot_t PAGE_EXEC __read_mostly;
1522 unsigned long pg_iobits __read_mostly;
1523
1524 unsigned long _PAGE_IE __read_mostly;
1525
1526 unsigned long _PAGE_E __read_mostly;
1527 EXPORT_SYMBOL(_PAGE_E);
1528
1529 unsigned long _PAGE_CACHE __read_mostly;
1530 EXPORT_SYMBOL(_PAGE_CACHE);
1531
1532 static void prot_init_common(unsigned long page_none,
1533                              unsigned long page_shared,
1534                              unsigned long page_copy,
1535                              unsigned long page_readonly,
1536                              unsigned long page_exec_bit)
1537 {
1538         PAGE_COPY = __pgprot(page_copy);
1539         PAGE_SHARED = __pgprot(page_shared);
1540
1541         protection_map[0x0] = __pgprot(page_none);
1542         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1543         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1544         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1545         protection_map[0x4] = __pgprot(page_readonly);
1546         protection_map[0x5] = __pgprot(page_readonly);
1547         protection_map[0x6] = __pgprot(page_copy);
1548         protection_map[0x7] = __pgprot(page_copy);
1549         protection_map[0x8] = __pgprot(page_none);
1550         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1551         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1552         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1553         protection_map[0xc] = __pgprot(page_readonly);
1554         protection_map[0xd] = __pgprot(page_readonly);
1555         protection_map[0xe] = __pgprot(page_shared);
1556         protection_map[0xf] = __pgprot(page_shared);
1557 }
1558
1559 static void __init sun4u_pgprot_init(void)
1560 {
1561         unsigned long page_none, page_shared, page_copy, page_readonly;
1562         unsigned long page_exec_bit;
1563
1564         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1565                                 _PAGE_CACHE_4U | _PAGE_P_4U |
1566                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1567                                 _PAGE_EXEC_4U);
1568         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1569                                        _PAGE_CACHE_4U | _PAGE_P_4U |
1570                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1571                                        _PAGE_EXEC_4U | _PAGE_L_4U);
1572         PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1573
1574         _PAGE_IE = _PAGE_IE_4U;
1575         _PAGE_E = _PAGE_E_4U;
1576         _PAGE_CACHE = _PAGE_CACHE_4U;
1577
1578         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1579                      __ACCESS_BITS_4U | _PAGE_E_4U);
1580
1581         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1582                 0xfffff80000000000;
1583         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1584                                    _PAGE_P_4U | _PAGE_W_4U);
1585
1586         /* XXX Should use 256MB on Panther. XXX */
1587         kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1588
1589         _PAGE_SZBITS = _PAGE_SZBITS_4U;
1590         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1591                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1592                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1593
1594
1595         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1596         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1597                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1598         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1599                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1600         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1601                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1602
1603         page_exec_bit = _PAGE_EXEC_4U;
1604
1605         prot_init_common(page_none, page_shared, page_copy, page_readonly,
1606                          page_exec_bit);
1607 }
1608
1609 static void __init sun4v_pgprot_init(void)
1610 {
1611         unsigned long page_none, page_shared, page_copy, page_readonly;
1612         unsigned long page_exec_bit;
1613
1614         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1615                                 _PAGE_CACHE_4V | _PAGE_P_4V |
1616                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1617                                 _PAGE_EXEC_4V);
1618         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1619         PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1620
1621         _PAGE_IE = _PAGE_IE_4V;
1622         _PAGE_E = _PAGE_E_4V;
1623         _PAGE_CACHE = _PAGE_CACHE_4V;
1624
1625         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1626                 0xfffff80000000000;
1627         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1628                                    _PAGE_P_4V | _PAGE_W_4V);
1629
1630         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1631                 0xfffff80000000000;
1632         kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1633                                    _PAGE_P_4V | _PAGE_W_4V);
1634
1635         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1636                      __ACCESS_BITS_4V | _PAGE_E_4V);
1637
1638         _PAGE_SZBITS = _PAGE_SZBITS_4V;
1639         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1640                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1641                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1642                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1643
1644         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1645         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1646                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1647         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1648                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1649         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1650                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1651
1652         page_exec_bit = _PAGE_EXEC_4V;
1653
1654         prot_init_common(page_none, page_shared, page_copy, page_readonly,
1655                          page_exec_bit);
1656 }
1657
1658 unsigned long pte_sz_bits(unsigned long sz)
1659 {
1660         if (tlb_type == hypervisor) {
1661                 switch (sz) {
1662                 case 8 * 1024:
1663                 default:
1664                         return _PAGE_SZ8K_4V;
1665                 case 64 * 1024:
1666                         return _PAGE_SZ64K_4V;
1667                 case 512 * 1024:
1668                         return _PAGE_SZ512K_4V;
1669                 case 4 * 1024 * 1024:
1670                         return _PAGE_SZ4MB_4V;
1671                 };
1672         } else {
1673                 switch (sz) {
1674                 case 8 * 1024:
1675                 default:
1676                         return _PAGE_SZ8K_4U;
1677                 case 64 * 1024:
1678                         return _PAGE_SZ64K_4U;
1679                 case 512 * 1024:
1680                         return _PAGE_SZ512K_4U;
1681                 case 4 * 1024 * 1024:
1682                         return _PAGE_SZ4MB_4U;
1683                 };
1684         }
1685 }
1686
1687 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1688 {
1689         pte_t pte;
1690
1691         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
1692         pte_val(pte) |= (((unsigned long)space) << 32);
1693         pte_val(pte) |= pte_sz_bits(page_size);
1694
1695         return pte;
1696 }
1697
1698 static unsigned long kern_large_tte(unsigned long paddr)
1699 {
1700         unsigned long val;
1701
1702         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1703                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1704                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1705         if (tlb_type == hypervisor)
1706                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1707                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1708                        _PAGE_EXEC_4V | _PAGE_W_4V);
1709
1710         return val | paddr;
1711 }
1712
1713 /*
1714  * Translate PROM's mapping we capture at boot time into physical address.
1715  * The second parameter is only set from prom_callback() invocations.
1716  */
1717 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1718 {
1719         unsigned long mask;
1720         int i;
1721
1722         mask = _PAGE_PADDR_4U;
1723         if (tlb_type == hypervisor)
1724                 mask = _PAGE_PADDR_4V;
1725
1726         for (i = 0; i < prom_trans_ents; i++) {
1727                 struct linux_prom_translation *p = &prom_trans[i];
1728
1729                 if (promva >= p->virt &&
1730                     promva < (p->virt + p->size)) {
1731                         unsigned long base = p->data & mask;
1732
1733                         if (error)
1734                                 *error = 0;
1735                         return base + (promva & (8192 - 1));
1736                 }
1737         }
1738         if (error)
1739                 *error = 1;
1740         return 0UL;
1741 }
1742
1743 /* XXX We should kill off this ugly thing at so me point. XXX */
1744 unsigned long sun4u_get_pte(unsigned long addr)
1745 {
1746         pgd_t *pgdp;
1747         pud_t *pudp;
1748         pmd_t *pmdp;
1749         pte_t *ptep;
1750         unsigned long mask = _PAGE_PADDR_4U;
1751
1752         if (tlb_type == hypervisor)
1753                 mask = _PAGE_PADDR_4V;
1754
1755         if (addr >= PAGE_OFFSET)
1756                 return addr & mask;
1757
1758         if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1759                 return prom_virt_to_phys(addr, NULL);
1760
1761         pgdp = pgd_offset_k(addr);
1762         pudp = pud_offset(pgdp, addr);
1763         pmdp = pmd_offset(pudp, addr);
1764         ptep = pte_offset_kernel(pmdp, addr);
1765
1766         return pte_val(*ptep) & mask;
1767 }
1768
1769 /* If not locked, zap it. */
1770 void __flush_tlb_all(void)
1771 {
1772         unsigned long pstate;
1773         int i;
1774
1775         __asm__ __volatile__("flushw\n\t"
1776                              "rdpr      %%pstate, %0\n\t"
1777                              "wrpr      %0, %1, %%pstate"
1778                              : "=r" (pstate)
1779                              : "i" (PSTATE_IE));
1780         if (tlb_type == spitfire) {
1781                 for (i = 0; i < 64; i++) {
1782                         /* Spitfire Errata #32 workaround */
1783                         /* NOTE: Always runs on spitfire, so no
1784                          *       cheetah+ page size encodings.
1785                          */
1786                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1787                                              "flush     %%g6"
1788                                              : /* No outputs */
1789                                              : "r" (0),
1790                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1791
1792                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1793                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1794                                                      "membar #Sync"
1795                                                      : /* no outputs */
1796                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1797                                 spitfire_put_dtlb_data(i, 0x0UL);
1798                         }
1799
1800                         /* Spitfire Errata #32 workaround */
1801                         /* NOTE: Always runs on spitfire, so no
1802                          *       cheetah+ page size encodings.
1803                          */
1804                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
1805                                              "flush     %%g6"
1806                                              : /* No outputs */
1807                                              : "r" (0),
1808                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1809
1810                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1811                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1812                                                      "membar #Sync"
1813                                                      : /* no outputs */
1814                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1815                                 spitfire_put_itlb_data(i, 0x0UL);
1816                         }
1817                 }
1818         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1819                 cheetah_flush_dtlb_all();
1820                 cheetah_flush_itlb_all();
1821         }
1822         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
1823                              : : "r" (pstate));
1824 }
1825
1826 #ifdef CONFIG_MEMORY_HOTPLUG
1827
1828 void online_page(struct page *page)
1829 {
1830         ClearPageReserved(page);
1831         set_page_count(page, 0);
1832         free_cold_page(page);
1833         totalram_pages++;
1834         num_physpages++;
1835 }
1836
1837 int remove_memory(u64 start, u64 size)
1838 {
1839         return -EINVAL;
1840 }
1841
1842 #endif /* CONFIG_MEMORY_HOTPLUG */