ea61fec206a76e51e87a7dfd36911a975c874a5e
[sfrench/cifs-2.6.git] / arch / sparc64 / kernel / pci_sun4v.c
1 /* pci_sun4v.c: SUN4V specific PCI controller support.
2  *
3  * Copyright (C) 2006, 2007 David S. Miller (davem@davemloft.net)
4  */
5
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/pci.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/percpu.h>
13 #include <linux/irq.h>
14 #include <linux/msi.h>
15
16 #include <asm/pbm.h>
17 #include <asm/iommu.h>
18 #include <asm/irq.h>
19 #include <asm/upa.h>
20 #include <asm/pstate.h>
21 #include <asm/oplib.h>
22 #include <asm/hypervisor.h>
23 #include <asm/prom.h>
24
25 #include "pci_impl.h"
26 #include "iommu_common.h"
27
28 #include "pci_sun4v.h"
29
30 #define PGLIST_NENTS    (PAGE_SIZE / sizeof(u64))
31
32 struct iommu_batch {
33         struct pci_dev  *pdev;          /* Device mapping is for.       */
34         unsigned long   prot;           /* IOMMU page protections       */
35         unsigned long   entry;          /* Index into IOTSB.            */
36         u64             *pglist;        /* List of physical pages       */
37         unsigned long   npages;         /* Number of pages in list.     */
38 };
39
40 static DEFINE_PER_CPU(struct iommu_batch, pci_iommu_batch);
41
42 /* Interrupts must be disabled.  */
43 static inline void pci_iommu_batch_start(struct pci_dev *pdev, unsigned long prot, unsigned long entry)
44 {
45         struct iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
46
47         p->pdev         = pdev;
48         p->prot         = prot;
49         p->entry        = entry;
50         p->npages       = 0;
51 }
52
53 /* Interrupts must be disabled.  */
54 static long pci_iommu_batch_flush(struct iommu_batch *p)
55 {
56         struct pci_pbm_info *pbm = p->pdev->dev.archdata.host_controller;
57         unsigned long devhandle = pbm->devhandle;
58         unsigned long prot = p->prot;
59         unsigned long entry = p->entry;
60         u64 *pglist = p->pglist;
61         unsigned long npages = p->npages;
62
63         while (npages != 0) {
64                 long num;
65
66                 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
67                                           npages, prot, __pa(pglist));
68                 if (unlikely(num < 0)) {
69                         if (printk_ratelimit())
70                                 printk("pci_iommu_batch_flush: IOMMU map of "
71                                        "[%08lx:%08lx:%lx:%lx:%lx] failed with "
72                                        "status %ld\n",
73                                        devhandle, HV_PCI_TSBID(0, entry),
74                                        npages, prot, __pa(pglist), num);
75                         return -1;
76                 }
77
78                 entry += num;
79                 npages -= num;
80                 pglist += num;
81         }
82
83         p->entry = entry;
84         p->npages = 0;
85
86         return 0;
87 }
88
89 /* Interrupts must be disabled.  */
90 static inline long pci_iommu_batch_add(u64 phys_page)
91 {
92         struct iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
93
94         BUG_ON(p->npages >= PGLIST_NENTS);
95
96         p->pglist[p->npages++] = phys_page;
97         if (p->npages == PGLIST_NENTS)
98                 return pci_iommu_batch_flush(p);
99
100         return 0;
101 }
102
103 /* Interrupts must be disabled.  */
104 static inline long pci_iommu_batch_end(void)
105 {
106         struct iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
107
108         BUG_ON(p->npages >= PGLIST_NENTS);
109
110         return pci_iommu_batch_flush(p);
111 }
112
113 static long pci_arena_alloc(struct iommu_arena *arena, unsigned long npages)
114 {
115         unsigned long n, i, start, end, limit;
116         int pass;
117
118         limit = arena->limit;
119         start = arena->hint;
120         pass = 0;
121
122 again:
123         n = find_next_zero_bit(arena->map, limit, start);
124         end = n + npages;
125         if (unlikely(end >= limit)) {
126                 if (likely(pass < 1)) {
127                         limit = start;
128                         start = 0;
129                         pass++;
130                         goto again;
131                 } else {
132                         /* Scanned the whole thing, give up. */
133                         return -1;
134                 }
135         }
136
137         for (i = n; i < end; i++) {
138                 if (test_bit(i, arena->map)) {
139                         start = i + 1;
140                         goto again;
141                 }
142         }
143
144         for (i = n; i < end; i++)
145                 __set_bit(i, arena->map);
146
147         arena->hint = end;
148
149         return n;
150 }
151
152 static void pci_arena_free(struct iommu_arena *arena, unsigned long base, unsigned long npages)
153 {
154         unsigned long i;
155
156         for (i = base; i < (base + npages); i++)
157                 __clear_bit(i, arena->map);
158 }
159
160 static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
161 {
162         struct iommu *iommu;
163         unsigned long flags, order, first_page, npages, n;
164         void *ret;
165         long entry;
166
167         size = IO_PAGE_ALIGN(size);
168         order = get_order(size);
169         if (unlikely(order >= MAX_ORDER))
170                 return NULL;
171
172         npages = size >> IO_PAGE_SHIFT;
173
174         first_page = __get_free_pages(gfp, order);
175         if (unlikely(first_page == 0UL))
176                 return NULL;
177
178         memset((char *)first_page, 0, PAGE_SIZE << order);
179
180         iommu = pdev->dev.archdata.iommu;
181
182         spin_lock_irqsave(&iommu->lock, flags);
183         entry = pci_arena_alloc(&iommu->arena, npages);
184         spin_unlock_irqrestore(&iommu->lock, flags);
185
186         if (unlikely(entry < 0L))
187                 goto arena_alloc_fail;
188
189         *dma_addrp = (iommu->page_table_map_base +
190                       (entry << IO_PAGE_SHIFT));
191         ret = (void *) first_page;
192         first_page = __pa(first_page);
193
194         local_irq_save(flags);
195
196         pci_iommu_batch_start(pdev,
197                               (HV_PCI_MAP_ATTR_READ |
198                                HV_PCI_MAP_ATTR_WRITE),
199                               entry);
200
201         for (n = 0; n < npages; n++) {
202                 long err = pci_iommu_batch_add(first_page + (n * PAGE_SIZE));
203                 if (unlikely(err < 0L))
204                         goto iommu_map_fail;
205         }
206
207         if (unlikely(pci_iommu_batch_end() < 0L))
208                 goto iommu_map_fail;
209
210         local_irq_restore(flags);
211
212         return ret;
213
214 iommu_map_fail:
215         /* Interrupts are disabled.  */
216         spin_lock(&iommu->lock);
217         pci_arena_free(&iommu->arena, entry, npages);
218         spin_unlock_irqrestore(&iommu->lock, flags);
219
220 arena_alloc_fail:
221         free_pages(first_page, order);
222         return NULL;
223 }
224
225 static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
226 {
227         struct pci_pbm_info *pbm;
228         struct iommu *iommu;
229         unsigned long flags, order, npages, entry;
230         u32 devhandle;
231
232         npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
233         iommu = pdev->dev.archdata.iommu;
234         pbm = pdev->dev.archdata.host_controller;
235         devhandle = pbm->devhandle;
236         entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
237
238         spin_lock_irqsave(&iommu->lock, flags);
239
240         pci_arena_free(&iommu->arena, entry, npages);
241
242         do {
243                 unsigned long num;
244
245                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
246                                             npages);
247                 entry += num;
248                 npages -= num;
249         } while (npages != 0);
250
251         spin_unlock_irqrestore(&iommu->lock, flags);
252
253         order = get_order(size);
254         if (order < 10)
255                 free_pages((unsigned long)cpu, order);
256 }
257
258 static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
259 {
260         struct iommu *iommu;
261         unsigned long flags, npages, oaddr;
262         unsigned long i, base_paddr;
263         u32 bus_addr, ret;
264         unsigned long prot;
265         long entry;
266
267         iommu = pdev->dev.archdata.iommu;
268
269         if (unlikely(direction == PCI_DMA_NONE))
270                 goto bad;
271
272         oaddr = (unsigned long)ptr;
273         npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
274         npages >>= IO_PAGE_SHIFT;
275
276         spin_lock_irqsave(&iommu->lock, flags);
277         entry = pci_arena_alloc(&iommu->arena, npages);
278         spin_unlock_irqrestore(&iommu->lock, flags);
279
280         if (unlikely(entry < 0L))
281                 goto bad;
282
283         bus_addr = (iommu->page_table_map_base +
284                     (entry << IO_PAGE_SHIFT));
285         ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
286         base_paddr = __pa(oaddr & IO_PAGE_MASK);
287         prot = HV_PCI_MAP_ATTR_READ;
288         if (direction != PCI_DMA_TODEVICE)
289                 prot |= HV_PCI_MAP_ATTR_WRITE;
290
291         local_irq_save(flags);
292
293         pci_iommu_batch_start(pdev, prot, entry);
294
295         for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
296                 long err = pci_iommu_batch_add(base_paddr);
297                 if (unlikely(err < 0L))
298                         goto iommu_map_fail;
299         }
300         if (unlikely(pci_iommu_batch_end() < 0L))
301                 goto iommu_map_fail;
302
303         local_irq_restore(flags);
304
305         return ret;
306
307 bad:
308         if (printk_ratelimit())
309                 WARN_ON(1);
310         return PCI_DMA_ERROR_CODE;
311
312 iommu_map_fail:
313         /* Interrupts are disabled.  */
314         spin_lock(&iommu->lock);
315         pci_arena_free(&iommu->arena, entry, npages);
316         spin_unlock_irqrestore(&iommu->lock, flags);
317
318         return PCI_DMA_ERROR_CODE;
319 }
320
321 static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
322 {
323         struct pci_pbm_info *pbm;
324         struct iommu *iommu;
325         unsigned long flags, npages;
326         long entry;
327         u32 devhandle;
328
329         if (unlikely(direction == PCI_DMA_NONE)) {
330                 if (printk_ratelimit())
331                         WARN_ON(1);
332                 return;
333         }
334
335         iommu = pdev->dev.archdata.iommu;
336         pbm = pdev->dev.archdata.host_controller;
337         devhandle = pbm->devhandle;
338
339         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
340         npages >>= IO_PAGE_SHIFT;
341         bus_addr &= IO_PAGE_MASK;
342
343         spin_lock_irqsave(&iommu->lock, flags);
344
345         entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
346         pci_arena_free(&iommu->arena, entry, npages);
347
348         do {
349                 unsigned long num;
350
351                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
352                                             npages);
353                 entry += num;
354                 npages -= num;
355         } while (npages != 0);
356
357         spin_unlock_irqrestore(&iommu->lock, flags);
358 }
359
360 #define SG_ENT_PHYS_ADDRESS(SG) \
361         (__pa(page_address((SG)->page)) + (SG)->offset)
362
363 static inline long fill_sg(long entry, struct pci_dev *pdev,
364                            struct scatterlist *sg,
365                            int nused, int nelems, unsigned long prot)
366 {
367         struct scatterlist *dma_sg = sg;
368         struct scatterlist *sg_end = sg + nelems;
369         unsigned long flags;
370         int i;
371
372         local_irq_save(flags);
373
374         pci_iommu_batch_start(pdev, prot, entry);
375
376         for (i = 0; i < nused; i++) {
377                 unsigned long pteval = ~0UL;
378                 u32 dma_npages;
379
380                 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
381                               dma_sg->dma_length +
382                               ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
383                 do {
384                         unsigned long offset;
385                         signed int len;
386
387                         /* If we are here, we know we have at least one
388                          * more page to map.  So walk forward until we
389                          * hit a page crossing, and begin creating new
390                          * mappings from that spot.
391                          */
392                         for (;;) {
393                                 unsigned long tmp;
394
395                                 tmp = SG_ENT_PHYS_ADDRESS(sg);
396                                 len = sg->length;
397                                 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
398                                         pteval = tmp & IO_PAGE_MASK;
399                                         offset = tmp & (IO_PAGE_SIZE - 1UL);
400                                         break;
401                                 }
402                                 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
403                                         pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
404                                         offset = 0UL;
405                                         len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
406                                         break;
407                                 }
408                                 sg++;
409                         }
410
411                         pteval = (pteval & IOPTE_PAGE);
412                         while (len > 0) {
413                                 long err;
414
415                                 err = pci_iommu_batch_add(pteval);
416                                 if (unlikely(err < 0L))
417                                         goto iommu_map_failed;
418
419                                 pteval += IO_PAGE_SIZE;
420                                 len -= (IO_PAGE_SIZE - offset);
421                                 offset = 0;
422                                 dma_npages--;
423                         }
424
425                         pteval = (pteval & IOPTE_PAGE) + len;
426                         sg++;
427
428                         /* Skip over any tail mappings we've fully mapped,
429                          * adjusting pteval along the way.  Stop when we
430                          * detect a page crossing event.
431                          */
432                         while (sg < sg_end &&
433                                (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
434                                (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
435                                ((pteval ^
436                                  (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
437                                 pteval += sg->length;
438                                 sg++;
439                         }
440                         if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
441                                 pteval = ~0UL;
442                 } while (dma_npages != 0);
443                 dma_sg++;
444         }
445
446         if (unlikely(pci_iommu_batch_end() < 0L))
447                 goto iommu_map_failed;
448
449         local_irq_restore(flags);
450         return 0;
451
452 iommu_map_failed:
453         local_irq_restore(flags);
454         return -1L;
455 }
456
457 static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
458 {
459         struct iommu *iommu;
460         unsigned long flags, npages, prot;
461         u32 dma_base;
462         struct scatterlist *sgtmp;
463         long entry, err;
464         int used;
465
466         /* Fast path single entry scatterlists. */
467         if (nelems == 1) {
468                 sglist->dma_address =
469                         pci_4v_map_single(pdev,
470                                           (page_address(sglist->page) + sglist->offset),
471                                           sglist->length, direction);
472                 if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
473                         return 0;
474                 sglist->dma_length = sglist->length;
475                 return 1;
476         }
477
478         iommu = pdev->dev.archdata.iommu;
479         
480         if (unlikely(direction == PCI_DMA_NONE))
481                 goto bad;
482
483         /* Step 1: Prepare scatter list. */
484         npages = prepare_sg(sglist, nelems);
485
486         /* Step 2: Allocate a cluster and context, if necessary. */
487         spin_lock_irqsave(&iommu->lock, flags);
488         entry = pci_arena_alloc(&iommu->arena, npages);
489         spin_unlock_irqrestore(&iommu->lock, flags);
490
491         if (unlikely(entry < 0L))
492                 goto bad;
493
494         dma_base = iommu->page_table_map_base +
495                 (entry << IO_PAGE_SHIFT);
496
497         /* Step 3: Normalize DMA addresses. */
498         used = nelems;
499
500         sgtmp = sglist;
501         while (used && sgtmp->dma_length) {
502                 sgtmp->dma_address += dma_base;
503                 sgtmp++;
504                 used--;
505         }
506         used = nelems - used;
507
508         /* Step 4: Create the mappings. */
509         prot = HV_PCI_MAP_ATTR_READ;
510         if (direction != PCI_DMA_TODEVICE)
511                 prot |= HV_PCI_MAP_ATTR_WRITE;
512
513         err = fill_sg(entry, pdev, sglist, used, nelems, prot);
514         if (unlikely(err < 0L))
515                 goto iommu_map_failed;
516
517         return used;
518
519 bad:
520         if (printk_ratelimit())
521                 WARN_ON(1);
522         return 0;
523
524 iommu_map_failed:
525         spin_lock_irqsave(&iommu->lock, flags);
526         pci_arena_free(&iommu->arena, entry, npages);
527         spin_unlock_irqrestore(&iommu->lock, flags);
528
529         return 0;
530 }
531
532 static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
533 {
534         struct pci_pbm_info *pbm;
535         struct iommu *iommu;
536         unsigned long flags, i, npages;
537         long entry;
538         u32 devhandle, bus_addr;
539
540         if (unlikely(direction == PCI_DMA_NONE)) {
541                 if (printk_ratelimit())
542                         WARN_ON(1);
543         }
544
545         iommu = pdev->dev.archdata.iommu;
546         pbm = pdev->dev.archdata.host_controller;
547         devhandle = pbm->devhandle;
548         
549         bus_addr = sglist->dma_address & IO_PAGE_MASK;
550
551         for (i = 1; i < nelems; i++)
552                 if (sglist[i].dma_length == 0)
553                         break;
554         i--;
555         npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
556                   bus_addr) >> IO_PAGE_SHIFT;
557
558         entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
559
560         spin_lock_irqsave(&iommu->lock, flags);
561
562         pci_arena_free(&iommu->arena, entry, npages);
563
564         do {
565                 unsigned long num;
566
567                 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
568                                             npages);
569                 entry += num;
570                 npages -= num;
571         } while (npages != 0);
572
573         spin_unlock_irqrestore(&iommu->lock, flags);
574 }
575
576 static void pci_4v_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
577 {
578         /* Nothing to do... */
579 }
580
581 static void pci_4v_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
582 {
583         /* Nothing to do... */
584 }
585
586 const struct pci_iommu_ops pci_sun4v_iommu_ops = {
587         .alloc_consistent               = pci_4v_alloc_consistent,
588         .free_consistent                = pci_4v_free_consistent,
589         .map_single                     = pci_4v_map_single,
590         .unmap_single                   = pci_4v_unmap_single,
591         .map_sg                         = pci_4v_map_sg,
592         .unmap_sg                       = pci_4v_unmap_sg,
593         .dma_sync_single_for_cpu        = pci_4v_dma_sync_single_for_cpu,
594         .dma_sync_sg_for_cpu            = pci_4v_dma_sync_sg_for_cpu,
595 };
596
597 static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func)
598 {
599         if (bus < pbm->pci_first_busno ||
600             bus > pbm->pci_last_busno)
601                 return 1;
602         return 0;
603 }
604
605 static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
606                                   int where, int size, u32 *value)
607 {
608         struct pci_pbm_info *pbm = bus_dev->sysdata;
609         u32 devhandle = pbm->devhandle;
610         unsigned int bus = bus_dev->number;
611         unsigned int device = PCI_SLOT(devfn);
612         unsigned int func = PCI_FUNC(devfn);
613         unsigned long ret;
614
615         if (bus_dev == pbm->pci_bus && devfn == 0x00)
616                 return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
617                                                     size, value);
618         if (pci_sun4v_out_of_range(pbm, bus, device, func)) {
619                 ret = ~0UL;
620         } else {
621                 ret = pci_sun4v_config_get(devhandle,
622                                 HV_PCI_DEVICE_BUILD(bus, device, func),
623                                 where, size);
624 #if 0
625                 printk("rcfg: [%x:%x:%x:%d]=[%lx]\n",
626                        devhandle, HV_PCI_DEVICE_BUILD(bus, device, func),
627                        where, size, ret);
628 #endif
629         }
630         switch (size) {
631         case 1:
632                 *value = ret & 0xff;
633                 break;
634         case 2:
635                 *value = ret & 0xffff;
636                 break;
637         case 4:
638                 *value = ret & 0xffffffff;
639                 break;
640         };
641
642
643         return PCIBIOS_SUCCESSFUL;
644 }
645
646 static int pci_sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
647                                    int where, int size, u32 value)
648 {
649         struct pci_pbm_info *pbm = bus_dev->sysdata;
650         u32 devhandle = pbm->devhandle;
651         unsigned int bus = bus_dev->number;
652         unsigned int device = PCI_SLOT(devfn);
653         unsigned int func = PCI_FUNC(devfn);
654         unsigned long ret;
655
656         if (bus_dev == pbm->pci_bus && devfn == 0x00)
657                 return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
658                                                      size, value);
659         if (pci_sun4v_out_of_range(pbm, bus, device, func)) {
660                 /* Do nothing. */
661         } else {
662                 ret = pci_sun4v_config_put(devhandle,
663                                 HV_PCI_DEVICE_BUILD(bus, device, func),
664                                 where, size, value);
665 #if 0
666                 printk("wcfg: [%x:%x:%x:%d] v[%x] == [%lx]\n",
667                        devhandle, HV_PCI_DEVICE_BUILD(bus, device, func),
668                        where, size, value, ret);
669 #endif
670         }
671         return PCIBIOS_SUCCESSFUL;
672 }
673
674 static struct pci_ops pci_sun4v_ops = {
675         .read =         pci_sun4v_read_pci_cfg,
676         .write =        pci_sun4v_write_pci_cfg,
677 };
678
679
680 static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm)
681 {
682         struct property *prop;
683         struct device_node *dp;
684
685         dp = pbm->prom_node;
686         prop = of_find_property(dp, "66mhz-capable", NULL);
687         pbm->is_66mhz_capable = (prop != NULL);
688         pbm->pci_bus = pci_scan_one_pbm(pbm);
689
690         /* XXX register error interrupt handlers XXX */
691 }
692
693 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
694                                             struct iommu *iommu)
695 {
696         struct iommu_arena *arena = &iommu->arena;
697         unsigned long i, cnt = 0;
698         u32 devhandle;
699
700         devhandle = pbm->devhandle;
701         for (i = 0; i < arena->limit; i++) {
702                 unsigned long ret, io_attrs, ra;
703
704                 ret = pci_sun4v_iommu_getmap(devhandle,
705                                              HV_PCI_TSBID(0, i),
706                                              &io_attrs, &ra);
707                 if (ret == HV_EOK) {
708                         if (page_in_phys_avail(ra)) {
709                                 pci_sun4v_iommu_demap(devhandle,
710                                                       HV_PCI_TSBID(0, i), 1);
711                         } else {
712                                 cnt++;
713                                 __set_bit(i, arena->map);
714                         }
715                 }
716         }
717
718         return cnt;
719 }
720
721 static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
722 {
723         struct iommu *iommu = pbm->iommu;
724         struct property *prop;
725         unsigned long num_tsb_entries, sz;
726         u32 vdma[2], dma_mask, dma_offset;
727         int tsbsize;
728
729         prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
730         if (prop) {
731                 u32 *val = prop->value;
732
733                 vdma[0] = val[0];
734                 vdma[1] = val[1];
735         } else {
736                 /* No property, use default values. */
737                 vdma[0] = 0x80000000;
738                 vdma[1] = 0x80000000;
739         }
740
741         dma_mask = vdma[0];
742         switch (vdma[1]) {
743                 case 0x20000000:
744                         dma_mask |= 0x1fffffff;
745                         tsbsize = 64;
746                         break;
747
748                 case 0x40000000:
749                         dma_mask |= 0x3fffffff;
750                         tsbsize = 128;
751                         break;
752
753                 case 0x80000000:
754                         dma_mask |= 0x7fffffff;
755                         tsbsize = 256;
756                         break;
757
758                 default:
759                         prom_printf("PCI-SUN4V: strange virtual-dma size.\n");
760                         prom_halt();
761         };
762
763         tsbsize *= (8 * 1024);
764
765         num_tsb_entries = tsbsize / sizeof(iopte_t);
766
767         dma_offset = vdma[0];
768
769         /* Setup initial software IOMMU state. */
770         spin_lock_init(&iommu->lock);
771         iommu->ctx_lowest_free = 1;
772         iommu->page_table_map_base = dma_offset;
773         iommu->dma_addr_mask = dma_mask;
774
775         /* Allocate and initialize the free area map.  */
776         sz = num_tsb_entries / 8;
777         sz = (sz + 7UL) & ~7UL;
778         iommu->arena.map = kzalloc(sz, GFP_KERNEL);
779         if (!iommu->arena.map) {
780                 prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
781                 prom_halt();
782         }
783         iommu->arena.limit = num_tsb_entries;
784
785         sz = probe_existing_entries(pbm, iommu);
786         if (sz)
787                 printk("%s: Imported %lu TSB entries from OBP\n",
788                        pbm->name, sz);
789 }
790
791 #ifdef CONFIG_PCI_MSI
792 struct pci_sun4v_msiq_entry {
793         u64             version_type;
794 #define MSIQ_VERSION_MASK               0xffffffff00000000UL
795 #define MSIQ_VERSION_SHIFT              32
796 #define MSIQ_TYPE_MASK                  0x00000000000000ffUL
797 #define MSIQ_TYPE_SHIFT                 0
798 #define MSIQ_TYPE_NONE                  0x00
799 #define MSIQ_TYPE_MSG                   0x01
800 #define MSIQ_TYPE_MSI32                 0x02
801 #define MSIQ_TYPE_MSI64                 0x03
802 #define MSIQ_TYPE_INTX                  0x08
803 #define MSIQ_TYPE_NONE2                 0xff
804
805         u64             intx_sysino;
806         u64             reserved1;
807         u64             stick;
808         u64             req_id;  /* bus/device/func */
809 #define MSIQ_REQID_BUS_MASK             0xff00UL
810 #define MSIQ_REQID_BUS_SHIFT            8
811 #define MSIQ_REQID_DEVICE_MASK          0x00f8UL
812 #define MSIQ_REQID_DEVICE_SHIFT         3
813 #define MSIQ_REQID_FUNC_MASK            0x0007UL
814 #define MSIQ_REQID_FUNC_SHIFT           0
815
816         u64             msi_address;
817
818         /* The format of this value is message type dependant.
819          * For MSI bits 15:0 are the data from the MSI packet.
820          * For MSI-X bits 31:0 are the data from the MSI packet.
821          * For MSG, the message code and message routing code where:
822          *      bits 39:32 is the bus/device/fn of the msg target-id
823          *      bits 18:16 is the message routing code
824          *      bits 7:0 is the message code
825          * For INTx the low order 2-bits are:
826          *      00 - INTA
827          *      01 - INTB
828          *      10 - INTC
829          *      11 - INTD
830          */
831         u64             msi_data;
832
833         u64             reserved2;
834 };
835
836 /* For now this just runs as a pre-handler for the real interrupt handler.
837  * So we just walk through the queue and ACK all the entries, update the
838  * head pointer, and return.
839  *
840  * In the longer term it would be nice to do something more integrated
841  * wherein we can pass in some of this MSI info to the drivers.  This
842  * would be most useful for PCIe fabric error messages, although we could
843  * invoke those directly from the loop here in order to pass the info around.
844  */
845 static void pci_sun4v_msi_prehandler(unsigned int ino, void *data1, void *data2)
846 {
847         struct pci_pbm_info *pbm = data1;
848         struct pci_sun4v_msiq_entry *base, *ep;
849         unsigned long msiqid, orig_head, head, type, err;
850
851         msiqid = (unsigned long) data2;
852
853         head = 0xdeadbeef;
854         err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, &head);
855         if (unlikely(err))
856                 goto hv_error_get;
857
858         if (unlikely(head >= (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry))))
859                 goto bad_offset;
860
861         head /= sizeof(struct pci_sun4v_msiq_entry);
862         orig_head = head;
863         base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
864                                    (pbm->msiq_ent_count *
865                                     sizeof(struct pci_sun4v_msiq_entry))));
866         ep = &base[head];
867         while ((ep->version_type & MSIQ_TYPE_MASK) != 0) {
868                 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
869                 if (unlikely(type != MSIQ_TYPE_MSI32 &&
870                              type != MSIQ_TYPE_MSI64))
871                         goto bad_type;
872
873                 pci_sun4v_msi_setstate(pbm->devhandle,
874                                        ep->msi_data /* msi_num */,
875                                        HV_MSISTATE_IDLE);
876
877                 /* Clear the entry.  */
878                 ep->version_type &= ~MSIQ_TYPE_MASK;
879
880                 /* Go to next entry in ring.  */
881                 head++;
882                 if (head >= pbm->msiq_ent_count)
883                         head = 0;
884                 ep = &base[head];
885         }
886
887         if (likely(head != orig_head)) {
888                 /* ACK entries by updating head pointer.  */
889                 head *= sizeof(struct pci_sun4v_msiq_entry);
890                 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
891                 if (unlikely(err))
892                         goto hv_error_set;
893         }
894         return;
895
896 hv_error_set:
897         printk(KERN_EMERG "MSI: Hypervisor set head gives error %lu\n", err);
898         goto hv_error_cont;
899
900 hv_error_get:
901         printk(KERN_EMERG "MSI: Hypervisor get head gives error %lu\n", err);
902
903 hv_error_cont:
904         printk(KERN_EMERG "MSI: devhandle[%x] msiqid[%lx] head[%lu]\n",
905                pbm->devhandle, msiqid, head);
906         return;
907
908 bad_offset:
909         printk(KERN_EMERG "MSI: Hypervisor gives bad offset %lx max(%lx)\n",
910                head, pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry));
911         return;
912
913 bad_type:
914         printk(KERN_EMERG "MSI: Entry has bad type %lx\n", type);
915         return;
916 }
917
918 static int msi_bitmap_alloc(struct pci_pbm_info *pbm)
919 {
920         unsigned long size, bits_per_ulong;
921
922         bits_per_ulong = sizeof(unsigned long) * 8;
923         size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1);
924         size /= 8;
925         BUG_ON(size % sizeof(unsigned long));
926
927         pbm->msi_bitmap = kzalloc(size, GFP_KERNEL);
928         if (!pbm->msi_bitmap)
929                 return -ENOMEM;
930
931         return 0;
932 }
933
934 static void msi_bitmap_free(struct pci_pbm_info *pbm)
935 {
936         kfree(pbm->msi_bitmap);
937         pbm->msi_bitmap = NULL;
938 }
939
940 static int msi_queue_alloc(struct pci_pbm_info *pbm)
941 {
942         unsigned long q_size, alloc_size, pages, order;
943         int i;
944
945         q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
946         alloc_size = (pbm->msiq_num * q_size);
947         order = get_order(alloc_size);
948         pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
949         if (pages == 0UL) {
950                 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
951                        order);
952                 return -ENOMEM;
953         }
954         memset((char *)pages, 0, PAGE_SIZE << order);
955         pbm->msi_queues = (void *) pages;
956
957         for (i = 0; i < pbm->msiq_num; i++) {
958                 unsigned long err, base = __pa(pages + (i * q_size));
959                 unsigned long ret1, ret2;
960
961                 err = pci_sun4v_msiq_conf(pbm->devhandle,
962                                           pbm->msiq_first + i,
963                                           base, pbm->msiq_ent_count);
964                 if (err) {
965                         printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
966                                err);
967                         goto h_error;
968                 }
969
970                 err = pci_sun4v_msiq_info(pbm->devhandle,
971                                           pbm->msiq_first + i,
972                                           &ret1, &ret2);
973                 if (err) {
974                         printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
975                                err);
976                         goto h_error;
977                 }
978                 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
979                         printk(KERN_ERR "MSI: Bogus qconf "
980                                "expected[%lx:%x] got[%lx:%lx]\n",
981                                base, pbm->msiq_ent_count,
982                                ret1, ret2);
983                         goto h_error;
984                 }
985         }
986
987         return 0;
988
989 h_error:
990         free_pages(pages, order);
991         return -EINVAL;
992 }
993
994 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
995 {
996         const u32 *val;
997         int len;
998
999         val = of_get_property(pbm->prom_node, "#msi-eqs", &len);
1000         if (!val || len != 4)
1001                 goto no_msi;
1002         pbm->msiq_num = *val;
1003         if (pbm->msiq_num) {
1004                 const struct msiq_prop {
1005                         u32 first_msiq;
1006                         u32 num_msiq;
1007                         u32 first_devino;
1008                 } *mqp;
1009                 const struct msi_range_prop {
1010                         u32 first_msi;
1011                         u32 num_msi;
1012                 } *mrng;
1013                 const struct addr_range_prop {
1014                         u32 msi32_high;
1015                         u32 msi32_low;
1016                         u32 msi32_len;
1017                         u32 msi64_high;
1018                         u32 msi64_low;
1019                         u32 msi64_len;
1020                 } *arng;
1021
1022                 val = of_get_property(pbm->prom_node, "msi-eq-size", &len);
1023                 if (!val || len != 4)
1024                         goto no_msi;
1025
1026                 pbm->msiq_ent_count = *val;
1027
1028                 mqp = of_get_property(pbm->prom_node,
1029                                       "msi-eq-to-devino", &len);
1030                 if (!mqp || len != sizeof(struct msiq_prop))
1031                         goto no_msi;
1032
1033                 pbm->msiq_first = mqp->first_msiq;
1034                 pbm->msiq_first_devino = mqp->first_devino;
1035
1036                 val = of_get_property(pbm->prom_node, "#msi", &len);
1037                 if (!val || len != 4)
1038                         goto no_msi;
1039                 pbm->msi_num = *val;
1040
1041                 mrng = of_get_property(pbm->prom_node, "msi-ranges", &len);
1042                 if (!mrng || len != sizeof(struct msi_range_prop))
1043                         goto no_msi;
1044                 pbm->msi_first = mrng->first_msi;
1045
1046                 val = of_get_property(pbm->prom_node, "msi-data-mask", &len);
1047                 if (!val || len != 4)
1048                         goto no_msi;
1049                 pbm->msi_data_mask = *val;
1050
1051                 val = of_get_property(pbm->prom_node, "msix-data-width", &len);
1052                 if (!val || len != 4)
1053                         goto no_msi;
1054                 pbm->msix_data_width = *val;
1055
1056                 arng = of_get_property(pbm->prom_node, "msi-address-ranges",
1057                                        &len);
1058                 if (!arng || len != sizeof(struct addr_range_prop))
1059                         goto no_msi;
1060                 pbm->msi32_start = ((u64)arng->msi32_high << 32) |
1061                         (u64) arng->msi32_low;
1062                 pbm->msi64_start = ((u64)arng->msi64_high << 32) |
1063                         (u64) arng->msi64_low;
1064                 pbm->msi32_len = arng->msi32_len;
1065                 pbm->msi64_len = arng->msi64_len;
1066
1067                 if (msi_bitmap_alloc(pbm))
1068                         goto no_msi;
1069
1070                 if (msi_queue_alloc(pbm)) {
1071                         msi_bitmap_free(pbm);
1072                         goto no_msi;
1073                 }
1074
1075                 printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] "
1076                        "devino[0x%x]\n",
1077                        pbm->name,
1078                        pbm->msiq_first, pbm->msiq_num,
1079                        pbm->msiq_ent_count,
1080                        pbm->msiq_first_devino);
1081                 printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] "
1082                        "width[%u]\n",
1083                        pbm->name,
1084                        pbm->msi_first, pbm->msi_num, pbm->msi_data_mask,
1085                        pbm->msix_data_width);
1086                 printk(KERN_INFO "%s: MSI addr32[0x%lx:0x%x] "
1087                        "addr64[0x%lx:0x%x]\n",
1088                        pbm->name,
1089                        pbm->msi32_start, pbm->msi32_len,
1090                        pbm->msi64_start, pbm->msi64_len);
1091                 printk(KERN_INFO "%s: MSI queues at RA [%p]\n",
1092                        pbm->name,
1093                        pbm->msi_queues);
1094         }
1095
1096         return;
1097
1098 no_msi:
1099         pbm->msiq_num = 0;
1100         printk(KERN_INFO "%s: No MSI support.\n", pbm->name);
1101 }
1102
1103 static int alloc_msi(struct pci_pbm_info *pbm)
1104 {
1105         int i;
1106
1107         for (i = 0; i < pbm->msi_num; i++) {
1108                 if (!test_and_set_bit(i, pbm->msi_bitmap))
1109                         return i + pbm->msi_first;
1110         }
1111
1112         return -ENOENT;
1113 }
1114
1115 static void free_msi(struct pci_pbm_info *pbm, int msi_num)
1116 {
1117         msi_num -= pbm->msi_first;
1118         clear_bit(msi_num, pbm->msi_bitmap);
1119 }
1120
1121 static int pci_sun4v_setup_msi_irq(unsigned int *virt_irq_p,
1122                                    struct pci_dev *pdev,
1123                                    struct msi_desc *entry)
1124 {
1125         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1126         unsigned long devino, msiqid;
1127         struct msi_msg msg;
1128         int msi_num, err;
1129
1130         *virt_irq_p = 0;
1131
1132         msi_num = alloc_msi(pbm);
1133         if (msi_num < 0)
1134                 return msi_num;
1135
1136         devino = sun4v_build_msi(pbm->devhandle, virt_irq_p,
1137                                  pbm->msiq_first_devino,
1138                                  (pbm->msiq_first_devino +
1139                                   pbm->msiq_num));
1140         err = -ENOMEM;
1141         if (!devino)
1142                 goto out_err;
1143
1144         msiqid = ((devino - pbm->msiq_first_devino) +
1145                   pbm->msiq_first);
1146
1147         err = -EINVAL;
1148         if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
1149         if (err)
1150                 goto out_err;
1151
1152         if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
1153                 goto out_err;
1154
1155         if (pci_sun4v_msi_setmsiq(pbm->devhandle,
1156                                   msi_num, msiqid,
1157                                   (entry->msi_attrib.is_64 ?
1158                                    HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
1159                 goto out_err;
1160
1161         if (pci_sun4v_msi_setstate(pbm->devhandle, msi_num, HV_MSISTATE_IDLE))
1162                 goto out_err;
1163
1164         if (pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_VALID))
1165                 goto out_err;
1166
1167         pdev->dev.archdata.msi_num = msi_num;
1168
1169         if (entry->msi_attrib.is_64) {
1170                 msg.address_hi = pbm->msi64_start >> 32;
1171                 msg.address_lo = pbm->msi64_start & 0xffffffff;
1172         } else {
1173                 msg.address_hi = 0;
1174                 msg.address_lo = pbm->msi32_start;
1175         }
1176         msg.data = msi_num;
1177
1178         set_irq_msi(*virt_irq_p, entry);
1179         write_msi_msg(*virt_irq_p, &msg);
1180
1181         irq_install_pre_handler(*virt_irq_p,
1182                                 pci_sun4v_msi_prehandler,
1183                                 pbm, (void *) msiqid);
1184
1185         return 0;
1186
1187 out_err:
1188         free_msi(pbm, msi_num);
1189         sun4v_destroy_msi(*virt_irq_p);
1190         *virt_irq_p = 0;
1191         return err;
1192
1193 }
1194
1195 static void pci_sun4v_teardown_msi_irq(unsigned int virt_irq,
1196                                        struct pci_dev *pdev)
1197 {
1198         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1199         unsigned long msiqid, err;
1200         unsigned int msi_num;
1201
1202         msi_num = pdev->dev.archdata.msi_num;
1203         err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi_num, &msiqid);
1204         if (err) {
1205                 printk(KERN_ERR "%s: getmsiq gives error %lu\n",
1206                        pbm->name, err);
1207                 return;
1208         }
1209
1210         pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_INVALID);
1211         pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_INVALID);
1212
1213         free_msi(pbm, msi_num);
1214
1215         /* The sun4v_destroy_msi() will liberate the devino and thus the MSIQ
1216          * allocation.
1217          */
1218         sun4v_destroy_msi(virt_irq);
1219 }
1220 #else /* CONFIG_PCI_MSI */
1221 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1222 {
1223 }
1224 #endif /* !(CONFIG_PCI_MSI) */
1225
1226 static void pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 devhandle)
1227 {
1228         struct pci_pbm_info *pbm;
1229
1230         if (devhandle & 0x40)
1231                 pbm = &p->pbm_B;
1232         else
1233                 pbm = &p->pbm_A;
1234
1235         pbm->next = pci_pbm_root;
1236         pci_pbm_root = pbm;
1237
1238         pbm->scan_bus = pci_sun4v_scan_bus;
1239         pbm->pci_ops = &pci_sun4v_ops;
1240
1241         pbm->parent = p;
1242         pbm->prom_node = dp;
1243
1244         pbm->devhandle = devhandle;
1245
1246         pbm->name = dp->full_name;
1247
1248         printk("%s: SUN4V PCI Bus Module\n", pbm->name);
1249
1250         pci_determine_mem_io_space(pbm);
1251
1252         pci_get_pbm_props(pbm);
1253         pci_sun4v_iommu_init(pbm);
1254         pci_sun4v_msi_init(pbm);
1255 }
1256
1257 void sun4v_pci_init(struct device_node *dp, char *model_name)
1258 {
1259         struct pci_controller_info *p;
1260         struct pci_pbm_info *pbm;
1261         struct iommu *iommu;
1262         struct property *prop;
1263         struct linux_prom64_registers *regs;
1264         u32 devhandle;
1265         int i;
1266
1267         prop = of_find_property(dp, "reg", NULL);
1268         regs = prop->value;
1269
1270         devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1271
1272         for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1273                 if (pbm->devhandle == (devhandle ^ 0x40)) {
1274                         pci_sun4v_pbm_init(pbm->parent, dp, devhandle);
1275                         return;
1276                 }
1277         }
1278
1279         for_each_possible_cpu(i) {
1280                 unsigned long page = get_zeroed_page(GFP_ATOMIC);
1281
1282                 if (!page)
1283                         goto fatal_memory_error;
1284
1285                 per_cpu(pci_iommu_batch, i).pglist = (u64 *) page;
1286         }
1287
1288         p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1289         if (!p)
1290                 goto fatal_memory_error;
1291
1292         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1293         if (!iommu)
1294                 goto fatal_memory_error;
1295
1296         p->pbm_A.iommu = iommu;
1297
1298         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1299         if (!iommu)
1300                 goto fatal_memory_error;
1301
1302         p->pbm_B.iommu = iommu;
1303
1304         p->index = pci_num_controllers++;
1305
1306 #ifdef CONFIG_PCI_MSI
1307         p->setup_msi_irq = pci_sun4v_setup_msi_irq;
1308         p->teardown_msi_irq = pci_sun4v_teardown_msi_irq;
1309 #endif
1310
1311         /* Like PSYCHO and SCHIZO we have a 2GB aligned area
1312          * for memory space.
1313          */
1314         pci_memspace_mask = 0x7fffffffUL;
1315
1316         pci_sun4v_pbm_init(p, dp, devhandle);
1317         return;
1318
1319 fatal_memory_error:
1320         prom_printf("SUN4V_PCI: Fatal memory allocation error.\n");
1321         prom_halt();
1322 }