arch/sparc/mm/init_64.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  arch/sparc64/mm/init.c
   4  *
   5  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   6  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   7  */
   8
   9 #include <linux/extable.h>
  10 #include <linux/kernel.h>
  11 #include <linux/sched.h>
  12 #include <linux/string.h>
  13 #include <linux/init.h>
  14 #include <linux/memblock.h>
  15 #include <linux/mm.h>
  16 #include <linux/hugetlb.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/poison.h>
  21 #include <linux/fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/kprobes.h>
  24 #include <linux/cache.h>
  25 #include <linux/sort.h>
  26 #include <linux/ioport.h>
  27 #include <linux/percpu.h>
  28 #include <linux/mmzone.h>
  29 #include <linux/gfp.h>
  30
  31 #include <asm/head.h>
  32 #include <asm/page.h>
  33 #include <asm/pgalloc.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/oplib.h>
  36 #include <asm/iommu.h>
  37 #include <asm/io.h>
  38 #include <linux/uaccess.h>
  39 #include <asm/mmu_context.h>
  40 #include <asm/tlbflush.h>
  41 #include <asm/dma.h>
  42 #include <asm/starfire.h>
  43 #include <asm/tlb.h>
  44 #include <asm/spitfire.h>
  45 #include <asm/sections.h>
  46 #include <asm/tsb.h>
  47 #include <asm/hypervisor.h>
  48 #include <asm/prom.h>
  49 #include <asm/mdesc.h>
  50 #include <asm/cpudata.h>
  51 #include <asm/setup.h>
  52 #include <asm/irq.h>
  53
  54 #include "init_64.h"
  55
  56 unsigned long kern_linear_pte_xor[4] __read_mostly;
  57 static unsigned long page_cache4v_flag;
  58
  59 /* A bitmap, two bits for every 256MB of physical memory.  These two
  60  * bits determine what page size we use for kernel linear
  61  * translations.  They form an index into kern_linear_pte_xor[].  The
  62  * value in the indexed slot is XOR'd with the TLB miss virtual
  63  * address to form the resulting TTE.  The mapping is:
  64  *
  65  *      0       ==>     4MB
  66  *      1       ==>     256MB
  67  *      2       ==>     2GB
  68  *      3       ==>     16GB
  69  *
  70  * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
  71  * support 2GB pages, and hopefully future cpus will support the 16GB
  72  * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
  73  * if these larger page sizes are not supported by the cpu.
  74  *
  75  * It would be nice to determine this from the machine description
  76  * 'cpu' properties, but we need to have this table setup before the
  77  * MDESC is initialized.
  78  */
  79
  80 #ifndef CONFIG_DEBUG_PAGEALLOC
  81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
  82  * Space is allocated for this right after the trap table in
  83  * arch/sparc64/kernel/head.S
  84  */
  85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  86 #endif
  87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
  88
  89 static unsigned long cpu_pgsz_mask;
  90
  91 #define MAX_BANKS       1024
  92
  93 static struct linux_prom64_registers pavail[MAX_BANKS];
  94 static int pavail_ents;
  95
  96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
  97
  98 static int cmp_p64(const void *a, const void *b)
  99 {
 100         const struct linux_prom64_registers *x = a, *y = b;
 101
 102         if (x->phys_addr > y->phys_addr)
 103                 return 1;
 104         if (x->phys_addr < y->phys_addr)
 105                 return -1;
 106         return 0;
 107 }
 108
 109 static void __init read_obp_memory(const char *property,
 110                                    struct linux_prom64_registers *regs,
 111                                    int *num_ents)
 112 {
 113         phandle node = prom_finddevice("/memory");
 114         int prop_size = prom_getproplen(node, property);
 115         int ents, ret, i;
 116
 117         ents = prop_size / sizeof(struct linux_prom64_registers);
 118         if (ents > MAX_BANKS) {
 119                 prom_printf("The machine has more %s property entries than "
 120                             "this kernel can support (%d).\n",
 121                             property, MAX_BANKS);
 122                 prom_halt();
 123         }
 124
 125         ret = prom_getproperty(node, property, (char *) regs, prop_size);
 126         if (ret == -1) {
 127                 prom_printf("Couldn't get %s property from /memory.\n",
 128                                 property);
 129                 prom_halt();
 130         }
 131
 132         /* Sanitize what we got from the firmware, by page aligning
 133          * everything.
 134          */
 135         for (i = 0; i < ents; i++) {
 136                 unsigned long base, size;
 137
 138                 base = regs[i].phys_addr;
 139                 size = regs[i].reg_size;
 140
 141                 size &= PAGE_MASK;
 142                 if (base & ~PAGE_MASK) {
 143                         unsigned long new_base = PAGE_ALIGN(base);
 144
 145                         size -= new_base - base;
 146                         if ((long) size < 0L)
 147                                 size = 0UL;
 148                         base = new_base;
 149                 }
 150                 if (size == 0UL) {
 151                         /* If it is empty, simply get rid of it.
 152                          * This simplifies the logic of the other
 153                          * functions that process these arrays.
 154                          */
 155                         memmove(&regs[i], &regs[i + 1],
 156                                 (ents - i - 1) * sizeof(regs[0]));
 157                         i--;
 158                         ents--;
 159                         continue;
 160                 }
 161                 regs[i].phys_addr = base;
 162                 regs[i].reg_size = size;
 163         }
 164
 165         *num_ents = ents;
 166
 167         sort(regs, ents, sizeof(struct linux_prom64_registers),
 168              cmp_p64, NULL);
 169 }
 170
 171 /* Kernel physical address base and size in bytes.  */
 172 unsigned long kern_base __read_mostly;
 173 unsigned long kern_size __read_mostly;
 174
 175 /* Initial ramdisk setup */
 176 extern unsigned long sparc_ramdisk_image64;
 177 extern unsigned int sparc_ramdisk_image;
 178 extern unsigned int sparc_ramdisk_size;
 179
 180 struct page *mem_map_zero __read_mostly;
 181 EXPORT_SYMBOL(mem_map_zero);
 182
 183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 184
 185 unsigned long sparc64_kern_pri_context __read_mostly;
 186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 187 unsigned long sparc64_kern_sec_context __read_mostly;
 188
 189 int num_kernel_image_mappings;
 190
 191 #ifdef CONFIG_DEBUG_DCFLUSH
 192 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 193 #ifdef CONFIG_SMP
 194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 195 #endif
 196 #endif
 197
 198 inline void flush_dcache_page_impl(struct page *page)
 199 {
 200         BUG_ON(tlb_type == hypervisor);
 201 #ifdef CONFIG_DEBUG_DCFLUSH
 202         atomic_inc(&dcpage_flushes);
 203 #endif
 204
 205 #ifdef DCACHE_ALIASING_POSSIBLE
 206         __flush_dcache_page(page_address(page),
 207                             ((tlb_type == spitfire) &&
 208                              page_mapping_file(page) != NULL));
 209 #else
 210         if (page_mapping_file(page) != NULL &&
 211             tlb_type == spitfire)
 212                 __flush_icache_page(__pa(page_address(page)));
 213 #endif
 214 }
 215
 216 #define PG_dcache_dirty         PG_arch_1
 217 #define PG_dcache_cpu_shift     32UL
 218 #define PG_dcache_cpu_mask      \
 219         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
 220
 221 #define dcache_dirty_cpu(page) \
 222         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 223
 224 static inline void set_dcache_dirty(struct page *page, int this_cpu)
 225 {
 226         unsigned long mask = this_cpu;
 227         unsigned long non_cpu_bits;
 228
 229         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 230         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 231
 232         __asm__ __volatile__("1:\n\t"
 233                              "ldx       [%2], %%g7\n\t"
 234                              "and       %%g7, %1, %%g1\n\t"
 235                              "or        %%g1, %0, %%g1\n\t"
 236                              "casx      [%2], %%g7, %%g1\n\t"
 237                              "cmp       %%g7, %%g1\n\t"
 238                              "bne,pn    %%xcc, 1b\n\t"
 239                              " nop"
 240                              : /* no outputs */
 241                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 242                              : "g1", "g7");
 243 }
 244
 245 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 246 {
 247         unsigned long mask = (1UL << PG_dcache_dirty);
 248
 249         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 250                              "1:\n\t"
 251                              "ldx       [%2], %%g7\n\t"
 252                              "srlx      %%g7, %4, %%g1\n\t"
 253                              "and       %%g1, %3, %%g1\n\t"
 254                              "cmp       %%g1, %0\n\t"
 255                              "bne,pn    %%icc, 2f\n\t"
 256                              " andn     %%g7, %1, %%g1\n\t"
 257                              "casx      [%2], %%g7, %%g1\n\t"
 258                              "cmp       %%g7, %%g1\n\t"
 259                              "bne,pn    %%xcc, 1b\n\t"
 260                              " nop\n"
 261                              "2:"
 262                              : /* no outputs */
 263                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 264                                "i" (PG_dcache_cpu_mask),
 265                                "i" (PG_dcache_cpu_shift)
 266                              : "g1", "g7");
 267 }
 268
 269 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 270 {
 271         unsigned long tsb_addr = (unsigned long) ent;
 272
 273         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
 274                 tsb_addr = __pa(tsb_addr);
 275
 276         __tsb_insert(tsb_addr, tag, pte);
 277 }
 278
 279 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
 280
 281 static void flush_dcache(unsigned long pfn)
 282 {
 283         struct page *page;
 284
 285         page = pfn_to_page(pfn);
 286         if (page) {
 287                 unsigned long pg_flags;
 288
 289                 pg_flags = page->flags;
 290                 if (pg_flags & (1UL << PG_dcache_dirty)) {
 291                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 292                                    PG_dcache_cpu_mask);
 293                         int this_cpu = get_cpu();
 294
 295                         /* This is just to optimize away some function calls
 296                          * in the SMP case.
 297                          */
 298                         if (cpu == this_cpu)
 299                                 flush_dcache_page_impl(page);
 300                         else
 301                                 smp_flush_dcache_page_impl(page, cpu);
 302
 303                         clear_dcache_dirty_cpu(page, cpu);
 304
 305                         put_cpu();
 306                 }
 307         }
 308 }
 309
 310 /* mm->context.lock must be held */
 311 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
 312                                     unsigned long tsb_hash_shift, unsigned long address,
 313                                     unsigned long tte)
 314 {
 315         struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
 316         unsigned long tag;
 317
 318         if (unlikely(!tsb))
 319                 return;
 320
 321         tsb += ((address >> tsb_hash_shift) &
 322                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
 323         tag = (address >> 22UL);
 324         tsb_insert(tsb, tag, tte);
 325 }
 326
 327 #ifdef CONFIG_HUGETLB_PAGE
 328 static void __init add_huge_page_size(unsigned long size)
 329 {
 330         unsigned int order;
 331
 332         if (size_to_hstate(size))
 333                 return;
 334
 335         order = ilog2(size) - PAGE_SHIFT;
 336         hugetlb_add_hstate(order);
 337 }
 338
 339 static int __init hugetlbpage_init(void)
 340 {
 341         add_huge_page_size(1UL << HPAGE_64K_SHIFT);
 342         add_huge_page_size(1UL << HPAGE_SHIFT);
 343         add_huge_page_size(1UL << HPAGE_256MB_SHIFT);
 344         add_huge_page_size(1UL << HPAGE_2GB_SHIFT);
 345
 346         return 0;
 347 }
 348
 349 arch_initcall(hugetlbpage_init);
 350
 351 static void __init pud_huge_patch(void)
 352 {
 353         struct pud_huge_patch_entry *p;
 354         unsigned long addr;
 355
 356         p = &__pud_huge_patch;
 357         addr = p->addr;
 358         *(unsigned int *)addr = p->insn;
 359
 360         __asm__ __volatile__("flush %0" : : "r" (addr));
 361 }
 362
 363 static int __init setup_hugepagesz(char *string)
 364 {
 365         unsigned long long hugepage_size;
 366         unsigned int hugepage_shift;
 367         unsigned short hv_pgsz_idx;
 368         unsigned int hv_pgsz_mask;
 369         int rc = 0;
 370
 371         hugepage_size = memparse(string, &string);
 372         hugepage_shift = ilog2(hugepage_size);
 373
 374         switch (hugepage_shift) {
 375         case HPAGE_16GB_SHIFT:
 376                 hv_pgsz_mask = HV_PGSZ_MASK_16GB;
 377                 hv_pgsz_idx = HV_PGSZ_IDX_16GB;
 378                 pud_huge_patch();
 379                 break;
 380         case HPAGE_2GB_SHIFT:
 381                 hv_pgsz_mask = HV_PGSZ_MASK_2GB;
 382                 hv_pgsz_idx = HV_PGSZ_IDX_2GB;
 383                 break;
 384         case HPAGE_256MB_SHIFT:
 385                 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
 386                 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
 387                 break;
 388         case HPAGE_SHIFT:
 389                 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
 390                 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
 391                 break;
 392         case HPAGE_64K_SHIFT:
 393                 hv_pgsz_mask = HV_PGSZ_MASK_64K;
 394                 hv_pgsz_idx = HV_PGSZ_IDX_64K;
 395                 break;
 396         default:
 397                 hv_pgsz_mask = 0;
 398         }
 399
 400         if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) {
 401                 hugetlb_bad_size();
 402                 pr_err("hugepagesz=%llu not supported by MMU.\n",
 403                         hugepage_size);
 404                 goto out;
 405         }
 406
 407         add_huge_page_size(hugepage_size);
 408         rc = 1;
 409
 410 out:
 411         return rc;
 412 }
 413 __setup("hugepagesz=", setup_hugepagesz);
 414 #endif  /* CONFIG_HUGETLB_PAGE */
 415
 416 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 417 {
 418         struct mm_struct *mm;
 419         unsigned long flags;
 420         bool is_huge_tsb;
 421         pte_t pte = *ptep;
 422
 423         if (tlb_type != hypervisor) {
 424                 unsigned long pfn = pte_pfn(pte);
 425
 426                 if (pfn_valid(pfn))
 427                         flush_dcache(pfn);
 428         }
 429
 430         mm = vma->vm_mm;
 431
 432         /* Don't insert a non-valid PTE into the TSB, we'll deadlock.  */
 433         if (!pte_accessible(mm, pte))
 434                 return;
 435
 436         spin_lock_irqsave(&mm->context.lock, flags);
 437
 438         is_huge_tsb = false;
 439 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 440         if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
 441                 unsigned long hugepage_size = PAGE_SIZE;
 442
 443                 if (is_vm_hugetlb_page(vma))
 444                         hugepage_size = huge_page_size(hstate_vma(vma));
 445
 446                 if (hugepage_size >= PUD_SIZE) {
 447                         unsigned long mask = 0x1ffc00000UL;
 448
 449                         /* Transfer bits [32:22] from address to resolve
 450                          * at 4M granularity.
 451                          */
 452                         pte_val(pte) &= ~mask;
 453                         pte_val(pte) |= (address & mask);
 454                 } else if (hugepage_size >= PMD_SIZE) {
 455                         /* We are fabricating 8MB pages using 4MB
 456                          * real hw pages.
 457                          */
 458                         pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
 459                 }
 460
 461                 if (hugepage_size >= PMD_SIZE) {
 462                         __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
 463                                 REAL_HPAGE_SHIFT, address, pte_val(pte));
 464                         is_huge_tsb = true;
 465                 }
 466         }
 467 #endif
 468         if (!is_huge_tsb)
 469                 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
 470                                         address, pte_val(pte));
 471
 472         spin_unlock_irqrestore(&mm->context.lock, flags);
 473 }
 474
 475 void flush_dcache_page(struct page *page)
 476 {
 477         struct address_space *mapping;
 478         int this_cpu;
 479
 480         if (tlb_type == hypervisor)
 481                 return;
 482
 483         /* Do not bother with the expensive D-cache flush if it
 484          * is merely the zero page.  The 'bigcore' testcase in GDB
 485          * causes this case to run millions of times.
 486          */
 487         if (page == ZERO_PAGE(0))
 488                 return;
 489
 490         this_cpu = get_cpu();
 491
 492         mapping = page_mapping_file(page);
 493         if (mapping && !mapping_mapped(mapping)) {
 494                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 495                 if (dirty) {
 496                         int dirty_cpu = dcache_dirty_cpu(page);
 497
 498                         if (dirty_cpu == this_cpu)
 499                                 goto out;
 500                         smp_flush_dcache_page_impl(page, dirty_cpu);
 501                 }
 502                 set_dcache_dirty(page, this_cpu);
 503         } else {
 504                 /* We could delay the flush for the !page_mapping
 505                  * case too.  But that case is for exec env/arg
 506                  * pages and those are %99 certainly going to get
 507                  * faulted into the tlb (and thus flushed) anyways.
 508                  */
 509                 flush_dcache_page_impl(page);
 510         }
 511
 512 out:
 513         put_cpu();
 514 }
 515 EXPORT_SYMBOL(flush_dcache_page);
 516
 517 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 518 {
 519         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 520         if (tlb_type == spitfire) {
 521                 unsigned long kaddr;
 522
 523                 /* This code only runs on Spitfire cpus so this is
 524                  * why we can assume _PAGE_PADDR_4U.
 525                  */
 526                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
 527                         unsigned long paddr, mask = _PAGE_PADDR_4U;
 528
 529                         if (kaddr >= PAGE_OFFSET)
 530                                 paddr = kaddr & mask;
 531                         else {
 532                                 pgd_t *pgdp = pgd_offset_k(kaddr);
 533                                 pud_t *pudp = pud_offset(pgdp, kaddr);
 534                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
 535                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
 536
 537                                 paddr = pte_val(*ptep) & mask;
 538                         }
 539                         __flush_icache_page(paddr);
 540                 }
 541         }
 542 }
 543 EXPORT_SYMBOL(flush_icache_range);
 544
 545 void mmu_info(struct seq_file *m)
 546 {
 547         static const char *pgsz_strings[] = {
 548                 "8K", "64K", "512K", "4MB", "32MB",
 549                 "256MB", "2GB", "16GB",
 550         };
 551         int i, printed;
 552
 553         if (tlb_type == cheetah)
 554                 seq_printf(m, "MMU Type\t: Cheetah\n");
 555         else if (tlb_type == cheetah_plus)
 556                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 557         else if (tlb_type == spitfire)
 558                 seq_printf(m, "MMU Type\t: Spitfire\n");
 559         else if (tlb_type == hypervisor)
 560                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 561         else
 562                 seq_printf(m, "MMU Type\t: ???\n");
 563
 564         seq_printf(m, "MMU PGSZs\t: ");
 565         printed = 0;
 566         for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
 567                 if (cpu_pgsz_mask & (1UL << i)) {
 568                         seq_printf(m, "%s%s",
 569                                    printed ? "," : "", pgsz_strings[i]);
 570                         printed++;
 571                 }
 572         }
 573         seq_putc(m, '\n');
 574
 575 #ifdef CONFIG_DEBUG_DCFLUSH
 576         seq_printf(m, "DCPageFlushes\t: %d\n",
 577                    atomic_read(&dcpage_flushes));
 578 #ifdef CONFIG_SMP
 579         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 580                    atomic_read(&dcpage_flushes_xcall));
 581 #endif /* CONFIG_SMP */
 582 #endif /* CONFIG_DEBUG_DCFLUSH */
 583 }
 584
 585 struct linux_prom_translation prom_trans[512] __read_mostly;
 586 unsigned int prom_trans_ents __read_mostly;
 587
 588 unsigned long kern_locked_tte_data;
 589
 590 /* The obp translations are saved based on 8k pagesize, since obp can
 591  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 592  * HI_OBP_ADDRESS range are handled in ktlb.S.
 593  */
 594 static inline int in_obp_range(unsigned long vaddr)
 595 {
 596         return (vaddr >= LOW_OBP_ADDRESS &&
 597                 vaddr < HI_OBP_ADDRESS);
 598 }
 599
 600 static int cmp_ptrans(const void *a, const void *b)
 601 {
 602         const struct linux_prom_translation *x = a, *y = b;
 603
 604         if (x->virt > y->virt)
 605                 return 1;
 606         if (x->virt < y->virt)
 607                 return -1;
 608         return 0;
 609 }
 610
 611 /* Read OBP translations property into 'prom_trans[]'.  */
 612 static void __init read_obp_translations(void)
 613 {
 614         int n, node, ents, first, last, i;
 615
 616         node = prom_finddevice("/virtual-memory");
 617         n = prom_getproplen(node, "translations");
 618         if (unlikely(n == 0 || n == -1)) {
 619                 prom_printf("prom_mappings: Couldn't get size.\n");
 620                 prom_halt();
 621         }
 622         if (unlikely(n > sizeof(prom_trans))) {
 623                 prom_printf("prom_mappings: Size %d is too big.\n", n);
 624                 prom_halt();
 625         }
 626
 627         if ((n = prom_getproperty(node, "translations",
 628                                   (char *)&prom_trans[0],
 629                                   sizeof(prom_trans))) == -1) {
 630                 prom_printf("prom_mappings: Couldn't get property.\n");
 631                 prom_halt();
 632         }
 633
 634         n = n / sizeof(struct linux_prom_translation);
 635
 636         ents = n;
 637
 638         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 639              cmp_ptrans, NULL);
 640
 641         /* Now kick out all the non-OBP entries.  */
 642         for (i = 0; i < ents; i++) {
 643                 if (in_obp_range(prom_trans[i].virt))
 644                         break;
 645         }
 646         first = i;
 647         for (; i < ents; i++) {
 648                 if (!in_obp_range(prom_trans[i].virt))
 649                         break;
 650         }
 651         last = i;
 652
 653         for (i = 0; i < (last - first); i++) {
 654                 struct linux_prom_translation *src = &prom_trans[i + first];
 655                 struct linux_prom_translation *dest = &prom_trans[i];
 656
 657                 *dest = *src;
 658         }
 659         for (; i < ents; i++) {
 660                 struct linux_prom_translation *dest = &prom_trans[i];
 661                 dest->virt = dest->size = dest->data = 0x0UL;
 662         }
 663
 664         prom_trans_ents = last - first;
 665
 666         if (tlb_type == spitfire) {
 667                 /* Clear diag TTE bits. */
 668                 for (i = 0; i < prom_trans_ents; i++)
 669                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 670         }
 671
 672         /* Force execute bit on.  */
 673         for (i = 0; i < prom_trans_ents; i++)
 674                 prom_trans[i].data |= (tlb_type == hypervisor ?
 675                                        _PAGE_EXEC_4V : _PAGE_EXEC_4U);
 676 }
 677
 678 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 679                                        unsigned long pte,
 680                                        unsigned long mmu)
 681 {
 682         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
 683
 684         if (ret != 0) {
 685                 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
 686                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
 687                 prom_halt();
 688         }
 689 }
 690
 691 static unsigned long kern_large_tte(unsigned long paddr);
 692
 693 static void __init remap_kernel(void)
 694 {
 695         unsigned long phys_page, tte_vaddr, tte_data;
 696         int i, tlb_ent = sparc64_highest_locked_tlbent();
 697
 698         tte_vaddr = (unsigned long) KERNBASE;
 699         phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
 700         tte_data = kern_large_tte(phys_page);
 701
 702         kern_locked_tte_data = tte_data;
 703
 704         /* Now lock us into the TLBs via Hypervisor or OBP. */
 705         if (tlb_type == hypervisor) {
 706                 for (i = 0; i < num_kernel_image_mappings; i++) {
 707                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 708                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 709                         tte_vaddr += 0x400000;
 710                         tte_data += 0x400000;
 711                 }
 712         } else {
 713                 for (i = 0; i < num_kernel_image_mappings; i++) {
 714                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
 715                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
 716                         tte_vaddr += 0x400000;
 717                         tte_data += 0x400000;
 718                 }
 719                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
 720         }
 721         if (tlb_type == cheetah_plus) {
 722                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 723                                             CTX_CHEETAH_PLUS_NUC);
 724                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 725                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 726         }
 727 }
 728
 729
 730 static void __init inherit_prom_mappings(void)
 731 {
 732         /* Now fixup OBP's idea about where we really are mapped. */
 733         printk("Remapping the kernel... ");
 734         remap_kernel();
 735         printk("done.\n");
 736 }
 737
 738 void prom_world(int enter)
 739 {
 740         if (!enter)
 741                 set_fs(get_fs());
 742
 743         __asm__ __volatile__("flushw");
 744 }
 745
 746 void __flush_dcache_range(unsigned long start, unsigned long end)
 747 {
 748         unsigned long va;
 749
 750         if (tlb_type == spitfire) {
 751                 int n = 0;
 752
 753                 for (va = start; va < end; va += 32) {
 754                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 755                         if (++n >= 512)
 756                                 break;
 757                 }
 758         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 759                 start = __pa(start);
 760                 end = __pa(end);
 761                 for (va = start; va < end; va += 32)
 762                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 763                                              "membar #Sync"
 764                                              : /* no outputs */
 765                                              : "r" (va),
 766                                                "i" (ASI_DCACHE_INVALIDATE));
 767         }
 768 }
 769 EXPORT_SYMBOL(__flush_dcache_range);
 770
 771 /* get_new_mmu_context() uses "cache + 1".  */
 772 DEFINE_SPINLOCK(ctx_alloc_lock);
 773 unsigned long tlb_context_cache = CTX_FIRST_VERSION;
 774 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
 775 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
 776 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
 777 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
 778
 779 static void mmu_context_wrap(void)
 780 {
 781         unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
 782         unsigned long new_ver, new_ctx, old_ctx;
 783         struct mm_struct *mm;
 784         int cpu;
 785
 786         bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
 787
 788         /* Reserve kernel context */
 789         set_bit(0, mmu_context_bmap);
 790
 791         new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
 792         if (unlikely(new_ver == 0))
 793                 new_ver = CTX_FIRST_VERSION;
 794         tlb_context_cache = new_ver;
 795
 796         /*
 797          * Make sure that any new mm that are added into per_cpu_secondary_mm,
 798          * are going to go through get_new_mmu_context() path.
 799          */
 800         mb();
 801
 802         /*
 803          * Updated versions to current on those CPUs that had valid secondary
 804          * contexts
 805          */
 806         for_each_online_cpu(cpu) {
 807                 /*
 808                  * If a new mm is stored after we took this mm from the array,
 809                  * it will go into get_new_mmu_context() path, because we
 810                  * already bumped the version in tlb_context_cache.
 811                  */
 812                 mm = per_cpu(per_cpu_secondary_mm, cpu);
 813
 814                 if (unlikely(!mm || mm == &init_mm))
 815                         continue;
 816
 817                 old_ctx = mm->context.sparc64_ctx_val;
 818                 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
 819                         new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
 820                         set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
 821                         mm->context.sparc64_ctx_val = new_ctx;
 822                 }
 823         }
 824 }
 825
 826 /* Caller does TLB context flushing on local CPU if necessary.
 827  * The caller also ensures that CTX_VALID(mm->context) is false.
 828  *
 829  * We must be careful about boundary cases so that we never
 830  * let the user have CTX 0 (nucleus) or we ever use a CTX
 831  * version of zero (and thus NO_CONTEXT would not be caught
 832  * by version mis-match tests in mmu_context.h).
 833  *
 834  * Always invoked with interrupts disabled.
 835  */
 836 void get_new_mmu_context(struct mm_struct *mm)
 837 {
 838         unsigned long ctx, new_ctx;
 839         unsigned long orig_pgsz_bits;
 840
 841         spin_lock(&ctx_alloc_lock);
 842 retry:
 843         /* wrap might have happened, test again if our context became valid */
 844         if (unlikely(CTX_VALID(mm->context)))
 845                 goto out;
 846         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 847         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 848         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 849         if (new_ctx >= (1 << CTX_NR_BITS)) {
 850                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 851                 if (new_ctx >= ctx) {
 852                         mmu_context_wrap();
 853                         goto retry;
 854                 }
 855         }
 856         if (mm->context.sparc64_ctx_val)
 857                 cpumask_clear(mm_cpumask(mm));
 858         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 859         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 860         tlb_context_cache = new_ctx;
 861         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 862 out:
 863         spin_unlock(&ctx_alloc_lock);
 864 }
 865
 866 static int numa_enabled = 1;
 867 static int numa_debug;
 868
 869 static int __init early_numa(char *p)
 870 {
 871         if (!p)
 872                 return 0;
 873
 874         if (strstr(p, "off"))
 875                 numa_enabled = 0;
 876
 877         if (strstr(p, "debug"))
 878                 numa_debug = 1;
 879
 880         return 0;
 881 }
 882 early_param("numa", early_numa);
 883
 884 #define numadbg(f, a...) \
 885 do {    if (numa_debug) \
 886                 printk(KERN_INFO f, ## a); \
 887 } while (0)
 888
 889 static void __init find_ramdisk(unsigned long phys_base)
 890 {
 891 #ifdef CONFIG_BLK_DEV_INITRD
 892         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 893                 unsigned long ramdisk_image;
 894
 895                 /* Older versions of the bootloader only supported a
 896                  * 32-bit physical address for the ramdisk image
 897                  * location, stored at sparc_ramdisk_image.  Newer
 898                  * SILO versions set sparc_ramdisk_image to zero and
 899                  * provide a full 64-bit physical address at
 900                  * sparc_ramdisk_image64.
 901                  */
 902                 ramdisk_image = sparc_ramdisk_image;
 903                 if (!ramdisk_image)
 904                         ramdisk_image = sparc_ramdisk_image64;
 905
 906                 /* Another bootloader quirk.  The bootloader normalizes
 907                  * the physical address to KERNBASE, so we have to
 908                  * factor that back out and add in the lowest valid
 909                  * physical page address to get the true physical address.
 910                  */
 911                 ramdisk_image -= KERNBASE;
 912                 ramdisk_image += phys_base;
 913
 914                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
 915                         ramdisk_image, sparc_ramdisk_size);
 916
 917                 initrd_start = ramdisk_image;
 918                 initrd_end = ramdisk_image + sparc_ramdisk_size;
 919
 920                 memblock_reserve(initrd_start, sparc_ramdisk_size);
 921
 922                 initrd_start += PAGE_OFFSET;
 923                 initrd_end += PAGE_OFFSET;
 924         }
 925 #endif
 926 }
 927
 928 struct node_mem_mask {
 929         unsigned long mask;
 930         unsigned long match;
 931 };
 932 static struct node_mem_mask node_masks[MAX_NUMNODES];
 933 static int num_node_masks;
 934
 935 #ifdef CONFIG_NEED_MULTIPLE_NODES
 936
 937 struct mdesc_mlgroup {
 938         u64     node;
 939         u64     latency;
 940         u64     match;
 941         u64     mask;
 942 };
 943
 944 static struct mdesc_mlgroup *mlgroups;
 945 static int num_mlgroups;
 946
 947 int numa_cpu_lookup_table[NR_CPUS];
 948 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
 949
 950 struct mdesc_mblock {
 951         u64     base;
 952         u64     size;
 953         u64     offset; /* RA-to-PA */
 954 };
 955 static struct mdesc_mblock *mblocks;
 956 static int num_mblocks;
 957
 958 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
 959 {
 960         struct mdesc_mblock *m = NULL;
 961         int i;
 962
 963         for (i = 0; i < num_mblocks; i++) {
 964                 m = &mblocks[i];
 965
 966                 if (addr >= m->base &&
 967                     addr < (m->base + m->size)) {
 968                         break;
 969                 }
 970         }
 971
 972         return m;
 973 }
 974
 975 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
 976 {
 977         int prev_nid, new_nid;
 978
 979         prev_nid = NUMA_NO_NODE;
 980         for ( ; start < end; start += PAGE_SIZE) {
 981                 for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
 982                         struct node_mem_mask *p = &node_masks[new_nid];
 983
 984                         if ((start & p->mask) == p->match) {
 985                                 if (prev_nid == NUMA_NO_NODE)
 986                                         prev_nid = new_nid;
 987                                 break;
 988                         }
 989                 }
 990
 991                 if (new_nid == num_node_masks) {
 992                         prev_nid = 0;
 993                         WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
 994                                   start);
 995                         break;
 996                 }
 997
 998                 if (prev_nid != new_nid)
 999                         break;
1000         }
1001         *nid = prev_nid;
1002
1003         return start > end ? end : start;
1004 }
1005
1006 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
1007 {
1008         u64 ret_end, pa_start, m_mask, m_match, m_end;
1009         struct mdesc_mblock *mblock;
1010         int _nid, i;
1011
1012         if (tlb_type != hypervisor)
1013                 return memblock_nid_range_sun4u(start, end, nid);
1014
1015         mblock = addr_to_mblock(start);
1016         if (!mblock) {
1017                 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
1018                           start);
1019
1020                 _nid = 0;
1021                 ret_end = end;
1022                 goto done;
1023         }
1024
1025         pa_start = start + mblock->offset;
1026         m_match = 0;
1027         m_mask = 0;
1028
1029         for (_nid = 0; _nid < num_node_masks; _nid++) {
1030                 struct node_mem_mask *const m = &node_masks[_nid];
1031
1032                 if ((pa_start & m->mask) == m->match) {
1033                         m_match = m->match;
1034                         m_mask = m->mask;
1035                         break;
1036                 }
1037         }
1038
1039         if (num_node_masks == _nid) {
1040                 /* We could not find NUMA group, so default to 0, but lets
1041                  * search for latency group, so we could calculate the correct
1042                  * end address that we return
1043                  */
1044                 _nid = 0;
1045
1046                 for (i = 0; i < num_mlgroups; i++) {
1047                         struct mdesc_mlgroup *const m = &mlgroups[i];
1048
1049                         if ((pa_start & m->mask) == m->match) {
1050                                 m_match = m->match;
1051                                 m_mask = m->mask;
1052                                 break;
1053                         }
1054                 }
1055
1056                 if (i == num_mlgroups) {
1057                         WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
1058                                   start);
1059
1060                         ret_end = end;
1061                         goto done;
1062                 }
1063         }
1064
1065         /*
1066          * Each latency group has match and mask, and each memory block has an
1067          * offset.  An address belongs to a latency group if its address matches
1068          * the following formula: ((addr + offset) & mask) == match
1069          * It is, however, slow to check every single page if it matches a
1070          * particular latency group. As optimization we calculate end value by
1071          * using bit arithmetics.
1072          */
1073         m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
1074         m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
1075         ret_end = m_end > end ? end : m_end;
1076
1077 done:
1078         *nid = _nid;
1079         return ret_end;
1080 }
1081 #endif
1082
1083 /* This must be invoked after performing all of the necessary
1084  * memblock_set_node() calls for 'nid'.  We need to be able to get
1085  * correct data from get_pfn_range_for_nid().
1086  */
1087 static void __init allocate_node_data(int nid)
1088 {
1089         struct pglist_data *p;
1090         unsigned long start_pfn, end_pfn;
1091 #ifdef CONFIG_NEED_MULTIPLE_NODES
1092
1093         NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data),
1094                                              SMP_CACHE_BYTES, nid);
1095         if (!NODE_DATA(nid)) {
1096                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
1097                 prom_halt();
1098         }
1099
1100         NODE_DATA(nid)->node_id = nid;
1101 #endif
1102
1103         p = NODE_DATA(nid);
1104
1105         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
1106         p->node_start_pfn = start_pfn;
1107         p->node_spanned_pages = end_pfn - start_pfn;
1108 }
1109
1110 static void init_node_masks_nonnuma(void)
1111 {
1112 #ifdef CONFIG_NEED_MULTIPLE_NODES
1113         int i;
1114 #endif
1115
1116         numadbg("Initializing tables for non-numa.\n");
1117
1118         node_masks[0].mask = 0;
1119         node_masks[0].match = 0;
1120         num_node_masks = 1;
1121
1122 #ifdef CONFIG_NEED_MULTIPLE_NODES
1123         for (i = 0; i < NR_CPUS; i++)
1124                 numa_cpu_lookup_table[i] = 0;
1125
1126         cpumask_setall(&numa_cpumask_lookup_table[0]);
1127 #endif
1128 }
1129
1130 #ifdef CONFIG_NEED_MULTIPLE_NODES
1131 struct pglist_data *node_data[MAX_NUMNODES];
1132
1133 EXPORT_SYMBOL(numa_cpu_lookup_table);
1134 EXPORT_SYMBOL(numa_cpumask_lookup_table);
1135 EXPORT_SYMBOL(node_data);
1136
1137 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
1138                                    u32 cfg_handle)
1139 {
1140         u64 arc;
1141
1142         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
1143                 u64 target = mdesc_arc_target(md, arc);
1144                 const u64 *val;
1145
1146                 val = mdesc_get_property(md, target,
1147                                          "cfg-handle", NULL);
1148                 if (val && *val == cfg_handle)
1149                         return 0;
1150         }
1151         return -ENODEV;
1152 }
1153
1154 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1155                                     u32 cfg_handle)
1156 {
1157         u64 arc, candidate, best_latency = ~(u64)0;
1158
1159         candidate = MDESC_NODE_NULL;
1160         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1161                 u64 target = mdesc_arc_target(md, arc);
1162                 const char *name = mdesc_node_name(md, target);
1163                 const u64 *val;
1164
1165                 if (strcmp(name, "pio-latency-group"))
1166                         continue;
1167
1168                 val = mdesc_get_property(md, target, "latency", NULL);
1169                 if (!val)
1170                         continue;
1171
1172                 if (*val < best_latency) {
1173                         candidate = target;
1174                         best_latency = *val;
1175                 }
1176         }
1177
1178         if (candidate == MDESC_NODE_NULL)
1179                 return -ENODEV;
1180
1181         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1182 }
1183
1184 int of_node_to_nid(struct device_node *dp)
1185 {
1186         const struct linux_prom64_registers *regs;
1187         struct mdesc_handle *md;
1188         u32 cfg_handle;
1189         int count, nid;
1190         u64 grp;
1191
1192         /* This is the right thing to do on currently supported
1193          * SUN4U NUMA platforms as well, as the PCI controller does
1194          * not sit behind any particular memory controller.
1195          */
1196         if (!mlgroups)
1197                 return -1;
1198
1199         regs = of_get_property(dp, "reg", NULL);
1200         if (!regs)
1201                 return -1;
1202
1203         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1204
1205         md = mdesc_grab();
1206
1207         count = 0;
1208         nid = NUMA_NO_NODE;
1209         mdesc_for_each_node_by_name(md, grp, "group") {
1210                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1211                         nid = count;
1212                         break;
1213                 }
1214                 count++;
1215         }
1216
1217         mdesc_release(md);
1218
1219         return nid;
1220 }
1221
1222 static void __init add_node_ranges(void)
1223 {
1224         struct memblock_region *reg;
1225         unsigned long prev_max;
1226
1227 memblock_resized:
1228         prev_max = memblock.memory.max;
1229
1230         for_each_memblock(memory, reg) {
1231                 unsigned long size = reg->size;
1232                 unsigned long start, end;
1233
1234                 start = reg->base;
1235                 end = start + size;
1236                 while (start < end) {
1237                         unsigned long this_end;
1238                         int nid;
1239
1240                         this_end = memblock_nid_range(start, end, &nid);
1241
1242                         numadbg("Setting memblock NUMA node nid[%d] "
1243                                 "start[%lx] end[%lx]\n",
1244                                 nid, start, this_end);
1245
1246                         memblock_set_node(start, this_end - start,
1247                                           &memblock.memory, nid);
1248                         if (memblock.memory.max != prev_max)
1249                                 goto memblock_resized;
1250                         start = this_end;
1251                 }
1252         }
1253 }
1254
1255 static int __init grab_mlgroups(struct mdesc_handle *md)
1256 {
1257         unsigned long paddr;
1258         int count = 0;
1259         u64 node;
1260
1261         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1262                 count++;
1263         if (!count)
1264                 return -ENOENT;
1265
1266         paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup),
1267                                     SMP_CACHE_BYTES);
1268         if (!paddr)
1269                 return -ENOMEM;
1270
1271         mlgroups = __va(paddr);
1272         num_mlgroups = count;
1273
1274         count = 0;
1275         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1276                 struct mdesc_mlgroup *m = &mlgroups[count++];
1277                 const u64 *val;
1278
1279                 m->node = node;
1280
1281                 val = mdesc_get_property(md, node, "latency", NULL);
1282                 m->latency = *val;
1283                 val = mdesc_get_property(md, node, "address-match", NULL);
1284                 m->match = *val;
1285                 val = mdesc_get_property(md, node, "address-mask", NULL);
1286                 m->mask = *val;
1287
1288                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1289                         "match[%llx] mask[%llx]\n",
1290                         count - 1, m->node, m->latency, m->match, m->mask);
1291         }
1292
1293         return 0;
1294 }
1295
1296 static int __init grab_mblocks(struct mdesc_handle *md)
1297 {
1298         unsigned long paddr;
1299         int count = 0;
1300         u64 node;
1301
1302         mdesc_for_each_node_by_name(md, node, "mblock")
1303                 count++;
1304         if (!count)
1305                 return -ENOENT;
1306
1307         paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock),
1308                                     SMP_CACHE_BYTES);
1309         if (!paddr)
1310                 return -ENOMEM;
1311
1312         mblocks = __va(paddr);
1313         num_mblocks = count;
1314
1315         count = 0;
1316         mdesc_for_each_node_by_name(md, node, "mblock") {
1317                 struct mdesc_mblock *m = &mblocks[count++];
1318                 const u64 *val;
1319
1320                 val = mdesc_get_property(md, node, "base", NULL);
1321                 m->base = *val;
1322                 val = mdesc_get_property(md, node, "size", NULL);
1323                 m->size = *val;
1324                 val = mdesc_get_property(md, node,
1325                                          "address-congruence-offset", NULL);
1326
1327                 /* The address-congruence-offset property is optional.
1328                  * Explicity zero it be identifty this.
1329                  */
1330                 if (val)
1331                         m->offset = *val;
1332                 else
1333                         m->offset = 0UL;
1334
1335                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1336                         count - 1, m->base, m->size, m->offset);
1337         }
1338
1339         return 0;
1340 }
1341
1342 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1343                                                u64 grp, cpumask_t *mask)
1344 {
1345         u64 arc;
1346
1347         cpumask_clear(mask);
1348
1349         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1350                 u64 target = mdesc_arc_target(md, arc);
1351                 const char *name = mdesc_node_name(md, target);
1352                 const u64 *id;
1353
1354                 if (strcmp(name, "cpu"))
1355                         continue;
1356                 id = mdesc_get_property(md, target, "id", NULL);
1357                 if (*id < nr_cpu_ids)
1358                         cpumask_set_cpu(*id, mask);
1359         }
1360 }
1361
1362 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1363 {
1364         int i;
1365
1366         for (i = 0; i < num_mlgroups; i++) {
1367                 struct mdesc_mlgroup *m = &mlgroups[i];
1368                 if (m->node == node)
1369                         return m;
1370         }
1371         return NULL;
1372 }
1373
1374 int __node_distance(int from, int to)
1375 {
1376         if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1377                 pr_warn("Returning default NUMA distance value for %d->%d\n",
1378                         from, to);
1379                 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1380         }
1381         return numa_latency[from][to];
1382 }
1383 EXPORT_SYMBOL(__node_distance);
1384
1385 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1386 {
1387         int i;
1388
1389         for (i = 0; i < MAX_NUMNODES; i++) {
1390                 struct node_mem_mask *n = &node_masks[i];
1391
1392                 if ((grp->mask == n->mask) && (grp->match == n->match))
1393                         break;
1394         }
1395         return i;
1396 }
1397
1398 static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1399                                                  u64 grp, int index)
1400 {
1401         u64 arc;
1402
1403         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1404                 int tnode;
1405                 u64 target = mdesc_arc_target(md, arc);
1406                 struct mdesc_mlgroup *m = find_mlgroup(target);
1407
1408                 if (!m)
1409                         continue;
1410                 tnode = find_best_numa_node_for_mlgroup(m);
1411                 if (tnode == MAX_NUMNODES)
1412                         continue;
1413                 numa_latency[index][tnode] = m->latency;
1414         }
1415 }
1416
1417 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1418                                       int index)
1419 {
1420         struct mdesc_mlgroup *candidate = NULL;
1421         u64 arc, best_latency = ~(u64)0;
1422         struct node_mem_mask *n;
1423
1424         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1425                 u64 target = mdesc_arc_target(md, arc);
1426                 struct mdesc_mlgroup *m = find_mlgroup(target);
1427                 if (!m)
1428                         continue;
1429                 if (m->latency < best_latency) {
1430                         candidate = m;
1431                         best_latency = m->latency;
1432                 }
1433         }
1434         if (!candidate)
1435                 return -ENOENT;
1436
1437         if (num_node_masks != index) {
1438                 printk(KERN_ERR "Inconsistent NUMA state, "
1439                        "index[%d] != num_node_masks[%d]\n",
1440                        index, num_node_masks);
1441                 return -EINVAL;
1442         }
1443
1444         n = &node_masks[num_node_masks++];
1445
1446         n->mask = candidate->mask;
1447         n->match = candidate->match;
1448
1449         numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1450                 index, n->mask, n->match, candidate->latency);
1451
1452         return 0;
1453 }
1454
1455 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1456                                          int index)
1457 {
1458         cpumask_t mask;
1459         int cpu;
1460
1461         numa_parse_mdesc_group_cpus(md, grp, &mask);
1462
1463         for_each_cpu(cpu, &mask)
1464                 numa_cpu_lookup_table[cpu] = index;
1465         cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1466
1467         if (numa_debug) {
1468                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1469                 for_each_cpu(cpu, &mask)
1470                         printk("%d ", cpu);
1471                 printk("]\n");
1472         }
1473
1474         return numa_attach_mlgroup(md, grp, index);
1475 }
1476
1477 static int __init numa_parse_mdesc(void)
1478 {
1479         struct mdesc_handle *md = mdesc_grab();
1480         int i, j, err, count;
1481         u64 node;
1482
1483         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1484         if (node == MDESC_NODE_NULL) {
1485                 mdesc_release(md);
1486                 return -ENOENT;
1487         }
1488
1489         err = grab_mblocks(md);
1490         if (err < 0)
1491                 goto out;
1492
1493         err = grab_mlgroups(md);
1494         if (err < 0)
1495                 goto out;
1496
1497         count = 0;
1498         mdesc_for_each_node_by_name(md, node, "group") {
1499                 err = numa_parse_mdesc_group(md, node, count);
1500                 if (err < 0)
1501                         break;
1502                 count++;
1503         }
1504
1505         count = 0;
1506         mdesc_for_each_node_by_name(md, node, "group") {
1507                 find_numa_latencies_for_group(md, node, count);
1508                 count++;
1509         }
1510
1511         /* Normalize numa latency matrix according to ACPI SLIT spec. */
1512         for (i = 0; i < MAX_NUMNODES; i++) {
1513                 u64 self_latency = numa_latency[i][i];
1514
1515                 for (j = 0; j < MAX_NUMNODES; j++) {
1516                         numa_latency[i][j] =
1517                                 (numa_latency[i][j] * LOCAL_DISTANCE) /
1518                                 self_latency;
1519                 }
1520         }
1521
1522         add_node_ranges();
1523
1524         for (i = 0; i < num_node_masks; i++) {
1525                 allocate_node_data(i);
1526                 node_set_online(i);
1527         }
1528
1529         err = 0;
1530 out:
1531         mdesc_release(md);
1532         return err;
1533 }
1534
1535 static int __init numa_parse_jbus(void)
1536 {
1537         unsigned long cpu, index;
1538
1539         /* NUMA node id is encoded in bits 36 and higher, and there is
1540          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1541          */
1542         index = 0;
1543         for_each_present_cpu(cpu) {
1544                 numa_cpu_lookup_table[cpu] = index;
1545                 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1546                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1547                 node_masks[index].match = cpu << 36UL;
1548
1549                 index++;
1550         }
1551         num_node_masks = index;
1552
1553         add_node_ranges();
1554
1555         for (index = 0; index < num_node_masks; index++) {
1556                 allocate_node_data(index);
1557                 node_set_online(index);
1558         }
1559
1560         return 0;
1561 }
1562
1563 static int __init numa_parse_sun4u(void)
1564 {
1565         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1566                 unsigned long ver;
1567
1568                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1569                 if ((ver >> 32UL) == __JALAPENO_ID ||
1570                     (ver >> 32UL) == __SERRANO_ID)
1571                         return numa_parse_jbus();
1572         }
1573         return -1;
1574 }
1575
1576 static int __init bootmem_init_numa(void)
1577 {
1578         int i, j;
1579         int err = -1;
1580
1581         numadbg("bootmem_init_numa()\n");
1582
1583         /* Some sane defaults for numa latency values */
1584         for (i = 0; i < MAX_NUMNODES; i++) {
1585                 for (j = 0; j < MAX_NUMNODES; j++)
1586                         numa_latency[i][j] = (i == j) ?
1587                                 LOCAL_DISTANCE : REMOTE_DISTANCE;
1588         }
1589
1590         if (numa_enabled) {
1591                 if (tlb_type == hypervisor)
1592                         err = numa_parse_mdesc();
1593                 else
1594                         err = numa_parse_sun4u();
1595         }
1596         return err;
1597 }
1598
1599 #else
1600
1601 static int bootmem_init_numa(void)
1602 {
1603         return -1;
1604 }
1605
1606 #endif
1607
1608 static void __init bootmem_init_nonnuma(void)
1609 {
1610         unsigned long top_of_ram = memblock_end_of_DRAM();
1611         unsigned long total_ram = memblock_phys_mem_size();
1612
1613         numadbg("bootmem_init_nonnuma()\n");
1614
1615         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1616                top_of_ram, total_ram);
1617         printk(KERN_INFO "Memory hole size: %ldMB\n",
1618                (top_of_ram - total_ram) >> 20);
1619
1620         init_node_masks_nonnuma();
1621         memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
1622         allocate_node_data(0);
1623         node_set_online(0);
1624 }
1625
1626 static unsigned long __init bootmem_init(unsigned long phys_base)
1627 {
1628         unsigned long end_pfn;
1629
1630         end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1631         max_pfn = max_low_pfn = end_pfn;
1632         min_low_pfn = (phys_base >> PAGE_SHIFT);
1633
1634         if (bootmem_init_numa() < 0)
1635                 bootmem_init_nonnuma();
1636
1637         /* Dump memblock with node info. */
1638         memblock_dump_all();
1639
1640         /* XXX cpu notifier XXX */
1641
1642         sparse_memory_present_with_active_regions(MAX_NUMNODES);
1643         sparse_init();
1644
1645         return end_pfn;
1646 }
1647
1648 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1649 static int pall_ents __initdata;
1650
1651 static unsigned long max_phys_bits = 40;
1652
1653 bool kern_addr_valid(unsigned long addr)
1654 {
1655         pgd_t *pgd;
1656         pud_t *pud;
1657         pmd_t *pmd;
1658         pte_t *pte;
1659
1660         if ((long)addr < 0L) {
1661                 unsigned long pa = __pa(addr);
1662
1663                 if ((pa >> max_phys_bits) != 0UL)
1664                         return false;
1665
1666                 return pfn_valid(pa >> PAGE_SHIFT);
1667         }
1668
1669         if (addr >= (unsigned long) KERNBASE &&
1670             addr < (unsigned long)&_end)
1671                 return true;
1672
1673         pgd = pgd_offset_k(addr);
1674         if (pgd_none(*pgd))
1675                 return 0;
1676
1677         pud = pud_offset(pgd, addr);
1678         if (pud_none(*pud))
1679                 return 0;
1680
1681         if (pud_large(*pud))
1682                 return pfn_valid(pud_pfn(*pud));
1683
1684         pmd = pmd_offset(pud, addr);
1685         if (pmd_none(*pmd))
1686                 return 0;
1687
1688         if (pmd_large(*pmd))
1689                 return pfn_valid(pmd_pfn(*pmd));
1690
1691         pte = pte_offset_kernel(pmd, addr);
1692         if (pte_none(*pte))
1693                 return 0;
1694
1695         return pfn_valid(pte_pfn(*pte));
1696 }
1697 EXPORT_SYMBOL(kern_addr_valid);
1698
1699 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1700                                               unsigned long vend,
1701                                               pud_t *pud)
1702 {
1703         const unsigned long mask16gb = (1UL << 34) - 1UL;
1704         u64 pte_val = vstart;
1705
1706         /* Each PUD is 8GB */
1707         if ((vstart & mask16gb) ||
1708             (vend - vstart <= mask16gb)) {
1709                 pte_val ^= kern_linear_pte_xor[2];
1710                 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1711
1712                 return vstart + PUD_SIZE;
1713         }
1714
1715         pte_val ^= kern_linear_pte_xor[3];
1716         pte_val |= _PAGE_PUD_HUGE;
1717
1718         vend = vstart + mask16gb + 1UL;
1719         while (vstart < vend) {
1720                 pud_val(*pud) = pte_val;
1721
1722                 pte_val += PUD_SIZE;
1723                 vstart += PUD_SIZE;
1724                 pud++;
1725         }
1726         return vstart;
1727 }
1728
1729 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1730                                    bool guard)
1731 {
1732         if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1733                 return true;
1734
1735         return false;
1736 }
1737
1738 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1739                                               unsigned long vend,
1740                                               pmd_t *pmd)
1741 {
1742         const unsigned long mask256mb = (1UL << 28) - 1UL;
1743         const unsigned long mask2gb = (1UL << 31) - 1UL;
1744         u64 pte_val = vstart;
1745
1746         /* Each PMD is 8MB */
1747         if ((vstart & mask256mb) ||
1748             (vend - vstart <= mask256mb)) {
1749                 pte_val ^= kern_linear_pte_xor[0];
1750                 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1751
1752                 return vstart + PMD_SIZE;
1753         }
1754
1755         if ((vstart & mask2gb) ||
1756             (vend - vstart <= mask2gb)) {
1757                 pte_val ^= kern_linear_pte_xor[1];
1758                 pte_val |= _PAGE_PMD_HUGE;
1759                 vend = vstart + mask256mb + 1UL;
1760         } else {
1761                 pte_val ^= kern_linear_pte_xor[2];
1762                 pte_val |= _PAGE_PMD_HUGE;
1763                 vend = vstart + mask2gb + 1UL;
1764         }
1765
1766         while (vstart < vend) {
1767                 pmd_val(*pmd) = pte_val;
1768
1769                 pte_val += PMD_SIZE;
1770                 vstart += PMD_SIZE;
1771                 pmd++;
1772         }
1773
1774         return vstart;
1775 }
1776
1777 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1778                                    bool guard)
1779 {
1780         if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1781                 return true;
1782
1783         return false;
1784 }
1785
1786 static unsigned long __ref kernel_map_range(unsigned long pstart,
1787                                             unsigned long pend, pgprot_t prot,
1788                                             bool use_huge)
1789 {
1790         unsigned long vstart = PAGE_OFFSET + pstart;
1791         unsigned long vend = PAGE_OFFSET + pend;
1792         unsigned long alloc_bytes = 0UL;
1793
1794         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1795                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1796                             vstart, vend);
1797                 prom_halt();
1798         }
1799
1800         while (vstart < vend) {
1801                 unsigned long this_end, paddr = __pa(vstart);
1802                 pgd_t *pgd = pgd_offset_k(vstart);
1803                 pud_t *pud;
1804                 pmd_t *pmd;
1805                 pte_t *pte;
1806
1807                 if (pgd_none(*pgd)) {
1808                         pud_t *new;
1809
1810                         new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1811                                                   PAGE_SIZE);
1812                         if (!new)
1813                                 goto err_alloc;
1814                         alloc_bytes += PAGE_SIZE;
1815                         pgd_populate(&init_mm, pgd, new);
1816                 }
1817                 pud = pud_offset(pgd, vstart);
1818                 if (pud_none(*pud)) {
1819                         pmd_t *new;
1820
1821                         if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1822                                 vstart = kernel_map_hugepud(vstart, vend, pud);
1823                                 continue;
1824                         }
1825                         new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1826                                                   PAGE_SIZE);
1827                         if (!new)
1828                                 goto err_alloc;
1829                         alloc_bytes += PAGE_SIZE;
1830                         pud_populate(&init_mm, pud, new);
1831                 }
1832
1833                 pmd = pmd_offset(pud, vstart);
1834                 if (pmd_none(*pmd)) {
1835                         pte_t *new;
1836
1837                         if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1838                                 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1839                                 continue;
1840                         }
1841                         new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1842                                                   PAGE_SIZE);
1843                         if (!new)
1844                                 goto err_alloc;
1845                         alloc_bytes += PAGE_SIZE;
1846                         pmd_populate_kernel(&init_mm, pmd, new);
1847                 }
1848
1849                 pte = pte_offset_kernel(pmd, vstart);
1850                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1851                 if (this_end > vend)
1852                         this_end = vend;
1853
1854                 while (vstart < this_end) {
1855                         pte_val(*pte) = (paddr | pgprot_val(prot));
1856
1857                         vstart += PAGE_SIZE;
1858                         paddr += PAGE_SIZE;
1859                         pte++;
1860                 }
1861         }
1862
1863         return alloc_bytes;
1864
1865 err_alloc:
1866         panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n",
1867               __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1868         return -ENOMEM;
1869 }
1870
1871 static void __init flush_all_kernel_tsbs(void)
1872 {
1873         int i;
1874
1875         for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1876                 struct tsb *ent = &swapper_tsb[i];
1877
1878                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1879         }
1880 #ifndef CONFIG_DEBUG_PAGEALLOC
1881         for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1882                 struct tsb *ent = &swapper_4m_tsb[i];
1883
1884                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1885         }
1886 #endif
1887 }
1888
1889 extern unsigned int kvmap_linear_patch[1];
1890
1891 static void __init kernel_physical_mapping_init(void)
1892 {
1893         unsigned long i, mem_alloced = 0UL;
1894         bool use_huge = true;
1895
1896 #ifdef CONFIG_DEBUG_PAGEALLOC
1897         use_huge = false;
1898 #endif
1899         for (i = 0; i < pall_ents; i++) {
1900                 unsigned long phys_start, phys_end;
1901
1902                 phys_start = pall[i].phys_addr;
1903                 phys_end = phys_start + pall[i].reg_size;
1904
1905                 mem_alloced += kernel_map_range(phys_start, phys_end,
1906                                                 PAGE_KERNEL, use_huge);
1907         }
1908
1909         printk("Allocated %ld bytes for kernel page tables.\n",
1910                mem_alloced);
1911
1912         kvmap_linear_patch[0] = 0x01000000; /* nop */
1913         flushi(&kvmap_linear_patch[0]);
1914
1915         flush_all_kernel_tsbs();
1916
1917         __flush_tlb_all();
1918 }
1919
1920 #ifdef CONFIG_DEBUG_PAGEALLOC
1921 void __kernel_map_pages(struct page *page, int numpages, int enable)
1922 {
1923         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1924         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1925
1926         kernel_map_range(phys_start, phys_end,
1927                          (enable ? PAGE_KERNEL : __pgprot(0)), false);
1928
1929         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1930                                PAGE_OFFSET + phys_end);
1931
1932         /* we should perform an IPI and flush all tlbs,
1933          * but that can deadlock->flush only current cpu.
1934          */
1935         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1936                                  PAGE_OFFSET + phys_end);
1937 }
1938 #endif
1939
1940 unsigned long __init find_ecache_flush_span(unsigned long size)
1941 {
1942         int i;
1943
1944         for (i = 0; i < pavail_ents; i++) {
1945                 if (pavail[i].reg_size >= size)
1946                         return pavail[i].phys_addr;
1947         }
1948
1949         return ~0UL;
1950 }
1951
1952 unsigned long PAGE_OFFSET;
1953 EXPORT_SYMBOL(PAGE_OFFSET);
1954
1955 unsigned long VMALLOC_END   = 0x0000010000000000UL;
1956 EXPORT_SYMBOL(VMALLOC_END);
1957
1958 unsigned long sparc64_va_hole_top =    0xfffff80000000000UL;
1959 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1960
1961 static void __init setup_page_offset(void)
1962 {
1963         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1964                 /* Cheetah/Panther support a full 64-bit virtual
1965                  * address, so we can use all that our page tables
1966                  * support.
1967                  */
1968                 sparc64_va_hole_top =    0xfff0000000000000UL;
1969                 sparc64_va_hole_bottom = 0x0010000000000000UL;
1970
1971                 max_phys_bits = 42;
1972         } else if (tlb_type == hypervisor) {
1973                 switch (sun4v_chip_type) {
1974                 case SUN4V_CHIP_NIAGARA1:
1975                 case SUN4V_CHIP_NIAGARA2:
1976                         /* T1 and T2 support 48-bit virtual addresses.  */
1977                         sparc64_va_hole_top =    0xffff800000000000UL;
1978                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1979
1980                         max_phys_bits = 39;
1981                         break;
1982                 case SUN4V_CHIP_NIAGARA3:
1983                         /* T3 supports 48-bit virtual addresses.  */
1984                         sparc64_va_hole_top =    0xffff800000000000UL;
1985                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1986
1987                         max_phys_bits = 43;
1988                         break;
1989                 case SUN4V_CHIP_NIAGARA4:
1990                 case SUN4V_CHIP_NIAGARA5:
1991                 case SUN4V_CHIP_SPARC64X:
1992                 case SUN4V_CHIP_SPARC_M6:
1993                         /* T4 and later support 52-bit virtual addresses.  */
1994                         sparc64_va_hole_top =    0xfff8000000000000UL;
1995                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1996                         max_phys_bits = 47;
1997                         break;
1998                 case SUN4V_CHIP_SPARC_M7:
1999                 case SUN4V_CHIP_SPARC_SN:
2000                         /* M7 and later support 52-bit virtual addresses.  */
2001                         sparc64_va_hole_top =    0xfff8000000000000UL;
2002                         sparc64_va_hole_bottom = 0x0008000000000000UL;
2003                         max_phys_bits = 49;
2004                         break;
2005                 case SUN4V_CHIP_SPARC_M8:
2006                 default:
2007                         /* M8 and later support 54-bit virtual addresses.
2008                          * However, restricting M8 and above VA bits to 53
2009                          * as 4-level page table cannot support more than
2010                          * 53 VA bits.
2011                          */
2012                         sparc64_va_hole_top =    0xfff0000000000000UL;
2013                         sparc64_va_hole_bottom = 0x0010000000000000UL;
2014                         max_phys_bits = 51;
2015                         break;
2016                 }
2017         }
2018
2019         if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
2020                 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
2021                             max_phys_bits);
2022                 prom_halt();
2023         }
2024
2025         PAGE_OFFSET = sparc64_va_hole_top;
2026         VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
2027                        (sparc64_va_hole_bottom >> 2));
2028
2029         pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2030                 PAGE_OFFSET, max_phys_bits);
2031         pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
2032                 VMALLOC_START, VMALLOC_END);
2033         pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
2034                 VMEMMAP_BASE, VMEMMAP_BASE << 1);
2035 }
2036
2037 static void __init tsb_phys_patch(void)
2038 {
2039         struct tsb_ldquad_phys_patch_entry *pquad;
2040         struct tsb_phys_patch_entry *p;
2041
2042         pquad = &__tsb_ldquad_phys_patch;
2043         while (pquad < &__tsb_ldquad_phys_patch_end) {
2044                 unsigned long addr = pquad->addr;
2045
2046                 if (tlb_type == hypervisor)
2047                         *(unsigned int *) addr = pquad->sun4v_insn;
2048                 else
2049                         *(unsigned int *) addr = pquad->sun4u_insn;
2050                 wmb();
2051                 __asm__ __volatile__("flush     %0"
2052                                      : /* no outputs */
2053                                      : "r" (addr));
2054
2055                 pquad++;
2056         }
2057
2058         p = &__tsb_phys_patch;
2059         while (p < &__tsb_phys_patch_end) {
2060                 unsigned long addr = p->addr;
2061
2062                 *(unsigned int *) addr = p->insn;
2063                 wmb();
2064                 __asm__ __volatile__("flush     %0"
2065                                      : /* no outputs */
2066                                      : "r" (addr));
2067
2068                 p++;
2069         }
2070 }
2071
2072 /* Don't mark as init, we give this to the Hypervisor.  */
2073 #ifndef CONFIG_DEBUG_PAGEALLOC
2074 #define NUM_KTSB_DESCR  2
2075 #else
2076 #define NUM_KTSB_DESCR  1
2077 #endif
2078 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2079
2080 /* The swapper TSBs are loaded with a base sequence of:
2081  *
2082  *      sethi   %uhi(SYMBOL), REG1
2083  *      sethi   %hi(SYMBOL), REG2
2084  *      or      REG1, %ulo(SYMBOL), REG1
2085  *      or      REG2, %lo(SYMBOL), REG2
2086  *      sllx    REG1, 32, REG1
2087  *      or      REG1, REG2, REG1
2088  *
2089  * When we use physical addressing for the TSB accesses, we patch the
2090  * first four instructions in the above sequence.
2091  */
2092
2093 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
2094 {
2095         unsigned long high_bits, low_bits;
2096
2097         high_bits = (pa >> 32) & 0xffffffff;
2098         low_bits = (pa >> 0) & 0xffffffff;
2099
2100         while (start < end) {
2101                 unsigned int *ia = (unsigned int *)(unsigned long)*start;
2102
2103                 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2104                 __asm__ __volatile__("flush     %0" : : "r" (ia));
2105
2106                 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2107                 __asm__ __volatile__("flush     %0" : : "r" (ia + 1));
2108
2109                 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
2110                 __asm__ __volatile__("flush     %0" : : "r" (ia + 2));
2111
2112                 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
2113                 __asm__ __volatile__("flush     %0" : : "r" (ia + 3));
2114
2115                 start++;
2116         }
2117 }
2118
2119 static void ktsb_phys_patch(void)
2120 {
2121         extern unsigned int __swapper_tsb_phys_patch;
2122         extern unsigned int __swapper_tsb_phys_patch_end;
2123         unsigned long ktsb_pa;
2124
2125         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2126         patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
2127                             &__swapper_tsb_phys_patch_end, ktsb_pa);
2128 #ifndef CONFIG_DEBUG_PAGEALLOC
2129         {
2130         extern unsigned int __swapper_4m_tsb_phys_patch;
2131         extern unsigned int __swapper_4m_tsb_phys_patch_end;
2132         ktsb_pa = (kern_base +
2133                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2134         patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
2135                             &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2136         }
2137 #endif
2138 }
2139
2140 static void __init sun4v_ktsb_init(void)
2141 {
2142         unsigned long ktsb_pa;
2143
2144         /* First KTSB for PAGE_SIZE mappings.  */
2145         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2146
2147         switch (PAGE_SIZE) {
2148         case 8 * 1024:
2149         default:
2150                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2151                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2152                 break;
2153
2154         case 64 * 1024:
2155                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2156                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2157                 break;
2158
2159         case 512 * 1024:
2160                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2161                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2162                 break;
2163
2164         case 4 * 1024 * 1024:
2165                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2166                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2167                 break;
2168         }
2169
2170         ktsb_descr[0].assoc = 1;
2171         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2172         ktsb_descr[0].ctx_idx = 0;
2173         ktsb_descr[0].tsb_base = ktsb_pa;
2174         ktsb_descr[0].resv = 0;
2175
2176 #ifndef CONFIG_DEBUG_PAGEALLOC
2177         /* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
2178         ktsb_pa = (kern_base +
2179                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2180
2181         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2182         ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2183                                     HV_PGSZ_MASK_256MB |
2184                                     HV_PGSZ_MASK_2GB |
2185                                     HV_PGSZ_MASK_16GB) &
2186                                    cpu_pgsz_mask);
2187         ktsb_descr[1].assoc = 1;
2188         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2189         ktsb_descr[1].ctx_idx = 0;
2190         ktsb_descr[1].tsb_base = ktsb_pa;
2191         ktsb_descr[1].resv = 0;
2192 #endif
2193 }
2194
2195 void sun4v_ktsb_register(void)
2196 {
2197         unsigned long pa, ret;
2198
2199         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2200
2201         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2202         if (ret != 0) {
2203                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2204                             "errors with %lx\n", pa, ret);
2205                 prom_halt();
2206         }
2207 }
2208
2209 static void __init sun4u_linear_pte_xor_finalize(void)
2210 {
2211 #ifndef CONFIG_DEBUG_PAGEALLOC
2212         /* This is where we would add Panther support for
2213          * 32MB and 256MB pages.
2214          */
2215 #endif
2216 }
2217
2218 static void __init sun4v_linear_pte_xor_finalize(void)
2219 {
2220         unsigned long pagecv_flag;
2221
2222         /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2223          * enables MCD error. Do not set bit 9 on M7 processor.
2224          */
2225         switch (sun4v_chip_type) {
2226         case SUN4V_CHIP_SPARC_M7:
2227         case SUN4V_CHIP_SPARC_M8:
2228         case SUN4V_CHIP_SPARC_SN:
2229                 pagecv_flag = 0x00;
2230                 break;
2231         default:
2232                 pagecv_flag = _PAGE_CV_4V;
2233                 break;
2234         }
2235 #ifndef CONFIG_DEBUG_PAGEALLOC
2236         if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2237                 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2238                         PAGE_OFFSET;
2239                 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2240                                            _PAGE_P_4V | _PAGE_W_4V);
2241         } else {
2242                 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2243         }
2244
2245         if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2246                 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2247                         PAGE_OFFSET;
2248                 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2249                                            _PAGE_P_4V | _PAGE_W_4V);
2250         } else {
2251                 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2252         }
2253
2254         if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2255                 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2256                         PAGE_OFFSET;
2257                 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2258                                            _PAGE_P_4V | _PAGE_W_4V);
2259         } else {
2260                 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2261         }
2262 #endif
2263 }
2264
2265 /* paging_init() sets up the page tables */
2266
2267 static unsigned long last_valid_pfn;
2268
2269 static void sun4u_pgprot_init(void);
2270 static void sun4v_pgprot_init(void);
2271
2272 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2273 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2274 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2275 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2276 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2277 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2278
2279 /* We need to exclude reserved regions. This exclusion will include
2280  * vmlinux and initrd. To be more precise the initrd size could be used to
2281  * compute a new lower limit because it is freed later during initialization.
2282  */
2283 static void __init reduce_memory(phys_addr_t limit_ram)
2284 {
2285         limit_ram += memblock_reserved_size();
2286         memblock_enforce_memory_limit(limit_ram);
2287 }
2288
2289 void __init paging_init(void)
2290 {
2291         unsigned long end_pfn, shift, phys_base;
2292         unsigned long real_end, i;
2293
2294         setup_page_offset();
2295
2296         /* These build time checkes make sure that the dcache_dirty_cpu()
2297          * page->flags usage will work.
2298          *
2299          * When a page gets marked as dcache-dirty, we store the
2300          * cpu number starting at bit 32 in the page->flags.  Also,
2301          * functions like clear_dcache_dirty_cpu use the cpu mask
2302          * in 13-bit signed-immediate instruction fields.
2303          */
2304
2305         /*
2306          * Page flags must not reach into upper 32 bits that are used
2307          * for the cpu number
2308          */
2309         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2310
2311         /*
2312          * The bit fields placed in the high range must not reach below
2313          * the 32 bit boundary. Otherwise we cannot place the cpu field
2314          * at the 32 bit boundary.
2315          */
2316         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2317                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2318
2319         BUILD_BUG_ON(NR_CPUS > 4096);
2320
2321         kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2322         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2323
2324         /* Invalidate both kernel TSBs.  */
2325         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2326 #ifndef CONFIG_DEBUG_PAGEALLOC
2327         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2328 #endif
2329
2330         /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2331          * bit on M7 processor. This is a conflicting usage of the same
2332          * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2333          * Detection error on all pages and this will lead to problems
2334          * later. Kernel does not run with MCD enabled and hence rest
2335          * of the required steps to fully configure memory corruption
2336          * detection are not taken. We need to ensure TTE.mcde is not
2337          * set on M7 processor. Compute the value of cacheability
2338          * flag for use later taking this into consideration.
2339          */
2340         switch (sun4v_chip_type) {
2341         case SUN4V_CHIP_SPARC_M7:
2342         case SUN4V_CHIP_SPARC_M8:
2343         case SUN4V_CHIP_SPARC_SN:
2344                 page_cache4v_flag = _PAGE_CP_4V;
2345                 break;
2346         default:
2347                 page_cache4v_flag = _PAGE_CACHE_4V;
2348                 break;
2349         }
2350
2351         if (tlb_type == hypervisor)
2352                 sun4v_pgprot_init();
2353         else
2354                 sun4u_pgprot_init();
2355
2356         if (tlb_type == cheetah_plus ||
2357             tlb_type == hypervisor) {
2358                 tsb_phys_patch();
2359                 ktsb_phys_patch();
2360         }
2361
2362         if (tlb_type == hypervisor)
2363                 sun4v_patch_tlb_handlers();
2364
2365         /* Find available physical memory...
2366          *
2367          * Read it twice in order to work around a bug in openfirmware.
2368          * The call to grab this table itself can cause openfirmware to
2369          * allocate memory, which in turn can take away some space from
2370          * the list of available memory.  Reading it twice makes sure
2371          * we really do get the final value.
2372          */
2373         read_obp_translations();
2374         read_obp_memory("reg", &pall[0], &pall_ents);
2375         read_obp_memory("available", &pavail[0], &pavail_ents);
2376         read_obp_memory("available", &pavail[0], &pavail_ents);
2377
2378         phys_base = 0xffffffffffffffffUL;
2379         for (i = 0; i < pavail_ents; i++) {
2380                 phys_base = min(phys_base, pavail[i].phys_addr);
2381                 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2382         }
2383
2384         memblock_reserve(kern_base, kern_size);
2385
2386         find_ramdisk(phys_base);
2387
2388         if (cmdline_memory_size)
2389                 reduce_memory(cmdline_memory_size);
2390
2391         memblock_allow_resize();
2392         memblock_dump_all();
2393
2394         set_bit(0, mmu_context_bmap);
2395
2396         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2397
2398         real_end = (unsigned long)_end;
2399         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2400         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2401                num_kernel_image_mappings);
2402
2403         /* Set kernel pgd to upper alias so physical page computations
2404          * work.
2405          */
2406         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2407
2408         memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2409
2410         inherit_prom_mappings();
2411
2412         /* Ok, we can use our TLB miss and window trap handlers safely.  */
2413         setup_tba();
2414
2415         __flush_tlb_all();
2416
2417         prom_build_devicetree();
2418         of_populate_present_mask();
2419 #ifndef CONFIG_SMP
2420         of_fill_in_cpu_data();
2421 #endif
2422
2423         if (tlb_type == hypervisor) {
2424                 sun4v_mdesc_init();
2425                 mdesc_populate_present_mask(cpu_all_mask);
2426 #ifndef CONFIG_SMP
2427                 mdesc_fill_in_cpu_data(cpu_all_mask);
2428 #endif
2429                 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2430
2431                 sun4v_linear_pte_xor_finalize();
2432
2433                 sun4v_ktsb_init();
2434                 sun4v_ktsb_register();
2435         } else {
2436                 unsigned long impl, ver;
2437
2438                 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2439                                  HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2440
2441                 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2442                 impl = ((ver >> 32) & 0xffff);
2443                 if (impl == PANTHER_IMPL)
2444                         cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2445                                           HV_PGSZ_MASK_256MB);
2446
2447                 sun4u_linear_pte_xor_finalize();
2448         }
2449
2450         /* Flush the TLBs and the 4M TSB so that the updated linear
2451          * pte XOR settings are realized for all mappings.
2452          */
2453         __flush_tlb_all();
2454 #ifndef CONFIG_DEBUG_PAGEALLOC
2455         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2456 #endif
2457         __flush_tlb_all();
2458
2459         /* Setup bootmem... */
2460         last_valid_pfn = end_pfn = bootmem_init(phys_base);
2461
2462         kernel_physical_mapping_init();
2463
2464         {
2465                 unsigned long max_zone_pfns[MAX_NR_ZONES];
2466
2467                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2468
2469                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2470
2471                 free_area_init_nodes(max_zone_pfns);
2472         }
2473
2474         printk("Booting Linux...\n");
2475 }
2476
2477 int page_in_phys_avail(unsigned long paddr)
2478 {
2479         int i;
2480
2481         paddr &= PAGE_MASK;
2482
2483         for (i = 0; i < pavail_ents; i++) {
2484                 unsigned long start, end;
2485
2486                 start = pavail[i].phys_addr;
2487                 end = start + pavail[i].reg_size;
2488
2489                 if (paddr >= start && paddr < end)
2490                         return 1;
2491         }
2492         if (paddr >= kern_base && paddr < (kern_base + kern_size))
2493                 return 1;
2494 #ifdef CONFIG_BLK_DEV_INITRD
2495         if (paddr >= __pa(initrd_start) &&
2496             paddr < __pa(PAGE_ALIGN(initrd_end)))
2497                 return 1;
2498 #endif
2499
2500         return 0;
2501 }
2502
2503 static void __init register_page_bootmem_info(void)
2504 {
2505 #ifdef CONFIG_NEED_MULTIPLE_NODES
2506         int i;
2507
2508         for_each_online_node(i)
2509                 if (NODE_DATA(i)->node_spanned_pages)
2510                         register_page_bootmem_info_node(NODE_DATA(i));
2511 #endif
2512 }
2513 void __init mem_init(void)
2514 {
2515         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2516
2517         memblock_free_all();
2518
2519         /*
2520          * Must be done after boot memory is put on freelist, because here we
2521          * might set fields in deferred struct pages that have not yet been
2522          * initialized, and memblock_free_all() initializes all the reserved
2523          * deferred pages for us.
2524          */
2525         register_page_bootmem_info();
2526
2527         /*
2528          * Set up the zero page, mark it reserved, so that page count
2529          * is not manipulated when freeing the page from user ptes.
2530          */
2531         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2532         if (mem_map_zero == NULL) {
2533                 prom_printf("paging_init: Cannot alloc zero page.\n");
2534                 prom_halt();
2535         }
2536         mark_page_reserved(mem_map_zero);
2537
2538         mem_init_print_info(NULL);
2539
2540         if (tlb_type == cheetah || tlb_type == cheetah_plus)
2541                 cheetah_ecache_flush_init();
2542 }
2543
2544 void free_initmem(void)
2545 {
2546         unsigned long addr, initend;
2547         int do_free = 1;
2548
2549         /* If the physical memory maps were trimmed by kernel command
2550          * line options, don't even try freeing this initmem stuff up.
2551          * The kernel image could have been in the trimmed out region
2552          * and if so the freeing below will free invalid page structs.
2553          */
2554         if (cmdline_memory_size)
2555                 do_free = 0;
2556
2557         /*
2558          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2559          */
2560         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2561         initend = (unsigned long)(__init_end) & PAGE_MASK;
2562         for (; addr < initend; addr += PAGE_SIZE) {
2563                 unsigned long page;
2564
2565                 page = (addr +
2566                         ((unsigned long) __va(kern_base)) -
2567                         ((unsigned long) KERNBASE));
2568                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2569
2570                 if (do_free)
2571                         free_reserved_page(virt_to_page(page));
2572         }
2573 }
2574
2575 pgprot_t PAGE_KERNEL __read_mostly;
2576 EXPORT_SYMBOL(PAGE_KERNEL);
2577
2578 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2579 pgprot_t PAGE_COPY __read_mostly;
2580
2581 pgprot_t PAGE_SHARED __read_mostly;
2582 EXPORT_SYMBOL(PAGE_SHARED);
2583
2584 unsigned long pg_iobits __read_mostly;
2585
2586 unsigned long _PAGE_IE __read_mostly;
2587 EXPORT_SYMBOL(_PAGE_IE);
2588
2589 unsigned long _PAGE_E __read_mostly;
2590 EXPORT_SYMBOL(_PAGE_E);
2591
2592 unsigned long _PAGE_CACHE __read_mostly;
2593 EXPORT_SYMBOL(_PAGE_CACHE);
2594
2595 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2596 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2597                                int node, struct vmem_altmap *altmap)
2598 {
2599         unsigned long pte_base;
2600
2601         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2602                     _PAGE_CP_4U | _PAGE_CV_4U |
2603                     _PAGE_P_4U | _PAGE_W_4U);
2604         if (tlb_type == hypervisor)
2605                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2606                             page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2607
2608         pte_base |= _PAGE_PMD_HUGE;
2609
2610         vstart = vstart & PMD_MASK;
2611         vend = ALIGN(vend, PMD_SIZE);
2612         for (; vstart < vend; vstart += PMD_SIZE) {
2613                 pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
2614                 unsigned long pte;
2615                 pud_t *pud;
2616                 pmd_t *pmd;
2617
2618                 if (!pgd)
2619                         return -ENOMEM;
2620
2621                 pud = vmemmap_pud_populate(pgd, vstart, node);
2622                 if (!pud)
2623                         return -ENOMEM;
2624
2625                 pmd = pmd_offset(pud, vstart);
2626                 pte = pmd_val(*pmd);
2627                 if (!(pte & _PAGE_VALID)) {
2628                         void *block = vmemmap_alloc_block(PMD_SIZE, node);
2629
2630                         if (!block)
2631                                 return -ENOMEM;
2632
2633                         pmd_val(*pmd) = pte_base | __pa(block);
2634                 }
2635         }
2636
2637         return 0;
2638 }
2639
2640 void vmemmap_free(unsigned long start, unsigned long end,
2641                 struct vmem_altmap *altmap)
2642 {
2643 }
2644 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2645
2646 static void prot_init_common(unsigned long page_none,
2647                              unsigned long page_shared,
2648                              unsigned long page_copy,
2649                              unsigned long page_readonly,
2650                              unsigned long page_exec_bit)
2651 {
2652         PAGE_COPY = __pgprot(page_copy);
2653         PAGE_SHARED = __pgprot(page_shared);
2654
2655         protection_map[0x0] = __pgprot(page_none);
2656         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2657         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2658         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2659         protection_map[0x4] = __pgprot(page_readonly);
2660         protection_map[0x5] = __pgprot(page_readonly);
2661         protection_map[0x6] = __pgprot(page_copy);
2662         protection_map[0x7] = __pgprot(page_copy);
2663         protection_map[0x8] = __pgprot(page_none);
2664         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2665         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2666         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2667         protection_map[0xc] = __pgprot(page_readonly);
2668         protection_map[0xd] = __pgprot(page_readonly);
2669         protection_map[0xe] = __pgprot(page_shared);
2670         protection_map[0xf] = __pgprot(page_shared);
2671 }
2672
2673 static void __init sun4u_pgprot_init(void)
2674 {
2675         unsigned long page_none, page_shared, page_copy, page_readonly;
2676         unsigned long page_exec_bit;
2677         int i;
2678
2679         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2680                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2681                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2682                                 _PAGE_EXEC_4U);
2683         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2684                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2685                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2686                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2687
2688         _PAGE_IE = _PAGE_IE_4U;
2689         _PAGE_E = _PAGE_E_4U;
2690         _PAGE_CACHE = _PAGE_CACHE_4U;
2691
2692         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2693                      __ACCESS_BITS_4U | _PAGE_E_4U);
2694
2695 #ifdef CONFIG_DEBUG_PAGEALLOC
2696         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2697 #else
2698         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2699                 PAGE_OFFSET;
2700 #endif
2701         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2702                                    _PAGE_P_4U | _PAGE_W_4U);
2703
2704         for (i = 1; i < 4; i++)
2705                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2706
2707         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2708                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2709                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2710
2711
2712         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2713         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2714                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2715         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2716                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2717         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2718                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2719
2720         page_exec_bit = _PAGE_EXEC_4U;
2721
2722         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2723                          page_exec_bit);
2724 }
2725
2726 static void __init sun4v_pgprot_init(void)
2727 {
2728         unsigned long page_none, page_shared, page_copy, page_readonly;
2729         unsigned long page_exec_bit;
2730         int i;
2731
2732         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2733                                 page_cache4v_flag | _PAGE_P_4V |
2734                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2735                                 _PAGE_EXEC_4V);
2736         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2737
2738         _PAGE_IE = _PAGE_IE_4V;
2739         _PAGE_E = _PAGE_E_4V;
2740         _PAGE_CACHE = page_cache4v_flag;
2741
2742 #ifdef CONFIG_DEBUG_PAGEALLOC
2743         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2744 #else
2745         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2746                 PAGE_OFFSET;
2747 #endif
2748         kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2749                                    _PAGE_W_4V);
2750
2751         for (i = 1; i < 4; i++)
2752                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2753
2754         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2755                      __ACCESS_BITS_4V | _PAGE_E_4V);
2756
2757         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2758                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2759                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2760                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2761
2762         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2763         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2764                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2765         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2766                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2767         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2768                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2769
2770         page_exec_bit = _PAGE_EXEC_4V;
2771
2772         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2773                          page_exec_bit);
2774 }
2775
2776 unsigned long pte_sz_bits(unsigned long sz)
2777 {
2778         if (tlb_type == hypervisor) {
2779                 switch (sz) {
2780                 case 8 * 1024:
2781                 default:
2782                         return _PAGE_SZ8K_4V;
2783                 case 64 * 1024:
2784                         return _PAGE_SZ64K_4V;
2785                 case 512 * 1024:
2786                         return _PAGE_SZ512K_4V;
2787                 case 4 * 1024 * 1024:
2788                         return _PAGE_SZ4MB_4V;
2789                 }
2790         } else {
2791                 switch (sz) {
2792                 case 8 * 1024:
2793                 default:
2794                         return _PAGE_SZ8K_4U;
2795                 case 64 * 1024:
2796                         return _PAGE_SZ64K_4U;
2797                 case 512 * 1024:
2798                         return _PAGE_SZ512K_4U;
2799                 case 4 * 1024 * 1024:
2800                         return _PAGE_SZ4MB_4U;
2801                 }
2802         }
2803 }
2804
2805 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2806 {
2807         pte_t pte;
2808
2809         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2810         pte_val(pte) |= (((unsigned long)space) << 32);
2811         pte_val(pte) |= pte_sz_bits(page_size);
2812
2813         return pte;
2814 }
2815
2816 static unsigned long kern_large_tte(unsigned long paddr)
2817 {
2818         unsigned long val;
2819
2820         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2821                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2822                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2823         if (tlb_type == hypervisor)
2824                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2825                        page_cache4v_flag | _PAGE_P_4V |
2826                        _PAGE_EXEC_4V | _PAGE_W_4V);
2827
2828         return val | paddr;
2829 }
2830
2831 /* If not locked, zap it. */
2832 void __flush_tlb_all(void)
2833 {
2834         unsigned long pstate;
2835         int i;
2836
2837         __asm__ __volatile__("flushw\n\t"
2838                              "rdpr      %%pstate, %0\n\t"
2839                              "wrpr      %0, %1, %%pstate"
2840                              : "=r" (pstate)
2841                              : "i" (PSTATE_IE));
2842         if (tlb_type == hypervisor) {
2843                 sun4v_mmu_demap_all();
2844         } else if (tlb_type == spitfire) {
2845                 for (i = 0; i < 64; i++) {
2846                         /* Spitfire Errata #32 workaround */
2847                         /* NOTE: Always runs on spitfire, so no
2848                          *       cheetah+ page size encodings.
2849                          */
2850                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2851                                              "flush     %%g6"
2852                                              : /* No outputs */
2853                                              : "r" (0),
2854                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2855
2856                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2857                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2858                                                      "membar #Sync"
2859                                                      : /* no outputs */
2860                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2861                                 spitfire_put_dtlb_data(i, 0x0UL);
2862                         }
2863
2864                         /* Spitfire Errata #32 workaround */
2865                         /* NOTE: Always runs on spitfire, so no
2866                          *       cheetah+ page size encodings.
2867                          */
2868                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2869                                              "flush     %%g6"
2870                                              : /* No outputs */
2871                                              : "r" (0),
2872                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2873
2874                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2875                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2876                                                      "membar #Sync"
2877                                                      : /* no outputs */
2878                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2879                                 spitfire_put_itlb_data(i, 0x0UL);
2880                         }
2881                 }
2882         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2883                 cheetah_flush_dtlb_all();
2884                 cheetah_flush_itlb_all();
2885         }
2886         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2887                              : : "r" (pstate));
2888 }
2889
2890 pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
2891 {
2892         struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2893         pte_t *pte = NULL;
2894
2895         if (page)
2896                 pte = (pte_t *) page_address(page);
2897
2898         return pte;
2899 }
2900
2901 pgtable_t pte_alloc_one(struct mm_struct *mm)
2902 {
2903         struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2904         if (!page)
2905                 return NULL;
2906         if (!pgtable_pte_page_ctor(page)) {
2907                 free_unref_page(page);
2908                 return NULL;
2909         }
2910         return (pte_t *) page_address(page);
2911 }
2912
2913 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2914 {
2915         free_page((unsigned long)pte);
2916 }
2917
2918 static void __pte_free(pgtable_t pte)
2919 {
2920         struct page *page = virt_to_page(pte);
2921
2922         pgtable_pte_page_dtor(page);
2923         __free_page(page);
2924 }
2925
2926 void pte_free(struct mm_struct *mm, pgtable_t pte)
2927 {
2928         __pte_free(pte);
2929 }
2930
2931 void pgtable_free(void *table, bool is_page)
2932 {
2933         if (is_page)
2934                 __pte_free(table);
2935         else
2936                 kmem_cache_free(pgtable_cache, table);
2937 }
2938
2939 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2940 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2941                           pmd_t *pmd)
2942 {
2943         unsigned long pte, flags;
2944         struct mm_struct *mm;
2945         pmd_t entry = *pmd;
2946
2947         if (!pmd_large(entry) || !pmd_young(entry))
2948                 return;
2949
2950         pte = pmd_val(entry);
2951
2952         /* Don't insert a non-valid PMD into the TSB, we'll deadlock.  */
2953         if (!(pte & _PAGE_VALID))
2954                 return;
2955
2956         /* We are fabricating 8MB pages using 4MB real hw pages.  */
2957         pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2958
2959         mm = vma->vm_mm;
2960
2961         spin_lock_irqsave(&mm->context.lock, flags);
2962
2963         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2964                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2965                                         addr, pte);
2966
2967         spin_unlock_irqrestore(&mm->context.lock, flags);
2968 }
2969 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2970
2971 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2972 static void context_reload(void *__data)
2973 {
2974         struct mm_struct *mm = __data;
2975
2976         if (mm == current->mm)
2977                 load_secondary_context(mm);
2978 }
2979
2980 void hugetlb_setup(struct pt_regs *regs)
2981 {
2982         struct mm_struct *mm = current->mm;
2983         struct tsb_config *tp;
2984
2985         if (faulthandler_disabled() || !mm) {
2986                 const struct exception_table_entry *entry;
2987
2988                 entry = search_exception_tables(regs->tpc);
2989                 if (entry) {
2990                         regs->tpc = entry->fixup;
2991                         regs->tnpc = regs->tpc + 4;
2992                         return;
2993                 }
2994                 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2995                 die_if_kernel("HugeTSB in atomic", regs);
2996         }
2997
2998         tp = &mm->context.tsb_block[MM_TSB_HUGE];
2999         if (likely(tp->tsb == NULL))
3000                 tsb_grow(mm, MM_TSB_HUGE, 0);
3001
3002         tsb_context_switch(mm);
3003         smp_tsb_sync(mm);
3004
3005         /* On UltraSPARC-III+ and later, configure the second half of
3006          * the Data-TLB for huge pages.
3007          */
3008         if (tlb_type == cheetah_plus) {
3009                 bool need_context_reload = false;
3010                 unsigned long ctx;
3011
3012                 spin_lock_irq(&ctx_alloc_lock);
3013                 ctx = mm->context.sparc64_ctx_val;
3014                 ctx &= ~CTX_PGSZ_MASK;
3015                 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
3016                 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
3017
3018                 if (ctx != mm->context.sparc64_ctx_val) {
3019                         /* When changing the page size fields, we
3020                          * must perform a context flush so that no
3021                          * stale entries match.  This flush must
3022                          * occur with the original context register
3023                          * settings.
3024                          */
3025                         do_flush_tlb_mm(mm);
3026
3027                         /* Reload the context register of all processors
3028                          * also executing in this address space.
3029                          */
3030                         mm->context.sparc64_ctx_val = ctx;
3031                         need_context_reload = true;
3032                 }
3033                 spin_unlock_irq(&ctx_alloc_lock);
3034
3035                 if (need_context_reload)
3036                         on_each_cpu(context_reload, mm, 0);
3037         }
3038 }
3039 #endif
3040
3041 static struct resource code_resource = {
3042         .name   = "Kernel code",
3043         .flags  = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3044 };
3045
3046 static struct resource data_resource = {
3047         .name   = "Kernel data",
3048         .flags  = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3049 };
3050
3051 static struct resource bss_resource = {
3052         .name   = "Kernel bss",
3053         .flags  = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3054 };
3055
3056 static inline resource_size_t compute_kern_paddr(void *addr)
3057 {
3058         return (resource_size_t) (addr - KERNBASE + kern_base);
3059 }
3060
3061 static void __init kernel_lds_init(void)
3062 {
3063         code_resource.start = compute_kern_paddr(_text);
3064         code_resource.end   = compute_kern_paddr(_etext - 1);
3065         data_resource.start = compute_kern_paddr(_etext);
3066         data_resource.end   = compute_kern_paddr(_edata - 1);
3067         bss_resource.start  = compute_kern_paddr(__bss_start);
3068         bss_resource.end    = compute_kern_paddr(_end - 1);
3069 }
3070
3071 static int __init report_memory(void)
3072 {
3073         int i;
3074         struct resource *res;
3075
3076         kernel_lds_init();
3077
3078         for (i = 0; i < pavail_ents; i++) {
3079                 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
3080
3081                 if (!res) {
3082                         pr_warn("Failed to allocate source.\n");
3083                         break;
3084                 }
3085
3086                 res->name = "System RAM";
3087                 res->start = pavail[i].phys_addr;
3088                 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3089                 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
3090
3091                 if (insert_resource(&iomem_resource, res) < 0) {
3092                         pr_warn("Resource insertion failed.\n");
3093                         break;
3094                 }
3095
3096                 insert_resource(res, &code_resource);
3097                 insert_resource(res, &data_resource);
3098                 insert_resource(res, &bss_resource);
3099         }
3100
3101         return 0;
3102 }
3103 arch_initcall(report_memory);
3104
3105 #ifdef CONFIG_SMP
3106 #define do_flush_tlb_kernel_range       smp_flush_tlb_kernel_range
3107 #else
3108 #define do_flush_tlb_kernel_range       __flush_tlb_kernel_range
3109 #endif
3110
3111 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3112 {
3113         if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3114                 if (start < LOW_OBP_ADDRESS) {
3115                         flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3116                         do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3117                 }
3118                 if (end > HI_OBP_ADDRESS) {
3119                         flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3120                         do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3121                 }
3122         } else {
3123                 flush_tsb_kernel_range(start, end);
3124                 do_flush_tlb_kernel_range(start, end);
3125         }
3126 }
3127
3128 void copy_user_highpage(struct page *to, struct page *from,
3129         unsigned long vaddr, struct vm_area_struct *vma)
3130 {
3131         char *vfrom, *vto;
3132
3133         vfrom = kmap_atomic(from);
3134         vto = kmap_atomic(to);
3135         copy_user_page(vto, vfrom, vaddr, to);
3136         kunmap_atomic(vto);
3137         kunmap_atomic(vfrom);
3138
3139         /* If this page has ADI enabled, copy over any ADI tags
3140          * as well
3141          */
3142         if (vma->vm_flags & VM_SPARC_ADI) {
3143                 unsigned long pfrom, pto, i, adi_tag;
3144
3145                 pfrom = page_to_phys(from);
3146                 pto = page_to_phys(to);
3147
3148                 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3149                         asm volatile("ldxa [%1] %2, %0\n\t"
3150                                         : "=r" (adi_tag)
3151                                         :  "r" (i), "i" (ASI_MCD_REAL));
3152                         asm volatile("stxa %0, [%1] %2\n\t"
3153                                         :
3154                                         : "r" (adi_tag), "r" (pto),
3155                                           "i" (ASI_MCD_REAL));
3156                         pto += adi_blksize();
3157                 }
3158                 asm volatile("membar #Sync\n\t");
3159         }
3160 }
3161 EXPORT_SYMBOL(copy_user_highpage);
3162
3163 void copy_highpage(struct page *to, struct page *from)
3164 {
3165         char *vfrom, *vto;
3166
3167         vfrom = kmap_atomic(from);
3168         vto = kmap_atomic(to);
3169         copy_page(vto, vfrom);
3170         kunmap_atomic(vto);
3171         kunmap_atomic(vfrom);
3172
3173         /* If this platform is ADI enabled, copy any ADI tags
3174          * as well
3175          */
3176         if (adi_capable()) {
3177                 unsigned long pfrom, pto, i, adi_tag;
3178
3179                 pfrom = page_to_phys(from);
3180                 pto = page_to_phys(to);
3181
3182                 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3183                         asm volatile("ldxa [%1] %2, %0\n\t"
3184                                         : "=r" (adi_tag)
3185                                         :  "r" (i), "i" (ASI_MCD_REAL));
3186                         asm volatile("stxa %0, [%1] %2\n\t"
3187                                         :
3188                                         : "r" (adi_tag), "r" (pto),
3189                                           "i" (ASI_MCD_REAL));
3190                         pto += adi_blksize();
3191                 }
3192                 asm volatile("membar #Sync\n\t");
3193         }
3194 }
3195 EXPORT_SYMBOL(copy_highpage);